A Survey on FPGA-Based Object Detection Using Various YOLO Techniques

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A Survey on FPGA-Based Object Detection Using Various YOLO Techniques 𝐊. 𝐁. 𝐋. 𝐏𝐡𝐚𝐧𝐢 𝐊𝐮𝐦𝐚𝐫 𝟏, 𝐃𝐫. 𝐊. 𝐉𝐡𝐚𝐧𝐬𝐢 𝐑𝐚𝐧𝐢𝟐 1M. Tech, VLSI & EMBEDDED SYSTEM, ECE, UCEK, JNTU Kakinada, Andhra Pradesh, India 2Assistant Professor, Dept. Of ECE, UCEK, JNTU Kakinada, Andhra Pradesh, India.

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Abstract- In recent years, object detection has gained significant attention in computer vision. It has uses in areas like autonomous vehicle navigation, pedestrian detection, surveillance systems, and IoT monitoring.

Many studies have aimed to improve the speed and accuracy of object detection systems to meet real-time needs. The latest technique, You Only Look Once (YOLO), takes a fresh approach by treating object detection as a regression problem. YOLOv8, the newest version, allows for the simultaneous prediction of multiple objects in an image with a single pass, achieving both high accuracy and fast inference. This paper surveys FPGA-based object detection methods that use YOLO and focuses on improving the efficiency of current systems for embedded environments.

It reviews various modifications to the YOLO framework, including quantization strategies (binary, multi-bit, fixed-point), hardware optimizations like pipelining, and Verilogbased FPGA implementations, analyzing their trade-offs in accuracy, throughput, and power consumption.

networks, YOLO achieves real-time performance on both CPUs and GPUs. This makes it a standard for applications that need quick inference [1].

The latest iteration, YOLOv8, released by Ultralytics in 2023, introduces significant architectural advancements that enhance its performance on standard benchmarks like COCO and PASCAL VOC. YOLOv8 incorporates an improved CSPDarknet backbone with C2f modules for efficient feature extraction, a PANet-inspired neck for robust multi-scale feature fusion, and a decoupled, anchor-free detection head that simplifies the prediction process while improving inference speed. These enhancements enable YOLOv8 to achieve state-of-the-art mean Average Precision (mAP) and fast processing, making it ideal for real-time applications. However, deploying such a computationally intensive model on resource-constrained edge devices, such as those used in drones, mobile robots, or IoT nodes, poses significant challenges. The deep layers and multi-scale processing of YOLOv8 demand substantial computational resources, which are often unavailable on edge platforms with limited memory, power budgets, and processing capabilities, necessitating specialized hardware solutions to maintain performance in embedded environments [2].

Keywords- Object Detection, YOLO, Binary Neural Networks (BNN), Hardware Acceleration, Embedded Vision.

1. Introduction

Field-Programmable Gate Arrays (FPGAs) offer a promising platform for deploying YOLOv8 in such resource-constrained settings due to their low power consumption and reconfigurable nature. Unlike GPUs, which benefit from high-bandwidth memory and massive parallelism, FPGAs have limited resources, including Look-Up Tables (LUTs), Block RAMs (BRAMs), and Digital Signal Processing (DSP) blocks, requiring careful optimization to handle YOLOv8’s complex operations. Translating the model’s floating-pointintensive computations into FPGA-compatible designs involves transforming layers such as convolution, batch normalization, activation functions, pooling, and fully connected layers into efficient hardware modules.

Hardware description languages like Verilog are employed to design these digital logic circuits, enabling precise control over dataflow, timing, and resource allocation. However, achieving real-time performance (typically 30+ frames per second) while minimizing power consumption and external memory access remains a significant challenge, as FPGA designs must

Real-time object detection has become essential in modern computer vision. It supports technologies like autonomous vehicles, smart surveillance systems, advanced robotics, and vision applications in the Internet of Things (IoT). These systems require the quick classification and localization of multiple objects in images or video streams. They need both high accuracy and low latency to work well in changing environments.

Traditional computer vision methods, which used handcrafted features, have largely been replaced by deep learning models because of their better ability to adapt to different scenes and datasets. low latency to work well in changing environments. Traditional computer vision methods, which used hand-crafted features, have largely been replaced by deep learning models because of their better ability to adapt to different scenes and datasets.

Among these models, the You Only Look Once (YOLO) family is widely used for its unified detection approach. It treats object detection as a regression problem. By removing the need for complex region proposal

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balance accuracy, utilization [3].

inference

speed,

and

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resource

robust, and efficient vision systems that can transform real-world applications [6].

2. Techniques in Focus

To address these challenges, several optimization techniques are critical for enabling real-time YOLOv8 inference on FPGAs. Quantization is a primary method, reducing the precision of weights and activations from 32-bit floating-point to lower-bit formats like 8-bit integers (INT8) or binary values (+1, -1), significantly decreasing memory usage and computational complexity. Binary Neural Networks (BNNs), inspired by frameworks like XNOR-Net, replace multiply-accumulate operations with XNOR and bitcount operations, which are highly efficient on FPGA logic due to their compatibility with bitwise operations. Architectural optimizations involve designing processing elements (PEs), modular units tailored for tasks like convolution or pooling, arranged in parallel pipelines to maximize data throughput. Techniques such as loop unrolling, memory tiling, and streaming interfaces ensure continuous data flow without pipeline stalls, enhancing latency and throughput. These optimizations are crucial for aligning YOLOv8’s computational demands with FPGA constraints [4].

2.1 Deep Learning-Based Detection Object detection, a fundamental task in computer vision, involves identifying and localizing multiple objects within images or video frames, critical for applications like autonomous driving and surveillance. Deep learning, particularly Convolutional Neural Networks (CNNs), has revolutionized this field by learning hierarchical feature representations from large-scale datasets such as COCO and PASCAL VOC. Unlike traditional algorithms relying on hand-crafted features, CNNs perform end-to-end classification and bounding box regression, offering superior generalization across diverse scenes. YOLOv8, a one-stage detector, processes images in a single forward pass, predicting class probabilities and bounding box coordinates simultaneously. Its architecture comprises a CSPDarknet backbone with C2f modules for efficient feature extraction, a PANet-inspired neck for multi-scale feature fusion, and an anchor-free detection head, enabling fast inference suitable for real-time embedded applications. However, its computational complexity necessitates optimization for deployment on resourceconstrained platforms like FPGAs.

Further hardware optimization strategies focus on efficient memory management and data reuse to minimize bottlenecks. Control logic is implemented to synchronize data flow and handle memory interfaces, ensuring seamless operation across layers. Memoryefficient buffer management strategies store intermediate feature maps in on-chip BRAM, reducing dependency on external DRAM, which introduces latency and increases power consumption. Reuse strategies, such as weight sharing and partial sum accumulation, minimize redundant computations, further optimizing resource usage. These techniques collectively enable YOLOv8 to achieve real-time performance on FPGAs, supporting applications where low latency and power efficiency are paramount, such as autonomous navigation and IoT-based monitoring [5].

2.2 Hardware Optimization Techniques Optimizing YOLOv8 for FPGA deployment requires techniques that balance computational efficiency with resource constraints. Quantization reduces the bit-width of weights and activations to 8-bit, 4-bit, or binary formats, significantly lowering memory and computation demands. Binary Neural Networks (BNNs) replace multiply-accumulate operations with XNOR and bit count operations, leveraging FPGA’s logic efficiency. Feature Pyramid Networks (FPNs) in YOLOv8’s neck combines high-resolution spatial details with deep semantic features, enhancing detection of objects at various scales while optimizing memory usage through lowerresolution processing. Anchor-free detection simplifies the training pipeline and hardware design by directly regressing bounding box centres, widths, and heights, reducing decoding complexity. Data reuse strategies, such as weight sharing and memory tiling, minimize memory bandwidth bottlenecks, ensuring efficient computation within FPGA’s limited resources, critical for achieving real-time performance in embedded systems.

The convergence of deep learning and hardware design is reshaping embedded intelligence, enabling advanced models like YOLOv8 to operate effectively on resourcelimited platforms. By implementing YOLOv8 in Verilog on FPGAs, researchers can address both the computational intensity of deep learning and the constraints of embedded systems, achieving an effective balance between accuracy and efficiency. This hardware-aware approach is critical for real-time intelligent systems in environments like drones, mobile robots, and IoT edge devices, where stringent power, size, and latency requirements must be met. The fusion of sophisticated object detection algorithms with hardware-optimized designs not only brings practical AI to resourceconstrained settings but also paves the way for scalable,

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2.3 FPGA Implementation Implementing YOLOv8 on FPGAs involves modeling its layers as register-transfer level (RTL) circuits using Verilog, a hardware description language. Convolution layers are designed as parallel processing elements

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(PEs), with XNOR-based operations for BNNs to enhance efficiency. Pooling, activation, and detection heads are implemented as modular units, with pipeline registers ensuring continuous dataflow to minimize latency. Onchip BRAM stores weights and feature maps, reducing reliance on external DRAM, which increases power consumption and latency. FPGA-centric optimizations, such as loop unrolling, parallel execution, and clock gating, maximize throughput while minimizing power usage. Systolic arrays and streaming architectures leverage FPGA’s reconfigurable logic, aligning YOLOv8’s computational requirements with hardware constraints.

These techniques enable real-time performance, making FPGA-based YOLOv8 implementations suitable for embedded vision applications in robotics, IoT, and autonomous systems.

it provides insights for FPGA-based object detection systems.

Saidani et al. (2024) [5] implement YOLOv5 on a Xilinx Zynq FPGA using 8-bit quantization and Verilog-coded modules, achieving 68.7% mAP and 45 FPS. Leveraging YOLOv5’s CSPDarknet backbone, the system demonstrates robust performance, but its dependence on external DRAM and higher-precision quantization increases power and resource demands compared to binary approaches.

Yang et al. (2023) [6] propose a Verilog-based FPGA acceleration core for deep learning models, supporting multi-bit quantization (8–16 bits). While offering flexibility for parallel processing, it lacks YOLO-specific optimizations, reducing its efficiency for advanced models like YOLOv8, making it a general-purpose reference for FPGA designs.

3. Literature Survey Lee et al. (2023) [1] propose a real-time object detection processor using a Binary Neural Network (BNN) with XNOR-based convolutions, implemented in Verilog on a Xilinx Zynq UltraScale+ FPGA. The design features a variable-precision computing unit (1-bit and 8-bit) and a DenseToRes layer for enhanced feature reuse, achieving a high throughput of 64.51 FPS with low resource usage.

However, its accuracy is limited to 64.92% mAP due to binarization, and high BRAM usage (84.76%) restricts scalability on smaller FPGAs, making it a valuable reference for binary quantization in Verilog-based designs.

Umuroglu et al. (2017) [7] introduce FINN, a Verilogbased framework for deploying BNNs like Tiny-YOLO on FPGAs. It supports custom bit-widths and streaming dataflow, achieving low latency. However, its focus on smaller networks limits scalability for complex architectures like YOLOv8, suitable for lightweight embedded applications.

Wang et al. (2022) [8] present YOLOv7, featuring E-ELAN blocks and re-parameterization for hardware efficiency.

Its modular structure suits Verilog-based FPGA deployment, but its GPU-oriented design requires significant adaptation for low-resource platforms, posing challenges for direct implementation.

Ultralytics (2023) [2] introduces YOLOv8, an anchor-free model with a C2f-based CSPDarknet backbone, a PANetinspired neck, and a decoupled detection head. Its support for quantization and ONNX export facilitates FPGA deployment, simplifying Verilog module design.

However, the complex C2f backbone poses challenges for low-resource FPGAs, requiring careful optimization to achieve real-time performance in embedded applications.

Zhang et al. (2021) [9] propose a mixed-precision YOLO model (2-bit, 4-bit, 8-bit) with Verilog-coded multiplyaccumulate (MAC) units. Dynamic precision control improves accuracy over binary models but increases control logic complexity, challenging low-resource FPGA designs, informing mixed-precision strategies.

Chen et al. (2020) [10] implement YOLO-Tiny on an Artix-7 FPGA using Verilog, with fixed-point arithmetic and shared BRAMs. The design achieves real-time performance with low power but sacrifices accuracy due to its simplified model, offering lessons for resourceconstrained deployments.

Rastegari et al. (2016) [3] present XNOR-Net, a pioneering BNN framework that replaces floating-point convolutions with XNOR and bitcount operations, reducing memory and computation demands. This approach is highly suitable for Verilog-based FPGA implementations, but its accuracy limitations make it less applicable to complex models like YOLOv8, serving as a foundational reference for binarization techniques.

Gao et al. (2021) [11] develop a power-aware CNN accelerator for a YOLOv3-inspired pipeline, using Verilog and reconfigurable arrays. It minimizes memory access via temporal locality but has a complex design, less suited for low-cost FPGAs, providing insights for poweraware optimization.

Zhou et al. (2022) [4] develop a YOLOv4-based detector on a Zynq UltraScale+ FPGA using Verilog and quantization-aware training (QAT). The design employs fixed-point arithmetic, dual-clock domains, and DMAcontrolled buffering, achieving over 30 FPS with low power consumption. Its reliance on external DRAM and complex tuning requirements increase design effort, but

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Iandola et al. (2016) [12] introduce SqueezeNet, a compact CNN with principles applicable to YOLO

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variants. Its low parameter count suits Verilog-based FPGA deployment, but its classification focus limits direct applicability to detection tasks, offering a reference for lightweight models.

Zhang et al. (2021) [14] present structured pruning for CNNs, implemented in Verilog with conditional logic to skip zero-valued filters. This reduces computation for YOLO models but requires careful pruning to maintain accuracy, offering a potential optimization strategy.

Qiu et al. (2019) [13] propose a tile-based CNN accelerator in Verilog, supporting weight sharing and streaming for YOLO-like models. Its scalability is strong, but it lacks specific optimizations for YOLOv8’s complex architecture, serving as a general reference for FPGA designs.

Liu et al. (2022) [15] develop a quantization-aware YOLOv5 model (INT4/INT8) for Verilog-based FPGA deployment. It preserves accuracy with low precision but requires calibration and retraining, increasing design complexity, informing quantization strategies for advanced models.

Table 1 - Analysis Table S.No

Author

Object Model / Technique

Limitations

High throughput (64.51 FPS), low resources, Verilog-friendly XNOR operations

Lower mAP (64.92%), high BRAM usage (84.76%)

1

Lee et al. [1]

XNOR-based (YOLO-like)

2

Ultralytics [2]

YOLOv8

Anchor-free, ONNX exportable, quantization support, simplified detection

Complex C2f backbone challenges Verilog mapping

3

Rastegari al. [3]

XNOR-Net

Binary operations reduce memory/computation, ideal for Verilog

Lower accuracy detection tasks

4

Zhou et al. [4]

YOLOv4 on Zynq FPGA

Real-time (30+ FPS), fixed-point QAT, low power via DMA

External memory complex tuning

5

Saidani et al.

[5]

YOLOv5 on Zynq FPGA

Good mAP (68.7%), high throughput (45 FPS), robust CSPDarknet

External DRAM, higher resource use with 8-bit quantization

6

Yang et al. [6]

DNN Accelerator

Supports multi-bit processing

Not YOLO-specific, resource demands

7

Umuroglu et al. [7]

FINN (Tiny-YOLO BNN)

Low latency, supports custom bit-widths, Verilog-based

Limited scalability for complex models like YOLOv8

8

Wang et al.

[8]

YOLOv7

Modular E-ELAN, parameterization

re-

GPU-oriented, needs adaptation for low-resource FPGAs

9

Zhang et al.

[9]

Mixed-Precision YOLO

Better accuracy than binary, dynamic Verilog MAC units

Complex control logic for mixed precision

10

Chen [10]

YOLO-Tiny on Artix-7

Low-cost, pipeline

Lower accuracy due to simplified model

11

Gao et al. [11]

YOLOv3-inspired Accelerator

Power-aware, reconfigurable memory access

12

Iandola et al.

[12]

SqueezeNet

Low parameters, deployment

13

Qiu et al. [13]

Tile-based Accelerator

CNN

Scalable, supports weight sharing, streaming for YOLO models

Lacks optimizations

14

Zhang et al.

[14]

Structured (YOLO)

Pruning

Reduces computation via Verilog conditional logic

Needs careful pruning to avoid accuracy loss

15

Liu et al. [15]

Quantization-Aware YOLOv5 (INT4/8)

Preserves mAP with low precision, Verilog compatible

Requires calibration, design complexity

et

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et

al.

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BNN

Positive Aspects

Impact Factor value: 8.315

parallel

hardware-friendly

real-time,

|

quantization,

fixed-point

suits

Verilog

arrays, Verilog

for

complex reliance,

higher

low

Complex design, less suited for low-cost FPGAs

FPGA

Classification-focused, limited for direct detection

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YOLOv8-specific

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increases

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4. Conclusion

[7] Umuroglu, Y., Fraser, N. J., Gambardella, G., Blott, M., Leong, P., Jahre, M., & Vissers, K. (2017). FINN: A framework for fast, scalable binarized neural network inference. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 65–74. DOI: 10.1145/3020078.3021744.

FPGA-based YOLOv8 object detection offers a promising solution for efficient, low-power vision systems in IoT, robotics, and autonomous vehicles. This survey reviews key techniques and 15 works, highlighting trade-offs in accuracy, throughput, and resource utilization. Binary quantization reduces computational complexity but sacrifices accuracy, while advanced models like YOLOv8 demand intricate Verilog designs for FPGA deployment.

Key challenges include managing the complex C2f backbone, minimizing external memory access, and optimizing resource-constrained platforms. Future research should focus on mixed-precision quantization to balance efficiency and accuracy, leverage high-level synthesis (HLS) for automated Verilog module generation, and incorporate dynamic power management techniques like clock gating and adaptive voltage scaling. Advanced feature fusion, such as BiFPN, could enhance multi-scale detection without increasing resource demands, paving the way for scalable, highperformance FPGA-based vision systems.

[8] Wang, C.-Y., Bochkovskiy, A., & Liao, H.-Y. M. (2022).

YOLOv7: Trainable bag-of-freebies sets new state-of-theart for real-time object detectors. arXiv preprint arXiv:2207.02696. https://arxiv.org/abs/2207.02696.

[9] Zhang, Y., Li, J., Wu, F., & Cheng, X. (2021). Mixedprecision quantization for FPGA-based YOLO object detection. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(10), 3456–3460.

DOI: 10.1109/TCSII.2021.3087890.

[10] Chen, T., Yang, S., Li, Q., & Zhou, Z. (2020). Real-time YOLO-Tiny implementation on Artix-7 FPGA for embedded vision. IEEE International Conference on ASIC (ASICON), 1–4.

DOI: 10.1109/ASICON49860.2020.9348492.

References

[11] Gao, M., Liu, Y., Zhang, J., & Wang, Q. (2021). Poweraware CNN accelerator for YOLOv3-based object detection on FPGAs. IEEE International Symposium on Circuits and Systems (ISCAS), 1–5.

DOI: 10.1109/ISCAS51556.2021.9401123.

[1] Lee, W., Lee, J., Lee, K., Shin, J., & Yoo, H. (2023). A real-time object detection processor with XNOR-based variable-precision computing unit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31(6), 749– 761. DOI: 10.1109/TVLSI.2023.3264512.

[12] Iandola, F. N., Han, S., Moskewicz, M. W., Ashraf, K., Dally, W. J., & Keutzer, K. (2016). SqueezeNet: AlexNetlevel accuracy with 50x fewer parameters and <0.5MB model size. arXiv preprint arXiv:1602.07360. https://arxiv.org/abs/1602.07360.

[2] Ultralytics. (2023). YOLOv8. GitHub Repository. https://github.com/ultralytics/ultralytics.

[3] Rastegari, M., Ordonez, V., Redmon, J., & Farhadi, A. (2016). XNOR-Net: ImageNet classification using binary convolutional neural networks. European Conference on Computer Vision (ECCV), 525–542. DOI: 10.1007/978-3319-46493-0_32.

[13] Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., Wang, Y., & Yang, H. (2019). Going deeper with embedded FPGA platform for convolutional neural network. Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 26–35. DOI: 10.1145/2847263.2847265.

[4] Zhou, Y., Zhang, L., & Chen, X. (2022). YOLOv4-based object detection system targeting Zynq UltraScale+ MPSoC platforms. IEEE International Conference on FieldProgrammable Technology (FPT), 1–8.

DOI: 10.1109/FPT55805.2022.00012.

[14] Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2021). Optimizing FPGA-based accelerator design for deep convolutional neural networks with structured pruning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(3), 456–469. DOI: 10.1109/TCAD.2020.3001256.

[5] Saidani, T., Ghodhbani, R., Alhomoud, A., Alshammari, A., Zayani, H., & Ben Ammar, M. (2024). Hardware acceleration for object detection using YOLOv5 deep learning algorithm on Xilinx Zynq FPGA platform.

Engineering, Technology & Applied Science Research, 14(1), 13066–13071. DOI: 10.48084/etasr.6761.

[15] Liu, Z., Shen, Z., Savvides, M., & Cheng, K.-T. (2022).

Quantization-aware YOLOv5 deployment on FPGAs for real-time object detection. IEEE International Conference on Computer Vision Workshops (ICCVW), 123–130. DOI: 10.1109/ICCVW56347.2022.00023.

[6] Yang, X., Zhuang, C., Feng, W., Yang, Z., & Wang, Q. (2023). FPGA implementation of a deep learning acceleration core architecture for image target detection.

Applied Sciences, 13(7), 4144.

DOI: 10.3390/app13074144.

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