Page 1




Solutions Driven by Innovative Applications

page 9

Production Testing of MEMS & Sensors

page 16


UP FRONT Most of us have seen the headlines about the economy and technology companies “rightsizing”.

FPGA - Persistence is about to pay off. A seachange in direction is bursting onto the scene. 3


Last year was the 75th anniversary of the invention of the transistor – the cornerstone of all modern electronics. 4

21 6


A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 26, Number 4
CATCHING UP WITH Roger Grace, Founder and President of Roger Grace Associates, joined the MEPTEC Advisory Board in 2022.

Publisher MEPTEC

Editor Ira Feldman

Sales Manager Gina Edwards

MEPTEC Executive Director

Ira Feldman

MEPTEC Advisory Board

Board Members

Dave Armstrong Advantest

Ivor Barber AMD

Zoë Conroy Cisco

Jeff Demmin Keysight Technologies

Abram Detofsky Intel

Neal Edwards AMD

Jaspreet Gandhi Meta

Roger Grace Roger Grace Associates

Ravi Mahajan Intel

Emeritus Advisors

Seth Alavi Sunsil

Anna Gualtieri Elle Technology

Phil Marcoux PPM Associates

Mary Olsson

Herb Reiter eda 2 asic Consulting, Inc., Retired

In Memoriam

Joel Camarda

Ron Jones


Lihong Cao ASE, Inc.

Ira Feldman Feldman Engineering Corp.

Mark Gerber ASE, Inc.

Roger H. Grace Roger Grace Associates

Vikas Gupta ASE, Inc.

Martin Hart TopLine Corporation

Patricia MacLeod ASE, Inc.

Vineet Pancholi Amkor Technology, Inc.

MEPTEC Report Vol. 26, No. 4. Published quarterly by MEPTEC, PO Box 1053, Los Altos, CA 94023. Copyright 2022 by MEPTEC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493.


Welcome 2023

Mixed Signals – Headlines vs. Reality

Most of have seen the headlines about the economy and technology companies “rightsizing”. At the same time, I’ve seen and felt the buzz of activity and energy at conferences and tradeshows. I was most recently at a packed SEMICON Korea and had many productive meetings. This was the polar opposite of a very anemic SEMICON West last July. Most of the semiconductor people I talked with are very busy with lots of exciting business activity. However, in the continued “mixed bag” analysts are forecasting particular hot sectors with reasonable overall semiconductor growth closer to longer term run rates versus the exceptionally outsized “make-up” growth of the past year or so. Given this, I’ll remain optimistic and hope the headlines don’t become a self-fulfilling prophesy if too many people ignore the real data.

Our next quarterly event will be Not Just Chips on the mornings of April 4-6, 2023. At this new virtual event, we will be taking a closer look at the design, packaging, and testing of devices that include more than traditional silicon dies. We will have presentations on Inter & Intra Package Interconnect and Assembly; Photonics and Optical packaging; and MEMS/Sensor Packaging. See the agenda and register now at to not miss this informative event.

In late Q2 we are planning our next stop on the Road to Chiplets covering “Ecosystem Collaboration” as an in-person event in Silicon Valley. Please look for our Call for Presentations and additional details in March. If you are interested in presenting or joining the technical program committee (TPC), please contact me. And if your company is interested in sponsoring or exhibiting at this event, please contact Rosina Haberl (

Lastly, a little business: MEPTEC is a member and corporate sponsor supported organization. If you have not already joined or renewed for this year, please do so now. And if your company is interested in sponsoring our programs, please let us know as corporate sponsorships allow us to provide the virtual events free of charge. For assistance with membership or sponsorships please contact Rosina Haberl (

I look forward to hearing your suggestions and feedback as to how MEPTEC can best serve you. Please don’t be shy!

Stay safe and healthy!

Ira Feldman

Executive Director, MEPTEC

+1 650-472-1192

WINTER 2022 MEPTEC REPORT | 3 The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council PO Box 1053, Los Altos, CA 94023 +1 (415) 287-3276 Email:

FPGA - Persistence is About to Pay Off

FOR QUITE SOME TIME WE HAVE been raising an ongoing Call to Action to the semiconductor and defense industries concerning a potential threat of a critical shortage of ruggedized Field Programmable Gate Array (FPGA) components with solder columns. These devices form a vital part of many defensive and aerospace essential systems. Without these mission-critical FPGA devices, warfighters might not fly, and many defense guidance systems might not operate. The threat has been hiding in plain sight and visible to engineers and civilian managers in charge. For well over 20 years, the industry has been dependent on just one monopoly subcontractor who is qualified to perform a specific type of assembly service needed to attach copper-wrapped solder columns to FPGA as the final critical step in their manufacture. It seems crazy.

Stating the Problem

The nation’s top 10 makers of ruggedized FPGA devices have been forced to use this single subcontractor designated on the Defense Logistics Agency’s (DLA) Qualified Manufacturer List (QML-38535) as a provider of copperwrapped solder column attachment services for the entire FPGA industry. Such a monopoly is outright dangerous. It is well understood that any supply chain dependent upon a single supplier is inherently vulnerable. It is, in a word, scary, particularly when we consider the current and accelerating military threats building against the United States.

We’ve been pursing action to develop a solution to resolve this. Over 25 articles published in this MEPTEC Report as well as in various other publications, have sounded the alarm, described the problem, and proposed viable solutions. We hoped for responses from individuals within the industry, and yet, like the mountaineer calling out into a chasm,

we’ve heard only the echoes of our own voice. We wondered if indeed we were heard, or even noticed; but now we can say, happily, that our call and our concerns have finally been heard after all.

Risk Assessment

The problem and its ramifications, should a real FPGA shortage ensue, cannot be emphasized strongly enough. But take heart; the defense and aerospace

Change is a Coming

A sea-change in direction is bursting onto the scene. Apparently, global instability, the COVID pandemic, and the demonstrated fragility of the global supply chain has moved decision makers to be more proactive in responding to threats. At a recent electronics manufacturing conference on the U.S. west coast, there was much talk flying about, all echoing common themes, such as on-shoring is coming back to U.S. manufacturing. Supply chain uncertainties make it more advisable to build things at home once again, alleviating uncertainties in trusting people who may not be your friends to make sensitive military parts. Advances in robotics and automation, meanwhile, have boosted precision manufacturing speed, volume, and capability to compensate for the lack of skilled assembly personnel that followed the pandemic. Production of defense-grade FPGA and ASIC devices with solder columns occupies a fragile market. America will soon broaden its supply base to include multiple suppliers who are capable of making and attaching solder columns for aerospace and defense grade FPGA components.


Happily, the Department of Defense DLA has resumed field audits for certifying Column Grid Array column attachment providers. Certifications of vendors for column attachment services are imminently on the way.

industry has a solution, and is moving forward to qualify multiple vendors for critical processes including column attachment services. This remedy requires a relatively low investment by FPGA device makers. Fabrication of copper-wrapped solder columns is not a simple matter and requires correct knowhow, manufacturing equipment and proficient operator skills to achieve.

This is very good news; the decades long monopoly streak of the single source subcontractor, one who provides 90% of America’s solder column attachment services, will fade into the sunset. In upcoming months, the industry will soon have more choices for column attachment services.

We will all be safer, and so will our Nation’s defense capability. ◆

The nation’s top 10 makers of ruggedized FPGA devices have been forced to use a single subcontractor designated on the Defense Logistics Agency’s (DLA) Qualified Manufacturer List (QML-38535) as a provider of copperwrapped solder column attachment services for the entire FPGA industry.

New Room Temperature Curable Gap Filler from Henkel is Optimized for Electronic Assembly Applications


As modern vehicles become increasingly dependent on sophisticated electronics, manufacturers require reliable solutions, while ensuring efficient and cost-effective assembly of key automotive electronics components such as control modules. As an expert partner to automotive OEMs and component manufacturers, Henkel Adhesive Technologies is expanding its portfolio of advanced materials to meet this demand with the launch of its new thermal liquid gap filler that has been optimized for a wide range of electronic assembly applications.

Bergquist gap filler TGF 2900LVO is a silicone-based, 2-component room temperature curable gap filler suitable for use in a wide range of electronic assembly applications.

“Representing a new generation of Henkel gap fillers, TGF 2900LVO demonstrates superior performance that makes it an outstanding choice for automotive control modules. These designs are ever evolving and find a versatile solution in the possibility of ultra-thin bondline thickness of TGF 2900LVO, lowering

the overall thermal resistivity of the system,” said Bart Van Eeghem, Business Development Manager at Henkel. “Thereby this new Henkel product meets exactly the needs of our customers. The versatility and longer working time allow to reduce the complexity of the supply chain and facilitating processability and flexibility.”

To learn more visit

SEMICON West Makes Two Big Moves – Shifts to October in 2024, Begins Annual Rotation with Phoenix in 2025

A FIXTURE IN THE SAN FRANCISCO Bay Area for more than 50 years, SEMICON West is moving to Phoenix for a five-year annual rotation starting in 2025 and shifting from its long-standing July event dates to October beginning in 2024, SEMI has announced. The event, North America’s premier microelectronics exhibition and conference, will be held again in Arizona in 2027 and 2029, with all three appearances at the Phoenix Convention Center.

“SEMI is excited to bring SEMICON West to Phoenix, a booming semiconductor manufacturing hub, in October 2025,” said Joe Stockunas, president of SEMI Americas, host of the exhibition and conference. “Greater Phoenix is home to more than 75 semiconductor companies including SEMI members EMD Electronics, Intel and Taiwan Semiconductor Manufacturing Company (TSMC), and the sector employs more than 100,000 with more jobs on the way. SEMI thanks the Greater Phoenix Economic Council (GPEC), Arizona Commerce Authority (ACA), and the city of Phoenix for their tremendous support as we make this important move,” Stockunas added.

In November, the state of Arizona

announced a $100 million investment in semiconductor industry research and development under the U.S. CHIPS and Science Act to consolidate the state’s competitive position. And in December, TSMC announced plans to triple its fab investments in Phoenix to $40 billion, facilities that are expected to create 13,000 high-tech jobs, and produce leading-edge 3-nanometer chips at the new factory by 2026.

Greater Phoenix is also a rich source of new talent for local semiconductor companies. The Arizona State University engineering program is the largest in the United States, with more than 30,000 students, including 7,000 focused on microelectronics-related fields. The Maricopa Community Colleges have also made significant investments in quick-start programs to bring even more technicians online.

Phoenix will first host SEMICON West Oct. 7-9, 2025. The event will continue to be held at the Moscone Center in San Francisco on the alternating years and over the long term. The event changes do not affect this year’s SEMICON West, scheduled for July 11-13 at the Moscone Center.

Visit to learn more. ◆



(TI) has said that its board of directors has selected Haviv Ilan to become the company’s next president and chief executive officer (CEO), effective April 1. Ilan, a 24-year veteran of TI, succeeds current CEO and president, Rich Templeton, who will transition out of these roles over the next two months but will remain the company’s chairman. The transition is a well-planned succession that follows Ilan’s promotion to senior vice president in 2014, executive vice president and chief operating officer in 2020 and election to the board of directors in 2021.




announced that Frank D. Yeary has been appointed as the new independent chair of its board of directors. This follows Dr. Omar Ishrak’s decision to step down as chair. Ishrak will remain on Intel’s board as an independent director and continue to serve on the audit and finance committee and corporate governance and nominating committee.

Yeary has served as a director of Intel since 2009. He also is a managing member at Darwin Capital Advisors. Yeary also serves on the board of Mobileye, PayPal Holdings, among others. In the past Yeary served as vice chancellor of UC Berkeley and spent 25 years in the finance industry. ◆



Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology, but occasional crosstalk diversions may deliver a message closer to home.

Curves & Waves

Last year was the 75th anniversary of the invention of the transistor. The Institute of Electrical and Electronics Engineers (IEEE) and other organizations celebrated this milestone with retrospectives as well as looking ahead. There is plenty to celebrate as these devices are the cornerstone of all modern electronics.

Transistors are the “silicon” that created Silicon Valley as the center for technology innovation that impacts all of our daily lives. In 1955, William Shockley built the Shockley Semiconductor Laboratory (less than a mile from our home) to pursue his version of the transistor. However, the primary research team he assembled did not take kindly to his interference. The “Traitorous Eight,” as they later become known, left to form Fairchild Semiconductor from which almost all other technology companies claim lineage.

As incredible as the transistor technology and story may be, many of these articles neglected to place the transistor into the historical context of technology curves and innovation waves. For this, we need to discuss Moore, Dennard, and go even further back to Kondratiev.

Gordon Moore in his seminal 1965 article “Cramming more circuits onto integrated circuits” (Electronics, Volume 38, Number 8) said “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (…). Certainly, over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the

number of components per integrated circuit for minimum cost will be 65,000.” (Emphasis added.) In 1975, Moore revised his forecast that the doubling rate would slow down to approximately every two years after 1980. These predictions have become known as “Moore’s Law”

Many people misquote or misinterpret Moore’s Law to say that transistors will shrink in size every two years or that the number of transistors in each integrated circuit will double every two years. They also confuse it with Dennard Scaling (discussed below). Moore’s Law is not about the number, size, or density of the transistors themselves but the cost of building integrated circuits (devices) with them.

I.e. the economics of fabricating and connecting them in a single device. In the last decade there has been a debate if Moore’s Law was dead as the largest semiconductor manufacturers continued to push ahead to even smaller process nodes. It is clear that the cost per transistor (component) has been increasing for several years for the advanced process nodes – therefore it is unequivocal that Moore’s Law no longer holds strictly speaking.

Even though Moore’s Law no longer governs the economics of fabricating transistors (integrated circuits), its continued importance cannot be underestimated in at least two ways. The first and most important thing it did (even when misunderstood) was to create the customer perception that electronic devices would either double in speed/performance/capacity or decrease in price by one-half every two years. Or an equivalent combination of performance improvement at lower cost. This has created never satisfied market place expectations requiring product companies to continuously improve their offerings.

Luckily, technology companies were able to continue to deliver increased performance as a benefit of Dennard scaling by pushing ahead with the development of advanced process nodes (smaller transistor sizes). In 1974, Robert H. Dennard coauthored a paper that described transistors as get smaller the power density staying constant. Which results in increased speed and lower power consumption of the transistor as it is made smaller (i.e. fabricated with an advanced process node). Unfortunately starting around 2006, performance no longer increased in the same ratio to transistor size reduction as historical Dennard scaling. Hence the performance to transistor size “curve” shifted, reducing

some of the benefits of smaller transistors.

So how did product companies continue to meet the expectations set by Moore’s Law as the economics of smaller transistors decreased and performance increases declined? By innovating! Key innovations were made in both transistor structure and packaging technology. The original single transistor of Shockley’s team was a pointcontact structure. This quickly changed to planar transistors built on wafers in volume in the 1950s and 60s. In the 2010s fin field-effect transistors (FinFET), with higher speed and higher current densities due to the structure, become the dominate design at the leading edge of 14 nm fabrication processes and below. And most recently, gate-all-around FET (GAAFET) structures are on company roadmaps for 5 and 3 nm devices that may ship as early as this year. And in December 2021, IBM and Samsung announced a new Vertical-Transport Field-Effect Transistor (VTFET) under development providing even greater transistor per area density. In addition to changing the shape of the transistor to reduce area and/or increase performance, some companies have stacked multiple transistors to pack more functionality in a given area. Of course, this type of stacking comes at the cost of processing additional wafer layers.

Ultimately, all of the transistor-based approaches will reach a limit beyond which the size of the transistor cannot be reduced. Where exactly that limit may be is unknown. Current research by Tsinghua University (China) has demonstrated a transistor with a 0.34 nm gate – the size of a single carbon atom. Many think that single-atom monolayers will be the end of the game but the industry has been surprised before.

The other key innovation is the More than Moore approach to building systems, as first described by the International Technology Roadmap for Semiconductors (ITRS) in the early 2000’s and now covered by the Heterogeneous Integration Roadmap (HIR). This includes Heterogeneous Integration (Chiplets, etc.) and other advanced packaging (2.5D, 3D, etc.) that I have written about previously. My money is on seeing a lot more innovation in these areas as the development costs are lower and the time to market is significantly faster than new transistors at ever shrinking process nodes.

The second biggest impact of Moore’s Law? It created a roadmap for


the entire semiconductor industry and its supply chain of equipment, technology, and materials providers to follow. It has set the cadence of innovation for this entire ecosystem for well over fifty years. Why did companies faithfully execute against the expectations set by Moore’s Law with greater compliance than any other industry standard or roadmap, or even government regulation? Simple: they were motivated by the economics! Now the challenge is to find other metrics or roadmaps that the industry will be selfmotivated to coalesce around and support. As product managers and technology innovators, it is important to understand the “curves” like Moore’s Law and Dennard scaling that define both the economics and feasibility of the technology foundation of one’s products. At the same time

waves are important too! In the 1920’s, Russian economist Nikolai Kondratiev developed the concept of business cycle theory the basic conclusions of which are now generally discredited. However, in his work he described transformative waves of innovative technology that lead to periods of wealth and stability. Others contemporaries of Kondratiev have also described similar ideas of “long waves” of technology evolution and prosperity.

A recent version of Kondratiev waves is illustrated below by Richard Almgren and Dmitry Skobelev in the Theoretical Background section of their article “Evolution of Technology and Technology Governance” (Journal of Open Innovation: Technology, Market, and Complexity. 28 March 2020).

The relevance of these technologi-

cal waves to the semiconductor industy? Transistors, and their associated semiconductor innovation, are the enabling technology of the TV, Aviation, & Computers (4th wave) and Biotech & Information Technology (5th wave). Without transistors or a replacement technology, neither wave would have existed. And looking ahead, presuming the general consensus is correct that Sustainability is the 6th wave, it is important to understand where technology innovations will occur and the technology required to support the wave in general to know where the business opportunities and threats exist.

Is your organization too busy or too focused on delivering your existing products and services to worry about curves and waves? Are you running as fast as possible to get from point A to point B without having time to consider the “big picture”? An outside consultant, with industry expertise, can provide the proper unbiased perspective to identify technology trends and disruptive innovation to inform your strategic planning process and product roadmaps. Of course, if you need to establish or improve the effectiveness of your planning processes and roadmaps they can assist there too.

When you are trying to identify where innovation disruption will occur – it is always best to think about curves and waves!

For more of my thoughts, please see my blog

As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆

1st wave 2nd wave 3rd wave 4th wave 5th wave 6th wave
Figure 1. Technological Waves. Source: Almgren 2020

Don’t Miss Out on the Industry’s Premier Event!

The only event that encompasses the diverse world of integrated systems packaging.

For more information, visit:

Conference Sponsors:

March 5–8, 2023 Mesa, Arizona

NOW IN ITS 24 th YEAR , TestConX has been bringing together electronic test professionals from around the world and connecting them to state-of-the-art solutions.

Join your colleagues for four days of cuttingedge presentations, networking, the latest product exhibits, and Arizona sunshine.


Fan-Out WLP & CSP Chiplets

Additive Manufacturing

Photonics Systems

Quantum and AI Systems

3D & TSV Processing

Heterogeneous Integration

Fine Pitch Flip-Chip

Advanced Substrates

Advanced Wire Bonding

Flexible & Wearable Devices

RF Components

Harsh Environment

Bio/Medical Devices

Thermal/Mech Simulation

Interconnect Reliability

Optical Interconnects


n 41 technical sessions with a total number of 350+ technical papers including:

• 5 interactive sessions including one student session

n 9 special invited sessions

n 16 CEU-approved Professional Development Courses

n Multiple opportunities for networking

n Technology Corner Exhibits, showcasing industry-leading product and service companies from around the world

n Various sponsorship opportunities for your company’s visibility

n ECTC Gala and evening receptions

Register now at

Vertically-integrated Packaging Solutions Driven by Innovative Applications

Editor’s Note: This article is based upon an article originally published in Chip Scale Review (July/August 2022)

THE INCREASE IN TRANSISTOR density continues to challenge foundry companies and integrated device manufacturers (IDM) companies. This is driven by the need for improved performance and higher fab yields, which have led companies to investigate heterogeneously integrated (HI) advanced packaging solutions. Advanced silicon node yield attainment is a key driver for looking at ways to approach intellectual property (IP) block integration and has opened up new creativity on how to bring the SOC building blocks together in a disaggregated format. The advanced silicon high development cost and lower yields are challenging designers to look for new ways of disaggregating system on chips (SoCs), to reduce the die size, by separating IP blocks that may not need to be in the most advanced silicon node. Creating a SoC-like solution with optimized silicon nodes for different portions of the chip is a new key focus. Advanced redistribution layer (RDL) packaging technologies that add a vertical integration element allow for a denser, 3D approach. At the same time, the traditional packaging components, such as substrates and interconnect technologies are also being pushed to limits in which new solutions are needed to extend roadmap requirements. These roadmap requirements are seen across all industry market segments including server, networking, graphics, mobile and telecom infrastructure.

Each market segment has unique requirements to meet their product needs and there are a few common challenges across all these segments. For example, as advanced silicon nodes continue to shrink the die size and increase the power density per square mm, the challenge of signal noise increases dramatically and must be addressed. New ways of providing power into critical areas

of the IP block and system design also create power delivery challenges. In addition, the impedance challenges of connecting one chip to another in a system dramatically reduces the performance that can affect battery life, or power requirements in an array bank of processors. The higher density per area of transistors and reduced line width to carry power also challenge the thermal capabilities of the package—and when combined with other areas of impedance in the system, can create larger system-level problems.

These challenges are impacting traditional SOC layout and architecture plans and require a new set of package structures. ASE has developed a series of RDL-based vertically-integrated packaging solutions that continue to evolve to meet these various challenges. These include six pillars underneath the VIPackTM platform include: fan-out system-in-package (FOSiP), fan-out chip-onsubstrate (FOCoS), fan-out chip-on-substrate bridge (FOCoS-B) (embedded), fan-out package-on-package (FO-PoP), 2.5D/3D and co-packaged optics (CPO). Each one of these package pillars addresses specific performance and/or form fit challenges and provides advanced solutions that address the market segments listed above. Packaging innovation within these six technology pillars are being evolved by ASE and these will be reviewed in the sections below.


As more companies look to system-level solutions and integration, system-in-package technology has expanded to leverage some more advanced process tools. The term system-in-package (SiP) has had many definitions over the years and as its umbrella has grown across both the low-end and high-end application spaces, the description must allow for advancements. ASE published its formal definition in 2014, which states that a SiP module is a package that contains an electronic system or sub-system and is min-

iaturized through IC assembly technologies. Although this is a broad definition, it still holds true today, as individual silicon solutions are moving toward highly-integrated system or sub-system level solutions.

If we look at the various package platform roadmaps today, we see a trend around miniaturization, not just for final package size, but also for performance. For the mobile space, the original equipment manufacturer (OEM) suppliers are driving component size reduction or integration across all sub-modules to enable more room for new functionality while managing battery space.


The integration of both a substrate-based package technology, with an RDL intermediate routing integration, has enabled a new structure called FOCoS. This package pillar helps to address the limitations of traditional flip-chip packages where a single SoC is assembled on a substrate. Two distinct categories are:

1. Utilizing the fan-out RDL process to redistribute the die-level I/Os to a coarser bump pitch to utilize less aggressive substrate design rules and/or to reduce the number of layers on the substrate. This approach also helps with low-k reliability issues related to chip-package interactions.

2. Multi-die and chiplet integration where two or more dies can be reconstituted into a fan-out module and then assembled on a substrate. The FOCoS platform provides versatility in integrating multiple instances of same dies or different dies across digital/analog and other functionalities to provide a highly integrated heterogeneous solution. Chiplet integration offers a compelling value proposition for yield improvement, IP reuse, performance, and cost optimization. Heterogeneous integration through advanced packaging technology enables chiplet integration with separate designs and different manufacturing


process nodes within a single package. It has provided advancement for more intelligence, greater connectivity, and higher performance at a more manageable cost.

Advanced packaging technologies such as flip-chip ball grid array (FCBGA), multi-

chip modules (MCMs), and 2.5D Si throughsilicon vias (TSVs) have been widely used for chiplets and die-to-die (D2D) interconnections across various semiconductor segments. However, with increasing demands for high density, high speed and low latency

of D2D interconnects, the FC MCM package has reached its limit due to the large Cu interconnect line/space L/S > 5/5 μm in the substrate, and unsustainable costs related to 2.5D Si TSV with larger interposer size (>2X reticle size). Therefore, alternative packaging solutions such as 2.5D TSVless and fan-out RDL interposer have been developed in recent years. Three of the six VIPackTM technology pillars namely, FOCoS, FOCoS-Bridge and 2.5D/3D provide chiplet integration options depending on the bandwidth, latency, and other design/performance requirements.

There are a number of FOCoS solutions, e.g., FOCoS chip first (FOCoS-CF) and FOCoS chip last (FOCoS-CL), that have been introduced. The schematic structure of FOCoS is shown in Figure 3 with the cross-section image as shown in Figure 4. The FOCoS package contains different chips and flip-chip devices mounted on a high pin count BGA substrate, and Cu RDL replaces the expense of using a Si TSV interposer to provide interconnects.

The FOCoS packaging technology has enabled chiplets integration with multiple RDL interconnects up to five layers, a smaller RDL L/S of 1.5/1.5 µm and a large fan-out module size of 32x38 mm2. It also provides a wide portfolio integration, such as an application-specific integrated circuit (ASIC) with high-bandwidth memory (HBM) and ASIC with Serdes across many segments of HPC, networking, artificial intelligence/ machine learning (AI/ML) and the Cloud. Furthermore, FOCoS has demonstrated the better electrical performance and lower cost than 2.5D Si TSV because of the elimination of the Si interposer along with reducing parasitic capacitance.


The Mobile phone space has continued to drive new functionality that has evolved the component level integration as well as the individual package requirements. The trend for most handheld consumer devices development has been towards multi-functional, high-definition display, low power consumption, high performance, and thin/ light packages, that are now commonly found in smartphones, tablets, and wearables. This trend drove the development of complex 3D or 2.XD integration on integrated circuit (IC) packages. Flip-chip package-on-package (FCPoP), initially with traditional C4 solder bump and later with fine-pitch Cu pillar was the primary package used because of the

Figure 1. A fan-out package on package (FOPoP). Figure 2. FOPoP cross-section details.

inherent low-inductance package interconnect.

The ever-increasing need for higher performance and thinner form factor drove the accelerated implementation of FOPoP in the mobile processor application space. The fundamental high-density, substrate-less configuration of the FOPoP package results in higher package performance because of the elimination of the substrate parasitic inductance along with a thinner package form factor.

Overall, the FOPoP structure provides 1) higher interconnection density and integration through a finer L/S redistribution layer (RDL) as compared to substrates, and 2) a shorter interconnect length resulting in better electrical performance, and 3) a smaller/thinner form factor because the fan-out technology allows die I/O signals to be fanned-out to a region larger than the die area without an organic substrate to meet a higher I/O count.

Figure 1 shows a FOPoP package with the cross-section image showing the die, RDLs, and Cu post details. Additional cross-section details are included in Figure 2, where the active side of the die utilizes two routing planes to fan out the I/O signals. Fine-pitch Cu posts are used on the periphery to enable electrical connections for the package on top.

The FOPoP package platform is further enhanced for increasing complexity and high-performance needs by enabling RDL on both sides of the die for increased integration and functionality. Furthermore, both landside caps and near-die deep trench capacitors (DTC) can be implemented to meet the power integrity requirements of advanced nodes. FOPoP is, and will continue to be, a key package platform for application processors, mobile/auto antenna-in-package (AiP), and co-packaged silicon-photonics applications.


Consumers with phone storage limitations and companies like Google and Facebook continue to add content to their data storage and cloud accounts. The increasing amount of data from all sectors, driven by digital transformation, is raising a problem of operational and storage costs. Meanwhile, the exponential cost leaps of silicon scaling and the unaffordable increasing of Si die size over the reticle limit have created an inflection point for the semiconductor industry. FOCoS-CF and FOCoS-CL technologies have been developed and introduced by using RDL interconnect for chiplets integration at

ASE. FOCoS-CF has been in mass production since 2016. Because of the inherent fanout RDL process limitation, however, it has hit a bottleneck in the manufacture of RDLs with higher layer counts (>6 layers) and finer line/space dimensions (L/S < 1 µm / 1 µm) for the applications that require high-density D2D connections, high input/output (I/O) counts, and high-speed signal transmission.

To address this, a new technology named as

FOCoS embedded Si bridge (FOCoS-B) has been developed to enable ultra-high density D2D interconnection with L/S < 1/1 µm for high-density chiplets integration. FOCoS-B packaging technology enables D2D interconnect by embedded a small Si die in a fan-out RDL interposer. The small Si die plays an interconnection bridge role between chiplets with L/S < 0.8 µm / 0.8 µm. Figure 5 shows the schematic structure of a FOCoS-B pack-

Figure 3. The schematic structure of a FOCoS package. Figure 4. Cross-section image of a FOCoS package. Figure 5. a) (left) Schematic structure and b) (right) the optical image for a FOCoS-B package.
a) b)

age with the optical image. It is composed of two identical fan-out modules, which are assembled on one FCBGA substrate in an MCM arrangement. The fan-out module is integrated by 10 chiplets (two ASICs and 8 HBM2e with 8 Si bridge dies). The FOCoS-B package body size is 78x70 mm2 with two fan-out chip modules at a size of 47x31 mm2, respectively. FOCoSB packages have passed reliability tests and chiplets integration has achieved good integrity. Figure 6 shows the cross-section of a FOCoS-B package; this package has extensive options and flexibility for multiple bridge die integration for mobile products, HPC, AI/ML and server applications.

FOCoS technology has demonstrated better electrical performance for chiplets integration. The fine-pitch RDL in FOCoS is essential to provide lower insertion loss and better signal integrity (SI) because of the thicker Cu RDL with L/S=2/2 µm compared to a thinner Cu RDL with L/ S=0.8/0.8 µm in a 2.5D Si TSV interposer, which results in the lower parasitic capacitance and lower cross talk. Figure 7 shows the insertion loss comparison between FOCoS and 2.5D Si TSV at different frequencies. The better eye diagram performance is also observed in FOCoS compared to 2.5D SI TSV, which is shown in Figure 8.

Table 1 by TSR in February 2022 shows the modular adoption rate across various radio frequency (RF) modules. The one reduced adoption is partially due to the exit of LG, shrinkage of Huawei and adoption of the power amplifier module with integrated duplexer (PAMiD). Because of this trend, the need for technology that enables further miniaturization and integration while managing new performance challenges is driving companies to look at fan-out wafer-level packaging (FOWLP)

Table 1. RF front-end module adoption rate. Source: TSR, Feb 2022 Figure 8. Eye diagram of a) (top) a FOCoS package vs. b) (bottom) a 2.5D interposer. Figure 7. Insertion loss comparison between a FOCoS package and a 2.5D interposer. Figure 6. A cross-section of a FOCoS-B package.

RDL SiP-based technology. Wi-Fi and ultra-wide band (UWB) RF modules are also leveraging the SiP platform. Figure 9 shows an example of a UWB module in an Apple iPhone 13 Pro with traditional SiP integration tools including packaged IC, discrete and IC components (five die, FC, WLP and shielding).

Specific drivers for FOSiP consideration include substrate thickness reduction, line/space control to minimize RF variation, and tighter component spacing for reduced losses for improved battery life (Figure 10). As with most advanced technologies, the key challenge is how to manage cost. When considering SiP, there is the tendency to focus on raw single-package cost vs. the system cost that integrates multiple packages and components. An overall system size reduction is realized by reduced individual component packaging, doublesided RDL for dense component integration (< 50 µm spacing) and a second RDL stack plane can simplify test, and in some cases, eliminating the substrate can help to enable a more competitive system solution.

Some of the key tools to consider in a fan-out RDL-based SiP may include chipfirst discrete passives, but this may require a Cu plating termination for integration into the RDL; or if chip last is used, a standard solder termination can be used. In addition, integrated or created passive components can also be beneficial. Both 2D and 3D spiral inductors, and even new inductor passives are being developed – within the RDL layers – to further improve the performance allowing them to be integrated and further miniaturized (see Figure 11).


High end processors and the integration of Wide-IO memory originally drove the need for a silicon based substrate to route the connections between processor and die. The 2.5D platform with a silicon interposer evolved as a natural progression from MCM on organic substrate because of readily available sub-micron L/S. This platform enables a greater than 1X reticle size die, and multi-layer sub-micron L/S for high interconnect density at low latency. The coefficient of thermal expansion (CTE) match between the active die and interposer also helps alleviate chip-package interactions that induce failure modes in flip-chip packages. Figure 12 shows the 2.5D package in high-volume production at ASE; an

Figure 9. 2021 teardown analysis – USI UWB. Source: TechSearch International. Figure 10. A chip-last double-sided FOSiP. Figure 11. a) (left) Embedded passives in the RDL layers; and b) (middle) discrete; and c) (right) created 2D and 3D.
a) c) b)
Figure 12. a) BGA side view of the 2.5D package; b) Top view showing ASIC and 4 HBM’s; c) Package cross-section with details of TSV in Si Interposer and bumps between interposer and substrate.
a) c) b)


ASIC and four HBMs are integrated on a silicon interposer using micro-bumps. The interposer is then assembled on a 70X70mm organic substrate.

Recent advances and ongoing developments in hybrid bonding (combined metal and dielectric bond) provide another step function improvement in interconnect density (Figure 13). Hybrid bonding is the

ideal candidate to achieve 10 μm and submicron scale for connectivity as compared to 100 µm pitch in advanced flip-chip technology. Both die-to-wafer (D2W) and D2D hybrid solutions address reticle size limitations for manufacturing large dies. The reduction in pitch provides flexibility in SoC portioning. Furthermore, reduction of interconnection lengths from mm

length to micron length, along with high area interconnect densities enabled by finer pitches, enables a true 3D structure with reduced footprint, low latency and high bandwidth while increasing the total SoC area. In addition to packaging portioned SoC dies, hybrid bonding enables stacking of 3D dynamic random access memory (DRAM), heterogeneous integra-

Figure 13. 2.5D to 3D evolution. Figure 14. Bandwidth/power vs. integration method.

tion at high I/O densities, lower power consumption, and form factor reduction.


What is beyond the traditional copper transmission lines? This becomes clearer when considering the speed a signal can travel through copper vs the speed of light. The next level of performance packaging for long-distance signal transmission is moving from the traditional copper conductor lines to light-based lines. Silicon photonics has been around since the mid-90s, but has faced technical and cost challenges. Since then, technical improvements and power-hungry scaling bandwidth requirements have driven the industry to accelerate the adoption of silicon photonics. Advances in module-based packaging of both pre-packaged and nonpackaged components have helped in the evolution toward CPO. When we look at the various ways network switches can be organized, there is a clear reason why co-packaging the switch die and optics are key. Figure 14 shows the increasing insertion loss (lower performance) and higher power requirements depending on how the communication is handled between the transmit and receive functions of the backplane.

This co-package configuration improvement reduces the losses between transmission lines and should follow similar rules when looking at IC packaging methodology. Looking at CPO closer, we see that this more integrated packaging methodology is bringing the critical components closer together to minimize losses between the electro-optical conversion process. Because of the custom nature of photonics ICs CPO generally does not follow any pre-defined packaging rules, which lead to many different types of configurations within the industry. To further improve the CPO area, components must be integrated in the most efficient way while keeping in mind the best way to attach the optical fiber. As mentioned above, when components are placed in a 2D plane, there are longer lines and losses associated with the layout. This can be further enhanced by creative packaging as shown in Figure 15. This figure shows a traditional PIC die next to the EIC, sideby side approach, but a more efficient

structure is shown by vertical coupling or grading coupling where the EIC die are located directly below the photonic IC. This is enabled by utilizing a double-sided fan-out wafer-level package structure that embeds two driver EIC die right below the photonic IC die, thereby minimizing the critical length between the dies. This type of sub-module integration can help to enable another level of performance improvement for CPO.


The industry continues to evolve and the new challenges are requiring new solutions. Six critically important packaging technologies form the pillars of ASE’s VIPack™ platform and are supported by a comprehensive and integrated co-design ecosystem. As described in this article, these pillars include ASE’s high-density RDL-based FOPoP, FOCoS, FOCoSBridge, and FOSiP, as well as TSV-based 2.5D and 3D IC and CPO processing capabilities. The VIPack™ platform provides the capabilities necessary to enable highly-integrated silicon packaging solutions required to optimize clock speed, bandwidth, and power delivery, and to reduce co-design time, product development, and time to market.

These six pillars will help to deliver unique opportunities to those seeking optimum efficiency and performance for

their applications. The technology pillars are built upon an open silicon ecosystem in partnership with foundries, component suppliers, and across the supply chain to provide design flexibility required for product realization. A spectrum of new process tools further enhances ASE’s current toolbox of capabilities and supports evolving package structures being developed in alignment with industry roadmaps. ◆


The ASE authors are based in North America and include members of the global engineering, marketing, and technical promotion team: Mark Gerber, Dr. Lihong Cao, Dr. Vikas Gupta, and Patricia MacLeod. Please contact Mark Gerber with any comments or questions: mark.

Figure 15. Traditional routing vs. advanced RDL integration.

Production Testing of MEMS & Sensors


The number and variety of sensors in typical mobile, wearable and automotive applications has exploded in the recent past and continues to grow well into the future. It is mission critical in select customer applications to ensure each of these sensors are production tested prior to assembly into the customer platform. Production testing of sensors requires the handler to induce the accurate level of stimulus in the range of operation and test access with tester instruments to test against the data sheet specifications. This article describes the production test challenges for high volume manufacturing.


Semiconductor, Outsourced Semiconductor Assembly & Test (OSAT), Multidie Packages, Heterogeneous Integration (HI) [1], Test, Functional Test, Structural Test, System Level Test (SLT), MicroElectro-Mechanical Systems (MEMS), Production Test Flow.

I. Introduction

Amkor delivers packaging and test services [2] for sensors and MEMS devices for magnetometers, accelerometers, gyroscopes, microphones, pressure, inertial, optical and RF (Radio Frequency) applications. Each of these sensor types may have a specific range of operation. For instance, absolute pressure sensors, side crash detection sensors, tire pressure sensors and barometric pressure sensors may be different sensors designed for the specific range of operation.

Temperature, pressure, and microphone sensor types may be amongst the highest by production volumes that have an automotive & environmental attach rate. There are a variety of test challenges for these products in the high-volume manufacturing process. The objective of this article is to highlight a couple of important aspects that are being resolved

by the test industry and Amkor, in order to reduce the overall production cycle times and hence the cost.

The RF sensors are a different category of product. RF sensors depend

on RADAR (radio detection and ranging). In an automotive application the transmitter transmits an RF pulse, which when reflected back from a reflector and received at the receiver is used to com-

Figure 1. Sensor package, without the ADC controller block. Figure 2. Sensor package, with the ADC controller block. Figure 3. Multi-die sensor package, may or may not include the controller.

pute the distance between two automobiles.

II. Multi-Die Package

For traditional customer applications, sensors are typically packaged separately. There are several benefits to the approach in the end application. The larger application platform may communicate with the sensor, via an application specific integrated controller (ASIC) over a slow speed serial digital interface like I2C, SPI, UART and/or others. There are two different functional block types within the package, one that includes an analog functional block and the other that includes a controller in addition within the package. Figures 1 & 2 show the two different sensor package blocks.

More recent application architectures and designs require higher density integration and hence demanding multiple sensors [2, 3] getting integrated within a single package. Figure 3 shows a block diagram on the left and a package model on the right. Heterogeneous Integration Roadmap chapter 17 [6] does a good job describing the challenges associated with multi-sensor product testing.

Depending on the sensor type and the end application, the sensor package may include a window to expose the sensor die, or be over-molded or have a cavity or may have a need to be a combination of molded and cavity type. These are pictured in Figure 4.

III. Key Test Challenges

One of the vital production test steps in the manufacturing process, is the Final Test step.

Production testing of sensor DUTs (Device Under Test) requires an ATE (Automatic Test Equipment), material handler and the test interface hardware. Figure 5 shows the functional block depiction of the production test cell. The package handler includes a calibrated stimulus source. This source generates the stimulus that the DUT is subjected to. The ATE is electrically connected to the DUT, via the test hardware and tests for all required data sheet attributes.

Product affordability & costing targets mandate multi-site testing of sensors. The magnitude of parallelism is limited by the maximum allowable parts that can be physically located on the test hardware, stimulus constraints and the number of parts the handler is able to present at the test sites.

The tester resource requirements to test most sensor types includes the appropriate count of channels on the power supply, digital & clock channels and analog test channels. (see Figure 6)

RF sensors are different. RF sen-

sor test requires RF instrumentation within the ATE. These radar sensors may include an antenna that may be integrated within the package. The CW (continuous wave) frequencies may range from <10GHz to <100GHz and signal power

Figure 6. Power, analog and digital signal path connection. Analog connection integrity is maintained, with differential signals. Digital connections are single-ended. In both cases, signal path calibration may be required. Figure 5. Functional blocks of the typical production setup Figure 4. Example Amkor Packages (Left to right) Exposed die, Overmolded, Cavity, Molded/ Cavity Package. Figure 7. Shown on the left is the live “bug” view of the RF sensor production test setup and on the right shows the top view of the block representation of the patch antenna placement on the top surface of the package.

<+10dBm, depending on the end-application requirements.

Testing of RF sensors is challenging, from a DUT setup standpoint. The twoway RF signal path between the test head and the DUT is made up of conduction path medium that may include shielded cables and the lossy over the “air” medium. Production setup must be repeatable and reproducible and calibratable. Any deviations from acceptable limits may result in loss of yield.

While multi-sensor packages, like the ones outlined in Figure 3, result in higher levels of integration, they may result in increased test times per insertion or increased count of test insertions to test each sensor, which again results in increased test time and hence the cost. Examples of multi-sensor packages include pressure/temperature, microphone/temperature or humidity/temperature.

The most popular and demanding market segment with the most stringent test requirements is the automotive market [4, 5]. The automotive industry, as of the writing of this article, is driving the most complex packaging and test services.

IV. Package Handling Challenges

Test capabilities for temperature sensors is by far relatively easily implemented in production test. Package handler manufacturers have stimulus sources integrated with package handling equipment. The number of choices of these stimulus sources is large and mostly customized by the handler supplier for each type of sensor. Sensors for microphone, magnetometer, accelerometer, pressure, relative humidity, gas detectors, and others may require test signal isolation from the production environment. At the same time, product affordability warrants maximizing parallel testing. Figure 8 shows an example of 70 sensor placement topology being tested in parallel within a production material handler.

Product specific parallel site test hardware design including DUT sockets, may require careful design verification to ensure all sites are stimulated within the specified test limits.

Microphone testing may be sensitive to stray ambient (e.g. facility ventilation air ducts) sound sources. There are numerous stray sound sources within the

production test environment that may impact the test result and production yield. In addition to isolation of stray sources of sounds, the manufacturing test cell may be sensitive to motor vibrations, floor footing vibrations, and changes in light sources, etc. Test equipment motors may need to be paused for the duration of test, which may impact the overall production throughput. Vacuum cups on the plungers to pick and place DUTs into test sites requires careful design, to avoid damaging the unit. Mechanical handling of pick and place or bowl feeder handlers is designed to prevent dropping of device packages. Dropped packages result in loss of manufacturing yield. Production site facility requirements are stringent. Production yields may be sensitive to variation in test facility temperature and relative humidity during the day and night. In order to alleviate some of the above stated challenges, handler vendors have encapsulated microphone test stimulus within an isolation chamber. The shield design isolates the DUTs from getting impacted for the duration of testing. Stimulus reference sound source and reference microphone may require periodic calibration, depending on the production environment to ensure impairment free operation.

Pressure sensor testing, depending on the range of operation, may be sensitive to minor leaks within the test chamber of the handler. The handler pressure chamber is designed to maintain, pressure, temperature, and relative humidity within the allowable specification limits. Cycling production parts through the chamber may result in condensation. This may result in additional settling times that slow down production throughput.

Sensors may require per unit trimming at a specific temperature and relative humidity, to ensure accuracy to the product data sheet. The trimming process may or may not be completely automated and while trimming necessary to perform, it may take time, that reduces the production units per hour (UPH) metric.

Other MEMS and sensors may have their own set of non-idealities within the handler and stimulus chamber. Multisensor products have continued to add complexities to the production test processes and systems. MEMS and sensor production test equipment may benefit from ‘design for manufacturing’ systemic and design improvements, that will allow production sites to keep the overall manufacturing costs from increasing as the sensor product volumes grow in the future.

MEMS and sensors in all categories may require multiple test insertions to test the performance at the complete temperature range of operation. Automotive range of operation may be wide.

Higher the site parallelism, higher are the sources of errors that impact the overall production throughput. It takes time and effort to eliminate test equipment induced false failures, to optimize first pass yield. Re-test of sensors may be required, to keep test equipment induced failures in-check. Methods to isolate true sensor architecture, design, fabrication, and package assembly related failures are required to be accurately tagged to allow process improvements generation over generation.

V. Test Manufacturing Metrics

There are a variety of key process indicators (KPI) that are tracked to ensure

Figure 8. DUTs layed out in an insulated chamber within the production environment. The chamber includes a calibrated stimulus source that is not shown in this view.

that test factory efficiencies are at the optimal levels and the out-going quality metrics for sensor production test are met. Typical factory throughput indicators may include Units per Hour (UPH), Units per Month (UPM), test cell count, lot rejection rate (LRR), first pass yield (FPY), on-time delivery (OTD), customer returns, inspection failures, and others.

Apart from sensor architecture, design, fabrication and packaging related failure mechanisms (true failures), inefficiencies that result in less-than-optimal yield for sensor production testing primarily stem from consistent performance on all parallel sites within the test cell. The central reason for site failure may be test hardware (load-board) related or inconsistent performance of the stimulus. It may be important to track the aging of production test hardware, to ensure that these fail mechanisms are minimized or eliminated with systemic root cause fixes.

VI. Summary

The number of sensors in recent applications is rapidly growing. IOT,


wearables, mobile and automotive applications are continuing to demand application specific higher resolution, accuracy, and range of operation for existing sensors. Complexities in production testing of MEMS & sensor devices is continuing to grow. New complexities are demanding streamlining and efficiency improvements to existing test equipment technologies, manufacturing processes, and systems.


The author expresses his gratitude to Amkor’s package design teams to allow sharing block level representations to surface production test complexities. The author also thanks Amkor’s sensor mass production test site manager Mon Lopez for providing feedback and areas of improvements that allow consistent test factory throughput.

Author Biography

Vineet Pancholi joined Amkor in Jan. 2019 and currently leads test technology development for 5G RF and high-speed

digital production test methodologies. Before joining Amkor, Vineet worked in test development at Microchip Technology. Prior, he spent 19 years at Intel in a variety of test roles, including tester supplier management, test technology development (burn-in, final and system level test) and RF tester architect. Vineet holds a patent on semiconductor device testers and has earned master’s degrees in physics and electrical engineering from Arizona State University. ◆


[1] Heterogeneous Integration Roadmap [2021] Chapter 11 – MEMS and Sensor Integration

[2] Amkor’s MEMS and Sensor Packages & Applications

[3] Amkor’s MEMS and Sensors Technology Sheet

[4] Amkor’s Automotive Brochure

[5] Amkor’s Test Services Brochure

[6] Heterogeneous Integration Roadmap [2021] Chapter 17 – Test Technology



SMART MICROSYSTEMS is excited to reside in America’s Silicon Heartland as the Midwest region of the US is now poised to create the next international semiconductor boom. As part of the semiconductor supply chain, SMART Microsystems provides services for microelectronic sub-assembly manufacturing. In addition to process development expertise, SMART Microsystems has in-house Test & Inspection capabilities making it a comprehensive resource for the development and manufacture of the next generation of products that require microelectronic sub-assemblies.


Test & Inspection

Wafer Dicing • Die Attach • Wire Bonding

Heavy Gauge Wire and Ribbon Bonding

Encapsulation and Dispensing

Test & Inspection and Failure Analysis

Reliability and Environmental Life Test

Super UV Weathering Chamber Testing

141 Innovation Drive, Elyria, Ohio 44035

Telephone: 440.366.4203

SMART Microsystems is located on the Campus of Lorain County Community College in the Great Lakes Technology Park.

Catching Up with Roger Grace

Founder and President

Roger Grace Associates

Owing to a very diverse and accomplished association of MEPTEC members, there are many informative, instructional, and entertaining stories to be told. “Catching Up With...” will feature stories from and about our members.

Roger Grace ( and https:// joined the MEPTEC Advisory Board in 2022. This interview was conducted via email and edited for clarity.

Wow, you’ve done so many interesting and exciting things over your career, it is hard to know where to start. How did you landed at Northeastern University and what interested in you in Electrical Engineering?

I was born in Cambridge Massachusetts and grew up in Somerville…the adjacent town. My mom was born in Portugal and emigrated to the US at the age of 14. Coming from a family of modest means, as a first-generation PortugueseAmerican, we did not have the necessary financial resources to have me attend college, and especially one out of the area, so I applied to several local Boston schools. I chose Northeastern since it had a co-op (i.e. work/study program) and was easily accessible by public transportation from my home. I received a scholarship for my freshman year and I made enough money at my co-op job to pay for the remaining four years of tuition (co-op at Northeastern is a five-year program). Virtually all of the men in my Somerville High School graduating class of 1961 who went off to college also chose Northeastern because of its immense value proposition. ..affordable tuition, proximity, convenient public transportation…and most importantly … they could receive an excellent engineering education and gain valuable experi-

ence vis-à-vis the co-op program and secure a great well-paying job (locally). I continue my close affiliation with Northeastern having served on several committees including the College of Engineering Industrial Advisory Board, organizing an all-day technical conference on printed sensors at their Silicon Valley campus and having been bestowed the College of Engineering Outstanding Alumni of the Year Award in 2004. (see Figure 1)

physics teacher…Mr. Paul Protopappas…I just loved solving physics problems.

As you worked on your Bachelor and Master degrees at Northeastern, you also worked on antenna and microwave systems at Avco Missile Systems and Raytheon. This was way before microwave communication was as common as it is today. Did you work on any specific applications?

I knew that I wanted to be an engineer as a young boy. My parents bought me a mega-size Erector set when I was seven or eight and I was totally consumed in building things. I also frequently disassembled and re-assembled my bicycle’s gears and my spinning fishing reel (I guess that this means that I was a young “gear head”). I grew up during the beginning of the space era…I was fascinated by the technology and I wanted to be a part of it…especially since there were so many companies located in the famous Route 128 area nearby engaged in this type of work. I was also very much encouraged to follow this course of study being significantly influenced by my high school

I was truly blessed to have an incredible co-op assignment with Avco Missile Systems in Wilmington in 1962. The group to which I was assigned was staffed with many Northeastern co-ops…both undergrad and graduate, many of whom went on to become quite famous in later years working for Raytheon as senior managers. I worked on developing microwave components and antennas for missile re-entry vehicles. I started out testing components and plotting Smith charts of impedances and taking radiation pattern measurements on the antenna range. By the time that I was a junior, I was designing microwave components and antennas and I remained at that job after earning my BSEE. I may not have obtained the highest grades but I did receive the highest job offer of my entire 1966 Northeastern graduating class due to my significant design experience obtained during co-op. [1] After a year as a full-time engineer, and while attending Northeastern’s MSEE program in the evenings, I accepted a position at Raytheon in Sudbury designing microwave antennas for active jamming systems. While there, I applied and was awarded a Raytheon Company Fellowship to complete my MSEE degree. After receiving my MSEE, Raytheon transferred me to Goleta (Santa Barbara, California) where I was a project engineer managing a team of technicians and engineers designing antennas and

Figure 1. Roger with his parents, Henry and Albertina Grace, flanked by Northeastern President Richard Freeland taken at the Boston Ritz Carlton Hotel on November 2001 during ceremonies commemorating his induction into the (alumni philanthropic) Frank Palmer Speare Society of Northeastern University.

feed structures for jamming systems and phased arrays for the B-1.

What was working at Ford Aerospace here in Silicon Valley like in the 1970’s compared to today?

It became quite apparent to me during my Santa Barbara stint that I missed my days living in a big city. I then accepted an offer from my previous Raytheon supervisor who was then at Ford Aerospace in Palo Alto. I started as a senior project engineer and was able to move to San Francisco. At Ford Aerospace, I managed a team of engineers and technicians to develop antennas and communication systems for military and commercial satellites and spacecraft. I thoroughly enjoyed working with my team and the relative “pastoral” setting of Palo Alto in the mid 1970’s. I had a pleasant 30 minute / no traffic commute from my San Francisco apartment! I later did a great deal of proposal writing and then making presentations on the NASA JPL Viking Orbiter ’75 project that I was managing. I felt that this was my calling…not designing…and I decided to apply for a marketing position at Ford…which was not in the cards for a person who did not have any connections in the Department of Defense. I then accepted a position at Avantek (now HP) as a marketing engineer for the company’s solid-state oscillators and amplifier products for the company’s military communications business…visiting customers and managing a rep network sales force. At that time, I also began my MBA program at the evening UC Berkeley Haas Graduate School of Business program.

How ground breaking was the Foxboro ICT microelectromechanical systems (MEMS) pressure sensors? How did you end up as the Marketing Manager at this medical device “startup”?

My tenure with Avantek lasted two years. After that, I was employed for a brief time at an advertising agency in San Francisco as an account executive…but was not pleased with my situation. A colleague introduced me to Don Lynam, CEO of Foxboro ICT who was looking for a marketing person. This was an instant connection…Don was from the Boston area

and graduated from Northeastern….and a fellow Red Sox fan. He wanted to create a marketing function in his 90-person, $5 million company and “groom” a successor…. i.e. me.

Don, Bill Geene, and Gene Burk started the company in 1971 as a buyout from Fairchild Semiconductor. Fairchild was developing silicon sensors for a military avionics program using 1.75 inch

feasibility of developing this device and specifically its features, specifications, price-point, and details of its specific various application scenarios. As a result of the research findings, we decided to collaborate with Sorenson Medical to design and manufacture this product and bring it to market. This product became a major success at Foxboro/ICT. Its current global annual market is approximately 35 million units and is manufactured by several companies including NovaSensor.

When you left Foxboro, you started your own company Roger Grace Associates. Was there something that inspired you to go out on your own?

Short answer…I was fired! I believe that I was most successful in my role at Foxboro/ICT over my two-year employ. However, Foxboro corporate management decided to restructure the management team at ICT after Don Lynam resigned for personal reasons. I and several other close allies of Don lost our jobs in a “purge” in the fall of 1980. For over a year, I searched diligently but did not find a job that I wanted to accept. One of my previous vendors at Foxboro/ICT owned a lead management company and offered me the VP of Sales position. I recommended that he needed a marketing plan first and instead he became the first client for Roger Grace Associates.

silicon wafers. I created an integrated marketing communications (iMARCOM) program and conducted market research to uncover new application opportunities for our “integrated circuit” (now referred to as MEMS) piezoresistive pressure sensor product line. Joining Foxboro/ICT in 1980, I was blessed to be able to collaborate with several exceptionally talented engineers including Janusz Bryzek, who was a project engineer at the time. (Janusz recently passed and I helped organize and co-author an article which appeared in the December issue of the MEPTEC Report.[2]) Together we were successful in developing the sensor industry’s first disposable blood pressure sensor an opportunity I uncovered. I invested a great deal of time visiting hospitals and clinics around the US conducting in-person interviews with hospital administrators, physicians, nurses, and biomedical engineers to assess the

My “big break” came as a result of being retained by the French Government’s newly formed organization FTEC. FTEC’s mission was to introduce French high-technology (this was considered to be an oxymoron by many of my friends and colleagues) to the US market. My role was to head up their “passives” group and to vet French companies who wished to enter the US market. These companies received significant funding from the French Government Department of Commerce to accomplish this. This was a three plus year consulting job and I loved going to New York City monthly and Paris bi-monthly to have meetings. While at FTEC, not only did I vet many French passive product manufacturers, I also created a manufacturers’ representative network covering all of the US, visiting customers with the reps, setting up an applications lab, creating a promotions

I recommended that he needed a marketing plan first, and he hired me to create one –my first client for Roger Grace Associates

program, and conducting competitive research on similar US manufactured products. My most significant success at FTEC was with Radiall which designs and manufactures microwave connectors and passive components and is a successful business to this day.

You’ve worked with many different people and companies as a marketing consultant… Are there any particular engagements / projects that you are most proud of that you can discuss?

My most favorite, gratifying and memorable experience since the founding of Roger Grace Associates in 1982 was with NovaSensor. In October 1985, I was part of the startup team of Kurt Petersen, Joe Mallon, Janusz Bryzek, and Joe Brown. I declined coming aboard full-time as their CMO and opted for a retained consulting position with stock options. My role at NovaSensor included conducting market research to determine product definition and details on competitive offerings. I was also responsible for creating and implementing an integrated marketing communications program with a focus on public relations to brand and position the company.

Through our close collaboration and a lot of hard work, NovaSensor quickly emerged from an obscure startup to an acknowledged industry leader. Giving presentations at technical conferences, including Sensors Expo, and publishing articles in many OEM electro-mechanical design publications gained us instant incredible visibility and awareness and resulted in much needed credibility in the eyes of our targeted designer community…and future investors. We won several international awards for the product launches that we created and won the prestigious R&D 100 Award for the silicon fusion bonding process technologies created by Kurt Petersen. We also contributed articles and our products were featured in many OEM design publications including a 34-page cover story in IEEE Spectrum (I believe that this was and is an all-time record) as well as extensive coverage in national daily publications including the New York Times, Washington Post and made several appearances on TV including 60 Minutes!

The most interesting thing was that NovaSensor had no shippable products for the first six months of the founding of the company…. but with the significant experience, immense interest and enthusiasm of its founders, we decided that our strategy was to extoll the virtues and benefits of MEMS as a unique technology to address many of the emerging markets. This positioning and branding strategy was the basis of establishing NovaSensor as the technology spokesperson of MEMS technology. It also was key in the development of significant new business opportunities for our “micromachined sensors”, a term that Kurt had created.

Following NovaSensor, I thoroughly enjoyed my consulting activities at another MEMS startup…Si-Time…working again with Kurt Petersen (CEO) and Joe Brown. Si-Time had a most unique MEMS oscillator which was developed at Stanford under the direction of Prof. Tom Kenny with intellectual property (IP) from Bosch. We were the fourth organization to enter the “system timing products” market…but within a period of approximately six months, we were again on the way of becoming the “industry darling” and industry spokesperson of MEMS silicon system timing products appearing in no less than six front-page articles in major international OEM design publications. All of this exposure provided Kurt and his team with the ammunition to obtain significant valuation in its subsequent rounds of VC funding. Once again, RGA was able to help capture several international awards for their most successful iMARCOM efforts as well winning a R&D 100 Award and a EETimes Award for best startup. Si-Time continues to this day as the spokesperson of the MEMS-based system timing products market.

What wisdom have you collected from your experience and the MEMS industry luminaries you have worked with that you care to share? Especially if they are applicable to other technology areas.

I have found in working with many dozens of companies over my last 40-plus years of technology consulting that my preference is definitely in startups and

small companies in the hardware space that have a unique product. Technology companies, especially startups, are typically product driven. And even though I am an engineer, I have “crossed over to the dark side” and became a technology marketer. My focus as a technical marketing consultant has been to help my hardware clients understand the market and the needs of the customer. The best way to accomplish this is to ask the customer what are their unfulfilled needs. This is no different than the homework assignments I gave my UC Berkeley students (more on this later).

We guide many of my clients by undertaking custom market research to best understand their potential customers and their competition’s strengths and weaknesses. Finally, I am a major advocate of conducting extensive and well-planned research to best understand my client’s internal competencies. The outcome of all of this research is to create a product solution that has a high level of potential success.

Additionally, I stress the addressing and communication of user benefits not product features. Quite frequently engineers are focused on achieving the best performance… Instead, they should focus on how the product specifications, features, and price -point make it the best possible solution to the customer’s needs. I always point out that they do not have to be perfect, just better than the competition. It is not what you have to sell but rather what the customer needs is my mantra.

My true pleasure in consulting is to make a discernable contribution to the success of the organization vis-à-vis collaborating with clients who embrace and value me as an integral part of their team not as a “hired gun”. My substantial engineering background has definitely helped me be accepted and considered as a peer by my clients. I truly enjoy working with startups with people who are wildly creative, with lots of energy, and are focused on achieving results and are not afraid of failure. Some of my most favorite clients are Janusz Bryzek, Kurt Petersen, and Joe Mallon…the NovaSensor founders.

How do you explain what Roger Grace Associates does especially for those


who confuse Marketing with Marketing Communication?

I inform my clients that hiring RGA as a retained marketing consultancy is like hiring a full-time VP of marketing but without the overhead and cost while achieving extraordinary results. We perform all of the classical marketing functions not only planning like many consultancies provide, but rather executing the plans through to completion, measuring the results and making recommendations on how to optimize the results…identical to a classical closed-loop control system. The focus of our client base is on technology-based hardware companies. Over the past 20 years, we have focused primarily on addressing the MEMS and sensors areas and are able to provide our clients with an insightful and highly experienced perspective on how to create products and how to best bring the products to market using the many tools of an iMARCOM program driven by extensive market research. It has become quite obvious to me over the years that marketing communications was not understood by my engineering-driven clients especially in the MEMS and sensors arena. I have seen the positive outcome of implementing an iMARCOM program with many of my clients and have especially experienced the incredible ROI of well-planned and executed public relations programs especially in the authoring of articles and presentations at key industry events. Most importantly, this approach of making presentations at conferences and writing articles are fully embraced by RGA to create our position and brand in the industry as leaders in the field of technology marketing. And most recently, with the emergence of social media, the “toolkit” of classical MARCOM elements has been augmented by social media and especially email blasts, LinkedIn, Facebook, and webinars to supplement the reduction of in-person conferences during COVID.

As someone with an extensive Engineering background how do you approach Marketing differently than someone without this experience?

When I ask my clients why they selected RGA over other technical marketing

consultants…the answer is consistently because of my in-depth engineering background and my ability to be able to understand their technology and manufacturing processes as it applies to the customer’s needs and applications….and most importantly, they trusted my judgement and subsequent recommendations. I am able to participate and contribute to technical meetings and understand the

understanding the editorial process and providing editors with information they require to help them create their articles. My contributions to the sensors industry were acknowledged by the bestowing of the Inaugural Sensors Industry Impact Award by Sensors Expo during the 2016 Sensors Expo. (see Figure 2)

MEMS technology took many years to go from concept to the widespread deployment of today especially with tens of MEMS sensors in every smartphone. Does the similar story of development to market apply to other technologies?

technology concepts and applications and the competitive landscape for their product offerings….and there is no rampup time…”I can hit the beach running”. I also use my several years in corporate marketing positions at Foxboro/ICT and Avantek to be able to place myself “in their shoes” as corporate marketing people. Another main benefit my clients gain from my extensive design engineering knowledge is my ability to effectively communicate with editors of publications who are aware of my technical background, the story of my clients’ technology and its customer benefits in solving application challenges. This is accomplished while simultaneously

Many years ago, and with Professor Steve Walsh of the University of New Mexico, we conducted a market research study to determine the time for approximately a dozen MEMS sensors to successfully translate from discovery to full commercialization…and the answer was approximately 30 years. MEMS pressure sensors were the first in this lineup and it took approximately 36 years. (see Figure 3.) I have lectured extensively about the outcome of this research and published the results for well over a decade and believe that it is typical of all products. This “MEMS commercialization process”, as shown in Figure 4, progresses through the four states of the product life cycle process…from introduction… to growth… to maturity and to finally to decline for most technology products. Currently, MEMS is solidly in the maturity state while other newer sensor technologies including printed and functional fabric technologies are at the beginning of their growth cycle.

Please tell us about the Roger Grace Associates MEMS Industry Commercialization Report Card. Why did you start doing this and why is it important?

I decided in 1998 to revisit this earlier research and to determine its rationale… my conclusion was that there are a number of critical success factors that all need to be in place to make this happen. After considerable research and a thorough review of industry offerings addressing this topic, I decided to create the MEMS Industry Commercialization Report Card.

Figure 2. Roger was the recipient of the Inaugural Sensors Expo Sensors Industry Impact Award during ceremonies held during Sensors Expo in June 2016 in San Jose, California.

Here, I judiciously selected 14 of these factors and have been reporting on the progress (or lack thereof) of the MEMS industry using market research, called the

Delphi Method, to interview approximately 45 MEMS industry pundits to not only obtain their letter grades but to have them provide their verbatims as to the rationale

of the grade given. The results of the 2021 Report were published in MEPTEC Report in the December 2022 issue. It was my initial intent and continues to be to conduct this research annually and publish the report and communicate it to the industry participants such that can learn from “state of the technology” from industry pundits and how to better achieve commercialization success. [3]

You were a visiting lecturer for the E-110 “The New Venture” class at the University of California, Berkeley from 1990 to 2003. You must have seen some really innovative business plans. Were there any that you knew would be a hit but weren’t or the reverse? Any success stories to highlight from your students?

I had the distinct honor and pleasure to be a visiting lecturer a.k.a. adjunct faculty member in the School of Engineering at the University of California, Berkeley. I team-taught this class with several other professionals to 32 upper-division students as an elective. My responsibility was to teach the marketing and chains of distribution functions of a business while my colleagues taught finance and intellectual property. The purpose of the class was to teach students how to collaborate in a team effort to produce a business plan for a product or service that they selected. Weekly, each of us would address the class with topics and the students would (hopefully) integrate some of it in their business plan. The notebooks which held the business plans were submitted weekly for our review and comments. The teams, like most startups, had the functions of CEO, CTO, CMO and CFO. The final grade was based on their business plan as well as their presentation which was given to a packed audience made up of VCs, angel investors, and professors from the Business School as well as invited guests. Since the classes were given during one of the country’s major technology booms, it was quite easy to have some of the presentation ideas receive immediate funding commitments during the presentations in the hallway outside the presentation room. The university did not permit the instructors to invest in these plans, however the psychic value to me and the others

Figure 3. Extensive research conducted by Roger Grace Associates and Professor Steve Walsh of the University of New Mexico has established that it takes approximately 30 years for a MEMS sensor to go from discovery to full commercialization. Figure 4. The commercialization process for MEMS, as well as for other technologies, is driven by several market research activities both in the front-and back-end of the process.

was truly gratifying. For the first class of each semester, we would invite one of the students whose plan was successfully funded in the past. They returned to the class with their great stories of success and all dressed up in fashionable Armani suits with their BMW convertibles parked downstairs in the faculty parking lot. The ideas that the students presented spread the spectrum from hardware to software…from low tech to high tech and from B- to -B and B- to- C sectors.

During my many lectures, I constantly impressed upon the students the incredible value in conducting market research and especially, if possible, in-person at the nearby Emeryville Best Buy parking lot and recommending that they wear their Cal sweatshirts and hats to establish their credibility. This approach is no different, but without the wearing of the Cal clothing, to what I recommend and conduct as part of my marketing consultancy to my clients where we conduct in-depth and person-to-person research at trade shows, focus groups or over the phone…and when these are not readily available…via email/web.

What do you do in your spare time to relax? Any particular hobbies?

My hobby portfolio diminished significantly as a result of COVID since it put a major damper on airline travel which was one of my favorite things to do. In the past, I was fortunate to have several international clients and made many trips to Europe especially as the president of the Micro and Nano Technology Commercialization Foundation (MANCEF) to give presentations at technology conferences. As my visits to Europe continued, I was invited to become a member on various EU Technical Committees and technical conference organizing committees and attend many meetings and conferences including the Smart Systems Integration Conference and the Advanced Microsystems for Automotive Applications. I always made it a point to spend additional time after these events to do some sightseeing in nearby areas. I especially loved visiting Paris and travelling to various wine regions to do wine tasting which is perhaps my most favorite hobby. Also, since I am a WW1 and WW2 buff,

I have visited many of the battlefields there including the landing beaches in Normandy and Bastogne, Belgium (Battle of the Bulge) for WW2 and Ypres, Belgium and Verdun, France for WW1.

I spend the majority of my time now at my Pacific Grove (Monterey) California 1905 “bungalow” tasting the local wines and visiting the Monterey Bay Aquarium. Also, I am a major classical music lover, listening to music and attending concerts whenever possible. I have had the great pleasure of visiting many of the beautiful concert halls in the US and in Europe. I have attended and am a patron of the annual Carmel Bach Festival for over 30 years.

I am a huge baseball fan of the Boston Red Sox. I remember starting at about seven years old attending Sox games at Fenway Park with my dad, another major fan. I continue to this day as a member of Red Sox Nation having had the immense pleasure of attending the Sox’s winning of the 2013 World Series at Fenway Park over the St. Louis Cardinals. And

celebrating with my parents the Sox’s World Series victory in 2004 breaking the 86-year “curse of the Bambino”. I also had the honor of throwing out the ceremonial first pitch at the Northeastern University/Boston Red Sox Spring Training game in Ft. Myers, Florida in 2017. (see Figure 5) I have visited 15 of the 30 major league ballfields as part of my love for the game and expect to visit them all over time.

Finally, I am a major “foodie” and love to watch cooking shows …Lydia Bastianich on PBS especially… and cooking Italian food. I believe that this started while I was a teenager in Boston while watching Julia Child a.k.a. The French Chef on TV from the Boston PBS station WGBH. Julia lived nearby and on occasion I would see her at lunch in Harvard Square.

What are your favorite places to visit for work and for pleasure?

Because of Covid, I have had to curtail my planned visits to many places especially Boston, where I still have family, and visit professors and administration colleagues at my Northeastern alma mater. I love to attend Red Sox games during the summer months as well as visit Cape Cod and eat lots of fried clams and lobsters! My future travel plans are to visit Cuba, the Baltic countries and St. Petersburg Russia (when political situation is better) and to take a wine cruise up the Douro River in Northern Portugal. ◆


[1] Northeastern University College of Engineering Magazine, A Northeastern All-Star, Fall 2017,

[2] R. Grace et al; Janusz Bryzek Tribute Retrospective; MEPTEC Report; Vol. 26, No.3; Fall 2022; pp.8-10; https://www.

[3] R. Grace; How Covid and the Down turning Economy Uncertainty are Affecting the Successful Commercialization of MEMS and What To Do About It: The MEMS Industry Report Card; MEPTEC Report; Vol. 26, No.3; Fall 2022;pp.1620; MTReport-26.3.pdf

Figure 5. Roger warming up for throwing out the ceremonial first pitch at the annual Northeastern University/Boston Red Sox ballgame at the opening game of the 2017 Spring Training Season in Ft. Myers, Florida.
MONSTERPAC® 80 170℃ Flip Chip Bonding URL: http://www.ConnecTec E mail: sales@ConnecTec Seoul / Sales Office #16229, 1109Room, Ace Gwangyo Tower2, 1286-1, Iui-Dong, Yeongtong-Gu, Suwon-Si, Gyeonggi-Do, KOREA San Jose / Sales Office 2033 Gateway Place,5th Floor, San Jose, CA 95110, USA OSRDA : Out Sourced R&D and Assembly Niigata / Head Office, R&D and Factory 3-1 Koudan-cho, Myoukou City, Niigata, JAPAN 944-0020 Phone: +81-255-72-7020 Tsukuba / R&D Laboratory By connecting various technologies, we provide comprehensive support and services for customer needs through cooperation with our affiliates & partners. MEMS/Bio/Photonics Flexible PET/PEN/PU Fine Traces/Bumps Large Die
Perfection Products Inc. 1320 S. Indianapolis Ave. • Lebanon, IN 46052 Phone: (765) 482-7786 • Fax: (765) 482-7792 Check out our Website: Email: Grip Ring Shippers I. C. TraysMulti-Channel Lead Frame Magazines - F.O.L./E.O.L. Film Frame Magazines Film Frames Film Frame Shippers TO Tapes & Magazines Magazines and Carriers for Process Handling Solutions Accept Nothing Less. Substrate Carrier Magazines Stack MagazinesE.O.L. Wafer Carriers Process Carriers (Boats) Boat Magazines Grip Rings Miscellaneous Magazines I. C. Tubes and Rails Grip Ring Magazines
Issuu converts static files into: digital portfolios, online yearbooks, online catalogs, digital photo albums and more. Sign up and create your flipbook.