COLUMN COUPLING & CROSSTALK By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology, but occasional crosstalk diversions may deliver a message closer to home.
Curves & Waves Last year was the 75th anniversary of the invention of the transistor. The Institute of Electrical and Electronics Engineers (IEEE) and other organizations celebrated this milestone with retrospectives as well as looking ahead. There is plenty to celebrate as these devices are the cornerstone of all modern electronics. Transistors are the “silicon” that created Silicon Valley as the center for technology innovation that impacts all of our daily lives. In 1955, William Shockley built the Shockley Semiconductor Laboratory (less than a mile from our home) to pursue his version of the transistor. However, the primary research team he assembled did not take kindly to his interference. The “Traitorous Eight,” as they later become known, left to form Fairchild Semiconductor from which almost all other technology companies claim lineage. As incredible as the transistor technology and story may be, many of these articles neglected to place the transistor into the historical context of technology curves and innovation waves. For this, we need to discuss Moore, Dennard, and go even further back to Kondratiev. Gordon Moore in his seminal 1965 article “Cramming more circuits onto integrated circuits” (Electronics, Volume 38, Number 8) said “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (…). Certainly, over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the 6 | MEPTEC REPORT
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number of components per integrated circuit for minimum cost will be 65,000.” (Emphasis added.) In 1975, Moore revised his forecast that the doubling rate would slow down to approximately every two years after 1980. These predictions have become known as “Moore’s Law”. Many people misquote or misinterpret Moore’s Law to say that transistors will shrink in size every two years or that the number of transistors in each integrated circuit will double every two years. They also confuse it with Dennard Scaling (discussed below). Moore’s Law is not about the number, size, or density of the transistors themselves but the cost of building integrated circuits (devices) with them. I.e. the economics of fabricating and connecting them in a single device. In the last decade there has been a debate if Moore’s Law was dead as the largest semiconductor manufacturers continued to push ahead to even smaller process nodes. It is clear that the cost per transistor (component) has been increasing for several years for the advanced process nodes – therefore it is unequivocal that Moore’s Law no longer holds strictly speaking. Even though Moore’s Law no longer governs the economics of fabricating transistors (integrated circuits), its continued importance cannot be underestimated in at least two ways. The first and most important thing it did (even when misunderstood) was to create the customer perception that electronic devices would either double in speed/performance/capacity or decrease in price by one-half every two years. Or an equivalent combination of performance improvement at lower cost. This has created never satisfied market place expectations requiring product companies to continuously improve their offerings. Luckily, technology companies were able to continue to deliver increased performance as a benefit of Dennard scaling by pushing ahead with the development of advanced process nodes (smaller transistor sizes). In 1974, Robert H. Dennard coauthored a paper that described transistors as get smaller the power density staying constant. Which results in increased speed and lower power consumption of the transistor as it is made smaller (i.e. fabricated with an advanced process node). Unfortunately starting around 2006, performance no longer increased in the same ratio to transistor size reduction as historical Dennard scaling. Hence the performance to transistor size “curve” shifted, reducing
some of the benefits of smaller transistors. So how did product companies continue to meet the expectations set by Moore’s Law as the economics of smaller transistors decreased and performance increases declined? By innovating! Key innovations were made in both transistor structure and packaging technology. The original single transistor of Shockley’s team was a pointcontact structure. This quickly changed to planar transistors built on wafers in volume in the 1950s and 60s. In the 2010s fin field-effect transistors (FinFET), with higher speed and higher current densities due to the structure, become the dominate design at the leading edge of 14 nm fabrication processes and below. And most recently, gate-all-around FET (GAAFET) structures are on company roadmaps for 5 and 3 nm devices that may ship as early as this year. And in December 2021, IBM and Samsung announced a new Vertical-Transport Field-Effect Transistor (VTFET) under development providing even greater transistor per area density. In addition to changing the shape of the transistor to reduce area and/or increase performance, some companies have stacked multiple transistors to pack more functionality in a given area. Of course, this type of stacking comes at the cost of processing additional wafer layers. Ultimately, all of the transistor-based approaches will reach a limit beyond which the size of the transistor cannot be reduced. Where exactly that limit may be is unknown. Current research by Tsinghua University (China) has demonstrated a transistor with a 0.34 nm gate – the size of a single carbon atom. Many think that single-atom monolayers will be the end of the game but the industry has been surprised before. The other key innovation is the More than Moore approach to building systems, as first described by the International Technology Roadmap for Semiconductors (ITRS) in the early 2000’s and now covered by the Heterogeneous Integration Roadmap (HIR). This includes Heterogeneous Integration (Chiplets, etc.) and other advanced packaging (2.5D, 3D, etc.) that I have written about previously. My money is on seeing a lot more innovation in these areas as the development costs are lower and the time to market is significantly faster than new transistors at ever shrinking process nodes. The second biggest impact of Moore’s Law? It created a roadmap for meptec.org