IRJET- Optimization of 1-Bit ALU using Ternary Logic

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Optimization of 1-Bit ALU using Ternary Logic A.Swetha Priya1, A.Sathish Kumar2 1Lead

Engineer, Cerium Systems, Bangalore Design Engineer, Broadcom, Bangalore ---------------------------------------------------------------------***--------------------------------------------------------------------2IC

Abstract - In this paper, we presented a novel approach for

implementation of 1-bit ALU using Ternary logic. The ternary logic or Three Valued Logic (3VL) is the next alternative approach offering several advantages over existing conventional binary digital logic. The proposed 3VL based ALU is designed for 1-bit operation and can be used for real time applications with better hardware reduction in turn minimizing the number of gates over binary logic. The 3VL based ALU is designed using CMOS ternary logic gates (TGates) for ternary based arithmetic and logical circuits which is suitable for LSI/VLSI implementation. The design can be extended to n-bit operation for real time applications. Today’s existing simulation tools do not permit the simulation of 3VL circuits. VHDL is used as a simulation tool for 3VL verification.

An objective of this study is to describe how existing 3VL system can be optimized in terms of transistors over binary logic. Ternary logic resulted in 25% reduction of transistor utility in 1-Bit ALU design when compared to binary logic.

Key Words: CMOS; T-ALU; T-Gates; Ternary logic; VHDL

1. INTRODUCTION Is it time to move beyond zeroes and ones? This very thought of Bernard Cole’s [1] article published in 2003 on the official site of the Embedded Development Community brought many researches to work upon Multi-Valued Logic to bring a new era of technology. Design of combinational and sequential circuits traditionally uses binary value. Twovalued binary logic has provided efficient two-state devices and circuits with its current status of complexity and sophistication reached mainly because of the continual development of microelectronics [1]. Interconnection problem exists as a intricate problem on both on-chip and between the chips for two-valued logic. Difficulty on chip for placement and routing (P&R) of digital logic elements increase in terms of capability per chip escalated on a complete chip. Also, silicon area used for inter connections are greater than that of the active logic elements used in the chip.

The first known classical father of logic, Aristotle found logical calculus where traditionally only two possible values (i.e., true and false) was obliged to be used for any proposition which includes or assumes the law of the excluded middle until the 20th century. Extension to mainstream formulaic two-valued logic (n = 2) called nvalued logic is brought out for n > 2 with the 20th century. As a measure of the cost or complexity of three valued circuits, the mathematical work of product of the radix and the

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number of signals has been proposed by Godel. Godel [2] has stipulated that the most efficient base for reducing the hardware in a circuitry is Euler constant (e = 2.718285...).

Since decadic 3 is the digit nearer to Euler Constant than base 2 offering great significance over the design of binary digital systems.

In fact, in reality, there is no clarity on the yes/no conditions. Real world scenarios like true/false/may be, open/close/half open or half close, yes/no/may be, left/right/straight or up/down/straight are observed conditions with uncertainty in decision making values.

Multiple decision making scenarios are encountered to understand the certainty level for the acceptance or rejection of the situations [3-7]. Unreliability-Reliability probabilistic model is as shown in Fig-1. The deterministic model explains that the reliability of the model is interpreted within the boundaries of 0≤R≤1. Vicinity of R being 0.5 could be interpreted as may be true or may be false and above 0.5 is said to be reliability level and below 0.5 is said to be unreliability level. It is interpreted to be certainly happening if R=1. And if R=0, it is interpreted to be not happening certainly.

Higher processing rates are achieved going up from unary logic level to higher logic level. Traditionally, there are many bases identified by the mankind from base-1(Unary) to base 109. As shown in Fig-2, any value apart from binary logic is called non-binary logic which is expressed in terms of nvalue and so is called Multi-Valued Logic (MVL). Higher processing levels gives advantage for memory management, communication throughput and domain specific computations. Economy of digits is an evident advantage of a ternary representation. It needs 58% more digits for binary to represent a number compared to ternary logic. These benefits have shown to be useful in the design of ternary computers, for digital filtering [8]. Ternary logic allows sign conversions. These advantages of ternary are casted in many applications in the field of Data Mining, Fuzzy logic, Machine Learning, Robotics, Artificial Intelligence, Digital signal processing, Image Processing and Digital control systems.

Mainly, Ternary is used in State Assignments and decision diagrams, error correction, error encoding and decoding, data compression and representation of discrete information, Automatic Theorem proving and in automatic telephony.

The scope of the paper is to implement the novel idea to explore the possibilities and advantages in realizing switching circuits which reduces T-gates for ALU slice.

Section 2 briefs out our preliminary study in the earlier papers on ternary logic to recognize and to bring out its

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importance. Section 3 gives the basic study of ternary logic gates. In Section 4, gives the ternary 1-bit ALU operation. The simulation of the ALU and its results is described in section 5.

Section 6 shows the advantages of ternary over binary and the conclusion is given in Section 7.

For X, Y, Z  L, there exists an equivalence (=) operation, such that X = X, If X= Y, then Y = X, If X=Y & Y=Z, then X = Z. Clearly (L, +,  ) is a distributive lattice with zero element(0 or ) and universal element(2 or ). Thus X, Y, Z  L [1-5]: Idempotent Law : X+X = X X X = X (2) Commutative Law: X+Y = Y+X X Y = Y X (3) Associative Law : (X+Y) + Z = X+(Y+Z) (4) X  (Y  Z) = (X  Y)  Z (5) Absorption Law : X+ X  Y =X X  (X+Y) = X (6) Distributive Law : X+Y  Z = (X+Y)  (X+Z) (7) X  (Y+Z) = X  Y+X  Z (8) To implement three valued logic function, unary variables are primarily selected through a Ternary decoder approach as shown in the Fig-3, which converts all the unary variables to suitable conditions of ternary variables to formulate a ternary function.

Fig -1: Implementation of ternary function

Fig -3: Implementation of ternary function a Literal is denoted by X i i , where a i = , , , is defined as given Table -1.

,

and

Table -1: Function Table of Unary Functions Fig -2: Levels of Switching Algebra and its extension to Nvalued logic

2. TERNARY SWITCHING ALGEBRA For a ternary switching algebra, a suitable set of operations ought to be selected from the set of all possible variables [1-5]. Let a system be L whose elements called propositions or statements are valued in the set { , , }. If X is a proposition, the value of X can be seen as a mapping V : L   ,  ,   such that (1) Objective of using general variables , , is to consider any type of present or future device technology and also for positive or negative logic representation. Ternary logic level ‘ ’ generally corresponds to logic-0 also called low voltage which is well defined in binary, ‘ ’ corresponds to an intermediate or uncertainty stage and ‘ ’ corresponds to logic-1 also called high voltage which is well defined in binary. The intermediate state ‘ ’ can be metaphorically thought of partially true and partially false condition.

2.1 Basic Laws of Ternary Logic

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Some expressions useful in ternary logic are: Where i = ,

(9) (10) (11) X   X   X   X  X   X   X   X  (12) X   X   X  (13) X   X   X  X   X   X  (14) X+ =X X• = (15) X+ = X• =X (16) Universally formulated De Morgan's Theorem [5] also holds good for ternary logic. Three types of inverters are used to implement De Morgan’s theorem.

X   X   X   X 

&

(17) (18) (19)  X  Y   X   Y  (20)  X  Y   X   Y  (21)  X  Y   X   Y       (22) X  X X  Y   X  Y The canonical Sum of Product (SOP) and Product of Sum (POS) Product of Sum (POS) can be written as X

X

Y 



Y 



 X  Y 

 X  Y

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f(xl,x2, ..., xn) = • g(xl,x2 ..... xn) + • h(x1,x2, ....,xn) i.e., f = g + • h

(23)

f(xl,x2, ..., xn) =( • g(xl,x2 ..... xn) ) • ( + h(x1,x2, ....,xn)) i.e., f = g • ( + h ) (24)

3. Ternary Gate Design The basic building block of ternary decoder is a general ternary inverter (GTI). A GTI is takes a unary operator with one input X and produces 3 possible outputs. The implementation of ternary inverter requires three types of inverters namely negative ternary inverter (NTI), simple ternary inverter (STI) and positive ternary inverter (PTI) forming an operator set that is complete in logic sense[6-9].

These T-inverter acts as a basic fundamental element for constructing ternary AND/NAND (T-AND/NAND), ternary OR/NOR( T-OR/NOR) and soon. Table -2 summarized the functioning of three types of ternary Inverters.

STI  X     X

Logic Sum or TOR and Logic Product or TAND:

X1  X2  … Xn =MAX ( X1, X2,…, Xn )

(27)

X1 X2  … Xn =MIN ( X1, X2,…, Xn )

(28)

Similarly, TNAND and TNOR is X1  X2  … Xn

=MIN ( X1 X2  … Xn )

(29)

(25)

X1  X2  ..  Xn =MAX ( X1  X2  ..  Xn )

(26)

In Voltage mode, logic state are specified in terms of distinct voltage levels i.e., V1, V2, V3....Vn. Voltage modes are further divided into balance modes and unbalanced modes [11]. Balanced modes are the logic states defined in terms of distinct voltage levels i.e., +V = 1(logic high), Ground = 0(intermediate state) & -V = -1(logic low). Balanced mode is more efficiently identified as standard in the industry. And based on the “N” value defined, we have these voltage levels like 1,0,-1 for ternary logic. Unbalanced modes are the logic states defined in terms of voltage levels i.,e V = 2(logic high), V/2 = 1(intermediate logic) & Ground = 0(logic low),(equivalently it is V = γ, V/2 = β & Ground = α or V =1, V/2 = z & Ground = 0). It uses non-negative numbers for representation. In Current mode [12], logic states are specified in terms of multiples of reference current states ie., xI1,xI2, xI3 .... xIn where x is reference current.

where i takes the value of for PTI and for the NTI operator. The minus sign represents arithmetic subtraction.

Symbols of Ternary Inverters are given in Fig-4.

Fig -4: Basic Ternary logic gates Table -2: Function Table For Ternary Inverter

(30)

4. Design of 1-Bit Ternary ALU Ternary OR (TOR) and Ternary AND (TAND) represent ORing (+) and ANDing (.) respectively on L in Ternary terminology. These gates are as shown in Fig-4. and basically it requires two or more multiple input operators [1-6].

Functioning of these gates are represented by following equations and are tabulated as given in Table -3.

Binary logic is restricted to only two states ‘0’ and ‘1’ whereas three-valued logics have three truth values. And so Ternary logic is also called three-valued or trivalent logic and is abbreviated to 3VL as it has three distinct voltage levels. 3VL, in general a multi-valued logic(MVL) is implemented in two modes i.e. current mode and voltage mode[10].

ALU (Arithmetic Logic Unit) which is the central execution unit of a CPU is a combinatorial circuit performing arithmetic and logical operations and its complexity keeps varying [13].

Ternary ALU (T-ALU) slice has been designed for the 1-bit ternary operations. This can be extended for n-bit operations also and can also be implemented by cascading smaller basic n/2 ALU slices as well. This proposed ALU is designed to have CMOS logic T-Gates for ternary arithmetic & logic operations which is suitable for LSI/VLSI implementation.

The design of ALU slice is shown in Fig-5 and works as per the functional Table -4. Depending on the selection line (S) and the bits X & Y, the corresponding operations will be performed by T-ALU. Arithmetic operations are as given in the Table -5.

Table -3: Truth Table For Basic Gates

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www.irjet.net A α α α β β β γ γ γ

B α β γ α β γ α β γ

Operation Addition Subtraction Multiplication Comparator -

Operation TAND TOR Ex-OR STNAND PTNAND NTNAND STNOR PTNOR NTNOR

Table – 6: 9- State Logic System[10]

Fig -5: Block diagram of 1-Bit T- ALU Slice

5. Simulator for T-ALU The performance evaluation of 3VL circuits is dealt with the use of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) as a logic simulator[10-14] which is used to model, simulate and describe tristate valued signals of a ternary systems with true, false and with a third transparent high impedance state. An effective way out to connect different distinct logic outputs with characteristics of high impedance state (Z) to a single input allowing the remaining outputs to operate in the normal binary sense can be done with VHDL. Commonly, the concept is used memory banks of computers and other similar devices to a common data bus where a large number of devices can communicate over the same channel ensuring only one to be enabled at a time.

Table -4: Functional Table of Logical Operations

Symbols U

Values Uninitialized

X 0 1 Z

Unknown Logic 0 Logic 1 High Impedance Weak unknown Weak zero Weak one Don’t care

W L H -

Fig -6: Waveforms of (a) Two-valued logic and (b) Three-valued logic

6. Total Number of Transistor Calculation For binary based two input AND & OR gate requires 4 transistors and for three input requires 6 transistors. The Binary 1-bit ALU can give only 4 different combinations of The proposed VHDL simulator is developed with technology dependent package called 9-state StdLogic_1164 package [14] whose levels are as listed in Table -6 which is used to synthesize and to verify the performance of ternary logic circuits. This VHDL permits to describe the circuits like TTL, CMOS, GaAs, NMOS, PMOS and ECL[15,16] based on the design implemented for the examination and requires a change in package development to support the design. To demonstrate the use of VHDL as a ternary logic simulator, we have used Logic Low to represent α or equivalently 0V, High impendence Z to represent β or equivalently 1V and Logic high to represent γ or equivalently 2V as shown in Fig-6. The simulation result of 1-bit T-ALU is as shown in Fig-7.

Table -5: Functional Table of T-ALU Bits

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operations like addition, subtraction, multiplication, comparator operation and a final multiplexer to select either one of the operation.

6.1 Binary Logic For addition operation, totally 6 gates are used.

No. of Inverters are 2 No. of 2 input AND & OR Gates are 4

 2*2 = 4  4*4 = 16 ----------------------Total no. of transistors with Inverters  20 transistors For subtraction operation, totally 3 gates are used.

No. of Inverters is 1  1*2 = 2 No. of 2 input AND is 1  1*4 = 4

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No. of 2 input XOR is 1

 1*8 = 8 ----------------------Total no. of transistors with Inverters  14 transistors For multiplication operation, totally 7 gates are used.

No. of Inverters is 2  2*2 = 4 No. of 2 input AND are 4  4*4 = 16 No. of 2 input OR is 1  1*4 = 4 ----------------------Total no. of transistors with Inverters  24 transistors For comparator operation, totally 5 gates are used.

No. of Inverters is 2  2*2 = 4 No. of 2 input AND are 3  3*4 = 12 ----------------------Total no. of transistors with Inverters  16 transistors For multiplexer operation, totally 9 gates are used.

No. of Inverters are 4  4*2 = 8 No. of 3 input AND are 4  4*4 = 16 No. of 4 input OR is 1  1*10 = 10 ----------------------Total no. of transistors with Inverters  34 transistors Other supporting inverters are 5 which would come totally to 118 transistors.

6.2 Ternary Logic For ternary based two input TAND and TOR gate requires 4 transistors and for three input requires 6 transistors.

For Addition (uses T- Half Adder)  4*4 = 16 For Subtraction (uses T- Half subtraction)  4*4 = 16 For Multiplication (uses T- gates)  4*4 = 16 For comparator (uses T-gates)  6*4 = 24 For multiplexer (uses T-gates)  4*4 = 16 ----------------------Total no. of transistors with Inverters  88 transistors Table -7: Ternary and Binary Logic Transistor Count Comparison for 1-Bit ALU

Table -8: Percentage of Transistor Savings For1-Bit ALU Total Number of Transistors Without Inverters With Inverters No. of wires

7. Conclusion In this paper, we developed a ALU using ternary logic with optimum hardware circuitry when compared to binary logic.

A scheme based on improved T-gate with formulated design of ALU and also simulation of 1-bit ALU slice is described in this paper. An optimization is performed to compared ternary against the binary to exhibit significance of circuit reduction in complexity, in turn reflecting in low static power consumption due to reduced hardware. Also speed of operation increases as the hardware overhead reduces in non-binary systems compared to binary systems. Moreover, proposed ALU can be easily made to implement several different functions with addition and/or modification in design and selection logic and can be made as realisable system to be incorporated as processing unit in ternary microprocessors. It will reduce the manufacturing cost and complexity and decrease the number of elements required to realize a given ternary function. This Ternary logic helped in about 25% reduction of hardware required in ALU design when compared to binary logic.

The VHDL simulator has been used to perform both synthesis and verification of Ternary logic on designs with a defined StdLogic_1164 package. To develop Ternary circuits and to verify their performance, tools for digital simulations are necessary to be developed. For layout generation and extraction corresponding software tools are not yet developed by industry. Presently it can be done manually for which mathematical foundation has been completed in this project. Further work may be carried out by larger ALU with the concept of signal co-ordination. Major advantage sought and achieved is reduction in gate count using Ternary logic.

REFERENCES

Percentage (%) Saving 19% 25% 18.1%

The total number of transistors comparison between the Ternary and Binary Logic for both 1-bit and 2-bit ALU are given in Table -7. Ternary Logic has showed that fewer numbers of transistors are required to design the ALU when compared to binary logic which as shown in Table -8.

Fig -7: The simulation result of 1-bit T-ALU

A.Sathish Kumar and A.Swetha Priya, “Minimization Of Ternary Combinational Circuits – A Survey”, International Journal Of Engineering Science and Technology (IJEST 2010), Vol. 02(8), ISSN:0975-5462, pp. 3576-3589, Aug. 2010.

[2] A. Sathish Kumar and A. Swetha Priya, “Modeling Of Combinational Circuits Based On Ternary Multiplexer Using VHDL”, International Journal On Computer Science and Engineering (IJCSE 2010), Vol. 02, No. 05, ISSN:0975-3397, pp.1777-1791, Aug. 2010.

[3] A.Sathish Kumar and A.Swetha Priya, “Modeling of Sequential Circuits Based On 3VL Flip-flops Using VHDL”, International Journal of Computer Information Systems (IJCIS 2010), Vol 1, Issue 5, ISSN 2229-5208, pp 38-47,Dec.2010.

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