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Evaluating isolation techniques in dc/dc converters Page 24

Polymer capacitors show promise as MLCC alternatives Page 35



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How to electrocute yourself in a few easy steps Here’s a fun project: Pop open an old microwave oven and scavenge the high-voltage transformer powering the cavity magnetron vacuum tube. Then use it to make yourself a Lichtenberg generator. But be sure there’s someone nearby to call an ambulance. Lichtenberg generators are used to create art and abstract objects by burning fractal patterns into various materials such as wood and acrylic. They also have a propensity to kill and maim people. The Canadian Electrical Safety Authority recently reported two incidents where a Lichtenberg generator made with microwave oven transformers killed the operator and another where the user was only saved by the quick thinking of a bystander who administered CPR. In that case, the surviving user merely had to contend with severe third-degree burns. It appears that many of these generators are homemade based on steps outlined in YouTube videos. These things generally look as dangerous as they are, consisting of not much more than the 2-kV oven transformer and a few dangling wires. And there are numerous online videos showing exactly how to disassemble microwave ovens, though one often sees warnings not to take apart these appliances because they contain toxic materials and lingering high voltage. The hazardous material is actually beryllium mixed in the ceramic that is part of the magnetron tube. Beryllium is a notorious carcinogen when inhaled. So those who are of a mind to attempt this disassembly should never cut, grind, or otherwise mess with the ceramic components in the magnetron tube. (Some YouTube oven disassembly videos point this out. Others do not.) The Canadian ESA also says you can find generators built this way being sold as commercial products, often in kit form. The problem with at least some of these kits is the aggressive marketing tactics being used to sell them. Their packaging indicates they are built with approved and certified components, but the complete generator has never been evaluated by any safety standards organization, says the ESA. You might think that serious woodworking hobbyists would be sympathetic to shenanigans involving Lichtenberg patterns. Not so. The American Association of Woodturners, whose main tool of choice is the lathe, issued a statement in 2017 condemning fractal burning. “The process known as Fractal



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Burning is prohibited from being used in any AAW-sponsored events, including regional and national symposia, and that AAW-chartered chapters are strongly urged to refrain from demonstrating or featuring the process in chapter events….. The risks from Lichtenberg burning…. are largely hidden and the standards for personal protection poorly understood. Incorrect assumptions can easily lead to injury or death,” said the organization in its statement. For those interested in creating Lichtenberg patterns without risking a lethal incident, there are alternatives. Hobbyist technology publications such as Popular Science describe a less dangerous method that involves creating Lichtenberg figures in dust using photocopier toner and a Van de Graaff generator (or even static electricity generated by shag carpeting). The result may not be as impressive as the tentaclelike patterns transformer-powered do-it-yourself generators produce, but they are much less likely to result in the operator ending up on the Darwin Award list.


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The Loss Leader (lowest)

XGL Family power inductors feature the industry’s lowest DC resistance and extremely low AC losses for a wide range of DC-DC converters Coilcraft XGL4020 Series molded power inductors are available in 14 inductance values from 0.11 to 8.2 µH, with current ratings up to 29 Amps. With up to 45% lower DCR than previous-generation products, they are the most efficient power inductors available today! Their ultra-low DCR and higher Irms also allow XGL4020 inductors to operate much

cooler than other components. XGL4020 Series inductors are qualified to AEC-Q200 Grade 1 standards (with a maximum part temperature of 165°C) and have no thermal aging issues, making them ideal for automotive and other harsh environment applications. Download the datasheet and request free samples at ®


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HOW TO ELECTROCUTE YOURSELF IN A FEW EASY STEPS BRINGING SCIENCE TO THE SELECTION OF MICA CAPACITORS FOR RF AND MICROWAVE CIRCUITS An RF modeler makes it easy to predict in-circuit S-parameters for mica capacitors used at microwave frequencies.


COMMON MISCONCEPTIONS ABOUT THE BODY DIODE Engineers who design power circuits around wide-bandgap semiconductors frequently make costly mistakes that relate to the switching behavior of transistors.

16 20 24

KEYS TO UNDERSTANDING RESISTOR SPECS The specification process for resistors involves more than just allowing for tolerance bands. Voltage, power, and temperature ratings can interact in ways that can degrade circuit reliability.

HOW TO MAKE DC/DC CONVERTERS RUGGED Design standards for rail transportation equipment are so severe that they are used as qualifications for products targeting other areas where ruggedness comes in handy. Here’s a quick overview of what these standards entail.

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WHY IT’S TOUGH TO CHARACTERIZE SiC POWER MOSFETs Switching transients and parasitics can combine to thwart the accurate measurement of important MOSFET operating parameters.

DON’T BE CONFUSED BY LINE AND NEUTRAL FUSES It pays to know when the use of a single fuse is less hazardous than fusing both hot and neutral wires.

POLYMER CAPACITORS SHOW PROMISE AS MLCC ALTERNATIVES It pays to know how different capacitor technologies behave when shortages force a search for good substitutes.





New ways of routing power around circuit boards bring more efficiency and fewer thermal problems.

SiC FETs now include measures aimed at keeping losses down while managing fast switching waveforms.

EVALUATING ISOLATION TECHNIQUES IN DC/DC CONVERTERS Different isolation methods give different results. It’s important to know what to expect from converters that separate their input and output in a specific way. |

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Bringing science to the selection of mica capacitors for RF and microwave circuits An RF modeler makes it easy to predict in-circuit S-parameters for mica capacitors used at microwave frequencies.

The choice of capacitor can particularly impact the performance of circuits handling RF and microwave frequencies. Specifying passive components operating in this region can seem more like art than science. Fortunately, new online tools can help simplify the process. For no-fail circuits that must maintain their performance, there is no better dielectric choice than mica. Originally invented by Cornell Dubilier (CDE), mica capacitors offer important advantages over MLCCs and porcelain capacitors. These benefits include high Q, stability, and reliability.

MC Series mica chip capacitors.



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Sam G. Parler, Jr., P.E. | Cornell Dubilier

Capacitors with a mica dielectric have significantly higher Q than other capacitors partly because of ESR (equivalent series resistance) that is 10 to 20% lower. Lower ESR also leads to lower losses, less self-heating, and the ability to tolerate higher currents. Mica capacitors are incredibly stable over time, temperature, frequency, and voltage, proving consistent performance even with varying operating conditions. Because mica is a strong mineral, capacitors constructed with it aren’t prone to cracking.  So mica capacitors handle higher voltages on larger chip sizes and work in applications subject to mechanical stresses that could destroy other capacitors. And mica capacitors tend to handle high-voltage spikes better than their ceramic counterparts. An online tool called the RF Mica Modeler provides an interactive console to assist in selecting the best mica capacitor within a capacitance range of 0.5 to 91,000 pF and voltage range of 100 to 4,000 V, targeting applications in the frequency range of 1 kHz to 4 GHz. The modeler charts estimates of the 10 • 2019

high-frequency electrical performance for three major classes of CDE circuitboard-mounted mica capacitors: leaded mica capacitors used in through-hole PCBs, surface-mounted metal case mica/ PTFE capacitors style MIN02 (5 X 5-mm footprint) and MCM01 (10×12 mm) for high current and high power-handling SMT mica chip capacitors in sizes 0805, 1210, 1812 and 2220. With one of the three package styles selected from the “Package Style” drop-down box, the “CDE Part Number” selection box lists standard catalog part numbers ranked by their capacitance value. Selecting a part number brings up an outline drawing and the physical dimensions. Also appearing is blue “CATALOG” text that is context sensitive. It will open a new tab in your browser with the datasheets for the selected package style (leaded, chip, metal case). The tool can model the S-parameters for the capacitor mounted on a test circuit transmission line, in either series or shunt (parallel) configuration, chosen in the dropdown box in the lower left of the modeler. The tool plots the capacitor’s |

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Selecting a package style

The Package Style selection dropdown in the modeler.

scattering parameters, de-embedded to the capacitor terminals as two reference planes, at which the capacitor terminals extend from the body. These would typically be soldered to circuit board traces on a length of transmission line with 50-Ω characteristic impedance. When configured as the test circuit for the capacitor, such a line would be driven at one end of the line by a sinusoidal energy source with a purely resistive source impedance of 50 Ω. The capacitor would mount in the physical center of the line. The other, unexcited end of the line is a second test port terminated with a purely resistive load impedance of 50 Ω to prevent reflections. The capacitor on such a transmission line can either mount in series with one interrupted conductor on the lines (known as series connection) or it can mount across the line (a shunt connection). In both connection schemes, the capacitor is assumed to mount symmetrically and equidistant with respect to the two ports (known as a “reciprocal” mounting scheme). Consequently, S21 is precisely equal to S12, and S11 is exactly equal to S22. If there is inductance in series with the capacitor connection (as arises from a lead or trace length included in the model for the capacitor), a “Circuit Inductance” slider control can include its effects on the displayed and modeled parametric curves. This additional inductance is added to the capacitor’s internal inductance (ESL) and affects the resonant frequency as well as the impedance and S-parameter plots. It also affects the output files, and this inductance value— if nonzero— is in the header field of the output file for documentation purposes. It does not affect the maximum RMS current plot.

Capacitor characteristics

INTERACTIVE CHARTS The modeler creates six charts for the selected capacitor. A mouse hover over the curve reveals the exact frequency and parameter value. When two or more curves are close to the point of interest, the rectangular border around the displayed coordinates takes on the color of the legend of the series to which you are pointing. |

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The modeler creates six charts for the selected capacitor. These charts are for an SMT chip device.

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Specifying heat sink thermal resistance

Theta slider control for metal-case style chip devices.

In the left column, the top chart plots the estimated, typical capacitance versus frequency for three temperatures. The nominal capacitance at the applicable test frequency serves as the base capacitance value; and obviously, the device tolerance would be applicable to actual capacitors. The temperature and frequency coefficients assumed by the modeler are typical values but are not warranted. Below the capacitance chart sits a plot of the typical impedance magnitude and series resistance. At the device’s resonant frequency, the apex of actual impedance magnitude curve will always touch the ESR curve. Note that the limited number of data points in the modeler plot for high-Q mica capacitors means this contact point will sometimes not be precisely resolved. The bottom-left chart is a plot of the capacitor Q, which is the ratio of the reactance to the resistance. Q is the multiplicative inverse of D, the dissipation factor, which can be visualized from the logarithmic Q chart by mentally reflecting it about the horizontal line with the ordinate value of Q=D=1. In the right column, the top plot graphs an estimate of the maximum expected RMS current handling at three ambient temperatures, assuming the capacitor sits on a typical PCB at the ambient temperature in natural convection. However, we recommend the current be derated and the capacitor be tested under worst-case conditions for qualification purposes. For package styles other than the SMT metal case, the software calculates RMS current ratings based upon the estimated ESR and at a maximum core heat rise of 60 °C, limited to a 125 °C maximum core temperature when mounted to a PCB in natural, free convection. For the SMT metal case styles, the maximum RMS current handling calculation assumes a maximum allowable heat rise above ambient of 120 °C and is also limited to a 185 °C maximum core temperature. The default thermal resistance of 50 °C/W is for natural convection without a heatsink or a large heat spreader. The Heatsink Thermal Resistance to Ambient Slider Control can be dragged left to select a much lower heatsink-to-ambient thermal resistance, even as low as 1 °C/W, possible only via an exotic heatsink such as liquid-cooled copper.



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An aggressive heatsink below 10 °C/W will greatly affect the joule-heating-limited current handling capabilities at higher frequencies. Because of limitations of the current-carrying capacity of the device tabs, the current in all cases is limited to 25 A rms. The middle chart in the right column is a plot of the real and imaginary components of S-parameter S11, which is identical to S22 due to the capacitor’s assumed symmetric mounting scheme. The final chart in the lower right is a plot of the real and imaginary components of S-parameter S21, which is identical to S12. For the metal-case style only, a slider tool immediately above the current ratings chart helps specify a value of the heatsink’s thermal resistance to ambient, as these capacitors are intended for heatsink attachment or to be soldered on a copper heat spreader. The lower frequency span is chosen to cover the frequency at which the capacitance and ESR limits are tested, 1 kHz for capacitors rated 1,000 pF and above and 1 MHz for capacitors rated less than 1,000 pF. Sometimes capacitors rated as low as 10 pF are used at frequencies below 1 MHz, so the lowest plotted frequency is 100 kHz instead of 1 MHz in the range of 10 to 999 pF. The upper-frequency range is chosen to cover the lower of 6 GHz and a small integer multiple of the first resonant frequency. The multiple is limited by the electrical size of the capacitor as well as the possibility of circulating currents caused by an imbalance of the conductor geometry within the capacitor. Note that above the maximum plotted frequency, there may be notches in the impedance magnitude and upward spikes in the series resistance caused by internally circulating currents. For CDE leaded mica capacitors, part numbers beginning with CMR will generally have better performance in this regard. And Cornell Dubilier’s mica design engineering department may be able to create a higher-performance capacitor to more effectively address special cases. Site users can generate an output of the model as a frequency listing with Z-parameter or S-parameter values. First select the desired output format in the “Output Format” dropdown box, including the capacitor core temperature. Then click |

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Output format drop-down list Users who generate an output of the model as a listing of Z- or S-parameter values do so by selecting the desired output format in the “Output Format” drop-down box at left, including the capacitor core temperature, then clicking the Generate Model Output button.

the Generate Model Output button. Note the output format in the popup window will be in space-delimited Touchstone format per the version 1.0 standard. The S-parameter output is 2-port .s2p with a reference impedance of 50 Ω. For the Z-parameters, the format still complies with the Touchstone 1.0 standard but is single-port with the reference impedance set to 1 Ω, so the resistance and reactance in ohms are listed without the need to apply a factor of 50. The data listing appears in a popup window. The window itself does not by default store to your hard drive or cloud storage path. Probably the best way to store it as a text or .s2p file is simply copy text from the window and paste it into a text editor for import into an RF modeler, plotting in a spreadsheet, etc. The data is the same as that visible in the corresponding modeler charts, reflecting a logarithmic frequency spacing of 100 points per decade, which is a 2.4% pointto-point frequency increment. This RF modeler is based on mathematical models of the physical construction of the capacitors, crosschecked with a limited amount of roomtemperature vector network analyzer data. Also, note there is little or no conservatism built into the applet. The typical ESR is not a maximum ESR limit, |

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and the maximum rms current is not a warranted life-test condition. And the applet is only valid for Cornell Dubilier capacitors, as their construction and qualities are unique. It’s best to verify performance and discuss application requirements, such as minimum lifetime, with RF Mica application engineers. Finally, here’s a legal disclaimer: The CDE RF Mica Capacitor Modeler is not a contract, license, or authorization of any kind. Specifications and model are subject to change without notice. Cornell Dubilier assumes no liability on accuracy, completeness or suitability for any application.

REFERENCES The Modeler, no registration required: MicaModeler01.html CDE Mica Capacitors: capacitors/mica

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Common misconceptions about the body diode Julian Styles | GaN Systems

Engineers who design power circuits around wide-bandgap semiconductors frequently make costly mistakes that relate to the switching behavior of transistors.

GaN reverse I/V curve

We need to face an awkward and embarrassing truth about ourselves in the world of power electronics. I’d like to ask you to try to be completely open and

Are you mistaken about the body diode? Many engineers are. We all have similar origin stories about how this confusion started. MOSFETs have an extremely useful property; that is, when VGS=0, they still conduct in reverse. They do this because they have a parasitic diode between source and drain called an intrinsic body diode. When learning power electronics, we all discovered that MOSFETs can conduct in reverse (because they have a body diode) and IGBTs can’t (because they don’t). Because “reverse current path with gate off” is kind of a mouthful, we all got accustomed to just referring to this effect as a “body diode.” And everything was fine, for decades. Then new widebandgap devices came along. Because of their construction, some don’t have parasitic diodes. But they still have the same useful property as MOSFETs: They conduct in reverse when VGS=0. Most notably, GaN E-HEMTs have this property. And so the confusion began.



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Id (A)

honest for a moment.

Vds (V) A diagram from the GaN Systems’ application note GN001 shows IR curves for different values of VGS. |

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THE BODY DIODE Half bridge turn-on 400V/20A - SJ MOSFET

Si MOSFET QRR loss dominates 6670uJ!

Half bridge turn-on 400V/20A - GaN E-HEMT

Snappy recovery: 1. High dlRR/dt, parasitic ringing 2. Body diode ruggedness

GaN EON = 92 μ J

Qoss loss only: 1. Much lower turn-on loss 2. No snappy recovery and uncontrolled high dlRR/dt 3. Clean waveforms

Switching waveforms of a typical MOSFET and E-HEMT illustrate some of the differences in turn-on behavior caused by the body diode. My colleagues and I have had many, many meetings with engineers who assume that, because GaN devices do not have body diodes, they do not conduct in reverse. We’ve had countless conversations similar to this one: Engineer: “So GaN Devices don’t have a body diode?” Me: “Correct.” Engineer: “So they can’t conduct in reverse with VGS off? So I need to add an anti-parallel diode?” Me: “Incorrect.” Cue engineer’s head exploding. It is time we update our terminology so we can accurately refer to the reverse conduction path, understand why body diodes are not necessary for this feature, and even appreciate the benefits that GaN devices bring to the world by having no body diode.

WHAT’S ACTUALLY GOING ON In GaN E-HEMTs, a lateral two-dimensional electron gas (2DEG) channel formed on an AlGaN/GaN hetero-epitaxy structure provides extremely high charge density and mobility. For enhancement-mode operation, a gate intrinsically depletes the 2DEG underneath the gate electrode at 0 V, or negative bias. A positive gate bias draws electrons into the depleted area and turns on the 2DEG channel. In forward conduction (first quadrant), this behavior works much like that of a MOSFET but with better switching performance. In the third quadrant, (VGS =0, VDS negative), the device behaves differently than a MOSFET. In simple terms, the negative bias on the drain terminal creates a voltage gradient in the device channel. This, in turn, causes the depletion region under the gate to have a negative electrical potential relative to the gate electrode. |

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In other words, the drain of GaN HEMT will behave as the source and the source will act as the drain. Once the potential difference between the gate and the channel exceeds the threshold voltage (VTH_GD) of the device, the device turns on, an effect sometimes called “self-commutation.” Because the device is conducting current, I, through its (resistive) channel, Ron, the voltage drop D is D = VTH_GD + IRon. If the device is turned off with a negative voltage, the drain must be more negative before self-commutation arises, and the total voltage drop DT is DT = VTH_GD + (-VGS) + IRon. Confession time. GaN device manufacturers have had a role in perpetuating our misunderstanding of the reverse conduction path. Over the years, GaN manufacturers have taken two main approaches to explain how their devices behave when reverse biased with VGS=0. First, some manufacturers simply kept using the term “body diode.” They explained that GaN devices have a magical body diode with zero QRR (reverse recovery charge) and a surprisingly high voltage drop. This is not true, but rather a convenient fiction that allows designers to design successful circuits most of the time. Second, some manufacturers publish detailed documentation of their device’s behavior with the expectation that engineers would carefully read the manual, realize the potential for error, and change their ways before considering the technology – a commendably honest approach, yet perhaps overlooking that engineers are human beings, and ingrained habits are difficult to change. As you might expect, the outcome of these approaches is confusion. To this day, GaN Systems’ field application engineers see customer design schematics that show our devices with added antiparallel diodes to provide a freewheeling current path. 10 • 2019



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Drain Reverse current path

Drain Reverse current path



Gate C GS Source • • • •


Parasitic body diode dv/dt failure High reverse recovery charge Qrr Not ideal for half bridge hard-switching

• • • • •

BENEFITS OF NO BODY DIODE It’s a shame that this misunderstanding of GaN devices’ lack of a body diode persists. After all, there are some real benefits to reverse conduction without a body diode. First, no body diode means no QRR, making GaN suitable for half-bridge hard switching. This, in turn, means no additional hard commutation due to the diode reverse recovery, which otherwise leads to much higher switching losses. The zero reverserecovery of GaN also enables new highefficiency topologies such as bridgeless totem pole PFC (power factor control). Second, the absence of a body diode means no burst of diode noise when the body diode turns on. This makes EMI design simpler and boosts performance. It is especially helpful in compact designs where power conversion and signal processing are on the same small PCB. Finally, there are benefits in dv/dt limits and reliability. MOSFETs have a failure mechanism caused by high dv/dt on the MOSFET body diode. While the body diode is in reverse recovery, its drain-source voltage rises. This behavior can cause a false turn-on of the internal parasitic NPN bipolar transistor, destroying the MOSFET. There is really only one disadvantage of having no body diode: higher reverse



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The differences between reverse conduction in MOSFETs and GaN HEMTs.

No parasitic BJT and body diode High dv.dt ruggedness Zero reverse recovery 2DEG can conduct in reverse, no need for anti-parallel diode Fit for half bridge hard & soft switching

voltage drop. The reverse voltage drop of a GaN E-HEMT includes a resistive element arising from the channel resistance and threshold voltage. The voltage drop in a 650-V GaN E-HEMT can be as much as 3 V when conducting large currents, larger than the equivalent drop in a MOSFET. This higher reverse voltage drop has the potential to reduce efficiency by increasing losses in the dead time of a typical half-bridge circuit. Fortunately, these losses can be reduced by shortening the dead time. The fast switching behavior of GaN E-HEMTs usually simplifies the task of shortening the dead time. In addition, embedded packages for GaN devices, such as GaN Systems GaNPx package, have low parasitic inductance, which ensures reliable switching transitions with shortened dead time. Generally, GaN circuit implementations see an efficiency gain from shortening dead time that significantly outweighs the losses from higher reverse voltage drop. It is easier to realize this efficiency gain as new-generation drivers and controllers increasingly support shorter dead times. It’s also worth noting that a short dead time is good for other reasons. For example, in Class D audio amplifiers, a shorter dead time leads to lower harmonic distortion and higher audio quality. 10 • 2019

There is a lot of help available for those who want to shake off the stigma of body-diode-wrongness and create designs optimized for efficiency and low cost. We can always create T-shirts with slogans like, “I ain’t got no body (diode)” and “Ask me about reverse conduction.” Joking aside, a better understanding about the facts regarding the body diode and a clear explanation of how GaN devices operate help clear up confusion, at least until the next evolution of power devices trigger a new set of definitions.

REFERENCES Design/ High side driver considerations, application-notes/ Recommended GaN driver/controller ICs, uploads/2018/04/GN001-Design_with_ GaN_EHEMT_180412.pdf Design examples, https://gansystems. com/design-center/ FAQ page, |

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Keys to understanding resistor specs Kory Schroeder Stackpole Electronics, Inc.

Although not a complex component, resistors have specifications that can be confusing, misleading, and misinterpreted. When specifying performance qualities, it is important to review

The specification process for resistors involves more than just allowing for tolerance bands. Voltage, power, and temperature ratings can interact in ways that can degrade circuit reliability.

and understand the resistor test conditions to properly interpret and apply the results to your design. There are potentially significant differences in data presented by resistor manufacturers and those differences can significantly affect performance.

POWER AND VOLTAGE RATINGS The power rating and voltage rating of a resistor are one common source of confusion. Simply put, the power rating is the amount of energy the resistor can dissipate in a given time at the designated ambient temperature. Manufacturers typically list multiple voltage ratings on a datasheet, but most often the primary concern is the maximum working voltage. Maximum working voltage is the maximum amount of voltage the resistor can withstand constantly without arcing. Maximum working voltage is often expressed as Vrms. It is critical to adhere to both the power rating and the maximum working voltage rating to avoid reliability problems. For example, if a 10-Ω 0402 chip resistor was subjected to the maximum working voltage of 50 V, the resulting power through the part would be 250 W. This far exceeds the resistor power rating. Conversely, for high resistance values, the amount of electrical energy that the 0402 resistor can withstand is determined by the working voltage rating of 50 V. If a 20-MΩ 0402 was subjected to the maximum power of 0.063 W, the voltage implied across the part would be 1,122 V, which surpasses the part’s voltage handling ability. Only at exactly 39.68 KΩ can the 0402 resistor handle both 50 V and 0.063 W simultaneously. This value is known as the “critical resistance value”.



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RESISTOR SPECS Power/voltage vs. resistance Power (W)

Voltage (V)


Power/voltage vs. resistance for a general-purpose thick-film standard power resistor (RMCF). Only at exactly 39.68 KΩ can the 0402 resistor handle both 50 V and 0.063 W simultaneously. This value is known as the critical resistance value.




1 ohm

39.68K Resistance (ohms)

Another aspect of the power rating is the temperature at which heat dissipation is measured. Many resistors are rated at temperatures of at least 70°C. This means the part can handle the designated power rating provided the ambient temperature around the part does not exceed 70°C. However, there are some higher power resistors that are only rated for full power operation up to 25°C. These power resistors typically require some type of external heat removal to operate at full rated power. Performance specs provide information about how a resistor behaves in a test or a set of tests. Engineers will regularly use this information to compare parts from different manufacturers. For a resistor series tested to a common standard such as AEC-Q200, it is relatively easy to compare performance.

Example: Resistor derating curve 100

Power ratio (%)

80 60

However, designers may need additional information even about AEC-compliant resistors. Some manufacturers will claim compliance with AEC (Automotive Electronics Council) testing and even provide all supporting data from AEC tests, but only carried out for small sample sizes. In some cases, these data files only show testing for 10 pieces or even fewer of each size, and in some cases, they may only show results for a single resistance value. Most AEC tests require at least 77 pieces from three distinctly different manufacturing lots in three different resistance values per size; they also spell out high, low, and critical resistance value (or as close as the nearest standard resistance value can come). Both test conditions and the way in which test results are stated can vary widely when common test standards are not followed. These variations can lead to misleading performance statements. For example, nichrome-based thin-film resistors are susceptible to moisture corrosion. Some manufacturers will tout their nichrome elements as having superior moisture resistance, citing extremely low resistance shifts to biased humidity testing. The load or bias on the resistor is a critical factor during testing. At full rated power, most resistors will generate enough heat to prevent moisture from condensing on the part, giving the appearance of











20M ohm


This example of a resister derating curve shows that if the associated part is to be used at 70°C, the power rating must be reduced to roughly 65% of its full value. Operating this part at full power and elevated temperature will lead to excessive resistance shifts and a potential failure of the resistor.

Case temperature |

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POWER & ENERGY EFFICIENCY HANDBOOK Performance Characteristics Test

Test specifications

Test conditions (JIS-C 5202)

Short time overload

±(2% + 0.1Ω)

2.5χ rated voltage for 5 sec.

Dielectric withstanding voltage

±(1% + 0.05Ω)

100 VAC, 1 minute

Resistance to soldering heat


260°C ± 5°C, for 10 sec. ± 0.5 sec. (solder bath)


95% coverage, minimum

235°C ± 5°C, for 2 sec. ± 0.5 sec. (Colophonium flux)

Temperature cycle

±(1% + 0.05Ω) Jumper (<0.05Ω)

-65°C: 30 min. 25°C: 2 to 3 min. 155°C: 30 min. 25°C: 2 to 3 min. (5 cycles)

Endurance (damp load)

±(3% + 0.1Ω) Jumper (<0.05Ω)

40°C ± 2°C 90% RH, rated load 90 min. on, 30 min. off for 1,000 hrs. -0hrs/+48 hrs.

Endurance (rated load)

±(3% + 0.1Ω) Jumper (<0.05Ω)

70°C ± 2°C, rated load 90 min. on, 30 min. off for 1,000 hrs. -0hrs/+48 hrs.

Voltage coefficient

±100 (ppm/V)

1/10 rated voltage for 3 sec. max. then rated voltage for 3 sec. max.

Robustness of termination

±(1% + 0.05Ω)

Bend of 3 mm for 5±1 sec.

robust moisture resistance. But in many applications, precision nichrome thin-film resistors will only see a fraction of their rated power. In these cases, the part will generate little heat, boosting the possibility of moisture condensing and collecting on the part. The resistance shift could be significantly different in the presence of a lower bias such as 10% rated power. Thus the test conditions are critical to understanding the results and ultimately to predicting resistor performance. Another frequently asked question is how to interpret the accumulated variation or tolerance stack-ups from the different potential sources of fluctuations. Adding the maximum potential shift from all the relevant tests provides the maximum expected resistance shift or worst-case scenario. In practice, use of worst-case figures is unnecessarily conservative for most applications. It may result in selecting a resistor with a high price tag and needlessly tight tolerance or low TCR. It is important to remember that each performance test is independent. Some tests will typically have a positive shift in resistance, and some will typically have a negative shift in resistance. In addition, test performance



Stackpole — P&EE HB 10-19.indd 18

An example of resistor performance characteristics. Note that these are not AEC-Q200 tests. typically differs from one resistor technology to the next. In most cases, the It’s also important to determine what actual resistance shift seen in the circuit is tests are relevant to the application. Test much less than the sum of the individual test conditions should be the same as what the tolerances. It is advisable to contact the resistor will actually see, and test results must resistor manufacturer about specific stability be properly interpreted. Ditto for whether requirements over the life of a given circuit for test results give actual maximum possible a resistor or series of resistors. shifts or typical performance. It is also important to understand Finally, the accumulated variance or whether the change in resistance shown in worst-case scenario does not consider the the performance specs is typical performance distribution of the individual, independent or the absolute maximum limit. Some variables. Overlooking this fact can lead to manufacturers will show typical results and an unnecessarily constraining design and not state limits explicitly unless customers would make typical commodity resistors specifically ask. Typical results are usually impractical to use. Whenever there is a two to three times better than the actual test question about how well a resistor suits a specification. This practice creates the false design, it’s best to have factory engineers impression that the part is better than other examine the design details to help make the similar products when the actual performance best choice. is no better and, in some cases, worse. In a nutshell, designs must not violate REFERENCES resistor power or voltage ratings; these Stackpole Electronics, Inc., are resistance-dependent parameters. Power ratings must be reconciled with the operating temperature. If the circuit operates at temperatures exceeding the resistor’s rated temperature, resistor power handling must be derated appropriately. 10 • 2019 |

10/10/19 8:43 AM

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How to make dc/dc converters rugged Martin Tenhumberg | Traco Power

Design standards for rail transportation equipment are so severe that they are used as qualifications for products targeting other areas where ruggedness comes in handy. Here’s a quick overview of what these standards entail.

Sizing up EMC threats

In transportation, there is an emphasis on electronic systems in rail because of expanding safety, telemetry and infotainment systems. The move away from fossil fuels to electric drives also adds further opportunities for electronic control. By the nature of the application, electronic systems in trains are powered from a relatively noisy dc source. Voltage spikes, surges and drop-outs are common, along with radiated and conducted EMI from the highpower transmission systems. Shock and vibration are a constant stress and temperature extremes and swings are normal. The safety of passengers and staff is also of utmost concern. Designers must further consider the flammability of the materials used as well as the smoke and gas emissions that may result. Other markets face many of the same challenges. Industrial mobile systems, such as construction and material handling machinery and forklift trucks, also see harsh outdoor conditions. Similar requirements apply to equipment for protection and recovery services such as police and fire, snowplows, and electric vehicle charging stations. With no clear standards of their own, applications in these markets typically turn to existing, ruggedized equipment already designed and built to railway standards.



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+ Battery -

DC-DC Converter

Area C + 5V Signal processing area protected 0V against EM interferenece

Area B Pheripheral electronic area partly protected against EM Area A interference Inside vehicle with sources of major EM interference

Typical positioning of a DC/DC converter between EMC areas in a rail application. EN 50155 provides an example of physical EMC areas A, B and C in rail applications that guide system designers toward the appropriate level of EMI filtering. |

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RUGGED CONVERTERS Operating input voltage range for rail converters Converter series 110VDC Nom

72VDC Nom DC input ranges for different rail applications. 24VDC Nom

Brownout range 100 ms

The conditions in such systems may be too much for standard industrial electronics which are often simply commercial grade devices with support for an extended temperature range. They are built with an underlying assumption that their supply rails will be ‘clean’ and that shock and vibration levels will be low. The rail environment, although harsh, has well defined qualities. Historically, when rail electrical equipment consisted of simple signaling, control, heating, and lighting, power rails were not filtered heavily. The equipment was expected to simply tolerate variations. Today the situation has improved. One standard, EN 61373, defines the sometimes-harsh shock and vibration environment for different prescribed areas within the train. Other generic standards, such as the EN 61000-4 series for EMC, are also often referenced. Finally, compliance with the British Railway Industries Association standard RIA 12 is often required, including its severe, high energy surges.

Continuous range

Input voltage

Surge range 1 sec

EN 50155 is the basis standard for railway electronics, meaning it calls up EN 61000-4, EN 61373, and others. It also applies for most other ruggedized dc/dc converter applications. It defines environmental and service conditions, reliability expectations, safety, design and construction methods. It also covers documentation and testing. Typical industrial-grade electronics might meet the general requirements, but dc/dc power converters must withstand much wider input voltage variation with several possible nominal values. The variations around each nominal can be summarized as follows: Continuous range = 0.7 – 1.25 x VNOM Brownout = 0.6 x VNOM for 100 msec Surge = 1.4 x VNOM for one second It is typically not practical to ride through brownouts for 100 msec, and surges of one second have too much energy to clamp. Power converters must therefore operate over the complete range with some safety margin. In practice, this means an input range of more than 2.33:1. Nominal voltages of 48 V and 96 V are also possible, with other French and US ranges having different minimums and maximums. The dc/dc converter manufacturers meet these requirements by offering converters with wider 4:1 input ranges (typically 43 – 160 V) to cover the majority of applications. Higher voltage, short-duration surges and transients are also specified according to EN 50121-3-2, derived from the basic standard EN61000-4. Fast transients are ±2 kV with rise and fall times of 5/50 nsec

Vibration test setup at the Traco Power Solutions laboratory in Wexford, Ireland. A vibration exciter (also known as a shaker) coupled with a stroboscope makes it is possible to evaluate the movement of individual components to help detect potential mechanical weaknesses during the development process. |

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Typical dc/dc converters from Traco Power suitable for rail and similar applications ranging from 3 to 300 W.




and repetition rate of 5 kHz. Surges are ±2 kV line-to-ground and ±1 kV line-to-line with rise and fall times of 1.2/50 µsec from a defined source impedance, ac coupled. There also may be contractual requirements to meet extended or different specifications, such as RIA 12. This standard requires immunity to surges of up to 1.5 x VNOM for one second and 3.5 x VNOM for 20 msec from a low source impedance of 0.2 Ω. For a 110 Vdc nominal system, this is a peak of 385 Vdc. This level lies outside the normal range of a converter, especially if it must work down to the 66 Vdc brownout minimum. The energy available from such a lowimpedance source means that the voltage cannot be clamped by a transient voltage suppressor (TVS). Depending on the power level, either a pre-regulator on the supply input or a circuit must switch off the input for the duration of the surge. Hold-up in the dc/dc converter must maintain the output during this period. Another requirement, also from RIA 12, is that the supply withstand fast transients of up to 8.4 kV with a trapezoidal waveform spanning 100 nsec from a 100Ω source impedance. These levels are relatively low energy and can be clamped effectively with a TVS diode or proprietary filters from dc/dc converter manufacturers.



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EMI AND ELECTROSTATIC DISCHARGE REQUIREMENTS The EN-61000-4 series is normally encountered as a standard for testing compliance with the EMC directive for ac input power supplies, all of which must have appropriate filtering. Industrial dc/ dc converters, however, are normally embedded in electronics and protected from supply-borne conducted EMI. Moreover, dc/dc converters require additional external filter networks because they do not normally include filtering suitable for direct connection to dc rails. EN 50121-3-2 also spells out requirements for immunity to conducted common-mode RF up to 80 MHz and immunity to electrostatic discharge and electromagnetic fields at the enclosure-port level. Conducted emissions follow the requirements of the basic standard EN 55016-2-1. Railway shock and vibration requirements are tough. EN 61373 defines the shock and vibration tests for rail applications. This standard specifies different categories of locations with rising levels of test severity: Category 1, Class A, Body mounted Category 1 Class B, Body mounted Category 2, Bogie Mounted Category 3, Axle mounted 10 • 2019

As an example, low-mass items in Class B body-mounted equipment must withstand vibration accelerations of 5.72 m/s2 in the vertical direction at test frequencies between 5 and 150 Hz, with longitudinal shocks peaking at 50 m/s2 (almost 5 g). In the most severe axle-mounted environment, equipment must withstand vibration up to 144 m/s2 (nearly 15 g) and shocks of more than 100 g in any direction. Operational conditions and more severe long-life stress levels are defined for different mounting orientations. Again, power modules not built to be rugged are unlikely to be adequate. At low power, dc/ dc converters housed in SIP-style packages don’t have enough mechanical support. For this reason, the TMR 3WIR and other similar products employ offset mounting pins that – along with encapsulation -- provide additional mechanical stability. Larger devices such as the TEQ 300WIR series combat the effects of vibration through the use of spring clamps on the cable connectors, ensuring a stable and longlasting connection.

TEMPERATURE SHOCK AND FIRE SAFETY Rail applications don’t normally see severe operating temperatures with passenger and cab areas expected to lie at 25°C nominal, rising to 55°C. Equipment cubicles may be at 70°C but, in all cases, equipment must survive an extra 15°C for 10 minutes. Thanks to the optimal design of integrated heatsinks, solutions such as the TEP 150WI and TEQ 300WIR fulfil these cooling requirements. At first glance, power converters rated for -40 to +85°C seem adequate for most encountered temperatures. Thermal shock, however, is also a consideration. Thermal shock replicates a train or other vehicle entering and leaving a tunnel or building where it may experience 40°C differences at 3°C/sec rates-of-change. This temperature shock may cause sudden condensation. |

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Passive heat sinks on the TEQ 300WIR dc/dc converters dissipate heat so there’s no need for additional cooling.

Left, additional offset mounting pins on the TMR 3WIR dc/dc converter provide additional mechanical stability. Right, spring clamps secure cables to help provide connections that won’t loosen from vibration.

Power converters for such environments require encapsulation or conformal coating with special precautions against damage from differential expansion rates and thermal shock. The use of nickel-plating, as opposed to gold, for the TEN 40WIR series of dc/dc converters protects against the corrosion that can result from repeated exposure to condensation. To promote passenger safety in the event of a fire, the materials used in dc/dc converters must also conform to EN 45545-2. The material requirements come from different hazard levels (HL) defined by EN 45545-1:2013. Hazard levels are determined from a combination of the vehicle’s construction and utilization category. Other parts of the EN 45545-2 standard, such as R26 for small electronic products, may also dictate additional product requirements. Tests for oxygen index, flue gas density, and smoke toxicity measure how the product compares to the requirements. The ultimate goal is to minimize the likelihood of a fire and, should one occur, limit its impact on passengers and staff in getting to safety unaided. Traco Power has addressed the rail requirements with a wide range of off-the-shelf products. Power ratings are from 3 to 300 W. The PCB-mounted versions support 11 ranges of power and the chassis-mounted units provide nine power ranges. All offer a 4:1 input range with variants that include 43-160 Vdc for 110 Vdc nominal as well as 9-36 Vdc and 18-75 Vdc for 24 and 48 Vdc |

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nominals. Packages include metal-can SIP8 in 3 and 6-W variants with additional mounting tabs for vibration-proofing; 8 W in a DIP24 package; and industry standard 1x1-in and 2x1-in types for ratings of 10 through 40 W. Chassis-mounted versions are also available from 20 to 300 W. Depending on the model, the converters include input filtering to EN 55032 class B level and feature the ruggedizing and environmental sealing required for rail and similar applications.

REFERENCES SCI study forecasts upturn in global rail market, https://www. Traco Power, TRACO POWER - Railway Power Solutions Portfolio, catalogue/PP2019-Railway-web.pdf

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Evaluating isolation techniques in dc/dc converters

Steve Roberts | Recom Power

Different isolation methods give different results. It’s important to know what to expect from converters that separate their input and output in a specific way.

Isolation in dc/dc converters has numerous uses besides just protection against electric shock. There are various grades of isolation that low-power dc/dc converters implement in different ways. Many dc/dc converters use an internal transformer to electrically (galvanically) separate the output from the input. This separation makes dc/dc converters versatile. Outputs that float with respect to the input prevent ground loops and reduce the potential for noise in electrical systems. Moreover, the output polarity

The RECOM RP-xxxx series uses potted-core transformer construction to offer 5.2 kVdc isolation test voltage rating in a compact SIP7 package (19.6 x 10.2 x 7 mm). This makes the RP series one of the most reliable high-isolation dc/ dc converters in the RECOM portfolio, used in demanding applications ranging from military aircraft to high-voltage test equipment.



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can be freely chosen. And, of course, the isolation barrier can prevent electric shock and reduce other hazards caused by faults. Because the output is isolated from the input, the choice of the ‘zero’ reference voltage for the input or output side is also arbitrary. For example, an isolated dc/dc converter with a 5-V output can be used to change voltage level and polarity (e.g. +5-V out from -48-V in), add to an existing voltage (e.g. generate +20 V from a +15-V supply) or create a dual output from a single supply (e.g. ±5 V from +5 V).

An example of a ring core transformer with functional isolation.

Potted - core transformer construction Step 1: Primary winding

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Step 2: Potting

Step 3: Lid fitted and secondary wound around case |

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ISOLATION TECHNIQUES Bobbin transformer cross section Secondary winding


A RECOM REM1 medical-grade dc/dc converter in a compact SIP7 case uses a reinforced transformer construction which lets it be medically certified to the IEC/ EN/UL 60601-1 safety standard with 4 kVac/1 min. isolation, 2 x MOPP (Measures of Patient Protection) and 250 Vac working voltage isolation.

Magnetic core Bobbin


Primary winding

A bobbin transformer with basic isolation. The isolation grade depends on the robustness of the isolation barrier. For dc/dc converters, the most commonly used classes are: Functional - The output is isolated, but there is no protection against electric shock. Basic - The isolation offers shock protection as long as the barrier is intact. Supplementary - An additional barrier to basic, required by agencies for redundancy. Reinforced – A single barrier equivalent to two layers of basic insulation.

IN AN ISOLATED SUPPLY It is useful to explore how these classes translate into practical transformer construction. For functional isolation, the transformer primary and secondary


windings are typically wound directly over one another, relying on the thickness of the wire lacquer for insulation. This method has the advantage of being inexpensive and yielding a compact transformer which, despite the small size, can withstand up to 4 kVdc isolation testing but with limited duration and as a non-repetitive test. Typical applications for functional isolation converters include non-safety-critical systems. Here the isolation is primarily used to prevent ground loops, block conducted interference paths, or to provide a change in functional ground reference voltage. In these applications, an isolation fault would not injure anyone or seriously damage the equipment, or (usually) stop the application from working. The isolation helps prevent

interference and boosts reliability, but is not safety-related. A good example is a CAN-bus data communication system. The CAN-bus specification does not specify that the bus wiring must be isolated. But in practice, isolating the interface eliminates many potential sources of error or interference with the data transmission. As both ends of the bus are isolated, the transmitter and receiver can sit at different ground potentials without problem. Any electrical interference is ignored by the differential bus topology, without the danger of external fields inducing an overall current flow in the wiring. This is one of the reasons why isolated CAN-bus systems are often used in heavy industrial automation plants and production processes.

Isolated dc/dc converter configurations Additive


Examples of isolated dc/dc converter applications include those that invert the polarity of a dc supply, boost a dc output, and provide a ± output from a single supply. |

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POWER & ENERGY EFFICIENCY HANDBOOK Typical reinforced transformer cross section

Supplementary insulation

An example of a reinforced transformer construction with a basic and supplementary layer of insulation (shown as the thick black lines in the diagram).


Texas Instruments ISO1042 5-Mbit data rate in CAN FD mode 1-Mbit data rate in CAN Classic mode

An evaluation board that uses a RECOM SMD dc/dc converters to provide isolated bus power.

Basic separation bridge transformer

Basic isolation grade requires secure insulation between the primary or secondary windings, rated at the system voltage lacquer insulation on winding wire is insufficient as pin-holes can be present. In a basic-insulation-grade transformer, the input and output windings are not wound directly over one another, but are separated by a minimum distance or with a physical barrier, such as an agency-approved insulating film. This method can be used in larger transformers where there is enough room to add layers of tape between the windings. For compact dc/dc converters, it may be a challenge to provide basic isolation without making the transformer too big. One technique uses a separation bridge to physically separate the windings. In addition, manufacturers may coat the ferrite ring core with plastic so it is also independently isolated from the windings. Another way of making a basic-insulated transformer uses a potted core. In this method of construction, the ferrite core with one winding (usually the primary) is placed in a plastic pot which is then filled with epoxy. A lid is fitted and then the second winding is wound around the whole construction through the hole in the middle. The insulation doesn’t depend on the lacquer around the transformer wires. Instead, it is independently ensured via the plastic pot and epoxy filling. Production processes ensure that the quality and thickness of epoxy and lid meet the minimum agency requirements for basic insulation at the stated system voltage. Although more complex to manufacture, this ‘potted-core’ method gives a very compact transformer with a reliable and consistent insulation performance which does not deteriorate with time. With reinforced isolation, input and output windings are separated by a larger distance or at least two physical barriers, each equivalent to a basic insulation rating. The multiple layers of insulation make the transformer bulkier, however, which limits the amount of miniaturization possible. One way around this problem is to use triple insulated (TIW) transformer wires which are already classified as offering reinforced insulation.


Primary winding

Secondary winding

The RECOM RxxPxx and RxxP2xx series use a bridge-design transformer type of construction which is production-tested up to 6.4 kVdc, in a compact SIP8 package (19.5 x 12.5 x 9.8 mm).

Transformer co




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Why it’s tough to characterize SiC power MOSFETs Levi Gant, Xuning Zhang, Ph.D. | Littelfuse, Inc.

Switching transients and parasitics can combine to thwart the accurate measurement of important MOSFET operating parameters.

Silicon carbide (SiC) power MOSFETs get a lot of attention because they can switch fast while maintaining high blocking voltages. But their superior switching qualities also have potential drawbacks. Parasitic inductances caused by less-thanoptimal board layouts, along with the SiC MOSFET’s fast dv/dt and di/dt qualities, can create voltage and current overshoot, switching losses, and system instability problems. To head off such difficulties, designers must understand SiC MOSFET switching qualities in depth. Additionally, the extremely fast switching speeds of SiC MOSFETs also present challenges when characterizing the devices. For example, equipment selection can affect test and measurement accuracy. The highly sensitive design and integration schemes of the driving and power stages also play a role in minimizing voltage spikes, EMI, and switching losses.

ENSURING TEST AND MEASUREMENT ACCURACY Circuit and package parasitics and the high-speed switching of SiC MOSFETs all complicate characterization tasks. The fast dv/dt and di/dt amplify measurement inaccuracies, voltage/current ringing, etc. High dv/dt can produce large transient voltage spikes, as well as common-mode noise that can appear as damped oscillations. High di/dt generates noise that can couple with nearby magnetic fields. These effects can be difficult to measure and diagnose. It



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takes special tools and test methods to uncover hidden problems before they emerge during product qualification stages or as infant mortality failures. And it takes tools with exceptional bandwidth and dynamic range to characterize SiC power devices that are switching high levels of power at high speeds. Differential probes are commonly used for high-voltage measurements of this type. But though they offer built-in galvanic isolation, they have relatively limited bandwidth. In contrast, passive voltage probes have enough bandwidth but lack galvanic isolation. Additionally, many passive voltage probes are not rated for high voltages. If this is the case, a traditional voltage divider must be designed into the circuit as well, introducing another resistive load. All things considered, the best option for these voltage measurements is a passive voltage probe with a voltage rating high enough to capture high dv/dt transients. Four methods are commonly used for measuring current: a Rogowski coil, an active current probe, a current transformer, or a coaxial current shunt. Each method presents both pros and cons. For example, an active current probe and a Rogowski coil are unobtrusive in terms of incorporating them into the test circuit. However, they typically lack the bandwidth to measure current ringing effects. A current transformer likely has enough bandwidth to capture ringing frequencies. But it requires that current pass through its aperture – sometimes a tight bottleneck -- and can’t make dc measurements, a drawback it shares with the Rogowski coil. |

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Double-pulse test setup DC charging control

GDPS Gate Driver


DC Power Supply

DC link capacitor for energy storage

External DC link capacitor

Function Generator

The current shunt also requires a bottleneck in the circuit and is not galvanically isolated like the other three options. But it is often the best way to measure current during characterization because it captures all frequencies, from dc up to megahertz. It should be noted, however, that the current shunt has a low power dissipation. So it is only appropriate for measurements in pulsed tests and not for continuously operated systems.

OPTIMIZING POWER LO OP LAYOUT Most power circuits actually contain two main circuits: the gate drive loop and the power loop. In the power loop, high levels of voltage and current switch at extremely fast edge rates. This phenomenon leads to voltage and current overshoot and ringing. The extent of overshoot and ringing relates to the amount of parasitic inductance and capacitance in the power loop. One primary concern is voltage overshoot during turn-off. This overshoot is characterized by the product of the di/dt and power loop inductance. A high di/dt is desirable, so designers must keep the power loop inductance as low as possible. Peak-voltage overshoots that approach the device’s maximum voltage rating put the device at greater risk of catastrophic failure. If excessive parasitic inductance in the power loop can’t be avoided, designers could be forced to limit the speed at which the devices switch or to implement a multi-level topology, at the cost of greater design complexity and more components. Another concern is electromagnetic interference. During switching, severe ringing in the current waveforms can turn the power loop into an antenna, broadcasting megahertz-band frequencies. This noise broadcast by the power loop can potentially couple into other sub-circuits, perhaps causing inadvertent device turn-on and shootthrough, nearby peripheral circuit malfunctions, or failure to comply with mandated electromagnetic compatibility regulations. |

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Gate Driver

Load Inductor


Aux. Power Supply

Probes & BNC Cable


A double-pulse test setup. In this test, an inductive load is in parallel with a free-wheeling device in the upper switch position. These elements make up the free-wheeling path for current during DUT turn-off states. The DUT occupies the lower switch position. This testing configuration is useful for studying switching energy and gate charge characteristics of the DUT.

The first principle of optimizing the power loop layout should be to keep the board compact and simple, minimizing the overall power loop area. The ideal scenario would be a loop that consists of only one point in space, that is, no trace/wire at all. A more realistic scenario is a loop with an outgoing path that overlaps with (is mirrored by, on another PCB layer) the return path, a practice known as lamination. In portions of the loop where lamination is not possible (such as the pins of a through-hole component), power paths should be wide enough to accommodate the current but as short as possible to maintain a compact overall loop. The use of decoupling capacitors is another good practice for optimizing the power-loop layout. The process of switching at high speeds creates higher-order harmonics of the switching frequency (fs) and transient-related frequencies (ftrans) that extend well into the megahertz range. Typically, the dc link capacitor acts as a notch filter, eliminating oscillations corresponding to fs and its harmonics of appreciable amplitude; however, it does not suppress ftrans frequencies, which can couple into neighboring traces and circuits. To suppress peaks associated with ftrans, connect relatively high-farad film capacitors across the dc link and place them as close to the power transistors as possible to minimize the associated loop inductance.

GATE DRIVER DESIGN The gate drive has two main purposes: to turn power switches on and off in a stable, well-controlled manner and to protect power 10 • 2019



10/10/19 9:12 AM


Results of a double-pulse test performed with an 800-V dc bus voltage and a device current of 20 A. Top, captured waveforms from double-pulse test (10 μsec/div). Middle, magnified portions of the waveforms above that correspond to the turn-off transient waveforms (50 nsec/ div). Bottom, magnified portions of the top waveform that correspond to the turn-on transient waveforms (50 nsec/div). These events are used to characterize the switching behavior of the MOSFET in terms of its switching energy, switching speed, rise and fall times, voltage overshoot, etc.



Littelfuse — P&EE HB 10-19.indd 30

10 • 2019

stages when necessary. However, these tasks can be difficult without proper design layout and integration of the gate drive with the power stage. Common problems include unnecessary switching losses, gatevoltage overshoot and ringing, and EMI from the power loop that makes the control circuit malfunction. Even a modest level of common-source inductance (LCSI) will resist fast changes in current and boost switching losses. In the presence of high gate and source loop inductance (LG and LS), high values of di/dt can lead to overshoots in the voltage that appears at the device gate. Oscillations in the gate voltage waveform can lead to inadvertent turn-on and, as a result, potentially catastrophic shoot-through events. Hammering the device gate repeatedly with excessive voltage can also degrade device reliability and lifetime. Best practices to optimize the design and integration of the gate driver circuit include reducing the effect of inductive coupling between the gate and power loops. Wherever possible, place these two loops in orthogonal planes. Next, just as with optimizing the power loop, minimize the total gate loop area through a combination of lamination and shortening of path lengths. Finally, to reduce common-source inductance, decouple the gate and power loops by using packages with a dedicated Kelvin source, such as the four-lead TO-247 or the sevenlead TO-263. Double-pulse testing offers a way to evaluate a SiC device’s switching performance accurately on a per-cycle basis. This test involves turning the device on twice. The width of the first turn-on pulse, in conjunction with the inductor value and bus voltage, determines the current amplitude through the device during turn-off. During the period between the first and second turn-on pulses, the energy stored in the inductor circulates through a free-wheeling device. This action allows the device to see the same set of operating parameters during the rising edge of the second pulse, the turn-on event. In a double-pulse test, an inductive load is placed in parallel with a free-wheeling device in the upper switch position. These elements make up the free-wheeling path for current during DUT turn-off. The DUT occupies the lower switch position. This testing configuration is useful for studying switching energy and gate charge qualities of the DUT. The waveforms of interest are gate-source voltage (VGS), drainsource voltage (VDS), and drain current (ID). In this test, voltage-controlled relays disconnect the dc power supply (positive and negative rails) from the test setup. The dc link capacitance is sized so it can maintain the desired bus voltage throughout the test after being disconnected from the dc power supply. This improves measurement conditions by minimizing the risk of ringing during transient events caused by ground loops. If the system can’t accommodate a dc link capacitor big enough to allow for disconnection from the dc voltage supply, the dc link capacitance must still be large enough to maintain dc voltage during device switching. The high switching speed of SiC MOSFETs means the dv/dt and di/dt can exceed 80 V/nsec and 5 A/nsec respectively under certain test conditions. Because these devices are switching on and off within tens of nanoseconds, the measurement probes must have adequate bandwidth, good dynamic performance, and loading capacitance that is small. |

10/10/19 9:12 AM

SiC MOSFETs Post-processed turn-off transient waveforms

Post-processed turn-on transient waveforms

(b) Turn-on transient waveforms

(a) Turn-off transient waveforms

Double-pulse test waveforms after post-processing.

Matlab is a useful tool for determining the numerical values of device switching qualities. Once the raw data is imported, the VDS and ID must be properly de-skewed. A nearby graphic gives an example of plots generated for the turn-on and turn-off transient voltage (VDS), current (ID), and instantaneous power. Switching energy calculations and switching behavior of the DUT can be derived from these waveforms. The waveforms indicate that, during the turnoff event, a ~70-V overshoot takes place, dv/dt = 68.72 V/ nsec, di/dt = 1 A/nsec, and turn-off loss is ~60 μJ. During the turn-on event, a ~10-A overshoot takes place, dv/dt = 39.47 V/nsec, di/dt = 5.2 A/nsec, and turn-on loss is ~270 μJ. Note that switching loss values are obtained via integration of instantaneous power. The double-pulse technique has proven useful for characterizing SiC MOSFET switching losses, as well as for other typical dynamic parameters such as switching times, gate charge, and reverse recovery.

REFERENCES An application note covers the Littelfuse Dynamic Characterization Platform: media/electronics/application_notes/littelfuse_dynamic_ characterization_platform_application_note.pdf.pdf

10 • 2019

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10/10/19 9:13 AM


Don’t be confused by line and neutral fuses David Norton | TDK-Lambda Americas

It pays to know when the use of a single fuse is less hazardous than fusing both hot and neutral wires.

For many years ac-dc power supplies for

Dual fusing

the medical market have been safety certified to the IEC 60601-1 medical standard and to the industrial IEC 60950-1 /IEC 62368-1 standards. Dual certification reduces the number of


Fuse F1


Fuse F2


individual model numbers manufacturers must produce and stock. A point to note is that two ac input fuses are needed in many medical applications, one in the Line side and one in the Neutral side. Dual fusing is necessary to guarantee full protection if the polarity of the Line and Neutral wiring to the power supply should be reversed.  This condition might arise due to a wiring error at the building’s ac socket or in the wiring feeding the power supply. Nevertheless, supply manufacturers such as TDK-Lambda now offer a single (Line) fuse option on new medical/industrial power supplies.  Here is the explanation why: If an industrial system is consuming more current than a regular ac socket can support, it would have to be permanently connected to a



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Earth ground

Distribution panel

Power supply

Voltage relationships in a phase-to-phase connection (208 Vac).

A power supply connected to the ac input, its Neutral connected to the earth ground at the panel. |

10/10/19 9:15 AM

FUSING External fusing

Distribution panel


Line L1

Fuse Internal power supply circuitry


Line L2

The installation of an external fuse or breaker in the Neutral of an industrial supply.

Ground Line L3 Ground

distribution panel or building wiring. This task is normally carried out by a professional electrician, who would be aware of the potential dangers of a polarity reversal.  In the event of an over-current fault in the power supply or fuse aging, there is a 50% chance that either the Line or Neutral fuse would open.  If the Neutral fuse was to open, a service technician may believe that there is no ac power applied to the power supply.  Inadvertent contact with the Line while touching the earth ground would result in an electrical shock.  This is even more likely if the power supply in question is of an open frame type construction. To avoid this possibility, the NEC, CEC, IEE Wiring Regulations and IEC 364 specifically prohibit fusing in the Neutral in this type of equipment.  To comply, a single-fuse power supply must be selected. 

Phase-to-phase voltage relationships 120Vac

Line L1


Neutral N often grounded

The candidates are typically industrial (single fuse) or medical/ industrial power supplies with a single-fuse option. This scenario brings up the question of whether there are cases where an external fuse should go in the neutral connection of an industrial DIN rail power supply.  DIN rail power supplies are rarely certified to medical safety standards. Usually they only have a single input fuse. Consider the case where the application is a power supply operating phase-to-phase from a three-phase WYE configuration in North America. Connecting phase-to-phase enables the equipment to be supplied with 208-Vac which draws less input current than using 115 Vac.  This configuration allows the use of smaller wire gauges and connectors which saves money and are easier to install.   In the UL safety report Conditions of Acceptability, or Technical Considerations section, reference is made to all testing being performed on a protected branch circuit rated for 20 A; this section also lists the items that a user should consider before applying power to the unit. If a short or overload inside the power supply happens across the Line-and-Neutral or Line-and-Ground, an internal fuse will open.  If the short happens from Neutral-to-Ground, the fuse or breaker at the distribution panel will open. If, however, the equipment connection to the building installation wiring is made via a non-industrial plug and socket, then an external fuse or breaker must be added in the Neutral line.  This applies to input voltages of less than 240 Vac +10%. It is best to always have your equipment installed by a qualified electrician and checked by a safety engineer for compliance to the relevant building and electrical codes!


Line L2


TDK-Lambda power topics blog,

A power supply connected phase-to-phase. |

TDK — P&EE HB 10-19.indd 33

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10/10/19 9:15 AM

TRACO POWER North America, Inc. +1 (408) 916-4570




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11.8-15.0 V 23.5-28.0 V 47.0-56.0 V 11.8-15.0 V 23.5-28.0 V 47.0-56.0 V 23.5-28.0 V 47.0-56.0 V 23.5-28.0 V 47.0-56.0 V

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Traco 10-19.indd 34

10/10/19 8:28 AM


Polymer capacitors show promise as MLCC alternatives

Randall Scasny | element14

It pays to know how different capacitor technologies behave when shortages force a search for good substitutes.

The demand for MLCCs (multilayer ceramic capacitors) has outstripped supplies since 2017. Industry observers expect the shortage will dissipate by 2020, but product manufacturers remain concerned. In a quest to find suitable alternatives, an online community of over 650,000 engineers held a spirited design contest which involved testing how polymer capacitors stack up against their ceramic counterparts. The rise of mobility – both in mobile computing and automotive uses – has triggered enormous demand for MLCCs. The complexity of MLCC manufacturing processes (using alternating nano-layers of ceramic and metal) has limited the number of manufacturers capable of realizing consistent quality control. The good news is that engineers have a variety of ways to avoid MLCCs in their designs. One approach is to use a larger capacitance in an available package, as long as it doesn’t incur much board redesign. Another approach is to use lesser-valued capacitors in parallel, or use a different capacitor technology altogether, such as conductive polymer capacitors. The element14 online community tested the last alternative through its Experimenting with Polymer Capacitors design contest. There were interesting results. Design challenge entrants received a kit of 17 types of Panasonic polymer capacitors ranging from 4.7 µF to 470 µF. They also got a peak ESR capacitor tester that made it possible to experiment with different capacitors, build original circuits, modify existing ones, and so forth. Entrants blogged about their findings. |

element14 — P&EE HB 10-19.indd 35

The ESR 70 and ESR meter and Tenma 72-1020 bench multimeter as used to gauge ESR in the capacitor tests.

10 • 2019



10/10/19 9:20 AM


Their first chore was to find the best way to measure Equivalent Series Resistance (ESR) and the actual capacitance of electrolytic capacitors. These parameters are important because today’s microprocessor-based systems require power sources that deliver high current and ultra-fast transient performance, with tight regulation. These conditions create a need for economical, compact capacitors with high capacitance values. An ideal capacitor has no series resistance, but ESR exists in all real-world capacitors, albeit with small values. Capacitor ESR influences circuit behavior and can worsen over time due to age (e.g. drying out of electrolyte in some capacitors), abuse, and overheating. Power dissipation rises, triggering a vicious circle of continued deteriorating performance. One of the first experiments members undertook was finding the most reliable way to measure the ESR of polymer capacitors. Members used two different methods, an oscilloscope and an ESR meter, to measure the relative ESR for Panasonic polymer capacitors. The caps met their datasheet specifications for the conditions examined. Members took extra care with lead placement and contact when measuring ESR.





Output Voltage (V)



Input Voltage (V)



Input Current (A)



Output Current (A)



Input Power (W)



Output Power (W)



Efficiency (%)



Ripple Voltage (Vp-p)




element14 — P&EE HB 10-19.indd 36

Scope measurement with square wave

The result: Both Scope methods gave similar results though there were some significant points = 50 Ω to note. Capacitance Ch.1 measurements between the ESR 70 and a Tenma 72-1020 bench multimeter were in good agreement Scope function although the ESR 70 generator consistently measured lower than the Tenma 72-1020. The Peak Scope measurement with sine wave ESR 70 proved easy to use but lacks sufficient Scope accuracy and precision for measuring ESR below = 50 Ω about 0.04 Ω. Ch.1 Rs The oscilloscope method, while more difficult to set up and slower, produced results Ch.2 resembling those of the ESR 70. However, the oscilloscope method has some benefits. For Scope function generator example, by varying the frequency or just observing the shape of the trace, it is Typical setups for measuring capacitor ESR using possible to get further insight into a scope and its built-in function generator. other non-ideal behavior of the capacitor (e.g., inductance). from the TPSM84A21, the input pins OUTPUT SWITCHING RIPPLE REDUCTION may need additional bulk capacitance. A typical recommended amount of bulk input Another experiment investigated the impact of replacing ceramic capacitors with polymer capacitance is 47 µF - 100 µF. Community members tested whether capacitor technology. Members added bulk a low-ESR polymer capacitance could help. capacitance to a TI SWIFT Power Module Extremely low ESR is necessary to reduce to see if polymer capacitors facilitated an ripple voltage amplitude, generally a task for output switching ripple reduction. using ceramic capacitors. An alternative is a The TPSM84A21 10A SWIFT Power single Panasonic aluminum polymer capacitor Module is a buck converter which which can replace several ceramic capacitors. can convert an 8-to-14-Vdc input to a Community members evaluated a 0.508-to-1.3-Vdc maximum 10-A output. limited number of conditions at relatively The module has both input and output low output power conditions. The first test capacitors built in. External capacitance employed no external bulk capacitance, is not normally needed. However, if the resulting in about 8 mV of ripple. Switching input supply sits more than a few inches Charge pump results. Polymer capacitors can perform dramatically better than MLCC Capacitors, especially when the working voltage is near the rated voltage of the capacitor.

10 • 2019 |

10/10/19 9:20 AM

MLCC ALTERNATIVES Charge pump circuit

In the case of the design contest, the charge pump circuit was a Dickson design that used a 12-V input. The output of the charge pump was ~48 V with no load.

ripple noise arose at the same frequency as the switching frequency of the module. Members next experimented by adding external bulk input capacitance in the form of a surface-mounted 120-µF Panasonic conductive aluminum solid capacitor. Adding the bulk input capacitor reduced the ripple from 8 mV to 5.6 mV, well below the datasheet value. Ripple and noise not reduced via filtering may be high enough to degrade the performance of devices connected to the power supply. The addition of bulk capacitance showed how output ripple and output-ripple noise can be reduced. Another experiment focused on a charge-pump application and compared the performance of polymer capacitors with MLCC capacitors. As a quick review, a charge pump is a kind of dc/dc converter that uses capacitors to raise or lower voltage.  Some form of switching device controls the connection of a supply voltage across a load through the capacitor. In charge pumps with a two-stage cycle, a capacitor first connects across the supply and charges to the supply voltage. In the second stage the circuit is reconfigured, so

Test No.

Input Voltage (V)

Input Current (A)

Output Voltage (V)

Output Current (A)

Output Load (Ohms)













the capacitor is in series with the supply and the load. This makes the voltage across the load equal to the sum of the original supply and the capacitor voltages. The pulsing nature of the higher voltage switched output is often smoothed by the use of an output capacitor. Charge pumps can double voltages, triple voltages, halve voltages, and generate arbitrary voltages by quickly alternating between modes, depending on the controller and circuit topology. In the case of the design contest, the charge pump circuit was a Dickson design that used a 12-V input. The output of the charge pump was ~48 V with no load. Experimenters drove this charge pump with a simple power oscillator. The design generated a pulse output using a 74HC4040D ripple counter, 74AC14 Schmitt trigger inverters, and an LMD18201 H-bridge. The circuit used only one of the outputs from this H-bridge driver because the capacitors are polarized, and the full bridge would reverse polarity. Charge pumps employed MLCC capacitors and polymer capacitors, both 10 µF devices rated for 50 V. Members found that under no load, both charge pumps generated the same voltage boost; with 12-V input they produced 47-V output. Yet to realize a 49-V out, the MLCC circuit needed two more volts at the input, 13% more input voltage. For the polymer capacitor charge pump at Power Output 49-V output with a glue gun heater load, the input Dissipated Ripple power was 7.94 W and the output power was in Load (mV) 6.76 W, providing an efficiency of 85.2%. For the (Watts) MLCC capacitor charge pump, at 49-V output with 0 8 a glue gun heater load, the input power was 9.15 W and the output power was 6.82 W, providing an 0.1 8 efficiency of 74.5%.









































Test results |

element14 — P&EE HB 10-19.indd 37

Experimenters checked several conditions at relatively low output power conditions, with and without an external bulk input capacitance.

10 • 2019



10/10/19 9:20 AM


The power oscillator driving the charge pump used only one of the outputs from its LMD18201 H-bridge chip because the capacitors are polarized, and the full bridge would reverse polarity.

Tests also found the output ripple voltage with the MLCC circuit was about five times higher than that of the polymer capacitor circuit, which could be important if this were used as a power supply. With the same input voltage (12 V) the polymer capacitor circuit generated about six more volts (under load) than the MLCC circuit, about 17% higher.

A REAL ALTERNATIVE TO MLCCS The charge pump circuit application showed polymer capacitors can perform dramatically better than MLCC Capacitors, especially when the working voltage is near the rated voltage of the capacitor. These experiments show great promise for polymer capacitors as MLCC replacements. Polymer capacitors, in fact, had advantages over their MLCC alternatives especially in terms of low ESR, less output switching ripple, and better energy efficiency. The shortage in MLCC capacitors also prompted much discussion in the engineering community regarding passive components in general and the use of conductive polymer capacitors. While supply and demand of MLCCs will eventually stabilize, the current MLCC shortage has helped enhance knowledge of conductive polymer capacitors and how alternatives to MLCCs might avoid supply challenges in the future.



element14 — P&EE HB 10-19.indd 38

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REFERENCES Evaluating polymer capacitors, community/community/designchallenges/polymer-capacitors/ blog/2019/05/13/experimenting-withpolymer-capacitors-introductory-blog The polymer capacitor contest page, community/community/designchallenges/polymer-capacitors |

10/10/19 9:20 AM

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Boosting performance in power distribution Phil Davies | Vicor Corp.

New ways of routing power around circuit boards bring more efficiency and fewer thermal problems.

Power distribution networks (PDNs) are the backbone of any power system. As system power demands rise, traditional PDNs are under tremendous pressure to deliver enough performance. There are two main ways to improve PDN impact on power system performance with regards to power losses and thermal management. Option one, reduce the PDN resistance with larger cables, connectors and thicker motherboard power planes; or option two, boost the PDN voltage to reduce its current for a given power delivery, which can allow use of smaller cables, connectors, motherboard copper planes and their associated size, cost and weight. For many years engineers have used option one for compatibility with the large ecosystem built up over decades for single-phase ac and 12-V dc-dc converters and regulators. Other reasons include the lack of performance of dc-dc converter topologies that could efficiently convert higher voltages to PoL (point-ofload) directly and the associated expense of these higher-voltage converters and regulators. However, modern-day power designs increasingly use option two, higher PDN voltage. This trend is driven by the significant rise in system load power. In the case of data centers, the addition of artificial intelligence (AI), machine learning, and deep learning has caused rack power to soar by a factor of two into the 20-kW range; and supercomputer server racks are now approaching 100 kW or more.

This increasing need for power has systems engineers reevaluating their complete PDNs, from the distribution of power to the racks, power distribution within the rack, and even the PDNs on the server blades because modern CPUs and AI processors consume more power. When rack power was at a 5-kW level, single-phase ac to the rack was the norm. The ac was then converted to 12 V for distribution to the server blades. At the 5-kW level the PDN current was 416 A (5 kW/12 V) and power distribution took place via heavy gauge cables. As processor power started to dramatically rise around 2015, rack power moved up to the 12-kW level. So 1 kA had to be managed within the rack for a 12-V PDN . The OCP (Open Compute Project) consortium -- whose membership includes most cloud, server and CPU companies -- continued to evolve its 12-V rack design. OCP racks moved from cables to bus bars and distributed multiple single-phase ac-to-12-V converters within the rack to minimize the PDN distance and resistance to the server blades. The major change from prior rack power delivery was that the single-phase ac was derived from the individual phases of a three-phase feed to the rack. Companies with the ability to build their own racks and data center solutions began to move to 48-V distribution. This strategy cut down the high-current PDN problem to 250 A for a 12-kW rack but brought new challenges to blade power conversion. As rack power has risen above the 20-kW range, server rack PDN design is continuing to evolve. Attempts to maintain the status quo 12-V legacy systems are creative on many fronts, but the introduction of AI into data centers with processors exceeding 1 kA steady-state with peak currents approaching 2 kA make 12V-based PDNs impractical. AI is all about performance, and 12-V PDNs limit performance and competitiveness. The ideal point-of-load power system. A regulator delivers top efficiency when Vin = Vout. Maximum efficiency comes when high-current delivery is closest to the point-of-load, minimizing I2R losses.



Vicor — P&EE HB 10-19.indd 40

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10/10/19 9:22 AM


High current delivery through the “last inch” impose obstacles on high-power processors. Vicor technology improves this performance and simplifies motherboard design.

To address the many challenges of highpower racks, the OCP consortium is evolving toward racks that accommodate 48-V PDNs. Moving to 48 from 12-V distribution reduces the input current requirement by a factor of 4 (P = V × I) and cuts losses by 16x (power loss = I2R). Moreover, there’s a move to 48-V power distribution in the automotive and 5G markets, LED lighting, display markets, and in industrial applications. Thus the ecosystem of 48-V power converters is rapidly expanding. Moving to 48 V makes good business sense. However, not all 48-V converter topologies and architectures are the same. Performance varies widely in the 48-V converter market, a fact worth carefully considering. With high-performance and power efficiency at the top of the list of requirements for high-power racks and data centers, several companies are moving to three-phaseac-to-48-V for distribution to the blades. Alternatively, high-voltage dc (at 380 V, derived from a rectified three-phase feed) distributed |

Vicor — P&EE HB 10-19.indd 41

within the rack can be used. Several High-Performance Computing (HPC) companies are using HVDC PDNs for racks up to 100 kW. As PDNs that supply the blades convert to 48 V, power conversion on the blade must change. This shift has led to many alternatives in architecture, topology and packaging of dcdc converters and regulators. The 48-V regime is new to data center servers but commonplace in communications applications such as routers and network switches, thanks to their use of -48-V leadacid rechargeable backup battery systems. The common architecture traditionally used in data center servers was called the Intermediate Bus Architecture or IBA. IBA consisted of an isolated non-regulated bus converter to convert the –48 V to +12V which was then fed to a bank of multiphase buck regulators for the points-of-load. Some of the cloud computing companies and HPC companies copied this architecture initially for their 48-V systems, but as power rose and voltage at the PoL dropped to 1 V and below, designers sought out alternative architectures and topologies.

10 • 2019

Power system architecture, switching topologies, and packaging are critical to a high-performance, high-density design. As AI and CPU processor currents rise, the density of the power delivery circuits at the PoL becomes the most critical element in AI applications because of the PDN resistance between the regulator and the PoL. The latest state-of-the-art AI processors have steady state currents of almost 1 kA with peak currents reaching 1.5 kA to 2 kA. Consider that a typical PDN resistance from the output of a conventional multiphase buck regulator to the processor is in the 200 to 400 µΩ range. The resulting power losses in the PCB are 200 – 400 W steady state (P = I2R), too high for any system to handle. PDN losses become the dominant factor in the efficiency and performance of the dc-dc regulator design. Because this is a point-of-load problem and higher voltage is impractical (PoL voltages are declining rapidly to keep Moore’s law in force), the only reasonable approach is to reduce the PDN Vertical Power Delivery (VPD) further eliminates power distribution losses and VR PCB area consumption. VPD resembles the Vicor LPD solution with the added integration of bypass capacitance into the current multiplier or GCM module.



10/10/19 9:22 AM


resistance, usually by placing the regulator as close as possible to the processor. In the case of a multiphase buck regulator, it typically takes 16 – 24 phases to support the high AI processor current. This is not a high current density approach and does not solve the PDN power loss problem.


MCM modules can deliver high current and can sit adjacent to the processor either on the motherboard or on the processor substrate. This close placement minimizes PDN losses and reduces the number of processor substrate BGA pins required for power.

An alternative to IBA is Vicor’s Factorized Power Architecture (FPA), which consists of a pre-regulation stage (PRM) followed by a voltagetransformation stage (VTM). This proprietary architecture optimizes the performance of each stage. The PRM performs a non-isolated (48 V is Safety Extra Low Voltage, SELV) regulation. It’s 48-V input is tightly regulated to provide a 48-V output, and conversion to the desired PoL voltage takes place in the VTM, which is a fixed ratio (The output voltage is a fixed ratio of the input voltage.) converter. This architecture and its performance are enhanced by proprietary topologies used within the PRM and VTM. The PRM uses a zerovoltage switching topology while the VTM uses a proprietary resonant high-frequency Sine Amplitude Converter (SAC) topology. Conversion to the PoL voltage uses both zero-voltage and zero-current switching. The VTM is essentially a dc-dc transformer where the voltage is reduced with the ratio of 1/K and the current is multiplied up by the K factor. The VTM, also known as a current-multiplier, is a high-currentdensity PoL converter. (New products currently hit 2 A/mm2 .) It can sit extremely close to the processor because of its innovative ChiP packaging technology and high-density integrated magnetics. This level of high current density offers designers great flexibility. Depending on processor current, engineers can choose between lateral or vertical power delivery (LPD and VPD). In LPD, the current multiplier sits within a few millimeters of the AI processor either on the same substrate or directly on the motherboard, reducing PDN to approximately 50 µΩ. For even higher performance, VPD moves the current multiplier directly beneath the processor where it’s output power pin map matches the pitch and location of the processor power pins above it. The currentmultiplier package also integrates the high-frequency bulk capacitors that typically sit beneath the processor on the motherboard or substrate. This type of current multiplier is called a GCM (Geared Current Multiplier). VPD reduces the PDN resistance to an incredible 5 to7 µΩ, enabling AI processors to realize their true performance capabilities. Complex power problems of this magnitude require a holistic design approach to deliver successful high-performance results. It takes innovations in architecture, topologies and packaging to solve the toughest power challenges. Higher-voltage PDNs can solve many system performance challenges. A reduction of PDN resistances is the key to unlocking the next generation power for HPC and enabling the promise of AI.

REFERENCES An application note covers the Littelfuse Dynamic Characterization Platform: application_notes/littelfuse_dynamic_characterization_platform_ application_note.pdf.pdf



Vicor — P&EE HB 10-19.indd 42

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10/10/19 9:23 AM

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10.10.19 13:21


Optimizing discrete SiC devices Dr. Anup Bhalla | UnitedSiC

SiC FETs now include measures aimed at keeping losses down while managing fast switching waveforms.

Silicon carbide (SiC) FETs have low onresistances, fast switching speeds, and intrinsic diodes with low reverse recovery charge (QRR) and low forward-drop (VF) qualities. These qualities make SiC FETs suitable for use in active-front-end threephase rectifiers, totem-pole power-factor correction (PFC) stages, interleaved PFC circuits, phase-shift full bridges, LLC and dual active-bridge circuits. To get the best from these devices, it is important to understand how system layout, thermal, power density and EMI constraints affect their performance.

UnitedSIC’s SiC FETs are cascoded devices formed by co-packaging a silicon MOSFET and a SiC JFET. It is useful to briefly explore what the cascode structure brings to SiC components. As a quick review, a cascoded JFET and MOSFET consists of a low-voltage MOSFET with its drain connected to the source of the JFET. The JFET gate is connected to the MOSFET source. The input to the cascoded combination is the gate of the MOSFET; the drain is the JFET drain, and the source is the MOSFET source. A JFET is normally on, and the The circuit at left shows MOSFET is normally off. The JFET VGS is how the common-

The benefits of a Kelvin connection Gate driver PWR

Gate driver


Gate driver PWR


Gate driver Load + gate current

Gate current


Load GND



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G Load current


Gate drive GND 10 • 2019


source inductance can reduce the voltage available at the FET gate because of the voltage drop across it caused by the rapidly changing load and gate currents through it. On the right, a Kelvin connection has been added to return the gate current so the large voltage drop induced by the main load current in the common source inductance no longer reduces the bias on the gate. This results in faster switching.

Load GND |

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SILICON CARBIDE FETs Turn-off waveforms

Turn-on waveforms



the inverse of the MOSFET VDS. The more positive the MOSFET VDS, the more negative the JFET VGS. When the MOSFET is off (VDS rises), the JFET turns off. The conventional view of SiC JFETs is that their nonstandard drive voltages and lack of an intrinsic diode makes them difficult to work with. The use of a JFET in cascode with a MOSFET solves both of these issues. It uses the MOSFET’s intrinsic diode while switching inductive loads and can be driven using low-voltage MOSFET drive voltages. Additionally, a JFET cascode actually performs better than a SiC MOSFET alone over temperature and at higher values of di/dt. UnitedSiC SiC FETs have a low specific on-resistance and sit in a thermally enhanced standard package. The devices are

Double-pulse test circuit L VGS





Cs Rs

A double-pulse test circuit with RC snubbers used for EON/EOFF measurements. |

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DC link

A comparison of VDS, ID waveforms (top row) and VGS waveforms (bottom row) using the same chipset in the three-leaded (dashed lines) and four-leaded packages (solid lines). Data is taken in an inductive-load, doublepulse circuit with RSNUB=10 Ω, CSNUB=220 pF, RGON=3 Ω, RGOFF=10 Ω, 40 A, 800 V, gate drive is -5 to 15V.

offered in two speed classes which are set during manufacturing by adjusting the gate resistance of the SiC JFET. The UJ3C series switches more slowly and has the higher QRR but is easier to use in standard three-leaded packages. In contrast, the UF3C devices are about twice as fast as the UJ3C parts and come in both three-leaded and Kelvin-source packages. These devices require a more careful circuit layout and benefit from the use of RC snubbers, especially for three-leaded packages with high common-source inductances. The TO247-4L package adds a Kelvin-source connection to a standard TO247-3L. This feature enables users to overcome the limitations imposed by common-source inductances. It also enables faster switching speeds and higher di/dt, creating clean gate waveforms and avoiding false triggering. However, the loop inductance of half-bridge configurations implemented in these packages stays quite high, in the 20-30 nH range, and this inductance leads to high voltage overshoots. These can be reduced using small RC snubbers. The surface-mount D2PAK-7L package has much lower package inductance and half-bridge loop inductance than the three-leaded packages. The DFN8X8 package further reduces loop inductances, by up to 8 nH. One reason that UnitedSiC can build high-performance cascode structures is that its SiC JFETs have drain-source capacitance (CDS) values that are almost zero. This low value

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POWER & ENERGY EFFICIENCY HANDBOOK Example waveforms of the UF3C120040K3S turn-off without snubber (top), with snubber (bottom) at VDS = 800 V, ID = 50 A, VGS = -5 V, Rgoff =33Ω. CH2: ID scale is 20 A/div; CH3: VGS scale is 10 V/div; CH4: VDS scale is 200 V/div. prevents a capacitive voltage divider from forming between the low-voltage MOSFET and the SiC FET. The low-voltage MOSFET is optimized for a ±25-V VGS(MAX) and a 5-V threshold voltage (Vth). This means that while its gate need only be driven from 0 to 12 V, it can also be driven across a wide range of operating voltages. Moreover, there is a relative absence of threshold-voltage hysteresis and negative gate-source voltage instabilities compared to conventional SiC MOSFETs. These properties make it possible to use the cascoded SiC FET at the same gate-drive voltages as superjunction MOSFETs, IGBTs or SiC MOSFETs, with large safety margins.

No snubber / snubber turnoff

Cascode devices are built so the gate resistance (Rg) of the MOSFET slows the device’s VDS swing. VDS, in turn, acts as the VGS drive for the normally-on JFET, enabling some control of dv/dt and di/dt rates. The UJ3C series supports moderate dv/dt rates of 20-40 V/nsec, while the UF3C series covers the 40-100-V/nsec range. The switching speed of SiC FETs enables faster turn-on and turn-off, and in the cascode configuration it also improves the Qrr. The normally-on SiC FET technology used in these devices has a low specific on-resistance (RdsA). This low resistance makes possible small chip sizes, which

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Comparing package performance





10• ︔ 220pF

10• ︔ 220pF

10• ︔ 220pF

Eon (uJ)







Eoff (uJ)







Etotal (uJ)







ON didt (A/ns)







ON dvdt (V/ns)







OFF didt (A/ns)







OFF dvdt (V/ns)







reduce the output capacitance (COSS) values. Consequently, RC snubbers can have a relatively small value for CSNUB and are typically built using surface-mount components in parallel with the source and drain of the FET. In practice, the need to simplify heatsinking may result in layouts with a significant total loop inductance. It may also be difficult to minimize the size of gate-drive loops, depending on the overall converter’s shape and size. Small RC snubbers can effectively manage switching issues with fast SiC transistors. The use of a 220-pF, 10-Ω snubber can dramatically reduce voltage/current ringing. This reduction, in turn, improves the VGS waveforms, because most of the noise on the gate waveforms stems from the ringing current acting on the internal common-source inductance (which is large in the TO2203L and TO247-3L packages). At high currents, it’s possible to increase the rate at which current changes during turn-on by boosting the gate voltage drive from 12 to 15-20 V. Switching waveforms are also well controlled in the presence of a similar snubber.

How the switching behavior of a 30 mΩ, 650-V FET being hard switched in a half-bridge compares at the same 20-A, 400-V condition when the device sits in three packages, listed in order of increasing size, power-loop inductance, and thermal dissipation capacity: the DFN8x8, D2PAK-7L, and TO247-4L. The right half of the table shows the switching data compared with a 10 Ω, 220 pF snubber across each FET, which is used to help manage voltage overshoots.

It is important to use isolated gate drivers with such Kelvinsource packages, because the return for the gate is no longer at the same voltage as the power source. The gate-drive power rails must therefore also be isolated, or the gate driver must be able to withstand some voltage bounce between the source and the Kelvin-source connections. If circuits are to be driven by a control IC with built-in drivers, designers must ensure the IC can only see the differential voltage across the external current-sensing resistor that is in series with the Kelvin-source device.


PUSHING TO HIGHER SPEEDS While it is less common to produce SiC MOSFETs in Kelvinsource packages, their performance benefits make them increasingly attractive. A Kelvin connection puts the commonsource inductance outside the gate drive loop. Consequently, the Kelvin-source connection bypasses any voltage drops developed across this inductance during rapid changes in current flow. Those voltage drops slow the device turn-on and turn-off. |

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