Page 1

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 25, Number 4

CLOSING OUT 2021 page 3

2021 +

Harnessing the Power of Data in Semiconductor Test page 11



UP FRONT It was certainly a year of mixed emotions, especially with progress towards the “new normal”.


CALL TO ACTION FPGA device makers missed a strategic window of opportunity to qualify alternative suppliers of solder columns.



COUPLING & CROSSTALK Fear of failure or not finding the best solution often results in “analysis paralysis” which prevents action.

CATCHING UP WITH Ravi Mahajan, Assembly and Test Technology Pathfinding at Intel joined the MEPTEC Advisory Board in 2020.



UP FRONT The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 141 Hewitt Street, Summerville, SC 29486 Tel: (650) 714-1570 Email: Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

MEPTEC Executive Director Ira Feldman

MEPTEC Advisory Board Board Members Dave Armstrong Advantest Ivor Barber AMD Calvin Cheung ASE (US) Inc. Zoë Conroy Cisco Jeff Demmin Keysight Technologies Abram Detofsky Intel Neal Edwards AMD Jaspreet Gandhi Xilinx Ravi Mahajan Intel Emeritus Advisors Seth Alavi Sunsil Joel Camarda Anna Gualtieri Elle Technology Phil Marcoux PPM Associates Mary Olsson Herb Reiter eda 2 asic Consulting, Inc., Retired In Memoriam Ron Jones

Contributors Ken Butler Advantest Ira Feldman Feldman Engineering Corp. Martin Hart TopLine Corporation Ravi Mahajan Intel Corporation

Closing Out 2021 Ira Feldman Executive Director, MEPTEC

It is time to say “adieu” to 2021. For many of us in the semiconductor industry it was a very busy year. And it was certainly a year of mixed emotions especially with progress towards the “new normal” combined with a few unexpected retreats. MEPTEC started the Road to Chiplets series this year in July with Architecture followed by Data & Test in November. Data & Test focused on the required cross-functional data sharing across factories and suppliers that is essential to transition Chiplets from design of experiments and prototypes to commercial reality. If you missed any of the excellent presentations from these events, you can find them on including links to the YouTube videos. We will be continuing this “road trip” with the next stop being Heterogenous Integration (HI) Testability in March 2022. We will be announcing the details along with some of the other stops on the Road to Chiplets in the new year. We also look forward to some great presentations in the MEPTEC-IMAPS Semiconductor Industry Speaker Series webinars. Lastly, a little end of the year business. MEPTEC is a member and corporate sponsor supported organization. If you have not already joined or renewed for the year, please do so now. And if your company is interested in sponsoring our programs, please let us know as corporate sponsorships allow us to provide the virtual events free of charge. For assistance with membership or sponsorships please contact Bette Cooper ( I look forward to hearing your suggestions and feedback as to how MEPTEC can best serve you. Please don’t be shy! Stay safe and healthy! Happy Holidays! Ira Feldman Executive Director, MEPTEC +1 650-472-1192

MEPTEC Report Vol. 25, No. 4. Published quarterly by MEPCOM LLC, 141 Hewitt Street, Summerville, SC 29486. Copyright 2021 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493.



Year 2030 – End of the Line for America’s FPGA Superiority Martin Hart TopLine Corporation

THE YEAR IS 2030. YOU MAY READ IN an industry newsletter an announcement that summarizes the following scenario: “Ninety-percent of aerospace and defense grade Field Programmable Gate Arrays (FPGA) with solder columns are unavailable, due to decisions made in the early part of the decade by civilians in the industrial base. The shortage of defense grade FPGA devices was caused by an unexpected shutdown of America’s sole-source subcontractor of solder columns without alternative vendors qualified in the supply chain. Fortunately, a few FPGA devices with solder columns are still being shipped from a dwindling stockpile of finished goods inventory.” Lack of a Robust and Sustainable Supply Chain The story continues: “Defense contractors are unable to provide timely delivery of black box control systems to downstream customers in the supply chain due the lack of FPGA devices with solder columns. The industry now relies on the application of FPGA devices without solder columns, known as Land Grid Array (LGA) which has limited reliability and usefulness in some defense systems. The defense industry now lacks a reliable supply of ruggedized FPGA devices with solder columns that provide a robust and extended life for critical missions. Blame, finger pointing and posturing within the nation’s defense industry has been going on for a while.” It’s a sad day for a once invincible industry. Warning Signs Ignored Warning signs for the potential for an outage were in plain sight back in the early 2020s. In the preceding decade, a handful of decision makers, mostly civilian engineering managers, placed a high-stakes bet that the availability of solder columns 4 | MEPTEC REPORT


would continue forever. They presumed that the then sole-source provider of column attachment services for defense-grade FPGA devices would always be available. They maintained that financial budgets were not available in their department to invest in qualifying alternative suppliers of solder columns.

FPGA device makers missed a strategic window of opportunity to qualify alternative suppliers of solder columns as a pro-active action FPGA device makers missed a strategic window of opportunity to qualify alternative suppliers of solder columns as a pro-active action to mitigate a future catastrophic occurrence should the then sole-subcontractor stop providing column attachment services. In late 2029, the industrial base initiated action to qualify additional suppliers of solder columns, but only after it was too late to do so. Postmortem Investigation Congress plans to hold subcommittee meetings to investigate how America’s defense base arrived at this point. C-level executives of the nation’s defense manufacturers are prepared to receive subpoenas to ‘explain the unexplainable’ to Congress. Testimony reveals that it was financially too difficult in the 2020s for the supply base to justify investing money in a tiny market – consisting of less than 100,000 FPGA devices per year – to support the defense industry to keep warfighters flying and rockets launching. Along the way, the Department of

Defense, including the Defense Logistic Agency (DLA), did not offer incentives to encourage the private sector to qualify alternative makers of solder columns. The defense establishment did not push the industrial base to broaden their reliance beyond the single source subcontractor who was providing solder column attachment services at the time. Only an incredibly small number of employees within the U.S. Government were aware that 90% of the supply chain of defense and aerospace grade FPGA devices depended on a single source subcontractor to attach solder columns. They also did not know that ruggedized FPGA would not perform reliably unless solder columns were attached to the FPGA package. No champion advocated for an industry-wide Plan “B” solution to supplement the FPGA industry in the event of a loss of a key and critical supplier. Conclusion By 2030, America’s self reliance on defense grade FPGA components has been downgraded. The industry is required to outsource column attachment services to trusted suppliers in other countries, since onshore capability is severely constrained. Defense grade FPGA chips, including devices with sensitive Intellectual Property (IP) must be shipped to foreign countries in the form of LGA packages for column attachment services, and then returned home for installation in sensitive U.S. defense systems. This results in significant cost increases with inherent delays. FPGA chips are processed through rigorous trust and security methodologies to ensure that sensitive IP is not compromised and that no tampering has occurred. America has lost control of her homeland IP superiority in defense-grade FPGA devices. America will find ways to adjust, but it is the end of the line for a once venerable onshore industry. ◆


MEMBER NEWS FormFactor Opens New Manufacturing Facility to Expand Capacity for Semiconductor Wafer Probe Card Production

FORMFACTOR, INC., A leading semiconductor test and measurement supplier, today announced the opening of a new manufacturing facility, expanding its Livermore, California campus. The 90,000 square foot facility provides the company with additional capacity to manufacture advanced wafer probe cards, essential equipment to test semiconductor

chips and support the growing test demand of advanced packaging. The new building features a class 1000 clean room for the assembly and test of MEMS probe cards, as well as office and warehouse space. The new facility represents a significant part of the company’s plans to invest approximately $70-80 million in 2021 on manufacturing capacity expansion.

“The opening of our new manufacturing facility is critical to answer the growing demand for our test technologies,” said Matt Losey, Senior Vice President and GM of FormFactor’s Probes Business Unit. “As our customers expand their chip production, we are dedicated to enabling their test success. Today, we design and ship probe cards with more than 85 million MEMS probes annually to customer fabs around the globe. This new manufacturing center will give us space to grow with the industry in the years ahead.” In addition to its Livermore, CA headquarters and probe card manufacturing center, FormFactor’s US probe card manufacturing facilities include Carlsbad, CA; Baldwin Park, CA and Beaverton, OR. ◆

Analog Devices' Essential Analog nanoPower Modules Extend Battery Life in Space-Constrained Applications DESIGNERS CAN NOW EXTEND BATTERY life and reduce size in space-constrained internet of things (IoT) devices with two nanoPower modules with built-in inductors from Analog Devices, Inc. Both products are part of Analog Devices’ Essential Analog family of efficient power ICs. The MAXM38643 1.8V to 5.5V input, 330nA quiescent current (IQ), 600mA buck module and the MAXM17225 0.4V to 5.5V input, 300nA IQ, 1A boost module with True Shutdown™ feature the lowest IQ compared to competitive solutions and deliver more battery life. By integrating a preselected inductor, these micro system-level IC modules (uSLIC™) also accelerate time to market and are up to 37 percent smaller size compared to a standalone IC plus external inductor. Applications include space-constrained consumer products, wearables, medical drug delivery, sensors, IoT devices, as well as wired, wireless and industrial products. Battery-powered IoT devices require low IQ in system standby mode to deliver longer battery life. Further, ultra-low shutdown current (0.5nA on MAXM17225 and 1nA on MAXM38643)

allows systems to consume virtually no system power during shutdown mode. Both MAXM38643 and MAXM17225 consume an order of magnitude less quiescent current (onetenth and one-twentieth, respectively) than competitive solutions with similar output currents. In addition, MAXM38643 and MAXM17225 have peak efficiencies of 96 percent and 95 percent respectively, the highest compared to competitive solutions. As a result, the modules consume less power to deliver longer life and reduced carbon footprint for both battery-operated and wired always-on devices. Both products utilize Analog Devices’ uSLIC power module technology featuring stacked, integrated inductors that enable designers to reduce solution PCB surface area and eliminate the time spent on component selection and board placement. Essential Analog ICs deliver Analog Devices’ advances in low-power, high-performance, single-function products to enable next-generation innovation in multiple applications and markets. For more information visit and ◆


DECA TECHNOLOGIES has reached an agreement with nepes corporation whereby nepes will expand its geographic footprint and manufacturing capabilities by taking over the operations of Deca Technologies Philippines manufacturing facility. The investment will permit the expansion of the WLCSP capacity already in mass production and now offer up to 100,000 wafers per month with a dual site capability courtesy of the Korea site in addition to the Philippines facility. As part of the agreement, nepes has licensed Deca’s M-Series technology to further enable the rapid industry adoption of advanced fan-out technology.


TELEDYNE FLIR has named Anne Bulik Vice President of the company’s Unmanned Aerial Systems (UAS) Business Unit. Bulik brings more than 20 years of experience in electronics and defense to her new role leading the business as it expands rapidly due to increased demand for Teledyne FLIR’s advanced drone products, payloads and technology. She will report to Dr. David Cullin, general manager of the Unmanned and Integrated Solutions business. Bulik joined FLIR in 2020 before the company was acquired by Teledyne Technologies to lead the Waterloo, Ontario division of UAS.





SEMICON Southeast Asia 2022 to Take Place in Penang with a Lens on Sustainability and Supply Chain Resilience


INDIUM CORPORATION has announced two personnel updates within its marketing team operating out of the company’s global headquarters in Clinton, New York, U.S. Jason Farrell has assumed the new role of Senior Digital Marketing Specialist and Joy Valencia has been hired as Marketing Communications Specialist. Farrell brings more than 15 years of industry experience to his new role where he manages, implements, and reports on the company’s digital marketing program. Valencia has been named Marketing Communications Specialist after previously serving as a Marcom Intern.


SEAL BUSINESS SUSTAINABILITY AWARD LATTICE SEMICONDUCTOR has announced that it has been named a 2021 SEAL Sustainability Award winner for its leadership, transparency, and commitment to sustainable business practices. The Lattice Nexus™ FPGA platform was recognized in the Sustainable Product Category for its leadership power efficiency and small size that enable efficient, long-lasting application designs for the Communications, Computing, Industrial, Automotive, and Consumer markets. The SEAL Sustainable Product Award honors innovative and impactful products that are “purposebuilt” for a sustainable future, judged by a panel of ten sustainability and ESG experts.


SEMI HAS ANNOUNCED NEXT YEAR’S edition of its annual semiconductor trade show and conference – SEMICON Southeast Asia 2022 will take place in Setia SPICE Arena & Convention Centre in Penang, Malaysia from June 21 to 23. Themed Forward as One – Building A Resilient and Sustainable Electronics Supply Chain in Southeast Asia, SEMICON SEA 2022 will shine a spotlight on the supply chain disruptions that have battered the semiconductor industry, as well as an increased emphasis on environmental and sustainability challenges that industry players need to grapple with. A confluence of factors is impacting the entire semiconductor value chain – from shortages in talent and workforce, extending to equipment and materials. With disruptions to the supply chain expected to persist into 2022, leading players in the semiconductor industry are increasingly looking to strengthen their business resiliency and continuity through the adoption of advanced technologies. “Disruption, business resiliency and agility have been the industry buzzwords this year, and that will continue well into the next,” said Ms Linda Tan, newly appointed President of SEMI Southeast Asia. “The shortages across every single touch point in the semiconductor value chain will inadvertently snowball into longer lead times for chip production if the industry

sticks to the current status quo. We are hopeful that the insightful discussions at SEMICON SEA 2022 around resiliency will shed light into best practices and culminate into concrete solutions to cope with the supply chain challenges.” Ms Tan continues, “On one hand, microchip innovation presents opportunities to overcome the world’s toughest sustainability challenges, with improved energy-saving and efficient chips to power our devices and machines. On the other, the industry is fighting an uphill battle in reducing the energy and resources required to manufacture these chips. We are excited for the next edition of SEMICON SEA to become the platform for leaders and experts in the semiconductor ecosystem to come together and share their vision on how the industry can forge a greener path in its manufacturing journey.” During the three-day conference, attendees at SEMICON SEA 2022 can look forward to a robust lineup of activities and discussions from experts and thought leaders from semiconductor companies across the world, including topics around supply chain diversification; Environmental, Social, and Governance (ESG); leveraging renewable energy sources; green factories; and agility and intelligence in manufacturing systems. More details about SEMICON SEA 2022 and registration for the event will be shared at a later date. ◆

Xilinx Launches Alveo U55C, Its Most Powerful Accelerator Card Ever, Purpose-Built for HPC and Big Data Workloads

XILINX, INC. has introduced the Alveo™ U55C data center accelerator card and a new standards-based, API-driven clustering solution for deploying FPGAs at massive scale. The Alveo U55C accelerator brings superior performanceper-watt to high performance computing (HPC) and database workloads and easily scales through the Xilinx® HPC clustering solution.


Purpose-built for HPC and big data workloads, the new Alveo U55C card is the company’s most powerful Alveo accelerator card ever, offering the highest compute density and HBM capacity in the Alveo accelerator portfolio. Together with the new Xilinx RoCE v2-based clustering solution, a broad spectrum of customers with large-scale compute workloads can now implement powerful FPGAbased HPC clustering using their existing data center infrastructure and network. The Alveo U55C card combines many key features that today’s HPC workloads require. It delivers more

parallelism of data pipelines, superior memory management, optimized data movement throughout the pipeline, and the highest performanceper-watt in the Alveo portfolio. The Alveo U55C card is a single-slot full height, half length (FHHL) form factor with a low 150W max power. It offers superior compute density and doubles the HBM2 to 16GB compared to its predecessor, the dual-slot Alveo U280 card. The U55C provides more compute in a smaller form factor for creating dense Alveo acceleratorbased clusters. For more information, visit ◆

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COLUMN COUPLING & CROSSTALK By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Fear WHY DO WESTERN HOLIDAY celebrations at this time of year – i.e. Christmas, Hanukkah, and Kwanza – all feature candles and light? Allow me to enlighten you while I provide some seasonal reminders and dispel some lingering COVID gloom. For those of us in the Northern hemisphere not only is it cold but it is dark during the winter months. The ‘warmth’ of the lights and our celebrations not only brings holiday cheer but helps dispel fear of the darkness and cold. It helps us bridge the gap of the unknown of winter into the rebirth of spring. Historically many people did not know if they would survive the challenges and cruelty of winter. Most of us are blessed with not only the resources of shelter and food but with an abundance of material goods. Therefore, depending on your outlook, winter ranges from, at worst, an unenjoyable inconvenient season to, at best, one of great fun with winter activities such as skiing and skating. (As we celebrate the season, we should remember those who are less fortunate and have needs all year round. If you can afford ski lift tickets or lavish holiday gifts, you can certainly afford to also donate to your local food bank or homeless support organization.) Let us explore a catalog of fear – FUD, FOMO, fear of failure, Imposter Syndrome, Atychiphobia, and Kakorrhaphiophobia to name a few – to dispel the dark clouds and learn how they can positively impact our lives personally and professionally and. Conquering fear can turn emotions which provide an excuse for failing to motivations for success.

Fear can clearly motivate behavior as demonstrated by FUD and FOMO. Fear, uncertainty, and doubt (FUD) is a classic tool used by sales and marketing people to motivate customers to stay with their company. “Yes, you could switch to our lower price competitor but their ______ (service, quality, performance, etc.…) would not be the same.” Or the classic information technology (IT) aphorism from the 1970s, but never an official motto or marketing campaign: “Nobody ever got fired for buying IBM.” For many years this was very true even after IBM lost their technology and innovation leadership position.

Fear of failure or not finding the best solution often results in “analysis paralysis” which prevents action. The rise of social media is primarily driven by the fear of missing out (FOMO). Your friends posting (or is it bragging?) about their great Thanksgiving vacation on the beach in Hawaii? Quick, we need to post something to top this! How about a Norman Rockwellian portrait of a lavish Thanksgiving dinner for fifty complete with picture-perfect turkey, dressing, and pumpkin pie? Social media applications are specifically designed to increase your engagement – i.e. the time you spend on them – by making you fear missing something “important” to increase their advertising revenue. It is important to remember that a vast majority of social media posts are how the poster wants to be viewed. These “snapshots of life” are carefully curated and staged to show the poster in only the best light. As we have learned, not everyone shares their bad news or day-to-day struggles. One friend who is going through cancer a second time has quit social media altogether as there is very little they care to share and they are depressed by the unreal representations

of others’ lives. Perhaps it would be healthier if we remember that all social media posts are “advertising” be it for products or our friends’ picture-perfect lives. There is a limit to how many ads we should consume at one sitting. What about fear in our professional lives? Bad managers definitely use fear of termination or threaten other punishments in an attempt to control employee behavior. They unfortunately use more sticks than carrots resulting in employee resentment. And there are certainly internalized fears such as: I need to work extra hard on this project to avoid failing or we should not try – as we do not have sufficient knowledge that it will be successful. Our fear of failure or leaving a bad impression often prevents innovation and risk taking. Fear of failure or not finding the best solution often results in “analysis paralysis” which prevents action. This individual or group “overthink” is common when there is too much data and/or the situation is overly complex. Good managers or a consultant with the proper perspective can often help distill the problem down to a specific and actionable item(s). Sometimes a solution that simply “clears the bar” is sufficient and spending resources on anything else is a waste of time. As attributed to Voltaire: “Perfect is the enemy of good”. Even high performing and capable individuals succumb to Imposter Syndrome – the feeling that one is a “fraud” or are “out of your league”. Individuals who are otherwise talented, capable, and qualified, fear that they will be exposed and will doubt their abilities which shortchanges their accomplishments. In the end, this fear can sabotage their ultimate success. This underscores the need to prioritize objective performance measurements over subjective opinions – i.e. focus on the results you delivered against plan versus what opinion others may have of you. When fear of failure starts to interfere with one’s ability to function, it becomes a behavioral disorder known as Atychiphobia or Kakorrahaphobia. And when fear of rejection is added to the mix, it is Kakorraphiophobia. Even when not as extreme as a behavioral disorder, many of us worry about fear of rejection. And within the engineering community, the fear of rejection may contribute the (continued on page 14) WINTER 2021 MEPTEC REPORT | 9


Harnessing the Power of Data in Semiconductor Test Ken Butler Strategic Business Creation Manager Advantest

WE LIVE IN TRULY EXCITING TIMES if you are a data scientist. Every day, new methods are being developed to harvest, cleanse, integrate, and analyze data sources and extract from them useful, actionable intelligence to aid decision-making and other processes. The foregoing is true in many fields of endeavor, but certainly true for semiconductor design, manufacturing, and test. Even though some say

Moore’s law, shown in Figure 1, may be slowing in terms of the traditional method of scaling transistor critical dimensions, engineers are coming up with clever solutions to pack more functionality into a single product, including 3D fabrication, multi-chip packaging, stacked die applications, buried power rails, and others. Hence, the density of components in products is increasing rapidly.

Compounding this growth is an unprecedented increase in the demand for semiconductors, driven by several factors such as transportation electrification, online retailing, and the pandemic’s acceleration of working from home. One metric for tracking the overall semiconductor output is the number of transistors fabricated per year. VLSI Research has estimated that quantity for several decades,

Figure 1. Illustration of Moore's Law from 1970 to 2020. Licensed under CC-BY by the authors Hannah Ritchie and Max Roser.



Figure 2. Transistors sold per year.

as shown in Figure 2. In 2021, the total output will be approximately 1.6x1021 (1.6 billion trillion) transistors! Now let’s estimate the test data resulting from that hard-to-imagine number of devices. Even if some of those transistors are never tested because they are sold into applications with very low quality requirements (we will conservatively assume 20% of the total), and if each transistor is tested only once and produces only a single bit of pass/fail data (again, very conservative), the resulting test data rate for the entirety of 2021 would be greater than 40 terabits per second! And all that data must be analyzed, not only to determine which components are good and bad, but also for many other “bits” (pun intended) of intelligence, such as passing but “suspect” components, whether or not the product containing the components meets its datasheet and reliability requirements, whether or not the manufacturing and testing processes and equipment remain healthy and under control, and a host of other critical information. And this estimate only addresses data generated by the test function and doesn’t include other valuable sources of information like design, fab and test equipment, sensor, inspection, and calibration and maintenance data. So, we must deal with an ocean of data to streamline and optimize our production processes. It is a nice example of what Jack Morton from Bell Labs called the tyranny of numbers way back in 1958[1]. Besides all this phenomenal growth are other industry trends that are changing the landscape of semiconductor test solutions today. Some of those are listed in the Table 1 along with the resulting challenges that emerge from them. Two facets of test that are significantly 12 | MEPTEC REPORT


Table 1. Industry trends and challenges to semiconductor test.

influenced by these trends are product quality and the cost of test. New and subtle defect mechanisms combined with the push towards ever higher levels of quality increase the amount and complexity of testing and screening that must be done to ensure low parts per billion test escape rates. And all this testing in turns consumes more test time, thus increasing the cost of test. Semiconductor suppliers are looking largely to data analytics to solve these problems and keep the cost of test at reasonable levels without any compromise in outgoing quality or reliability. What are the types of solutions the industry is seeking? We will provide a few examples below. Solutions like these are part of Advantest Cloud Solutions, which is an open solution ecosystem providing integrated data sources and based

on a single scalable platform. We have worked with customers and our partner PDF Solutions to develop innovative products which leverage data to optimize test operations across the integrated circuit (IC) product lifecycle. Dynamic Parametric Test One of the earliest test steps performed on semiconductor devices is parametric test, also known as e-test or wafer acceptance test (WAT). This testing is performed during and at the end of wafer manufacturing. The structures being tested can be individual transistors, resistors, and other components that are fabricated in the scribe lines, which are the small spaces between each die on a wafer, as is illustrated in Figure 3 below[2]. Although these structures fill most of the scribe lines

Figure 3. Illustration of parametric test.

across the wafer, the testing is typically limited to a few sites on the wafer, for example 20 sites spread across the wafer surface. The test measurements provide valuable data used to monitor the health of the manufacturing process. When anomalies are detected, typically the material flow is stopped so the fab engineers can determine the cause of the problem. That often involves retesting material, collecting additional information, and performing additional manual analyses. As one can imagine, such events are disruptive and potentially costly to fab operations. Dynamic Parametric Test (DPT) was created to automate and speed up the resolution of these types of excursions. Using DPT on an Advantest V93000/SMU8 parametric tester with PDF Solutions Exensio® software, a set of user-definable rules are established and checked during parametric testing. When the rules detect an issue, actions are immediately triggered to accelerate the root cause identification process. The actions vary and could include changing the test algorithms, running additional tests, testing additional die, or some combination of the above. This process is illustrated in Figure 4 and Figure 5. In this example, a diode measurement is being performed. An out-of-specification measurement is detected, which triggers a DPT rule, and the test flow quickly adapts to a sweep of additional diode measurements across additional e-test sites on the wafer. This real-time update collects the additional data necessary to diagnose the cause of the issue without requiring a stoppage of material flow and the reloading and retesting of aberrant wafers, thus saving both time and cost. In the example cited here, the resulting root cause was quickly narrowed to a reticle or etch issue. Production Test Edge Computing Downstream from parametric test is production testing. There are multiple forms of production test. When the devices are still in wafer form, “wafer probe” or “wafer sort” testing is performed. After the die passing wafer sort have been singulated and packaged, they are subjected to “final test” (FT) or “package test”. There are also optional test steps such as system level test (SLT), where the die is subjected to a longer test that more closely

Figure 4. DPT detects out-of-spec diode parametric test.

Figure 5. DPT adaptively adjusts parametric test execution to collect additional data.

resembles its actual in-system operation, and burn-in, where the devices are tested, possibly for hours in duration, at elevated voltage and/or temperature to accelerate early life failures and measure product reliability. Historically, production tests are a “one size fits all” proposition, where, for a given product, the same suite of tests are applied to every die. But what is desired is to utilize data emanating from the test process itself to modify test content and execution so that each die sees the “right” tests, thereby optimally utilizing test resources in terms of data collection, cost, and quality. This process is referred to generically as adaptive test. One form of adaptive test is executed as a post-test operation, where, for example, wafer sort data is analyzed after the fact and downstream final test operations are adjusted based on that analysis. But much as in the DPT example above,

semiconductor suppliers are also pursuing real-time adaptive test processes during production, where test flow and content is altered during test execution, with low millisecond latencies. There have been several examples published in just the last few years that would work well when deployed as real-time adaptive test applications, including adaptive limit setting during search routines, predictive device trim, classifiers and device clustering, and burn-in optimization via at-risk device identification.[3] – [12] As a result, ACS Edge was developed to address this need for very fast, lowlatency and highly secure analytics during production test. It is a high-performance compute platform with a dedicated and secure communication channel to the tester. Analytics are wrapped in docker containers to ensure reliable execution regardless of the configuration of the compute environment. All information relating to WINTER 2021 MEPTEC REPORT | 13

TEST DATA the analytics and the data being analyzed are encrypted to prohibit unauthorized access that could compromise sensitive proprietary information. One good example of a potential realtime adaptive test application is the trim time reduction technique by Niranjan et al [6]. Trimming refers to the process of adjusting the performance of circuits during test, typically by altering the characteristics of one or more on-die components using electrical fusing or other techniques. Trim operations are often an incremental trial-and-error method to locate and set the optimal performance, and as such can be very time consuming, and thus costly. In this work, a product is described which requires 173 different trim operations. The researchers develop a machine learning technique that can examine the trim solutions for a subset of the 173 trim operations and predict the likely outcome of the remaining ones, thus drastically speeding up the overall trim process. The experimental results were reported by simulating the method on historic data. But an actual production implementation would a require high performance real-time computing capability such is are available using ACS Edge to keep test cost at reasonable levels. Conclusions As outlined above, the sources of semiconductor product data are becoming larger and more diverse. And IC developers and manufacturers are more chal-

lenged than ever to deliver devices ontime at the highest quality with the lowest possible cost. They look to advanced data analytics to extract the necessary intelligence to adjust manufacturing and test flows to adapt to an ever-changing environment. The test function plays a pivotal role because it directly interfaces with each device to extract and analyze the data needed to monitor and control product quality and performance. In this article, we have shown some examples of the types of solutions being deployed into production to address the foregoing challenges. We look forward to continued innovation in manufacturing and test data analytics. ◆ References [1] Various, "Tyranny of numbers," 2021. [Online]. Available: Tyranny_of_numbers. [Accessed 22 Oct. 2021]. [2] M. Bhushan and M. Ketchen, "Electrical Tests and Characterization in Manufacturing," in CMOS Test and Evaluation, New York, NY, Springer, 2015. [3] D. Neethirajan, X. C. K. Subramani, K. Schaub, I. Leventhal and Y. Makris, "Machine learning-based noise classification and decomposition in RF transceivers," in IEEE VLSI Test Symposium, Monterey, CA, 2019. [4] C. Xanthopoulos, D. Neethirajan, S. Boddikurapati, A. Nahar and Y. Makris, "Wafer-level adaptive Vmin calibration seed forecasting," in Design, Automation and Test in Europe, Grenoble, France, 2019. [5] M. Eiki, K. Schaub, I. Leventhal and B. Buras,

"In test flow neural network inference on the V93000 SmarTest test cell controller," in IEEE International Test Conference, Washington, DC, 2019. [6] V. Niranjan, D. Neethirajan, C. Xanthopoulos, E. De La Rosa, C. Alleyne, S. Mier and Y. Makris, "Trim time reduction in analog/RF ICs based on inter-trim correlation," in IEEE VLSI Test Symposium, Virtual, 2021.

[7] T. Y.-T. Kuo, W.-C. Lin, E. J.-W. Fang and S. S.-Y. Hsueh, "Minimum operating voltage prediction in production test using accumulative learning," in IEEE International Test Conference, Virtual, 2021. [8] M. Shintani, M. Inoue, T. Nakamura, M. Kajiyama and M. Eiki, "Wafer-level variation modeling for multi-site RF IC testing via hierarchical Gaussian process," in IEEE International Test Conference, Virtual, 2021. [9] M. Liu and K. Chakrabarty, "Adaptive methods for machine learning-based testing of integrated circuits and boards," in IEEE International Test Conference, Virtual, 2021. [10] S. Traynor, C. He, K. Klein and Y. Yu, "Adaptive high voltage stress methodology to enable automotive quality on finFET technologies," in IEEE International Test Conference, Virtual, 2021. [11] C. Nigh, G. Bhargava and R. Blanton, "AAA - Automated, on-ATE AI debug of scan chain failures," in IEEE International Test Conference, Virtual, 2021. [12] C. He, P. Grosch, O. Anilturk, J. Witowski, C. Ford, R. Kalyan, J. Robinson, D. Price, J. Rathert and B. Saville, "Defect-directed stress testing using I-PAT inline defect inspection results," in IEEE International Test Conference, Virtual, 2021.

COLUMN (continued from page 9) disproportionate number of introverts… Now that we have cataloged a sizable number of fears, what can we do? We can turn to history and see how individuals and groups have conquered their fears and achieved “the impossible.” “The only thing we have to fear is fear itself” is a good reminder to stop worrying as was best expressed by Franklin D. Roosevelt in his 1933 Presidential Inauguration address. When viewed historically and in light of FDR’s paralysis, hidden from public view, 14 | MEPTEC REPORT


FDR’s accomplishments and confidence are exceptional. History is full of stories where fear is conquered and long odds are overcome. Be sure to tap your corporate or industry experts who have indepth knowledge about how challenges were solved in the past. What is old is, or can be, new again… Perhaps we should turn to another Franklin for sage advice: “If you fail to prepare you are preparing to fail”. This aphorism is often attributed to Benjamin Franklin, however the true origin is unknown. Nevertheless, the key to success is planning and preparation even

when you are fearful of the outcomes. Just because you are fearful of the worst-case scenario does not justify ignoring it in your planning, or worse, not making any plans! I wish you “Happy Holidays” filed with light, joy, and wonderful plans for a successful New Year! For more of my thoughts, please see my blog As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆














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Catching Up with Ravi Mahajan Intel Fellow, Assembly and Test Technology Pathfinding Intel Corporation

Owing to a very diverse and accomplished association of MEPTEC members, there are many informative, instructional, and entertaining stories to be told. “Catching Up With…” will feature stories from and about our members. Ravi Mahajan (https://www.linkedin. com/in/ravi-mahajan-86746b1/) joined the MEPTEC Advisory Board in 2020. He was also profiled in Intel’s Newsroom’s “Behind the Builders” series ( us/en/newsroom/news/revolutions-ledchips-made-quilts.html) in June 2021. This interview was conducted via email and edited for clarity. You grew up in Mumbai, India and earned your bachelor’s degree at the University of Bombay. You then continued studying Mechanical Engineering and completed your master’s degree at the University of Houston followed by a Ph.D. from Lehigh University. All very strong academic institutions. Were there big surprises – academically and socially – between India and the US? Undergraduate education in India exposed me to a very broad set of engineering topics and information. A lot of the education focus was on information retention as opposed to directly checking how much of it I had understood and assimilated. The positive was that it strengthened my ability to recall different subjects and at various times in my career this helped me get a deeper understanding and appreciation of engineering research. We were mainly trained in systematic engineering analysis and there was significantly less emphasis on engineering creativity. 16 | MEPTEC REPORT


When I came to the US I was struck by the much greater emphasis on creativity, depth of understanding and a sense of fun especially in engineering competitions. Both systems produced thoughtful engineers but with a significantly different balance between analysis and synthesis. Over the years, I have tried to consciously increase my personal balance towards creativity because innovation is crucial to industries like ours. The other difference was the much greater approachability of teachers in the US compared to India and the much higher degree of informality. I remember being surprised when a student walked into an exam in Houston with a bottle of Coke. That would never have happened in India. It took me a while to adapt to the US system of research and education, but once I did, I was fascinated and to date after three decades I still find myself learning. I like the easy access to some of the top thinkers in academia and industry, the free flow of information and the many opportunities to network. The other thing I totally love is the library system in the US. It is an absolute pleasure to have such easy and comprehensive access to papers and books. What drove your particular academic path? Were you planning to stay in academia or were you working towards applied (commercial) research? Was there something specific that attracted you to Intel when in you joined in the 1990’s? After completing my Bachelor’s, I felt I had quite a bit more to learn and wanted to get a Master’s degree. I spent a semester pursuing a Master’s degree in India at IIT Mumbai before coming to

the US. During my stay at IIT, I developed an interest in Fracture Mechanics after reading a paper on mixed-mode fracture by Prof. Fazil Erdogan, which had a significant impact on my career. I moved to the University of Houston in 1986 and started working with Prof. Ravi-Chandar on experimental Fracture Mechanics using transmission caustics to study crack initiation and growth paths in polymers under mixed more loading. I wanted to continue on to a PhD and Prof. Ravi-Chandar encouraged me to apply to Lehigh which has a very strong program in Fracture Mechanics and overall, in Applied Mechanics. I wrote a letter to Prof. Erdogan asking if he would take me as a PhD student. I was thrilled when he accepted me and since that time, I have always proudly introduced myself as his student. Despite being a legend in the field with many demands on his time, he was very generous with it and he was an outstanding advisor. When I graduated in 1992, jobs were hard to come by, so I was open to either an academic or an industrial career. Since the early part of my PhD work was funded by SRC, my resume was in their database and caught Mostafa Aghazadeh’s attention at Intel. He was looking to grow his group of thermal and thermo-mechanical engineers and the job was a natural fit. I joined Intel in May 1992 and have not looked back since. What was your PhD dissertation on and is it relevant to what you have done commercially? What do you know now that would change this research? My PhD dissertation was on analytical and numerical solutions to calculate stresses in cracked orthotropic materials

when they are reinforced with thin films and subjected to thermo-mechanical stresses. I formulated the problem using singular integral equations, established the strengths of singularities at key stress points and developed numerical solutions to calculate stress intensities at key failure sites. The methods we developed could be used to study silicon and package reliability since most semiconductor devices are complex composites with multiple materials junctions that are potential failure initiation sites. After joining Intel, I continued working on this subject with Prof. Madenci at the University of Arizona, and we solved some very interesting problems in interface delamination. The only thing I would change in my PhD work is increasing interactions with industry experts to generate modeling tools they can use in real life applications. I was too focused on the underlying mathematics during my dissertation, and less on the making the results user friendly and that is something I would definitely change if I had to do this all over again. You started at Intel as an individual contributor working on thermomechanical stress analysis of packaged semiconductor devices. What was your primary focus? I started as a thermo-mechanical stress analyst, branched into thermal management in about a year of joining. In the early 1990s, Intel was still using ceramic packaging for its high-end processors and lead-frame based organic packaging for lower cost segments. My initial assignments were on solving cracking problems in ceramic packages and developing the right mold compounds and die attach materials for molded packages. I developed moisture absorption models to minimize pop-corning and to study delamination at the die attach interface. My PhD work came in handy for modeling stresses at the die-lead frame interface and in defining materials properties for die attach materials. I quantified the relative importance of modulus, CTE and glass transition temperature and found the right combination of properties to maximize reliability and certify the technology.

At Lehigh I had also worked on photomechanics, studying crack initiations under thermal shock loads, and learned about Moire interferometry and Digital Image Correlation (DIC). This came in handy when I joined Intel because I was able to introduce Moire at Intel and use it to solve some pretty significant problems in packaging.

After completing my Bachelor’s, I felt I had quite a bit more to learn and wanted to get a Master’s degree. I spent a semester pursuing a Master’s degree in India at IIT Mumbai before coming to the US. Later you become a group manager for Thermal Mechanical Tools and Analysis (TMTA), Assembly and Technology Development. What were the challenges of managing a sizable engineering and technician team plus a characterization lab? How did you balance the operational aspects of this role versus your research interests? In 1993, I was asked to start managing TMTA and around the same time assigned to help develop packaging solutions for Merced, initially jointly developed by Intel and HP for servers. One of the key challenges in Merced was to develop cost effective cooling solutions for a thermal design power (TDP) projection of 50W, which was a significantly higher than the previous generation TDP of ~15W. The HP collaboration was very fruitful, and I partnered with Chandrakant Patel (now HP Senior Fellow) and

a number of engineers at Intel including Ram Viswanath (now an Intel VP) to develop the vapor chamber-based heatspreader technology. Around the same time my team and others at Intel were also maturing heat-pipes for laptop cooling and we developed our understanding of the basic technology to create solutions for both application segments. I inherited a very good core TMTA team and had the flexibility grow it the way I wanted to, focusing on building a strong team of modeling experts and experimentalists. It was easy to blend my research interests with Intel’s goals and I could both manage a team and work on individual projects because the team I led was truly excellent. We established collaborations with Prof. Ken Goodson (Stanford), Prof. Bongtae Han (IBM and then at Clemson) to mature thermal metrologies and photo-mechanics techniques (Moire interferometry and DIC) and use them to solve complex thermal and thermo-mechanical problems. The investments initiated then continue on today (under Dr. Gaurang Choksi and his team); as a result, we have a very strong lab to complement our modeling capabilities. We strengthened our modeling competencies and focused on developing validated models to increase trust in their predictability. In 1994, Prof. Rao Tummala started the PRC in Georgia Tech and SRC was funding professors like Prof. Yogi Joshi and Prof. Ganesh Subbarayan to improve modeling and experimental tools. All of them became natural collaborators, helping mature modeling and experimental core competencies and training the next generation of engineers who found natural homes in Intel. Overall, the environment was excellent, there were great opportunities, thermal and thermo-mechanical challenges were growing, and we were well placed to participate in some significant technological changes. One of these big changes in the mid-1990s was when Intel decided to pursue organic flip-chip. Conventional wisdom was that the CTE mismatch between silicon and package was too high and the technology would not work. On the flip side, this was a great engineering challenge and both thermals and thermoWINTER 2021 MEPTEC REPORT | 17


mechanics were very relevant topics to be addressed in realizing the promise of organic flip-chip. TMTA was ideally placed, and it was easy to provide opportunities to a group of highly motivated engineers. Intel management followed an approach I really like i.e., they assembled a team of talented engineers and technicians, defined the broad parameters of the problem, gave them the resources and freedom needed and created an environment where technological problems could be surfaced and solved. Some of the top management in Intel’s Assembly and Test Technology Development today honed their skills and shaped their careers in the flip-chip development era. A part of your time as a group manager and later as an individual contributor coincided with Intel’s switch from very fast single core to multicore processors primarily due to the heat/power density. As individual cores become faster do you think we will approach this threshold again? Heat densities for single core processors were certainly high and projected to be higher when Intel switched to multi-core processors in 2004. Without getting into specifics about heat densities, they were a significant problem and we collaborated with leading industry experts like the late Prof. Avram Bar-Cohen (U Maryland) and Prof Suresh Garimella (Purdue) to develop some truly innovative technologies. Ravi Prasher (now at Lawrence Berkeley National Laboratory) was making a significant mark with his work on micro-channel cooling and thin film thermoelectrics and we benefited quite a bit from his leadership in the thermal area. The Heterogeneous Integration Roadmap (HIR) does a pretty good job of describing heat density envelopes we need to plan for moving forward and will allow researchers and technologists to benchmark their solutions against a common reference. You also worked on Design Process Development for package technology for mobile computing. Obviously, you understood the key packaging technology from your studies but 18 | MEPTEC REPORT


what did you learn about High Volume Manufacturing (HVM) that came as a big surprise? Intel built daughter cards (also called cartridges) for a few years in the 1990s and during this time I helped in the physical designs for cartridges used in mobile computing. The products had to ramp quickly in HVM, and we needed to establish systematic processes to develop integrated product designs that could be easily transitioned to HVM. My key learning was that crisp and complete communication was crucial when dealing with the large groups involved in manufacturing. Often times poor communication led to missteps and simple problems multiplied so I learned to be deliberate and pay extra attention to clarity. The good thing about Intel is that over the years we have developed communication processes and protocols to help scale manufacturing volumes smoothly. I was able to improve by leveraging the experience of people who had done this many times. In 2000 you became the Lead Architect for Packaging Technology Architecture, in Pathfinding in Assembly & Test Technology Development (ATTD). Is this more of a leadership role than a direct management role? If so, what are the advantages and disadvantages of working cross functionally versus directly supervising? Does this type of role give you more flexibility to innovate and research in new directions? This was more of a technical and strategic leadership role where I led and was part of cross-functional teams but had very limited management responsibilities. In the Intel culture we often form task focused teams that have the charter to solve specific issues or develop specific aspects of technology. I find this approach to be more flexible and more effective in matrixed organizations because you can focus on finding balanced solutions. I prefer this kind of structure because if the scope is well defined, you usually end up developing comprehensive solutions. Senior Intel leaders like Nasser Grayeli,

Bala Natarajan, Bob Sankman and Babak Sabi deserve credit for helping mature the concept of Pathfinding in ATTD and providing challenging opportunities. You invented the Silicon Bridge which is the core concept behind Intel’s EMIB (Embedded Multi-Die Interconnect Bridge). What was the inspiration behind the concept? How long did it take from initial idea to knowing there was a solid idea? And from proof of concept to commercialization and High-Volume Manufacturing (HVM) production? In the mid-2000s a few of us in the Pathfinding group began developing scaling models for bump and wiring densities (and for other aspects of packaging like thermals and power delivery) to be able to project targets for future generations of packaging. The idea was to plan for package technology features that did not limit silicon scaling, well in advance of deployment. We wanted to give ourselves runway to systematically work out key technology issues and develop cost effective packaging that allowed us to take full advantage of Moore’s Law scaling. We observed that package interconnect densities scaled linearly at the rate of ~10% gen over gen which was sufficient for homogeneous integration. I along with Sandeep Sane, invented Silicon bridge as a solution for achieving significantly higher interconnect densities than the linear 10%. These higher interconnect densities give product designers an option to partition a monolithic design into various components without compromising on interconnect density. It took us a while to develop the building blocks (e.g., handling and embedding thin silicon, fine pitch chip attach & underfill etc.,) needed to translate the concept to reality. In parallel, the need for these kinds of dense multi-chip packaging (MCP) solutions was maturing. In the early part of the past decade, it was evident that highperformance computing (HPC) applications could benefit significantly from high bandwidth, high-capacity dynamic random access memory (DRAM) connected by power efficient interconnects. This

provided additional impetus for EMIB development and by the time Intel publicly announced EMIB in 2014, we had a very good overall understanding of all aspects of the technology including HVM scalability. Through the Silicon Bridge / EMIB development did you ever doubt the technology would be successful? If so, any advice to others who may be doubting the viability of their ideas? We had to overcome quite a few difficult technical challenges and overcome economic hurdles along the way, which is typical for complex technologies; however, over the years I have learned to trust the ingenuity of engineers and Intel has some of the best packaging engineers on the planet. Technology development, especially complex technology integration requires focus, engineering skills and teamwork. Once we got the right people working on technology development, I was fairly confident that we could make EMIB successful because I (and a few other thought leaders in Intel) had not identified any intrinsic showstoppers in the technology. My only advice to developing and promoting a new idea is to be to be tenacious in pursuing it, be open to feedback especially if it helps you strengthen and expand your ideas. Almost five years ago, you were named as an Intel Fellow in recognition of your excellent work and leadership. What does being an Intel Fellow entail beyond the recognition? As Intel Fellow, I get a chance to participate in and drive more strategic discussions. I can help encourage innovation across the company and mentor talent; both are extremely important to build a deep and resilient organization. While I have always led cross-functional teams to solve key problems, after becoming Fellow, I have definitely received greater opportunities to lead more diverse teams and expand my scope. The gradual but significant increase in scope has helped with increasing influence both within the

company and in the overall packaging community. Next year you will have been with Intel for 30 years. Is this a surprise? Would you have thought this before you joined or when you first started? I had honestly not thought about where I would be thirty years later when I joined Intel. At that time, I was just happy to have a promising job. I seem to have

As Intel Fellow, I get a chance to participate in and drive more strategic discussions. I can help encourage innovation across the company and mentor talent; both are extremely important to build a deep and resilient organization. caught the train at the right time so to speak. Intel was fast paced and challenging from day one and continues to be that way even today. I had excellent managers and mentors who helped open doors, and I was rarely ever held back. So overall Intel has been a great place to work and if anything has more opportunities today than it did when I started. You’ve mentioned Thomas Kuhn’s book “The Structure of Scientific Revolutions” and the shift in your thoughts about research and the scientific method. Would you mind sharing that again? I audited a class on Science and Technology at the University of Houston taught by Prof. John Lienhard because I was

trying to clarify my own understanding of the subject. It was a fascinating class where he discussed the philosophy of science and the impact of technology on the direction of history. Thomas Kuhn’s book was required reading for the course. Around the same time, I took an excellent class in linear algebra taught by Prof. Louis Wheeler where he discussed the concepts of orthogonality in multidimensional spaces. As these concepts began to sink in, I realized that there were deeper truths underpinning mathematical thought. In that backdrop, “The Structure of Scientific Revolutions” was a revelation; it was cogent, complete (at least I thought so then) and to my way of thinking, a pragmatic description of scientific behavior. It reduced the process of science from being esoteric to an explicable process and gave me a framework I could understand and use to learn more about different developments in science. So, I spent time understanding the historical evolution of non-Euclidean geometry, astronomy, and complex algebra and their progress seemed to fit in Kuhn’s overall construct. The idea of paradigms and normal science made intuitive sense, put my graduate work in context and gave focus and direction to my approach. I don’t naturally keep up with literature in this field so had not read too many criticisms or analyses of Thomas Kuhn’s work till recently when I read “Theory and Reality” by Peter Godfrey-Smith. I would highly recommend this book if you want to get a sweeping historical perspective of the nature of science. You have been extremely active in many industry associations and organizations beyond MEPTEC including IEEE, ASME, SEMI-THERM, Semiconductor Research Corporation (SRC) at many different levels. And you have been recognized with several significant awards. Why is it important to you to actively engage outside of Intel? How would you encourage others to participate in industry organizations? And what should we do to get companies to see the benefits to enable and encourage their employees to do likewise? WINTER 2021 MEPTEC REPORT | 19


I firmly believe that active engagement with industry associations and research entities is crucial for the advancement of technology, driving standards, and just as importantly for maturing the next generation of engineers. It is also a way of giving back to the community, sustaining its vibrancy, and getting a broader perspective of the field. For instance, if you look at the work being done in defining the Heterogeneous Integration Roadmap, you can easily see that Heterogeneous Integration is critical to the advancement of computing and communications and working in this area brings tremendous opportunities and challenges. The SRC has done a great job of defining decadal challenges as well and the work at Intel and in different packaging research centers, DARPA and other US Government programs shows the value of HI. The opportunities are tremendous and we need to engage broadly as a community, understand and integrate diverse ideas, and define a set of research challenges to be solved for success. No one company or group alone can do this, and broad community engagement is crucial. Exposure and participation in panels, conferences and workshops is essential for engineers to maintain their edge, stay updated and contribute to the field. These kinds of engagements also help (in my opinion) employee morale and retention. Recent MEPTEC, IEEE, and ASME InterPACK panels and workshops are excellent examples of forums where we have had broad, active engagement and I believe they are essential to the field.

tional level of technical depth and discussion. It is this depth and ability to bring people together for comprehensive and meaningful discussions that I like the most. I think what we should continue to do in MEPTEC is to tailor events so that we are moving things forward and building on discussions in the recent past.

What should MEPTEC be doing to increase its value to the members and the industry in general? What does MEPTEC do that stands out among the organizations you have been or are involved with?

Writing technical articles and editing takes a little getting used but once you get over the initial hesitation, it can be quite rewarding. I have always found that writing a good paper requires clarity of thought, expression, and organization. I use a mental construct I borrowed from one of my managers and colleagues, former Intel Fellow Bob Sankman. He said all presentations and papers are essentially a means of telling a story. I structure all my papers by trying to create as complete a story as possible with a simple linear flow. Simple sentences in active voice are probably the best way to

I would like to first commend MEPTEC on an excellent job of hosting industry talks, panels, and workshops. This has been my first full year of engagement with MEPTEC, and I have thoroughly enjoyed all the events I was able to attend. They complemented other conferences very well and provided an addi20 | MEPTEC REPORT


How has Mumbai changed during your lifetime? Has the adoption of electronic technology greatly improved the quality of life or otherwise had a larger impact in Mumbai / India than say the US in your lifetime? Mumbai has changed tremendously in my lifetime. Some places like my high school have improved gradually, while retaining the same comfortable feel of tradition and stability. Other places and events have changed beyond recognition. Banking has modernized, there are way more restaurants and shopping malls, traffic is heavier and even with new flyovers, it is difficult to get around. Overall, you can see the effect of modernization everywhere and what I find most heartening is that there is an enthusiastic engineering and business community that is very aware of all the latest technology and business trends, thanks to the internet and that bodes well for growth. You do a significant amount of detailed technical writing and editing for patents and journals, any advice for those who find this difficult to do or comprehend?

go because they create the most impact in work like ours. I have found that creating a draft and then coming back to it the next day to polish it, is for me an effective way of maturing a paper or a presentation. Being an editor essentially is to first take the viewpoint of a reader and I search for coherence and clarity first and then completeness. Companies like Intel that blend engineers from diverse backgrounds have a rich source of ideas. I am part of the intellectual property (IP) committee in Intel and get to see these ideas regularly. The same ideas of clarity, completeness and simplicity apply to describing ideas. I personally like simple and well annotated pictures or process flows to explain an idea. How do you spend your leisure time? Any favorite places to visit or hobbies? I spend quite a bit of time with my family both at home and travelling together. Favorite places to visit include the San Francisco Bay Area, India, New Zealand, and Australia. I am a big fan of Cricket and other fans will understand this special memory: my family and I have watched the first day of two Boxing Day matches in Melbourne and it was the one and only time I saw Sachin Tendulkar bat (he only lasted one ball!). I have a deep interest in history especially in the evolution of empires, people, religion, and culture. Over the years, I have accumulated a large collection of books on different topics i.e. history, philosophy, mathematics, fiction, and cultures and read and re-read them. The two cities I absolutely loved visiting were Istanbul and Athens; I had wanted to visit them since I was a child and they lived up to expectations and more. I also have a love of and learned north Indian classical music and occasionally help host concerts in Phoenix. I have had the pleasure of hosting some of today’s top artists and being able to talk to them about their art and listening to them live makes for some memorable experiences. ◆

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