TECHNOLOGY
Front-end Product Co-development in the New SiP Era Hui Liu, Senior Manager, Packaging Design, Intel Nate Unger, Director, Packaging Design, Intel John Xie, Director, Packaging R&D, Intel
THE SEMICONDUCTOR INDUSTRY is entering into a new era for System in Package (SiP) being driven by miniaturization, heterogonous integration, and high computing power requirements from applications, such as internet, mobile, cloud, and IoE. 2.5D/3D SiP provides cost effective, feature enriching, and fast time to market (TTM) solutions and is becoming more and more attractive. The slowdown of silicon technology scaling is accelerating the wider adoption of SiP as well. Figure 1 shows IC industry evolution path. From component co-development aspect, the industry experienced silowork, team-work, traditional Backend Die-package Co-design (BDC), and is entering into more advanced co-architecting and true product co-development era.
The traditional backend die-package co-design methodology, which has been evolving mostly around monolithic/SoC solutions, is characterized by these four attributes: • Die and package are treated as two separated designs • Packaging engineering is considered backend effort - Help address silicon design issues • Collaboration is mostly between IC engineering and packaging engineer ing • Collaboration happens mostly in design stage
EMIB
Figure 2. Stratix™ 10 FPGA
In the new SiP era, product co-devel-
opment faces more and bigger design, manufacturing, and quality challenges due to its overall complexity, especially in chip-to-chip (C2C) connection and communication. The traditional Backend Die-package Co-design methodology is no longer good enough for addressing these new SiP challenges. A new co-
Codev
Silo work
Team work
Codesign
Coarch
Codev
PKG
LF WB
FC MCM
S-die PoP
2.5/3D
New SiP
IC
VLSI
ULSI
SoC
3D-IC
?
~1990
~2000
~2010
Future
PC
Internet
Mobile
Cloud IoE
Year
App
1960 - 1980s
Pre-PC
Figure 1. IC Industry Evolution
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SPRING 2016 MEPTEC REPORT 21