Design of cmos phase locked loops from circuit level to architecture level 1st edition behzad razavi

Design of CMOS phase locked loops from circuit level to architecture level 1st

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3.4.2 Reference Oscillator Phase Noise

3.4.3

5.5.1

6.1.2 Effect of Flicker Noise

6.2

6.3.1 Design

6.4 Class-C Oscillators

6.4.1 Design Example

6

8.10.2 Shaping of VCO Phase

8.10.3 Charge Pump Noise

8.10.5 Supply Noise

9.2 PFD Design

9.3 Charge Pump Design

9 3 1 First CP Design

9.3.2 Second CP Design

9.3.3 Third CP Design

9.3.4 Fourth CP Design

9.3.5 PFD/CP Interface

9 4 Behavioral Simulations of PLL

9.4.1 Loop Simplification

1

Oscillator Fundamentals

At the heart of every phase-locked loop lies an oscillator, playing a critical role in the performance that can be achieved. For this reason, we devote five chapters of this book to oscillator design. This chapter aims to build a solid foundation for general oscillator concepts before we delve into high-performance design in Chapters 3-6. We begin with basic concepts and discover how a negative-feedback system can oscillate. We then extend our view to ring and LC oscillators

1.1 Basic Concepts

If we release a pendulum from an angle, it swings for a while and gradually comes to a stop The “oscillation” begins because the original potential energy turns into kinetic energy as the pendulum reaches its vertical position (Fig. 1.1), allowing it to continue its trajectory to the other extreme angle (position 3), at which the

Position 1 Position 2 Position 3

1.1 A pendulum acting as an oscillatory system.

energy is again in potential form The oscillation stops because the friction at the hinge and the air resistance convert some of the pendulum’s energy to heat in every oscillation period

In order to sustain the oscillation, we can provide external energy to the pendulum so as to compensate for the loss caused by the hinge and the air. For example, if we give the pendulum a gentle push each time it returns to position 1, it will continue to swing. If the push is too weak, we undercompensate, allowing the oscillation to die; if the push is too strong, we overcompensate, forcing the swing amplitude to increase from one cycle to the next We also note that the period of oscillation is independent of the amplitude 1

The above mechanical example points to several ingredients of an oscillatory system: (1) an initial “imbalance,” i.e., an initial condition or packet of energy (provided by bringing the pendulum to position 1); (2) a tendency for one type of energy to turn into another and vice versa; and (3) a sustaining mechanism that replenishes the energy lost due to inevitable imperfections Not all oscillator circuits contain all of these ingredients, but it is helpful to bear these concepts in mind 1

Figure

Example 1.1

Repeat the foregoing experiments with a “lossless” pendulum.

Solution

If released from an angle, such a pendulum oscillates indefinitely Now, if we give a push each time the pendulum reaches the left end, then the swing keeps increasing due to the additional energy that we inject into the system in each cycle. Note that this indefinite growth does not occur if we give a push at a frequency other than the pendulum’s natural oscillation frequency.

The above example serves as a guide in our analysis: if a system has a tendency to oscillate at a frequency ω0 , then it creates a growing oscillatory output in response to an external injection at a frequency ω0 . From another perspective, such a system indefinitely amplifies a periodic input at this frequency.

1.2 Oscillatory Feedback System

We know from basic analog design that a negative-feedback system can become unstable. We exploit this property to construct oscillators

Let us first study oscillation in the frequency domain. Consider the feedback system shown in Fig. 1.2(a), where the negative sign at one adder input signifies negative feedback at low frequencies. Depicted in Fig.

Figure 1.2 (a) Simple feedback system, (b) realization using an op amp, (c) open-loop frequency response showing zero phase margin, (d) signal inversion at ω0 , and (e) propagation of a sinusoid at ω0 around the loop

1.2(b) is an implementation example, which, in response to a low-frequency sinusoidal input, simply acts as a unity-gain buffer. Note that the op amp exhibits negligible phase shift at low frequencies.

How can the arrangements in Figs 1 2(a) or (b) oscillate? Writing the closed-loop transfer function of the former as

we observe that the denominator falls to zero if H(s) = 1 for some value of s. If X (s) is a sinusoid, then s = jω0 and we must have H(jω0 ) = 1. The open-loop frequency response thus exhibits a unity magnitude and a 180◦ phase shift at ω0 [Fig. 1.2(c)]. We note that (Y/X)(jω0 ) → ±∞, concluding that the system provides an infinite gain for such a sinusoid As surmised in the previous section, this scenario suggests an oscillatory loop

Let us examine the condition H(jω0 ) = 1 more closely: this equality means that H(s) itself inverts the input at this frequency [Fig. 1.2(d)]. That is, H(s) has so much phase shift (or delay) at ω0 that the overall feedback becomes positive. This can be seen by setting the main input, X, to zero, breaking the loop, and applying a stimulus at this frequency [Fig 1 2(e)], and following it around the loop The returned signal is in phase with the test voltage, Vt We say the loop contains a 180 ◦ phase shift due to the nominally negative feedback and another frequency-dependent 180◦ phase shift arising from H(s). These two phase shifts must not be confused with each other.

The total phase shift of 360◦ at ω0 implies that the signal returns to enhance itself as it circulates around the loop This phenomenon results in amplitude growth because the returned signal is at least as large as the starting signal, i e , because |H(jω0 )| = 1 We therefore summarize the conditions for oscillation as

H(jω0 )| = 1 (1.2)

(jω0 ) = 180◦ , (1.3)

which are called “Barkhausen’s” criteria. We also call H(jω0 ) = 1 the “startup condition.” Note that H(jω) generally has a complex value at ω = ω0 and becomes real only at ω0 .

The oscillation buildup can also be studied in the time domain. We begin with the arrangement shown in Fig. 1.3(a) and note that, with H(jω0) = 1, the output is equal to the input but shifted by 180◦ . If the loop

is closed [Fig. 1.3(b)], the output is subtracted from the input, yielding a larger swing at A. This signal is again inverted and subtracted from the input, leading to indefinite grow of the amplitude [Fig 1 3(c)]

In summary, a negative-feedback system can generate a growing periodic output in response to a sinusoidal input if its loop gain reaches 1 at a finite frequency, ω0 . But does such a system oscillate if we apply no input? Yes, the wideband noise of the devices within the loop exhibits a finite energy in the vicinity of ω0 , producing a small component that circulates around the loop and causes oscillation. For example, as shown in Fig 1 4, a noise source, Vn, at the input of H(s) yields an output given by

Figure 1.3 Growth of an input sinusoid around the loop with time.

Figure 1.4 Effect of noise injected into a closed-loop system.

thereby experiencing infinite gain at s = jω0 That is, even though Vn is infinitesimally small at ω0 , Y can assume a finite swing.

The foregoing analysis suggests that, to test for oscillation, we can inject a sinusoidal input at any point and observe the response at any point so long as both points are within the loop.2 In Fig. 1.4, for example, Vn can be placed at the output of H (s) Similarly, the point of observation can be P rather than Y By the same token, the injection and observation points can be the same, pointing to another method of finding the oscillation conditions that is suited to some circuits. We inject a current at ω0 into a node within the loop and examine the voltage at that node, i.e., we compute the impedance. If the voltage and hence the impedance go to infinity at ω0 , the circuit can oscillate. Figure 1.5 depicts the concept. We return to this point in Section 1 5 3

1.3 A Deeper Understanding

Analysis Methods In the analysis of oscillators, we first wish to determine how the devices and the bias conditions must be chosen so as to guarantee oscillation. Our previous studies point to three methods using the small-signal model of the circuit:

1. Open the loop and enforce the startup condition,H (jω0 ) = 1, thus obtaining the circuit design requirements.

2. In analogy with the ideal pendulum example, release the closed-loop circuit with an initial condition and determine the design parameters for oscillation. The initial condition can be created by an impulse of current injected into a node within the loop or simply by assuming a finite voltage on a capacitor

3. Inject a sinusoidal current into a node in the closed-loop circuit and compute the conditions necessary for the impedance seen at this node to go to infinity. This method is not universal but still proves helpful.

A given oscillator topology may lend itself more easily to one method than to another. The following examples illustrate these thoughts

Figure 1.5 Infinite port impedance in an oscillatory circuit

Example 1.2

A common-source (CS) stage is placed in a feedback loop as shown in Fig. 1.6(a). Can the circuit oscillate?

Figure 1.6 (a) Feedback around a CS stage, and (b) equivalent circuit.

Neglect other capacitances and channel-length modulation

Solution

To retain consistency with the block diagram of Fig. 1.2(a) and noting that the CS stage inverts at low frequencies, we denote the circuit in the dashed box by H(s) (why?) Applying the first analysis method, we write

Owing to its single pole, H(s) can contribute a maximum phase of 90◦ (at infinite frequency), disallowing H(jω0) = 1. Thus, the loop cannot oscillate.

Let us try the second method by applying an initial condition to CL Since M1 operates as a diodeconnected device, the small-signal model reduces to that shown in Fig 1 2(b), revealing that CL simply discharges through RD||g 1 m and no oscillation occurs. Similarly, the third method gives an impedance of RD||g 1 m ||(CL s) 1 seen at the output node, indicating that it cannot go to infinity at any s = jω.

Example 1.3

The common-source stage studied in the previous example does not exhibit enough phase shift to allow oscillation. It is possible to insert an additional delay in the loop in the form of a delay line as shown in Fig 1 7(a) Here, a voltage change at the drain takes ΔT seconds to reach the gate Determine the startup condition and the frequency of oscillation. Neglect all capacitances and channel-length modulation.

Solution

Using our first analysis method, we break the loop as illustrated in Fig. 1.7(b) and write

(The transfer function of the ideal delay line is equal to e sΔT ) We seek H(jω0) = 1, i e , gmRD exp( jω0ΔT ) = 1. It follows that, if |H(jω0)| = 1 and H(jω0) = 180◦ , then

Figure 1.7 (a) CS stage with a feedback delay line, (b) open-loop system, (c) computation of impedance at one node, and (d) illustration of infinite impedance at ω0

The first equation is the startup condition, and the second can be expressed as

where f0 = ω0/(2π). The circuit therefore oscillates with a period equal to 2ΔT . Note that the delay line introduces a phase shift of 180◦ at ω0.

We can apply the third method by computing the closed-loop impedance seen at, for example, the output node. From the arrangement depicted in Fig. 1.7(c), we haveVG = VX exp( sΔT ) and hence a small-signal drain current of gmVX exp( sΔT ) A KCL at the output node gives

and hence

We observe that if the startup condition, gmRD = 1 is fulfilled, then the denominator goes to zero for s = jω0 = j2π/(2ΔT ). The reader is encouraged to apply the second analysis method as well.

To gain more insight, let us compute the output impedance of the circuit while excluding RD. If RD = ∞ in Eq. (1.13), we have

which reduces to VX/IX = 1/gm at s = jω0. Interestingly, the loop comprising M1 and ΔT presents a negative resistance, which cancels the “loss” due to RD if gmRD = 1 [Fig 1 7(d)]

Oscillation Growth It is important to distinguish between two cases when H(jω0) = 1 and the loop is stimulated In response to an initial condition (or an impulse), the circuit oscillates with a constant amplitude [Fig 1 8(a)] as did the ideal pendulum in the previous section On the other hand, with a sinusoidal excitation at ω0, the oscillation amplitude continues to grow [Fig. 1.8(b)] (unless some other mechanism, e.g., a nonlinearity, stops the growth).

Figure 1.8 Response of an oscillatory system to (a) an impulse, and (b) a sinusoid at ω0

Startup Condition Revisited The condition H(jω0 ) = 1 places the feedback loop at the edge of oscillation, failing to hold if process, voltage, and temperature (PVT) variations cause a slight drop in the loop gain. Moreover, this condition prohibits large-signal oscillations: if the oscillation amplitude grows to the extent that the circuit becomes nonlinear, the loop gain may drop below unity, violating the startup condition. The following example illustrates this point.

Example 1.4

Figure 1 9(a) shows a differential realization of the oscillator studied in Example 1 3 If gmRD = 1, explain

1.9 Differential pair with feedback delay lines.

why the oscillation amplitude remains small.

Solution

The circuit operates such that VX and VY swing differentially and so do VA and VB. If VA and VB have small swings, the differential pair exhibits a unity voltage gain, sustaining the oscillation. The circuit cannot operate with large swings because the gain would then drop below unity at the peaks of VA and VB .

For the two reasons mentioned above, namely, PVT variations and gain drop due to nonlinearity, oscillators are typically designed with |H(jω0 | > 1 [and H(jω0) = 180◦].

Example 1.5

The differential oscillator of Fig. 1.9 is redesigned for voltage swings that are large enough to ensure ISS is entirely steered to the left or to the right. Determine the small-signal loop gain.

Figure

Solution

Suppose the four nodes carry a peak-to-peak swing of V0 . For M1 or M2 to carry all of ISS , we have |VA VB |max = V0 = √2(VGS VT H ) [1], where VGS VT H denotes the transistors’ overdrive voltage in equilibrium (when VA = VB) With complete switching of the differential pair, we also have |VX VY |max = ISS RD = |VA VB|max It follows that

and hence

because gm = ISS /(VGS VT H ) in equilibrium (where ID1 = ID2 = ISS /2).

With |H(jω0 )| > 1 and H(jω0 ) = 180◦ [Fig. 1.10(a)], we face an interesting puzzle. If, for example,

Figure 1.10 (a) Open-loop response with gain greater than unity at ω0 , and (b) impulse response of closed-loop system.

H(jω0 ) = 2, then the closed-loop gain is equal to H(jω0 )/[1 + H(jω0 )] = +2 and not infinity! How then does the circuit oscillate? This result shows that the loop does not oscillate at ω0 . Rather, the circuit may find another value of s such that H(s)/[1 + H(s)] → ∞, i.e., H(s1 ) = 1, where s1 has a complex value, σ1 + jω1 , and σ1 > 0. We study this case in Appendix I but should mention here that such a value of s leads to a growing sinusoid even with an impulse input [Fig. 1.10(b)], a point of contrast to the situation depicted in Fig 1 8(a) [As explained in Appendix I, the condition |H(jω0 )| > 1 does not always guarantee oscillation, but suffices for typical oscillators.]

In the case of |H(jω0 )| > 1 and H(jω0 ) = 180◦ , our node impedance test must also be revisited. For example, if gmRD > 1 in Eq. (1.13), then |VX/IX| becomes real and negative at s = jω0 (why?). In particular, the output resistance seen in Fig. 1.7(d) is now “stronger” than RD, leaving a residual negative component after canceling RD This component thus allows the oscillation amplitude to grow

Positive Feedback at dc

We have seen that positive feedback at a finite frequency, ω0 , can cause oscillation. But what happens if we have positive feedback at dc (low frequencies) as well? For example, if we cascade two CS stages as shown in Fig. 1.11 to obtain a greater phase shift, the feedback becomes positive at dc. If the low-frequency loop gain is greater than unity, this circuit latches up This can be seen by assuming a small upward perturbation in VX, which leads to a greater, downward change in VY This change in turn causes even a larger upward change in VX, etc. We say the circuit “regenerates” until VX reaches VDD and VY falls to a low value, turning M1 off. This circuit is in fact used as a memory cell.

Figure 1.11 Two CS stages in a feedback loop.

To avoid latch-up, we design oscillators such that, at dc, the feedback is negative or, if it is positive, the loop gain is well below unity.

Oscillator Topologies Numerous oscillator topologies have been introduced over the years. Examples include “phase-shift,” “Wien bridge,” “relaxation,” “multivibrator,” “ring,” and LC oscillators In this book, we deal with primarily the last two as they are most commonly used in integrated circuit design.

1.4 Basic Ring Oscillators

Ring oscillators are popular in today’s phase-locked system for their design flexibility and wide frequency tuning range. This section builds the foundation for these oscillators and Chapters 3 and 4 introduce advanced ring concepts.

We have seen that a single common-source stage does not provide sufficient phase shift to allow H(jω0 ) = 180◦ Even a loop employing two CS stages fails to oscillate because H(jω) reaches 180◦ only at ω = ∞ We therefore surmise that a three-stage “ring” can satisfy both H(jω0) = 180◦ and |H(jω0)| = 1. Depicted in Fig. 1.12(a), this simple ring oscillator has negative feedback at low frequencies

Figure 1.12 (a) Three CS stages in a feedback loop, (b) loop transmission, and (c) node waveforms.

and can be analyzed by assuming identical stages. The circuit in the dashed box is called H(s) to comply with the negative-feedback system shown in Fig 1 2(a) We write

where channel-length modulation and other capacitances are neglected It follows that

Figure 1 12(b) sketches the magnitude and phase behavior For |H(jω0 )| = 1, we have

and hence

Also, H(jω0 ) = 180◦ yields

and

Interestingly, (1.20) and (1.22) give

In other words, each stage must provide a low-frequency voltage gain of 2 to guarantee oscillation. A few properties of the above oscillator are worth noting. First, at ω0 , each stage exhibits a phase shift of 60◦ arising from its output pole plus 180◦ due to the low-frequency inversion of a CS amplifier Thus, the waveforms at X, Y , and Z in Fig. 1.12(a) have a phase separation of 240◦ (= 120◦) [Fig. 1.12(c)]. Second, CL can represent all of the transistor capacitances with reasonable accuracy. For example, at Y , CL includes CGS 2 , CDB1 , and the Miller effect of CGD2 . Since the waveforms in Fig. 1.12(c) suggest equal swings at the three nodes, we can assume a large-signal voltage gain of 1 from Y to Z and write the Miller capacitance as Cmill = [1 ( 1)]CGD2 = 2CGD2 3

Example 1.6

A ring oscillator similar to Fig. 1.12(a) incorporates N identical CS stages, where N is an odd number. Determine the startup condition and the frequency of oscillation

Solution

With an odd number of stages, the loop provides negative feedback at low frequencies, necessitating a frequency-dependent phase shift of 180◦/N per stage for oscillation. That is,

24) and hence

As N increases, ω0 falls because each stage must exhibit less phase shift To ensure a unity loop gain at this frequency, we must have

obtaining

As N increases, the required low-frequency gain decreases.

Oscillation Amplitude As explained in the previous section, a loop gain of unity at ω0 produces only a small oscillation amplitude. In practice, the three-stage ring of Fig. 1.12(a) must generate nearly rail-to-rail swings, requiring a small-signal, low-frequency gain higher than 2 per stage. The reader is encouraged to prove that the closed-loop poles of the circuit lie in the right half plane if gmRD > 2.

We can visualize the oscillation startup by assuming identical stages and hence equal initial voltages at all three nodes As shown in Fig 1 13, with a small perturbation (e g , due to the noise of the devices), the circuit

begins to oscillate and the amplitude grows. The growth continues until the nonlinearity of each stage causes the gain to drop near and at the peaks. We say the “average” loop gain falls to unity due to the nonlinearity.

Example 1.7

Equation (1.20) implies that ω0 is a function of gm while Eq. (1.22) does not. Explain this discrepancy.

Solution

Since Eq (1 22) derives from the phase shift criterion, it approximately applies even to large-signal operation After all, the phase shift per stage must be 60◦ whether the swings are large or not. Equation (1.20), on the other hand, begins to lose its validity as the loop enters the large-signal regime.4

We recognize that the oscillation amplitude is determined by the circuit’s nonlinearities if | H(jω0 )| > 1; otherwise, the amplitude would grow indefinitely. The calculation of the amplitude is difficult in the circuit of Fig. 1.12(a) because the additional 60◦ phase shift requires that the CS stage be treated as a nonlinear dynamic system. Fortunately, however, the oscillator topologies used in practice provide well-defined voltage swings, as seen in subsequent chapters

4

Figure 1.13 Initial growth of VX

Ideal Waveforms We have seen that ring oscillator waveforms are close to a sinusoid if |H(jω0 )| = 1 and begin to resemble a square wave if |H(jω0 )| is well above unity. We can then ask what the desirable waveform of an oscillator should be. Most applications prefer sharp transitions to ensure rapid turn-on and turn-off of the devices that are driven by the oscillator. For example, a radio-frequency (RF) mixer sensing the output of an oscillator exhibits less noise with abrupt edges Thus, if possible, we wish to design for square waveforms.

1.4.1 Inverter-Based Rings

A common implementation of ring oscillators employs CMOS inverters rather than resistively-loaded CS amplifiers as gain stages Shown in Fig 1 14(a) is an example If the circuit begins with VX = VY = VZ ,

Figure 1.14 (a) Three-stage inverter-based ring oscillator, (b) node waveforms, (c) realistic signal shape, and (d) waveform for a five-stage ring.

each stage exhibits a small-signal voltage gain of (gmN + gmP )(rON ||rOP ), which typically exceeds 2 The noise of the devices then causes regeneration until the oscillation reaches rail-to-rail voltage swings. Note that the negative feedback at dc prevents latch-up.

What if, upon power up, the ring begins with one node at zero? For example, if VX = 0, then VY = VDD and VZ = 0; the third inverter thus raises VX toward VDD In other words, VX = 0 cannot be a stable state Figure 1 14(b) depicts the circuit’s steady-state waveforms, revealing that a transition on one node causes another on the next node after one gate delay, TD. The total oscillation period is therefore equal to 6TD.

The reader may wonder if the oscillation frequencies obtained from our small-signal and large-signal analyses are equal. For the three-stage ring of Fig. 1.14(a), the former analysis and Eq. (1.22) give ω0 = 2πf0 = √3/[(rON ||rOP )CL], where CL denotes the total capacitance seen from each node to ground The latter analysis, on the other hand, predicts f0 = 1/(6TD). These two values are generally unequal, with 1/(6TD) correctly predicting the frequency, but the small-signal result gives additional insight.

Some Properties

The actual waveforms of the foregoing three-stage ring oscillator are less sharp than the square waves in Fig 1 14(b) but not as gradual as a sinusoid Illustrated as an example in Fig 1 14(c), VX changes its direction as soon as it reaches VDD or ground because of the short delay around the loop By comparison, a five-stage ring provides an oscillation period of 10TD, allowing some “relaxation” time for the high and low levels of VX [Fig. 1.14(d)].

A few digital design principles reveal other properties of ring oscillators. First, since the delay of an inverter falls as VDD increases, the oscillation frequency is inversely proportional to the supply voltage As explained in Chapter 3, the supply sensitivity of ring oscillators proves problematic in most applications Second, each inverter draws an average power of f0 CLV 2 DD, leading to a total power consumption of nf0CLV 2 DD for an n-stage ring.

1.5 Basic LC Oscillators

LC oscillators have some advantages over ring configurations, specifically, lower phase noise and the ability to operate at higher frequencies. We therefore employ LC topologies in many applications.

The analysis and design of LC oscillators heavily rely on the properties and modeling of LC tanks It is thus necessary to begin our study with basic LC circuits

1.5.1 LC Circuit Concepts

We know from basic circuit theory that the behavior of an ideal capacitor is expressed as I = C1 dV /dt in the time domain and as V = I/(C1 s) in the frequency domain Similarly, an ideal inductor can be modeled by V = L1 dI/dt or V = (L1 s)I. The parallel combination of these two components exhibits interesting properties. Illustrated in Fig. 1.15(a), such an impedance is dominated by L1 at low frequencies and by C1

Figure 1.15 (a) Ideal parallel LC tank, and (b) its impedance characteristics

at high frequencies (why?). We thus expect both |Z1 | and Z1 to act accordingly. As shown in Fig. 1.15(b), Z1 behaves inductively for ω < ω0 = 1/√L1 C1 and capacitively for ω > ω0 . At the resonance frequency, ω0, the two reactances cancel each other, producing Z1 = (L1jω0 )||[1/(C1 jω0 )] = ±j∞ The LC tank exemplifies a “resonator”

Let us now incorporate a more realistic inductor model. Implemented as a metal wire, L1 suffers from a finite series resistance, RS [Fig. 1.16(a)]. We say L1 is “lossy” because the current flowing through it

1.16 (a) Lossy LC tank, and (b) its equivalent model

causes thermal dissipation in RS . This physical model, however, gives little intuition, especially if we seek a resemblance between the behaviors of the ideal and the lossy tanks As seen later, we prefer a model that represents the loss by a parallel resistance, Rp [Fig 1 16(b)] Of course, the tanks of Figs 1 16(a) and 1 16(b) cannot be equivalent at all frequencies (why?) but one circuit can approximate the other for some frequency range.

To derive the values of Lp and Rp in terms of L1 and RS, we omit C1 and equate Z1 and Zp:

Figure

For sinusoidal signals, s = jω, and

This equation holds in general only if the imaginary and real parts are independently zero, yielding

Calculating Rp from the former and substituting in the latter, we have

As explained later in this section, typically

and

From Eq (1 32), we obtain

It is important to bear in mind that a lower RS or a higher Rp translates to a more ideal tank

Example 1.8

Explain which part of the above analysis fails if ω changes arbitrarily.

Solution

As ω falls, the approximation R2 S /(L 1ω 2) ³ L 1 eventually fails to hold. Without this approximation, we must substitute for Lp in (1.32) from (1.33), obtaining the exact value of Rp:

The parallel equivalent resistance given by (1.35) or (1.36) is a fictitious, mathematical quantity that simplifies our analyses. Interestingly, Rp is a frequency-dependent quantity, but we typically assume it has a constant value calculated at the tank resonance frequency (As explained in Chapter 5, RS itself varies with frequency due to the skin effect.)

Example 1.9

A parallel tank resonating at 5 GHz employs a 5-nH inductor with a series resistance of 20 Ω Determine the value of Rp at 5 GHz and the error that it incurs if the tank resonance frequency is changed to 5 5 GHz Assume RS is constant.

Solution

From Eq (1 36), we have Rp ≈ 1 25 kΩ (´ RS ) At 5 5 GHz, on the other hand, the actual Rp would be equal to 1 51 kΩ Thus, a constant value of 1 25 kΩ incurs an error of about 18% at 5 5 GHz

Figure 1.17 (a) Parallel lossy LC tank, (b) magnitude of impedance, and (c) phase of impedance

Let us examine the impedance of an LC tank whose loss is modeled by a parallel resistor Rp [Fig. 1.17(a)]. The magnitude and phase follow those depicted in Fig. 1.15(b) at very low or very high frequencies (why?). Around the resonance frequency, however, |Z1 | rises to only Rp while L1 and C1 cancel each other [Fig 1 17(b)] Similarly, the phase displays a gradual change [Fig 1 17(c)]

An important conclusion here is that, as the tank becomes less lossy, both |Z1| and Z1 exhibit sharper changes.

Example 1.10

If Rp in Fig. 1.17(a) doubles while L1 and C1 remain constant, what happens to the phase plot in Fig. 1.17(c)?

Solution

We expect the phase transition around ω0 to become sharper. We write

For s = jω,

It follows that

To determine how the slope of Z depends on Rp, we differentiate (1.40) with respect to ω and replace L1 C1 ω2 with 1 in the result, arriving at

The slope around ω0 is thus linearly proportional to Rp.

We should remark that the phase profile depicted in Fig 1 17(c) is not exact at low frequencies if L1 has a series resistance RS . This is because the tank simply reduces to RS near dc, displaying zero phase shift. This point is nonetheless unimportant in most of our studies.

Quality Factor To determine how “good” an inductor is, we can define a figure of merit for it, specifically, a “quality factor,” Q. We expect the Q to be extremely high for an ideal inductor and lower as we include loss. For an inductor L1 having a series RS , we define the Q as

Note that RS is compared to the impedance of L1 at the frequency of interest. In essence, the numerator represents the desired impedance and the denominator, the undesired impedance. TheQ rises linearly with ω if RS is assumed independent of the frequency

We make three remarks First, our previous approximation, R2 S /(L1ω2 ) ³ L1 , in fact translates to Q2 ´ 1, which holds in most practical cases. Second, substituting RS = L1 ω/Q in (1.35) gives

revealing that we wish Rp to be as large as possible. Indeed, Rp = ∞ leads to an ideal parallel tank. This expression may suggest that Q falls as ω rises, but we must recall that Rp itself is frequency-dependent. Third, substituting Rp = QL1 ω in Eq. (1.41), we have an alternative definition for Q at the resonance frequency:

That is, the Q can be viewed as proportional to the slope of the phase response.

Tuned Amplification The parallel tank exemplifies a “tuned load,” a two-terminal circuit whose impedance reaches a peak only at a certain frequency. As with resistors and current sources, a tuned circuit can serve as the load in an amplifier, providing narrowband amplification. Shown in Fig. 1.18(a), such an arrangement has

Figure 1.18 (a) CS stage using a tuned load, (b) equivalent circuit at resonance, and (c) frequency response.

a transfer function given

if channel-length modulation is neglected We now appreciate the simplicity afforded by the parallelresistance model: at the resonance frequency, ω0, the circuit reduces to that in Fig. 1.18(b), yielding a voltage gain of gmRp and a phase shift of 180◦ . From the plots in Fig. 1.17, we readily arrive at the gain and phase profiles depicted in Fig. 1.18(c). The amplifier also acts as a band-pass filter (BPF).

Example 1.11

The tuned amplifier of Fig. 1.18(a) senses a sinusoidal input at ω0 with a peak amplitude of 20 mV and a dc level of 500 mV. If gmRp = 5, plot the output waveform. Assume VDD = 1 V.

Solution

The circuit inverts the signal and amplifies it by a factor of 5. But, what is the dc level at the output? If the series resistance of L1 is neglected, the dc drop from VDD to Vout must be zero. (An ideal inductor cannot sustain a finite dc voltage.) Thus, Vout has an average value equal to VDD , exhibiting voltage swings above VDD (Fig. 1.19). This property of parallel LC tanks proves useful in low-voltage design.

1.5.2 LC Oscillators as Feedback Systems

As with the resistively-loaded CS stage in Section 1.4, the tuned amplifier of Fig. 1.18(a) can be placed in a feedback loop to obtain oscillation. To this end, we must establish a total phase shift of 360◦ around the loop at ω0 , which the circuit of Fig. 1.18(a) cannot. We therefore cascade two identical stages as shown in Fig. 1 20(a), noting that the open-loop transfer function exhibits a magnitude of (gmRp)2 and a phase of 360◦ at ω0 = 1/√L1 C1 The closed-loop circuit thus oscillates at ω0 if (gmRp)2 ≥ 1 We often redraw the oscillator as shown in Fig. 1.20(b). Symmetry implies that VX and VY vary differentially with time.

Example 1.12

Can the above 1C oscillator latch up?

Solution

To determine the possibility of latch-up, we examine the circuit near dc, recognizing that the parallel resistance model no longer holds. If each inductor exhibits a low-frequency series resistance of RS, the oscillator reduces to the configuration depicted in Fig 1 21, where the loop gain is given by (gmRS )2 To avoid latch–up, we must have (gmRS )2 < 1, a condition readily met in typical designs

Figure 1.19 Tuned amplifier input and output waveforms

1.20 (a) Two cascaded tuned CS stages in a loop, and (b) the circuit redrawn as cross-coupled amplifiers.

Figure 1.21 LC oscillator equivalent circuit at low frequencies

It is instructive to sketch the waveforms of the oscillator of Fig. 1.20(b). As explained in Section 1.3, we generally choose the loop gain greater than unity so as to ensure large swings. In Fig. 1.20(b), M1 and M2 experience complete switching if (gmRp)2 is sufficiently large; thus, as, for example, VX falls and VY rises, M2 begins to turn off and M1 turns on more. The drain currents therefore swing between 0 and a maximum value (Fig. 1.22). Flowing through their respective tanks, these currents generate VX and VY . We

Figure 1.22 Cross-coupled oscillator waveforms

observe that (1) the output common-mode level is approximately equal to VDD (Example 1.11), and (2) the voltage waveforms resemble sinusoids whereas the current waveforms do not. This is because the parallel tank significantly filters components at 2ω0, 3ω0 , etc., as it converts the current to voltage.

Example 1.13

What is the maximum drain-source voltage experienced by M1 and M2 in Fig. 1.20(b)?

Figure

Solution

For a single-ended peak swing of Vp, the drain voltage in Fig. 1.22 reaches approximately VDD + Vp. This value of VDS may not be allowed by the technology because it can “stress” the transistor, shortening its lifetime

Example 1.14

One oscillation test that we devised in Section 1 3 is to measure the impedance between two nodes of the circuit and determine whether it goes to infinity at some frequency. Apply this test to the circuit of Fig. 1.20(b). Neglect channel-length modulation.

Solution

Let us examine the impedance between X and Y Drawing the small-signal model as shown in Fig 1 23(a), we observe that the net current injected into ground by the two tanks is zero because VX and VY are dif-

Figure 1.23 (a) Small-signal model of oscillator, (b) model with merged tanks, and (c) equivalent circuit for calculating output resistance of cross-coupled pair.

ferential We therefore place the two in series and merge them as shown in Fig 1 23(b) This allows us to compute the overall impedance as a parallel combination of two impedances, namely, the tank in the dashed box and the resistance produced between X and Y by M1 and M2 . For the latter, we construct the model depicted in Fig. 1.23(c), note that gmVX + gmVY = 0 (why?), and write a KVL, VY + Vt = VX. That is, Vt = 2VX = 2VY Also, I

2 In other words,

For oscillation to occur, the parallel combination of this (negative) resistance and the tank in Fig 1 23(b) must go to infinity:

We intuitively predict that both the first parallel combination and the second must individually go to infinity.

To be more rigorous, however, let us return to Example 1 10 and apply Eq (1 39) to the case at hand:

t It (jω) = j(2L1 ω) 1 L1 C1 ω2 + j (2L1ω) (2Rp)|| 2 gm (1.48)

This function goes to infinity if ω = 1/√L1C1 and 2Rp||( 2/gm) = ±∞, i.e., gm = 1/Rp. As expected, this result agrees with the startup condition (gmRp)2 = 1 derived previously

An interesting and useful observation here is that the cross-coupled transistors M1 and M2 in Fig 1 20(b) produce a negative (small-signal) resistance between their drains. We return to this point in Section 1.5.3.

Example 1.15

In analogy with the three-stage ring oscillator of Fig. 1.12(a), a student constructs the multi-phase circuit shown in Fig. 1.24(a). Determine the frequency of oscillation and the startup condition.

1.24 Three-stage ring using tuned amplifiers

Solution

For the total phase shift around the loop to be equal to 360◦ , each stage must contribute 120◦ Since VB /VA = gmZ1 , we have ( gmZ1) = 120◦ From Fig 1 18(c), we observe that this occurs at a frequency below the resonance frequency, ω0 . Returning to Eq. (1.40) and subtracting π from it to account for the inversion produced by a CS stage, we have

where ω1 denotes the oscillation frequency (not to be confused with the tanks’ resonance frequency). In this case, the phase difference between each tank’s current and voltage is equal to 60◦ rather than zero. Thus,

and hence

Figure

This result can be simplified if we express the tank Q at the resonance frequency as Q = Rp/(L1 ω0 ), note that ω0 = 1/√L1C1 , and write

52)

The reader can prove that ω1 < ω0 . For example, if Q = 5, then ω1 = 0.84ω0. To arrive at a simpler expression, we factor 4Q2 from 3+4Q2 in the numerator and write ¶1 + 3/(4Q2 ) ≈ 1+3/(8Q2 ), obtaining

if 8Q2 ´ 3. As expected, the higher the Q, the less ω1 departs from ω0 ; this occurs because the higher Q translates to a greater slope for Z in Fig. 1.17(c) and hence requires only a small deviation from ω0 to establish a phase shift of 60◦ in the tank

As with the resistively-loaded ring oscillator, each stage in this circuit displays a complex transfer function at ω1 because the tanks operate away from resonance. The cascade of the three stages, however, has a real transfer function.

For the startup condition, the magnitude squared of the transfer function of one stage must be at least unity at ω = ω1 Multiplying the magnitude of Z1 in Eq (1 39) by gm and squaring the result, we have

Let us write ω1 = αω0 from Eq (1 53) and

Thus,

That is,

Note that α itself is a function of Q, and both Q and Rp are computed at the resonance frequency, ω0 . For example, if Q = 5, then α = 0 84 and gmRp must be at least 2 02 We observe that this oscillator demands a greater gmRp than does the two-stage counterpart.

The oscillator of Fig. 1.20(b) suffers from a poorly-defined bias current: when the gate voltage reaches VDD + Vp, the drain current strongly depends on the transistor characteristics and on VDD To resolve this issue, we modify the circuit as described below.

Differential Feedback Oscillator The foregoing oscillator developments have focused on single-ended tuned CS stages. We can alternatively consider a differential pair with tuned loads and explore whether it can form an oscillator Shown in Fig 1 25(a), such an arrangement exhibits a small-signal differential transfer function similar to that of the CS stage of Fig 1 18(a), providing a peak gain of gmRp at ω0 It is instructive to first study the large-signal behavior of the circuit with a differential sinusoidal input at ω0. As illustrated in Fig. 1.25(b), M1 and M2 experience complete switching if the input amplitude is large

Figure 1.25 (a) Differential pair with LC loads, (b) large-signal input and output waveforms, (c) relation between square wave and its first harmonic

enough, with ID1 and ID2 swinging between 0 and ISS . Approximating each drain current waveform by a square wave, we observe that the fundamental sees a load impedance of Rp while the higher harmonics see a low impedance Thus, VX and VY resemble sinusoids

We can calculate the peak output voltage swing in Fig. 1.25(b) as follows. A square wave toggling between +1 and 1 contains a fundamental with a peak value of 4/π [Fig. 1.25(c)]. (This is a useful property to remember. It is also helpful to remember that the fundamental has a larger amplitude than the square wave.) The peak fundamental amplitude of ID1 and ID2 is therefore equal to (4/π)(ISS /2) (why?) Since this component has a frequency of ω0, it flows only through Rp on each side, generating a sinusoidal voltage with a peak single-ended amplitude of

The peak-to-peak differential output swing is equal to 4Vp = (8/π)ISS Rp. The reader is cautioned not to confuse the various factors of 2 that arise in these amplitude calculations.

Let us now place the tuned differential pair of Fig. 1.25(a) in a feedback loop. In our first attempt, we tie X to A and Y to B [Fig 1 26(a)] Why does this circuit not oscillate? The overall loop must provide a total phase shift of 360◦ , but we know from Fig 1 25(a) that this is not possible We then swap the feedback connections as shown in Fig. 1.26(b), adding another 180◦ to the phase profile of Fig. 1.25(a). Now, at ω = ω0 , the phase shift around the loop is equal to 0◦ (or 360◦ ). The circuit thus oscillates if (gmRp)2 ≥ 1. Note that gm denotes the small-signal transconductance of M1 or M2 when each carries a current of ISS /2. The oscillator derived above resembles that in Fig 1 20(b) except for the tail current source, which defines the bias current much more accurately From the analysis leading to Eq (1 58), we have learned that the new topology provides a differential peak-to-peak swing of (8/π)ISS Rp (if M1 and M2 experience complete switching) with a CM level equal to VDD.