Advanced Computer Architecture
Final Exam Questions
Course Introduction
Advanced Computer Architecture delves into the design, analysis, and evaluation of modern computer systems at the architectural level. The course explores topics such as instruction set architectures, pipelining, superscalar and VLIW processors, memory hierarchies, cache optimization, parallel architectures, and advanced techniques for performance enhancement. Students will examine trade-offs in processor design, power efficiency, and scalability, as well as emerging trends such as multicore and manycore architectures. Through case studies and hands-on assignments, learners gain a comprehensive understanding of how architectural innovations drive the performance and efficiency of contemporary computing systems.
Recommended Textbook
Computer Organization and Architecture 10th Edition by William Stallings
Available Study Resources on Quizplus
21 Chapters
945 Verified Questions
945 Flashcards
Source URL: https://quizplus.com/study-set/3890 Page 2
Chapter 1: Basic Concepts and Computer Evolution
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77479
Sample Questions
Q1) Computer technology is changing at a __________ pace.
A)slow
B)slow to medium
C)rapid
D)non-existent
Answer: C
Q2) Historically the distinction between architecture and organization has not been an important one.
A)True
B)False
Answer: False
Q3) A computer is a complex system.
A)True
B)False
Answer: True
Q4) The basic functions that a computer can perform are: data processing,data movement,control,and _________.
Answer: data storage
Q5) __________ refers to those attributes of a system visible to a programmer.
Answer: Computer architecture
To view all questions and flashcards with answers, click on the resource link above. Page 3
Chapter 2: Performance Issues
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77478
Sample Questions
Q1) Operations performed by a processor,such as fetching an instruction,decoding the instruction,performing an arithmetic operation,and so on,are governed by a system clock.
A)True
B)False
Answer: True
Q2) The __________ is a relatively small fast memory interposed between a larger,slower memory and the logic that accesses the larger memory.
A)peripheral
B)cache
C)processor
D)arithmetic and logic unit
Answer: B
Q3) The __________ Mean used for a time-based variable,such as program execution time,has the important property that it is directly proportional to the total time.
Answer: Arithmetic
Q4) __________ Law applies to a queuing system.
Answer: Little's
To view all questions and flashcards with answers, click on the resource link above.
4
Chapter 3: A Top-Level View of Computer Function and
Interconnection
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77477
Sample Questions
Q1) Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.
A)True
B)False
Answer: True
Q2) Timing refers to the way in which events are coordinated on the bus.
A)True
B)False
Answer: True
Q3) A(n)_________ is generated by a failure such as power failure or memory parity error.
A)I / O interrupt
B)hardware failure interrupt
C)timer interrupt
D)program interrupt
Answer: B
Q4) A _________ interrupt simply means that the processor can and will ignore that interrupt request signal.
Answer: disabled
To view all questions and flashcards with answers, click on the resource link above. Page 5
Chapter 4: Cache Memory
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77476
Sample Questions
Q1) individual blocks or records have a unique address based on physical location with
A)associative access
B)physical access
C)direct access
D)sequential access
Q2) The three performance parameters for memory are: access time,transfer rate,and
Q3) The most commonly used physical types of memory are: semiconductor memory,__________ memory (used for disk and tape),and optical and magneto-optical.
Q4) For set-associative mapping the cache control logic interprets a memory address as three fields: Set,Word,and __________.
Q5) __________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.
A)Direct mapping
B)Associative mapping
C)Set associative mapping
D)None of the above
To view all questions and flashcards with answers, click on the resource link above. Page 6
Chapter 5: Internal Memory
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77475
Sample Questions
Q1) A static RAM will hold its data as long as power is supplied to it.
A)True
B)False
Q2) In earlier computers the most common form of random-access storage for computer main memory employed an array of doughnut-shaped ferromagnetic loops referred to as __________.
Q3) A number of chips can be grouped together to form a memory bank.
A)True
B)False
Q4) Which of the following memory types are nonvolatile?
A)erasable PROM
B)programmable ROM
C)flash memory
D)all of the above
Q5) __________ works by creating resistance rather than directly storing charge.
Q6) Semiconductor memory comes in packaged chips.
A)True
B)False
Q7) RAM,ROM,PROM,EPROM,EEPROM,and flash memory are all examples of __________ memory types.
To view all questions and flashcards with answers, click on the resource link above. Page 7
Chapter 6: External Memory
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77474
Sample Questions
Q1) Adjacent tracks are separated by _________.
A)sectors
B)gaps
C)pits
D)heads
Q2) RAID levels 4 through 6 make use of an __________ access technique that allows separate I / O requests to be satisfied in parallel.
Q3) The time required to move the disk arm to the required track is the __________.
Q4) The _________ strategy employs multiple disk drives and distributes data in such a way as to enable simultaneous access to data from multiple drives,thereby improving I / O performance and allowing easier incremental increases in capacity.
Q5) In most contemporary systems fixed-length sectors are used,with _________ bytes being the nearly universal sector size.
A)64
B)128
C)256
D)512
Q6) Data is organized on the platter in a concentric set of rings called ________.
To view all questions and flashcards with answers, click on the resource link above. Page 8
Chapter 7: Input Output
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77473
Sample Questions
Q1) The most recent,and fastest,peripheral connection technology to become available for general-purpose use is __________,developed by Intel with collaboration from Apple.
Q2) A set of I / O modules is a key element of a computer system.
A)True
B)False
Q3) An external device connected to an I / O module is often referred to as a __________ device.
Q4) We can broadly classify external devices into three categories: human readable,communication,and __________.
Q5) ________ is when the DMA module must force the processor to suspend operation temporarily.
A)Interrupt
B)Thunderbolt
C)Cycle stealing
D)Lock down
Q6) When large volumes of data are to be moved,a more efficient technique is direct memory access (DMA).
A)True
B)False
Page 9
To view all questions and flashcards with answers, click on the resource link above.
Chapter 8: Operating System Support
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77472
Sample Questions
Q1) The ABI is the boundary between hardware and software.
A)True
B)False
Q2) The technique where memory is expanded to hold three,four,or more programs and switch among all of them is __________,(or multitasking).
Q3) When the processor executes a process it automatically converts from logical to physical address by adding the current starting location of the process,called its __________,to each logical address.
Q4) With _________ the virtual address is the same as the physical address.
A)unsegmented unpaged memory
B)unsegmented paged memory
C)segmented unpaged memory
D)segmented paged memory
Q5) The __________ ,or nucleus,contains the most frequently used functions in the OS.
Q6) Managers are users of domains that must observe the access permissions of the individual sections and / or pages that make up that domain.
A)True
B)False
To view all questions and flashcards with answers, click on the resource link above. Page 10
Chapter 9: Number Systems
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77471
Sample Questions
Q1) In the number 472.156 the 2 is the _________.
A)most significant digit
B)radix point
C)least significant digit
D)none of the above
Q2) (2 x 10-1)+ (5 x 10-2)+ (6 x 10-3)represents the number _________.
Q3) The decimal system is a special case of a positional number system with radix 10 and with digits in the range 0 through 9.
A)True
B)False
Q4) Because 16 symbols are used,the notation is called hexadecimal and the 16 symbols are the __________.
Q5) Binary 0101 is hexadecimal _________.
A)0
B)5
C)A
D)10
Q6) Our primary counting system is based on binary digits to represent numbers. A)True
B)False
Page 11
To view all questions and flashcards with answers, click on the resource link above.
Chapter 10: Computer Arithmetic
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77470
Sample Questions
Q1) If two numbers are added,and they are both positive or both negative,then _________ occurs if and only if the result has the opposite sign.
Q2) A __________ is one in which the most significant digit of the significand is nonzero.
Q3) Actual floating-point representations include a special bit pattern to designate zero.
A)True
B)False
Q4) __________ representation is almost universally used as the processor representation for integers.
A)Biased
B)Twos compliment
C)Sign-magnitude
D)Decimal
Q5) Overflow is a less serious problem because the result can generally be satisfactorily approximated by 0.
A)True
B)False
Q6) The use of subnormal numbers is referred to as _________ underflow.
To view all questions and flashcards with answers, click on the resource link above. Page 12
Chapter 11: Digital Logic
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77469
Sample Questions
Q1) A ________ is an interconnected set of gates whose output at any time is a function only of the input at that time.
Q2) The _________ connects multiple inputs to a single output.
Q3) A _________ is a PLD featuring a general structure that allows very high logic capacity and offers more narrow logic resources and a higher ration of flip-flops to logic resources than do CPLDs.
A)SPLD
B)FPGA
C)PAL
D)PLA
Q4) Binary addition is exactly the same as Boolean algebra.
A)True
B)False
Q5) A register is a digital circuit used within the CPU to store one or more bits of data.
A)True
B)False
Q6) Each gate is defined in three ways: graphic symbol,algebraic notation,and
To view all questions and flashcards with answers, click on the resource link above. Page 13
Chapter 12: Characteristics and Functions
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77468
Sample Questions
Q1) The _________ instruction includes an implied address.
A)skip
B)rotate
C)stack
D)push
Q2) Source and result operands can be in one of four areas: main or virtual memory,immediate,I / O device,and _________.
Q3) _________ instructions are those that can be executed only while the processor is in a certain privileged state or is executing a program in a special privileged area of memory.
Q4) Most machines provide the basic arithmetic operations of add, subtract,multiply,and divide.
A)True
B)False
Q5) The instruction set is the programmer's means of controlling the processor.
A)True
B)False
Q6) The __________ reference tells the processor where to fetch the next instruction after the execution of this instruction is complete.
Page 14
To view all questions and flashcards with answers, click on the resource link above.
Chapter 13: Addressing Modes and Formats
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77467
Sample Questions
Q1) The advantage of __________ is that no memory reference other than the instruction fetch is required to obtain the operand.
A)direct addressing
B)immediate addressing
C)register addressing D)stack addressing
Q2) The actual mapping to a physical address is a function of the _________ and is invisible to the programmer.
Q3) Programs written in assembly language are translated into machine language by an _________.
Q4) The __________ instruction set is designed to increase the performance of ARM implementations that use a 16-bit or narrower memory data bus and to allow better code density than provided by the ARM instruction set.
Q5) The simplest form of addressing is __________ addressing.
Q6) Sometimes referred to as a pushdown list or last-in-first-out queue,a __________ is a linear array of locations.
Q7) If a programmer wished to program directly in machine language it would be necessary to enter the program as ________ data.
Page 15
To view all questions and flashcards with answers, click on the resource link above.
Chapter 14: Processor Structure and Function
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77466
Sample Questions
Q1) Condition codes facilitate multiway branches.
A)True
B)False
Q2) The _________ stage includes ALU operations,cache access,and register update.
A)decode
B)execute
C)fetch
D)write back
Q3) The _________ contains the address of an instruction to be fetched.
A)instruction register
B)memory address register
C)memory buffer register
D)program counter
Q4) The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.
A)dynamic branch
B)loop table
C)branch history table
D)flag
Q5) An instruction cycle includes the following stages: fetch,execute,and _______.
Page 16
To view all questions and flashcards with answers, click on the resource link above.
Chapter 15: Reduced Instruction Set Computers
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77465
Sample Questions
Q1) RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.
A)True
B)False
Q2) The difference between the operations provided in high-level languages (HLLs)and those provided in computer architecture is known as the ________.
Q3) The MIPS R4000 processor chip is partitioned into two sections,one containing the CPU and the other containing a _________ for memory management.
Q4) Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.
A)True
B)False
Q5) Procedure calls and returns are not important aspects of HLL programs.
A)True
B)False
Q6) Blocks of memory,recently used global variables,memory addressing,and one operand addressed and accessed per cycle are characteristics of _________ organizations.
To view all questions and flashcards with answers, click on the resource link above. Page 17
Chapter 16: Parallelism and Superscalar Processors
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77464
Sample Questions
Q1) Instead of the first instruction producing a value that the second instruction uses,with ___________ the second instruction destroys a value that the first instruction uses.
A)in-order issue
B)resource conflict
C)antidependency
D)out-of-order completion
Q2) Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion,out-of-order issue with out-of-order completion,and ____________.
Q3) The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution.
A)True
B)False
Q4) The term _________ parallelism refers to the degree to which,on average,the instructions of a program can be executed in parallel.
Q5) ________ exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.
Q6) An alternative to _________ is a scoreboarding.
To view all questions and flashcards with answers, click on the resource link above. Page 18
Chapter 17: Parallel Processing
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77463
Sample Questions
Q1) The __________ is the simplest mechanism for constructing a multiprocessor system.
Q2) Which of the following is an essential characteristic of cloud computing?
A)rapid elasticity
B)measured service
C)broad network access
D)all of the above
Q3) Hardware-based solutions are generally referred to as cache coherence _______.
A)clusters
B)streams
C)protocols
D)vectors
Q4) A ________ is a dispatchable unit of work within a process that includes a processor context and its own data area for a stack.
A)process
B)process switch
C)thread
D)thread switch
Q5) _________ is the easiest multithreading approach to implement.
Q6) Two key characteristics of a process are: scheduling / execution and ________.
To view all questions and flashcards with answers, click on the resource link above. Page 19
Chapter 18: Multicore Computers
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77462
Sample Questions
Q1) _______ applications embrace threading in a fundamental way.
A)Multi-instance
B)Multi-process
C)Java
D)Threaded
Q2) The principal building block of the IBM zEnterprise EC12 mainframe is the
Q3) The SCU uses hybrid MESI and _________ protocols to maintain coherency between the individual L1 data caches and the L2 cache.
Q4) The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.
A)True
B)False
Q5) The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.
Q6) _______ law assumes a program in which a fraction (1- f )of the execution time involves code that is inherently serial and a fraction f that involves code that is infinitely parallelizable with no scheduling overhead.
To view all questions and flashcards with answers, click on the resource link above. Page 20
Chapter 19: General-Purpose Graphic Processing Units
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77461
Sample Questions
Q1) The parallel code in the form of a function to be run on GPU is the ________ .
A)grid
B)thread
C)kernel
D)none of the above
Q2) An instance of the kernel on the GPU is a ___________ .
A)thread
B)warp
C)grid
D)block
Q3) A _________ is a single instance of the kernel function.
Q4) The entire Gen8 compute architecture interfaces to the rest of the SoC components via a dedicated unit called the ____________ .
Q5) All but one set of GPU processor cores will be idle,while one SM is bearing the full processing load.
A)True
B)False
Q6) The _________ global scheduler unit on the GPU chip distributes the thread blocks to the SMs.
To view all questions and flashcards with answers, click on the resource link above. Page 21
Chapter 20: Control Unit Operation
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77460
Sample Questions
Q1) The execution of a program consists of the sequential execution of instructions.
A)True
B)False
Q2) Control unit implementation techniques fall into two categories: microprogrammed implementation and ___________ implementation.
Q3) The ____________ generated by the control unit cause the opening and closing of logic gates,resulting in the transfer of data to and from registers and the operation of the ALU.
Q4) Which of the following is an Intel 8085 external signal?
A)CLK(OUT)
B)read control
C)HOLDA
D)all of the above
Q5) __________ are the functional,or atomic,operations of a processor.
A)Micro-operations
B)Interrupts
C)Subcycles
D)All of the above
Q6) The __________ register specifies the address in memory for a read or write operation.
To view all questions and flashcards with answers, click on the resource link above. Page 22
Chapter 21: Microprogrammed Control
Available Study Resources on Quizplus for this Chatper
45 Verified Questions
45 Flashcards
Source URL: https://quizplus.com/quiz/77459
Sample Questions
Q1) The standard IBM 3033 control memory consists of ________ words.
A)2K
B)8K
C)4K
D)16K
Q2) The terms __________ relate to the relative width of microinstructions.
A)packed / unpacked
B)hard / soft
C)horizontal / vertical
D)direct / indirect
Q3) The term microprogram was first coined by __________ in the early 1950s.
A)M.V.Wilkes
B)D.Siewiorek
C)M.Sebern
D)S.Tucker
Q4) Each microinstruction cycle is made up of two parts: fetch and _________.
Q5) The LSI-11 is a good example of a __________ microinstruction approach.
Q6) In a __________ microinstruction every bit in the control field attaches to a control line.
Q7) A sequence of instructions is known as a ___________,or firmware.
To view all questions and flashcards with answers, click on the resource link above. Page 23