Heterogeneous reconfigurable processors for real time baseband processing from algorithm to architec

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Heterogeneous Reconfigurable Processors for Real Time Baseband Processing From Algorithm to Architecture 1st Edition Chenxin Zhang

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Chenxin Zhang · Liang Liu

Heterogeneous

Recon

gurable Processors for RealTime Baseband Processing

From Algorithm to Architecture

ChenxinZhang•LiangLiu•ViktorÖwall

Heterogeneous ReconfigurableProcessors forReal-TimeBaseband Processing

FromAlgorithmtoArchitecture

ChenxinZhang

DepartmentofElectricalandInformation Technology

LundUniversity

Lund,Sweden

ViktorÖwall

DepartmentofElectricalandInformation Technology

LundUniversity

Lund,Sweden

LiangLiu

DepartmentofElectricalandInformation Technology

LundUniversity

Lund,Sweden

ISBN978-3-319-24002-2ISBN978-3-319-24004-6(eBook) DOI10.1007/978-3-319-24004-6

LibraryofCongressControlNumber:2015958762

SpringerChamHeidelbergNewYorkDordrechtLondon ©SpringerInternationalPublishingSwitzerland2016

Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpartof thematerialisconcerned,specificallytherightsoftranslation,reprinting,reuseofillustrations,recitation, broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionorinformation storageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodology nowknownorhereafterdeveloped.

Theuseofgeneraldescriptivenames,registerednames,trademarks,servicemarks,etc.inthispublication doesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfromtherelevant protectivelawsandregulationsandthereforefreeforgeneraluse.

Thepublisher,theauthorsandtheeditorsaresafetoassumethattheadviceandinformationinthisbook arebelievedtobetrueandaccurateatthedateofpublication.Neitherthepublishernortheauthorsor theeditorsgiveawarranty,expressorimplied,withrespecttothematerialcontainedhereinorforany errorsoromissionsthatmayhavebeenmade.

Printedonacid-freepaper

SpringerInternationalPublishingAGSwitzerlandispartofSpringerScience+BusinessMedia(www. springer.com)

1.1ScopeoftheBook .......................................................3

1.2Outline ...................................................................4

1.2.1Chapter4:TheReconfigurableCellArray

1.2.2Chapter5:Multi-StandardDigitalFront-EndProcessing ....5

1.2.3Chapter6:Multi-TaskMIMOSignalProcessing .............5

1.2.4Chapter7:FutureMulti-UserMIMOSystems ................5

2DigitalHardwarePlatforms ................................................9

2.1ProgrammableProcessors ..............................................10

2.1.1General-PurposeProcessors ....................................11

2.1.2Special-PurposeProcessors ....................................12

2.1.3Application-SpecificInstructionSetProcessors ..............12

2.1.4ConfigurableInstructionSetProcessors .......................12

2.2Application-SpecificIntegratedCircuits ...............................13

2.3ReconfigurableArchitectures ...........................................13

2.4ACommentonPowerEfficiency

3.1WirelessCommunicationTechnologies ................................18

3.1.1OrthogonalFrequencyDivisionMultiplexing .................18

3.1.2Multiple-InputMultiple-Output ................................19

3.2OverviewofDigitalBasebandProcessing .............................20

3.2.1ChannelEncoding/Decoding ...................................20

3.2.2SymbolMapping/Demapping

3.2.3DomainTransformation ........................................21

3.2.4DigitalFront-EndProcessing ..................................22

3.2.5ChannelEstimation

3.2.6ChannelMatrixPre-processing

3.2.7SymbolDetection

3.3BasebandProcessingProperties

4TheReconfigurableCellArray

4.1Introduction

4.2PriorWorkandState-of-the-Art

4.3ArchitectureOverview

4.3.1ProcessingCell

4.3.2MemoryCell

4.3.4ResourceConfiguration

5Multi-StandardDigitalFront-EndProcessing

5.1Introduction

5.2AlgorithmandImplementationAspects

5.2.1TimeSynchronizationandCFOEstimation

5.2.2OperationAnalysis

5.3.1DataflowProcessor

5.4ImplementationResultsandDiscussion

5.4.1Task-LevelPipeline

5.4.2MemoryInterleaving

5.4.3ContextSwitching

5.4.4ConfigurationGenerator

5.4.5HardwareFlexibility

5.4.6ImplementationResults

5.4.7MeasurementResults

5.5Summary

6Multi-TaskMIMOSignalProcessing

6.1Introduction

6.2MIMOSignalProcessing

6.2.1ChannelEstimation

6.2.2ChannelMatrixPre-processing

6.2.3SymbolDetection

6.3AlgorithmEvaluationandOperationAnalysis

6.3.1SimulationEnvironment

6.3.2PerformanceEvaluation

6.3.3OperationandComplexityAnalysis

6.3.4ProcessingFlowandTimingAnalysis

6.4HardwareDevelopment .................................................101

6.4.1ArchitectureOverview .........................................102

6.4.2VectorDataflowProcessor

6.4.3VectorDataMemoryTile ......................................112

6.4.4ScalarResourceCellsandAccelerators

6.4.5ConcurrentCandidateEvaluation ..............................120

6.5ImplementationResultsandComparison

6.5.1ImplementationResults ........................................124

6.5.2TaskMappingandTimingAnalysis

6.5.3ComputationEfficiency ........................................133

6.5.4PowerandEnergyConsumption

6.5.5ComparisonandDiscussion ....................................135

6.6AdaptiveChannelPre-processor

6.6.1QR-UpdateScheme .............................................144

6.6.2Group-SortAlgorithm

6.6.3AlgorithmEvaluationandOperationAnalysis ................146

6.6.4ImplementationResultsandDiscussion

6.7Summary ................................................................150 References .....................................................................150

7FutureMulti-UserMIMOSystems:ADiscussion

7.1MIMOGoestoMassive ................................................156

7.1.1MassiveMIMOBasics .........................................156

7.1.2FromTheorytoPractice ........................................157

7.2MassiveMIMOBasebandProcessing .................................160

7.2.1BasebandProcessingOverview ................................161

7.2.2UplinkMulti-UserDetection ...................................162

7.2.3DownlinkBeam-FormingPre-coding .........................163

7.3NewChallengesinReconfigurableArchitectureDesign

7.3.1ComputationalComplexity .....................................164

7.3.2ProcessingDistribution .........................................165

7.3.3Spatial-DomainSelectivity .....................................167

7.4Summary ................................................................167 References .....................................................................168

ListofAcronyms

ADC Analog-to-digitalconverter.

ALU Arithmeticlogicunit.

ASIC Application-specificintegratedcircuit.

ASIP Application-specificinstructionsetprocessor.

AWGN AdditivewhiteGaussiannoise.

BPSK Binaryphase-shiftkeying.

CFO Carrierfrequencyoffset.

CGRA Coarse-grainedreconfigurablearchitecture.

CISC Complexinstructionsetcomputing.

CMAC Complex-valuedmultiply-accumulate.

CMOS Complementarymetal-oxide-semiconductor.

CORDIC Coordinaterotationdigitalcomputer.

CP Cyclicprefix.

CSI Channelstateinformation.

CVG Candidatevectorgeneration.

DAC Digital-to-analogconverter.

DFE Digitalfront-end.

DLP Data-levelparallelism.

DMA Directmemoryaccess.

DSP Digitalsignalprocessor.

DVB Digitalvideobroadcasting.

DVB-H Digitalvideobroadcastingforhandheld.

ED Euclideandistance.

EPA ExtendedpedestrianA.

EQD Equallydistributed.

ETU Extendedtypicalurban.

EVA ExtendedvehicularA.

FEC Forwarderrorcorrection.

FER Frameerrorrate.

FFT FastFouriertransform.

FIFO Firstinfirstout.

FNE Fastnodeenumeration.

FPGA Field-programmablegatearray.

FSD Fixed-complexityspheredecoder.

FSM Finite-statemachine.

FU Functionunit.

GALS Globallyasynchronouslocallysynchronous.

GOPS Gigaoperationspersecond.

GPC Genericsignalprocessingcell.

GPP Generalpurposeprocessor.

GPR Generalpurposeregister.

GPS Globalpositioningsystem.

GPU Graphicsprocessingunit.

GSM Globalsystemformobilecommunications.

HDL Hardwaredescriptionlanguage.

i.i.d. Independentandidenticallydistributed.

ICI Inter-carrier-interference.

IFFT InversefastFouriertransform.

ILC Innerloopcontroller.

ILP Instruction-levelparallelism.

IMD IMbalanceddistributed.

IP Intellectualproperty.

ISA Instructionsetarchitecture.

ISI Inter-symbol-interference.

LS Leastsquare.

LSB Leastsignificantbit.

LTE Longtermevolution.

LTE-A

Longtermevolution-advanced.

LUT Look-uptable.

MAC Multiply-accumulate.

MGS ModifiedGram-Schmidt.

MIMO Multiple-inputmultiple-output.

ML Maximum-likelihood.

MMR Matrixmaskregister.

MMSE Minimummean-squareerror.

MPMC Multi-portmemorycontroller.

MRC Maximum-ratiocombining.

MSE Meansquarederror.

NFC Nearfieldcommunication.

NoC Network-on-chip.

NRE Non-recurringengineering.

OFDM Orthogonalfrequencydivisionmultiplexing.

PDP Power-delayprofile.

QAM Quadratureamplitudemodulation.

QoS Qualityofservice.

QPSK Quadraturephase-shiftkeying.

QRD QRdecomposition.

RAM Randomaccessmemory.

RC Resourcecell.

RISC Reducedinstructionsetcomputing.

ROM Read-onlymemory.

RTL Registertransferlevel.

SCC Streamconfigurationcontroller.

SCENIC SystemCenvironmentwithinteractivecontrol.

SD Spheredecoder.

SDC Streamdatacontroller.

SDR Software-definedradio.

SIMD Singleinstructionmultipledata.

SIMT Singleinstructionstreammultipletasks.

SNR Signal-to-noiseratio.

SPE Successivepartialnodeexpansion.

SQRD SortedQRdecomposition.

STS Shorttrainingsymbol.

SVD Singularvaluedecomposition.

TDD Time-divisionduplexing.

TLP Thread-levelparallelism.

UART Universalasynchronousreceiver/transmitter.

UMTS Universalmobiletelecommunicationssystem.

VDP Vectordotproduct.

VHDL Veryhighspeedintegratedcircuit(VHSIC)HDL.

VLIW Verylonginstructionword.

VLSI Very-large-scaleintegration.

VPR Vectorpermutationregister.

WCDMA Widebandcodedivisionmultipleaccess.

ZF Zero-forcing.

ListofDefinitions

. / Complexconjugate.

. /H Hermitiantranspose.

. /T Vector/matrixtranspose.

. / Matrixpseudo-inverse.

. /i Columnvector.

. /i;i .i; i/th matrixelement.

k k Euclideanvectorlength.

k k2 `2 -norm.

M Constellationsize.

NSW FrequencycorrelationwindowinR.MMSE-SW.

Nc NumberofOFDMsubcarriers.

N Numberofantennas.

H Complex-valuedMIMOchannelmatrix.

I Identitymatrix.

P Permutationmatrixinsorted-QRdecomposition.

Q UnitarymatrixinQRdecomposition.

R UppertriangularmatrixinQRdecomposition.

n i.i.d.complexGaussiannoisevector.

b c Floorfunction.Rounds x tonearestintegertowards 1

O Computationalcomplexity.

2 n Varianceofnoisevector n

f OFDMsubcarrierspacing.

sCMOS Technologyscalingfactor.

Approximation.

d e Ceilingfunction.Rounds x tonearestintegertowards C1 xiii

J Element-wisevectormultiplication.

" Fractionalcarrierfrequencyoffset.

Post-detectionSNR.

2 For x 2 A,theelement x belongstotheset A

NodeperturbationparameterinMMSE-NP.

/ Proportional.

R Realcontinuousspace.

Q Slicingfunctioninsymboldetection,returninganearestconstellation point.

OFDMsymbolstart.

Chapter1 Introduction

Thisbookdiscussesaninterdisciplinarystudyinwirelesscommunicationand Very-large-scaleintegration(VLSI)design,morespecifically,implementationof digitalbasebandprocessingusingreconfigurablearchitectures.Developmentof suchkindofsystems,sometimesreferredtoasbasebandprocessors[15]or Software-definedradio(SDR)platforms[8],isanimportantandchallenging subject,especiallyforsmall-scalebasestations(e.g.,femtocells)andmobile terminalsthatmustprovidereliableservicesundervariousoperatingscenarioswith lowpowerconsumption.

Theimportanceofthesubjectisdrivenbytwofacts.First,thereisahuge demandforwirelesscommunicationintheworld.Thenumberofdevicesconnected totheInternetinonewayortheotherisexpectedtoreach50billionby2020 [3, 9].Inotherwords,everypersononearthwillhavearoundsixdeviceson average.Second,thenumberofradiostandardsgrowsincreasinglyfastinorder tosufficeever-growinguserdemandssuchasdatarate.Forexample,comparedto theworld’sfirsthand-helddevicedemonstratedin1973,today’sfourth-generation (4G)mobileterminalsareabletoprocessnotonlyvoiceandtextbutalsodata streamingwiththespeedofuptogigabit-per-second[7];thecoming5Gwireless communicationnetworkwillprovide1000-foldgainincapacity.Moreover,modern wirelesssystemsneedtobebackwardcompatibletosupport2GGlobalsystem formobilecommunications(GSM)and3GUniversalmobiletelecommunications system(UMTS),aswellastosupportarangeofdifferentradiostandardsfor improvinguserexperience.Examplesofthesestandardsarebluetooth,IEEE802.11 series,Globalpositioningsystem(GPS),andNearfieldcommunication(NFC).As envisionedin[5],asingle4Gmobileterminalneedstosupportmorethan10radio standardswithtensofoperationmodesineachstandard[e.g.,63for3GPPLong termevolution(LTE)].Usingtraditionalimplementationstrategies,equippingeach ofthesestandardswithanApplication-specificintegratedcircuit(ASIC),becomes antiquatedandunaffordablewithregardtoareaconsumptionanddevelopmenttime. ©SpringerInternationalPublishingSwitzerland2016

Besides,itisunlikelythatauserwillenableallofthesestandardsatthesametime inasingleterminal.Thus,thereisaneedforaflexiblehardwareplatformcapableof supportingoperationsamongmultiplestandardsandtasksandallocatingresources dynamicallytosufficecurrentcomputationaldemands.

Inadditiontothemulti-standardmulti-tasksupport,flexibilityisrequiredtocope withtherapidevolutionofbasebandprocessingalgorithmsandenablerun-time algorithmadaptiontoprovidebetterQualityofservice(QoS)andmaintainrobust, reliable,andseamlessconnectivity.Furthermore,benefitingfromthehardware reconfigurability,sucharchitectureshavethepotentialtoperformsystemupdates andbug-fixeswhilethesystemisinoperation.Thisfeaturewillprolongproduct life-timeandensurebenefitsintermsoftime-to-market[13, 15, 16].Lastbutnot theleast,fromanalgorithmdevelopmentperspective,reconfigurablecomputing providesamoresoftware-centricprogrammingapproach.Thisallowshardware platformstobedevelopedon-demandandpotentiallyinthesamelanguageas usedforsoftwaredevelopment.Unifiedprogrammingenvironmentenhancesproductivitybysimplifyingsystemintegrationandverification.Besidesitsimportance, thetargetsubjectfacesmanydesignchallengesinpracticalimplementations,such asrequirementsofhighcomputationalperformanceandlowenergyconsumption. Primaryconcernsforcontemporarysystemdesignsareshiftingfromcomputational performancetoenergyefficiency[2, 17].Thistrendbecomesmoreandmore prominentinwirelesscommunicationdesigns.Forexample,thetransitionfrom3G to4Gwirelesscommunicationsystemsdemands3ordersofmagnitudeincreasein computationalcomplexity,whereasthetotalpowerbudgetremainsapproximately constantinasinglemobileterminal[14, 21].Reconfigurablearchitectures,sinceits inventionin1960[10],promisetooffergreathardwareflexibilityandcomputational performance.Theyallowrun-timehardwarereconfigurationstoacceleratearbitrary algorithms,andthusextendtheapplicationdomainandversatilityofthedevice. However,duetohugeroutingoverhead,theycannotmatchpowerandareaefficiencyofASICs,inspiteoftheirtremendousdevelopmentsoverthepastdecades. Asanexample,fine-grainedinterconnectsincommercialField-programmablegate array(FPGA)consumeover75%ofthechiparea[20],andcause17–54times areaoverheadand5.7–62timesmorepowerconsumptionincomparisontoASICs [12].Moreover,bit-levelfunctionblocksofFPGAsincuradditionalareaand powerpenaltieswhenimplementingword-levelcomputations.Theareaandpower overheadhaverestrictedtheusageofreconfigurablearchitecturesincost-sensitive applicationssuchaswirelesscommunicationinmobileterminals.Toaddressthese overheadissues,newtypesofreconfigurablearchitectureswithcoarse-grained functionblockshavegainedincreasingattentioninrecentyearsinbothacademia andindustry[1, 4, 6, 11, 18, 19].

Thisbookpresentsacoarse-graineddynamicallyreconfigurablecellarray architecture,whichisdesignedandtailoredwithaprimaryfocusondigital basebandprocessinginwirelesscommunication.Byexploitingthecomputational characteristicsofthetargetapplicationdomain,thepresenteddomain-specificcell arrayarchitecturebridgesthegapbetweenASICsandconventionalreconfigurable platforms.Theflexibility,performance,andhardwareefficiencyofthecellarrayare demonstratedthroughcasestudies.

1.1ScopeoftheBook

Thegoalofthisbookistofindefficientreconfigurablearchitecturesthatcanprovide abalanceamongcomputationalcapability,flexibility,andhardwareefficiency. Thedrivingapplicationforhardwaredevelopmentsandperformanceevaluations isdigitalbasebandprocessinginwirelesscommunication.Thetargetplatformis commerciallydeployedwirelesscommunicationequipmentanddevices,which needtoprovidereal-timeperformancewithrestrictedbudgetsofphysicalsizeand energydissipation.

Thecentralpartofthisbookisthepresentationofadynamicallyreconfigurable cellarrayarchitecture.Performanceofthecellarrayisevaluatedthroughtwocase studies,whichareconductedtoaddresstwofollowingquestions:

•Canthecellarraybeusedformulti-standardandmulti-taskprocessing?Isthe controloverheadaffordable?

•Canthecellarraymeetreal-timerequirementswhenperformingsophisticated basebandprocessingtasks?Undersuchausecase,whatistheareaandenergy efficiencyincomparisontoASICsandconventionalreconfigurablearchitectures?

Throughoutthebookandbyconductingalgorithm–architectureco-design,specialattentionispaidtofourdistinctareasofthecellarraydesign:

•Systemarchitecturedesign,includingvariousprocessingelements,memorysubsystems,Network-on-chip(NoC),anddynamicreconfiguration.

•Designflowofthecellarray.

•Designtrade-offs,includingselectionofprocessingelementsandaccelerators, taskpartitioningbetweenhardwareandsoftwareaswellasbetweenprocessing elementsandmemorysub-systems.

•Instructionsetandfunctiondescriptordesignforvariousprocessingelements andmemorysub-systems,respectively.

Digitalbasebandprocessinginwirelesscommunicationsystemsincludes manytaskssuchasOrthogonalfrequencydivisionmultiplexing(OFDM)modulation/demodulation,Multiple-inputmultiple-output(MIMO)signalprocessing, Forwarderrorcorrection(FEC),interleaving,scrambling,etc.Amongthese,this bookfocusesonfourcrucialblocksinatypicalbasebandprocessingchainatthe receiver,i.e.,Digitalfront-end(DFE),channelestimation,channelpre-processing, andsymboldetection.However,thesamedesignmethodologyisapplicablefor otherbasebandprocessingblocksandapplications.

1.2Outline

Chapters 2 and 3 servetogiveanoverviewoftheresearchfield.Chapter 2 discusses reconfigurablearchitecturesandvariousprocessingalternatives.Chapter 3 covers typicaldigitalbasebandprocessingtasksincontemporarywirelesscommunication systems.Thesetwointroductorychaptersarenotintendedtogivedetaileddescriptionsoneachofthesubject.Theyarepresentedtogivereferenceinformationon termsandconceptsusedlaterinthebook.

Chapter 4 introducesthecoarse-graineddynamicallyreconfigurablecellarray architecture,includingbothsysteminfrastructureandahardwaredesignflow.Using thecellarrayasabaselinearchitecture,Chaps. 5 and 6 presenttwocasestudiesto demonstratetheperformanceofthepresenteddomain-specificreconfigurablecell array.Thetwostudiesareconductedinaccordancetotheprocessingflowofa typicalbasebandprocessingchainatthereceiver.Inaddition,thetwocasestudies manifestarchitecturalevolutionofthecellarray,namelyfromscalar-tovectorbasedarchitecture.Chapter 7 opensupdiscussiononreconfigurablearchitecture designfornext-generationwirelesscommunicationsystems.Signalprocessing operationsinMassiveMIMOanddesignchallengesforreconfigurableplatforms arediscussed.

1.2.1Chapter 4:TheReconfigurableCellArray

Conventionalfine-grainedarchitectures,suchasFPGAs,providegreatflexibility byallowingbit-levelmanipulationsinsystemdesigns.However,thefine-grained configurabilityresultsinlongconfigurationtimeandpoorareaandpowerefficiency, andthusrestrictstheusageofsucharchitecturesintime-criticalandarea/powerlimitedapplications.Toaddresstheseissues,recentworkfocusesoncoarse-grained architectures,aimingtoprovideabalancebetweenflexibilityandhardwareefficiencybyadoptingword-leveldataprocessing.Inthischapter,acoarse-grained dynamicallyreconfigurablecellarrayarchitectureispresented.Thearchitecture isconstructedfromanarrayofheterogeneousfunctionalunitscommunicating viahierarchicalnetworkinterconnects.Thestrengthofthearchitectureliesinthe simplifieddatasharingachievedbydecoupledprocessingandmemorycells,the substantialcommunicationcostreductionobtainedbyahierarchicalnetworkstructure,andthefastcontextswitchingenabledbyauniquerun-timereconfiguration mechanism.

1.2.2Chapter 5:Multi-StandardDigitalFront-EndProcessing

Thischapteraimsatdemonstratingtheflexibilityofthereconfigurablecellarray architectureandevaluatingthecontroloverheadofhardwarereconfigurations,in termsofclockcyclesandareaconsumption.Forthispurpose,thecellarrayis configuredtoconcurrentlyprocessmultipleradiostandards.FlexibilityofthearchitectureisdemonstratedbyperformingtimesynchronizationandCarrierfrequency offset(CFO)estimationinadigitalfront-endreceiverformultipleOFDM-based standards.Asaproof-of-concept,thisbookfocusesonthreecontemporarilywidely usedradiostandards,3GPPLTEs,IEEE802.11n,andDigitalvideobroadcasting forhandheld(DVB-H).Theemployedreconfigurablecellarray,containing2 2 resourcecells,supportsallthreestandardsandiscapableofprocessingtwo concurrentdatastreams.Dynamicconfigurationofthecellarrayenablesrun-time switchingbetweendifferentstandardsandallowsadoptionofdifferentalgorithms onthesameplatform.Thankstotheadoptedfastconfigurationscheme,context switchingbetweendifferentoperationscenariosrequiresatmost11clockcycles.

1.2.3Chapter 6:Multi-TaskMIMOSignalProcessing

Thischapteraimsatdemonstratingtheflexibilityandreal-timeprocessingcapabilityofthecellarrayaswellasevaluatingtheareaandenergyefficiencywhen performingsophisticatedbasebandprocessingtasks.

Drivenbytherequirementofmulti-dimensionalcomputingincontemporary wirelesscommunicationtechnologies,reconfigurableplatformshavecometothe eraofvector-basedarchitectures.Inthischapter,thereconfigurablecellarrayis extendedwithextensivevectorcomputingcapabilities,aimingforhigh-throughput basebandprocessinginMIMO-OFDMsystems.Besidestheheterogeneousand hierarchicalresourcedeployments,avector-enhancedSingleinstructionmultiple data(SIMD)structureandvariousmemoryaccessschemesareemployed.These architecturalenhancementsaredesignedtosufficestringentcomputationalrequirementswhileretaininghighflexibilityandhardwareefficiency.Todemonstrate itsperformanceandflexibility,threecomputationallyintensiveblocks,namely channelestimation,channelpre-processing,andsymboldetection,ofa4 4MIMO processingchainina20MHz64-QAM3GPPLongtermevolution-advanced(LTEA)downlinkaremappedandprocessedinreal-time.

1.2.4Chapter 7:FutureMulti-UserMIMOSystems

Thischapterlooksaheadintoadvancedmulti-userMassiveMIMOtechnology for5Gwirelesscommunicationsystemsandopensupdiscussionforitsbaseband

processordesign.Wirelesscommunicationtechnologyisevolvingatafastpace tomeetrequirementsofemergingapplications.Accordingly,thedevelopedreconfigurablearchitectureshouldbeextensibletosupportsignalprocessinginfuture wirelesscommunicationsystems.Inthischapter,thebasicconceptoftherelatively newMIMOtechnology,MassiveMIMO,isintroduced.Tofacilitatethecorrespondinghardwarearchitecturedesign,operationsinMassiveMIMObaseband processingareprofiledandanalyzed.Additionally,wediscusshowthenewfeatures inMassiveMIMOprocessingaffectthearchitecturedesign,intermsofoperation characteristicsandprocessingdistribution.Thischapterservesasapre-studyanda designguidelinefordevelopinganefficientreconfigurablecomputingplatformfor MassiveMIMOsystems.

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19.T.J.Todman,G.A.Constantinides,S.J.E.Wilton,O.Mencer,W.Luk,P.Y.K.Cheung, Reconfigurablecomputing:architecturesanddesignmethods.Comput.Digit.Tech. 152, 193–207(2005)

20.C.C.Wang,F.L.Yuan,H.Chen,D.Markovi ´ c,A1.1GOPS/mWFPGAchipwithhierarchical interconnectfabric,in IEEESymposiumonVLSICircuits(VLSIC),June2011,pp.136–137

21.M.Woh,S.Mahlke,T.Mudge,C.Chakrabarti,Mobilesupercomputersforthenext-generation cellphone.IEEEComput. 43(1),81–85(2010)

Chapter2

DigitalHardwarePlatforms

Sincetheinventionoftheintegratedcircuitinthe1950s,therehasbeenexplosive developmentsofelectroniccircuits.Overthelastdecades,theamountoftransistors, whicharethefundamentalelementsofdigitalandanalogcircuits,fittingonasingle silicondiehasincreasedexponentially,fromafewthousandstobillionstodate.This trendwasalreadyobservedin1965[15]byIntel’sco-founderGordonE.Mooreand latercametobeknownas“Moore’slaw”coinedbyCarverMead.Moore’slawhas heldtruesincethenandisadrivingforceoftheadvancementsofVery-large-scale integration(VLSI)design[11].

Enabledbythetechnologyadvancements,variousformsofhardwareplatformsemergedtocatertoavarietyofapplications.Dependingondesigntradeoffsbetweenflexibilityandefficiency,theseplatformscanbebroadlydivided intothreeclasses,namely programmableprocessors, reconfigurablearchitectures, and Application-specificintegratedcircuits(ASICs).Programmableprocessors include,forexample,Generalpurposeprocessors(GPPs)andApplication-specific instructionsetprocessors(ASIPs).Reconfigurablearchitecturesdifferfromthe programmableprocessorsinawaythattheyexposebothdataandcontrolpath totheuserandare“programmable”throughhardwareconfigurations.Fieldprogrammablegatearray(FPGA)isawell-recognizedexampleofthisarchitecture category.ASICsarecustomizeddesignswithlimitedflexibility.Hardwaremodificationsafterchipfabricationfornewfunctionadoptionisbarelypossibleforthis typeofplatforms.Theyarecommonlyusedintime-andpower-criticalsystems, whereflexibilityisnotaprimaryconcern.Figure 2.1 illustratesageneralview ofhowthesethreeclassesofplatformsfareintheflexibility-efficiencydesign space.Itshouldbepointedoutthatcomparisonofparticulararchitectureinstances amongtheseclasseshasbecomeincreasinglyobscurebecauseofhugearchitecture varietiesanddifferentoptimizationobjectivessuchasapplicationdomainsand speedgrades.Thus,Fig. 2.1 onlyservestogiveanoverviewofhowdifferent platformstradeflexibilityforefficiency.Flexibility,includingprogrammabilityand

Fig.2.1 Comparisonofflexibilityandefficiencyforvariousformsofhardwareplatforms.This bookfocusesonthedesignofCoarse-grainedreconfigurablearchitectures(CGRAs)

versatility,ismeasuredastheabilitytoadoptaplatformintodifferentapplication domainsandtoperformdifferenttasks.Forinstance,GPPsarehighlyflexible platformssincetheyaredesignedwithouthavinganyparticularapplicationinmind. Efficiencyrelatestobothcomputationalperformanceandenergyconsumptionand isameasureofhowwellaplatformperformsinanapplication.Inthiscontext, ASICsrevealthehighestefficiencybecauseofhardwarecustomizations.Thisbook focusesonCoarse-grainedreconfigurablearchitectures(CGRAs),aimingtobridge theflexibility-efficiencygapbetweenASICsandtheothertwoclassesofplatforms, illustratedinFig. 2.1.

2.1ProgrammableProcessors

Programmableprocessorsaredesignedbasedoninstructionsets,whicharespecificationsofoperationcodes(opcodes)usedtoconductoperationsofunderlying hardwareelements.Dependingondesignobjectives,aninstructionsetcanbe optimizedwithrespectto,forexample,applicationdomainandfriendlinesstohighlevelprogrammingconstructs[10].SomeexamplesofInstructionsetarchitecture (ISA)categoriesareComplexinstructionsetcomputing(CISC),Reducedinstructionsetcomputing(RISC),andVerylonginstructionword(VLIW).

Basedupontheretargetabilityoftheinstructionset,programmableprocessors canbecategorizedintofixedandconfigurableISAs.Comparedtothelatterone, fixedISAsareeasytodesignandcanbeoptimizedforobtaininghighperformance suchashighclockfrequencybydeeppipelining[10].ExamplesoffixedISAsare GPPs,special-purposeprocessors,andASIPs.ConfigurableISAsprovidetheuser flexibilitiesinselectingappropriateinstructionsfortargetapplications.Thisway, theISAscanbecustomizedtoattainhigherefficiencyincomparisontofixedISAs. However,thisinstructionsetcustomizabilitycomplicatesthedesignofbaseline architectureandsoftwaretoolchain(e.g.,compilerandemulator).

2.1.1General-PurposeProcessors

GPPsarehighlyprogrammable,capableofsupportinganyalgorithmthatcanbe compiledtoacomputerprogram.Thus,theyaredominantlyusedinpersonal computers.AlthoughGPPshavealwaysbeenimplementedwiththelatestsemiconductortechnologyinordertoachievethehighestpossibleprocessingspeed, theysufferfromaperformancebottleneck:thesequentialnatureofprogram execution.Toaddressthisissue,manydesigntechniqueshavebeenproposed, whichrangefromISAtomicroarchitecturedesignwithagoalofincreasingthe numberofexecutedinstructionspersecond.Examplesofthesetechniquesare superscalarandVLIWarchitecturesforexploiting Instruction-levelparallelism (ILP),Singleinstructionmultipledata(SIMD)architectures(e.g.,Intel’sPentium MMXandAMD’s3DNow!ISA)forenabling Data-levelparallelism(DLP),and multithreadingtechnology(e.g.,Intel’shyper-threading[14])forproviding Threadlevelparallelism(TLP).Furthermore,GPPshaveshiftedtoamulti-coreparadigm duetoenergyandpowerconstraintsongrowthincomputingperformance[7].

Figure 2.2 showstheslowdowninprocessorperformancegrowth,clockspeed,and powerconsumption,aswellasthecontinuedexponentialgrowthinthenumberof transistorsperchip[7].

Fig.2.2 Transistors,frequency,power,performance,andprocessorcoresovertime[7]

2.1.2Special-PurposeProcessors

Special-purposeprocessorsaredesignedtobeusedforaparticularapplication domain.Well-knownexamplesareDigitalsignalprocessors(DSPs)andGraphicsprocessingunits(GPUs).DSPsaredesignedforperformingdigitalsignal processingtaskssuchasfilteringandtransforms.Commonlyusedoperationsin signalprocessingalgorithmsareacceleratedinDSPs.Anexampleismultiplication followedbyaccumulation,widelyusedindigitalfilters[18].Thisoperationis performedusingdedicatedMultiply-accumulate(MAC)unitsinDSPsandusually takesoneclockcycletoexecute.Othercommonlyusedoperationsincludevarious addressingmodessuchasmoduloandring-buffer.

GPUsarespecializedcomputationalunitsdedicatedtomanipulatingcomputer graphics.Thankstotheirhighlyparallelstructure(e.g.,containinghundredsof processingcores[16]),theyareabletoprocesslargeblocksofdatainparallel. Takingadvantageofthehighprocessingcapability,General-Purposecomputingon GraphicsProcessingUnit(GPGPU)hasrecentlygainedinpopularity.Anexample istheCUDAplatform[8]fromNvidia,whichsupportsC/CCC andFortran programmingonGPUsandcanalsobeusedforMatlabprogramaccelerations[17].

2.1.3Application-SpecificInstructionSetProcessors

ComparedtoDSPsandGPUs,ASIPsareoptimizedforasingleapplicationora smallgroupsofapplications[13].Ageneraldesignflowisthatabaselineprocessor, whichcouldbeaRISCprocessororDSP,isextendedwithapplication-specific instructions.Besides,infrequentlyusedinstructionsandfunctionunitsarepruned, aimingtotradeflexibilityforenergyandcostefficiency.

2.1.4ConfigurableInstructionSetProcessors

DifferentfromthefixedISAs,configurableinstructionsetprocessorsprovideusers acollectionofinstructionsandabaselinearchitecturecontainingvarioushardware features.Dependingontargetapplications,usershavethepossibilityofselecting appropriateinstructionstoconstructacustomizedinstructionsetatdesign-time. Meanwhile,themicroarchitectureoftheprocessorscanbecustomizedbyselecting, forexample,differentfunctionunitsandthenumberofpipelinestages.Oncethe instructionsetandthemicroarchitecturearefinetuned,hardwareimplementation oftheprocessorisgenerated.Fromthehardware’spointofview,thegenerated processorisatypeofASIP,however,withon-demandfunctioncustomizations. Xtensaconfigurablecores[3]fromCadence(previouslyTensilica)isanexample oftheconfigurableinstructionsetprocessor.Thankstotheinstructionsetand

microarchitecturecustomizations,thistypeofprocessorsprovideshighprocessing performanceandhardwareefficiency.However,designofthebaselinearchitecture andthecorrespondingsoftwaresupportaremorecomplicatedthanfixedISAs,since theyneedtocoverahugesetofconfigurations.

2.2Application-SpecificIntegratedCircuits

ASICsaredesignedtoperformspecifictasks.Therefore,computationaldatapaths andcontrolcircuitscanbeoptimizedforparticularusecases.ThisbringsASICs tothefarrightofthedesignspaceinFig. 2.1,indicatingthattheyarethemost efficient(intermsofperformanceandenergyconsumption)typeofplatforms amongthethreeclasses.Therefore,ASICsarecommonlyusedtoachievereal-time performancewithinthebudgetforphysicalsizeandenergydissipation.However, thespecializedhardwarearchitecturelimitsthecapabilityofadaptingsystemto differentapplicationsandoperationscenarios.Thislimitationresultsinreduced overallareaefficiencyintermsofhardwarereuseandsharing.Additionally,this typeofplatformsrequiresaratherlonghardwareredesigntime(forbug-fixesor functionupdates)andexhaustivetestingprocedures.Furthermore,theexploding silicondesigncostlimitstheadoptionofASICs,especiallyindeepsub-micro semiconductortechnology.

2.3ReconfigurableArchitectures

Reconfigurablearchitecturesaretheoneshavingthecapabilityofmakingsubstantialchangestothedatapathitselfinadditiontothecontrolflow.Thismeans thatnotonlythesoftwarethatrunsonaplatformismodified,butalsohowthe hardwarearchitectureoperates[1, 5, 6, 9, 21, 22].Withcombinedcontroland datapathmanipulations,reconfigurablearchitecturesareabletoexploitpotential parallelism,enableenergyefficientcomputing,allowextensivehardwarereuse,and reducesystemdesigncycleandcost[12].

Reconfigurablearchitecturesareeither homogeneous or heterogeneous.Ina homogeneousarchitecture,allelementscontainthesamehardwareresources.This uniformstructuresimplifiesthemappingofuserapplications,sinceadditional constraintsonfunctionpartitionsandplacementsareavoided.However,homogeneousstructuresareinefficientintermsofhardwareutilizationoflogicandrouting resources[12].Incontrast,heterogeneousarchitecturescontainarrayelementswith differentfunctionality,suchasspecializedelementsforstreamdataprocessingor control-flowhandling.Comparedtothehomogeneousstructure,adoptionofvarious typesofarrayelementsreduceshardwareoverheadandimprovespowerefficiency atthecostofmorecomplexmappingalgorithms.

Thesizeofthehardwareelementsinsideareconfigurablearchitectureisreferred toas granularity.Fine-grainedarchitecturesandCGRAsaretwovariantsof reconfigurablearchitectures.Fine-grainedarchitectures,suchasFPGAs,areusually builtuponsmallLook-uptables(LUTs).Sucharchitectureshavetheabilityto mapanylogicfunctionsatbit-levelontotheirfine-grainedlattice.However,this bit-orientedarchitectureresultsinalargeamountofcontrolandroutingoverhead, forexample,whenperformingword-levelcomputations.Theseoverheadsalso affectpowerconsumptionandsystemconfigurationtime.Incontrast,CGRAs areconstructedfromlargerbuildingblocksinasizerangingfromArithmetic logicunits(ALUs)tofull-scaleprocessors.Thesehardwareblockscommunicate throughaword-levelroutingnetwork.TheincreasedgranularityinCGRAsreduces routingareaoverhead,improvesconfigurationtime,andachieveshigherpower efficiencydespitelessmappingflexibility.Besides,CGRAsdifferfromfinegrainedarchitecturesindesignmethodology.Tomapfunctionalityintogates,FPGA designsrelyonahardware-centricapproach,whichusuallyrequiresprogramming inHardwaredescriptionlanguage(HDL)suchasVHDL.Incontrast,CGRAs provideamoresoftware-centricprogrammingapproachtomapfunctionalityto, forexample,processingcoresusingahigherlevellanguagelikeC.Softwarecentricdesignapproachenhancesproductivityandsimplifiessystemintegrationand verification.

ThisbookfocusesonthedevelopmentofCGRA,morespecifically,domainspecificCGRAforbasebandprocessinginwirelesscommunicationsystems. DetailedarchitectureofthepresentedCGRA-baseddynamicallyreconfigurable cellarrayispresentedinChap. 4 withcasestudiesinChaps. 5 and 6.

2.4ACommentonPowerEfficiency

AsmentionedinChap. 1,primaryconcernsforcontemporarysystemdesignsare shiftingfromcomputationalperformancetopowerefficiency[2, 20].Attaininghigh powerefficiencyisespeciallyimportantforthetargetapplicationsofthisbook, namelysmall-scalebasestationsandmobileterminals,sincetheyareallconstrained bystringentpowerrequirements.Thus,itiscrucialtohaveabetterunderstanding ofthecompositionofpowerconsumption.

ThetotalpowerconsumptionforadigitalcircuitbuiltwithCMOStransistors maybeexpressedas[19]

where Ptotal , Pdynamic ,and Pleakage representthetotal,dynamic,andleakagepower consumption,respectively. ˛ istheswitchingactivityofthecircuit, CL theload

capacitance, CSC theshortcircuitcapacitance, VDD thesupplyvoltage,and f the clockfrequency. IDC and Ileak denotethestaticandleakagecurrent,respectively. Inthedesignofreconfigurablearchitectures, Pdynamic isusuallyadominating factorbecauseofhighclockfrequencyandhardwareutilization.Incomparison, theleakagepowerisoflessconcernforsuchkindofarchitectures.However,it shouldbepointedoutthatleakagepowerisbecomingmoreandmoreimportant withtechnologyscalingandthusneedsmoreattention.Oneofthewell-known approachesfordesigninglowpowercircuitsistoreducethequadraticterm V 2 DD in(2.1)atthecostofperformancesacrificesuchasclockfrequency.Tocompensate fortheperformanceloss,differenttechniquescanbeusedsuchaspipeliningand parallelprocessing[4]butattheexpenseofareaconsumption.Thus,itcanbeseen thathardwaredesigningisatrade-offbetweenvariousparametersamongthedesign space.

References

1.Z.Abdin,B.Svensson,Evolutioninarchitecturesandprogrammingmethodologiesofcoarsegrainedreconfigurablecomputing.MicroprocessorsMicrosyst.Embed.Hardw.Des. 33, 161–178(2009)

2.S.Borkar,Thousandcorechips-atechnologyperspective,in 44thAnnualDesignAutomation Conference(DAC),2007,pp.746–749

3.J.Byrne,TensilicaDSPtargetsLTEadvanced,Mar2011. http://www.tensilica.com/uploads/ pdf/MPR_BBE64.pdf

4.A.P.Chandrakasan,S.Sheng,R.W.Brodersen,Low-powerCMOSdigitaldesign.IEEEJ. SolidStateCircuits 27(4),473–484(1992)

5.A.Chattopadhyay,Ingredientsofadaptability:asurveyofreconfigurableprocessors.in VLSI Design,Jan2013

6.K.Compton,S.Hauck,Reconfigurablecomputing:asurveyofsystemsandsoftware.ACM Comput.Surv. 34,171–210(2002)

7.S.H.Fuller,L.I.Millett,Computingperformance:gameoverornextlevel?Computer 44(1), 31–38(2011)

8.M.Garland,etal.,ParallelcomputingexperienceswithCUDA.IEEEMicro 28(4),13–27 (2008)

9.R.Hartenstein,Adecadeofreconfigurablecomputing:avisionaryretrospective,in Design, AutomationTestinEuropeConferenceExhibition(DATE),2001,pp.642–649

10.J.L.Hennessy,D.A.Patterson, ComputerArchitecture:AQuantitativeApproach,4thedn. (MorganKaufmannPublishers,SanFrancisco,CA,2003)

11.R.W.Keyes,TheimpactofMoore’slaw.IEEESolidStateCircuitsSoc.Newslett. 11(5), 25–27(2006)

12.T.Lenart,Designofreconfigurablehardwarearchitecturesforreal-timeapplications.Ph.D. thesis,DepartmentofElectricalandInformationTechnology,LundUniversity,May2008

13.D.Liu, EmbeddedDSPProcessorDesign:ApplicationSpecificInstructionSetProcessors,1st edn.(MorganKaufmannPublishers,SanFrancisco,CA,2008)

14.D.Marr,etal.,Hyper-threadingtechnologyarchitectureandmicroarchitecture:ahypertext history.IntelTechnol.J. 6(1),4–15(2002)

15.G.E.Moore,Crammingmorecomponentsontointegratedcircuits.Electronics 38(8), 114–117(1965)

16.NVIDIA,TeslaC2050/C2070GPUComputingProcessor,July2010

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This wonderful example of man’s handiwork connects the extreme lower points of Prospect Park on the American side, with Victoria Park on the Canadian side. It has a single deck, is 1,268 feet long, 49 feet wide and 190 feet above the water, and was built in 1898. Splendid views are had from this bridge. High-Resolution

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The Ice Palace, a thing of beauty in the production of which man essayed to supplement Nature, was erected in the State Reservation in the winter of 1898. “An area of 120 by 160 feet was covered by its gleaming walls of crystal. The entire structure was gay with bunting and flags by day and brilliant with electrical illumination by night.”

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LUNA ISLAND BRIDGE BRIDGE TO THIRD SISTER ISLAND

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Stands on Queenston Heights, about four miles below the Whirlpool It was erected to commemorate the memory of Sir Isaac Brock who fell in battle in the war of 1812. It is a noble shaft, 100 feet high, capped with a statue of Brock. It is seen for many miles in all directions.

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This Suspension Bridge is now the only one which spans Niagara River It links Queenston on the Canadian side with Lewiston on the American side, seven miles below the Falls, and is crossed by the Belt Line trolley route about the Gorge. The suspended span is 800 feet, and it has a cable span of 1040 feet.

A FAMILIAR WINTER SCENE IN PROSPECT PARK.

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Hig hRes oluti on

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Issuu converts static files into: digital portfolios, online yearbooks, online catalogs, digital photo albums and more. Sign up and create your flipbook.