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Volume 22, Number 4

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A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

THE BODY ELECTRIC

2019 Medical Electronics Symposium May 21 & 22, 2019

Lorain County Community College, Elyria, Ohio

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page 11 DARPA’s CHIPS Program for IP Reuse and Heterogeneous Integration page 15 Packaging & Assembly for High-Temperature Electronics Part I – Devices and Materials page 19

Tufts University researchers have developed a “smart” bandage that will actively monitor the condition of wounds and deliver drug treatments to improve healing. The bioelectronics bandage features integrated pH and temperatures sensors that electronically trigger drug release when it senses that wounds are not healing properly.

page 28 -Corp.

INSIDE THIS ISSUE

12 24 SoC Silicon and Software 2018 Design Cost Analysis

ISO 9001 is viewed by most people as the minimum table stakes of good business practice.

30

Ensuring the reliability of package designs has become essential to long-term performance.

34

Advancements in “connected” medical electronics are revolutionizing the health care industry.


A proud legacy. An exciting future. As the original pioneers of the OSAT industry, Amkor has helped define and advance the technology manufacturing landscape. Since 1968, we’ve delivered innovative packaging solutions with the service and capacity global customers rely on.

We’re proud of what we’ve done, and can’t wait to show you what’s next.

www.amkor.com


315 Savannah River Dr., Summerville, SC 29485 Tel: (650) 714-1570 Email: bcooper@meptec.org

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Volume 22, Number 4

The 2019 MEPTEC/SMTA Medical Electronics Symposium, “The Body Electric”, is a two-day event to be held on Tuesday and Wednesday, May 21st and 22nd at Lorain County Community College in Elyria, Ohio. This event will bring together experts to cover topics such as: Forecasting and Analytics, MEMS, Sensors and Integrated Circuits, Implantable Devices and Neural Interface, Medical Robotics, Equipment, and Prosthetics, Packaging and Board Level Assembly, Advanced Materials and Reliability. (see page 11)

THE BODY ELECTRIC

2019 Medical Electronics Symposium May 21 & 22, 2019

MEPTEC Advisory Board

Lorain County Community College, Elyria, Ohio

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page 11

Board Members Ivor Barber AMD Jack Belani Indium Corporation Joel Camarda Altierre

DARPA’s CHIPS Program for IP Reuse and Heterogeneous Integration page 15 Packaging & Assembly for High-Temperature Electronics Part I – Devices and Materials page 19

Tufts University researchers have developed a “smart” bandage that will actively monitor the condition of wounds and deliver drug treatments to improve healing. The bioelectronics bandage features integrated pH and temperatures sensors that electronically trigger drug release when it senses that wounds are not healing properly.

page 28 -Corp.

INSIDE THIS ISSUE

12 24 SoC Silicon and Software 2018 Design Cost Analysis

ISO 9001 is viewed by most people as the minimum table stakes of good business practice.

30

Ensuring the reliability of package designs has become essential to long-term performance.

34

Volume 22, Number 4

ON THE COVER

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Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards

WINTER 2018

The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council

Advancements in “connected” medical electronics are revolutionizing the health care industry.

Jeff Demmin Booz Allen Hamilton Douglass Dixon Henkel Corporation Nick Leonardi SMART Microsystems Phil Marcoux PPM Associates Gamal Refai-Ahmed Xilinx Herb Reiter eda 2 asic Consulting Rich Rice ASE (US) Inc. Scott Sikorski STATS ChipPAC Jim Walker WLP Concepts Special Advisors Ron Jones N-Able Group International Mary Olsson Gary Smith EDA Honorary Advisors Seth Alavi Sunsil Gary Catlin Rob Cole Skip Fehr Anna Gualtieri Elle Technology Marc Papageorge ICINTEK In Memoriam Bance Hom

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ANALYSIS – Silicon designers and system architects are constantly looking for ways to reduce their design costs and still meet market requirements and ASP targets. This article references data and analysis from Semico’s report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, SC103-18. RICH WAWRZYNIAK PRINCIPAL ANALYST: ASIC & SOC, SEMICO

INTEGRATION technologies are integrated. With a standard CHIPS interface for heterogeneous integration, IP reuse is enabled at the chiplet level. Heterogeneous design will become essentially the same as monolithic design, with the knowledge that IP blocks can be integrated successfully. Finally, a modular design paradigm is needed to enable designers to take full advantage of interface standards and heterogeneous IP reuse. Design tools and process design kits (PDKs) will account for different device technologies and their integration, with the appropriate design, simulation, and analysis capabilities in place. CHIPS Program Structure The CHIPS program is structured in two Technical Areas (TAs) – Modular Digital Systems (TA1) and Supporting Technologies (TA3). System performers are Intel, Lockheed Martin, Northrop Grumman, and the University of Michigan. Each of the System performers is designing a system using the CHIPS approach, and the teams are also collaborating to specify and implement an interface standard. Since convergence on the interface standard is required before designs can be finalized, this was the first major milestone in the CHIPS program. The Supporting Technologies performers are providing IP blocks and design tools that will be used by the system designers, although the IP blocks and design tools will be developed with broader usage in mind. Performers developing design tools are Georgia Tech and Cadence, while IP blocks are being developed by Intrinsix, Jariet Technologies, Micron Technology, North Carolina State University, and Synopsys. The system designers will also be providing IP blocks. To ensure successful integration, the CHIPS program is also pursuing multiple integration strategies. The first will be a leading edge but broadly available industry standard interconnect on a silicon interposer, while at least one other approach with much finer pitch will be developed in parallel for Phase 2 of the four-year program. CHIPS Interface Standard The performers in the CHIPS program have agreed to base the CHIPS 16 MEPTEC REPORT

Figure 1. The basic AIB I/O cell (left) and clock forwarding architecture (right). (Source: Intel)

interface standard on Intel’s Advanced Interface Bus (AIB) standard. This was enabled by Intel offering a paid-up, royalty-free license for the relevant IP and documentation. After extensive discussion and debate among the CHIPS performers, AIB was chosen as the basis for the CHIPS interface. The key factors in that decision were: 1) performance metrics that meet the CHIPS requirements, 2) the flexibility to meet a range of applications, with CHIPS-specific “lite” and “turbo” options, for example, and 3) silicon-proven maturity based on Intel’s use of AIB. The I/O cell and details of the clock forwarding architecture are shown in Figure 1. Chiplets, IP Reuse, and Design The success of the CHIPS program depends on creating a set of IP blocks with numerous applications, since a key

Table II. Chiplets in Process for CHIPS Phase 1 or Proposed for Phase 2.

part of the CHIPS premise is reuse of common IP blocks. The CHIPS program has selected several performers to provide IP blocks for the program, whether for their own system demonstrations or for use by others in the program. Chiplets currently being designed and manufactured in Phase 1 and those under consideration for Phase 2 are summarized in Table II. The chiplet sizes range from approximately 0.5mm2 to 15mm2, with most being 1-4mm2. Plans for chiplet fabrication include leveraging multi-project wafer (MPW) runs at GlobalFoundries (14nm, 32nm, and 65nm) and TSMC (16nm node via DARPA’s CRAFT program). Design tools for a vertically-integrated design flow for IP reuse and heterogeneous integration are under development by Georgia Tech. That team’s tasks include protocol implementation, analysis of chiplet options, interposer routing analysis, and power delivery network analysis. A sample analysis indicates a 33% reduction in power with an integrated voltage regulator chiplet, and the voltage response in that scenario is shown in Figure 2. Cadence Design Systems is contributing to the CHIPS design environment by creating models of different interconnect schemes and verifying them with measurements performed by NIST. Their studies are covering organic and silicon interposer options. Modular Design and Applications The pieces of the CHIPS program are being brought together in a phased sequence of demonstrations: interface functionality (Phase 1), modular systems (Phase 2), and rapid modular system

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upgrade (Phase 3). A number of teams are developing systems with the CHIPS approach. Intel is developing a platform based on its Stratix-10 FPGA (Figure 3), which enables a wide range of applications, including those that leverage machine learning. The CHIPS interface based on Intel’s AIB is used to connect the FPGA to various chiplets (e.g., data converters, ASICs, processors, and analog functions), and memory can be integrated with other standard interfaces. The CHIPS team at the University of Michigan has made rapid progress with its first set of chiplets being taped out in April 2018 for a 16nm MPW run at TSMC via DARPA’s CRAFT (Circuit Realization at Faster Timescales) program. This includes a deep neural network (DNN) accelerator and neuro-coding chiplets for visual processing applications, as well as the first CHIPS instantiation of the AIB-based interface (Figure 4). Lockheed Martin Advanced Technology Laboratories has proposed an application that addresses a spectrum of common DoD challenges [10]. Along with the inherent cost reduction of decreasing the total design and manufacturing effort required for system upgrades, the CHIPS approach improves reliability, qualification cost and time, and diminishing manufacturing sources (DMS) challenges. With a modular electronics sub-system based on IP reuse and standard interfaces, it is possible to swap in just the components that need an upgrade, thus preventing a total overhaul of the system to retain leadingedge performance. This is particularly critical for applications with life cycles measured in decades, such as aircraft. Lockheed is pursuing this approach in a network interface unit in a major avionics platform. Northrop Grumman Mission Systems (NGMS) is also pursuing CHIPS-based systems for defense applications and has identified digital transceivers as an application that could benefit from a chipletbased approach. By separating the SoC into separate functions, it is possible to optimize the device node and even the foundry source [11]. For this application, a key enabling technology for SoC disaggregation is sub-10µm interconnect pitch, and NGMS is working with Micross to develop this.

Core chiplet IVR chiplet

Passive chiplet

IVR

L, C

LDO

0.8

0.4 0.2 0

PCB

Droop

0.6

interposer package

Interposer VR

DC drop

VOUT

Settling time

IL

ΔIL 1.9

1.95

2

2.05

2.1

2.15

Time (µs)

2.2

2.25

2.3

2.35

Figure 2. Georgia Tech’s design tools enable analysis of chiplet integrated voltage regulator performance, among many other features. (Source: Georgia Tech)

Figure 3. Intel’s CHIPS application platform is based on its Stratix-10 FPGA. (Source: Intel)

Figure 4. Michigan’s initial set of chiplets were taped out in April 2018 for a 16nm CMOS MPW foundry run and included an AIB test chip. (Source: U. of Michigan)

Manufacturing and Supply Chain Early in the CHIPS program, the performers settled on 55µm Cu pillar interconnect as the primary path, since this represents the finest pitch interconnect that has an established supply chain and user base. As the first step in the CHIPS program, it is a convenient compromise using leadingedge but broadly available technology.

In parallel, two CHIPS teams are developing alternative interconnect approaches with much finer pitch interconnect to extend the CHIPS roadmap well into the future. Micross and NGMS are collaborating on ultra-fine-pitch interconnect, which NGMS has shown to be a critical enabler for their target applications. Micross has demonstrated both Cu WINTER 2018 MEPTEC REPORT 17

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William Boyce SMART Microsystems Ltd. Jeffrey Demmin Booz Allen Hamilton Ira Feldman Feldman Engineering Corp.

State-of-the-Art Technology Briefs

organization. This means that the executive level manager in the organization can no longer just push the requirements on to the quality representative, they must be engaged. This approach fosters a top down effect that demonstrates to everyone in the organization that the top management is quality centric, and has real buy-in. I think that we can all agree that this is good for any organization. When most people that have been in business for some time think of ISO compliance, they think of a lot of meaningless paperwork and painful audits. But this is quite simply not the case, because the current ISO compliance does

William Boyce is the Engineering Manager at SMART Microsystems. He has served in senior engineering roles over the last 19 years with accomplishments that include manufactured automotive sensors. He is certified in EIT and Six Sigma Green Belt and is an industry recognized expert in Al wire bonding. Additionally, he designed and led the metrology lab and machine shop at Sensata. Mr. Boyce earned a Bachelor of Science in Engineering degree from the University of Rhode Island and has been a member of the IMAPS New England Chapter for over 10 years.

The SMART Advantage. Lowest Overall Development Time and Cost.

Rose Guino Henkel Electronic Materials LLC Ron Jones N-Able Group International

Custom Prototype and Process Development

Custom Environmental Life Test and Failure Analysis

ISO9001:2015 C E R T I F I E D

Custom Manufacturing Services

DEVELOPMENT, TESTING, AND MANUFACTURING OF UNIQUE CUSTOMER-DESIGNED PRODUCTS

26 MEPTEC REPORT WINTER 2018

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A special feature courtesy of Binghamton University We are pleased to continue this feature in the MEPTEC Report, brought to us by new Advisory Board member Dr. Gamal RafaiAhmed from Xilinx. The State-of-the-Art Technology Briefs contains articles from the Binghamton University S3IP “Flashes.” Full text is available upon request through the IEEC Site at: http://www.binghamton.edu/s3ip/index.html.

Additive 3-D printing manufacturing can be used to manufacture porous electrodes for lithium-ion batteries. However, because of manufacturing process limitations the design of these 3-D printed electrodes is limited to only a few architectures. Carnegie Mellon University researchers have developed a revolutionary new method of 3-D printing battery electrodes that creates a 3-D microlattice structure with controlled porosity. This structure used as batteries’ electrodes can improve battery performance with a fourfold increase in specific capacity and a twofold increase in areal capacity when compared to a solid block electrode. (IEEC file #10749, EIN 007, 8/1/18) Harvard University researchers have developed a new printing method that uses sound waves to generate droplets from liquids with a large range of composition and viscosity. This technique could enable the manufacturing of new biopharmaceuticals, cosmetics, and food, and expand optical and conductive materials applications. The use of acoustic forces enables myriad materials to be printed in a drop-on-demand manner. The researchers built a subwavelength acoustic resonator that can generate a highly confined acoustic field resulting in a pulling force exceeding 100 times the meptec.org

Dr. Randall K. Kirschman R&D Consultant

normal gravitation forces at the tip of the printer. (IEEC file #10793, Printed Electronics World, 9/11/18) University of Delaware engineers are developing the next-generation smart textiles. Their approach is an application of flexible carbon nanotube composites coatings on a series of fibers, such as nylon, cotton, and wool. Fabric suited with this sensing technology can lead the charge toward future “smart garments.” The carbon nanofibers release electrical changes in the fabric when squeezed. The coatings measure a large range of pressures. The nanocomposite coatings “are created on the fibers using electrophoretic deposition (EPD) of polyethyleneimine functionalized carbon nanotubes. (IEEC file #10768, Design News, 8/16/18)

University of Illinois researchers found that by “sandwiching” two-dimensional (2D) materials used in nanoelectronic devices between their three-dimensional silicon bases and an ultrathin layer of aluminum oxide they can significantly reduce the risk of component failure due to overheating. Many silicon-based electronic components contain 2D materials (such as graphene), hence incorporating 2D materials into components allows them to be several orders of magnitude smaller than if they were made with conventional, 3D materials. (IEEC file #10792, R&D, 9/12/18) A new method to 3D print lithium-ion batteries in virtually any shape has been developed by Duke University researchers. Electric vehicles and most electronic devices, such as cell phones and laptop computers, are powered by lithium-ion batteries. Until now, manufacturers have had

to design their devices around the size and shape of commercially available batteries. To print the lithium-ion batteries with a 3D printer, the researchers increased the ionic conductivity of PLA (polylactic acid) by infusing it with an electrolyte solution. In addition, they boosted the battery’s electrical conductivity by incorporating graphene or multi-walled carbon nanotubes into the anode or cathode, respectively. (IEEC file #10865, Science Daily, 10/17/18)

Chinese researchers have developed a hybrid conductive material that is part elastic polymer and part liquid metal. Circuits made with this material can take on most two-dimensional shapes, are highly conductive, stretchable, fully biocompatible and able to be fabricated conveniently across all size scales with micro-feature precision. This will have broad applications for both wearable electronics and implantable devices. (IEEC file #10803, US Tech, 9/14/18) RMIT University researchers have developed an option for scalable quantum computers using a topological photonic chip to process quantum information. The team demonstrated that quantum information can be encoded, processed and transferred at a distance with topological circuits on the chip. The new chip design will open the way to studying quantum effects in topological materials and to a new area of topologically robust quantum processing in integrated photonics technology. The breakthrough could lead to the development of new materials, new generation computers, and a better understanding of fundamental science. (IEEC file #10801, R&D, 9/14/18) WINTER 2018 MEPTEC REPORT 27

Design Complexity Levels Within each process geometry, there are differing levels of effort that directly relate to how expensive a particular design start is. These complexity levels are driven by several factors: • Gate count • Transistor budget • Architecture • Compute resources • Communications channels • Number and type of IP blocks • Feature sets and functionality dictated by market requirements • Software complexity

Advanced Performance Multicore SoC 1st Time Design Starts by Design Effort

Source: Semico Research Corp.

* Forecast

While software is not included in Semico’s analysis as a direct design cost, it does have a significant impact on the overall silicon architecture created to run that software. One of the major reasons for increasing design cost is the complexity of the software intended to run on the silicon and the architecture necessary to run these software applications efficiently and with good performance. As the software applications have become more feature rich, the silicon must also adapt to accommodate this rising complexity and the increase in the number of lines of code being run. With these thoughts in mind, the costs for each type of SoC are subdivided into different levels of effort to reflect that not all designs must function at the highest possible performance or functionality to be competitive in the market. Semico analyzes design activity based on a variety of different market segments and has created a model to gauge the impact of rising design costs on SoC design starts. Following is a review of the three categories of SoCs: Advanced Performance

Basic SoC 1st Time Design Starts by Design Effort

Multicore SoC, Value Multicore SoC and Basic SoC. The Advanced Performance Multicore SoC design starts represent the most complex and expensive designs at the beginning of each process node. Over the forecast period, the average silicon design cost for an Advanced Performance Multicore SoC will increase as designs become more complex and the effort to accomplish them increases. Silicon design costs for a first-time Advanced Performance Multicore SoC at the 7nm node are projected to be 23% higher than at the 10nm node. The increase in cost hasn’t pevented the released of new designs because there are a range of design costs which indicate differing levels of effort and complexity. A higher complexity part would require more tools, more IP, more people to complete and would take longer to accomplish than would a part with less complexity. As the number of design starts transition from older nodes to newer nodes, with their higher associated costs, the

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Source: Semico Research Corp.

* Forecast

average design cost for all Advanced Performance Multicore SoCs increases over the forecast period. However, since activity continues at the older nodes, the average design cost is not increasing as fast as the overall silicon design costs for this type of SoC at the most advanced nodes. The CAGR for average design costs for an Advanced Performance Multicore SoC is 2.5% for the period 2017 – 2023. The number of Value Multicore SoC design starts is almost double compared to the Advanced Performance Multicore SoC design starts. This is due to the fact that the Value designs are easier to accomplish, cost less and take less time to finish. This can give an advantage to companies that do not need to offer the most complex solution to their customers yet want to participate in their market with acceptable solutions that meet market requirements. The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017. Over the forecast period, the average silicon design cost

for a Value Multicore SoC will increase as designs become more complex and the effort to accomplish them increases. The fastest growing category as it relates to new designs is the Basic SoC. Basic SoC designs represent the least complex and least expensive efforts at the beginning of each process node. These design costs continue to decline over time as more designs are created, more expertise is gained, the costs of EDA tools decline over time and the reuse of IP increases. Removing derivative designs and respins shows that the number of 1st time efforts for Basic SoCs is growing the fastest of the three SoC types with a CAGR of 12.0% over the forecast period. An interesting note to the Basic SoC category is that many of these designs will be targeted at Internet of Things (IoT) applications. Semico believes that there will be a segment of these applications that will require higher functionality and will be a candidate for 28nm solutions over time. The total number of designs at 28nm starts out small

but increases over time. These designs will cost more and are responsible for the increase in average costs starting in 2014. Thereafter, these costs still increase but at a slower rate. This is also the reason for the large number of Basic SoC designs and the higher CAGR for these designs. They are coming from a relatively small base starting in 2008, but ramp quickly driven by IoT demand for lower cost solutions and reasonable functionality. Unlike Advanced Performance Multicore and Value Multicore SoCs, Basic SoCs see lower amounts of design activity below 28nm over the forecast period. Currently, this is due to the end applications for which Basic SoCs are used. These applications do not need the same complexity levels as the other two types of SoC. This will especially be true for Basic SoCs aimed at IoT solutions. These parts simply don’t need high complexity and their design costs are correspondingly lower, leading to a lower average design cost overall. In general, Semico believes that although design costs for complex SoCs have increased, and that re-spins and long design cycle times are not optimum conditions for the SoC market, their effect on market growth has not been overly detrimental. New, more efficient tool sets from EDA companies and semiconductor intellectual property blocks from 3rd party IP companies, make designers more productive and are well received by the market. Companies with innovative solutions are targeting the appropriate market application and are the main reason why design starts continue to grow. For more information on SoC design costs and SoC design starts by market application, contact Rick Vogelei at rickv@semico.com. ◆

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INTEGRATION – The path to higher performance requires a broader set of feasible device technology options. DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will address these challenges by developing interface standards, IP reuse methodologies, and modular design approaches. JEFFREY DEMMIN, BOOZ ALLEN HAMILTON ANDREAS OLOFSSON, DARPA

DR. RANDALL K. KIRSCHMAN R&D CONSULTANT FOR ELECTRONICS TECHNOLOGY

not dictate the method you use, only the results. Having just completed our annual registration reassessment audit with no findings, we often get the question “how do you do that?”. The answer is actually quite simple. As a microelectronics assembly business, we were ISO compliant long before we achieved ISO registration. In fact, internally as an organization, our audits are a non-event because nothing changes and no special preparation is required by the staff. We simply keep doing those things we have been doing all along. So, if your organization is doing all of the things that are required to be a good and customer focused business, you are already ISO compliant, so why not get credit for it and achieve registration. At SMART we use ISO registered suppliers, and we love to have ISO registered customers. For more information about SMART services visit smartmicrosystems.com. ◆

THE RISE IN SILICON AND software design costs has impacted and influenced design activity in the semiconductor industry and is shaping company strategies and the decisions designers are making as it relates to number and type of designs. While it is true that SoCs with the highest design costs probably contain the most complexity, it does not necessarily follow that every product in a given geometry must also incur the same high costs to be competitive. Silicon designers and system architects are constantly looking for ways to reduce their design costs and still meet market requirements and ASP targets. This article references data and analysis from Semico’s report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, SC103-18.

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improve. In our case, we conduct regular quality training of the entire staff to continuously improve our implementation of the QMS. We also perform regularly scheduled reviews of our processes and customer feedback at our scheduled management review meetings. Evidence-based decision making is a process like any other. It takes a certain level of organizational discipline to establish and maintain the process. There are a lot of tools that are available to facilitate the effort, like DFMEA, PFMEA, SPC, design reviews, and DOE. We use all of these tools and some others, on a regular basis, to bring quantitative data to the decision making process. The microelectronics assembly business is a very technical and detail oriented business, so tools like a FMEA and DOE are a natural fit. Over time, these tools have become a staple of our business, it just so happens that they also fit the ISO evidence based decision making model. Leadership, engagement of people, and relationship management are all basic requirements of good and effective leadership in any business. In the new ISO 9001 standard there is a very real focus on the engagement of management. In fact, the quality representative position in an organization has been eliminated in the new standard. This is driving action and engagement to higher levels in the

Rich Wawrzyniak Principal Analyst: ASIC & SoC, Semico

12 MEPTEC REPORT

PACKAGING – For more efficient use of resources, and to reduce energy waste and pollution, electronics must be extended into new areas. A key area is operation beyond the present “standard” or “military” temperature range of −55°C to +125°C. Power systems for electric vehicles and airplanes could be more efficient using high-temperature electronics (HTE).

TECH BRIEFS

Contributors

ANALYSIS

Impact of Rising Design Costs on SoC Design Starts

PACKAGING

INTEGRATION

Figure 5. Micross has demonstrated bonding on test structures at 5µm Cu/Cu pitch (left) and 10µm Au/Au pitch (right). (Source: Micross)

Figure 6. UCLA is developing an interconnect scheme that leverages silicon wafers as the substrate (left) with 10µm and below pitch Cu interconnections. (Source: UCLA)

and Au metallurgies for 10µm and below pitch (Figure 5) with non-collapsible bumps [12]. A team at UCLA is also developing sub-10µm interconnect for CHIPS. They have demonstrated Au-capped Cu pillar interconnect at 10µm pitch (Figure 6) and have roadmap options to eliminate the Au cap and decrease the pitch further. A novel part of UCLA’s approach is the use of a silicon wafer as the substrate. This Silicon Interconnect Fabric (Si-IF) provides performance and mechanical advantages, and UCLA is developing system-level approaches for integrating the Si-IF. The interconnect strategy is a critical part of the CHIPS eco-system. Along with the technical capabilities for finepitch interconnect, there also needs to be access to foundries, MPW runs, volume assembly, PDKs, and other critical supply chain capabilities. DARPA is paving the way for some of this, but the eco-system also needs industry support that arises from the market potential of the CHIPS approach. In parallel, business models that fill new needs in the

CHIPS eco-system are being explored. For example, silicon IP companies are pursuing the option of becoming chiplet suppliers. Instead of just providing soft or even hard IP, they will sell verified chiplets ready for assembly. This is one example of the innovation brought by the CHIPS approach to the semiconductor marketplace. Conclusion DARPA’s CHIPS program aims to serve as the necessary piece of the puzzle that lets heterogeneous integration gain momentum in the marketplace by leveraging proven approaches of the semiconductor industry. With advantages for both defense and commercial applications, a critical mass of CHIPS adopters is expected. The industry has recognized the great challenges before us in IEEE’s newly revamped International Roadmap for Devices and Systems [13], and an important step was made when the IEEE, SEMI, and ASME jointly established the Heterogeneous Integration Roadmap[14] in recognition of the importance of het-

18 MEPTEC REPORT WINTER 2018

erogeneous integration to the solution set for these upcoming challenges. In this spirit, DARPA has been at the forefront of heterogeneous integration for many years and is now focused on enabling the traction needed to drive broad adoption via the CHIPS program. ◆

Packaging & Assembly for High-Temperature Electronics

References

Dr. Randall K. Kirschman R&D Consultant for Electronics Technology

[1]

D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “Heterogeneous Integration for Revolutionary Microwave Circuits at DARPA,” Microwave Journal, June 2015, pp. 22-38.

[2]

D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “A Revolution on the Horizon from DARPA,” IEEE Microwave Magazine, March/April 2017, pp. 44-59.

[3]

www.darpa.mil/Our_Work/MTO/Programs/ DAHI/DAHI_Foundry_Technology.asp.

[4]

D. Scott, et al., “Diverse Accessible Heterogeneous Integration (DAHI) Foundry Establishment at Northrop Grumman Aerospace Systems (NGAS),” Proc. IPRM, Santa Barbara, 2015.

[5]

Y.-C. Wu, et al., “InP HBT/GaN HEMT/ Si CMOS Heterogeneous Integrated Q-Band VCO-Amplifier Chain,” Proc. IPRM, Santa Barbara, 2015.

[6]

Andrew Carter et al., “Wafer-Scale InP/Si CMOS 3D Integration Using Low-Temperature Oxide Bonding.” Compound Semiconductor Week, 2015.

[7]

Lawrence J. Kushner et al., “A 30 GS/s, 12-bit, 8-Vpp, Arbitrary Waveform Generator with Integrated 25 fs Clock in the DARPA DAHI Process.” GOMAC 2016.

[8]

D. Green, “DARPA’s CHIPS Program and Making Heterogeneous Integration Common,” 3D ASIP, December 2017.

[9]

D. Green et al., “Heterogeneous Integration at DARPA: Pathfinding and Progress in Assembly Approaches,” ECTC, May 2018.

[10] R. Stevens et al., “An Application Specific IP (ASIP) Approach Offers a Design Solution Between ASICs and FPGA,” 3D ASIP, December 2017. [11] P. Borodulin et al., “Disaggregation of Advanced Node SoCs into 2.5D Modular Architectures for Rapid IP Reuse,” 3D ASIP, December 2017. [12] M. Lueck et al., “High Density Interconnect Bonding at 10µm Pitch and Below Using Non-Collapsible Microbumps,” 3D ASIP, December 2017. [13] “International Roadmap for Devices and Systems,” irds.ieee.org/roadmap-2017. [14] “Heterogeneous Integration Roadmap,” eps.ieee.org/technology/heterogeneousintegration-roadmap.html .

meptec.org

Part I – Devices and Materials

FOR MORE EFFICIENT USE OF resources, and to reduce energy waste and pollution, electronics must be extended into new areas. A key area is operation beyond the present “standard” or “military” temperature range of −55°C to +125°C. Power systems for electric vehicles and airplanes could be more efficient using high-temperature electronics (HTE), capable of operation at environmental temperatures from 200°C to 500°C or beyond.* Closely related is the move toward “distributed systems”: placing more of a system’s electronics close to sensors and actuators to enhance performance (Figure 1). High-temperature electronics is needed because these sensors and actuators are often in high-temperature environments. Additional applications—with an inherent high-temperature environment— include spacecraft, electric-generating plants, and petroleum and geothermal wells[1][2]. For a high-temperature application, operating electronics within the “standard” temperature range exacts a substantial toll in size, weight, power, and system complexity and efficiency. To keep electronics below +125°C, either (a) the electronics must be located in a “standardtemperature” ambient, which is likely remote from where it needs to be for best system performance, or (b) a cooling or refrigeration system, with its associated issues, must be employed. How does electronics extend its operational temperature range upward? Assembly and packaging technology has a major role. It must provide an electroniccomponent-friendly environment—thermal, electrical and mechanical—while not compromising the component’s intrinsic

Figure.1 The idea of a distributed system. (*Aircraft or auto engine, oil well, hot planet, …)

performance. In other words, an extension of the same requirements as for “standard” temperatures [3]. This brief article cannot go into details, but will touch on a few of the major points. Moving to higher temperatures requires assembly and packaging based on (a) materials that can survive and are stable, (b) designs and techniques that prevent interactions among the materials, and (c) processes that are compatible with the materials and electronic components. Extending the thermal, electrical and mechanical design presents an extra challenge because many materials characteristics are strongly temperature dependent, more so as temperature increases. Furthermore, there are nearly always additional environmental stresses to be considered: EMI, magnetic fields, chemicals, dirt, shock/vibration, or radiation. A basic requirement for any electronic system is suitable semiconductor devices (diodes and transistors). Thus, a first question is what are the high-temperature capabilities of semiconductor materials and devices?

Semiconductors Silicon is the mainstay, and a range of Si ICs rated up to ≈ 200–225°C is commercially available (Figure 2); a few can be used to even higher temperatures if derated. Also, SiGe ICs are appearing commercially, rated up to 250°C. Although Si devices have been operated to over 400°C [4], a practical limit for Si is about 300°C for non-power circuits and about 200°C for power circuits. To go beyond the extended-temperature capabilities of Si, the frontrunners are silicon carbide (SiC) [5], gallium nitride (GaN), and diamond (C) [6]. These

Figure 2. Si COTS ICs rated at 175°C (left, V reference) and 210°C (right, 8-ch MUX) (note difference in packaging, plastic vs ceramic). Photos courtesy Analog Devices.

* Unless noted otherwise, all temperatures in this article are environmental/ambient temperatures. meptec.org

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TECH BRIEFS – The State-of-the-Art Technology Briefs contains articles from the Binghamton University S3IP “Flashes.” Binghamton University currently has research thrusts in healthcare/medical electronics; 2.5D/3D packaging; power electronics; cybersecure hw/sw systems; photonics; MEMS; and next generation networks, computers and communications. DR. GAMAL RAFAI-AHMED XILINX

Nicholas Leonardi SMART Microsystems Ltd. Andreas Olofsson DARPA Dr. Gamal Rafai-Ahmed Xilinx

DEPARTMENTS

8 Coupling & Crosstalk 10 Industry Insights

24 SMART Microsystems News 30 Henkel News

34 Opinion

Rich Wawrzyniak Semico

MEPTEC Report Vol. 22, No. 4. Published quarterly by MEPCOM LLC, 315 Savannah River Dr., Summerville, SC 29485. Copyright 2018 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130.


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MEMBER NEWS 

COMPREHENSIVE RE-BRANDING REFLECTS BOSCHMAN’S AMBITIOUS GROWTH PLAN Boschman Advanced Packaging Technology, formerly known as Boschman Group underwent a comprehensive corporate re-branding. The existing entities Advanced Packaging Center and Boschman Technologies have merged into Boschman’s three business activities: Package Development, Assembly Services and Equipment. The re-branding reflects both the growth of the company as well as its vision for the future. The re-branding consisted of: a new corporate brand name, new operational brand names, a new slogan, new marketing material, a new web-site and a new focus for the company. Completing the execution, the company revealed its new name as Boschman Advanced Packaging Technology along with its new slogan: “Smaller, better and lower cost: we realize the best package for your product”. www.boschman.nl

ONCE AGAIN, DELPHON IS ONE OF THE BEST COMPANIES TO WORK FOR IN THE BAY AREA Delphon has announced that it has been named one of the San Francisco Bay Area’s Best and Brightest Companies to work for. Delphon was specifically recognized for creating a diverse, happy, and productive environment for their employees, and consistently looking at new and creative ways to make the employee experience fulfill-

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High Operating Temperature Underfill for Electronics Protection in Aero and Auto High-performance material raises device reliability within challenging environments ANTICIPATING THE requirements for next-generation high-reliability electronics applications, Henkel has developed Loctite Eccobond UF 1173. The protective underfill material, which has been formulated with health and safety top-of-mind, does not contain any reportable REACH SVHCs, is not CMR classified and delivers outstanding performance under high operating temperature environments. Henkel’s new underfill system improves on oldergeneration materials, not only with its prioritization of health and safety, but also from a performance and processing perspective. Loctite Eccobond UF 1173 is a onecomponent underfill that can be jet or needle dispensed,

flows fast in and around tight interspaces and cures quickly to form void-free interconnect protection from shock, drop and vibration. Importantly, the novel underfill exhibits high glass transition (Tg) temperature capability of 155°C and a low coefficient of thermal expan-

sion (CTE) to ensure robust protection performance even under stressful conditions. For more information about Loctite Eccobond UF 1173 or any of the company’s electronic protection materials, visit the Henkel website www.henkel-adhesives.com/ electronics. ◆

World’s First TPM for Cybersecurity in the Connected Car INFINEON TECHNOLOGIES IS ENABLING a crucial step toward greater cybersecurity in the connected car. The Munich-based company is the world’s first semiconductor manufacturer to put a Trusted Platform Module (TPM) specifically for automotive applications on the market. The new OPTIGA™ TPM 2.0 protects communication between the car manufacturer and the car which increasingly turns into a computer on wheels. A number of car manufacturers already designed in Infineon’s OPTIGA TPM. The TPM is a hardware-based security solution that has proven its worth in IT security. By using it, car manufacturers can incorporate sensitive security keys for assigning access rights, authentication and data encryption in the car in a protected way. The TPM can also be updated so that the level of security can be kept up to date throughout the vehicle’s service life. “As a computer on wheels, the connected car benefits from the experience of the IT industry,” said Martin Brunner, expert for automotive security at Infineon. “In the complex interplay between software, network and cloud,

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security hardware creates the solid foundation for secured communication. Backed by Infineon’s many years of expertise in the automotive and security areas, we have optimized the OPTIGA TPM for automotive applications. It is easy to integrate and substantially increases cybersecurity – from production to recycling of connected cars.” The new OPTIGA TPM 2.0 SLI 9670 is available now available and manufactured in security-certified production facilities of Infineon Germany and the Philippines. Further information is available at www.infineon.com/ Auto-TPM. ◆ meptec.org


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MEMBER NEWS

Xilinx Extends Data Center Leadership with New Alveo U280 HBM2 Accelerator Card; Dell EMC First to Qualify Alveo U200 XILINX HAS ANNOUNCED that it is expanding its recently-announced Alveo™ data center accelerator cards portfolio with a new product, the Alveo U280. The Alveo U280 card will offer new features including support for highbandwidth memory (HBM2) and leading edge, high-performance server interconnect. Xilinx also announced that Dell EMC is the first server vendor to qualify its Alveo U200 accelerator card, which will be available from Dell EMC to accelerate key HPC and other workloads with select Dell EMC PowerEdge servers. The Alveo portfolio of powerful accelerator cards is designed to dramatically increase performance in industry-standard servers across cloud and on-premise data centers. “We are pleased to welcome Dell EMC as a go-tomarket partner, and to unveil

the Alveo U280, which is suited for memory-bound applications that can benefit from industry-standard HBM2 and outstanding throughput,” said Manish Muthal, vice president, data center, Xilinx. “The new card is a strong complement to the Alveo portfolio which is seeing tremendous interest from customers and partners.” The new Alveo U280 accelerator card offers eight gigabytes of HBM2 at 460 gigabytes-per-second to provide high-performance, adaptable acceleration for memory-bound, compute

intensive applications including database analytics and machine learning inference. The U280 acceleration card includes PCI Express 4.0 with CCIX support to leverage the latest server interconnect infrastructure for high-bandwidth, low latency, cache coherent shared memory access with upcoming CCIX host processors. All of these features are designed to support today’s demanding HPC environments, as well as other common data center workloads such as financial trading and risk modeling, database acceleration and more. For more information, visit www.xilinx.com. ◆

Students in Huntsville-Madison County, Alabama, Will Participate in FlexFactor Following $250,000 Boeing Grant BOEING HAS AWARDED $250,000 TOWARD a new workforce development initiative in partnership with the Alabama Community College System and NextFlex, America’s Flexible Hybrid Electronics Innovation Institute. The fund will fuel the local adoption of NextFlex’s flagship workforce development program FlexFactor®, aimed at preparing the next generation of the advanced manufacturing workforce. The partnership between NextFlex, Boeing, and participating local school districts and colleges will give Huntsville-Madison County area students the opportunity to see how advanced materials and products can combine to create innovative solutions to a diverse range of problems. The immersive multi-week experience helps participating students kickstart their advanced manufacturing career paths by familiarizing them with the technology and the vast range of professional opportunities in the field. “FlexFactor allows students to grasp their potential to address and solve the biggest chalmeptec.org

lenges of the future using the power of technology, an entrepreneurial mindset, and a range of soft skills like environmental scanning and deduction, contextual value creation and collaboration,” explained Brynt Parmeter, director of Workforce Development at NextFlex. “Students emerge from the program understanding that they are the ones who will come up with the solutions to the vast range of social, environmental and health problems our world faces.” The Boeing-funded Huntsville-Madison County initiative is the second national expansion of the FlexFactor program that piloted in Northern California, following the spring 2018 expansion of the program to Lorain Community College in Elyria, Ohio. The Huntsville-Madison County expansion will build on the successes of the 2,000 students who have already gone through the program, highlighting the astounding capacity of this generation to grasp the power and potential of emerging technologies. Visit www.nextflex.us for more information ◆

ing and exciting. Delphon recognizes that the success of any business starts with its people and strives to create an environment where employees can grow and feel supported. The Best and Brightest Companies to Work For® competition identifies and honors organizations that display a commitment to excellence in their human resource practices and employee enrichment. www.delphon.com

PEELABLE THERMAL INTERFACE MATERIAL (TIM) FROM HENKEL GETS INDUSTRY PRIZE Notching its second notable industry prize, Henkel’s Bergquist Gap Filler TGF 1500RW liquid thermal interface material recently took top honors in the Global Technology Awards’ adhesives/coatings/encapsulants/TIMs category. The award contest, which is sponsored by Global SMT and Packaging magazine, recognizes the best new innovations in the electronics assembly and packaging industries. Henkel Business Development Director, Dr. Mark Currie, accepted the prize during a special ceremony at last month’s Surface Mount Technology International conference. The latest in a series of thermal material breakthroughs from Henkel, Bergquist Gap Filler TGF 1500RW is a one-part, cure-in-place liquid gap filler that provides multiple advantages for high-volume, high-value assemblies. As a liquid material, the new TIM is well-suited for filling the gaps within challenging and complex architectures. www.henkel-adhesives.com

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MEMBER NEWS

 INFINEON ACQUIRES

NASA Low Outgassing Rated UV Curing Adhesive with High Glass Transition Temperature

Infineon Technologies AG has acquired Siltectra GmbH, a start-up based in Dresden. The start-up has developed an innovative technology (Cold Split) to process crystal material efficiently and with minimal loss of material. Infineon will use the Cold Split technology to split silicon carbide (SiC) wafers, thus doubling the number of chips out of one wafer. A purchase price of 124 million Euros was agreed on with the venture capital investor MIG Fonds, the main shareholder. “This acquisition will help us expand our excellent portfolio with the new material silicon carbide as well. Our system understanding and our unique know how on thin wafer technology will be ideally complemented by the Cold Split technology and the innovative capacity of Siltectra,” said Dr. Reinhard Ploss, CEO of Infineon.

MASTER BOND UV26 IS A new one part UV curable system featuring an exceptionally high glass transition temperature (Tg) ranging from 160 to 170°C. This NASA low outgassing certified compound also offers strong adhesion to a wide variety of substrates such as glass, surface treated metals and many plastics. As a coating and adhesive it is also capable of withstanding harsh chemicals including acids, bases, fuels and many aggressive solvents. This low viscosity compound (250-1,500 cps at 75°F) cures rapidly upon exposure to a UV light source at a wavelength of 320-365 nm with an energy output as low as 20-40 milliwatts per cm2. With a refractive index of 1.55 at room temperature, this system features outstanding optical clarity. UV26 offers robust physical strength properties upon curing and is ideal for high performance bonding and coating applications. It features low shrinkage upon

SILTECTRA, SILICON CARBIDE SPECIALIST

www.infineon.com

DISTINGUISHED INDUSTRY EXECUTIVE DR. LEE CHOON HEUNG APPOINTED JCET GROUP CEO STATS ChipPAC Pte. Ltd. has announced that the Board of Directors of its holding company, Jiangsu Changjiang Electronics Technology Co., Ltd (‘JCET’) has appointed Dr. Lee Choon Heung as Chief Executive Officer (‘CEO’) for JCET Group, as well as Chief Executive Officer and Chairman for STATS ChipPAC. Dr. Lee brings to JCET a wealth of expertise and veteran leadership with 20 years of extensive

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curing and serviceability from -60°F to +500°F [-51°C to +260°C]. Master Bond UV26 is 100% solids, does not contain any solvents or volatiles and is not oxygen inhibited. It is available for purchase in 10 cc and 30 cc syringes, 1/2 pint and 1 pint containers. The shelf life at 75°F is 6 months in the original unopened containers. Master Bond UV26 offers the convenience of a no mix system and rapidly cures upon exposure to a UV light

source. It features low outgassing properties and excellent chemical resistance while maintaining superb physical strength, even upon exposure to high temperatures. Read more about Master Bond’s high glass transition temperature formulations at https://www.masterbond.com/ properties/epoxy-adhesivesystems-high-glass-transitiontemperature or contact Tech Support. Phone: +1-201-3438983 Fax: +1-201-343-2132 Email: technical@masterbond.com. ◆

SEMI Unveils Industry’s First Power and Compound Fab Outlook SEMI HAS ANNOUNCED THE INDUSTRY’S first worldwide fab data for power and compound semiconductors. The new report, Power and Compound Fab Outlook, provides comprehensive front-end semiconductor fab information and a forecast to 2022 for global manufacturing capabilities of power and compound semiconductors. Power devices are rising in importance as energy-efficiency standards tighten to meet growing demand for power-thrifty high-end consumer electronics, wireless communications, electric vehicles, green energy, data centers, and both industrial and consumer IoT (Internet of Things) applications. Semiconductor fabs around the globe have responded with improvements to power usage in every aspect of electronics including power harvesting, delivery, transformation, storage, and consumption. Cost structure and performance are critical in power electronics, dictating the pace

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of market growth and technology adoption. With compound materials driving significant gains in the energy efficiency of power devices, the Power and Compound Fab Outlook highlights particular compound materials that have been adopted in semiconductor fabs. The report is an essential business tool for anyone interested in related tool and material markets as well as power and compound materials capacity in fabs by region and wafer sizes. For more information, visit www.semi.org and follow SEMI on LinkedIn and Twitter. ◆ meptec.org


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MEMBER NEWS

Amkor Offers Optical Package Solutions for Multiple Applications AMKOR TECHNOLOGY, INC. HAS announced the extension of its MEMS and Sensor package platforms to address the growing optical market. The new optical package platforms are derivatives of their successful ChipArray® BGA and MicroLeadFrame® product families and can be used for many applications, including LIDAR, fingerprint sensing, ambient light sensing and 3D facial recognition. “Amkor has over 25 years of experience manufacturing and testing MEMS and Sensor devices for automotive, communications and consumer applications,” said John Donaghey, Corporate Vice President, Amkor Technology.

“We are excited to extend our high-volume MEMS and Sensor package platforms to address optical market requirements. This allows our customers to bring their solutions to market quickly without sacrificing performance.” Amkor’s factories are IATF16949 certified and have the ability to meet the rigorous requirements of the AEC-Q100 specification. Full turnkey optical MEMS and Sensor solutions from Amkor include design, assembly and test. To learn more about Amkor’s capabilities in Optical MEMS and Sensor packaging, visit www.amkor.com/technology/optical-sensors/. ◆

SonoLab™ Welcomes DAGE X-ray Tool TO RELIABLY DETECT, image and analyze defects in electronic components and similar items, it makes sense to employ multiple nondestructive tools and methods. As part of Nordson’s recent acquisition of Sonoscan, a Nordson DAGE X-ray tool was recently added to the C-SAM® acoustic micro imaging tools at Nordson SONOSCAN. Customers bring their tough problems to the SonoLab. Are these flip chip and BGA bumps intact and properly bonded? Are there voids in the underfill? Why do the die in these IGBT modules keep cracking and failing? Ultrasound penetrates most production materials, including dense metals, but not air or porous materials. X-ray penetrates air and porous materials in addition to most production materials, but may not penetrate some dense metal layers. X-ray images are created by transmitting X-rays through the sample and detecting the shadow image it casts. Higher density materials such as solder cast a darker shadow while lower density regions such as voids meptec.org

semiconductor packaging and test experience. Dr. Lee served in several senior management positions at Amkor Technology Inc. including head of their R&D centre, head of global procurement, group vice president, senior vice president and Chief Technology Officer. Dr. Lee, holds a Ph.D. in Theoretical Solid State Physics from Case Western Reserve University, currently holds 59 industry patents, and has published 19 academic papers around the world. The JCET Board of Directors and the management team also expressed their utmost gratitude and appreciation to Dr. Han Byung Joon and Mr. Lai Chih-Ming for their outstanding leadership and valuable contributions during their tenure at STATS ChipPAC. www.statschippac.com

NORDSON RECEIVES OUTSTANDING PHILANTHROPIC BUSINESS AWARD

cast a lighter shadow, making it easy to see features such as voiding. Scattering of X-rays is typically not observed. Ultrasound is partly reflected and partly transmitted at interfaces between most materials, but is almost entirely reflected by the airto-solid interface at voids and other gaps, and there is no transmission, even if the void or gap is only a fraction of a micron thick. This property of ultrasound makes imaging thin delaminations easy, even in samples containing dense metals. The wires in devices scatter ultrasound and make imaging difficult, but X-ray’s higher resolution brings out

the details. The ability to move samples between the two side-by-side and complementary nondestructive tools has already demonstrated superior results for SonoLab customers. Nordson SONOSCAN is complemented by our Nordson DAGE, Nordson YESTECH and Nordson MATRIX divisions. Together, we offer a full suite of test and inspection products and solutions to customers in the electronics assembly and semiconductor industries. Visit SONOSCAN at www.nordsonsonoscan.com for more information. ◆

Nordson Corporation announces that it received the Outstanding Philanthropic Business/Corporation Award from the Association of Fundraising Professionals (AFP) San Diego Chapter. The award honors the dedication, leadership, and community contributions of San Diego County’s philanthropists, volunteers, professionals, and organizations. Nordson was nominated by six of the non-profit organizations it supports in the San Diego area: Girl Scouts San Diego, Casa de Amparo, Interfaith Community Services, North County Philanthropy Council, MiraCosta College, and Carlsbad Educational Foundation. www.nordson.com

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COUPLING & CROSSTALK By Ira Feldman Electronic coupling is the transfer of energy from one circuit or medium to another. Sometimes it is intentional and sometimes not (crosstalk). I hope that this column, by mixing technology and general observations, is thought-provoking and “couples” with your thinking. Most of the time I will stick to technology but occasional crosstalk diversions may deliver a message closer to home.

Knowledge Worker or Knowledge Serf?  “I WANT TO CHAT WITH YOU

but first I need a few moments to finish a computer task I’m working on. Rats! Why doesn’t it work? Hmm, the last time I did this was a year ago. Nothing seems the same, I first must untangle my brain from what appears to be non-standard logic and useless updates.” Have you tried to figure out how you did something last time by attempting to recreate your steps? You know exactly what you want to do, however you no longer remember exactly how. Or worse, you’ve made notes of the steps but the software or system has changed so you need to figure it out again. This happens regularly with TurboTax which I rarely use except during tax season, I either forget to make necessary adjustments, or worse, how to make them. And the built-In “guidance” system isn’t terribly helpful. The same goes with some of the more specialized commands in common programs like Microsoft Office or Adobe Photoshop. You most often use a small set of functions so things “just work”. But the moment you start trying to use the more complex functions, unless you use them regularly, you need to figure it out all over again. Pivot tables anyone? Level adjustment curves? And don’t get me started on the foibles of “specialized” software like QuickBooks where I’ve learned far more about how it works than actual accounting. When I get done with some daunting task I often wonder if I’m a skilled analyst or just a slave to a system. In 1959, Peter Drucker coined the 8 MEPTEC REPORT

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term “Knowledge Worker” to describe occupations that are distinct from manual labor, the value comes out of the application of knowledge and problem solving. “Office work” is knowledge work but performed at differing levels of value. Clearly when professionals such as engineers, programmers, architects, lawyers, and physicians are actually adding value that is “highest value knowledge work”. And clerical tasks can be knowledge work, albeit of lower value, when they require judgment and knowledge to complete appropriately. The issue is that sometimes professionals are forced to spend more time in low to no value activity than in actual knowledge work. Once the diagnosis is made and the course of treatment set, a doctor entering the data for a prescription by a physician is simply clerical effort. Worse would be a doctor sorting out an insurance issue that is a necessary but non-value added activity.

With the frequent shortage of qualified talent and with the ability to scale, automated solutions are the direction of the future. As a professional what are your choices when faced with a low value and often repetitive task? Do it yourself (DIY), delegate, automate, or choose to not do it. Avoiding or deferring indefinitely is effectively choosing not to do it. A clear ‘no’ is better since there is a conscious decision that can be communicated. Human nature does not like saying, or hearing, no but it is a skill all professionals should develop. This can help for some things, but not everything can be declined - for example taxes. DIY unfortunately is the most common solution for many professionals especially when they want it done right. Or when the other options are too painful or impractical. I don’t like doing my personal taxes but I’ve found it is far easier to get them done correctly the first time rather than having my accountant “help me”. He would simply ask me for all the

data like TurboTax does and I’d still have to review and consider my options. Successful delegation of a task requires both a resource that you trust to do it correctly and a clear definition of what needs to be done. Anything else is a recipe for potential disaster. Having a resource available is obvious but without complete trust, you’ll be following up, checking the process, or the results. And the definition needs to be precise and complete. Unlike personal taxes, the complexity of my business taxes and the “black and white” availability of the data via the aforementioned QuickBooks, permits me to entrust the entire process to a specialist: my accountant – a trusted, skilled knowledge worker! Delegation can be an informal or a formal process. It runs from casually asking someone to lend a hand to making a detailed request of someone whose job it is to run a process. Even when it is someone’s full time job, the results will vary if the trust and definition aren’t complete. Humans can be good but not perfect in terms of repeatability and consistency. I’ve written plenty of International Standards Organization (ISO) 9000 and 13485 procedures for general manufacturing and medical devices that were later discovered to not being followed consistently. Management must commit to each critical step or specification being checked multiple times by different people and processes. Otherwise, problems could slip through. And preparation for the required ISO audits are always extensive and can include a lot of re-training and manual “cleanup”. Why? People are not machines. So let us automate it! The great news is once it is automated it will be repeatable and the solution should scale. Unfortunately, this is not as easy or straightforward as it should be due to intertwined cost and implementation issues. The challenge is how to implement the right tools that capture or ‘encode’ the processes and make them efficient. The ideal situation is to build on your own professional experience and judgment with the expertise and guidance of a consultant who understands the specific needs of your industry plus the advantages and limitations of existing software. Even when there may be focused solutions for a specific industry, they may be too costly or require the business to change its own processes to conform to the software. At one startup meptec.org


I assisted in a close look at a configuration management / document control system. Though the software licenses were reasonably priced, we did not have the full-time person required to run and customize the system. At another company, executive management decided we should implement a very well-known customer relationship manager (CRM) platform. The effort to transition our existing solutions to this tool were overwhelming. And the cost of customization far exceeded the budget, so it was never properly configured to be really useful to the organization. As a result, it was never truly adopted by the team. In general, implementing tools for professionals and smaller organization is problematic. For example, Business Process Automation (BPA) software is designed to automate business processes and day to day activities. However, it is currently an immature field with no clear winners. What professionals and small businesses need are tools that have the ease of use of Microsoft Office along with a significant user base and open data standards. Unfortunately, the current trend

towards cloud-based applications that are “walled gardens” is not promising. Yes, the user or their company is freed from managing the application and they gain pervasive access. However, companies end up at the mercy of the supplier since updates including changes in functionality are forced by the supplier. It is very rare for a web application to ask the user which version they wish to run. Sometimes key functionality is removed without notice. And with limited data access and no data standards, the user may find it difficult if not impossible to transfer to a different solution should the need arise. So the quandary that needs to be solved is how do professionals lead organizations that build and maintain sustainable processes? There needs to be a mix of resources available to trust with delegated tasks and automated solutions. With the frequent shortage of qualified talent and with the ability to scale, automated solutions are the direction of the future. Professionals will need to pick their battles and select where to wisely invest in information technology and automation. Due to the expertise required, the professionals themselves

and trusted consultants will be required to implement these automated solutions. The right automation tools are required to scale a business and enable people to deliver consistent products and services. Without these the professional will become little more than a knowledge serf! For more of my thoughts, please see my blog http://hightechbizdev.com. As always, I look forward to hearing your comments directly. Please contact me to discuss your thoughts or if I can be of any assistance. ◆ IRA FELDMAN is the Principal Consultant of Feldman Engineering Corp. which guides high technology products and services from concept to high volume manufacturing. He engages on a wide range of projects including technical marketing, product-generation processes, supplychain management, and business development. (ira@feldmanengineering.com)

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INDUSTRY INSIGHTS By Ron Jones

What Does “Responsible Brands” Compliance Mean?  IF YOU ASK 10 PEOPLE FOR THEIR definition of Corporate Social Responsibility (CSR), you will likely get 10 different answers on what should be included and what should not. The same is true with the term Sustainability. Some see Sustainability as only environmental while others include things like long term financial viability and employee availability. Multiple surveys have shown that a majority of people would prefer to buy from a company that operates in a responsible manner. However, it is impossible for the average consumer to understand all the potential factors that go into responsible operations and material sourcing, and companies with large advertising budgets might leave false impressions. The primary goal of Responsible Brands Initiative (RBI) is to enable consumers to have ready access to an uncomplicated and objective assessment of a company’s CSR and sustainability performance and an easy way to consider that performance when making their buying decision. The planned approach uses a wide variety of individual factors that are weighted in a structured way to come up with an overall performance score. The weighting also comprehends the differences between industries on some factors such as manufacturing for an automobile company vs. a financial institution. RBI is working with experts in a variety of industries and roles, and we encourage you to consider participating. Our goal is to be comprehensive in scope while involving experts and collaborating towards the final scoring system. Once complete and in use, we expect that a company’s RBI performance score will have an impact on people, organizations and the environment. Over a dozen stakeholder audiences are being considered, for example employees, customers, government, suppliers, creditors, community, owners and investors and the envi10 MEPTEC REPORT

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ronment. Experts from these sectors will decide the weighting based on the impact of specific criteria to the group. We plan to incorporate recognized third party data into the weighting when possible to raise credibility and reduce effort. So far, criteria for Responsible Brand™ compliance includes: • metrics that are practical, objective, demonstrable and significant. • metrics that are required by law and others that are not. • metrics that encompass most tenets of Corporate Social Responsibility and Sustainability. • a rubric that weights various aspects of CSR into a balanced and meaningful overall view. • no requirement that a company be perfect to be in compliance. • no factors that preclude a company from being in compliance. • no criteria that are political or personal in nature • criteria that reflects support for the spirit of responsible sourcing and efforts that go above and beyond minimum requirements. • inertia and persistence of compliance that is minimally impacted by current events. • recognition for achieving Responsible Brands compliance and use of RBI Compliant logo • openness on the details of the compliance scorecard. • a focus on corporate CSR environment, policies and actions, not individual products or services. We need your help, now. The definition of a responsible company, based on specific criteria, and eventually the program to recognize Responsible Brands compliance requires involving myriad people and entities. Topic experts are needed for working groups to define compliance requirements, branding elements, and promotion programs to activate consumers. As you make plans for implementing programs to meet CSR objectives for your company, consider investing resources in Responsible Brands Initiative. This is a simple way to increase the impact of what may already be in your annual budget. By supporting RBI, your company will gain additional recognition and credibility with the growing audience who favor products which are produced in a responsible manner. More information about how you can help is available on our website. Please visit http://responsiblebrands.org ◆ meptec.org


THE BODY ELECTRIC

2019 MEDICAL ELECTRONICS SYMPOSIUM The John A. Spitzer Conference Center at Lorain County Community College in Elyria, Ohio

T

he human body is an extremely complex “electrical (neurological) system”, with companies continuing their quest to understand and improve capability as related to neural interface, basically connecting the human body directly into computers! There is no question, capabilities in smart phone/watch technologies connected to the internet erases any doubt of the potential to connect people to computers. With the brain being the human equivalent of the “MicroProcessor”, semiconductor companies such as IBM, Intel, MicroChip and MicroSemi have been well aware of potential for connectivity. Others have taken knowledge of neural interface to help humans manage their internal electrical systems, including Medtronic, Philips and Abbott, with a range of pacemakers, defibrillators and neural therapies. Expanding the potential scope of linking the brain to computers and to the internet has attracted the likes of Amazon, Apple, Facebook, Google, MicroSoft, Neuralink and others, adding to the list that already includes J&J, G.E., T.I., Stryker, and Edwards. MicroProcessors and other ASIC Chips, coupled with MEMS and Sensors, are now seen as the “nextbig-thing” over the next 5 years looking at the Internet-of-Things (IoT). This event will bring together experts to cover topics such as:  Forecasting and Analytics  MEMS, Sensors and Integrated Circuits  Implantable Devices and Neural Interface  Medical Robotics, Equipment, and Prosthetics  Packaging and Board Level Assembly  Advanced Materials and Reliability For more information about event attendance, sponsorships, or exhibiting, please email bcooper@meptec.org with the subject line “The Body Electric”. Presented by

Special SMART Microsystems Facility Tour Planned for Wednesday, May 22nd

VISIT SMTA.ORG/MEDICAL FOR MORE INFORMATION


ANALYSIS

Impact of Rising Design Costs on SoC Design Starts Rich Wawrzyniak Principal Analyst: ASIC & SoC, Semico

THE RISE IN SILICON AND software design costs has impacted and influenced design activity in the semiconductor industry and is shaping company strategies and the decisions designers are making as it relates to number and type of designs. While it is true that SoCs with the highest design costs probably contain the most complexity, it does not necessarily follow that every product in a given geometry must also incur the same high costs to be competitive. Silicon designers and system architects are constantly looking for ways to reduce their design costs and still meet market requirements and ASP targets. This article references data and analysis from Semico’s report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, SC103-18. Design Complexity Levels Within each process geometry, there are differing levels of effort that directly relate to how expensive a particular design start is. These complexity levels are driven by several factors: • Gate count • Transistor budget • Architecture • Compute resources • Communications channels • Number and type of IP blocks • Feature sets and functionality dictated by market requirements • Software complexity 12 MEPTEC REPORT

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Advanced Performance Multicore SoC 1st Time Design Starts by Design Effort

* Forecast

While software is not included in Semico’s analysis as a direct design cost, it does have a significant impact on the overall silicon architecture created to run that software. One of the major reasons for increasing design cost is the complexity of the software intended to run on the silicon and the architecture necessary to run these software applications efficiently and with good performance. As the software applications have become more feature rich, the silicon must also adapt to accommodate this rising complexity and the increase in the number of lines of code being run. With these thoughts in mind, the costs for each type of SoC are subdivided into different levels of effort to reflect that not all designs must function at the highest possible performance or functionality to be competitive in the market. Semico analyzes design activity based on a variety of different market segments and has created a model to gauge the impact of rising design costs on SoC design starts. Following is a review of the three categories of SoCs: Advanced Performance

Source: Semico Research Corp.

Multicore SoC, Value Multicore SoC and Basic SoC. The Advanced Performance Multicore SoC design starts represent the most complex and expensive designs at the beginning of each process node. Over the forecast period, the average silicon design cost for an Advanced Performance Multicore SoC will increase as designs become more complex and the effort to accomplish them increases. Silicon design costs for a first-time Advanced Performance Multicore SoC at the 7nm node are projected to be 23% higher than at the 10nm node. The increase in cost hasn’t prevented the released of new designs because there are a range of design costs which indicate differing levels of effort and complexity. A higher complexity part would require more tools, more IP, more people to complete and would take longer to accomplish than would a part with less complexity. As the number of design starts transition from older nodes to newer nodes, with their higher associated costs, the meptec.org


Basic SoC 1st Time Design Starts by Design Effort

* Forecast

average design cost for all Advanced Performance Multicore SoCs increases over the forecast period. However, since activity continues at the older nodes, the average design cost is not increasing as fast as the overall silicon design costs for this type of SoC at the most advanced nodes. The CAGR for average design costs for an Advanced Performance Multicore SoC is 2.5% for the period 2017 – 2023. The number of Value Multicore SoC design starts is almost double compared to the Advanced Performance Multicore SoC design starts. This is due to the fact that the Value designs are easier to accomplish, cost less and take less time to finish. This can give an advantage to companies that do not need to offer the most complex solution to their customers yet want to participate in their market with acceptable solutions that meet market requirements. The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017. Over the forecast period, the average silicon design cost for a Value Multicore SoC will increase meptec.org

Source: Semico Research Corp.

as designs become more complex and the effort to accomplish them increases. The fastest growing category as it relates to new designs is the Basic SoC. Basic SoC designs represent the least complex and least expensive efforts at the beginning of each process node. These design costs continue to decline over time as more designs are created, more expertise is gained, the costs of EDA tools decline over time and the reuse of IP increases. Removing derivative designs and respins shows that the number of 1st time efforts for Basic SoCs is growing the fastest of the three SoC types with a CAGR of 12.0% over the forecast period. An interesting note to the Basic SoC category is that many of these designs will be targeted at Internet of Things (IoT) applications. Semico believes that there will be a segment of these applications that will require higher functionality and will be a candidate for 28nm solutions over time. The total number of designs at 28nm starts out small but increases over time. These designs

will cost more and are responsible for the increase in average costs starting in 2014. Thereafter, these costs still increase but at a slower rate. This is also the reason for the large number of Basic SoC designs and the higher CAGR for these designs. They are coming from a relatively small base starting in 2008, but ramp quickly driven by IoT demand for lower cost solutions and reasonable functionality. Unlike Advanced Performance Multicore and Value Multicore SoCs, Basic SoCs see lower amounts of design activity below 28nm over the forecast period. Currently, this is due to the end applications for which Basic SoCs are used. These applications do not need the same complexity levels as the other two types of SoC. This will especially be true for Basic SoCs aimed at IoT solutions. These parts simply don’t need high complexity and their design costs are correspondingly lower, leading to a lower average design cost overall. In general, Semico believes that although design costs for complex SoCs have increased, and that re-spins and long design cycle times are not optimum conditions for the SoC market, their effect on market growth has not been overly detrimental. New, more efficient tool sets from EDA companies and semiconductor intellectual property blocks from 3rd party IP companies, make designers more productive and are well received by the market. Companies with innovative solutions are targeting the appropriate market application and are the main reason why design starts continue to grow. For more information on SoC design costs and SoC design starts by market application, contact Rick Vogelei at rickv@semico.com. ◆

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Connect with the leaders in Semiconductors, MEMS, Sensors, Flexible Electronics, Packaging, Advanced Materials, 3D, and Design and Manufacturing. SEMI gathers the global electronics manufacturing supply chain in large, medium and intimate events. Join our expositions or conferences and take your business to the next level.

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INDUSTRY STRATEGY SYMPOSIUM

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ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE

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INTERNATIONAL TRADE PARTNERS CONFERENCE

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INTEGRATION

DARPA’s CHIPS Program for IP Reuse and Heterogeneous Integration Jeffrey Demmin, Booz Allen Hamilton, Arlington, VA and Andreas Olofsson, Defense Advanced Research Projects Agency (DARPA)

Heterogeneous Integration at DARPA The DARPA Microsystems Technology Office (MTO) has driven the development of revolutionary materials, devices, and integration techniques to meet the performance requirements for the most advanced electronic systems [1, 2]. Recently, the Diverse Accessible Heterogeneous Integration (DAHI) program developed heterogeneous integration processes to combine advanced CS devices and other devices with high-density silicon CMOS in a foundry setting [3-7]. This work demonstrated the benefits of heterogeneous integration in defense applications while solving fundamental technical issues to set the stage for further progress. Now, DARPA is working to extend mainstream semiconductor design infrastructure for rapid and cost-effective integration of heterogeneous device technologies. This represents a significant step past the monolithic silicon approach that has stalled in the face of prohibitive cost and design issues at leading-edge nodes. The path to higher performance requires a broader set of feasible device technology options. DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program will address these challenges by developing interface standards, IP reuse methodologies, and modular design approaches with the goal of making heterogeneous integration as straightforward as printed circuit board design and assembly, without compromising device performance [8, 9]. The CHIPS Approach To enable the vision of seamless integration of diverse device technologies, interface standards are needed to foster a CHIPS eco-system. The CHIPS methodology will be adopted only if design-

Table I. CHIPS Program Metrics.

ers throughout the industry can design chiplets to a known interface standard. (Additionally, the existence of a CHIPS standard will be a self-reinforcing scenario – the use of the standard by chip designers will broaden its utility, thus encouraging more designers to make use of it.) While there are numerous parallel and serial interface standards in the industry, they are typically for specific functions, such as the High Bandwidth Memory (HBM) DRAM standard codified in JEDEC’s JESD235A standard. The CHIPS program is driving convergence on an interface standard that will

likely leverage existing standards but is also tailored for the specific technical requirements of connecting chiplets in applications that can benefit the most from modularization. The CHIPS program metrics are summarized in Table I. The second pillar of the CHIPS approach is IP reuse. To save time and money – measured in years and millions of dollars – it is typical in monolithic chip design to reuse verified IP blocks for common functions. For heterogeneous systems, though, this IP infrastructure is lacking because of the increasingly complex challenges when multiple

Distribution Statement “A” (Approved for Public Release, Distribution Unlimited) meptec.org

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INTEGRATION technologies are integrated. With a standard CHIPS interface for heterogeneous integration, IP reuse is enabled at the chiplet level. Heterogeneous design will become essentially the same as monolithic design, with the knowledge that IP blocks can be integrated successfully. Finally, a modular design paradigm is needed to enable designers to take full advantage of interface standards and heterogeneous IP reuse. Design tools and process design kits (PDKs) will account for different device technologies and their integration, with the appropriate design, simulation, and analysis capabilities in place. CHIPS Program Structure The CHIPS program is structured in two Technical Areas (TAs) – Modular Digital Systems (TA1) and Supporting Technologies (TA3). System performers are Intel, Lockheed Martin, Northrop Grumman, and the University of Michigan. Each of the System performers is designing a system using the CHIPS approach, and the teams are also collaborating to specify and implement an interface standard. Since convergence on the interface standard is required before designs can be finalized, this was the first major milestone in the CHIPS program. The Supporting Technologies performers are providing IP blocks and design tools that will be used by the system designers, although the IP blocks and design tools will be developed with broader usage in mind. Performers developing design tools are Georgia Tech and Cadence, while IP blocks are being developed by Intrinsix, Jariet Technologies, Micron Technology, North Carolina State University, and Synopsys. The system designers will also be providing IP blocks. To ensure successful integration, the CHIPS program is also pursuing multiple integration strategies. The first will be a leading edge but broadly available industry standard interconnect on a silicon interposer, while at least one other approach with much finer pitch will be developed in parallel for Phase 2 of the four-year program. CHIPS Interface Standard The performers in the CHIPS program have agreed to base the CHIPS 16 MEPTEC REPORT

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Figure 1. The basic AIB I/O cell (left) and clock forwarding architecture (right). (Source: Intel)

interface standard on Intel’s Advanced Interface Bus (AIB) standard. This was enabled by Intel offering a paid-up, royalty-free license for the relevant IP and documentation. After extensive discussion and debate among the CHIPS performers, AIB was chosen as the basis for the CHIPS interface. The key factors in that decision were: 1) performance metrics that meet the CHIPS requirements, 2) the flexibility to meet a range of applications, with CHIPS-specific “lite” and “turbo” options, for example, and 3) silicon-proven maturity based on Intel’s use of AIB. The I/O cell and details of the clock forwarding architecture are shown in Figure 1. Chiplets, IP Reuse, and Design The success of the CHIPS program depends on creating a set of IP blocks with numerous applications, since a key

Table II. Chiplets in Process for CHIPS Phase 1 or Proposed for Phase 2.

part of the CHIPS premise is reuse of common IP blocks. The CHIPS program has selected several performers to provide IP blocks for the program, whether for their own system demonstrations or for use by others in the program. Chiplets currently being designed and manufactured in Phase 1 and those under consideration for Phase 2 are summarized in Table II. The chiplet sizes range from approximately 0.5mm2 to 15mm2, with most being 1-4mm2. Plans for chiplet fabrication include leveraging multi-project wafer (MPW) runs at GlobalFoundries (14nm, 32nm, and 65nm) and TSMC (16nm node via DARPA’s CRAFT program). Design tools for a vertically-integrated design flow for IP reuse and heterogeneous integration are under development by Georgia Tech. That team’s tasks include protocol implementation, analysis of chiplet options, interposer routing analysis, and power delivery network analysis. A sample analysis indicates a 33% reduction in power with an integrated voltage regulator chiplet, and the voltage response in that scenario is shown in Figure 2. Cadence Design Systems is contributing to the CHIPS design environment by creating models of different interconnect schemes and verifying them with measurements performed by NIST. Their studies are covering organic and silicon interposer options. Modular Design and Applications The pieces of the CHIPS program are being brought together in a phased sequence of demonstrations: interface functionality (Phase 1), modular systems (Phase 2), and rapid modular system meptec.org


upgrade (Phase 3). A number of teams are developing systems with the CHIPS approach. Intel is developing a platform based on its Stratix-10 FPGA (Figure 3), which enables a wide range of applications, including those that leverage machine learning. The CHIPS interface based on Intel’s AIB is used to connect the FPGA to various chiplets (e.g., data converters, ASICs, processors, and analog functions), and memory can be integrated with other standard interfaces. The CHIPS team at the University of Michigan has made rapid progress with its first set of chiplets being taped out in April 2018 for a 16nm MPW run at TSMC via DARPA’s CRAFT (Circuit Realization at Faster Timescales) program. This includes a deep neural network (DNN) accelerator and neuro-coding chiplets for visual processing applications, as well as the first CHIPS instantiation of the AIB-based interface (Figure 4). Lockheed Martin Advanced Technology Laboratories has proposed an application that addresses a spectrum of common DoD challenges [10]. Along with the inherent cost reduction of decreasing the total design and manufacturing effort required for system upgrades, the CHIPS approach improves reliability, qualification cost and time, and diminishing manufacturing sources (DMS) challenges. With a modular electronics sub-system based on IP reuse and standard interfaces, it is possible to swap in just the components that need an upgrade, thus preventing a total overhaul of the system to retain leadingedge performance. This is particularly critical for applications with life cycles measured in decades, such as aircraft. Lockheed is pursuing this approach in a network interface unit in a major avionics platform. Northrop Grumman Mission Systems (NGMS) is also pursuing CHIPS-based systems for defense applications and has identified digital transceivers as an application that could benefit from a chipletbased approach. By separating the SoC into separate functions, it is possible to optimize the device node and even the foundry source [11]. For this application, a key enabling technology for SoC disaggregation is sub-10µm interconnect pitch, and NGMS is working with Micross to develop this. meptec.org

Core chiplet IVR chiplet

Passive chiplet

IVR

L, C

LDO

0.8

interposer

0.4

package

0.2 0

PCB Interposer VR

Droop

0.6

DC drop

VOUT

Settling time

IL

ΔIL 1.9

1.95

2

2.05

2.1

2.15

Time (µs)

2.2

2.25

2.3

2.35

Figure 2. Georgia Tech’s design tools enable analysis of chiplet integrated voltage regulator performance, among many other features. (Source: Georgia Tech)

Figure 3. Intel’s CHIPS application platform is based on its Stratix-10 FPGA. (Source: Intel)

Figure 4. Michigan’s initial set of chiplets were taped out in April 2018 for a 16nm CMOS MPW foundry run and included an AIB test chip. (Source: U. of Michigan)

Manufacturing and Supply Chain Early in the CHIPS program, the performers settled on 55µm Cu pillar interconnect as the primary path, since this represents the finest pitch interconnect that has an established supply chain and user base. As the first step in the CHIPS program, it is a convenient compromise using leadingedge but broadly available technology.

In parallel, two CHIPS teams are developing alternative interconnect approaches with much finer pitch interconnect to extend the CHIPS roadmap well into the future. Micross and NGMS are collaborating on ultra-fine-pitch interconnect, which NGMS has shown to be a critical enabler for their target applications. Micross has demonstrated both Cu WINTER 2018 MEPTEC REPORT 17


INTEGRATION erogeneous integration to the solution set for these upcoming challenges. In this spirit, DARPA has been at the forefront of heterogeneous integration for many years and is now focused on enabling the traction needed to drive broad adoption via the CHIPS program. ◆ References

Figure 5. Micross has demonstrated bonding on test structures at 5µm Cu/Cu pitch (left) and 10µm Au/Au pitch (right). (Source: Micross)

[1]

D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “Heterogeneous Integration for Revolutionary Microwave Circuits at DARPA,” Microwave Journal, June 2015, pp. 22-38.

[2]

D. Green, C. Dohrmann, J. Demmin, Y. Zheng, T.-H. Chang, “A Revolution on the Horizon from DARPA,” IEEE Microwave Magazine, March/April 2017, pp. 44-59.

[3] www.darpa.mil/Our_Work/MTO/Programs/ DAHI/DAHI_Foundry_Technology.asp. [4]

Figure 6. UCLA is developing an interconnect scheme that leverages silicon wafers as the substrate (left) with 10µm and below pitch Cu interconnections. (Source: UCLA)

and Au metallurgies for 10µm and below pitch (Figure 5) with non-collapsible bumps [12]. A team at UCLA is also developing sub-10µm interconnect for CHIPS. They have demonstrated Au-capped Cu pillar interconnect at 10µm pitch (Figure 6) and have roadmap options to eliminate the Au cap and decrease the pitch further. A novel part of UCLA’s approach is the use of a silicon wafer as the substrate. This Silicon Interconnect Fabric (Si-IF) provides performance and mechanical advantages, and UCLA is developing system-level approaches for integrating the Si-IF. The interconnect strategy is a critical part of the CHIPS eco-system. Along with the technical capabilities for finepitch interconnect, there also needs to be access to foundries, MPW runs, volume assembly, PDKs, and other critical supply chain capabilities. DARPA is paving the way for some of this, but the eco-system also needs industry support that arises from the market potential of the CHIPS approach. In parallel, business models that fill new needs in the 18 MEPTEC REPORT WINTER 2018

CHIPS eco-system are being explored. For example, silicon IP companies are pursuing the option of becoming chiplet suppliers. Instead of just providing soft or even hard IP, they will sell verified chiplets ready for assembly. This is one example of the innovation brought by the CHIPS approach to the semiconductor marketplace. Conclusion DARPA’s CHIPS program aims to serve as the necessary piece of the puzzle that lets heterogeneous integration gain momentum in the marketplace by leveraging proven approaches of the semiconductor industry. With advantages for both defense and commercial applications, a critical mass of CHIPS adopters is expected. The industry has recognized the great challenges before us in IEEE’s newly revamped International Roadmap for Devices and Systems [13], and an important step was made when the IEEE, SEMI, and ASME jointly established the Heterogeneous Integration Roadmap[14] in recognition of the importance of het-

D. Scott, et al., “Diverse Accessible Heterogeneous Integration (DAHI) Foundry Establishment at Northrop Grumman Aerospace Systems (NGAS),” Proc. IPRM, Santa Barbara, 2015.

[5] Y.-C. Wu, et al., “InP HBT/GaN HEMT/ Si CMOS Heterogeneous Integrated Q-Band VCO-Amplifier Chain,” Proc. IPRM, Santa Barbara, 2015. [6]

Andrew Carter et al., “Wafer-Scale InP/Si CMOS 3D Integration Using Low-Temperature Oxide Bonding.” Compound Semiconductor Week, 2015.

[7]

Lawrence J. Kushner et al., “A 30 GS/s, 12-bit, 8-Vpp, Arbitrary Waveform Generator with Integrated 25 fs Clock in the DARPA DAHI Process.” GOMAC 2016.

[8] D. Green, “DARPA’s CHIPS Program and Making Heterogeneous Integration Com mon,” 3D ASIP, December 2017. [9] D. Green et al., “Heterogeneous Integration at DARPA: Pathfinding and Progress in Assembly Approaches,” ECTC, May 2018. [10]

R. Stevens et al., “An Application Specific IP (ASIP) Approach Offers a Design Solution Between ASICs and FPGA,” 3D ASIP, December 2017.

[11]

P. Borodulin et al., “Disaggregation of Advanced Node SoCs into 2.5D Modular Architectures for Rapid IP Reuse,” 3D ASIP, December 2017.

[12]

M. Lueck et al., “High Density Interconnect Bonding at 10µm Pitch and Below Using Non-Collapsible Microbumps,” 3D ASIP, December 2017.

[13] “International Roadmap for Devices and Systems,” irds.ieee.org/roadmap-2017. [14] “Heterogeneous Integration Roadmap,” eps.ieee.org/technology/heterogeneous integration-roadmap.html .

meptec.org


PACKAGING

Packaging & Assembly for High-Temperature Electronics Part I – Devices and Materials Dr. Randall K. Kirschman R&D Consultant for Electronics Technology

FOR MORE EFFICIENT USE OF resources, and to reduce energy waste and pollution, electronics must be extended into new areas. A key area is operation beyond the present “standard” or “military” temperature range of −55°C to +125°C. Power systems for electric vehicles and airplanes could be more efficient using high-temperature electronics (HTE), capable of operation at environmental temperatures from 200°C to 500°C or beyond.* Closely related is the move toward “distributed systems”: placing more of a system’s electronics close to sensors and actuators to enhance performance (Figure 1). High-temperature electronics is needed because these sensors and actuators are often in high-temperature environments. Additional applications—with an inherent high-temperature environment— include spacecraft, electric-generating plants, and petroleum and geothermal wells[1][2]. For a high-temperature application, operating electronics within the “standard” temperature range exacts a substantial toll in size, weight, power, and system complexity and efficiency. To keep electronics below +125°C, either (a) the electronics must be located in a “standardtemperature” ambient, which is likely remote from where it needs to be for best system performance, or (b) a cooling or refrigeration system, with its associated issues, must be employed. How does electronics extend its operational temperature range upward? Assembly and packaging technology has a major role. It must provide an electroniccomponent-friendly environment—thermal, electrical and mechanical—while not compromising the component’s intrinsic

Figure 1. The idea of a distributed system. (*Aircraft or auto engine, oil well, hot planet, …)

performance. In other words, an extension of the same requirements as for “standard” temperatures [3]. This brief article cannot go into details, but will touch on a few of the major points. Moving to higher temperatures requires assembly and packaging based on (a) materials that can survive and are stable, (b) designs and techniques that prevent interactions among the materials, and (c) processes that are compatible with the materials and electronic components. Extending the thermal, electrical and mechanical design presents an extra challenge because many materials characteristics are strongly temperature dependent, more so as temperature increases. Furthermore, there are nearly always additional environmental stresses to be considered: EMI, magnetic fields, chemicals, dirt, shock/vibration, or radiation. A basic requirement for any electronic system is suitable semiconductor devices (diodes and transistors). Thus, a first question is what are the high-temperature capabilities of semiconductor materials and devices?

Semiconductors Silicon is the mainstay, and a range of Si ICs rated up to ≈ 200–225°C is commercially available (Figure 2); a few can be used to even higher temperatures if derated. Also, SiGe ICs are appearing commercially, rated up to 250°C. Although Si devices have been operated to over 400°C [4], a practical limit for Si is about 300°C for non-power circuits and about 200°C for power circuits. To go beyond the extended-temperature capabilities of Si, the frontrunners are silicon carbide (SiC) [5], gallium nitride (GaN), and diamond (C) [6]. These

Figure 2. Si COTS ICs rated at 175°C (left, V reference) and 210°C (right, 8-ch MUX) (note difference in packaging, plastic vs ceramic). Photos courtesy Analog Devices.

* Unless noted otherwise, all temperatures in this article are environmental/ambient temperatures. meptec.org

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PACKAGING are wide-bandgap (WBG) semiconductor materials, having theoretical semiconducting electronic functionality to at least 1000°C, though the practical temperature limits are significantly less and primarily dictated by the reactivity of other devicefabrication materials (e.g. contacts, dopants, oxides, and their interfaces). In addition to their much higher temperature limits, these materials have other basic advantages over Si, such as higher thermal conductivities and breakdown fields, making them attractive for high power or high frequency even for “standard” temperatures. Thus, these materials are under development independent of applications for high-temperature environments. SiC electronics experienced a difficult birth and childhood, but a range of COTS diodes, transistors and power modules is now available, specified for ≈ 175–225°C ambient (internal temperature will be higher). GaN device development is also progressing, and COTS devices are available for “standard” temperatures. COTS SiC and GaN integrated circuits cannot be far off [7], but in order to justify the higher cost of wide-bandgap manufacture, these circuits will have to provide functionality beyond what is possible using lower-cost Si approaches. C (diamond) may be considered the ultimate semiconductor material, but in comparison to SiC and GaN, development of C devices has been hindered by severe materials and processing difficulties. Devices based on these three materials are capable of very high operating temperatures. Indeed, operation above 800°C, and for more than 10,000 hours at 500°C has been demonstrated for SiC transistors and ICs (Figure 3) [8][9].

Figure 3. A packaged SiC IC operating at 500°C and capable of >10,000 hours operation in air. Photo courtesy NASA Glenn Research Center.

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Figure 4. Processing and operating temperature comparisons for joining methods. For an explanation of TH see the sidebar. Melt T = solder or braze melting temperature.

But one component cannot be considered in isolation from the total system. Transferring the high-temperature capabilities of WBG semiconductor devices to “real-world” applications demands assembly and packaging materials and techniques with equal or higher temperature capabilities. Electrical, thermal and mechanical issues require advances beyond the present COTS Si-device packaging, even for “standard” temperatures [10][11]. What worked for Si will not be adequate. Packages and Substrates Many of the current high temperature COTS products are packaged in plastic, but experience has shown that plastic packages are not stable for long-term operation much above 200°C. Most vendors do not use plastic even for ≈ 200°C (Figure 2). The high coefficient of thermal expansion (CTE) of plastics— particularly above their glass transition temperature—poses an added difficulty. Moreover, plastics’ thermal conductivities are low, a serious disadvantage for high-temperature WBG power applications with their higher power-to-area ratios. Similarly, standard organic PWBs and flex are unsuitable for extended operation much above ≈ 200°C, and their typical Cu traces are subject to oxidation unless protected. Higher temperatures require a shift to inorganic materials: ceramics and metals, which can easily accommodate 500°C or higher. This does not present a serious difficulty, since packages and substrates based on metals and ceramics are well developed. Alumina (Al2O3) and

aluminum nitride (AlN) have been used at temperatures to 500°C, including hightemperature cofired ceramic (HTCC) packages. Likewise, thick-film preciousmetal conductors have been found suited for use at least to 500°C [12]. The primary difficulties for extreme temperatures relate to assembly technology and associated materials compatibility. Attachment/Joining What are possible techniques for attachment of die or substrates? Epoxies and other polymeric adhesives are limited to about 200°C. Ag-filled adhesives also have the issue of Ag migration. Standard soldering or brazing techniques are a candidate, but have a serious drawback: the melting temperature must exceed the highest operating temperature of the assembly [13]. On top of that, the processing temperature must be above the solder or braze melting temperature, typically by tens of degrees (Figure 4 upper). This is compounded when step soldering or brazing is needed. Such high processing temperatures can damage components and also introduce high stress when cooled because of CTE differences. Several alternative techniques have been devised, so that the processing temperature is approximately the same as— or preferably lower than—the subsequent operating temperature (Figure 4 lower) [10]. One such technique is sintering, typically with Ag particles, which can be sintered at 300°C or lower, and which should be stable to temperatures approaching 962°C, the melting point of Ag. Figure 5 left illustrates an assembly meptec.org


Figure 5. Pre-processing illustrations of Ag sintering (left), and Cu-Sn TLP (right).

before heating; during sintering the Ag particles will join to form a typically ≈ 80% dense solid, and will also bond to the substrate and die metallizations. However, migration remains a concern. Another technique is transient liquidphase (TLP) bonding and its sibling diffusion bonding. TLP bonding can use a wide variety of materials and arrangements[14]: one example, using Cu and Sn, is illustrated in Figure 5 right [15]. Upon heating the assembly to 300°C (a temperature well below the melting point of Cu but above that of Sn) the Sn liquefies and interacts with the Cu, to form a solid bond stable to > 400°C. A third technique uses thick-film materials [9][12]. However, these alternative joining methods have their drawbacks compared to established techniques, among them is that they are time-inten-

Figure 6. A 300°C telemetry system with three SiC ICs Au flip-chip bonded to Au thin-film traces on an AlN substrate. Photo courtesy GE Global Research.

Figure 7. Cross-section of a Au wire bonded to Al metallization illustrating degradation after 4000 hours at 200°C. Photo courtesy Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration.

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sive and require changes from existing procedures and equipment. Interconnections and Interactions The next step is electrical interconnection, which often is via wire or ribbon bonding. Au is suitable for high-temperature interconnections to 500°C or higher, because of its relative inertness and high melting point of 1064°C. Likewise, Cu, Pd-clad Cu, Ni or Pt, should be capable of 500°C or higher, although additional experience is needed. Al and doped Al should be adequate up to 500°C, but their melting points of 660°C for Al and a tad lower for doped Al represent a TH of ≈ 0.8 at 500°C, which risks restructuring from time and cycling. Also, Al and Cu wires would require isolation to avoid interactions with oxygen or other possible ambients. Bump bonding is an alternative, and has been validated for 300°C circuits (Figure 6) [16], and examined to 500°C [17]. As temperature rises, interactions such as interdiffusion and corrosion become increasingly likely, driven by the greater thermal energy. Thus, a major difficulty in wirebonding arises from interactions between the bondwire and other materials. A long-standing example is the interaction between Au and Al (Figure 7) [18] , often referred to as “purple plague,” and which has been a problem even for “standard-temperature” electronics. Other combinations of materials—solders as well as bondwires—are susceptible to detrimental interactions with metallizations on die, substrates, or passive components. Similarly, detrimental interactions can become problematic with multilayer metallizations. Fortunately, methods of avoiding such interactions are known, but require care in selecting materials and designs. Encapsulation and Underfill Encapsulants, typically based on polymers, present temperature limitations and high CTE similar to those of organic packages, substrates, and adhesives.

TH, the homologous temperature, is a dimensionless ratio of the melting (eutectic or liquidis) temperature of a material to an ambient or operating temperature. The temperatures are absolute temperatures (kelvins or K). TH thus allows a basis for comparison of materials. An operational TH ≤ 2/3 is recommended, but electronic components often exceed this. For example, consider Sn63/ Pb37 solder, which has a melting (eutectic) temperature of 183°C = 456 K. Operation of electronic components to the upper limit of the “standard-temperature” range (i.e. 125°C = 398 K) represents a TH of nearly 0.9 for Sn63/Pb37 solder! Electronics reliability was achieved with Sn63/Pb37 even though the solder has reduced strength and is subject to creep at this high TH. Lead-free SAC solders with melting temperatures of ≈ 220°C have a slightly more comfortable TH of ≈ 0.8. From the opposite viewpoint, the upper end of the “standard” electronics temperature range, 125°C = 398 K, would indicate a solder melting temperature of 597 K = 324°C for a TH of 2/3 or 498 K = 225°C for a TH of 0.8. Thus, for the upper diagram in Figure 4, using an operating temperature of 300°C = 573 K, would indicate a melting temperature for the solder (braze*) of 586°C for TH of 2/3 or 443°C for TH of 0.8. * In electronics, higher temperature (≈ > 300 - 400°C) materials are often referred to as brazes.

A possible exception is silicone-based materials, which could be usable to ≈ 250°C [19]. Alternatives are glasses or ceramics, but these have high stiffness. Additional experience is needed for encapsulants and underfills for hightemperature service. ◆ Read Part II of Packaging & Assembly for High-Temperature Electronics in the Spring 2019 issue of the MEPTEC Report. continued on page 22

WINTER 2018 MEPTEC REPORT 21


PACKAGING Acknowledgements I am indebted to Rich Grzybowski (MACOM), Colin Johnston (Department of Materials, University of Oxford), Phil Neudeck (NASA Glenn Research Center), David Shaddock (General Electric Global Research), Harold Snyder (Physical Solutions Group), and Jeff Watson (Analog Devices) for reviewing this article and for valuable suggestions and providing graphics. Meetings Meetings on high-temperature electronics take place yearly, sponsored by IMAPS: HiTEC (International Conference and Exhibition on High Temperature Electronics, even years in the USA) and HiTEN (International Conference and Exhibition on High Temperature Electronics Network, odd years in Europe). For information on past meetings, or to be alerted by e-mail of upcoming extreme-temperature electronics events, please visit www.ExtremeTemperatureElectronics.com. References [1] P. Voosen, “Armed with tough computer chips, scientists are ready to return to the hell of Venus,” Science, 22 Nov. 2017 (http://www. sciencemag.org/news/2017/11/armed-toughcomputer-chips-scientists-are-ready-returnhell-venus); doi:10.1126/science.aar5433 [2] J. Watson and G. Castro, “High-temperature electronics pose design and reliability challenges,” Analog Dialogue, 46-04, April 2012 (http://www.analog.com/en/analogdialogue/articles/high-temperature-electronicpose-design-challenges.html). [3] R. W. Johnson, Introduction to Part VIII: “Hybrid materials, assembly, and packaging,” pp. 729-748 in High-Temperature Electronics, ed. R. Kirschman, IEEE Press/Wiley, 1999; ISBN: 0-7803-3477-9. [4] R. K. Kirschman, Introduction to Part I: “General introduction,” pp. 3-35, in High-Temperature Electronics, ed. R. Kirschman, IEEE Press/Wiley, 1999; ISBN: 0-7803-3477-9. [5] R. Singh and S. Sundaresan, “Fulfilling the promise of high-temperature operation with silicon carbide devices,” IEEE Power Electronics Magazine, v. 2, n. 1, pp. 27–35, March 2015.

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[6] S. Shikata, “Single crystal diamond wafers for high power electronics,” Diamond and Related Materials, v. 65, pp. 168–175, May 2016; doi:10.1016/j.diamond. 2016.03.013. [7] E. Ramsay, “The heat is on: The quest for high temperature analogue and mixed signal electronics is taking advantage of silicon carbide’s properties,” New Electronics, pp. 29-30, 24 May 2016 (http://www.newelectronics.co.uk/ electronics-technology/the-quest-for-high-temperature-analogue-and-mixed-signal-electronicsis-taking-advantage-of-silicon-carbides-properties/141355/). [8] G. Beheim, P. G. Neudeck and D. J. Spry, “High temperature SiC electronics: Update and outlook,” NASA Glenn Research Center Propulsion Controls and Diagnostics Workshop, Cleveland, Ohio, 28-29 Feb. 2012 (slides) (http://www.grc.nasa.gov/www/cdtb/aboutus/ workshop2012/Presentations/Session%203.%20 Distributed%20Engine%20Control/DEC_04_ Beheim.pdf). [9] P. G. Neudeck, D. J. Spry, L. Chen, N. F. Prokop and M. J. Krasowski, “Demonstration of 4H-SiC digital integrated circuits above 800 °C,” IEEE Electron Device Letters, v. 38, n. 8, pp. 1082–1085, Aug. 2017.

power module,” Rev. Adv. Mater. Sci., v. 53, pp. 147-160, 2018 [15] S. W. Yoon, M. D Glover, H. A. Mantooth and K. Shiozaki, “Reliable and repeatable bonding technology for high temperature automotive power modules for electrified vehicles,” Journal of Micromechanics and Microengineering, v. 23, 015017, 12 pages, 2013; doi:10.1088/09601317/23/1/015017 [16] R. Ghandi, C.-P. Chen, L. Yin, R. Saia, T. Johnson, P. Sandvik, K. Fang and R. W. Johnson, “Reliability of SiC digital telemetry circuits on AlN substrate,” IMAPS Conference and Exhibition on High Temperature Electronics Network 2013 (HiTEN 2013), Oxford, U.K., 8–10 July 2013, pp. 302–308 (www.imapsource.org/doi/abs/10.4071/HITEN-WP16); doi:10.4071/imaps.397. [17] D. Shaddock and L. Yin, “High temperature electronics packaging: An overview of substrates for high temperature,” 2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 24–27 May 2015, pp. 1166-1169; doi: 10.1109/ ISCAS.2015.7168846.

[10] J. Broughton, V. Smet, R. R. Tummala and Y. K. Joshi, “Review of thermal packaging technologies for automotive power electronics for traction purposes,” Journal of Electronic Packaging, v. 140, n. 4, 040801-1 to -11, Paper No: EP-17-1128, Dec. 2018; doi: 10.1115/1.4040828.

[18] M. Schneider-Ramelow, S. Schmitz, B. Schuch and W. Grubl, “Kirkendall voiding in Au ball bond interconnects on Al chip metallization in the temperature range from 100 – 200°C after optimized intermetallic coverage,” 2009 European Microelectronics and Packaging Conference, Rimini, Italy, 15-18 June 2009 (http://ieeexplore.ieee.org/stamp/stamp. jsp?tp=&arnumber=5272967).

[11] N. Kaminski, “The ideal chip is not enough: Issues retarding the success of wide band-gap devices,” Japanese Journal of Applied Physics, v. 56, n. 4S, 04CA03, 2017 (http://iopscience.iop.org/article/10.7567/ JJAP.56.04CA03); doi.org/10.7567/ JJAP.56.04CA03.

[19] R. Khazaka, L. Mendizabal, D. Henry, R. Hanna and O. Lesaint, “Assessment of dielectric encapsulation for high temperature high voltage modules,” 2015 IEEE 65th Electronic Components & Technology Conference, San Diego, California, 26–29 May 2015, pp. 1914– 1919; doi: 10.1109/ECTC.2015.7159862 ◆

[12] L.-Y. Chen, P. G. Neudeck, D. J. Spry, G. M. Beheim and G. W. Hunter, “Electrical performance of a high temperature 32-I/O HTCC alumina package,” International Conference on High Temperature Electronics (HiTEC 2016), Albuquerque, New Mexico, 10–12 May 2016 (http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa. gov/20160014867.pdf); doi: 10.4071/2016HITEC-66 [13] P. T. Vianco, “Challenges facing the high temperature electronics industry in the event of restrictions on high Pb solders,” 2014 SMTA Gulf Coast Chapter Expo, 6 March 2014 (slides) (http://www.smta.org/chapters/files/ Houston-2014-Presentation-Vianco.pdf). [14] D. H. Jung, A. Sharma, M. Mayer and J. P. Jung, “Review on recent advances in transient liquid phase (TLP) bonding for thermoelectric

Dr. Randall Kirschman is based in Silicon Valley and provides consulting related to R&D for electronic devices and circuits, as well as assistance in obtaining funding, particularly for extreme temperatures. He also presents professional development courses covering the principles and practical aspects of low-temperature and high-temperature electronics. (www.ExtremeTemperatureElectronics.com). He received his Ph.D. from Caltech in physics and electrical engineering. E-mail: ExtElect@ gmail.com.

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WB1 and WB2 Pull Test Data 600

Force (g)

THERE ARE MANY QUALITY management systems (QMS) that are used in the microelectronic assembly business, too many to list them all here. AS9100 is for aerospace, IATF for automotive, ISO13485 for medical, ISO17025 for calibration and test labs, just to mention a few. Most of these standards are based from the ISO9001 QMS, and for good reason, ISO 9001 is viewed by most people as the minimum table stakes of good business practice. At SMART Microsystems, we have chosen to be ISO 9001-2015 registered, completing our third annual reassessment external audit in November. Although ISO has gone through a lot of changes over the years, the guiding principles are still just plain common sense for the microelectronics assembly business. The seven ISO guiding principles are: customer focus, process approach, continuous improvement, evidence-based decision making, leadership, engagement of people, relationship management. Customer focus seems like a simple enough concept, but exactly how is it implemented in practice? We like to say that the “voice of the customer” is ever present in the beginning, the end, and everywhere in between in the internal processes of any work being performed. We also reach back to our customers to get feedback on their unique perspective of what they think of the work we have performed for them. We document the feedback and record it for future reference. The process approach can be as simple or as complicated as we please. ISO 9001 does not dictate how an organization conducts business, but requires that one can produce evidence of the process. At SMART we use a simple but effective method of tracking work in process.

550

Pull Data

500

UCL

450

LCL

400

LSL

350

USL

300 1

8

15 22 29 36 43 50 57 64 71 78 85 92 99 106 113 120 127 134 141

Sample

SPC data for evidence based decision making.

Example of PFMEA.

All work in process at SMART has a “traveler” document with it that contains all of the information needed to complete the work required for that job. This document then becomes a permanent record when the job is complete. In addition, all of the major activities that are customer

related have a well-documented process. Continuous improvement is a major focus of ISO 9001-2015. It is no longer adequate to simply demonstrate what has been done through the year, but also how the organization has improved. What defined steps the organization is taking to meptec.org


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improve. In our case, we conduct regular quality training of the entire staff to continuously improve our implementation of the QMS. We also perform regularly scheduled reviews of our processes and customer feedback at our scheduled management review meetings. Evidence-based decision making is a process like any other. It takes a certain level of organizational discipline to establish and maintain the process. There are a lot of tools that are available to facilitate the effort, like DFMEA, PFMEA, SPC, design reviews, and DOE. We use all of these tools and some others, on a regular basis, to bring quantitative data to the decision making process. The microelectronics assembly business is a very technical and detail oriented business, so tools like a FMEA and DOE are a natural fit. Over time, these tools have become a staple of our business, it just so happens that they also fit the ISO evidence based decision making model. Leadership, engagement of people, and relationship management are all basic requirements of good and effective leadership in any business. In the new ISO 9001 standard there is a very real focus on the engagement of management. In fact, the quality representative position in an organization has been eliminated in the new standard. This is driving action and engagement to higher levels in the

organization. This means that the executive level manager in the organization can no longer just push the requirements on to the quality representative, they must be engaged. This approach fosters a top down effect that demonstrates to everyone in the organization that the top management is quality centric, and has real buy-in. I think that we can all agree that this is good for any organization. When most people that have been in business for some time think of ISO compliance, they think of a lot of meaningless paperwork and painful audits. But this is quite simply not the case, because the current ISO compliance does

not dictate the method you use, only the results. Having just completed our annual registration reassessment audit with no findings, we often get the question “how do you do that?”. The answer is actually quite simple. As a microelectronics assembly business, we were ISO compliant long before we achieved ISO registration. In fact, internally as an organization, our audits are a non-event because nothing changes and no special preparation is required by the staff. We simply keep doing those things we have been doing all along. So, if your organization is doing all of the things that are required to be a good and customer focused business, you are already ISO compliant, so why not get credit for it and achieve registration. At SMART we use ISO registered suppliers, and we love to have ISO registered customers. For more information about SMART services visit smartmicrosystems.com. ◆ William Boyce is the Engineering Manager at SMART Microsystems. He has served in senior engineering roles over the last 19 years with accomplishments that include manufactured automotive sensors. He is certified in EIT and Six Sigma Green Belt and is an industry recognized expert in Al wire bonding. Additionally, he designed and led the metrology lab and machine shop at Sensata. Mr. Boyce earned a Bachelor of Science in Engineering degree from the University of Rhode Island and has been a member of the IMAPS New England Chapter for over 10 years.

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TECH BRIEFS

State-of-the-Art Technology Briefs A special feature courtesy of Binghamton University We are pleased to continue this feature in the MEPTEC Report, brought to us by new Advisory Board member Dr. Gamal RafaiAhmed from Xilinx. The State-of-the-Art Technology Briefs contains articles from the Binghamton University S3IP “Flashes.” Full text is available upon request through the IEEC Site at: http://www.binghamton.edu/s3ip/index.html.

Additive 3-D printing manufacturing can be used to manufacture porous electrodes for lithium-ion batteries. However, because of manufacturing process limitations the design of these 3-D printed electrodes is limited to only a few architectures. Carnegie Mellon University researchers have developed a revolutionary new method of 3-D printing battery electrodes that creates a 3-D microlattice structure with controlled porosity. This structure used as batteries’ electrodes can improve battery performance with a fourfold increase in specific capacity and a twofold increase in areal capacity when compared to a solid block electrode. (IEEC file #10749, EIN 007, 8/1/18) Harvard University researchers have developed a new printing method that uses sound waves to generate droplets from liquids with a large range of composition and viscosity. This technique could enable the manufacturing of new biopharmaceuticals, cosmetics, and food, and expand optical and conductive materials applications. The use of acoustic forces enables myriad materials to be printed in a drop-on-demand manner. The researchers built a subwavelength acoustic resonator that can generate a highly confined acoustic field resulting in a pulling force exceeding 100 times the meptec.org

normal gravitation forces at the tip of the printer. (IEEC file #10793, Printed Electronics World, 9/11/18) University of Delaware engineers are developing the next-generation smart textiles. Their approach is an application of flexible carbon nanotube composites coatings on a series of fibers, such as nylon, cotton, and wool. Fabric suited with this sensing technology can lead the charge toward future “smart garments.” The carbon nanofibers release electrical changes in the fabric when squeezed. The coatings measure a large range of pressures. The nanocomposite coatings “are created on the fibers using electrophoretic deposition (EPD) of polyethyleneimine functionalized carbon nanotubes. (IEEC file #10768, Design News, 8/16/18)

University of Illinois researchers found that by “sandwiching” two-dimensional (2D) materials used in nanoelectronic devices between their three-dimensional silicon bases and an ultrathin layer of aluminum oxide they can significantly reduce the risk of component failure due to overheating. Many silicon-based electronic components contain 2D materials (such as graphene), hence incorporating 2D materials into components allows them to be several orders of magnitude smaller than if they were made with conventional, 3D materials. (IEEC file #10792, R&D, 9/12/18) A new method to 3D print lithium-ion batteries in virtually any shape has been developed by Duke University researchers. Electric vehicles and most electronic devices, such as cell phones and laptop computers, are powered by lithium-ion batteries. Until now, manufacturers have had

to design their devices around the size and shape of commercially available batteries. To print the lithium-ion batteries with a 3D printer, the researchers increased the ionic conductivity of PLA (polylactic acid) by infusing it with an electrolyte solution. In addition, they boosted the battery’s electrical conductivity by incorporating graphene or multi-walled carbon nanotubes into the anode or cathode, respectively. (IEEC file #10865, Science Daily, 10/17/18)

Chinese researchers have developed a hybrid conductive material that is part elastic polymer and part liquid metal. Circuits made with this material can take on most two-dimensional shapes, are highly conductive, stretchable, fully biocompatible and able to be fabricated conveniently across all size scales with micro-feature precision. This will have broad applications for both wearable electronics and implantable devices. (IEEC file #10803, US Tech, 9/14/18) RMIT University researchers have developed an option for scalable quantum computers using a topological photonic chip to process quantum information. The team demonstrated that quantum information can be encoded, processed and transferred at a distance with topological circuits on the chip. The new chip design will open the way to studying quantum effects in topological materials and to a new area of topologically robust quantum processing in integrated photonics technology. The breakthrough could lead to the development of new materials, new generation computers, and a better understanding of fundamental science. (IEEC file #10801, R&D, 9/14/18) WINTER 2018 MEPTEC REPORT 27


TECH BRIEFS

Drexel College researchers have developed a method for spraying invisibly thin antennas, made from a type of two-dimensional, metallic material called MXene, that perform as well as those being used in mobile devices, wireless routers and portable transducers. The ability to spray an antenna on a flexible substrate or make it optically transparent there could have a lot of new places to set up networks. This technology could enable the truly seamless integration of antennas with everyday objects which will be critical for the emerging Internet of Things, (IEEC file #10818, Science Daily, 9/21/18) ITMO University researchers using MAPbI3 perovskite, with silicon particles between the mesoporous TiO2 transport layer and active layers were able to enhance solar cell efficiency up to 19%. Various metal nanoparticles have been tried before, but can have drawbacks such as absorbing energy, or increasing corrosion. In the case of the silicon particles, they don’t absorb light, nor do they interact with other materials in the cell. Dielectric particles don’t absorb light, so they don’t heat up. They are chemically inert and don’t affect the stability of the battery. Besides, being highly resonant, such particles can absorb more light of a wide range of wavelengths. (IEEC file #10790, Electronics Weekly, 9/7/18) MARKET TRENDS MARKET TRENDS

Tufts University researchers have developed a “smart” bandage that will actively monitor the condition of wounds and deliver drug treatments to improve healing. The bioelectronics bandage features integrated pH and temperatures sensors that electronically trigger drug release when it senses that wounds are not healing 28 MEPTEC REPORT WINTER 2018

properly. Bioelectronics is an intersection between electronic engineering and life sciences. The area of precision diagnostics and precision medicine will be revolutionized by innovations of this type. (IEEC file #10804, R&D, 9/6/18) The “RF-over-Fiber market is expected to grow from $336 million in 2018 to $566 million by 2023, at a CAGR of 10.97%. The primary drivers for this increase are the demand for fiber optic cables with higher bandwidth, adoption of 4G, 5G, LTE advanced, and VoIP technologies, and military enhanced communication and security. The L band accounts for the largest share of the RF-over-fiber market. (IEEC file #10778, Sensors, 8/16/18)

A “wearable cockpit” is being developed by BAE Systems to shape future intuitive technologies for pilots. In the ‘wearable cockpit you remove many of the physical elements of the cockpit, and replace it with a virtual display, projected through the helmet. The concept is a software-only cockpit that’s upgradeable, adaptable, and reconfigurable. Pilots are heading toward congested military domains that will increase data sources and complexity of assistive technology instead of floundering with information overload, pilots need quick access to critical information. (IEEC file #10828, ECN, 9/24/18) The silicon-on-insulator market to reach $1.83 Billion by 2023 up from $686 million, with a CAGR of 21.7%. The increasing use of SOI wafers in advanced devices such as smartphones, and wearables are expected to boost the market for consumer electronics applications. Manufacturing thin wafers with SOI technology prevents the wastage of silicon thus reducing the cost of the semiconductor devices. The effective use of silicon during the manufacture of thin SOI wafers is a major fac-

tor driving the growth of the SOI market. (IEEC file #10753, Solid State Technology, 7/27/18) The IoT market is $5.28 billion in 2018 and projected to reach $22.48 billion by 2023, with a CAGR of 33.60%. Pressure sensors is the largest share of IoT sensors market during the forecasted period. Wireless network technologies will hold the largest share of IoT sensors market, and the IoT sensors market for consumer vertical to grow at highest. (IEEC file #10797, EE Times, 8/22/18) Nantero memory design based on carbon nanotubes (CNTs) is poised to become a replacement for DRAM. Fujitsu aims to ship next year a DRAM alternative using the technology. DRAM represents the largest sector of the semiconductor market, expected to surpass $100 billion in sales this year. Nantero’ s non-volatile NRAMs use electrostatic charge to activate stochastic arrays of CNT cells. This is relatively easy to sputter on to any CMOS process. This can outstrip the DRAM roadmap with a 100mm2 die made in a 28nm process stacking 4-Gbit CNT layers into 16-Gbit devices. (IEEC file #10796, EE Times, 8/22/18)

University of Minnesota scientists have developed a 3D printed an array of light receptors on a hemispherical surface. This is a significant step toward creating a “bionic eye” that could someday help blind people see. They started with a hemispherical glass dome to overcome the challenge of printing electronics on a curved surface. Using their custom-built 3D printer, they applied an ink of silver particles, then used semiconducting polymer materials to print the photodiodes, which convert light into electricity. (IEEC file #10798, Science Daily, 8/28/18)

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University of California researchers have developed printable metal tags that could be attached to items and turn them into “smart” Internet of Things (IoT) devices. The metal tags are made from patterns of copper foil printed onto thin, flexible, paper-like substrates and made to reflect Wi-Fi signals. The tags work like “mirrors” that reflect radio signals from a WIFI router. The tags can be tacked onto objects that people touch and interact with every day, like water bottles, walls or doors. These objects then become smart, connected devices that can signal a WIFI device whenever a user interacts with them. (IEEC file #10776, ECN, 8/16/18) RECENT PATENTS RECENT PATENTS Stacked die package with aligned active and passive through-silicon vias (Assignee: Rambus Inc.) Pub. No – US10026666 - Disclosed is a package-onpackage (PoP) assembly comprises a twotiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wire bonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost throughsilicon vias (TSVs) that connect to stacked DRAM die(s). Multiple interconnections between die (Assignee: Freescale Semiconductor, Inc.) Patent No – 10,037,970 - Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die. Direct bonded copper semiconductor packages (Assignee: Semiconductor Components Ind.) Patent No.- 15/973873-A power semiconductor package includes a meptec.org

first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die is coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. Semiconductor package having routable encapsulated conductive substrate (Assignee: Amkor Technology) Patent No – 10,049,954 - A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. Tall and fine pitch interconnects (Assignee: Invensas Corp.) Pub. No.US10103121 - Types of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Non-wettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers. BINGHAMTON UNIVERSITY BINGHAMTON UNIVERSITY BINGHAMTON UNIVERSITY currently has research thrusts in healthcare / medical electronics; 2.5D/3D packaging; power electronics; cybersecure hw/sw systems; photonics; MEMS; and next generation networks, computers and communications. The S3IP Center of Excellence is an umbrella organization comprising five constituent

research centers. More information is available at www.binghamton.edu/s3ip Integrated Electronics Engineering Center (IEEC) - The IEEC is a New York Center of Advanced Technology (CAT) responsible for the advancement of electronics packaging. Its mission is to provide research into electronics packaging to enhance our partner’s products, improve reliability and understand why parts fail. More information is available at www.binghamton.edu/ieec Center for Autonomous Solar Power (CASP) - The CASP center focusses on thin film solar cells and supercapacitors. The recent progress incudes 7.5% efficiency pure sulfide CZTS solar cell without an antireflection coating, and nano-structured transition metal oxide supercapacitor with specific capacitance of 760 F/g, maximum energy density of 8 Wh/kg, and a power density of 13 KW/kg. The CASP team has been invited to take part in the Cohort 5 NEXUS-NY program to explore market opportunity of a dielectric capacitor technology (patent currently drafted) that recently came out of CASP center. More information is available at www.binghamton.edu/casp. NorthEast Center for Chemical Energy Storage (NECCES) - NECCES has been extended by DOE until 2020. One of our major goals for 2018 is to build the capability to make prototype lithium-ion cells that are more realistic than the coin cells that are now being used. An industry grade dry-room has been installed, and a pouch cell prototype manufacturing line is now being installed. We expect this to be operational before year-end 2018. More information is available at www.binghamton.edu/necces. Analytical and Diagnostic Laboratory (ADL) - The ADL provides an array of analytical and diagnostic tools located in a single facility to address the needs of faculty and industry in understanding materials, structures and failures that are found in electronics packaging. The ADL supports the 5 research centers previously mentioned. The facilities of the ADL are available to our industry partners. More information is available at www.binghamton.edu/adl ◆ WINTER 2018 MEPTEC REPORT 29


Advanced Packaging Technologies Get Reliability Boost from NCF Material Rose Guino, Henkel Electronic Materials LLC

THE PAST DECADE HAS WITNESSED dramatic growth in mobile and computing technology, a market dynamic that has driven the development and adoption of various interconnect solutions. Traditionally, transistor scaling has been the technique used to advance form and function, but this method has become increasingly challenging and costly. Therefore, many device designers are considering new advanced packaging techniques to address the continued requirement for high performance and increased functionality. Modern package designs include increased I/O, system-in-package and higher interconnect densities, among others. As newer packages become thinner and smaller with more I/O for greater function, ensuring the reliability of the designs becomes essential to long-term performance. Stress management and structural bump protection are critical factors, as chips are more fragile than ever with lower silicon nodes and ultra-low dielectric layers. Wafers and dies with through silicon vias (TSVs) are thinner to accommodate

30 MEPTEC REPORT WINTER 2018

3D stacking and thinner substrates are already available, making handling and warpage control more challenging. Achieving higher functionality for a given die size has also given rise to copper (Cu) pillar technology. This technique allows designers to place Cu pillar bumps in higher density, enabling increased I/O and utilizing wafer functionality. But, like other challenging designs, Cu pillar bump pitches of less than 50 μm and narrow sub-40 μm bondline gaps make conventional bump protection methods increasingly problematic. Traditional capillary underfills (CUFs), for example, are hard-pressed to flow in and around the tight dimensions. Because flux cleaning under the tight spaces is also challenging, underfill compatibility with flux residues is a growing concern. In addition, new substrate solder mask designs such as partial or full solder mask openings (SMOs) are making the underfill process more complex and void-prone due to the added substrate topography. Because of these realities, non-conductive paste (NCP) and non-conductive

film (NCF) – also referred to as waferapplied underfill (WAUF) – materials have emerged as the most reliable underfill solutions for Cu pillar and TSV packaging approaches. Both NCP and NCF materials offer excellent bump-pad alignment accuracy through thermal compression bonding, as shown in the process diagram below. In the memory market, however, where 3D TSV stacking applications have evolved into the dominant packaging technique, TSV die applications less than 100 μm thick are challenging for thermal compression bonding of paste materials. Because of the potential for die top and bonding tool contamination with NCPs, packaging specialists have moved toward the use of NCF for die structures – including TSV and Cu pillar – where more controlled flow and fillet formation are required. As illustrated in the diagram on page 32, the NCF is applied via lamination and not only protects the bumps on the wafer, but also serves as additional support for wafer handling and successive processing. Bump protection is achieved

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NON CONDUCTIVE FILM

Advanced Packaging Technologies Get Reliability Boost From NCF Material Today’s smaller footprint, greater I/O package designs dictate use of emerging technologies like through-silicon via (TSV) and copper pillar to address form factor requirements. With this come thinner dies for 3D stacking and higher-density bump, driving the need for greater protection to ensure reliability. In the memory market, where TSV applications with die less than 100 μm thick are common, Henkel’s new non-conductive film (NCF) technology provides controlled flow, stability and protection without the concerns associated with paste-based underfill materials and challenges posed by thermal compression bonding.

For more information, contact 1-800-562-8483 or visit us online at henkel-adhesives.com/electronics All marks used are trademarks and/or registered trademarks of Henkel and its affiliates in the U.S., Germany and elsewhere. © 2017 Henkel Corporation. All rights reserved. (5/17)


immediately following thermal compression bonding, and die stacking of TSV dies is highly viable. The latest NCF material to be introduced to market is a 2-in-1 wafer-applied underfill film from Henkel. Henkel’s NCF has been developed to facilitate die processing for die that are less than 60 μm thick and, as compared to previous generation materials, the new NCF has a long work life of 8 weeks; 6 weeks with the backgrinding tape and an additional 2 weeks once the backgrinding tape is removed. Not only does the backgrinding tape facilitate wafer thinning when required, it also delivers handling stability and enables complete NCF gap filling and coverage for maximum bump protection. The material has lower melt viscosity which allows for lower bond force processing, exceptionally fast three-second cure, a four-month shelf life and no outgassing during processing. Henkel’s NCF has been designed to balance flow behavior and cure kinetics to achieve good joints without entrapment or solder extrusion, provide

good fillet coverage and complete gap filling. In addition to all of the performance and reliability benefits afforded by NCF, film-based materials are ideal for the requirements of memory chip processing and, even for non-memory applications, enable the close placement of die, which is not achievable with paste-based materi-

als. As the industry moves toward more challenging designs and 3D integration, advanced materials such as Henkel’s new non-conductive film will be essential for robust wafer processing and long-term package reliability. Email rose.guino@henkel.com for more about NCF benefits. For Henkel info visit www.henkel.com/electronics. ◆

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32 MEPTEC REPORT WINTER 2018

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OPINION 

continued from page 34

Privacy – The HIPPA Guideline (Health Insurance Portability and Accountability Act) for personal information, maintained by healthcare and insurance industries, mandates information privacy and protection from fraud and theft, including internet related areas. In summary, unlike stand-alone medical devices, connected medical devices must be; secure on-line/on-network, maintain connectivity, follow connectivity guidelines as well as FDA regulations, all while continuing to maintain privacy of personal information. Overcoming these challenges will continue to be the focus for the brightest minds in the medical and electronics industries as they continue to merge resources in these efforts. Progress in connected medical devices as related to diagnostic capabilities, with equal improvement in therapeutic treatments, bring hope to individuals and challenges to the health care industry. The challenges mentioned were specific to the product, however, there is another set of

challenges related to perception, education and training for both the patients and medical professionals. Commercialization of connected devices, with people (not just patients) attempting to understand new technologies and information, may strain professional resources, as they address the consumer calls and questions. I am confident the move toward monitoring and prevention for “maintaining wellness” will continue to improve standards of living, with earlier diagnosis and the advanced therapies improving medical outcomes for infants to senior citizens around the world. This is an exciting time to be involved in the medical electronics industry. Please join us at the upcoming MEPTEC/SMTA Medical Electronics Symposium on May 21 & 22, 2019 to hear keynotes and speakers discuss new medical device technologies, with break-out sessions addressing materials, reliability, assembly, and challenges related to Electronic Medical Devices. (see page11) ◆

Package Substrates

NICHOLAS LEONARDI is Founder and Principal Consultant at Electronics Business Development Experts, a member of the MEPTEC Advisory Board, current Chairman of the 2019 MEPTEC/SMTA Medical Electronics Symposium, and the acting Director of Business Development for SMART Microsystems. Mr. Leonardi brings years of experience in engineering, manufacturing, sales and marketing, with companies including Advanced Micro Devices, General Electric, National Semiconductor (T.I.) and LSI Logic (Avago). Prior industry activity included Chairmanships for; JEDEC Microprocessor Package Standard, SEMI Materials Standards, Electronics Industry Technical Symposiums and participation as Advisory Board member for Arizona State University Bio-Medical Engineering School. Mr. Leonardi holds B.S. Degree in Materials Engineering from Alfred University, in New York. (www.EBDExperts.com)

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WINTER 2018 MEPTEC REPORT 33


OPINION

Challenges in the Commercialization of Connected “IoT” Medical Electronics Nicholas Leonardi Principal Consultant at e-BizDev Experts, MEPTEC Advisory Board Member, Director of Business Development at SMART Microsystems Ltd.

ADVANCEMENTS IN “CONNECTED” medical electronic technologies, with their associated commercialization directly to consumers, are revolutionizing the health care industry. Medical electronics can be seen as the next wave of “Connected Commercialization”, with challenges possibly greater than previous waves, as computers saw their fullest potential connected to the internet, as did cell phones connected on global networks. Therefore, it is important to understand and resolve challenges in medical electronics in our connected world, to continue to strengthen the entire global healthcare system. The large global companies in computing, cell phones and internet activities, including Facebook, Google, Amazon, and Microsoft, are developing their own medical products and partnering with the medical electronics companies like Abbott, Medtronic and GE. This editorial addresses challenges specific to individual human lives and impacting a wide range of medical professionals and organizations. Challenges continue to include; electronics reliability, industry regulation and personal privacy, now adding in complex issues related to internet security and connectivity performance, which become critical. To put things in perspective, measuring your heartbeat or footsteps on the standalone “wrist-band device” is impressive, however, monitoring your EKG on your smartwatch through your smartphone app, which can be uploaded to the cloud is unbelievable. Medical electronic devices for health care, including insulin pumps, defibrillators, CPAP machines, cardiac devices and oxygen tanks are all being monitored remotely. This is valuable information for patients and the medical professionals 34 MEPTEC REPORT WINTER 2018

managing their care plans, without requiring the patient to be supervised or report to a medical facility. Monitoring is considered an initial stage of connectivity, with the other more complex stages to follow as information is gathered, with analysis done by a connected system. The analytical system would then make the appropriate recommendations or change current treatment, putting trust into an automated monitoranalysis-treatment system.

It is important to understand and resolve challenges in medical electronics in our connected world, to continue to strengthen the entire global healthcare system. Surgeons capable of performing robotic minimally-invasive procedures, with a patient in the same operating room, are aware of additional potential risks of performing that same procedure on a patient in a different state or country, with the “connected” systems. Background : IoT / IP - It is important to understand that medical devices and other electronic devices, such as cell phones and watches, that are connected

directly to the Internet (IoT / Internet-ofThings), follow the Internet Protocol (IP). Specifically, “IP” is the “communications protocol” used by the internet to control the flow of information, and although common knowledge to most “techies”, needs to be stated none the less. Therefore, every connected device has their own individual “IP Address” and potential of connecting to all other devices (yes, in the world), part of huge global “IoT” network. Internet Security – This is going beyond just information, with symptom diagnostics and their treatments potentially impacted when corrupted or hacked, risking the lives of patients, noting significant efforts continuing to be placed into this important area. Connectivity – With movement toward WiFi, currently Cellular is preferred method of device connectivity. Being much more mobile and designed for multiple users, it does not slow down like WiFi networks when there are too many users logged onto the system. Regulation – Connected devices are certified to levels of network performance, tested on ability to send and receive data, as well as signal minimums to be connected. Called Over-the-Air (OTA) Tests, they involve the FCC and/or CE and mobile network operators. Reliability – Medical device reliability in the U.S. is governed by the FDA (CDRH) with Classes I, II, and III, increasing in regulation from Class I to Class III. Design related to improved wireless communication, device power and miniaturization are all challenges. continued on page 33

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Magazines and Carriers for Process Handling Solutions

Film Frames

Film Frame Magazines

Film Frame Shippers

Grip Rings

Grip Ring Magazines

Grip Ring Shippers

Lead Frame Magazines - F.O.L./E.O.L.

Stack Magazines E.O.L.

Process Carriers (Boats)

Boat Magazines

I. C. Trays Multi-Channel

I. C. Tubes and Rails

Miscellaneous Magazines

Substrate Carrier Magazines

TO Tapes & Magazines

Wafer Carriers

Accept Nothing Less.

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Profile for MEPCOM LLC/MEPTEC

MEPTEC Report Winter 2018  

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

MEPTEC Report Winter 2018  

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council

Profile for mepcom