DEPARTMENT OF ELECTRONICS & COMMUNICATION “T3 EXAMINATION, 2017-2018� Semester:6TH Subject:Microprocessor & Interfacing Branch: ECE Course Type:CORE Time: 3 Hours Max.Marks: 80
Date of Exam:18/05/2018 Subject Code: ECH-326T Session: I Course Nature: HARD Program: B.Tech Signature: HOD/Associate HOD:
Note: - PART A is Compulsory (2 Marks each). Attempt any two Questions each from Part B and Part C. PART A
Ě…Ě…Ě…Ě…Ě…Ě… equal to_____________ in 64X mode? Q1(a) If Baud rate is 440, the đ?‘‡đ?‘‹đ??ś Q1(b) What is Mode0 of 8253? Q1(c)Explain N Key rollover mode of 8279? Q1(d) Draw Control Word format of 8257? Q1(e) Explain Register Relative Addressing mode with example? Ě…Ě…Ě…Ě…Ě…Ě… Ě…Ě…Ě…Ě…Ě…Ě…Ě… Q1(f)Explain following pins of 8086 (i) đ??ľđ??ťđ??¸ (ii) đ?‘‡đ??¸đ?‘†đ?‘‡ Q1(g)Draw Control Word format of BSR in 8255? Q1(h) Write difference between 8253 and 8254? Q1(i) What is Read Back Command in 8254? Q1(j) What is Full Duplex Communication? PART B
Q2. (i) Explain Flag register of 8086. (5) (ii) Draw and explain Minimum and Maximum Mode operation of 8086. (10) Q3. (i) Explain Internal Block diagram of 8257 Programmable DMA Controller.(10) (ii)Explain the sequence of operation of 8257. (5) Q4. Explain in detail the operation of 8279 IC. (15) PART C
Q5. (i) Explain and Draw Interfacing circuit of 8255 with 8085. (8) (ii) Explain the Modes of 8255 in which it can be functionally programmed. (7) Q6. (i) Draw functional Block Diagram of 8253 and explain its each section. (8) (ii) Design the Hardware & write program to generate 100 msec. delay using 8253. Q7. (i) Explain all the pins of 8251 USART. (ii) Draw and Explain the Block Diagram of 8251in detail. *******
(7) (8)
(7)