International Research Journal of Engineering and Technology (IRJET)
e-ISSN: 2395-0056
Volume: 08 Issue: 07 | July 2021
p-ISSN: 2395-0072
www.irjet.net
FET Structures for Future Technology Nodes Meenakshi Manoj1, Rajesh.M.S2 1Student,
M.Tech VLSI and Embedded System, College of Engineering Chengannur, Kerala, India Dept. of Electronics and Communication, College of Engineering Chengannur, Kerala, India ---------------------------------------------------------------------***---------------------------------------------------------------------2Professor,
Abstract - The Field Effect Transistors (FET) is considered
or that might even replace existing silicon technology and allow device scaling to continue to the atomic scale. The allotropes of carbon make a good substitute to be used instead of silicon. It is found that digital VLSI circuits fabricated from GNRFETs can achieve better properties vs. silicon CMOS [3]. GNRFET in all geometries shows better properties when compared to silicon FETs. The structures shows lower internal parasitic capacitance along with lower affection of short channel effects (SCEs).
as the bedrock of modern electronics. With the growing technological advancements, it is necessary to have a replacement to silicon based devices, as they have shown significant drawbacks in lower technological nodes. The Graphene Nano Ribbon (GNR) based devices can be used as a replacement for conventional silicon based devices. The GNRFET can be scaled down to low nanometer ranges. The benefits of FET geometries can also be used to scale down the device. In this work, device scaling is done for the GNRFE and different geometries are compared. Also the geometrical benefit of back gate geometry is utilized to aggressively scale the structure to sub-3 nm technology node.
The designing of FET have reached much different geometry including double-gate, tri-gate, gate-all-around etc. These structures were designed to obtain better properties and functionality and also to withstand scaling. The firstly designed back-gate FET geometries actually provide major advantages that have not been exploited for highly scaled technologies: (1) back-gate FETs enable physical scaling beyond the limits of both top-gate and gate-all-around FET geometries, and (2) back-gate FETs simultaneously provide significant reduction in parasitic capacitances compared to top-gate and other geometries[1]. These advantages can be used to design a back-gate FET, which belongs in the lower nanometre dimension. This work includes designing of different geometries of back gate GNRFET at lower nanometre dimensions. A back-gate FET, with 30-nm CGP, that falls to 3-nm node is designed. A comparison of both GNRFETs is done to know the advantages.
Key Words: Scaling, back-gate geometry, grapheme Nano ribbon, GNRFET, VLSI, nanotechnology, CGP.
1. INTRODUCTION The world is being advanced every day. New technologies and ideas are being invented and numerous researches are going on. The electronics field is always being equipped with new changes. Each new invention is changing the face of world and electronics. One main field of interest in electronics is the scaling of devices. The sizes of devices have reached up to very lower dimensions, and are expected to be smaller in the coming era. With the basic device being scaled, the electronics equipment’s are being reduced in size and are easy to be handled by the end users. The scaling is done accordingly to Moore’s law and now the progress in silicon technology continues to outpace the historic pace of Moore's Law, but the end of device scaling now seem to be only a few years away [1]. As scaling beyond today’s state-of-the-art sub-10 nm technology nodes becomes increasingly challenging, it remains unclear how transistors will scale to future sub-3 nm technology nodes [1],[-2]. Even if CGP is scales to a large extend, the required shrinking of the physical spacing between the gate and the source/drain of the FET result in increased parasitic capacitance, degrading potential energy-delay product (EDP) benefits [3],[4]. The scaling of device can also give rise to increased short channel effects (SCE) in FETs and can eventually cause degradation of performance and efficiency of FETs.
2. GRAPHENE NANO RIBBON (GNR) Graphene nano ribbons (GNR) are strips of graphene fabricated as sheets at lower nanometer dimensions, with a width less than 100 nm and thickness of 1 – 2 nm. GNR sheets consist of a single layer of atoms making it a monolayer structure. The atoms form a dense honeycomb two-dimensional lattice crystal structure. GNR possess all properties of graphene including good mechanical, thermal and optical properties, high selectivity and sensitivity, optical transparency, good flexibility and elasticity highest ballistic and electron speed and also possess tensile strength ten times that of steel, making it ideal for use in electronic applications when compared to other traditional materials. The most prevalent and significant property being its electrical conductivity. The graphene can be arranged in any geometry according to the application and need. It can be wrapped up into 0-D fullerenes, folded into 1-D nanotubes or stacked into 3-D graphite. GNR is considered one of the most promising models for future nano electronics.
Because of these reasons, it is necessary to search for beyond-silicon emerging nanotechnologies to supplement silicon CMOS. Therefore, it is of intense interest to find new molecular-scale devices that might complement basic silicon platform by providing it with new capabilities -
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