Enhancing Full Adder Efficiency for Low-Power Applications in 32nm CMOS Technology

International Journal of Advanced Multidisciplinary Research and Educational Development Volume 1, Issue 1 | March-April 2025 | www.ijamred.com

ISSN: 3107-6513

Enhancing Full Adder Efficiency for Low-Power Applications in 32nm CMOS Technology Shilpa More1, Gagandeep S. Dhir2, Ramandeep S. Dhir3 1 ,2

Research Scholar, 3Ass.Prof Department of EEE Savitribai Phule Pune University, Pimpri.

Abstract: The partial drive designed for improved speed and compactness of CMOS technology wants the uninterrupted innovation of progressive features and procedures. However, there are no encouraging applicants who can exchange CMOS with improved performance and high-density addition for the moment. CMOS skills for lofty presentation analogue application in conditions of speed-to-power indulgence, tool competence with warm electron inject entry present plan parameter. With the development of new materials also come new manufacturing challenges. We will also discuss the standing of relationship in the CMOS commercial model. The effort, hence, prove the efficiency of GEWE-RC for RFICs by superior competence, enhanced speed power dissipation performance; and thus, in the design and modelling of power amplifiers. This performance valuation is supported out spending ATLAS device simulator.

Keywords— CMOS technology, Mathematical model, characterization vehicles, deep sub micrometer processes

speed, and linear decrease in supply voltage. At the 1. INTRODUCTION A widely adopted and highly regarded MOSFET similar time, transistor region decrease quadraticaly. technology in use today is the complementary metal- The tendency show a deliberate enhance in expire oxide-semiconductor (CMOS) technology. CMOS

region which means that the numeral of transistors

has

increase at least quadraticaly.

become

the

cornerstone

of

modern

semiconductor design, powering a vast array of

CMOS delivers the essential individualities

devices, including microprocessors, memory units,

required for high-density reason plans. Moreover,

and application-specific integrated circuits (ASICs). with recent advances in the field of Bi CMOS, it is Its versatility and energy efficiency have made it the projected that we have a tools which will afford a preferred choice for creating high-performance, low- conversion to the next period. power electronic systems across industries. Grading

2. PROPOSED DESIGN

of MOS transistor scopes is a key feature in the

The design is basically divided into three building

upgrading of performance of CMOS technologies.

blocks. In this design one XNOR gate, two

This power efficiency can be attributed to a quadratic

multiplexer circuits and one inverter has present and

reduction of switching charge, linear increase in

1

International Journal of Advanced Multidisciplinary Research and Educational Development Volume 1, Issue 1 | March-April 2025 | www.ijamred.com

XNOR WORKING

these entire combined make a full adder circuit and perform operations of binary addition.

The

significance

of

ISSN: 3107-6513

In this plan method filled adder formation is

short-circuit

control intended via contravention the filled adder into three indulgence in CMOS buffer, come from the modules. Module 1 is an XOR-XNOR circuit which information that a huge part of the power dissolute drive the extra module; therefore it should contain in VLSI circuit is due to on-chip with off-chip superior dynamic ability plus provide occupied indication driver trails, which are based on inverting swing output concurrently. buffers. Another projected plan, filled adder circuit

For A=1 & B=1, P1 & N2 will be off & N1 will be

is realize through by component 1 & component 2 as on, due to which the output node will be high as there 2 XNOR gate with component 3 as 2:1 MUX. The is no conducting path from output node to ground. planned XNOR unit is intended by inverter plus one There will be a threshold drop in the N1 and to NMOS transistor are used to obtain the amount while maintain the high output swing and reduce the production of this unit is once more process by an

threshold voltage drop and to reduce time delay,

extra comparable component and MUX is used to channel width of N1 can be increased. There are two obtain carry.

XNOR gates which are cascade toward create the SUM. MUX WORKING A multiplexer (MUX) is a device that selectively routes one of many input signals to a single output based on a control line. It functions as an electronic switch, enabling high-speed data transmission by choosing the appropriate signal path. A basic, nonFig1; Block Diagram of Proposed Full Adder

electronic representation of a multiplexer can be

XNOR DESIGN

found in a single-pole, multi-position switch, which manually directs a single input to one of several output positions. In the realm of digital electronics, multiplexers play a vital role in enabling high-speed switching, allowing multiple data sources to be efficiently routed to a single output.

In the context of MOS technology, there are two primary types of MOS transistors: NMOS and

Fig 2: Proposed XNOR cell

2

International Journal of Advanced Multidisciplinary Research and Educational Development Volume 1, Issue 1 | March-April 2025 | www.ijamred.com

ISSN: 3107-6513

PMOS. An NMOS transistor efficiently pulls the The XOR along with XNOR circuit can be output to a "LOW" state but struggles with implemented within dissimilar architectures through performance when transitioning to a "HIGH" state. by dissimilar circuit designs. These articles evaluate Similarly, a PMOS transistor excels in pulling the as well as contrast the presentation of a variety of output to "LOW," but its performance diminishes drawing technique of XOR-XNOR circuits. In when it needs to drive a "HIGH" signal. These today's electronic industry, one of the most critical characteristics influence the design and efficiency of parameters is low power consumption. To develop circuits utilizing both types of transistors. MUX is as devices that are more reliable and efficient, it is exposed into this circuit is planned with the assist of essential to minimize power usage. As the demand general NAND gates where 7 PMOS and 7 NMOS for portable consumer electronics rises and chip sizes are used. The whole numbers of 14 transistors are continue to shrink, managing power dissipation used in the CMOS plan P button is linked toward the becomes increasingly challenging.

Vdd to the output as well as N button is linked

For CMOS circuits, power consumption must be

toward the output to Vss. In this CMOS design minimized for two primary reasons: NMOS works as pull down network and PMOS Thermal management: The primary goal is to reduce works as pull up network.

heat generation, allowing a higher density of

SIMULATION

functions to be integrated onto a single IC chip without compromising performance or stability.

Energy efficiency: With smaller and more complex devices, lowering power consumption ensures longer battery life and reduced energy demands, key factors for the next generation of portable electronics.

Any quantity of control utilization is productive as lengthy as it doesn’t disgrace generally circuit presentation.

Fig3: Schema of Full Adder in DSCH

The second key factor in minimizing power consumption is ensuring optimal performance in

COMPARATIVE ANALYSIS

In this article control plus region expenditure for battery-operated devices. By selecting the right the auto generate design, half tradition intended plan design approach, the power efficiency of circuits can with completely convention planned outline of XOR be significantly enhanced at the design stage. with XNOR based full subtracter has been compared. Without implementing low-power design strategies,

3

ISSN: XXX-XXXX

International Journal of Advanced Multidisciplinary Research and Educational Development Volume 1, Issue 1 | March-April 2025 | www.ijamred.com

devices often face the issue of rapid battery depletion. generation of diminution, through each new Furthermore, packaging and cooling solutions manufacture bring predictable compensation into become

more

complex

and

creating conditions of price, velocity as well as power

costly,

significant challenges in maintaining performance. utilization. There will probably exist variation This, in turn, leads to an unavoidable rise in the resting on CMOS circuit, except rejection essential overall

cost

of

the

device,

making

power move into circuit kind seem towards on the outlook.

management a crucial consideration in modern REFERENCE 1. B. Dilli kumar, K. Charan kumar , M. Bharathi,

electronics development.

CONCLUSION

“Low power multiplexer based full adder using

The continuous miniaturization of the CMOS

pass transistor logic”, International Journal of Advanced Research in Computer Engineering &

technology resulted in ultra fast processors and will

Technology Volume 1, Issue 5, July 2012, pp.

also degrade the device performance due to Short

291-296.

Channel Effects (SCEs). In order to overcome these

2. Hanho Lee and Gerald Soblman, “A new

problems, various device engineering techniques were proposed like source drain engineering (LDD MOSFET) lateral channel engineering (i.e. graded

low_voltage

full

adder

International

Symposium

circuit”, on

Circuits

IEEE and

Systems, 1997, pp. 88-92.

guide MOSFET, corona and Dielectric pouch

3. Pranshu Sharma, Anjali Sharma, Richa Singh,

MOSFET), entry dielectric manufacturing (i.e.

“ Design and Analysis of Area and Power

gateway pile MOSFET), substrate manufacturing

Efficient 1-Bit Full Subtractor using 120nm

(i.e. Silicon On Insulator with Silicon On not

Technology”, International Journal of Computer

anything

Applications Vol.88, No.12, February 2014, pp.

MOSFET)

plus

gateway

electrode

36-42.

manufacturing (i.e. twice gateway MOSFET). The

4. E. Grossar, M. Stucchi, K. Maex, W. Dehaene,

effort obtainable in this exposition was mostly

“Read stability and write-ability analysis of

focused on Dielectric pouch MOSFET from side

SRAM cells for nanometer technologies.” IEEE

guide manufacturing, Silicon On not anything

Journal of Solid-State Circuits, vol. 41, no. 11, pp.

MOSFET from substrate manufacturing as well as

2577-2588, 2006.

twice gateway MOSFET from gateway electrode

5. M.Khare et al., "A high performance 90nm SOI

manufacturing technique that can beat the demerits

technology with 0.992 mm2 6T-SRAM cell",

linked by size MOSFET along with too offer get

Proc. Intl. Electron Devices Meeting, pp. 407–

better machine presentation. Conservative CMOS

410, 2002.

manufacture process have supported numerous

4

ISSN: XXX-XXXX

International Journal of Advanced Multidisciplinary Research and Educational Development Volume 1, Issue 1 | March-April 2025 | www.ijamred.com

6. Neil H. E. Weste, David Money Harris, "CMOS

VLSI Technology, Kyoto, Japan, 10–12 June

VLSI Design A Circuits and Systems Perspective

2003; pp. 65–66.

- 4th Edition", Pearson Education, 2011.

13. Shauly, E.; Parag, A.; Khmaisy, H.; Krispil,

7. 1. S.-M. Kang and Y. Leblebici, “CMOS Digital

U.; Adan, O.; Levi, S.; Latinski, S.;

Integrated Circuits: Analysis and Design”,

Schwarzband, I.; Rotstein, I. Standard cell

McGraw Hill, 2002.

8. Suman Nehra and P. K. Ghosh, “Design of a Low

electrical and physical variability analysis based on automatic physical measurement

Power XNOR gate Using MTCMOS Technique”, Advance in Electronic and Electric Engineering.

for design-for-manufacturing purposes. Proc.

SPIE 2011, doi:10.1117/12.881841.

ISSN 2231-1297, Vol. 3, Number 6 (2013), pp.

14. Shahidi,

701-710.

G.G.

Design-Technology

9. Narendra, S.G. Challenges, Design Choices in

Interaction for Post-32 nm Node CMOS

nanoscale CMOS. ACM J. Emerg. Technol.

Technology. In Proceedings of the 2010

Comput. Syst. 2005, 1, 7–49.

Symposium on VLSI Technology (VLSIT),

10. Sill, F.; You, J.; Timmermann, D. Design of

Honolulu, HI, USA, 15–17 June 2010; pp.

Mixed Gates for Leakage Reduction. In

143–144.

Proceedings of the 17th ACM Great Lakes Symposium on VLSI, New York, NY, USA, 11– 13 March 2007.

11. Smayling, M.; Axelrad, V. Simulation-Based Lithography Optimization for Logic Circuits at 22 nm and Below. In Proceedings of the International Conference on Simulation of Semiconductor

Processes

and

Devices,

SISPAD ’09, San Diego, CA, USA, 9–11 September 2009; pp. 1–4.

12. Arnaud, F.; Boeuf, F.; Salvetti, F.; Lenoble,

D.; Wacquant, F.; Regnier, C.; Morin, P.; Emonet, N.; Denis, E.; Oberlin, J.C.; et al. A Functional 0.69 μm2 Embedded 6T-SRAM bit cell for 65 nm CMOS platform. In Proceedings of the 2003 Symposium on

5