TheESDHandbook
StevenH.Voldman
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LibraryofCongressCataloging-in-PublicationData
Names:Voldman,StevenH.,author.
Title:TheESDhandbook/StevenH.Voldman.
Description:Firstedition.|Hoboken,NJ:Wiley,[2021]|Includes bibliographicalreferencesandindex.
Identifiers:LCCN2020025380(print)|LCCN2020025381(ebook)|ISBN 9781119965176(hardback)|ISBN9781119233107(adobepdf)|ISBN 9781119233138(epub)
Subjects:LCSH:Electricdischarges.|Semiconductors–Protection.| Breakdown(Electricity)
Classification:LCCQC585.7.E43V652021(print)|LCCQC585.7.E43 (ebook)|DDC537.5/2–dc23
LCrecordavailableathttps://lccn.loc.gov/2020025380
LCebookrecordavailableathttps://lccn.loc.gov/2020025381
CoverDesign:Wiley
CoverImage:©Lehrer/Shutterstock
Setin9.5/12.5ptSTIXTwoTextbySPiGlobal,Chennai,India 10987654321
Contents
AbouttheAuthor xxxvii
Acknowledgements xxxix
1ESD,EOS,EMI,EMC,andLatchup 1
1.1ElectrostaticDischarge(ESD) 1
1.1.1WhatDoYouMeanbytheTerm“ElectrostaticDischarge”? 1
1.2HumanBodyModel(HBM) 2
1.2.1WhyDoWeHaveaHumanBodyModel? 2
1.2.1.1WhatDoesitCharacterize? 2
1.3MachineModel(MM) 3
1.3.1WhatisthePurposeoftheMachineModel? 3
1.3.1.1HowisitDifferentfromtheHumanBodyModel? 3
1.4CassetteModel 3
1.4.1WhyDoWeHaveaCassetteModel?WhatDoesitRepresent? 3
1.5ChargedDeviceModel(CDM) 4
1.5.1WhatistheChargedDeviceModel? 4
1.5.1.1WhyisitImportant? 4
1.6TransmissionLinePulse(TLP) 5
1.6.1WhywastheTLPModelIntroduced? 5
1.6.1.1WhyisitSoValuableforCircuitDesignersandESDEngineers? 5
1.7VeryFastTransmissionLinePulse(VF-TLP) 8
1.7.1WhyDoWeNeedtoEvaluateVF-TLP? 8
1.8ElectricalOverstress(EOS) 8
1.9ElectricalOverstress(EOS) 8
1.9.1HowisEOSDifferfromESD? 8
1.10EOSSources–Lightning 9
1.11EOSSources–ElectromagneticPulse(EMP) 9
1.12EOSSources–Machinery 10
1.13EOSSources–PowerDistribution 10
1.14EOSSources–Switches,Relays,andCoils 10
1.15EOSDesignFlowandProductDefinition 10
1.15.1HowDoYouAddEOStotheProductDesignFlow? 10
1.16EOSSources–DesignIssues 11
1.17ElectromagneticInterference(EMI) 12
1.17.1WhatTypeofProductsareSensitivetoEMI? 12
1.18ElectromagneticCompatibility(EMC) 13
1.19Latchup 13
1.19.1WhatisLatchup?WhyisitImportant? 13 QuestionsandAnswers 14
1.20SummaryandClosingComments 15 References 15
2ESDinManufacturing 21
2.1Flooring 21
2.1.1Question:WhyisFlooringanESDIssue? 21
2.2WorkSurfaces 21
2.2.1WhyareWorksurfacesanESDIssue? 21
2.3Garments 22
2.3.1Question:DoGarmentsPlayaRoleinChargingofProducts? 22
2.4WristStraps 22
2.4.1WhyareWristStrapsRequiredinaManufacturingEnvironment? 22
2.5Shoes–Footwear 22
2.5.1HowDoShoesInfluenceTribocharging? 22
2.6Ionization 23
2.6.1WhatistheRoleofIonizationinManufacturing? 23
2.7CleanRooms 24
2.7.1Seating 24
2.7.1.1WhyareChairsaChargingIssue? 24
2.8Carts 26
2.8.1WhyareCartsanESDIssue? 26
2.9ShippingTubes 26
2.9.1WhyareShippingTubesaProblem? 26
2.10Trays 27
2.10.1WhatApplicationareSensitivetoESDinTrays? 27
2.11Measurements 27
2.11.1PackagingandShipping 27
2.11.2ESDIdentification 27
2.12Verification 28
2.12.1ESDProgramManagement–TwelveStepstoBuildinganESDStrategy 28
2.13Audit 28
2.13.1ESDProgramAuditing 28
2.14TriboelectricCharging–HowDoesitHappen? 29
2.15Conductors,Semiconductors,andInsulators 30
2.16StaticDissipativeMaterials 30
2.17ESDandMaterials 31
2.18ElectrificationandCoulomb’sLaw 31
2.18.1ElectrificationbyFriction 32
2.18.2ElectrificationbyInduction 32
2.18.3ElectrificationbyConduction 32
2.19ElectromagnetismandElectrodynamics 33
2.20ElectricalBreakdown 33
2.20.1ElectrostaticDischargeandBreakdown 33
2.20.2BreakdownandPaschen’sLaw 33
2.20.3BreakdownandTownsend 34
2.20.4BreakdownandToepler’sLaw 34
2.20.5AvalancheBreakdown 35
2.21Electro-QuasistaticsandMagnetoquasistatics 36
2.22ElectrodynamicsandMaxwell’sEquations 36
2.23ElectrostaticDischarge(ESD) 36
2.24ElectromagneticCompatibility(EMC) 37
2.25ElectromagneticInterference(EMI) 37
2.26FundamentalsofManufacturingandElectrostatics 37
2.27Materials,Tooling,HumanFactors,andElectrostaticDischarge 38
2.28MaterialsandHuman-inducedElectricFields 39
2.29ManufacturingEnvironmentandTooling 39
2.30ManufacturingEquipmentandESDManufacturingProblems 39
2.31ManufacturingMaterials 39
2.32MeasurementandTestEquipment 40
2.33ManufacturingTestingforCompliance 41
2.34GroundingandBondingSystems 42
2.35WorkSurfaces 42
2.36WristStraps 43
2.37ConstantMonitors 43
2.38Footwear 43
2.39Floors 44
2.40PersonnelGroundingwithGarments 44
2.41Garments 44
2.42AirIonization 44
2.43Seating 45
2.44PackagingandShipping 46
2.45Trays 46
2.46ESDIdentification 46
2.47ESDProgramAuditing 46
2.48ESDOn-ChipProtection 47
2.49ESD,EOS,EMI,EMC,andLatchup 47
2.49.1ESD 47
2.49.2EOS 48
2.49.3EMI 48
2.49.4EMC 48
2.50ManufacturingElectricalOverstress(EOS) 48
2.50.1ManufacturingEOSSources–Machinery 49
2.50.2ManufacturingEOSSources–PowerDistribution 49
2.50.3ManufacturingEOSSources–Switches,RelaysandCoils 49
x Contents
2.51EMI 50
2.52EMC 50
2.53SummaryandClosingComments 50 References 50
3ESDStandards 55
3.1Factory–Flooring 55
3.1.1Factory–Worksurfaces 55
3.1.2Factory–Ionization 55
3.1.3Factory–Garments 55
3.1.4Factory–WristStraps 55
3.1.5Factory–Grounding 56
3.2Factory–ResistanceMeasurementofMaterials 56
3.2.1Components–HBM 56
3.2.2Components–MM 56
3.2.3Components–CDM 57
3.2.4Components–SDM 57
3.2.5Components–TLP 57
3.2.6Components–VF-TLP 57
3.2.7Systems–IEC61000-4-2 58
3.2.8Systems–CableDischargeEvent(CDE) 58
3.2.9Components–HMM 58
3.3JEDEC 58
3.4InternationalElectro-TechnicalCommission(IEC) 59
3.5IEEE 59
3.6DepartmentofDefense(DOD) 59
3.7MilitaryStandards 59
3.8SAE 60
3.9SummaryandClosingComments 60 QuestionsandAnswers 60 References 61
4ESDTesting 65
4.1ElectrostaticDischarge(ESD)Testing 65
4.2ESDModels 65
4.2.1HumanBodyModel(HBM) 66
4.2.2HBMPulseWaveform 67
4.2.3HBMEquivalentCircuitModel 67
4.2.4HBMTesterSource 67
4.3HBMTestSystem 69
4.4HBMTwo-pinTestSystem 69
4.5MachineModel(MM) 69
4.5.1MMEquivalentCircuit 69
4.5.2MMPulseWaveform 70
4.5.3ESDMMTesterSource 70
4.6SmallChargeModel(SCM) 70
4.7SmallChargeModelSource 71
4.7.1ChargedDeviceModel 71
4.8CDMPulseWaveform 72
4.8.1CDMCommercialTester 72
4.8.2CDMEquivalentCircuit 72
4.8.3CDMEquivalentCircuitwithTesterChassis 74
4.8.4HumanMetalModel(HMM) 74
4.8.5HMMPulseWaveform 75
4.8.6HMMPulseWaveformEquation 76
4.9HMMEquivalentCircuit 77
4.10HMMTestEquipment 77
4.11HMMTestConfiguration 78
4.11.1HMMHorizontalConfiguration 78
4.11.2HMMVerticalConfiguration 78
4.12HMMFixtureBoard 78
4.13TransmissionLinePulse(TLP) 82
4.14TLPTestSystems 84
4.14.1VeryFastTransmissionLinePulse(VF-TLP) 84
4.14.2VF-TLPPulseWaveform 84
4.15IEC61000-4-2 87
4.15.1IEC61000-4-2AirDischarge 88
4.15.2IEC61000-4-2DirectContactDischarge 88
4.15.3IEC61000-4-2PulseWaveform 88
4.15.4IEC61000-4-2PulseWaveformEquation 89
4.16EquivalentCircuit 89
4.17TestEquipment 89
4.18CableDischargeEvent(CDE) 90
4.18.1CDE–Charging,Discharging,andPulseWaveform 92
4.18.2ChargingProcess 92
4.18.3DischargingProcess 92
4.19CDEPulseWaveform 93
4.20EquivalentCircuit 93
4.21CommercialTestSystems 94
4.22SystemsElectromagneticInterference(EMI) 95
4.23ElectromagneticCompatibility(EMC) 95
4.24ElectricalOverstress(EOS) 95
4.25Latchup 95
4.26ElectricalOverstress(EOS) 95
4.27EOSSources–Lightning 96
4.28EOSSources–ElectromagneticPulse(EMP) 97
4.29ElectromagneticCompatibility 97
4.30SummaryandClosingComments 100 References 100
5ESDDevicePhysics 117
5.1Electro-thermalInstability 117
5.2StableSystem 118
5.3UnstableSystem 118
5.4DifferentialRelationofVoltageandCurrent 120
5.5TimeConstantHierarchy 121
5.6ThermalPhysicsTimeConstants 121
5.7Adiabatic,ThermalDiffusionTimeScaleandSteadyState 121
5.8Electro-quasistaticandMagnetoquasistatics 122
5.9ElectricalInstability 124
5.9.1ThermalTimeConstantApproach 124
5.9.1.1HeatCapacity 124
5.9.1.2ThermalDiffusion 124
5.9.1.3HeatTransportEquation 124
5.10ThermalPhysicsTimeConstants 125
5.11Adiabatic,ThermalDiffusionTimeScaleandSteadyState 126
5.12ElectricalInstabilityandBreakdown 126
5.12.1ElectricalInstability 126
5.13SpatialInstabilityandElectro-thermalCurrentConstriction 127
5.14EquipotentialSurface 127
5.15HeatFlow 128
5.16ConservationofHeat 128
5.17ElectricPotentialandTemperatureGradient 128
5.17.1MaximumTemperatureandMinimumPotential 128
5.18ElectricEnergy,Resistivity,andThermalConductivity 129
5.18.1IntrinsicTemperature 129
5.18.2RadiusofCurrentConstriction 130
5.18.3DifferentialPotentialandDifferentialThermalPotential 130
5.18.4ResistanceReductionandCurrentConstriction 130
5.18.5ContactRadiusandContourRelationship 131
5.18.6CurrentConstrictionRelationship 131
5.18.7IntrinsicTemperature 131
5.19Breakdown 131
5.19.1Paschen’sBreakdownTheory 131
5.19.2Townsend’sConcept 132
5.19.3Toepler’sLaw 132
5.19.4AvalancheBreakdown 133
5.19.4.1EnergyTransferfromElectricFieldtoCarriers 133
5.19.4.2EnergyBalanceRelationship 133
5.19.4.3ImpactIonizationCoefficient 133
5.19.4.4ImpactIonizationMeanFreePathandOpticalGenerationMeanFree Path 134
5.19.4.5ImpactIonizationCoefficient 134
5.19.5BreakdowninAir 135
5.20ElectronCurrentContinuityRelationship 136
5.20.1Time-dependentElectronPopulation 136
5.20.2ElectronDensity 137
5.21AirBreakdownandPeakCurrents 138
5.22Electro-thermalInstability 139
5.23MathematicalMethods–Green’sFunctionandMethodofImages 141
5.23.1CaseofaParallelepipedinanInfiniteMedium 142
5.24MathematicalMethods–Green’sFunctionandMethodofImages 143
5.24.1CaseofaParallelepipedinanInfiniteMedium 144
5.24.2CaseoftheSemi-infiniteDomain 145
5.25MathematicalMethods–IntegralTransformsoftheHeatConduction Equation 148
5.26FluxPotentialTransferRelationsMatrixMethodology 152
5.27HeatEquationVariableConductivity 154
5.28MathematicalMethods–BoltzmannTransformation 156
5.29MathematicalMethods–TheDuhamelFormulation 158
5.30SphericalSourceTascaModel 160
5.31Wunsch–BellModel 163
5.32TheSmithandLittauModel 166
5.33TheArkihpov–Astvatsaturyan–Godovosyn–RudenkoModel 168
5.34TheVlasov–SinkevitchModel 169
5.35TheDwyer,FranklinandCampbellModel 169
5.36NegativeDifferentialResistorandResistorBallasting 174
5.37AshModel–NonlinearFailurePowerThresholds 176
5.38StatisticalModelsforESDPrediction 178
5.39SummaryandClosingComments 180 References 180
6ESDEventsandProtectionCircuits 189
6.1HumanBodyModel(HBM) 189
6.1.1HBMPulseWaveform 189
6.1.2HBMEquivalentCircuitModel 189
6.1.3HBMTesterSource 189
6.1.4HBMFailure 190
6.2MachineModel(MM) 191
6.2.1MMEquivalentCircuit 191
6.2.2MMPulseWaveform 192
6.2.3ESDMMTesterSource 192
6.2.4MachineModelExampleofMMFailure 193
6.3ChargedDeviceModel 193
6.3.1CDMPulseWaveform 193
6.3.2CDMCommercialTester 193
6.3.3CDMEquivalentCircuit 196
6.3.4CDMEquivalentCircuitwithTesterChassis 196
6.3.5CDMFailureMechanism 196
6.4HumanMetalModel(HMM) 197
6.4.1HMMPulseWaveform 198
6.4.2HMMPulseWaveformEquation 198
6.4.3EquivalentCircuit 200
6.4.4HMMTestEquipment 200
6.4.5HMMTestConfiguration 201
6.4.5.1HorizontalConfiguration 201
6.4.5.2VerticalConfiguration 202
6.4.6HMMFixtureBoard 202
6.5IEC61000-4-2History 204
6.5.1IEC61000-4-2Scope 204
6.5.2IEC61000-4-2Purpose 204
6.5.2.1AirDischarge 205
6.5.2.2DirectContactDischarge 205
6.5.2.3PulseWaveform 205
6.5.2.4PulseWaveformEquation 206
6.5.3EquivalentCircuit 207
6.5.4TestEquipment 207
6.5.5TestConfiguration 208
6.5.6IEC61000-4-2ESDProtectionCircuitry 208
6.5.7ESDGuns 209
6.6IEC61000-4-5 209
6.6.1History 209
6.6.2IEC61000-4-5Scope 210
6.6.3IEC61000-4-5Purpose 210
6.6.4IEC61000-4-5PulseWaveform 210
6.6.5IEC61000-4-5TestEquipment 211
6.6.6IEC61000-4-5TestSequenceandProcedure 212
6.6.7FailureMechanisms 213
6.6.8IEC61000-4-5ESDCurrentPaths 213
6.6.9ESDProtectionCircuitSolutions 213
6.7CableDischargeEvent(CDE) 213
6.7.1CableDischargeEventHistory 213
6.8CDMScope 215
6.8.1CDMPurpose 215
6.8.2CableDischargeEvent–Charging,Discharging,andPulseWaveform 216
6.8.3CDEChargingProcess 216
6.8.4CDEDischargingProcess 217
6.8.5CDEPulseWaveform 217
6.8.6CDEEquivalentCircuit 217
6.8.7CDETestEquipment 218
6.8.7.1CommercialTestSystems 218 References 219
7ESDFailureMechanism 235
7.1TablesofCMOSESDFailureMechanisms 235
7.2LOCOSIsolation-DefinedCMOS 235
7.3LOCOS-boundThickOxideMOSFET 241
7.4LOCOS-BoundStructures 242
7.4.1LOCOS-boundP+/N-wellJunctionDiode 242
7.4.2LOCOS-boundN+/P-SubstrateJunctionDiode 244
7.4.3LOCOS-boundN-Well/P-SubstrateJunctionDiode 244
7.4.4LOCOS-boundLateralN-welltoN-well 244
7.4.5LOCOS-boundlateralN+ toN-well 245
7.5ShallowTrenchIsolation(STI) 245
7.6STIPull-downESDFailureMechanism 245
7.7STIPull-DownandGateWrap-Around 246
7.7.1SilicideandDiodes 247
7.7.2Non-silicidedDiodeStructures 247
7.8MOSFETs 247
7.8.1N-channelMOSFET 247
7.8.2N-channelMulti-fingerMOSFET 250
7.9LOCOS-boundThickOxideMOSFET 252
7.9.1CascodeSeriesN-channelMOSFET 252
7.9.2P-channelMOSFET 252
7.9.3P-channelMulti-fingerMOSFET 253
7.9.4TungstenSilicideGateMOSFET 253
7.9.5PolysiliconSilicideGateMOSFET 254
7.9.6MetalGate/HighKDielectricMOSFET 254
7.10BipolarTransistorDevices 254
7.10.1LOCOS-boundLateralPNPBipolar 254
7.10.2Polysilicon-definedDevices 254
7.10.3Polysilicon-boundGatedDiode 255
7.10.4LateralDiodewithBlockMask 255
7.10.5Resistors 256
7.10.6DiffusedResistors 256
7.10.7N-wellResistors 256
7.10.8BuriedResistors 258
7.11SilicideBlockedN-diffusionResistors 259
7.12SiliconGermaniumESDFailureMechanisms 259
7.13SiliconGermaniumCarbonESDFailureMechanisms 259
7.14GalliumArsenideTechnologyESDFailureMechanisms 260
7.15IndiumGalliumArsenideESDFailureMechanisms 261
7.15.1MagneticRecording 261
7.15.2FinFETTransistors 262
7.16MicroElectromechanical(MEM)Systems 263
7.17Micro-mirrorArrayFailures 265
7.17.1ManufacturingFailure 265
7.17.2EOSFailureMechanisms 265
7.17.3EOSFailureMechanisms–SemiconductorProcess–Application Mismatch 267
7.17.4EOSFailureMechanisms–BondWireFailures 267
7.17.5EOSFailureMechanisms–ExternalLoadtoChipFailures 268
7.17.6EOSFailureMechanisms–PrintedCircuitBoard(PCB)toChipFailures 268
7.17.7EOSFailureMechanisms–ReverseInsertion 268
7.18EOSBondPadandInterconnectFailure 269
7.18.1EOSFailure–PackagingFailure 269
7.18.1.1ElectricalOverstress–PackagingAblation 269
7.19SummaryandClosingComments 272 References 273
8ESDDesignSynthesis 281
8.1ESDDesignSynthesisandArchitectureFlow 281
8.1.1FundamentalConceptsofESDDesign 281
8.1.2Top-downESDDesign 285
8.1.3Bottom-upESDDesign 285
8.1.4Top-downESDDesign–MemorySemiconductorChips 285
8.1.5Top-downESDDesign–ASICDesignSystem 286
8.2ESDDesign–theSignalPathandtheAlternateCurrentPath 287
8.3ESDElectricalCircuitandSchematicArchitectureConcepts 289
8.4TheIdealESDNetwork 289
8.4.1IdealESDNetworksandtheCurrent-VoltageD.C.DesignWindow 289
8.4.2TheESDDesignWindow 290
8.4.3TheIdealESDNetworksintheFrequencyDomainDesignWindow 291
8.5MappingSemiconductorChipsandESDDesigns 293
8.6MappingacrossSemiconductorFabricators 294
8.7ESDDesignMappingacrossTechnologyGenerations 295
8.7.1MappingfromBipolarTechnologytoCMOSTechnology 296
8.7.2MappingfromDigitalCMOSTechnologytoMixedSignalAnalog-DigitalCMOS Technology 297
8.7.3MappingfromBulkCMOSTechnologytoSiliconOnInsulator(SOI) 297
8.7.4ESDDesign–MappingCMOStoRFCMOSTechnology 298
8.7.4.1ESDChipArchitecture,andESDTestStandards 299
8.7.4.2ESDChipArchitecture,andESDTesting 299
8.7.4.3ESDChipArchitecture,andESDAlternativeCurrentPaths 300
8.7.4.4ESDCircuits,I/O,andCores 300
8.7.4.5ESDSignalPinCircuits 300
8.7.4.6ESDPowerClampNetworks 302
8.7.4.7ESDRail-to-RailCircuits 303
8.7.4.8ESDDesignandNoise 304
8.7.4.9ESDInternalSignalPathESDNetworks 305
8.7.5CrossDomainESDNetworks 306
8.8ESDNetworks,Sequencing,andChipArchitecture 306
8.8.1ESDDesignSynthesis–Latchup-freeESDNetworks 307
8.8.1.1ESDDesignConcepts–Buffering–Inter-device 309
8.8.1.2ESDDesignConcepts–Ballasting–Inter-Device 309
8.8.1.3ESDDesignConcepts–Ballasting–Intra-device 311
8.8.1.4ESDDesignConcepts–DistributedLoadTechniques 311
8.8.1.5ESDDesignConcepts–DummyCircuits 312
8.8.1.6ESDDesignConcepts–PowerSupplyDecoupling 313
8.8.1.7ESDDesignConcepts–FeedbackLoopDecoupling 313
8.9ESDLayoutandFloorplan-relatedConcepts 314
8.9.1DesignSymmetry 314
8.9.2DesignSegmentation 315
8.9.2.1ESDDesignConcepts–UtilizationofEmptySpace 317
8.9.2.2ESDDesignSynthesis–AcrossChipLineWidthVariation(ACLV) 317
8.9.2.3ESDDesignConcepts–DummyShapes 318
8.9.2.4ESDDesignConcepts–DummyMasks 319
8.9.2.5ESDDesignConcepts–Adjacency 320
8.9.2.6ESDDesignConcepts–AnalogCircuitTechniques 321
8.9.2.7ESDDesignConcepts–WireBonds 322
8.9.2.8ESDDesignRules 322
8.9.2.9ESDDesignRuleCheck(DRC) 322
8.9.2.10ESDLayoutVersusSchematic(LVS) 322
8.9.3ElectricalResistanceChecking(ERC) 323
8.10ESDArchitectureandFloor-planning 323
8.10.1ESDDesignFloorplan 323
8.10.2PeripheralI/ODesign 324
8.10.2.1PadLimitedPeripheralI/ODesignArchitecture 324
8.10.2.2PadLimitedPeripheralI/ODesignArchitecture–StaggeredI/O 326
8.10.3CoreLimitedPeripheralI/ODesignArchitecture 327
8.10.4LumpedESDPowerClampinPeripheralI/ODesignArchitecture 328
8.10.5LumpedESDPowerClampsinPeripheralI/ODesignArchitectureinthe SemiconductorChipCorners 328
8.10.6LumpedESDPowerClampinPeripheralI/ODesignArchitecture–Power Pads 328
8.10.7LumpedESDPowerClampinPeripheralI/ODesign Architecture–Master/SlaveESDPowerClampSystem 329
8.10.7.1ArrayI/O 330
8.10.7.2ArrayI/O–OffChipDriver(OCD)Banks 331
8.10.7.3ArrayI/ONibbleArchitecture 332
8.10.8ArrayI/OPairArchitecture 333
8.10.9ArrayI/O–FullyDistributed 334
8.10.10ESDArchitecture–DummyBusArchitectures 338
8.10.11ESDArchitecture–DummyVDD Bus 338
8.10.12ESDArchitecture–DummyGround(VSS )Bus 339
8.10.12.1NativeVoltagePowerSupplyArchitecture 340
8.10.12.2SinglePowerSupplyArchitecture 340
8.10.12.3MixedVoltageArchitecture 340
8.10.12.4MixedSignalArchitecture 345
8.10.12.5Mixed-systemArchitecture–DigitalandAnalogCMOS 345
8.11DigitalandAnalogCMOSArchitecture 347
8.12DigitalandAnalogFloorplan–PlacementofAnalogCircuits 348
8.13Mixed-signalArchitecture–Digital,Analog,andRFArchitecture 350
8.14SummaryandClosingComments 351 Questions 351 References 352
9On-chipESDProtectionCircuits–InputCircuitry 363
9.1ReceiversandESD 363
9.2ReceiversandReceiverDelayTime 363
9.3ESDLoadingEffectonReceiverPerformance 364
9.4ReceiversandHBM 365
9.5ReceiversandCDM 366
9.6ReceiversandReceiverEvolution 368
9.7ReceiverCircuitswithHalf-passTransmissionGate 368
9.8ReceiverwithFull-passTransmissionGate 371
9.9Receiver,Half-passTransmissionGate,andKeeperNetwork 373
9.10Receiver,Half-passTransmissionGate,andtheModifiedKeeperNetwork 377
9.11ReceiverCircuitswithPseudo-zeroVT Half-passTransmissionGates 379
9.12ReceiverwithZeroVT TransmissionGate 381
9.13ReceiverCircuitswithBleedTransistors 383
9.14ReceiverCircuitswithTestFunctions 384
9.15ReceiverwithSchmittTriggerFeedbackNetwork 385
9.16BipolarTransistorReceivers 389
9.16.1BipolarSingle-endedReceiverCircuits 389
9.16.2DifferentialReceivers 390
9.16.3SignalDifferentialReceiver 391
9.16.4SignalCMOSDifferentialReceivers 391
9.16.5SignalBipolarDifferentialReceivers 391
9.17CMOSDifferentialReceiverwithAnalogLayoutConcepts 397
9.18CMOSDifferentialReceiverCapacitanceLoading 398
9.19CMOSDifferentialReceiverESDMismatch 398
9.20AnalogDifferentialPairESDSignalPinMatchingwithCommonWell Layout 400
9.21AnalogDifferentialPairCommonCentroidDesignLayout–Signal-Pinto Signal-PinandParasiticESDElements 403
9.22Off-chipDrivers(OCD) 405
9.23Off-chipDriverI/OStandardsandESD 407
9.24Off-chipDriver(OCD)ESDDesignBasics 408
9.24.1OCD:CMOSAsymmetricPull-up/Pull-down 408
9.24.2OCD:CMOSSymmetricPull-up/Pull-down 410
9.24.3OCD:GunningTransceiverLogic(GTL) 411
9.24.4OCD:High-speedTransceiverLogic(HSTL) 412
9.24.5OCD:StubSeriesTerminatedLogic(SSTL) 413
9.25Off-chipDrivers(OCD):MixedVoltageInterface 414
9.26Off-chipDrivers(OCD):Self-biasWellOCDNetworks 414
9.27Self-biasWellOff-chipDriver(OCD)Networks 415
9.28ESDProtectionNetworksforSelf-biasWellOCDNetworks 417
9.29ProgrammableImpedanceOff-chipDriver(OCD)Network 418
9.30ESDInputProtectionNetworksforProgrammableImpedanceOff-chip Drivers 422
9.31UniversalOff-chipDrivers 423
9.32GateArrayOff-chipDriverDesign 423
9.32.1GateArrayOff-chipDriverESDDesignPractices 423
9.32.2GateArrayOCDDesign–UsageofUnusedElements 423
9.33GateArrayOCDDesign–ImpedanceMatchingofUnusedElements 425
9.34OCDESDDesign–PowerRailsOverMulti-fingerMOSFETs 426
9.35Off-chipDriver:Gate-modulatedMOSFETESDNetwork 427
9.36Off-chipDriverSimplifiedGateModulatedNetwork 428
9.37Off-chipDriversESDDesign:IntegrationofCouplingandBallasting Techniques 428
9.38BallastingandCoupling 429
9.39MOSFETSource-initiatedGate-bootstrappedResistorBallastedMulti-finger MOSFETwithDiode 429
9.40MOSFETSource-initiatedGate-bootstrappedResistorBallastedMulti-finger MOSFETwithaMOSFET 430
9.41Gate-coupledDominoResistor-ballastedMOSFET 431
9.42Substrate-modulatedResistorBallastedMOSFET 433
9.43SummaryandClosingComments 434 Problems 435 References 437
10On-ChipESDProtectionCircuits–ESDPowerClamps 441
10.1ESDPowerClamps 441
10.2ESDPowerClampDesignPractices 441
10.3CurrentLoops 442
10.4Impedance 442
10.5Segmentation 443
10.6VoltageLimitations 443
10.7Latchup 443
10.8ESDPowerClampCircuits 444
10.9ClassificationofESDPowerClamps 444
10.10Master-SlaveESDPowerClamps 445
10.11TriggerNetworks 445
10.12ESDPowerClampCharacteristicsandIssues 445
10.13DesignSynthesisofESDPowerClamp–KeyDesignParameters 446
10.14DesignSynthesisofESDPowerClampsTriggerNetworks 446
10.15TransientResponseFrequencyTriggerElementandtheESDFrequency Window 446
10.16ESDPowerClampFrequencyDesignWindow 447
10.17DesignSynthesisofESDPowerClamp–VoltageTriggeredESDTrigger Elements 448
10.18DesignSynthesisofESDPowerClamp–TheESDPowerClampShunting Element 449
10.19ESDPowerClampTriggerConditionvs.ShuntFailure 450
10.20ESDClampElement–WidthScaling 450
10.21ESDClampElement–On-resistance 450
10.22ESDClampElement–SafeOperatingArea(SOA) 451
10.23ESDPowerClampIssues 451
10.24ESDPowerClampIssues–Power-upandPower-down 451
10.25ESDPowerClampIssues–FalseTriggering 452
10.26ESDPowerClampIssues–Pre-charging 452
10.27ESDPowerClampIssues–Post-charging 452
10.28ESDPowerClampDesign 453
10.28.1NativePowerSupplyRC-TriggeredMOSFETESDPowerClamp 453
10.28.2Non-NativePowerSupplyRC-triggeredMOSFETESDPowerClamp 453
10.28.3ESDPowerClampNetworkswithImprovedInverterStageFeedback 454
10.28.4CMOSRC-triggerClampwithCMOSPFETHalf-latchKeeperFeedback 454
10.28.5CMOSRC-triggerClampwithCMOSPFETFull-latchKeeperFeedback 454
10.29ESDPowerClampDesignSynthesis–ForwardBiasTriggeredESDPower Clamps 456
10.29.1ESDPowerClampDesignSynthesis–IEC61000-4-2ResponsiveESDPower Clamps 456
10.29.2ESDPowerClampDesignSynthesis–Pre-chargingandPost-charging InsensitiveESDPowerClamps 457
10.29.3Master/SlaveESDPowerClampSystems 457
10.30SeriesStackedRC-triggeredESDPowerClamps 459
10.30.1ESDPowerClamps–TripleWellSeriesDiodesasCoreClamps 459
10.31TripleWellDiodeStringESDPowerClamp 463
10.31.1TripleWellESDPowerClampNetworkwithIndependentN-BandVoltage Bias 463
10.32BipolarESDPowerClamps 464
10.32.1BipolarVoltage-TriggeredESDPowerClamps 464
10.32.2BipolarESDPowerClamp–ZenerBreakdownVoltage-Triggered 465
10.32.3BipolarESDPowerClamp–BVCEOVoltageTriggeredESDPowerClamp 466
10.32.4TheJohnsonLimitRelationship 466
10.33ESDPowerClampDesignSynthesis–BipolarESDPowerClamps 469
10.33.1MixedVoltageInterfaceForward-biasVoltageandBVCEO-Breakdown SynthesizedBipolarESDPowerClamps 471
10.33.2Ultra-low-voltageForward-biasedVoltage-triggerBiCMOSESDPower Clamp 476
10.34BipolarESDPowerClampswithFrequencyTriggerElements: Capacitance-triggered 480
10.35SiliconControlledRectifierPowerClamps 481
10.35.1ESDSiliconControlledRectifier(SCR)Circuits 481
10.35.2Uni-DirectionalSiliconControlledRectifier(SCR) 481
10.35.3Bi-directionalSiliconControlledRectifier(SCR)ESDPowerClamps 482
10.35.4MediumLevelSCR(MLSCR)ESDPowerClamps 482
10.35.5LowVoltageTriggeredSCR(LVTSCR)ESDPowerClamps 483 Problems 483 References 486
11ESDArchitectureandFloorPlanning 491
11.1ESDDesignFloorPlan 491
11.2PeripheralI/ODesign 492
11.3PadLimitedPeripheralI/ODesignArchitecture 493
11.4PadLimitedPeripheralI/ODesignArchitecture–StaggeredI/O 493
11.5CoreLimitedPeripheralI/ODesignArchitecture 495
11.6LumpedESDPowerClampinPeripheralI/ODesignArchitecture 496
11.7LumpedESDPowerClampinPeripheralI/ODesignArchitectureinthe SemiconductorChipCorners 496
11.8LumpedESDPowerClampinPeripheralI/ODesignArchitecture–Power Pads 497
11.9LumpedESDPowerClampinPeripheralI/ODesignArchitecture–Master/SlaveESDPowerClampSystem 498
11.10ArrayI/O 498
11.10.1ArrayI/O–OffChipDriver(OCD)Banks 499
11.11ArrayI/ONibbleArchitecture 501
11.12ArrayI/OPairArchitecture 503
11.13ArrayI/O–FullyDistributed 504
11.14ESDArchitecture–DummyBusArchitecture 507
11.15ESDArchitecture–DummyVDDBus 507
11.16ESDArchitecture–DummyGround(VSS)Bus 508
11.17NativeVoltagePowerSupplyArchitecture 508
11.18SinglePowerSupplyArchitecture 509
11.19MixedVoltageArchitecture 509
11.20MixedVoltageArchitecture–SinglePowerSupply 509
11.21MixedVoltageArchitecture–DualPowerSupply 511
11.22MixedSignalArchitecture 514
11.22.1MixedSignalArchitecture–CMOS 514
11.22.2MixedSystemArchitecture–DigitalandAnalogCMOS 514
11.22.3DigitalandAnalogCMOSArchitecture 514
11.23DigitalandAnalogFloorPlan–PlacementofAnalogCircuits 515
11.24MixedSignalArchitecture–Digital,Analog,andRFArchitecture 518
11.25ESDPowerGridDesign 519
11.25.1ESDPowerGrid 519
11.25.2ESDPowerGrid–KeyESDDesignParameters 519
11.25.3PowerGridLayoutDesign 519
11.25.4PowerGridDesign–SlottingofPowerGrid 519
11.25.5PowerGridDesign–SegmentationofPowerGrids 520
11.25.6PowerGridDesign–ChipCorners 521
11.25.7PowerGridDesign–StackingofMetalLevels 522
11.25.8PowerGridDesign–WiringBaysandWeavedPowerBusDesigns 523
11.25.9ESDSpecificationPowerGridConsiderations 523
11.25.10CDMSpecificationPowerGridandInterconnectDesignConsiderations 523
11.25.11HMMandIECSpecificationPowerGridandInterconnectDesign Considerations 524
11.25.12SemiconductorChipGuardRingSeal 524
11.26I/OtoCoreGuardRings 525
11.26.1I/OtoI/OGuardRings 526
11.27WithinI/OGuardRings 527
11.27.1WithinI/OCellGuardRing 527
11.28ESD-to-I/OOff-ChipDriver(OCD)GuardRing 527
11.28.1ESDSignalPinGuardRings 528
11.28.2ESDSignalPinGuardRingsandDual-diodeESDNetwork 529
11.28.3MixedSignalGuardRings–DigitaltoAnalog 531
11.28.4MixedVoltageGuardRings–HighVoltagetoLowVoltage 531
11.28.5HighVoltageGuardRings 532
11.28.6PassiveandActiveGuardRings 533
11.28.7PassiveGuardRings 534
11.28.8ActiveGuardRings 534
11.28.9TrenchGuardRings 535
11.28.10ThroughSiliconVia(TSV)GuardRings 536
11.28.11GuardRingDesignRuleChecking(DRC) 537
11.28.12InternalLatchupandGuardRingDesignRules 537
11.28.13ExternalLatchupGuardRingDesignRules 538
11.29GuardRingsandComputerAidedDesign(CAD)Methods 539
11.29.1Built-inGuardRings 539
11.29.2GuardRingParameterizedCells(Pcell) 539
11.29.3Post-processingMethodologyofGuardRingModification 540
11.30SummaryandClosingComments 541 References 541
12ESDDigitalDesign 551
12.1FundamentalConceptsofESDDesign 551
12.2ConceptsofESDDigitalDesign 551
12.3DeviceResponsetoExternalEvents 552
12.4AlternativeCurrentLoops 553
12.4.1Switches 553
12.4.2DecouplingofCurrentPaths 553
12.5DecouplingofFeedbackLoops 554
12.6DecouplingofPowerRails 554
12.7LocalandGlobalDistribution 554
12.8UsageofParasiticElements 555
12.8.1Buffering 555
12.8.2Ballasting 555
12.9UnusedSectionofaSemiconductorDevice,Circuit,orChipFunction 556
12.10UnusedCorners 556
12.11UnusedWhiteSpace 556
12.12ImpedanceMatchingBetweenFloatingandNon-floatingNetworks 556
12.13UnconnectedStructures 557
12.13.1UtilizationofDummyStructuresandDummyCircuits 557
12.13.2Non-scalableSourceEvents 557
12.13.3AreaEfficiency 557
12.14Symmetry 557
12.15DesignSynthesis 557
12.15.1SynthesisandArchitectureofaSemiconductorChipforESDProtection 557
12.15.2ElectricalandSpatialConnectivity 558
12.15.3ElectricalConnectivity 558
12.15.4ThermalConnectivity 559
12.15.5SpatialConnectivity 559
12.16ESD,Latchup,andNoise 559
12.16.1Noise 560
12.16.2Latchup 561
12.16.3InterfaceCircuitsandESDElements 561
12.16.4ESDPowerClampNetworks 564
12.16.5PlacementofESDPowerClamps 566
12.16.6ESDRail-to-RailNetworks 568
12.16.7PlacementofESDRail-to-RailNetworks 570
12.16.8PeripheralandArrayI/O 570
12.16.9GuardRings 572
12.16.10Pads,FloatingPads,andNoConnectPads 573
12.17StructuresUnderBondPads 574
12.18SummaryandClosingComments 575 References 576
13ESDAnalogDesign 583
13.1AnalogDesign:LocalMatching 583
13.2AnalogDesign:GlobalMatching 583
13.3Symmetry 584
13.3.1LayoutDesignSymmetry 584
13.4AnalogDesign–LocalMatching 584
13.5AnalogDesign–GlobalMatching 584
13.5.1DesignOrientation 585
13.5.2SymmetryandMatching 585
13.5.3LayoutDesignSymmetry 585
13.5.4ThermalSymmetry 585
13.6CommonCentroidDesign 586
13.7CommonCentroidArrays 586
13.7.1One-axisCommonCentroidDesign 586
13.7.2Two-axisCommonCentroidDesign 586
13.8InterdigitationDesign 586
13.9CommonCentroidandInterdigitationDesign 587
13.9.1LinewidthControl 588
13.9.2AnalogDesign–AcrossChipLineWidthVariation(ACLV) 590
13.9.3PassiveElementDesign 591
13.9.4ResistorElementDesign 591
13.9.5ResistorElementDesign:DogboneLayout 591
13.9.6ResistorDesign–AnalogInterdigitatedLayout 592
13.10DummyResistorLayout 593
13.11ThermoelectricCancelationLayout 593
13.12ElectrostaticShield 593
13.13InterdigitatedResistorsandESDParasitics 594
13.14CapacitorElementDesign 595
13.15InductorElementDesign 596
13.15.1QualityFactor 597
13.16ESDFailureinInductors 597
13.17InductorPhysicalVariables 598
13.18InductorElementDesign 599
13.19DiodeDesign 599
13.19.1CircularDiodeDesigns 600
13.19.2OctagonalDiodeDesign 600
13.19.3MOSFETDesign 601
13.19.4Multi-fingerMOSFETwithDummyFingers 601
13.20AnalogESDCircuits 602
13.20.1AnalogESDDevicesandCircuits 602
13.20.2AnalogESDDiodes 602
13.20.3AnalogDualDiodeandSeriesDiodes 602
13.20.4AnalogESD:DualDiode–Resistor 602
13.20.5DualDiode–Resistor–DualDiode 605
13.20.6Dual-diodeResistor–GroundedGateMOSFET 606
13.20.6.1Back-to-BackDiodeStrings 606
13.21ESDMOSFETs 607
13.21.1GroundedGateMOSFET 608
13.21.2ESDPowerClamps–RCTriggeredMOSFET 609
13.22Receivers 609
13.22.1SignalBipolarDifferentialReceivers 610
13.23CMOSDifferentialReceiverwithAnalogLayoutConcepts 614
13.23.1CMOSDifferentialReceiverCapacitanceLoading 616
13.23.2CMOSDifferentialReceiverESDMismatch 616
13.23.3AnalogDifferentialPairESDSignalPinMatchingwithCommonWell Layout 617
13.24AnalogDifferentialPairCommonCentroidDesignLayout–Signal-pinto Signal-pinandParasiticESDElements 620
13.25SummaryandClosingComments 624 References 624
14ESDRFDesign 629
14.1FundamentalConceptsofESDDesign 629
14.2FundamentalConceptsofRFESDDesign 632
14.3RFCMOSInputCircuits 637
14.3.1RFCMOSESDDiodeNetworks 637
14.3.2RFCMOSDiodeStringESDNetwork 641
14.3.3RFCMOS–Diode-inductorESDNetworks 643
14.3.4RFInductor-diodeESDNetworks 645
14.3.5RFDiode-inductorESDNetworks 646
14.4RFCMOSImpedanceIsolationLCResonatorESDNetworks 647
14.4.1RFCMOSLC-diodeESDNetworks 647
14.4.2RFCMOSDiode-LCESDNetworks 648
14.5RFCMOSLC-diodeNetworksExperimentalResults 648
14.6RFCMOSLNAESDDesign–LowResistanceESDInductorandESDDiode ClampingElementsin Π-configuration 650
14.7RFCMOST-coilInductorESDInputNetwork 653
14.8RFCMOSDistributedESDNetworks 655
14.9RFCMOSDistributedESD-RFNetworks 656
14.10RFCMOSDistributedRF-ESDNetworksUsingSeriesInductorsand Dual-diodeShunts 656
14.11RFCMOSDistributedRF-ESDNetworksUsingSeriesInductorsandMOSFET ParallelShunts 659
14.12RFCMOSDistributedESDNetworks–TransmissionLinesandCo-planar Waveguides 661
14.13RFCMOS–ESDandRFLDMOSPowerTechnology 663
14.14SummaryandClosingComments 666 References 666
15ESDPowerElectronicsDesign 681
15.1ReliabilityTechnologyScalingandtheReliabilityBathtubCurve 681
15.1.1ReliabilityDesignBox 681
15.1.2ApplicationVoltageandVoltageMetrics–TriggerVoltage,andAbsolute MaximumVoltage 682
15.1.3SafeOperatingArea(SOA) 683
15.1.4ElectricalSafeOperatingArea(E-SOA) 683
15.1.5ThermalSafeOperatingArea(T-SOA) 684
15.1.6TransientSafeOperatingArea 685
15.2InputCircuitry 686
15.2.1ESDInputCircuits 686
15.2.2AnalogInputCircuitProtection 686
15.2.3High-voltageAnalogInputCircuitProtection 686
15.2.4AnalogInputHigh-voltageGroundedGateNMOS(GGNMOS) 686
15.2.5Two-stageHigh-voltageAnalogInputCircuitProtection 687
15.2.6AnalogESDOutputCircuits 687
15.2.7AnalogESDOutputNetworksandDistinctions 688
15.2.8AnalogOpenDrainESDOutputNetworks 689
15.2.9AnalogESDGround-to-GroundNetworks 689
15.2.10Back-to-BackCMOSDiodeString 690
15.2.11HVGGNMOSDiode-configuredGround-to-GroundNetwork 690
15.2.12ESDSilicon-controlledRectifierCircuits 690
15.2.13UnidirectionalSilicon-controlledRectifier(SCR) 690
15.2.14Bi-directionalSilicon-controlledRectifier(SCR) 691
15.2.15Medium-levelSilicon-controlledRectifier(MLSCR) 691
15.2.16Low-voltageTriggeredSCR(LVTSCR) 692
15.2.17AnalogandPowerTechnologywithESDCircuitIntegration 693
15.2.18AnalogESD–IsolatedandNon-isolatedDesigns 693
15.2.19IntegratedBodyTies 693
15.2.20Self-PROTECTINGvsNon-selfProtectingDesigns 693
15.2.21LateralDiffusedMOS(LDMOS)Circuits 693
15.2.22LOCOS-definedLDMOS 694
15.2.23RESURFTransistor 694
15.2.24AdvantagesandDisadvantagesofLOCOS-definedLDMOSTransistors 694
15.2.25ShallowTrenchIsolation(STI)-definedLDMOS 695
15.2.26ShallowTrenchIsolation(STI)-definedIsolatedLDMOS 695
15.2.27LDMOSLayout–CircularDesign 696
15.2.28LDMOSTransmissionLinePulse(TLP)I-VCharacteristic 696
15.2.29Drain-extendedMOS(DeMOS)Circuits 697
15.2.30DeNMOS 697
15.2.31DeNMOS-SCRTransistor 698
15.2.32Ultra-highVoltageLDMOS(UHV-LDMOS)Circuits 699
15.2.33Ultra-highVoltageLDMOS(UHV-LDMOS) 699
15.2.34UHV-LDMOSLayout–CircularDesign 699
15.2.35Ultra-highVoltageLDMOS(UHV-LDMOS)SCR 699
15.3SummaryandClosingComments 702 References 702
16ESDinAdvancedCMOS 709
16.1InterconnectsandESD 709
16.2AluminumInterconnects 710
16.3Interconnects–Vias 714
16.3.1TaperedAluminumVia 714
16.4Interconnects–Wiring 715
16.4.1TitaniumInterconnectsTi/Al/Ti 715
16.4.1.1CopperInterconnects 715
16.5Junctions 719
16.5.1AbruptJunctions 719
16.5.2Low-dopedDrainsandESD 720
16.5.3ExtensionImplants 721
16.5.4GateStructures 722
16.5.4.1SalicidesandESD 722
16.5.5SalicideResistanceModel 723
16.6TitaniumSilicide 725
16.6.1MolybdenumandTitaniumSalicide 729
16.6.2CobaltSilicides 730
16.7ShallowTrenchIsolation 731
16.7.1IsolationStructuresandESD 731
16.7.2LOCOSIsolation 731
16.8LOCOS-boundESDStructures 734
16.9LOCOS-boundp+/n-wellJunctionDiodes 734
16.10LOCOS-boundn+ JunctionDiodes 736
16.11LOCOS-boundn-well/SubstrateDiodes 737
16.12LOCOS-boundLateralN-WelltoN-WellBipolarESDElement 738
16.13LOCOS-boundLateralN+ toN-wellBipolarESDElement 738
16.14LOCOS-boundLateralpnpBipolarESDElement 739
16.15LOCOS-boundThickOxideMOSFETESDElement 739
16.16ShallowTrenchIsolation 739
16.16.1ShallowTrenchIsolationPull-down 740
16.17STI-boundESDStructures 741
16.17.1STI-boundp+/N-wellJunctions 741
16.17.2STI-boundN+ JunctionDiodes 744
16.17.3STI-boundN-well/SubstrateDiodes 745
16.17.3.1Substrates 745
16.17.4SubstrateP++ withEpitaxialRegion 745
16.18SubstrateModeling–ElectricalandThermalDiscretization 746
16.19HeavilyDopedSubstrates 750
16.19.1Substrates:HeavilyDopedSubstrates 750
16.19.2P-substrateDopingScaling 751
16.19.2.1Substrates:Low-dopedSubstrates 751
16.19.3DiffusedWells 752
16.19.4DiffusedWellVerticalProfile 753
16.19.5RetrogradeandVerticallyModulatedWells 755
16.19.6RetrogradeandVerticallyModulatedWells 756
16.19.7RetrogradeWellSubstrateModulation 760
16.20RetrogradeWellsandESDScaling 766
16.20.1Sub-collectors 769
16.20.2BallastResistors 772
16.21TripleWellandIsolatedMOSFETCMOS 775
16.21.1DeepTrenchIsolation 776
16.21.2DeepTrenchasGuardRings 777
16.21.3DeepTrenchandLatchup 778
16.21.4DeepTrenchandESDStructures 778
16.22SummaryandClosingComments 779 References 779
17ESDinSilicononInsulator 783
17.1SilicononInsulator(SOI)Technologies 783
17.1.1SOIESDDesignConcepts 783
17.1.2DistinctionofSOIversusBulkCMOSESDStructures 783
17.1.3VerticalParasiticDevices 784
17.1.4NoParasiticDevices 784
17.2EliminationofCMOSLatchup 784
17.2.1IsolationofCMOSNFETsandCMOSPFETs 785
17.3LackofVerticalBipolarTransistors 785
17.4FloatingGateTieDowns 785
17.5PhysicalSeparationofMOSFETsfromtheBulkSubstrate 785
17.6SOIESDDesignFundamentalConcepts 786
17.6.1SpatialUniformity 786
17.6.2AvoidanceofLocalizedHeating 787
17.6.3AvoidanceofSOIMOSFETDielectricBreakdown 787
17.6.4AvoidanceofMOSFETSecondBreakdown 787
17.6.5SOIversusBulkCMOSLayoutDistinctions 787
17.6.6SOIDesignMOSFETwithBodyContact:T-ShapeLayoutStyle 788
17.6.7FloatingBodyIssue 788
17.6.8SOIMOSFETBodyContact 788
17.6.9SOIT-shapedLateralDiode 789
17.6.10SOIESDDoubleDiodeCircuitwithT-andH-shapedDevices 789
17.6.11SOIESDDoubleDiodeNetworkwithp-channelMOSFETS 790
17.6.12SOIESDDoubleDiodeNetworkwithBodyContactedn-channelMOSFET Devices 791
17.7SOILateralDiodeStructure 791
17.8Transistors–BulkversusSOITechnology 791
17.8.1SOILateralDiodeDesign 792
17.8.2SOILateralDiodePerimeterDesign 793
17.8.3SOILateralDiodeChannelLengthDesign 793
17.8.4SOILateralp+/n /n+ DiodeStructure 793
17.8.5SOILateralp+/p /n+ DiodeStructure 794
17.8.6SOILateralp+/p /n /n+ DiodeStructure 794
17.8.7SOILateralUngatedp+/p /n /n+ DiodeStructure 795
17.8.8SOILateralDiodeStructuresandSOIMOSFETHalos 795
17.9SOIBuriedResistors(BR)Elements 796
17.10DynamicThresholdMOS(DTMOS)SOIMOSFET 797
17.11SOIP+ BodyContactAbuttingn+ Drain 798
17.11.1P+ BodyContactSeparatedfromn+ Drain 798
17.11.2PolysiliconBodyIsolationfromn+ Contact 798
17.12TransmissionLinePulse(TLP)TestingofSOIDiodeDesigns 798
17.13SOIESDwithMOSFETDrainandBodyWidthRatioVariation 799
17.14SOIDual-GateMOSFETStructure 799
17.15SOIESDDesign–MixedVoltageT-ShapeLayoutStyle 800
17.15.1SOIESDDesign:MixedVoltageDiodeStrings 801
