Ee205 term project

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EE 205 – DIGITAL DESIGN TERM PROJECT Keypad Scanner & Sequential Adder/Subtractor Project Objectives: For this semester’s project, you will design and implement a sequential adder/subtractor module. The module will keep track of the latest two numbers entered via a keypad. Then it will either add or subtract them with respect to the mode chosen. Finally the numbers to be operated and result will be displayed on the 7- segment displays of FPGA card. You will write Verilog codes and simulate them in Xilinx ISE and implement your design on FPGA Spartan3E100 card. The project will be split into two parts.

Project Part 1: For the first part, you will only display the number pressed on the keypad in one of the seven segment displays of FPGA. The block diagram for this part is as below;

Figure 1: Part1 Block Diagram Input numbers for the module will be given by a keypad. The keypad you will use should be a 4x4 matrix keypad. All the buttons are connected to each other with wires in a matrix formation, in other words 4 wires for each row and 4 wires for each column. Row and column wires do not touch each other initially. Once a button is pressed, the wires crossing that button

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