Ee 205 preliminary 1

YILDIRIM BEYAZIT UNIVERSITY EE 205 – DIGITAL DESIGN PRELIMINARY WORK – 1 – Behavioral and Structural Implementation of Gate Level Logic Models Background Knowledge: This week there will be no preliminary homework submission. Instead please setup Xilinx, study thoroughly below sections and start working on lab assignment.

Basic Operators: B = {0, 1}

– Variables represent 0 or 1 only, while operators return 0 or 1 only •

is logical AND: a AND b returns 1 only when both a=1 and b=1

+ is logical OR: a OR b returns 1 if either (or both) a=1 or b=1 ’ is logical NOT: NOT a returns the opposite of a (1 if a=0, 0 if a=1)

Verilog Logic and Arithmetic Operators DESCRIPTION Addition Subtraction Multiplication Logical right shif Logical lef shif Greater than Less than Greater than or equal to Less than or equal to Equality Inequality Equal to Bitwise AND Bitwise OR Bitwise XOR Bitwise NOT

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OPERATOR SYMBOL + * >> << > < >= <= == != = & | ^ ~

YILDIRIM BEYAZIT UNIVERSITY Verilog Operator precedence Operator !, +, * >>, << <, <=, >, >=, ==, != &, |, ^

Precedence Highest

lowest

Axioms and Theorems of Boolean Algebra: • identity

1. X + 0 = X

1D. X • 1 = X

• null

2. X + 1 = 1

2D. X • 0 = 0

• idempotency

3. X + X = X

3D. X • X = X

• involution

4. (X’)’ = X

• complementarity

5. X + X’ = 1

5D. X • X’ = 0

• commutativity

6. X + Y = Y + X

6D. X • Y = Y • X

• associativity

7.( X + Y) + Z = X + ( Y + Z)

7D.( X • Y) • Z = X • ( Y • Z)

• distributivity

8. X • (Y + Z) = (X • Y) + (X • Z)

8D. X + (Y • Z) = (X + Y) • (X +Z)

• uniting

9. X • Y + X • Y’ = X

9D. (X + Y) • (X + Y’) = X

• absorption

10. X + X • Y = X

10D. X • (X + Y) = X

11. (X + Y’) • Y = X • Y

11D. (X • Y’) + Y = X + Y

• factoring • concensus

12. (X + Y) • (X’ + Z) = X • Z + X’ • Y

12D. X • Y + X’ • Z = (X + Z) • (X’ + Y)

13. (X • Y) + (Y • Z) + (X’ • Z) =X • Y + X’ • Z 13D. (X + Y) • (Y + Z) • (X’ + Z) =(X + Y) • (X’ + Z)

• de Morgan’s

14. (X + Y + ...)’ = X’ • Y’ • ...

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14D. (X • Y • ...)’ = X’ + Y’ +

YILDIRIM BEYAZIT UNIVERSITY Xilinx ISE Design Suit Tutorial: Follow the below steps to create your first project in Xilinx. The module creation and testbench simulations will be done for logic NOT gate.

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Double click on ISE Design Suite 14.7 icon or shortcut.

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From file menu click on New Project.

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Name your project and click next. Be careful not to choose a read only directory as your project workspace.

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Enter below settings and click on next. (these are set for the BASYS2 card we will use in coming labs)

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Here the process so far is summarized. Simply click on Finish.

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Now a new empty project is created. Right click on Hierarchy panel then on the submenu click on New Source.

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On New Source Wizardpanel select Verilog Module and name your file then click on Next.

You can skip next 2 windows by clicking on Next then Finish.

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Now the new source file is added under the project.

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Write the Verilog codes for NOT gate as shown below.

Here the input and output variables are written inside the parenthesis right next to the module name (line1). Then they are identified as inputs or outputs; obviously for our case “a” is the input whereas “b” is the output of NOT gate (lines3&4). After the input and output variables are defined, the assignment is set using the assign command and logic operators (line6). Here b should be the inverse of a, hence =~ (equals logic NOT of) is used. You can always refer to the table on page1 for more logic operators.

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Then on the Processes panel expand the Synthesize-XST tab and double click on Check Syntax. This will check the syntax of your code. Should there be no such errors it should have a green check mark next to it.

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Now we will add test bench simulation. To do so, right click on Hierarchy panel and click New Source. This time select Verilog Test Fixture, name the file and click on Next. Then skip next 2 windows clicking on Next and Finish.

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In order to see the testbench, select Simulation on View pane (atop of Hierarchy panel).

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You can see the new testbench module is created. We will use this testbench module to simulate the NOT gate module we have created previously.

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Write the code shown below and double click on Behavioral Check Syntax. (save the changes if asked)

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YILDIRIM BEYAZIT UNIVERSITY First of all, register and wires are created (lines4&5). The variable which will have a changing value (usually the input variable) is created as register, reg. The variable whose value is defined as a result of other variables is created as wire.

Then notgatemodule is called with a user defined nameuut (line7).Here, inside the parenthesis input and output ports of notgatemodule are connected. ( .a(a),.b(b) ) “.a” is the register created in testbench (reg a) and the “(a)” is the input port of notgate module. Same applies to “.b” and “(b)”.

After these, initial process is called (line8-18).Inside this process register a value is changed after some time delays. Time delay is defined with # character. For example #10 means 10ns delay.

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After syntax is checked, double click on Simulate Behavioral Model.

When the simulation finishes a new ISim window will open with the input and output waveforms.

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Click on Zoom to Full View then select and drag the yellow cursor to where the changes happen. Now click on Zoom In.

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As you can see the input and output waveforms are generated with respect to input output relations described in notgatemodule and the variable assignments defined in testbenchNOTGATE_tb.

Behavioral vs. Structural Deisgn in Verilog: Please study the following link for a detailed explanation on differences between structural and behavioral design in Verilog: http://www.verilogtutorial.info/chapter_2.htm

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