Heavy ion induced single event latchup Allen et al nsrec 2016

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Heavy Ion Induced Single-Event Latchup Screening of Integrated Circuits Using Commercial Off-the-Shelf Evaluation Boards Gregory R. Allen, Member, IEEE, Farokh Irom, Leif Scheick, Member, IEEE, Sergeh Vartanian, and Michael O’Connor Abstract— We present heavy ion single-event latchup (SEL) screening data for a variety of commercial-off-the-shelf (COTS) devices intended for use on low-cost missions, and discuss the device preparation techniques used to expose the die for groundbased heavy-ion testing.

Index Terms— commercial-off-the-shelf, single-event latchup, heavy ions.

T

I. INTRODUCTION

HE use of state-of-the-art commercial integrated circuits (IC) in space systems is highly desirable as they can lead to significant improvement in system performance and capability.

Additionally, there has been a shift in NASA and the aerospace community to develop CubeSat missions that often see the use of commercial off-the-shelf (COTS) components for their electronics. CubeSats often have limited budgets and tight schedules, and therefore the mission assurance requirements and test budgets scale accordingly.

While mission assurance requirements are evolving for miniaturized satellites, one approach is to focus limited radiation test budgets on the most at-risk components along with devices that could end the mission if a failure occurred.

Even though only a fraction of the devices go through groundbased testing compared to larger, more expensive missions, budgets are still tight and that has required a new approach to single-event effects (SEE) test development. This is especially true of single-event latchup (SEL) screening; the primary topic of this paper.

II. DEVICES TESTED A. Texas Instruments TPS54226 The TPS54226 is a synchronous buck converter. that enables system designers to complete the suite of various end Some of the work described herein was performed by the Jet Propulsion Laboratory, California Institute of Technology under contract with the National Aeronautics and Space Administration (NASA) with funding from the NASA Electronics Parts Program (NEPP) and NASA ESR&T. The research was carried out at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration © 2016. California Institute of Technology. Government sponsorship acknowledged.

G. R. Allen is with the Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA 91109 USA (telephone: 818-353-7558; fax: 818393-4559; e-mail: Gregory.r.allen@jpl.nasa.gov

equipment’s power bus regulators with a cost effective, low component count, low standby current solution. The TPS54226 also has a proprietary circuit that enables the device to adapt to both low equivalent series resistance (ESR) output capacitors, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V VCC input, and from 2-V to 18-V VIN input power supply voltage. The output voltage can be programmed between 0.76 V and 5.5 V. The device also features an adjustable slow start time and a power good function. The TPS54226 is available in the 14 pin HTSSOP or 16 pin QFN package, and designed to operate from –40°C to 85°C [1].

B. Linear Technology LT3845 The LT3845 is a high-voltage, synchronous, current mode controller used for medium to high power, high efficiency supplies. It offers a wide 4V to 60V input range (7.5V minimum start-up voltage). An onboard regulator simplifies the biasing requirements by providing IC power directly from VIN. Additional features include adjustable fixed operating frequency that can be synchronized to an external clock for noise sensitive applications, gate drivers capable of driving large N-channel MOSFETs, a precision under-voltage lockout, 10μA shutdown current, short-circuit protection and a programmable soft-start. The LT3845 is available in a 16-lead thermally enhanced TSSOP package and 16-pin through hole N package [2].

C. Linear Technology LTC3129 The LTC3129 is a high efficiency, 200mA buck-boost DC/DC converter with a wide VIN and VOUT range. It includes an accurate RUN pin threshold to allow predictable regulator turnon and a maximum power point control capability that ensures maximum power extraction from non-ideal power sources such as photovoltaic panels.

F. Irom is with the Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA 91109 USA (telephone: 818-353-7558; fax: 818393-4559; e-mail: firom@jpl.nasa.gov L. Z. Scheick is with the Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA 91109 USA (telephone: 818-354-3273 fax: 818393-4559; e-mail: Lief.Z.Scheick@jpl.nasa.gov S. Vartanian is with the Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA 91109 USA (telephone: 818-354-0311; fax: 818393-4559; e-mail: Sergeh.Vartanian@jpl.nasa.gov M. O’Connor is with the Jet Propulsion Laboratory / California Institute of Technology, Pasadena, CA 91109 USA (telephone: 818-354-5595; fax: 818393-4459; e-mail: Michael.D.Oconnor@jpl.nasa.gov

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The LTC3129 employs an ultralow noise, 1.2MHz PWM switching architecture that minimizes solution footprint by allowing the use of tiny, low profile inductors and ceramic capacitors. Built-in loop compensation and soft-start simplify the design. For high efficiency operation at light loads, automatic Burst Mode operation can be selected, reducing the quiescent current to just 1.3μA. Additional features include a power good output, less than 10nA of shutdown current and thermal shutdown. The LTC3129 is available in thermally enhanced 3mm × 3mm QFN and 16-lead MSOP packages [3].

families. Each sub-family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built- in systemlevel blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGA-based systems. The devices are built on a 40 nm stateof-the-art copper process technology [7].

III. EVALUATION BOARD PREPARATION FOR HEAVY ION SINGLE-EVENT LATCHUP Single-event effects test development costs can often be significantly cut through the use of evaluation boards; however, there are challenges that must be addressed. The first area of concern is the correct biasing of the DUT. For an SEL test, monitoring the supply current to the DUT is important. Power to the DUT must be directly applied without the interference of voltage regulators, current limiting resistors, etc. One must understand the bias conditions the board was designed for, and if that design can handle the test requirements, namely bias voltage and elevated temperature. Perhaps the most difficult challenge is exposing the die without damaging the DUT or board. Nearly all COTS are packaged in one plastic package or another. Plastic de-capsulation is not new, but has become more challenging as packages have gotten smaller and smaller. A common method for de-capsulating plastic IC’s is to use a machine such as Niscene Technolgy JetEtch or a manual method to eat away at the plastic using a combination of temperature and fuming nitric/fuming sulfuric acids. Typically, this is performed at the component level, i.e. a stand-alone device not already soldered to a printed circuit board (PCB).

The remainder of this section will describe various approaches to achieve part preparation using the tested devices as examples.

D. Texas Instruments TPS562209 The TPS562209 is a simple, easy-to- use, 2-A and 3-A synchronous step-down converters in 6 pin SOT-23 package.

The device is optimized to operate with minimum external component counts and also optimized to achieve low standby current. TPS562209 always operates in continuous conduction mode, which reduces the output ripple voltage in light load compared to discontinuous conduction mode. TPS562209 is available in a 6-pin 1.6 × 2.9(mm) SOT (DDC) package, and specified from –40°C to 150°C of junction temperature [4].

E. Analog Devices ADA4091 The ADA4091-2 dual and ADA4091-4 quad are micropower, single-supply, 1.2 MHz bandwidth amplifiers featuring rail-to- rail inputs and outputs. They are guaranteed to operate from a +3.0V to +30V single supply as well as from ±1.5V to ±15V dual supplies. Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo-electric, and resistive transducers.

The ability to swing rail-to-rail at both the input and output enables designers, for example, to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios (SNR) [5].

A. Standard Approach-TPS54226 The TPS54226 provides an example of a fairly large, plastic HTSSOP package. We typically can achieve a high decapsulation yield for packages of this type if the solder can easily be reflowed. In such cases, we remove the part and replace it with a part that was decasulated,. Alternatively, we might attempt to decapsulate the part in situ on a test board. Fig. 1 shows the TPS54226 device evaluation board in an HTSSOP. In this instance, the entire board is heated on a hot plate along with pure 90% fuming nitric. Once both the acid and DUT are at temperature, an eyedropper is used to place a few drops of acid on the surface of the plastic part. If the part is large enough, there is typically enough surface tension in the acid/plastic reaction to avoid the acid spilling over to the PCB, which would corrode and destroy the copper in the board. In the event that the device is corrupted, it is fairly easy to replace, either with an encapsulated device or an already etched one. The rinse process is the standard approach of acetone, water, followed by isopropyl, and an oven bake at 85 degrees Celsius.

F. Altera MAX10 Altera’s MAX10 FPGAs provide advanced processing capabilities in a low-cost, single chip small form factor programmable logic device. Building upon the single chip heritage of previous MAX device families, densities range from 2K – 50K logic elements, using either single or dual-core voltage supplies. MAX10 FPGAs are built on TSMC’s 55 nm embedded NOR flash technology, enabling instant-on functionality. Integrated features include analog-to-digital converters (ADCs) and dual configuration flash allowing you to store and dynamically switch between two images on a single chip. Unlike CPLDs, MAX 10 FPGAs also include fullfeatured FPGA capabilities, such as Nios® II soft core embedded processor support, digital signal processing (DSP) blocks, and soft DDR3 memory controllers.

G. Xilinx Virtex-6 Virtex®-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. The Virtex-6 family contains multiple distinct sub-families. This overview covers the devices in the LXT, SXT, and HXT sub-

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after the wet etch. Gonzales suggested a maskant by Dymax, part number BT-730. If access to the board is required, Gonzales’ approach should be considered.

For a QFN device that is not available on an evaluation boards, we find that breakout boards, such as the one depicted in Fig. 3, are extremely useful for fast and low-cost prototyping of test devices. The part can be mounted to the breakout card and etched in place using the method discussed above in section III-B. The 100mil spacing of the breakout card’s pins enables development of quick prototyping boards.

Fig. 1. Exposed TPS54226 die on the evaluation board.

B. Small QFN Packages-LTC3129 As packages get smaller, there is not enough surface area on the plastic package to contain the acid and prevent it from spilling over to the PCB. In such cases, one can remove the part to etch it, or attempt to etch it on the board with mitigation. With packages such as the LTC3129 QFN, often if the part is decapsulated, the package is often too degraded to reflow back onto the evaluation board. One method to prevent acid from spilling over is to surround the DUT with general-purpose epoxy. See Figure 2. This protects the integrity of both the package and the PCB. One must be careful not to pile the epoxy too high, especially if angular measurements are to be performed.

Fig. 3. 24 pin QFN device mounted to breakout card prior to etching. The device is etched on the card to maintain package integrity.

Fig. 2. LTC3129 evaluation board with exposed die and epoxy protecting the PCB.

C. Copper or Silver Bond Wires-MAX10 FPGA Devices with copper or silver bond wires are susceptible to acid at elevated temperature unlike gold wires. We find that the most reliable de-capsulation method is to use a proprietary process such as the JetEtch Pro CuProtect [9]. While other vendors sell similar products, we have access to this particular unit and have had good success with it. In such cases, where a machine must be used, either the part must be removed and reflowed, or the board must be fitted into the machine.

The CuProtect ™ applies a bias to the acid solution that leads to bonding of charged sulfate ions to the copper wire. This provides a temporary, removable protective layer for the wire.

Consequently, one should not rinse the DUT until the very end, i.e. when the desired encapsulant has been removed. Rinsing the part prematurely would destroy the protection afforded by the sulfate ions [10]. Once the desired encapsulant has been etched, the standard rinse and bake described in III.A should be applied.

Etching at lower temperatures also increases reliability, we typically use 35-40 degrees Celsius.

Another option that has yet to be explored by the authors of this paper was outlined in [8] by M. Gonzales et al. The authors of that paper suggested a UV/light curable maskant that cures very quickly, but is trimmable and can be pealed

Because the CuProtect ™ process is less controlled than the manual approach, care must be taken to protect the PCB. One approach is to cover the area surrounding the DUT with Kapton Tape, then cut a hole over the area to be etched and proceed

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with typical gasket coverage as described in Section III-A. Waxes and silicone compounds (e.g vacuum grease) can also help eliminate damage to the board from fumes and escaped acid. Of course, the aforementioned maskant technique can be applied if the part is small, or other board components prevent reliable gasket coverage.

Fig. 5. TPS562209 evaluation board with backside thinned, dead-bugged DUT.

E. Large, Flip-Chip-Xilinx Virtex-6 Flip-chip devices such as the Xilinx Virtex-6 require backside thinning to allow ion penetration to the active region of the device. This particular device’s substrate is 31mil thick (~787um). For test purposes, removing approximately 700um is desired. In the event that evaluation boards are being used for testing, as in this case, we typically thin the substrate of the part while it is on the board (Fig. 6), as opposed to buying the board, a spare part and thinning it, and reflowing the thinned device.

This approach reduces time, cost, and increases reliability.

Fig. 4. Altera MAX10 evaluation board with exposed die. The bond wires were copper in this instance, and as such the plastic was exposed at low temperature using Nisene’s CuProtect. Simple taping was used in addition to the rubber gasket to protect the evaluation board.

A popular technique that is becoming more prevalent in the failure analysis world is combining laser ablation and wet etch [11]. The technique uses a programmable (energy, wavelength, and location) laser to etch the majority of the encapsulant, followed by minimal wet etch. This technique minimizes the amount of time and volume of acid required to expose the die, and therefore the amount of potential damage to the bond wires.

It should be noted that this technique is under study and some groups have observed electrical damage to the DUT [12].

Furthermore, extra care should be taken to inspect Cu or Ag bond wires post-etch. Even if the device is functional, inspection is important because degradation such as thinning, pitting, and/or bond pad corrosion may have occured. While the DUT may be functional on the bench-top, it may no longer be able to handle the same current flow. Degraded wires could lead to erroneous test results. For example, a single-event functional interrupt could initiate an elevated current state that the degraded bond wire can’t sustain. In this case, the SEFI may be mistakenly be classified as a destructive single-event effect.

Fig. 6. Xilinx Virtex-6 evaluation board mounted on the ASAP-1 backsidemilling machine.

D. Non-standard Device Packaging-TPS562209 The TPS562209 was packaged with a partial lead-frame over the die; therefore, backside irradiation was the only option. One device was sacrificed and cross-sectioned. The silicon substrate was measured to be approximately 250um thick, and a mill was used to remove 200um of silicon and the DUT was deadbugged to the evaluation board with epoxy and wired to the original footprint, as shown in Figure 5.

However, with larger die such as this device, and with the semiconductor industry moving more and more towards printed circuit board-based substrate packaging, curved and warped die have become more and more common. Center-to-edge warpage of 20um is quite common, where values of hundreds of microns have also been observed [13]. The issue occurs when there are thermal expansion mismatches between different materials in the package, e.g. the PCB substrate, silicon die, underfill material, etc.

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The failure analysis community has been addressing this issue from a reliability perspective. Backside thinning of a warped die can lead to a sudden relaxation of pressure which can cause die cracking. To solve this problem, several companies have developed tools such as thermal stages, which relax the die, and three dimensional software that uniformly thin the substrate.

When thinning a warped die, both die thickness and uniformity must be considered. Typically, devices are thinned down to around 60um to 80um of remaining silicon for heavy ion testing using the 15MeV/amu beam at Texas A&M cyclotron or the 16MeV/amu cocktail at Lawrence Berkeley National Laboratory where many ion ranges are on the order of 100um.

Before beginning the actual thinning process, one must know starting die thickness. Some manufacturers will provide nominal thickness values, but these often have a tolerance of up to 2%. For example, a die thickness measurement provided for this part had a tolerance of +/-13um. Another option is to crosssection a sacrificial device prior to, or the actual DUT after testing. This is of course destructive and potentially costly. The third option is to use interferometric or other light-based measurement techniques outlined later on in this section.

Fig. 7. F3-XXT software screen-shot depicting thinned substrate thickness and uniformity.

If die warpage is ignored, and the part thinned in a planar manner, the center of the die will be thinned to the assumed value of 80um, but the edge of the die will be very thick, potentially 35um-40um thicker than the center. This thickness would stop the particles from penetrating to the active region of the outer regions of the DUT. However, the experimenter may incorrectly assume uniform ion penetration and sufficient range due to observed SEE effects from the thinner center region.

This is of particular concern when dealing with larger input/output buffers that operate at higher voltages and may be more sensitive to SEL relative to the lower voltage memory cells or storage elements in the core of the device.

Fig. 8. F3-XXT software screen-shot depicting thinned substrate thickness and uniformity with graphical 3D representation.

One solution we have found to address these issues is to introduce an interferometric substrate thickness measurement tool such as the F3-XXT [14]. The tool and associated software will provide initial thickness measurements, post thinning thickness and uniformity. An example is shown in Fig. 7-8 below. This data shown in Fig. 7-8 is from a similar FPGA tested in [15].

IV. FACILITY AND TEST CONDITIONS Heavy ion experiments were performed at Texas A&M University cyclotron [16]. Exposures were conducted with the ion species shown in Table 1. Generally speaking, tests were performed in accordance with JESD57 [17]. Particle fluence per exposure was typically 1x107cm-2 with a flux adjusted for the observed event rate, nominally between 1x103 cm-2s-1 to 1x105 cm-2s-1. In the cases where the DUTs were heated, a heat gun or thermal resistive strips were used in conjunction with a pair of thermocouples. Bias was supplied to the DUTs with HP6629A power supplies and monitored and controlled with custom Visual Basic software that includes SEL detection.

Ion Au Ta Ag Cu Ar Kr

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Energy (MeV) 2954 2714 1634 944 599 2081

TABLE I BEAM PARAMETERS Initial LET in Si Range to Bragg Peak in Si (Vaccum) (um) 2 (MeV-cm /mg) 80.2 102 72.2 109 38.5 130 17.8 156 7.7 220 19.9 484

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F. Altera MAX10 The first ion selected for the experiment was Gold (Au) at 15 MeV/n with the starting LET of 85.4 MeV-cm2/mg at normal incidence. The DUT was biased at nominal voltage 3.3V, and tested both at room and elevated temperature. SEL was observed on the 3.3V supply VCCA, which supplies the PLL regulator and ADC block.

Both device types, VCC_ONE and the standard MAX10, were tested for both temperature conditions and observed to have exhibit SEL at approximately the same cross-section across all tested LET. As an aside, we observed that when the devices were held in an un-configured state, i.e. the program pin was asserted, SEL was not observed. This indicates the ADC and PLL are unpowered during this un-configured state. Also of note, when the power supply current clamps were removed (opened to 2A), the SEL events maintained about a 1.1A latched state until power cycled. SEL cross-section vs. effective LET is plotted below along with Weibull fits and parameters below in Fig. 9.

V. TEST RESULTS In general, the limited budget associated with the testing dictated an SEL screen only, as opposed to full characterization.

Also, we use the term “destructive” in the present discussion to indicate that the first SEL event destroyed the device in spite of current limiting or relatively fast software-initiated power cycling. The reader should be cautioned that even if the SEL event was not immediately destructive latent damage can significantly impact part reliability, and we have performed no latent damage investigations on the present set of devices A. Texas Instruments TPS54226 The TPS54226 was tested at both elevated and room temperature for a variety of input voltages. As the test was a SEL screen, all testing was performed with Texas’ 15MeV/amu Tantalum (Ta) beam. The normal incident LET was 77.4 MeVcm2/mg at the surface of the part. At room temperature, no SEL was observed for VCC=10V, but destructive SEL occurred at VCC=12V. When the device was heated to 80°C, destructive SEL was observed at 10V. When VCC was lowered to 8V at 80°C, no SEL was observed.

B. Linear Technology LT3845 The LT3845 is built on bipolar technology, and as such SEL was not expected. We did, however, observe self-recovering transient current spikes on VCC, and eventually a destructive event. Testing was performed at an incident LET of 77.4 with Texas’ 15MeV/AMU Ta beam. The destructive event only occurs when the supply voltage is greater than 40V. We speculate that this is likely single event dielectric rupture (SEDR).

C. Linear Technology LTC3129 The LTC3129 was tested at room temperature for a variety of input voltages. As the test was a SEL screen, all testing was performed with 15MeV/amu Tantalum (Ta) beam at Texas A&M. The normal incident LET was 77.4 MeV-cm2/mg at the surface of the part. At room temperature, and the lowest operational VCC, 2.42V, destructive SEL was observed.

Fig. 9. Altera MAX10 SEL cross-section vs. LET for both tested temperatures.

G. Xilinx Virtex-6 The Xilinx Virtex-6 was tested for Single Event Effect (SEE)-induced latchup events at the Texas A&M Cyclotron Institute in September of 2014. A 25 MeV/amu Kr ion beam was used to deliver an effective Linear Energy Transfer (LET) of 37 MeV-cm2/mg to a fluence greater than 1x107 particles/cm2. There were no latchup events recorded for the XC6VLX240T-FFG1156; the same SEL response is expected for any of the other devices in this family. Table II provides a summary of the test parameters for the latchup irradiations.

Each DUT was heated to a nominal pretest temperature of +80°C and biased with specification-maximum voltages.

D. Texas Instruments TPS562209 The TPS562209 was tested at both elevated and room temperature for a variety of input voltages. As the test was a SEL screen, all testing was performed with a high LET. We used 15MeV/amu Tantalum (Ta) at Texas A&M, which has an incident LET of 77.4 MeV-cm2/mg. At room temperature, destructive SEL was observed for VCC=10V. When the device was heated to 80°C, no SEL was observed at VCC=8V, but of course still occurred at 10V. E. Analog Devices ADA4091 The ADA4091 was tested at both elevated and room temperature for a variety of input voltages. As the test was a SEL screen, all testing was performed with a high LET. We used 15 MeV/amu Tantalum (Ta) at Texas A&M, which has an incident LET of 77.4 MeV-cm2/mg. No SEL was observed at an input voltage of 36V and an elevated temperature of 60°C.

TABLE II DUT SEL TEST CONDITIONS FOR XILINX VIRTEX 6 Parameter Value Unit Initial DUT junction temperature Internal core voltage Auxiliary voltage I/O Voltage 2.5 I/O Voltage 1.5

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+80 1.05 2.625 2.625 1.575

°C V V V V

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[16] ‘Cyclotron Institute Texas A&M University,’ [Online]. Available: http://cyclotron.tamu.edu. . [Accessed: 30- Jun- 2016].

[17] JEDEC JESD57, “Test Procedure for the Management of Single-Event Effects in Semiconductor Devices from Heavy Ion Irradiation (JC 13.4),” EIA/JEDEC, 2500 Wilson Blvd., Arlington, VA 22201-3834.

H. Test Result Summary Table III below provides a summary of the above test results.

TABLE III SUMMARY OF TEST RESULTS Device TPS54226 LT3845 LTC3129 TPS562209 ADA4091 MAX10 Virtex-6

Test Results SEL LETTH < 77.4 MeV-cm2/mg @VCC=12V & 20°C SEL LETTH < 77.4 MeV-cm2/mg @VCC=10V & 80°C SEL LETTH > 77.4 MeV-cm2/mg @VCC=10V & 20°C SEDR* < 77.4 MeV-cm2/mg @VCC=40V & 20°C SEDR* < 77.4 MeV-cm2/mg @VCC=30V & 20°C SEL LETTH < 77.4 MeV-cm2/mg @VCC=2.42V & 20°C SEL LETTH < 77.4 MeV-cm2/mg @VCC=10V & 20°C SEL LETTH > 77.4 MeV-cm2/mg @VCC=8V & 80°C SEL LETTH > 77.4 MeV-cm2/mg @VCC=36V & 60°C SEL LETTH < 42.2 MeV-cm2/mg @ Nominal Conditions SEL LETTH > 77.4 MeV-cm2/mg @Max. Spec. Bias and 80°C

*Assumed effect, more testing to be done to verify.

[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]

[12]

[13]

[14] [15]

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‘A Straightforward Guide to the Sample Preparation of Curved & Warped IC’s,’ [Online].

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