ISTFA 2011, Proceedings from the 37th International Symposium for Testing and Failure Analysis, November 13-17, 2011 San Jose, CA, USA
Copyright © 2011 ASM International®. All rights reserved. www.asminternational.org
Failure Analysis of Flip Chip C4 Package Using Focused Ion Beam Milling Technique Lihong Cao, Loc Tran, Wallace Donna Advanced Micro Devices, Inc Austin, Texas, USA Lihong.cao@amd.com, Tel: 512-602-4272
Abstract
Experiment
This article describes how Focused Ion Beam (FIB) milling methodology enhances the capability of package-level failure analysis on flip-chip packages by eliminating the artifacts induced by using conventional mechanical techniques. DualBeam Focused Ion Beam (DB FIB) cross sections were successful in detecting failure mechanisms related either to the die/C4 bump or package defect inside the organic substrate. This paper outlines detailed sample preparation techniques prior to performing the DB FIB cross-sections, along with case studies of DB FIB cross-sections.
1. Fault isolation technique for package failure analysis The electrical characterization by using a parametric analyzer is the first step of the fault isolation. Time Domain Reflectometry (TDR) has been successfully used to isolate Open/Short package-level failures by generating a step signal which is transmitted through the device under test (DUT) [6]. When a discontinuity in the DUT is encountered, a part of the transmitted signal is reflected. In this paper, a comparative TDR method is used to quickly determine whether an Open/Short failure is within the package or within the silicon. The impedance profile of a failing signal is compared to the impedance profile of a “golden” unit and a bare package (without die attachment). Another non-destructive technique used to detect package level failures is C-Mode Scanning Acoustic Microscopy (CSAM). CSAM is widely used in flipchip devices to evaluate the chip-to-bump interface, the solder joint through the entire thickness of the solder ball, and the solder-to-substrate interface. In this work, CSAM with a 230MHz high frequency transducer is selected to perform scanning on the samples to identify the failure.
Introduction IC packages are becoming increasingly complex due to the increasing size, I/O numbers, and application of lead-free solder bumps [1, 2]. Package level reliability and failure analysis has become an area of more concern and challenge. Effectively detecting failure mechanisms has become very critical. Conventional mechanical cross-section technique is the most common methodology to determine failure modes in the semiconductor industry. However, the typical problem of mechanical cross-sections is the smearing of the soft material into the cracks and delamination, as well as easily inducing artifacts. Thus, it is difficult to determine failure mechanisms.
2. Dual Beam FIB-SEM milling and imaging system Focused ion beam milling can provide detailed and specific information about structures without inducing artifacts by precisely monitoring the beam etch patterning and the area of exposure. FIB systems generally use a Gallium Liquid Metal Ion Source (Ga-LMIS) as the source of the ions, providing a typical beam current range of 1 pA to 20-60 nA [7]. In this study two systems are used; one is a FEI Strada400 with a maximum beam current of 21nA and another is the upgraded Strada400 with a maximum beam current of 65nA. The effect of beam current was studied.
Focused ion beam milling technology is widely used in the semiconductor industry for the purposes of circuit edit, fault isolation, Si- level cross-sectioning, Transmission Electron Microscope (TEM) analysis preparation, and material ablation [3, 4, 5]. By precisely monitoring the beam etch patterning and the area of exposure, very detailed characteristics of the failing structure, such as manufacturing defects, can be detected without inducing any artifacts. Instead of using FIB for Si-level analysis, this paper presents the DB FIB technique to perform package level cross-sections on flip chip packages to determine the failure mechanisms. The detailed process with high precision and artifact free access to the defective buried interconnection and microstructure is also discussed in this paper.
3. Sample preparation The samples in this study are flip chip Organic Pin Grid Array (OPGA) packages and the Si device is Silicon On Insulator (SOI). The Si die with a thickness of 750um is attached to an organic substrate with a thickness of 1.4mm through lead free solder bumps. In order to find the root cause of package failure, an extensive sample preparation is needed to expose
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