Automated backside polishing bonniegannon5 08

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Backside Polishing Technique

Automated Backside Silicon Polishing for Die Encapsulated in a Package Bonnie Gannon, IBM Systems and Technology Group, Essex Junction, Vt. blgannon@us.ibm.com

Introduction With the growing complexity of new processes and packaging material, the need for automated backside silicon polishing for integrated circuits (ICs) is necessary. The ability to achieve successful polishing results in cases where ICs are mounted on ceramic or laminate material is not as difficult because the ICs are above the substrate. For ICs encapsulated inside packaging material, it is more challenging to obtain a scratch-free silicon surface.

procedure is followed with 30, 15, 6, 3, and finally 1 μm diamond paste steps. This process could possibly take 2 to 3 h to complete.

There are many inherent problems with this process.

It can be rather difficult to master the technique of pressing hard enough on the silicon surface to remove the scratches and, at the same time, pressing gently enough so as not to cause uneven surface topography.

There are a variety of tools to perform fault localization tests for microelectronics failure analysis. These techniques often require the silicon to be thinned and optically polished to acquire unobstructed signals from the circuits from the backside. The previous method required an operator to hand polish the ICs for testing. A newly improved automated process for polishing the surface of the silicon offers many advantages.

Previous Sample Preparation Method

Fig. 1

Surface topography line scan results

Fig. 2

Edge scratches after hand polishing

When it has been determined that a particular sample has a defect, the lid or packaging material is removed above the silicon using a high-precision milling tool with an end mill. The epoxy is then scraped off the silicon with a razor blade to expose the backside surface. The IC is thinned to the appropriate thickness with a diamond bit, which leaves a silicon surface roughness of approximately 1200 nm (Fig. 1).

The sample is removed from the tool, and hand polishing begins. A cotton tip is inserted into a rotary tool to facilitate the application of a variety of diamond pastes to attain a smooth surface. Typically, a 45 μm paste is applied with a lubricant until the scratches from the diamond bit have been removed. This

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Electronic Device Failure Analysis

Quite often, by the time the surface is optically prepared for fault localization testing, there are valleys and hills created by this tedious process.

Secondly, it is very difficult to polish the scratches out of the corners of the die, because the cotton tip comes in contact with the packaging material (Fig. 2).

This creates problems when trying to gather signals from the circuit during testing if the fault area was near the corners of the IC. Thirdly, sometimes the scratches are hard to remove.

The operator needs to continue polishing (thinning) the surface with a particular paste before switching to the next smaller micron paste, which can cause too much silicon thinning. This makes it difficult to arrive at the desired optimal final thickness. This problem is also magnified because of the nonplanarity of the hills and valleys caused by this process.

Finally, the operator experiences strain and body fatigue from looking down toward the work surface and holding the rotary tool in the same position for long periods of time.

Automated Backside Silicon Polishing The sample is prepared again by using the milling tool to remove the packaging material and thin the silicon. There are a couple of steps to prepare the tool for polishing. A photo of the tool is seen in Fig. 3. The stage where the sample is placed needs to be leveled for planarity, and the X and Y coordinates for the die size must be calculated and applied. After this, the sample is mounted in a wax bed puck and measured to determine the sample planarity prior to polishing (Fig. 4). Final leveling can be completed after the puck is mounted on the stage.

There are four steps necessary to polish the sample.

A diamond bit is initially used to remove some of the surface roughness from the milling tool (Fig. 5).

This step is followed with a 15 μm polysilicon diamond paste for approximately 10 min (Fig. 6). Following the 15 μm polish, the same technique is used with a 3 μm paste and a colloidal silica final polish (Fig. 7, 8).

Fig. 3

Automated polishing tool

Fig. 5

After the sample is thinned with a diamond bit

Fig. 4

Closeup of the stage

Fig. 6

After the 15 μm polish

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Automated Backside Silicon Polishing for Die (continued)

Fig. 10 Removal rate for 15 and 3 μm polishing steps

Fig. 7

After the 3 μm polish

Fig. 11 Comparing removal differences from center to edge for 15 and 3 μm polishing steps

An atomic force microscope analysis was performed after the colloidal silica final polish. The silicon surface roughness was measured at approximately 0.3 nm (Fig. 9).

Experimental Results

Fig. 8

Colloidal silica polish

Multiple samples were cycled through the 15 and 3 μm paste steps to determine the average amount of silicon removed per step (Fig. 10). A few samples of the colloidal silica step were also completed; however, the amount of silicon removal was too minimal to measure.

The average amount of silicon removed for the 15 μm paste was 20 μm, while 10 μm was the average for the 3 μm cycle.

There is, however, an imperfection with this process that must be considered when polishing a sample on the tool: The edges of the sample polish faster than the center of the IC during the 15 and 3 μm cycles (Fig. 11).

Fig. 9

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Atomic force microscope results after polishing with the automated polishing tool

Electronic Device Failure Analysis

The average difference from center to edge measurement is approximately 10 μm for the 15 μm paste and 5 μm for the 3 μm paste. If the desired final thickness of silicon was less than 50 μm, a total difference of 15 μm between edge and center thickness could potentially cause a problem and destroy a sample. Figure 12 is an example of a part that was damaged due to overpolishing the edges compared to the (continued on page 10)

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Automated Backside Silicon Polishing for Die (continued) (continued from page 8)

Fig. 12 Silicon removed from the top and bottom of the polishing area

Fig. 14 Possible fault areas indicated by arrows at bottom of image

packaging material: • Planarity is improved and more predictable.

• The probability of arriving at the optimal final thickness is increased.

• Corner scratches are removed.

• The physical fatigue of the operator is eliminated.

In addition to these advantages, the operator production throughput is increased because the individual can work on other things while the tool is operating.

Acknowledgments Fig. 13 Acoustic microscopy results

center of the die. The silicon was very thin to begin with, and a small box was polished using the automated polishing tool. The top and bottom of the silicon were polished through to the bottom side of the circuit of the IC, which would destroy the ability to test the part.

A scanning acoustic microscope image was taken of a sample to ensure no cracks or die damage were induced by polishing (Fig. 13). The results were good.

Conclusion When a sample has been prepared successfully, it can be submitted to a fault isolation tool. The sample in Fig. 14 was submitted to the photon emission microscope, and a potential fault in the circuit was found.

There are multiple advantages to automating the silicon polishing process for die encapsulated in

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Electronic Device Failure Analysis

The author acknowledges Richard Ross, Jim Salimeno, David Vallett, Phil Kaszuba, Andrew Deering, and Greg Nuttall for their help and encouragement with experiments, tools, and article review.

About the Author Bonnie Gannon is a failure analyst in the Sample Preparation and Special Techniques Group at IBM in Vermont. She has 22 years of experience in the semiconductor industry, ranging from wafer fabrication and materials analysis to department supervisor. She has spent the past 12 years in failure analysis. Bonnie has extensive experience and knowledge in frontside and backside sample prep and has been involved in process development in these areas. She enjoys working with her team to develop new techniques to prepare ICs in packaging material for fault isolation testing.