2020 IWLPC Event Guide

2020 17th Annual

International Wafer-Level Packaging Conference & Exposition “Bridging the Boundaries: Wafer, Panel and Beyond” Live Virtual Exposition: October 13-14 On-Demand Conference & Expo: October 13-30

Event Guide Organized by

www.iwlpc.org

Supported by 1

October 13-30, 2020 | IWLPC Conference & Exposition

Welcome to the 17th Annual International Wafer-Level Packaging Conference IWLPC brings together the semiconductor industry’s most respected authorities addressing all aspects of Wafer-Level Packaging, 3D Integration and Advanced Manufacturing and Test.

General Chair

Chris Scanlan, JCET Group

Executive Team

Tanya Martin, SMTA Jaclyn Sarandrea, SMTA Lawrence Michaels, Chip Scale Review Kim Newman, Chip Scale Review

Wafer-Level Packaging Track

Saurabh N. Athavale, Ph.D., Western Digital, Chair Tom Strothmann, Besi North America, Inc., Co-Chair Jacinta Aman Lim, Nepes Tanja Braun, Ph.D., Fraunhofer IZM Burt Carpenter, NXP Semiconductors Takenori Fujiwara, Ph.D., Toray Industries, Inc. Timo Henttonen, Microsoft E. Jan Vardaman, TechSearch International, Inc.

3D Integration Track

John Lannon, Ph.D., Micross Advanced Interconnect Technology, Chair Thomas Gregorich, ZEISS Semiconductor Manufacturing Technology Zia Karim, Ph.D., Yield Engineering Systems Herb Reiter, eda 2 asic Consulting, Inc. Ted Tessier, Gordian Semiconductor Packaging Solutions

Advanced Manufacturing and Test Track

Garrett Oakes, EV Group, Chair Habib Hichri, Ph.D., Ajinomoto Fine-Techno USA Corporation, Co-Chair Keith Best, Onto Innovation Scott Jewler, SVXR, Inc. Ananthakrishnan Narayanan, Ph.D., Phononic, Inc.

Get to Know the Technical Committee Members >>

Join industry leaders, technologists and innovators for the 17th Annual International Wafer-Level Packaging Conference & Exhibition (IWLPC). The IWLPC is recognized as the premier semiconductor packaging conference and exposition focused on ad-vanced wafer-level packaging technology. This year’s conference theme, “Bridging the Boundaries: Wafer, Panel and Beyond” reflects the role of advanced waferlevel packaging in the enablement of 5G communications, AI, and IoT, automotive and more.

The IWLPC has always provided a dynamic environment for learning, networking and technical exchange and this year will be no different. Well, maybe a little different. The 2020 conference will be the first IWLPC to be held virtually. The conference committee has arranged for a high-quality virtual conference experience to deliver the technical content and to facilitate communication and networking. As in prior years, the conference comprises of three major parts: the technical program, the professional development courses, and the technology exposition. The technical program has three parallel tracks with over 40 presentations on waferlevel packaging, 3D integration, and advanced manufacturing and test technologies. This year the technical presentations will be available on demand from October 13 through October 30. A chat feature will enable attendees to interact with the speakers, exhibitors and other attendees.

The 2020 IWLPC will kick off with a keynote talk titled “Trends, Challenges, Opportunities in Advanced Packaging for Smart Computing Era” given by Dan Oh, Ph.D., Engineering VP of Test & System Package (TSP), Samsung Electronics. Dr. Oh’s speech will be broadcast live on Tuesday, October 13, 2020 at 9:00am US Pacific. In addition, Jan Vardaman of Techsearch will moderate a panel discussion entitled “Meeting Future Advanced Packaging Challenges: What’s Next?” This event will be live on Wednesday, October 14 at 9:00am US Pacific. Two professional development courses will also be offered. Finally, the technology exposition this year will feature many leading companies from across the advanced packaging supply chain. Attendees will be able to browse the virtual exhibition hall and engage in live chat sessions with the exhibitors. We look forward to seeing you this October in cyberspace. Let’s have another great IWLPC!

— Chris Scanlan, JCET IWLPC General Chair

October 13-30, 2020 | IWLPC Conference & Exposition

2

“Bridging the Boundaries: Wafer, Panel and Beyond�

WLP Track

Wafer-Level Package (WLP) is becoming a defacto choice for many applications. The recent advancements in WLP is making this package form a more adaptable and suitable package for automotive application as well, in addition to other applications. The WLP track is covering key technologies: Advanced WLP (SIP, Flex, Glass wafer), Reliability & Metrology, FO-WLP (High density RDL, Panel-level, FoWLP, Processes/ Material (Electroplating, warpage elimination, thermal laser separation).

3D Integration Track

Multi-functional or smart systems based on heterogeneous integration approaches are now driving the next wave of 3D integration innovation.

Some application examples include mixed signal analog/RF systems and high-performance sensors or imagers. Successful implementation of these approaches rely heavily on sound designs, reliable die/wafer bonding processes, improved interconnect fabrication processes, and related characterization and test techniques. The 3D integration track has been organized to cover each of these aspects of heterogeneous integration with session papers ranging from die-package-board co-design for 2.5/3D-ICs and WLP to innovations in panel plating and advanced lithography to novel temporary bond and de-bond solutions.

Advanced Manufacturing and Test Track

The Advanced Manufacturing and Test Track remains devoted to bringing together speakers to address key operational challenges in the diverse field of wafer-level packaging (WLP) and panel-level packaging (PLP). The speakers represent academia, equipment suppliers and device manufacturers and have recorded presentations on a variety of topics applicable to R&D phases through high-volume phases of device manufacturing. This track will feature solutions for silicon and glass, new and improved process materials, advances in testing methods, techniques for heterogeneous integration, and concepts for fan-out packaging. Streaming this track will allow tapping into the ideas, experiences and solutions of the speakers.

Exposition

While full exposition access will be available to attendees October 13-30, the real-time, virtual exposition will take place October 13-14, where the IWLPC will showcase various exhibiting companies; many which are the leaders in the semiconductor packaging and test industry. Attendees will be able to see the latest products and discuss a broad range of services in a virtual interactive environment.

The International Wafer-Level Packaging Conference has become one of the premier forums focused in three key technology areas: Wafer-Level Packaging, 3D Integration and Advanced Manufacturing and Test.

3

October 13-30, 2020 | IWLPC Conference & Exposition

Professional Development Courses Tuesday, October 27 | 8:30am-12:00pm (US Pacific)

Thursday, October 29 | 8:30am-12:00pm (US Pacific)

PDC 1

PDC 2

Polymers in Wafer-Level Packaging

From Wafer to Panel-Level Packaging

Jeff Gotro, Ph.D., Innocentrix, LLC

Tanja Braun, Ph.D., Fraunhofer IZM Michael Topper, Fraunhofer IZM

Overview The course will provide an overview of polymers and the important structure-property-process-performance relationships for polymers used in wafer-level packaging. The main learning objectives will be: 1) understand the types of polymers used in wafer-level packages, including underfills (pre-applied and wafer applied), mold compounds, and substrate materials 2) gain insights on how polymers are used in Fan Out Wafer-Level Packaging, specifically mold compounds and polymer redistribution layers (RDL) 3) learn the key polymer and processes challenges in Fan Out Wafer-Level Packaging 4) Understand the materials and process challenges for polymer used in panel-level packaging.

Overview Panel-Level Packaging (PLP) is one of the latest trends in microelectronics packing. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package also approach larger substrates formats. These are targeted in this course.

Manufacturing is currently done on wafer level up to 12�/300 mm and 330 mm respectively. For higher productivity and therewith lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, PLP might be the next big step. PLP has the opportunity to adapt processes, materials and equipment from other technology areas. Printed Circuit Board (PCB), Liquid Crystal Display (LCD) or solar equipment is manufactured on panel sizes and offer new approaches also for PLP. However, an easy upscaling of technology when moving from wafer to panel level is not possible.

Materials, equipment and processes have to be further developed or at least adapted. This course will give a status of the current Fan-in and Fan-out Wafer-Level Packaging as well as Panel-Level Packaging including Fan-out Panel-Level Packaging substrate embedding approaches. This will include materials discussion, technologies, applications and market trends as well as cost modelling.

Who Should Attend?

Packaging engineers involved in the development, production, and reliability testing of electronic packages would benefit. Those interested in gaining a basic understanding of the role of polymers and polymer-based materials used in electronic packaging will also find this PDC valuable.

Get to Know the Instructors >> October 13-30, 2020 | IWLPC Conference & Exposition

Who Should Attend?

Anyone who is interested in Advanced Packaging, Fan-in and Fan-out Wafer-Level Packaging and the transition to Panel-Level Packaging. Engineers and managers are welcome as detailed technology descriptions as well as market trends, applications and cost modelling are presented.

4

MultiPlate® for FOPLP Next generation plating tool

Next generation plating system and Innolyte® process family for panel level packaging

Fully automated handling under cleanroom conditions

20 A/dm² plating current density for Cu pillar plating

<7% panel distribution on full panel size RDL boards

<7% uniformity on RDL design

MultiPlate® is the next generation ECD tool that offers the versatility and multi-functionality necessary to tackle current and future challenges for optimal performance in advanced packaging technologies.

Redistribution layers (RDL) for next generation need fine line features of sub 5 μm lines and spaces without significant yield loss, and tall copper pillar (>100 μm) plating is requested without increasing the plating time. The new Innolyte® product family for electrolytic plating of RDL structures and pillars allows plating at highest current densities while achieving excellent uniformity of the plated structures.

Atotech Group +49 30 349850 info@atotech.com Global head office

atotech.com

5

October 13-30, 2020 | IWLPC Conference & Exposition

Keynote Presentation

Tuesday, October 13 | 9:00am (US Pacific) *On-Demand Playback Available

Trends, Challenges, Opportunities in Advanced Packaging for Smart Computing Era Dan Oh, Ph.D. Engineering VP of the Test & System Package (TSP) Samsung Electronics About the Speaker >> About the Presentation The AI-driven smart computing era pursues computer performance and reduced power consumption. Advanced packaging technology achieves these goals by integrating logic and memory chips at closer proximities.

This talk portrays how semiconductor technology has evolved from the system integration perspective, and then, it describes some of the future integration schemes which will provide yet another scaling path to modern Silicon-based IC technology. However, extreme integration technology scaling by combining package-level, wafer-level, and fab process-level integration technologies results in problems with high-power density.

To address the challenges in providing power and extracting dissipated heat from highly integrated systems, potential innovative solutions in signal, power, and thermal designs are also examined.

Live Panel Discussion

Wednesday, October 14 | 9:00am (US Pacific) *On-Demand Playback Available

Meeting Future Advanced Packaging Challenges: Whatâ&#x20AC;&#x2122;s Next?

Panel Moderator E. Jan Vardaman, TechSearch International, Inc.

As the industry moves into the next silicon nodes and enters the era of heterogeneous integration, packaging plays an increasingly important role.

Material selection, design, and fabrication of features, inspection, test, and reliability will be critical. The industry struggles with options to achieve highdensity substrate to support high-bandwidth memory (HBM) plus logic. New versions of FO-WLP are being adopted. The panel members will discuss views on the challenges and possible solutions.

October 13-30, 2020 | IWLPC Conference & Exposition

Panelists Tim Olson, DECA Tanja Braun, Ph.D., Fraunhofer IZM Rahul Manepalli, Ph.D., Intel Corporation Max Min, Ph.D., Samsung Foundry Shin-Puu Jeng, Ph.D., TSMC

6

Wafer-Level Packaging Track #170 #171 #172 #173 #174

600mm Wafer-Level Fan Out on Panel-Level Processing with 6-Sided Die Protection Jacinta Aman Lim, Nepes VIEW ABSTRACT

Low-Warpage Encapsulants for Wafer-Level Packaging Jay Chao, Ph.D., Henkel Corporation VIEW ABSTRACT

Design Process & Methodology for Achieving High-Volume Production Quality for FOWLP Packaging Keith Felton & John Ferguson, Mentor Graphics VIEW ABSTRACT

Development of Low Dielectric Loss Polymides and Fabrication of Advanced Packagings for 5G Applications Takenori Fujiwara, Ph.D., Toray Industries, Inc. VIEW ABSTRACT

High Resolution Dry-Film Photo Imageable Dielectric (PID) Material for FOWLP, FOPLP, and High Density Package Substrates Chihiro Funakoshi, TAIYO INK MFG. CO., LTD VIEW ABSTRACT

7

October 13-30, 2020 | IWLPC Conference & Exposition

Wafer-Level Packaging Track #175 #176 #177 #178 #179 #180

Advanced Preclean Chamber for UBM/RDL Contact Resistance Improvement in Advanced Node Packaging Application Clinton Goh, Applied Materials VIEW ABSTRACT

Advanced RDL Interposer PKG Technology for Heterogeneous Integration Jae-Gwon Jang, Samsung VIEW ABSTRACT

Fan-Out Wafer-Level Packaging Advanced Manufacturing Solution for Fan-Out WLP/PLP by DFD (Die Face Down) Compression Mold Yuichi Kajikawa, TOWA USA Corp.

VIEW ABSTRACT

Board Level Reliability of Automotive Grade WLCSP for Radar Applications Nishant Lakhera, Ph.D., NXP Semiconductors VIEW ABSTRACT

Maskless Lithography Optimized for Heterogeneous and Chiplet Integration Bozena Matuskova, EV Group VIEW ABSTRACT

Selective Copper Metallization for Advanced Packaging Rashid Mavliev, Ph.D., Ipgrip, Inc. VIEW ABSTRACT

October 13-30, 2020 | IWLPC Conference & Exposition

8

Wafer-Level Packaging Track

#181

Current Crowding and Stress Effects in WCSP Solder Interconnects: A Simulative and Practical Study about the Effects of Major Electromigration Failure Mechanisms in DC and Pulsed-DC Conditions Allison Osmanson, University of Texas at Arlington VIEW ABSTRACT

#182 #183

Physical Verification of Panel-Level Packaging Designs Utilizing Adaptive Patterning Technology Tarek Ramadan, Mentor Graphics VIEW ABSTRACT

Electrochemical Plating of Nano-Twinned Cu for WLP Applications Pingping Ye, Ph.D., MacDermid Alpha VIEW ABSTRACT

9

October 13-30, 2020 | IWLPC Conference & Exposition

Advanced Manufacturing and Test Track #210 #211 #212

Fluxless Soldering in Activated Hydrogen Atmosphere Gregory Arslanian, Air Products and Chemicals, Inc. VIEW ABSTRACT

New X-Ray Tubes for Wafer-Level Inspection Keith Bryant, Keith Bryant Consultancy VIEW ABSTRACT

Producing Planarized Uniform Layer in Advanced Photosensitive Polyimide Over Complex Geometry for Fan-Out PLP Applied with a Novel Nozzle-less Spray Coating Technology Stuart Erickson, Ultrasonic Systems, Inc. VIEW ABSTRACT

#213 #215 #216

Emerging Process and Assembly Challenges in Electronics Manufacturing Glenn Farris, Universal Instruments Corporation VIEW ABSTRACT

Force Measurement with Piezo Electric Sensors in Advanced Packaging Robert Hillinger, Kistler Instrumente AG VIEW ABSTRACT

Silicon Die Bonding using a Photostructurable Adhesive Material Kai Hollstein, Institute for Microelectronic Systems VIEW ABSTRACT

October 13-30, 2020 | IWLPC Conference & Exposition

10

Advanced Manufacturing and Test Track #217 #218 #219 #220 #221

Defect Printability for 2/2 RDL and the Impact of Advanced Reticle Processes Bryan Kasprowicz, Photronics VIEW ABSTRACT

Glass in Wafer and Panel-Level Packaging: Changes, Challenges, Hurdles and Barriers Martin Letz, Ph.D., SCHOTT AG VIEW ABSTRACT

Non-Surface Contact Approach for Device Flip Sarah Parrish, V-TEK, Inc. VIEW ABSTRACT

Optimizing X-Ray Inspection for Advanced Packaging Applications Brennan Peterson, Ph.D., SVXR, Inc. VIEW ABSTRACT

Handling of Different FOPLP Layouts on Large Area Thermal Chucks Debbie-Claire Sanchez, P.E., ERS electronic GmbH VIEW ABSTRACT

11

October 13-30, 2020 | IWLPC Conference & Exposition

Advanced Packaging Experts Get published in Chip Scale Review

Chip Scale Review accepts abstracts year-round.

Submit your 200-250 word abstract to editor@chipscalereview.com

The most comprehensive & reliable source for the global semiconductor packaging industry info@chipscalereview.com October 13-30, 2020 | IWLPC Conference & Exposition

12

www.chipscalereview.com

Advanced Manufacturing and Test Track

#222 #223 #224 #225

Bringing New Life to Glass for Wafer-Level Packaging Applications Rafael Santos, Ph.D., LPKF Laser & Electronics AG VIEW ABSTRACT

Novel Surface Finish for Next Generation Wafer-Level Packaging Applications Kunal Shah, Ph.D., LILOTREE VIEW ABSTRACT

Submicron Lithography Enabling Panel Based Heterogeneous Integration Doug Shelton, Canon USA VIEW ABSTRACT

Characterization of Formaldehyde-free Electro-less Copper Plating for Semi-Additive Process Masaharu Takeuchi, C. Uyemura & Co., Ltd. VIEW ABSTRACT

13

October 13-30, 2020 | IWLPC Conference & Exposition

3D Integration Track #360 #361 #362

Optimization of Low Temperature PECVD Dielectric Stacks for ViaReveal Passivation Keith Buchanan, P.E., SPTS Technologies VIEW ABSTRACT

EMI Shielding for System in Package using Nozzless Ultrasonic Spray Coating and Silver Particle Free Ink Stuart Erickson, Ultrasonic Systems, Inc. VIEW ABSTRACT

A Study About Facile Interconnect Formations Involving SB²-Jet Solder Ball Stacking for Colonnade Patterning in Hybrid Package Architectures Matthias Fettke, PacTech VIEW ABSTRACT

#363 #364 #365

Die to Wafer Hybrid Bonding: Multi-Die Stacking with TSV Integration Guilian Gao, Ph.D., Xperi VIEW ABSTRACT

Construction Kit of RF-Blocks in Package Technologies Andy Heinig, Fraunhofer IIS - EAS VIEW ABSTRACT

Cure Process Impact on Cure Time and Properties of Low Temperature Polyimide for 3D Stacking Applications Zia Karim, Ph.D., Yield Engineering Systems VIEW ABSTRACT

October 13-30, 2020 | IWLPC Conference & Exposition

14

3D Integration Track #366 #367 #368 #369 #371

Through Glass Vias using an Industry Compatible Glass Handling Solution David Levy, Mosaic Microsystems VIEW ABSTRACT

Hydrogen Embrittlement and Nano Void Classification Within Electroless Copper Deposits Roger Massey, Atotech UK VIEW ABSTRACT

Accelerating Innovations in the New Era of HPC, 5G and Networking with Advanced 3D Packaging Technologies Max Min, Ph.D., Samsung Foundry VIEW ABSTRACT

RDL-First FOWLP for Low-Density Applications with RISPAC Technology Isamu Nishimura, ROHM Co., Ltd VIEW ABSTRACT

Machine Learning Based Methodologies for 3D X-Ray Measurement, Characterization and Optimization for Buried Structures in Advanced Packages Ramanpreet Singh Pahwa, Ph.D., ASTAR Institute VIEW ABSTRACT

15

October 13-30, 2020 | IWLPC Conference & Exposition

2021 18th International Wafer-Level Packaging Conference

SAVE

t h e da te

Organized by:

September 14-16, 2021

Conference and Exhibition: September 14-15, 2021 Professional Development Courses: September 16, 2021 DoubleTree by Hilton San Jose | San Jose, CA, USA October 13-30, 2020 | IWLPC Conference & Exposition

16

www.iwlpc.com

2021 18th International Wafer-Level Packaging Conference

Your Knowledge & Research Matters!

CALL

fo r a b s t ra c ts

Organized by:

Abstracts due April 5th, 2021 Conference and Exhibition: September 14-15, 2021 Professional Development Courses: September 16, 2021 DoubleTree by Hilton San Jose | San Jose, CA, USA

17

www.iwlpc.com

October 13-30, 2020 | IWLPC Conference & Exposition

Exhibitor A-Z 3D InCites

Applied Materials

Francoise von Trapp 45 W. Jefferson Street, Suite 700, Phoenix, AZ 85003 Phone: (978) 340-0773 www.3dincites.com

Patricia E. Seto 3050 Bowers Ave., PO Box 58039, Santa Clara, CA 95054 Phone: (408) 584-1405 Email: patricia_e_seto@amat.com www.appliedmaterials.com

3D InCites is an online media resource founded in 2009 to stir up interest in 3D integration. Now in its 11th year, 3D InCites has broadened its scope stir up interest in heterogeneous integration.

As such, 3D InCites is about much more than just through-silicon vias and subsequent stacking technologies. Rather, 3D InCites has become part of the whole advanced packaging conversation as it relates to heterogeneous integration, the Internet of things, and other applications these technologies enable. As a community, 3D InCites brings to life the people, the personalities, and the minds behind heterogeneous integration and related technologies in a uniquely personal way. The goal is to inform key decision-makers about progress in technology development, design, standards, infrastructure, and implementation.

Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality.

At Applied Materials, our innovations make possible the technology shaping the future.

Learn more at www.appliedmaterials.com.

Canon USA Takaaki Tsunoda 3300 N. First Street, San Jose, CA 95134 Phone: (408) 912-0573 Email: ttsunoda@cusa.canon.com www.usa.canon.com

Ajinomoto Fine-Techno USA Corporation Ryo Miyamoto 20380 Town Center Lane, Suite 105, Cupertino, CA 95014 Phone: (408) 564-7245 Email: miyamotor@ajiusa.com www.ajinorthamerica.com

Canon’s Industrial Products Group offers manufacturing equipment (PVD, Etching, Lithography, Vacuum Components, etc.) Our PVD product line includes oblique sputtering that enables precise film deposition with exceptional uniformity. Recently we released following products. Wafer Bonding Equipment: It employs a new technology that offers permanent bonding at room temperature. X-ray Source for Non-destructive Testing: It is a sealed transmissive microfocus X-ray source with a resolution of 2 µm L/S at 6 W. A sealed tube using diamond to dissipate heat gives one of the unique features of this X-ray source.

Ajinomoto Fine-Techno is a leading provider of electronic materials such as insulation build-up film called “Ajinomoto Build-up Film” (ABF), photosensitive dielectrics, optoelectronics, and molding material. ABF is the world first build-up film for organic semiconductor substrate, and it has been widely used for the advanced package. To meet current and future industry demands, we have started providing new ABF materials with tailored properties and photo sensitive dielectrics for high density Cu wiring and high-speed transmission applications. We can also provide molding materials for WLP and PLP in the form of liquid and film form. Our molding material with low stress targeted to reduce the warpage of wafer/ panel after molding. In addition, we recently developed transparent materials for advanced display such as micro-LED and OLED, and these are introduced in this booth.

Chip Scale Review Kim Newman PO Box 2165, Morgan Hill, CA 95038 Phone: (408) 846-8580 Email: info@chipscalereivew.com www.chipscalereview.com

Chip Scale Review is the preeminent global magazine leading the way in middle-end and back-end technologies for advanced semiconductors covering device & wafer-level test, assembly & packaging. Now in it’s 24th year, Chip Scale Review continues to showcase industry leaders with exclusive editorial content that includes in-depth technical articles by leading industry technologists, market forecasts and updates from veteran industry analysts, research institutions, industry news, events and reviews. Also featured are international directories of equipment manufacturers, materials suppliers and service providers.

October 13-30, 2020 | IWLPC Conference & Exposition

18

Exhibitor A-Z Dow Consumer Solutions

EV Group

Nicholas Emmendorfer 2200 W. Salzburg Road, Midland, MI 48686 Phone: (989) 496-1309 Email: nicholas.emmendorfer@dow.com www.dow.com

Garrett Oakes 7700 S. River Pkwy., Tempe, AZ 85284 Phone: (480) 305-2443 Email: g.oakes@evgroup.com www.evgroup.com

Dow is a global leader in material technologies and innovation, serving customers throughout the value chain. Our materials add proven reliability and efficiency for sealing, protecting, adhering, cooling, and enhancing technologies across wide range of segments; including mobility and transportation, personal and home care, consumer and electronics, building and construction and chemical processing.

EV Group (EVG) is a leading supplier of high-volume production equipment and process solutions for the manufacture of semiconductors, MEMS, compound semiconductors, power devices and nanotechnology devices. A recognized market and technology leader in wafer-level bonding and lithography for advanced packaging and nanotechnology, EVG’s key products include wafer bonding, thin-wafer processing and lithography/nanoimprint lithography (NIL) equipment, photoresist coaters, as well as cleaning and inspection/ metrology systems. With state-of-the-art application labs and cleanrooms at its headquarters in Austria, as well as in the U.S. and Japan, EVG is focused on delivering superior process expertise to its global R&D and production customer and partner base – from the initial development through to the final integration at the customer’s site. Founded in 1980, EVG services and supports an elaborate network of global customers and partners all over the world, with more than 1000 employees worldwide and fully-owned subsidiaries in the U.S., Japan, South Korea, China and Taiwan.

ECI Technology R&D: Dr. Eugene Shalyt 60 Gordon Drive, Totowa, NJ 7512 Phone: (973) 774-4235 Email: eshalyt@ecitechnology.com www.ecitechnology.com

ECI Technology is a trusted developer, manufacturer, and global supplier of chemical process control equipment used throughout the semiconductor, advanced wafer-level packaging, PCB, and LEDs industries – qualifying incoming wet chemistry, managing process control of plating bath solutions and wet processes, and monitors and optimizes process solutions for reuse. Built on decades of inorganic and organic chemistry research and critical intellectual property, ECI works with semiconductor manufacturers, OEMs, and material suppliers to provide optimized control solutions for new and established processes.

Fraunhofer IIS/EAS Andy Heinig Zeunerstr. 38, 01069 Dresden, Germany Phone: +49 173 1981144 Email: Andy.Heinig@eas.iis.fraunhofer.de www.eas.iis.fraunhofer.de

The Fraunhofer Institute for Integrated Circuits IIS is one of Germany’s most important industrial applied research facilities for the development of microelectronic systems. The scientists in the Division Engineering of Adaptive Systems EAS, located in Dresden, develop key technologies for the connected world of tomorrow including modern packaging solutions. Particular design challenges include mastering complexity, optimal utilization of additional degrees of freedom, verification regarding manufacturability and consideration of close thermal, mechanical and electrical coupling in the stacked system. Fraunhofer IIS/EAS can assist you in solving these challenges for an optimized system packaging.

ERS Electronic GmbH Sophia Oldeide Stettiner Str. 3-5, Germering/Munich, Germany 82110 Email: oldeide@ers-gmbh.de www.ers-gmbh.com

ERS has been supplying innovative thermal test solutions to the semiconductor industry since 1970 and is famous for fast-ramping and precise low-noise thermal systems (-65°C to +400°C) for analytical, parametric and wafer sort probing up to 300mm. We design and build stand-alone thermal-forcing systems and custom production tools for difficult thermal applications. We also supply the advanced wafer level packaging market with its fully automatic debonders and manual warpage adjust tools used in the production of both 200mm and 300mm eWLB device packages. On a broader scale, ERS supports not only eWLB but many other Fan-Out WaferLevel-Packaging (FOWLP) and Panel-Level-Packaging (FOPLP) technologies. Our headquarter, sales department, engineering center and production facilities are in the Munich suburb of Germering, and we also have sales and support offices in the US, China, Singapore and Taiwan.

19

October 13-30, 2020 | IWLPC Conference & Exposition

Exhibitor A-Z

Heidelberg Instruments, Inc.

NAMICS

Niels Wijnaendts van Resandt 2539 W. 237th Street, Suite A, Torrance, CA 90505 Phone: (781) 287-9758 Email: info@himt.us www.himt.de

Ken Araujo 226 Airport Pkwy., Suite 660, San Jose, CA 95110 Phone: (774) 929-5462 Email: araujo@namics-usa.com www.namics-usa.com

Heidelberg Instruments is a world leader in the production of highprecision direct write lithography systems and maskless aligners. Due to their flexibility, these systems are used in research, development and industrial applications for direct writing and photomask production by some of the most prestigious universities and industry leaders in the areas of MEMS, BioMEMS, nano technology, ASICS, TFT, plasma displays, micro optics, and many other related applications.

NAMICS is a global technology leader of advanced materials for semiconductor devices and packages, passive components and solar cells with over 70 years of experience and expertise. Headquartered in Niigata, Japan, NAMICS serves its worldwide customers with subsidiaries in the USA, Europe, Taiwan, Singapore, Korea, Hong Kong, and China providing unmatched worldwide support. Please contact us to learn about NAMICS diverse product line of materials such as our packaging and board level underfills, liquid mold underfill for wafer level applications, pressure-less sintering technology for die attach and TIM applications and adhesives for sensor and camera modules.

We build more than products; we build relationships, and NAMICS sets the gold standard for customer service by offering customizing products, world class customer support to provide a solution for your personal application.

Micross Alan Huffman 3021 E. Cornwallis Road, Research Triangle Park, NC 27709 Phone: (919) 248-9216 Email: alan.huffman@micross.com www.micross.com

Micross Advanced Interconnect Technology (AIT), one of the premier wafer bumping & wafer level packaging on-shore facilities in the U.S., develops and provides next-gen interconnect and 3D integration technologies to customers worldwide. Micross AIT supports multiple advanced interconnect and assembly technologies facilitating next-generation electronic systems, including wafer level packaging processes for solder (Pb-based and Pb-free) and Cu pillar bumping, high density (fine pitch) interconnects, through silicon vias (TSV) and silicon and glass interposers. This ITAR-registered facility supports wafer sizes up to 200mm and the flexibility to tailor unique solutions to customerâ&#x20AC;&#x2122;s most demanding requirements.

October 13-30, 2020 | IWLPC Conference & Exposition

20

Exhibitor A-Z PacTech

SMTA

Bernd Otto 328 Martin Ave., Santa Clara, CA 95050 Phone: (408) 421-7465 Email: bernd.otto@pactech.com www.pactech.com

Saniya Pilgaonkar 6600 City W. Pkwy., Suite 300 Eden Prairie, MN 55344 Phone: 952-920-7682 Email: info@smta.org www.smta.org

Pac Tech - Packaging Technologies GmbH (group member of NAGASE & CO. Ltd.) is headquartered in Germany with wholly owned subsidiaries: PacTech USA Inc. in Silicon Valley, USA, and PacTech ASIA Sdn. Bhd. in Penang, Malaysia. PacTech is comprised of three business units: EQUIPMENT MANUFACTURING: Manual & Automatic ENIG & ENEPIG plating tools, Laser solder jetting equipment, Wafer-level solder ball transfer systems, Laser assisted flip-chip bonders. SUBCONTRACT SERVICES: Flip Chip and Wafer Level Package Bumping Services including ENIG or ENEPIG for UBM (solder bumping) or OPM (wirebond). Other services include Electroplating, Laser Solder Jetting, Wafer Level Solder Balling, Repassivation, RDL, Backmetal, Wafer Thinning, Wafer Dicing, Tape & Reel, AOI, X-Ray, SEM, FIB. CHEMISTRY: Pre-Treatment and process chemistry for electroless plating.

The SMTA is an international association for electronics engineering and manufacturing professionals seeking to improve processes through best practices and real world solutions. SMTA offers access to local and global communities of experts as well as accumulated research and training materials from thousands of companies dedicated to advancing the electronics industry. With 50 chapters around the world and thousands of active members, we invite you to join us at one of our local, regional, national or international technical events.

SUSS MicroTec Todd Schivo 220 Klug Circle, Corona, CA 92880 Email: todd.schivo@suss.com www.suss.com

Simco-Ion, Technology Group

SUSS MicroTec is a leading supplier of equipment and process solutions for microstructuring in the semiconductor industry and related markets.Our portfolio covers a comprehensive range of products and solutions for backend lithography, wafer bonding and photomask processing, complemented by micro-optical components.

In close cooperation with research institutes and industry partners SUSS MicroTec contributes to the advancement of next-generation technologies such as 3D Integration and Imprint Lithography as well as key processes for Wafer-Level Packaging, MEMS and LED manufacturing. With its global infrastructure for applications and service, SUSS MicroTec supports more than 8,000 installed systems worldwide.

Karl White 1141 Harbor Bay Pkwy., Suite 201, Alameda, CA 94523 Phone: (800) 367-2452 Email: ioninfo@simco-ion.com www.simco-ion.com

Simco-Ion, the world’s largest supplier of static control and monitoring solutions, offers a comprehensive portfolio of ISOdesigned ionizers and digital controllers to address electrostatic charge/discharge problems in clean manufacturing environments.

We offer product solutions to address Industry 4.0 requirements and new manufacturing processes. Our Novx products provide real-time monitoring, analyze, and control ionization while providing production traceability and control. Innovative products, specially designed to operate in extreme temperatures and critical environments, meet or exceed ISO cleanroom standards.

Industry-exclusive! Custom evaluations to develop a solutions package to manage your electrostatic challenges, improve operations, increase product yield, and control costs.

SVXR (Silicon Valley X-ray) Inc. Francisco Machuca 70 Bonaventura Drive, San Jose, CA 95134 Phone: (408) 618-8051 Email: francisco.machuca@svxr.com www.svxr.com

Smiths Interconnect

Founded in 2013 and headquartered in San Jose, California, SVXR is a pioneer in the development and deployment of fully automatic fast inline X-ray inspection solutions utilizing the latest Artificial Intelligence (AI) and Machine Learning (ML) methodologies.

Our innovation – High-Resolution Automatic X-ray Inspection (HR-AXI), delivers front-end wafer fab-like inspection techniques to the advanced packaging industry. SVXR’s customer support network includes Taiwan, Korea, Japan, and the United States.

With abundant technical expertise and a team of semiconductor industry professionals, we help clients achieve their most stringent manufacturing objectives. For more information about SVXR, please visit www.svxr.com.

Alvy Padiyil 860 Hillview Court, Suite 240, Milpitas, CA 95035 Phone: (408) 957-9607 Email: alvy.padiyil@smithsinterconnect.com www.smithsinterconnect.com

Smiths Interconnect, through its IDI brand spring probes and other compliant technologies, is a premier manufacturer of solutions for WL and package test. The Monet Series incorporates spring probe technology with the coplanarity demands of WL package testing.

Please visit www.smithsinterconnect.com to learn more about Smiths Interconnect.

21

October 13-30, 2020 | IWLPC Conference & Exposition

Exhibitor A-Z Taiyo Ink Manufacturing Co., Ltd.

XPERI

Yuya Suzuki 1731 Technology Drive, Suite 595, San Jose, CA 95110 Phone: (775) 885-9959 Email: yuyas@taiyo-america.com www.taiyo-hd.co.jp/en/

XPERI Abul Nuruzzaman 3025 Orchard Pkwy., San Jose, CA 95134 Phone: (408) 321-6051 Email: abul.nuruzzaman@xperi.com www.invensas.com

Taiyo is a leading chemical company of solder resist materials, and other dielectric materials, who supports your current and next generation of IC packaging products. Hope to talk with you on our booth!

Xperi invents, develops, and delivers technologies that enable extraordinary experiences. Xperi technologies, delivered via its brands (DTS, HD Radio, IMAX Enhanced, Invensas, TiVo), and by its startup, Perceive, make entertainment more entertaining, and smart devices smarter. Xperi technologies are integrated into billions of consumer devices, media platforms, and semiconductors worldwide, driving increased value for partners, customers and consumers.

Our advanced semiconductor packaging and 3D interconnect technologies can be found in billions of devices, DRAM memories, image sensors, RF devices, sensors, processors and mixed signal devices currently in high volume production at leading original equipment makers, original design manufacturers, and integrated device manufacturers.

TechSearch International Jan Vardaman 4801 Spicewood Springs Road, Suite 150, Austin, TX 78759 Phone: (512) 372-8887 Email:jan@techsearchinc.com www.techsearchinc.com

TechSearch International, Inc. has a 33-year history of market and technology trend analysis focused on semiconductor packaging, materials, and assembly. Research topics include WLP, FO-WLP and panel-level processing, Flip Chip, CSPs, BGAs, 3DICs, Si Interposers, System-in-Package (SiP) and Heterogeneous Integration, ADAS and automotive electronics, and power devices. In conjunction with SavanSys Solutions, wire bond, flip chip, WLP, and 3D IC cost models are offered. TechSearch International professionals have an extensive network of more than 21,000 contacts in North America, Asia, and Europe and travel extensively, visiting major electronics manufacturing operations and research facilities worldwide.

October 13-30, 2020 | IWLPC Conference & Exposition

Yield Engineering Systems Joe Simas 3178 Laurelview Court, Fremont, CA 94538 Phone: (510) 954-6889 Email: jsimas@yieldengineering.com www.yieldengineering.com

Silicon Valley-based Yield Engineering Systems (YES) manufactures manual and HVM vacuum cure systems, monolayer coating systems and plasma cleaning tools used for precise surface modification of semiconductor, optical and life science substrates. YES enables customers in multiple high-growth segments including advanced packaging, MEMS, medical/biotech, AR/VR, display, LED, automotive, power, communications, and other emerging technologies.

22

ADVANCE YOUR CAREER WITH: »THE LATEST TECHNICAL INFO » PROFESSIONAL NETWORKING » JOB RESOURCES ...AND MUCH MORE

Join Today! www.smta.org/membership 23

October 13-30, 2020 | IWLPC Conference & Exposition

Thank you to our Event Sponsors Platinum

Gold

Silver

Supported By:

Supporting Media:

October 13-30, 2020 | IWLPC Conference & Exposition

24