Chassis and Enclosures are Becoming Systems Embedded Designs Take On Optical Connectivity Safety Certification Challenges Automotive Software The Magazine of Record for the Embedded Computer Industry
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Vol 16 / No 6 / June 2015
CPU Architectures Integrate Different Processing Cores
An RTC Group Publication
The Magazine of Record for the Embedded Computing Industry
CHASSIS AND ENCLOSURES
A Special Look at Chassis and Enclosures: When a Box Becomes a System by Tom Williams, Editor-in-Chief
TECHNOLOGY CORE SAFETY HETEROGENEOUS SYSTEM ARCHITECTURE
16 Enabling Heterogeneous Solutions Using Standard Communication Middleware DEPARTMENTS 06
The Code Now Runs the Car—Tons of it
Latest Developments in the Embedded Marketplace
Enabling Heterogeneous Solutions Using Standard Communication Middleware Girish Shirasat, Concurrent Technologies
Today’s High-Powered GPUs— Strong for Graphics and for Math by Marc Couture, Curtiss-Wright Defense Solutions
OPTICAL CONNECTIVITY IN SYSTEM DESIGN
Harnessing Optical Links for Embedded Systems by Rodger Hosking, Pentek
TECHNOLOGY IN SYSTEMS AUTOMOTIVE SYSTEMS
PRODUCTS & TECHNOLOGY Newest Embedded Technology Used by Industry Leaders
Compliance with ISO 26262 Causing Headaches? Here’s help by Mark Richardson, LDRA
TECHNOLOGY DEVELOPMENT MOBILE SYSTEMS
Design Once, Use Many: The Need for a Common Hardware/Software Solution for Mobile Computing by Geoff Goetz, Bsquare
34 Design Once, Use Many: The Need for a Common Hardware/Software Solution for Mobile Computing RTC Magazine JUNE 2015 | 3
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The Code Now Runs the Car—Tons of it by Tom Williams, Editor-In-Chief
Look at all the shiny new automobiles rolling off the assembly lines. Ever more of them come equipped with nifty touch screens that allow access to myriad functions both affecting the driving experience and infotainment. There are continuous readouts for miles-per-gallon, odometers, GPS, surrounding awareness, views for helping park and more. There are interfaces for Bluetooth smartphone access with one-touch dialing and hands-free operation, there are audio controls for conventional and satellite radio, for audio (thank goodness, not video) entertainment and more. Deeper down in the vehicle there are electronic control units with software for controlling nearly every aspect of the car’s operation from engine to braking systems, stability control and airbags. Active safety systems use radar for adaptive cruise control, sensors warn of drifting out of the lane—the list goes on. Even the windows, wipers and other non-obvious things are under control of the embedded software buried deep within what is evolving into an intensely complex web of embedded systems. And we haven’t even mentioned Internet and remote access such as the ability of police to request a manufacturer to shut down a vehicle that is being pursued. Yes, this has happened. And God forbid we should bring up the possibility of hackers breaking into automotive systems while they are on the road. As far as we know, that hasn’t happened—yet. So you carefully consider all the wondrous features and options offered with an array of vehicles and decide on a purchase. Dealer, bank or lending institution is happy to help and off you drive. You buy fuel, keep up with maintenance and make payments and one day the title arrives in the mail. Now you actually own the vehicle free and clear, right? Not so fast. Does that title say anything about all the code
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embedded in the car? No. There is no transfer of the intellectual property rights to any of the software in that car. In fact, there seems to be very definite taboos associated with it. I was once at an Embedded Systems Conference where one of the featured activities was to watch a group tear down embedded devices to identify what made them up. They disassembled such things as a Segue scooter, and other interesting items with interesting sensors, actuators and ICs. At one show they were tearing down a Toyota Prius identifying which graphic chips it used, which communications ICs, etc. I insolently raised my hand and asked if they had managed to disassemble the software to see how it actually worked. The reaction was almost paranoid. “We couldn’t do that because the software is proprietary and rigidly protected.” Indeed it is, but it is not possible to understand the function of such a system without understanding the code. So what they had was a fairly boring parts list. The explosive growth of the software content of automobiles is relatively new and it is safe to say that consumers have not fully appreciated its implications. For that matter, neither have manufacturers. When they do, things could get interesting. So far, relatively few of the newer “software heavy” vehicles have made it to the used car market, but that is merely a matter of time. There have already been a number of recalls on several models that have simply required a software patch or upgrade—something we’re all familiar with in other areas. But what about software maintenance or continued licensing? These are things we haven’t completely encountered yet, but we could. Maintenance is of course familiar in the form of recalls and recalls are motivated either by government regulations or concerns about safety
or corporate reputation. But there are certain “options” that cost the manufacturer nothing because they are already built in to every vehicle. There is, however, a charge to enable them. For example, one brand has a low tire pressure indicator that lets the driver know that a tire is low. It’s up to him to figure out which one. The upgrade displays all four tires and their individual pressures. Enabling that simply involves a software switch—for a price. But what if automobile manufacturers get the idea that software could constitute a continuing revenue stream? As far as I know we haven’t seen this yet but it is certainly possible for manufacturers to consider, say, a seven-year license on the code contained in a car with annual maintenance or license fees to be paid beyond that. Shut down functions—with sufficient warning for safety— could be built in and made so that they can be prevented only by a licensed dealer on payment of a fee or perhaps remotely. This might be manageable, if annoying, with vehicles in the hands of first or second owners with clear links back to a dealer. But what about down the line when cars end up in Wizard Wally’s used car lot? Will an independent auto software maintenance industry emerge? That is doubtful given the jealousy with which information about the code is guarded. But with the continuing explosion of software content in automobiles it at least makes sense to think about the possible implications for the future.
New EEMBC Benchmark Targets Improved Performance of the ‘Things’ on the Internet of Things EEMBC, the Embedded Microprocessor Benchmark Consortium has announced its focus on a benchmark to ensure optimum efficiency of edge nodes (end points) on the Internet of Things (IoT). This new benchmark, currently in development within EEMBC’s IoT working group, aims to provide a standardized, industry- created and -endorsed method to provide application developers with accurate, reliable information that allows them to quickly and equitably compare the efficiency of system solutions targeted at IoT end-point applications. An edge node, referred to as the ‘thing’ of the IoT, has four primary parts: 1) the sensors or transducers; 2) the processing (e.g. security, compression, protocol stack, data analysis); 3) the interfaces connecting the transducers and microcontroller; and 4) a communication mechanism used to send/receive information between the edge node and the network. When designing an edge node device, battery-life is often one of the most important factors because of the need for portability and flexibility in placement. Therefore, the new EEMBC benchmark will provide a method to reliably determine the combined energy consumption of the platform, taking into consideration the real-world effects of the ‘thing’ parts. This approach enables the optimized selection of the microcontroller and radio-frequency component (e.g. Bluetooth and ZigBee). “Due to the diversity of IoT edge node applications, several configuration profiles are needed to represent the most popular functions, adding to the value and usefulness-and complexityof the benchmarks” said Mark Wallis, co-chair of the EEMBC IoT working group and system architect at STMicroelectronics. “These multiple configuration profiles will allow black-box comparisons of corresponding products, and white-box comparisons of platforms which may be used for other applications not covered by existing profiles, but similar enough for the benchmark to give a useful indication of the expected performance and energy efficiency of the platform.” Current active working group members include Analog Devices, ARM, Freescale, Imagination Technologies, Microchip, NXP, Silicon Labs, STMicroelectronics, Synopsys, and Texas Instruments.
LPWAN IoT Connectivity Standard over ISM Spectrum Published The Weightless SIG has announced the publication of version 1.0 of the new Weightless-N open standard based on a low power wide area star network architecture. Operating in sub-GHz spectrum using ultra narrow band (UNB) technology, Weightless-N offers best in class signal propagation characteristics leading to excellent range of several kilometers even in challenging urban environments. Very low power consumption provides for exceptionally long battery life measured in years from small conventional cells and leading edge innovation in design minimizes both terminal hardware and network costs. Central to the Weightless proposition is its status as an open standard. Weightless is differentiated from all alternative proprietary LPWAN technologies by uniquely enabling a competitive, free and fair market that does not lock developers into using particular vendors or network service providers. Any company is able to develop both low cost base stations and terminals using royalty free Weightless technology. Networks can be owned and operated independently by any company or, typically, IoT terminal devices and applications can be produced for use cases that will rely on connection to networks operated by third parties. A Weightless terminal device can be produced for less than two dollars with a Weightless base station bill of materials of less than $3000. Weightless-N is designed around a differential binary phase shift keying (DBPSK) digital modulation scheme to transmit within narrow frequency bands using a frequency hopping algorithm for interference mitigation and enhanced security. It provides for encryption and implicit authentication using a shared secret key regime to encode transmitted information via a 128 bit AES algorithm. The technology supports mobility with the network automatically routing terminal messages to the correct destination. Multiple networks, typically operated by different companies, are enabled and can be co-located. Each base station queries a central database to determine which network the terminal is registered to in order to decode and route data accordingly. The complete specification is available to Weightless SIG Members for immediate download from the organization’s website.
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NXP and Qualcomm Accelerate Adoption of NFC and Security in Mobile, Wearable and IoT Devices NXP Semiconductors has announced that Qualcomm Technologies, a subsidiary of Qualcomm Incorporated, will integrate NXP’s near field communication (NFC) and embedded secure element (eSE) solutions across Qualcomm Snapdragon 800, 600, 400 and 200 processor-based platforms. Qualcomm Snapdragon is a product of Qualcomm Technologies, Inc. The agreement will enable the rapid introduction of NFC and eSE on Snapdragon-based devices to meet market demands for increased functionality in a broad range of consumer applications. New reference designs expand the reach of NFC beyond the smartphone and into other applications such as home automation, consumer electronics, automotive, smart appliances, personal computing and wearables. The availability of NXP’s NFC and eSE solutions for Snapdragon platforms will help accelerate the deployment of secure transactions into a myriad of new applications, such as mobile payments and digital identity for mobile, automotive and Internet of Everything (IoE) segments, complementing Qualcomm Technologies’ advanced security solutions. The new offering will feature the NQ220 module, which was derived from the recently launched NXP PN66T module. The NQ220 is designed to enable service providers to easily deliver new applications by simplifying the process of deploying credentials to devices, significantly reducing design costs and time-to-market considerations for mobile wallets and additional applications such as prepaid payment, transit and access control. The NQ220 reference design is available now through NXP sales channels, please contact NXP sales for further information.
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PLINY Aims to Develop a Predictive Engine to Auto-Complete and Auto-Correct Code GrammaTech has announced it has begun work on PLINY, a technology to automatically detect program defects, suggest program repairs, and complete program drafts based on code and specifications mined from vast repositories of existing code. PLINY is part of the Defense Advanced Research Projects Agency’s (DARPA’s) Mining and Understanding Software Enclaves (MUSE) program. MUSE is an initiative that seeks to gather hundreds of billions of lines of publicly available open-source computer code to mine in an effort to create a searchable database of properties, behaviors, and vulnerabilities. PLINY is a joint effort among GrammaTech, Rice University, the University of Texas-Austin, and the University of Wisconsin-Madison. “If successful, PLINY has the potential to be a transformative technology,” said David Melski, VP of Research at GrammaTech. “It has the potential to change the way programming is done, the way programming is taught, and who does programming. It could give the power to express computation to people who don’t currently have it.” GrammaTech’s role in the PLINY project focuses on analyzing code to extract program elements that represent computational paradigms, as well as identifying syntactic and semantic features that characterize the program elements. Accurate identification and characterization of program elements is essential to enabling organization and search of PLINY’s code database. GrammaTech’s CodeSonar static analysis tool will be at the center of the effort to generate features. CodeSonar provides extraordinary scalability, an ability to analyze diverse code samples, and an analysis engine with proven capabilities for discovering subtle program properties.
Sealevel Systems and ADLINK Announce Partnership for Computer-on-Module Solutions Sealevel Systems, Inc. and Adlink Technology have announced a partnership designed to provide industry-leading computing and I/O solutions for OEMs using Adlink’s computer-on-module (COM) and Sealevel’s custom carrier board technology. The agreement comes as a result of a number of successful collaborations between the two companies across vertical markets, including oil and gas, military and automotive applications. Adlink’s COM products provide the generic computing engine along with storage, Ethernet, keyboard/mouse and display common to most applications. The modular architecture allows future upgrade of the processor subsystem and offers superior life cycle management of systems and applications. Adlink’s computer-on-modules are available based on COM Express, Qseven and SMARC specifications. Sealevel’s custom carrier boards provide the application-specific circuitry particular to a customer’s unique application. Common I/O carrier board features can include serial, digital and analog I/O, all of which can be designed to meet the I/O count, voltage ranges and connector types required by the application.
ARM and Enea Demonstrate Reference Platform for Network Function Virtualization ARM and Enea have showcased an ARM-based reference platform for Open Platform for Network Function Virtualization (OPNFV). This demonstration of an early developer release on the ARM architecture brings unique value to the NFV vision, enabling processing efficiency and cross-platform flexibility and choice. “This is a tremendous leap forward in delivering the NFV vision across a wide range of highly-integrated, workload-optimized ARM networking SoCs, available via the common OpenDataPlane (ODP) interface layer,” said Charlene Marini, vice president of embedded marketing, ARM. “This application-ready platform is also the enabling layer for the Intelligent Flexible Cloud framework that will transform the network infrastructure over the next decade.” The open source, carrier-grade NFV Infrastructure platform supports a set of example Virtual Network Function (VNF) applications. The collaboration of Enea and the ARM ecosystem of silicon partners will provide the initial building blocks of the platform, including OpenStack, OpenDaylight, Open vSwitch, KVM and the ODP built on a Linux foundation. The focus is on creating an application-ready platform based on the ARM architecture and OpenDataPlane moving the industry towards a standardized open source framework to support the flexibility, greater automation and scalability that is required for network infrastructure moving forward while enabling underlying processing efficiency. This initial release will be incorporated into the integration and testing processes of the Linux Foundation’s OPNFV project. This will enable the broader OPNFV community to participate in performance and reliability optimizations and validating VNF applications on the ARM architecture.
Hacktivism Professionalizing and Going after Bigger Targets New research from leading market analysts, Juniper Research, suggests that the rapid digitization of consumers’ lives and enterprise records will increase the cost of data breaches to $2.1 trillion globally by 2019, increasing to almost four times the estimated cost of breaches in 2015. The research, entitled The Future of Cybercrime & Security: Financial & Corporate Threats & Mitigation, has found that the majority of these breaches will come from existing IT and network infrastructure. While new threats targeting mobile devices and the IoT (Internet of Things) are being reported at an increasing rate, the number of infected devices is minimal in comparison to more
traditional computing devices. The report also highlights the increasing professionalism of cybercrime, with the emergence of cybercrime products (i.e. sale of malware creation software) over the past year, as well as the decline in casual activist hacks. Hacktivism has become more successful and less prolific – in future, Juniper expects fewer attacks overall, but more successful ones. “Currently, we aren’t seeing much dangerous mobile or IoT malware because it’s not profitable”, noted report author James Moar. “The kind of threats we will see on these devices will be either ransomware, with consumers’ devices locked down until they pay the hackers to use their devices, or as part of botnets, where processing power is harnessed as part of a more lucrative hack. With the absence of a direct payout from IoT hacks, there is little motive for criminals to develop the required tools.” The research noted that leading OTT (Over The Top) players such as Apple, Google and Amazon were in pole position to capitalize on this transition, with each now offering cloud-based solutions both for personal storage and premium content access. It argued that if consumers are tied into multiple products from an OTT, those consumers becomes increasingly reluctant to churn away from one element of the brand, as he/she loses access to content across their devices. RTC Magazine JUNE 2015 | 9
EDITORS REPORT CHASSIS AND ENCLOSURES
A Special Look at Chassis and Enclosures: When a Box Becomes a System Today’s embedded systems are moving into ever more challenging applications and environments. They must often resolve conflicting demands of modularity, ruggedness, cooling and more. Developers are rising to these challenges with ever more innovative answers. by Tom Williams, Editor-in-Chief
It is perhaps common to think of electronic enclosures and chassis as a given or maybe as a side issue in most systems. Of course, we all know that is not the case—not even for the seemingly endless rows of racks that populate modern data centers. And it is even more definitely not the case in terms of embedded systems—especially mobile systems. Embedded systems, by their very name must fit very high compute and I/O power into ever smaller spaces. It’s no surprise that such requirements pose challenges for power, heat and space that must be dealt with not only for the needed functionality, but also for reliability. Ruggedization has become a specific design criterion. Not only must many systems be built to withstand extremes of shock and vibrations, but many must also protect their components from hostile surrounding conditions like harmful chemicals or extreme weather. And these rugged designs must still be able to dissipate the heat to the same component requirements as those used in comfortable air-conditioned settings.
Figure 1 The TechSYS from Verotech
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We present here a look at some of today’s most innovative enclosures. Some are offered from their vendors as standard products designed to accommodate certain widely known requirements. Still almost all can be modified and customized by their vendors to meet the specific requirements of users. Some enclosures presented here are from vendors who specialize in offering standard and custom enclosure designs for customers. Others are presented with the systems they contain because the manufacturer saw fit to mention and/or emphasize the nature of the chassis or enclosure as an important aspect of the system design. We can see from these examples several trends or characteristics aimed at the wide range of embedded applications. Among these are flexibility and modularity as well as innovative approaches to ruggedization and cooling.
Configurability and Modularity at Center Stage
For example, a modular system assembled from standard building blocks, the TecSYS from Verotec is user-configurable around the default options if required (Figure 1). Typically, TecSYS is housed in the field-proven Diplomat desktop enclosure, available in 3U and 6U heights, full and half widths and a variety of depths; other variants support 19 inch rack mounting. Thermal management, power supply configuration and backplane size and architecture are selected from Verotec’s standard product portfolio, ensuring short lead times and platforms configured exactly to the requirements of the application. TecSYS is suitable for use in both the development and production environments. The TecSYS platform can be very easily configured for any standard bus structures such as VPX, VMEbus, VME64x and cPCI, with boards mounted either horizontally or vertically as required. A typical platform is configured for VPX. The system is housed in a 10.5 inch half-width 6U, 12.7 inch (322mm) deep Diplomat enclosure, which is configured with a 2U plenum
chamber at the bottom, a 3U KM6-RF subrack in the middle and a 1U air exhaust chamber at the top. The heart of the system is a 5-Slot 3U full mesh X4 PCI Express VITA 46.4 backplane, which also provides VITA 46.10 RTM capability, an important consideration for I/O, which is easily accessed through a removable rear panel; the top cover is also readily removable for improved access. The backplane provides System Management and JTAG Interfaces; it gives fat pipe communications between all five slots and provides an interface with one of the most widely used architectures, PCI Express. Pluggable PSUs with two independent converters operating in parallel provide 30A at 5V and 40A at 3.3V simultaneously. Getting the most in terms of efficiency and functionality in the ATCA world is aided by a chassis design that offers a number of options. A redundant shelf manager integrated with the switch fabric saves two slots that are usually dedicated switch fabric slots in the ATCA chassis from Pixus Technologies (Figure 2) for an ATCA system platform compliant to PICMG 3.0 Rev.2.0. The two extra slots can then be utilized as standard payload slots, allowing more boards/performance in significantly less space. The PXS0640 can optionally be configured for full HA redundancy across all FRUs, including power modules, cooling units, shelf managers/telco alarm, and switches. If AC power is not required, a 5U chassis option is available. The 40GBASE-KR4, 6-slot backplane supports dual star fabric, with an option for a full mesh, and an option for a replicated mesh on node slots so that the combined switch/shelf manager allows a full 6 node slots. Full redundancy is supported with dual shelf manager, dual cooling units, dual switches and dual power modules. A 4 x 1100W AC supply (N+1), 2 x 50 Amp DC PEM allows AC and DC to run at same time for swapping modules. There is a front power entry module, front and rear ESD jack. Redundant FRU information devices and a telco alarm are also included.The PXS0640 is RoHS compliant. The PXS0610 6U shelf combines the shelf management slots with the Hub providing 50% more payload slots on the same
Figure 2 The Pixus PSX0640
Figure 3 The Pentair Interscale M case
form factor. The HASS integrates a VT003 shelf manager from Vadatech and a 40GbE/10GbE switch and a GbE switch on the same module. This allows saving of two slots in the system for the payload vs. having dedicated switches in the system. With two VT003s in the system there is full redundancy and failover both on the switch side as well as on the shelf manager side. The VT003 can also run as a protocol analyzer to monitor, inject, capture and validate I2C traffic on the Intelligent Platform Management Bus (IPMB). A Graphical User Interface (GUI) validates and displays the IPMI packets or schedules IPMI messages for injection into the Shelf. The GUI application communicates with the VT003 through the Ethernet port. The VT003 is fully hot-swappable to minimize service down time. The industry is telling us there is a specific need for small, compact construction style cases that are also robust, with ease of assembly and convenient mounting options for the electronics inside. The cases should also be high quality, offer EMI protection, and have an attractive look. Looking beyond the 19-inch industry standard to also include smaller form factors, the Interscale M case from Pentair (Figure 3) offers flexibility, competitive delivery, and a very competitive price point. Along with customized printing, available optional cutouts for specific I/O requirements and a wide range of standard sizes the Interscale M is making a strong push to fit and exceed these industry needs.
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EDITORS REPORT CHASSIS AND ENCLOSURES
Figure 4 The ADLMES-8200 from ADL Embedded Solutions
Additional performance features include a case designed to meet IP 30, consisting of just four parts that can be easily assembled and disassembled with two screws! A total of 21 case sizes are available direct from stock. EMI protection is achieved by the interlocking case walls and offers 20 dB at up to 2 GHz. A wide range of standard accessories, e.g. flexible board mounting configurations, various case feet options, a range of fans and internal PCB mounting options allow the Interscale M user to integrate electronics quickly, simply and affordably. Further services are also available such as final assembly of the chassis, including accessories and heat simulation using FLOWTHERM or a wind-tunnel test. Modular components equate to high availability and shortened time to market, which can be especially critical in the PC/104 and 3.5-inch SBC market. A new embedded enclosure design with highly configurable modularity from ADL Embedded Solutions makes it possible to expand or reduce a system without replacing the entire enclosure (Figure 4) ailability starting point for meeting your specifications. Once integrated, the ADLMES-8200 lends itself to extending the life of existing products by allowing the enclosure to be modified with minimal impact, translating into lower development and sustaining costs, and shorter development cycles. Also addressing critical cooling issues for compact systems, the ADLMES-8200 has a thermally conductive base, ribbed sidewalls and finned top that provide radiative and conductive cooling paths for superior thermal management to the outside of the enclosure. The ADLMES front I/O plate can be quick-turned and built to custom specifications to support most types of I/O connectors. If additional I/O connectors are required, the MES backplate can also be customized in a minimal configuration. The ADLMES-8200 can be further customized for high IP requirements by replacing the front I/O plate and bezel with a custom milled faceplate that supports the pre-specified high IP connectors. Supported by ADL Embedded Solutions’ Team of SolidWorks design and modeling engineers, customizations are handled expertly and efficiently. Air cooling can be important in most situations and in many, such as office environments, it must minimize noise. VadaTech, a manufacturer of embedded boards and complete application-ready platforms, has released a new 6U MicroTCA embedded computing system platform with quiet fan trays designed to 12 | RTC Magazine JUNE 2015
operate at under 55dBA, suitable for office use. The VT898 is a 6-slot cube chassis that is 10.5 inches tall by 10 inches wide by 10.5 inches deep (Figure 5). The “Whisper” chassis features redundant cooling in a push/pull frontto-rear airflow configuration. The elegant design includes a spring-loaded handle that is flush to the top of the chassis when I’m not in use and glide strips for smooth PSU and fan tray extraction. The 6U Cube chassis platform includes a 40GbE-capable backplane, a 1000W AC power supply, Telco Alarm, and a JTAG Switch Module. The backplane has routing for FCLK, and TCLK A-D. VadaTech offers MicroTCA and other form factor chassis platforms in various styles including Cubes, Vertical Shelves, Horizontal Shelves, and Rugged ATRs.
Combining Requirements for Versatility
Considerations for configurability, ruggedness and cooling come together in a low cost data-grade MicroTCA chassis that is suitable for a wide range of embedded applications including industrial and defense applications that do not require all of the functionality of a fully compliant MicroTCA system. Enhanced ruggedization options are available for defense applications. The PXS0108 from Pixus Technologies (Figure 6) leverages over 20 years of superior cooling, backplane, and packaging innovation with proven Kaparel and Rittal technologies. The PXS0108 has an active backplane that alleviates the need for expensive power modules (PMs). The backplane provides a power manager for each slot that controls and limits the management and payload power to the maximum allowed 8 Amps per slot. On power-up, payload power is delayed to allow the MCH(s) to fully come online. The AMCs are then sequentially enabled allowing for a smooth power up sequence. The PXS0108 has configuration options that allow redundant power supplies, backplane topologies and FRU information de-vices. Features include the MicroTCA System Platform based on the PICMG MicroTCA.0 R1.0 specification. The unit is 19 inches x 1U x 9 inches deep and is RoHS compliant. Redundant or non-redundant backplane configurations are available and
Figure 5 The VT898 from Vadatech
warranty backed by superior customer support and service. Independent test labs certify Crystal Group’s RS2516PS18 Rugged 2U Server meets requirements for MIL-STD-810, MIL-S-901, MIL-STD-461, and FCC Class A certification.
And Now Bullet Proofing
Figure 6 The Pixus PXS0108
AMCs are hot swappable. In redundant configuration, MCH failover support and MCHs are hot swappable. A superior cooling configuration for airflow uses a push-pull, side-to-side configuration that removes the need for expensive Cooling Units (CUs). An active backplane removes the need for expensive Power Modules (PMs). The PXS0108 has nine fixed fans. Eight provide for a pushpull configuration in the module area and one provides cooling in the power supply area. Airflow is from right to left. The fans are fixed and are not managed and therefore constantly operate a full speed. There is no air inlet filter on the PXS0108. Pixus Technologies can modify this product to meet specific customer requirements without NRE (minimum order placement is required). Achieving ruggedness can also pose a challenge to weight and cooling issues, especially when size is also critical. In addition, when heat and cooling are critical, it can be an advantage to have the power supplies tailored to and supplied with the enclosure. In the case of the Crystal Group, this has led to an innovative choice of materials. Their new new, rugged 2U Server features a chassis constructed from light-weight carbon fiber and strain-hardened aircraft aluminum, and designed for use in harsh environments like those found in military, oil & gas, mining and other industrial applications. The RS2516PS18 (Figure 7) provides high data storage capability in a compact 2U design. The unit measures 18 inches in depth and weighs 25 lbs. dependent on content. The server is constructed with carbon fiber and aluminum materials for light weight and high data density applications. The unit can be configured for 24 by 9mm SSD’s or 16 hot swappable 2.5 inch 15mm drives. The RS2516PS18 contains rear I/O for power and SAS connections and can be mounted on Jonathan rails or Delrin glides. The RS2516PS18 is designed to be advantageous to customers looking to put large amounts of storage in a compact lightweight form factor. It is able to be configured with 24 hot swappable SATA/SAS disks while still maintaining the shock/vibe levels that customers are accustomed to, as well as retaining the same thermal profile of -40°C to +55°C without any degradation in computational performance. The RS2516PS18 is an air cooled unit with six high speed, high volume, and low noise fans. The unit’s power conscious performance comes from a 460W AC power supply or a 425W 18-36VDC supply. The rugged storage device is available with optional humidity and EMI kits and is covered by a 5 plus year
A number of chassis that may also find use in military—especially UAV—applications have in addition to what we think of as “ruggedness” also the need to be bullet proof. All the while they must contain the electronics and dissipate the heat. Dawn VME provides a family—of 3U Open VPX products called CUBE to provide for the needs of the UAV market is available in 1 through 6 slots (Figure 8). Each chassis is shipped complete with backplane, power system and is I/O ready for the addition of boards. Backplane topology and I/O to panel connectors may be mapped into the system at time of order by using Dawn’s patented and performance “Eye-tested” Fabric Mapping Module Technology. The CUBE chassis provides a bullet proof sealed environment for application and boards to run in. Each design is thermally modeled using the latest in 3D modeling and thermal analysis CAD software. Dawn can model a planned configuration and determine exact thermal performance before placing order. Dawn’s 3U form factor conduction cooled chassis for cold plate deployment is designed for all rugged environments: Airborne, Land and Sea. Conduction-cooled base coupled, via short and efficient path, provides for optimum cooling. Maximum power dissipation depends on cold plate. A RuSH enhanced 3U conduction cooled power supply monitors system-critical performance parameters including voltage, current, and temperature. Power supply startup is under firmware control and may be factory modified to operate with startup-sensitive boards. The RuSH monitor is interfaced into the OpenVPX IPMB (I2C) management plane, providing communication link up with system cards. The rigid front panel interface eliminates wiring challenges and backplane overlays enable PMC/XMC to I/O customization with I/O mappable between backplane and rigid I/O board using Dawn’s patented FMM modules.
Liquid Cooling Meets Rugged
A liquid cooled High Performance Embedded Computer (HPEC) server is designed for maximum performance in rugged
Figure 7 The RS2516PS18 from the Crystal Group
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EDITORS REPORT CHASSIS AND ENCLOSURES The BoldHPC is a 19-inch rack mount computer offering one or two chassis offers optional configurations including double blades, single blade with PSU, and single blade with PCIe expansion for I/O boards and mass storage. The introduction of the BoldHPC brings supercomputing power to applications never previously possible. The design is extremely energy efficient and liquid cooling is reliable for high performance in difficult environments. The BoldHPC is based on the ACPU-20 blade which includes 1 or 2 Intel E5 v2 processors with up to 12 cores each, and up to two NVIDIA Kepler GPUs or two Intel Phi coprocessors can be populated per blade. The BoldHPC 50-10 is rugged and reliable without any moving parts, making it suitable for intelligent surveillance and reconnaissance, heavy computational loads, simulation, signal processing, data concentrators and other rugged HPC applications. Figure 8 The CUBE enclosure from Dawn VME
environments. Safe, reliable liquid cooling enables the Dynatem BoldHPC with greater performanceâ€”1000 times more effective than air-coolingâ€”and consumes less energy than fans. The design is extremely energy efficient with greater than 3.15 Gflops per watt (Figure 9).
14 | RTC Magazine JUNE 2015
The Chassis as System
There comes a point where the technical capabilities built into a chassis to support the range of capabilities that may be built into it take on the characteristics of a system design in themselves. This appears to be the cased with an 18-slot chassis that features a high-bandwidth, all-hybrid backplane to meet a wide range of high-performance test and measurement application needs. The hybrid connector type in every peripheral
Figure 9 The Dynatem BoldHPC
slot of the NI PXIe-1085 from National Instruments (Figure 10) enables the most flexibility in terms of instrumentation module placement. It also incorporates all the features of the latest PXI specification including support for both PXI and PXI Express modules with a built-in 10 MHz reference clock, PXI trigger bus, and PXI star trigger for PXI modules and a built-in 100 MHz reference clock, SYNC100, and PXI differential star trigger for PXI Express modules. This chassis enables higher-bandwidth systems and provides the flexibility needed to work with both hybrid-compatible PXI and PXI Express modules. There are a total of 16 PXI hybrid-compatible slots and one PXI Express system timing slot that can accept either a PXI Express system timing module or PXI Express module. The PXI Express system slot offers one x16 and one x8 PCI Express Gen 3 link to two switches. Each switch provides a x8 PCI Express link to eight or nine peripheral slots. The NI PXIe-1085 chassis integrates three PWM system fans to provide forced-air cooling that meets the increased cooling demands of PXI Express and CompactPCI. The NI PXIe-1085 incorporates the power supply components into a modular unit that can be replaced quickly, resulting in a mean time to repair (MTTR) of less than five minutes.Additionally, the three cooling fans are hot-swappable and easily replaceable with access to the rear of the chassis. The chassis also monitors power supply health/voltages, air intake temperature, and fan health/speed. It also provides any failure feedback to the user via status LEDs located on the front bezel of the chassis. This chassis includes IN/OUT SMA connectors for the 10 MHz reference clock on the front of the chassis. When the backplane detects a 10 MHz signal on the IN connector, it phase locks PXI_CLK10, PXIe_CLK100, and PXIe_SYNC100 to the
external clock. The OUT connector provides a buffered, nonTTL version of the 10 MHz reference clock. The NI PXIe-1085 chassis is configured with NI Measurement & Automation Explorer (MAX). With this software configuration tool, you can easily configure NI PXIe-1085 systems without time-consuming manual installation of initialization files. MAX creates the pxisys.ini file that defines the layout and parameters of your PXI system including chassis, controller, and plug-in modules. So we can definitely say that for modern embedded systems, chassis and enclosures are far from a side issue and can often take on the character of systems in their own right. The task for developers of such enclosures is to battle often conflicting demands for configurability, cooling, size, weight, connector placement, power supplies and ruggedness. That is definitely a set of challenges that demands a systems approach. ADL Embedded Solutions San Diego, CA 858-490-0597 www.adl-usa.com Crystal Group Hiawatha, IA (319) 378-1636 www.crystalrugged.com Dawn VME Products Fremont, CA (510) 657-4444 www.dawnvme.com Dynatem Mission Viejo CA. 949.855.3235 www.dynatem.com National Instruments Austin, TX (512) 683-0100 www.ni.com Pentair Minneapolis, MN (763) 545-1730 www.pentair.com Pixus Technologies Waterloo, Ontario (519) 885 5775 www.pixustechnologies.com VadaTech Henderson, NV (702) 896-3337 www.VadaTech.com
Figure 10 The National Instruments NI PXIe-1085
Verotech Derry, NH (603) 821-9921 www.verotec.us
RTC Magazine JUNE 2015 | 15
TECHNOLOGY CORE HETEROGENEOUS SYSTEM ARCHITECTURE
Enabling Heterogeneous Solutions Using Standard Communication Middleware
With the ever increasing trend for processor boards to include more general purpose cores for better parallel processing capacity along with fabric interconnect bandwidth it is possible to construct very flexible HPEC systems. by Girish Shirasat, Concurrent Technologies
A High Performance Computer (HPC) situated in a data center environment is typically made up of a collection of racks and cabinets connected by Ethernet, Infiniband or both. These run applications on top of a wide array of standards-based communication middleware that are widely extensible and capable of physical distribution. Each HPC rack consists of several server elements and each of these is likely to include a combination of Intel CPU and accelerator devices operating in a heterogeneous fashion to provide the best possible performance dependent on the application type. When additional performance is required another server rack can be added to increase the cluster size and because the interconnect mechanism is based on Ethernet or similar, the application has more resources and operates faster. While adding more server racks can be both inconvenient and costly, it is possible because physical space is usually available to rent. The opposite is usually true for High Performance Embedded Computers (HPEC) where the physical space envelope for a system is pre-defined and often cannot be extended. For
16 | RTC Magazine JUNE 2015
example, in a cockpit or in-vehicle environment the space may be fixed years in advance so as much functionality needs to be crammed into the available size envelope as possible, and this often includes more specialized devices including high speed analogue I/O, FPGAs for pre-processing, CPUs for analysis, storage, display and control. Legacy HPEC systems often consisted of physically or logically separate elements but there is a trend to migrate more functionality to heterogeneous CPU and GPGPU resources which are relatively easy to program. In an HPEC environment the interconnect is also likely to be different with serial fabrics like Ethernet, PCI Express and RapidIO all being used to connect the elements to provide the necessary real time performance and low latency necessary for a high performance distributed system. While these fabrics offer key technical advantages, there is a lack of support for standards-based user space APIs which could be used as the basis for communication middleware. This can make it a challenge to design a distributed HPEC system with these fabrics.
design paradigm wherein there are multiple data sources and sinks in Distributed Application Distributed Application Distributed Application a system which are loosely coupled. The sources publish themselves as producers of data in a DDS network Communication Middleware Example - Sockets, OpenDDS, OpenMPI while the sinks subscribe to these publishers to consume the data. The subscribers do not need to know the Example - Linux Operating System Example - VxWorks Operating System address of the publishers; the DDS network takes care of data delivery based on the type of data the Communication Fabric subscriber is requesting. Multiple Example - PCI Express, RapidIO, Ethernet publishers/subscribers can join or leave the DDS network without application connection management Figure 1 Distributed System Architecture. Some of the most commonly used communication middleware used in HPEC implications. Other than OpenDDS, systems are Sockets, OpenDDS and OpenMPI. there are many proprietary and optimized versions of DDS for What is standard communication embedded systems which include some additional functional attributes like making efficient use of any additional cores that middleware? are available in modern processors. Communication middleware is a software component that OpenMPI is an open source implementation of Message sits between an application and an operating system providing Passing Interface, which is a language independent standard standards-based abstraction for applications to communicate communication protocol for writing distributed applications. between each other. The application communication paths can It supports both the point-to-point and the collective design be within processes in a single processor module or multiple modules. Communication middleware simplifies the distributed paradigm of distributed applications. It provides a high-level programming abstraction for sending and receiving messages application design by providing a coherent unified view of the without worrying about managing the connection, multiplexing, system communication infrastructure abstracting the operating system communication interfaces along with the fabric commu- etc. This is another design paradigm to write a distributed application that is widely used for a compute intensive application. nication complexities leaving the system architect to focus on One of the examples of the functionality offered by MPI is to actual work in hand, i.e., designing the distributed application. distribute a block of data to different local or remote processes Figure 1 shows where the communication middleware fits in to for split computation and then combine the results with just a a distributed system architecture. single API. The Sockets application programming interface is one of The choice of which communication middleware to use dethe most ubiquitous communication middleware elements pends heavily upon the type of application being designed. It is and is usually based on the Berkeley socket standard. It can be considered analogous to assembly level programming when writing a distributed application. It provides a relatively low level Beam-forming Sonar Input AG AM AM MCH Output A1x/msd C 1x/msd C1x/msd Switch programming interface to distributed appli(SysCon) cation writers and would be the preferred choice when it comes to adhering to strict Data Fabric performance requirements and using limitData Data Data Data Data ed system resources. Sockets are based on a connection-orientated, client/server design paradigm which requires the client to know Control the address of the server in order to commuFabric Control Control Control Control Control nicate. Almost all operating systems support Fabric Fabric Fabric Fabric Fabric sockets as a default in their distribution. OpenDDS is an open source implementaSystem Management Bus tion of Data Distribution Service, which is communication middleware standardized by the Object Management Group (OMG). Figure 2 DDS is based on the published/subscriber Example Sonar Processing System RTC Magazine JUNE 2015 | 17
TECHNOLOGY CORE HETEROGENEOUS SYSTEM ARCHITECTURE How Does Communication Middleware Map onto an HPEC System?
AMC1x/msd (System Controller)
Input Handling Process
Input Data Subscriber
Output Handling Process
Input Data Publisher
Output Data Subscriber
GPGPU Offload Publisher/ Subscriber
Display Input Data Publisher
Disk Array Storage
GPGPU Offload Publisher/ Subscriber
GPGPU Offload Publisher/ Subscriber
Input Data Subscribe
Input Data Subscribe
GPGPU Offload Publisher/ Subscriber
GPGPU Offload Publisher/ Subscriber
AG A1x/msd (Co-processors)
AG A1x/msd (Co-processors)
Figure 3 Sonar Processing System Data Flow Model
quite possible that one might design a system using a combination of communication middleware depending upon the data being processed.
Enabling Open Standard Communication Middleware for HPEC
Unlike Ethernet where most operating systems provide a socket API as a standard way of accessing the fabric, PCI Express and RapidIO lack this standardized API support. Hence a system architect wanting to design a multiprocessor HPEC system around PCI Express or RapidIO fabrics needs to design a proprietary API on top of these fabrics leading to a significant rise in the total cost of ownership of the product along with the risk of using a proprietary solution that is not easily portable. To address this need of trying to encapsulate the complexities of communication over a PCI Express or RapidIO fabric, Concurrent Technologies developed Fabric Interconnect Networking Software (FIN-S) which virtualizes the PCI Express/RapidIO fabrics allowing any existing Ethernet application to run on these interconnects with no change. This high level of portability is achieved in combination with high bandwidth, low CPU utilization and can offer low latency interconnects. The fact that FIN-S allows any socket based application to run on top of PCI Express and RapidIO fabric enables the use of higher level communication middleware like OpenMPI and DDS out of the box along with the low level socket APIs. On OpenMPI, users can use the standard TCP/IP Byte Transfer Layer (BTL) to write their compute intensive distributed application. 18 | RTC Magazine JUNE 2015
Having covered how FIN-S enables the use of different communication middleware based on PCI Express and RapidIO fabric, letâ€™s consider an example of a simple sonar array processing element mapped on to a MicroTCA system constructed of AdvancedMC modules and then look at the data delivery model using DDS middleware so that we can get a practical context of how standard communication middleware can map onto an HPEC syst Figure 2 shows a simplified composition of a multi-processor Sonar system comprising an input module which might contain a DSP/FPGA combination to do the data preprocessing work. On the output side the beamforming module may also have a similar composition to generate the correct signals to be transmitted. The processing algorithms involved in sonar processing are dependent on the number of elements in the array as well as the field of view and this is very computationally intensive. In this example system algorithms would be carried out by multiple Concurrent Technologies AM C1x/msd modules which are based on fourth Generation Intel Cor i7 processors with offload acceleration carried out by AG A1x/msd modules based on NVIDIA Tegra K1 devices. These General Purpose Graphical Processor Units (GPGPUs) are easily programmed using CUDA or OpenCL and consist of multiple cores with the capability of up to 1.4TFLOPS processing performance in a module about the size of a postcard. In a MicroTCA system, all the cards are connected to each other by a MicroTCA Carrier Hub (MCH) and in this example the data plane would be RapidIO Gen 2 with Gigabit Ethernet links on the control plane. Additionally, the AM C1x/msd denoted as SysCon in Figure 2 is acting as a system controller and has additional responsibility of interfacing with the input and output cards along with controlling, display and data storage. The additional AM C1x/msd and AG A1x/msd cards act as co-processors working alongside the system controller in algorithm computation and load sharing. With the system architecture of our sonar processing element defined, letâ€™s now look at the data flow model of this system using the DDS middleware in Figure 3. The AM C1x/msd system controller SBC is comprised of an input data handling process
Figure 4 AM C1X/MSD Module 1
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TECHNOLOGY CORE HETEROGENEOUS SYSTEM ARCHITECTURE which is responsible for streaming the preprocessed data from the module that listens to the sonar data (Figure 4). A subset of this data may be consumed by a compute process on the system controller as required for coordination and management. The compute processes which are responsible for carrying out all the algorithmic computation on the data subscribe to it, split it up into manageable portions and offload by publishing to the GPGPU resources. The GPGPU elements form the work horses of the entire system and can easily be scaled to cope with higher numbers of sonar array elements or more complex beam phasing capabilities. Once the GPGPU offload engines have processed their data they publish their results for reassembly by the AM C1x/msd modules which then publish the final beamforming output. Depending upon the system load, more co-processor boards can be added into the system up to the maximum allowed by the chassis configuration. There is no need to change the
control and monitoring application on the system controller or co-processor devices nor need to know the actual address of the publisher/subscribers; additional compute nodes become part of the DDS network as soon as they boot and can start contributing by dispersing the system load. By virtualizing PCI Express and RapidIO fabric as Ethernet, FIN-S enables the use of standard off the shelf communication middleware allowing the system architect to focus on designing portable, high performance, fabric-agnostic distributed applications rather than expending time and resource in sorting out the fabric level inter-board communication, thus reducing the total cost of ownership of the system. Concurrent Technologies Woburn, MA (781) 933-5900 www.cct.co.uk
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TECHNOLOGY CORE HETEROGENEOUS SYSTEM ARCHITECTURE
Todayâ€™s High-Powered GPUsâ€”Strong for Graphics and for Math Powerful multicore CPUs are increasingly integrating high performance graphics coprocessors on the same die with fast low-latency connections. The parallelism of these coprocessors makes them capable of numeric calculations that rival DSP cores. by Marc Couture, Curtiss-Wright Defense Solutions.
Today, to build advanced embedded processing systems for use in applications such as image signal processing and computer vision, defense system designers use multi-core processors, high capacity memory chips, wide bandwidth fabrics and open software developed for commercial markets. In a recent innovation, system designers are increasingly making use of the graphics processing units (GPUs) integrated within a new generation of Intel x86 architecture chips. To understand the advantages that an integrated GPU offers for aerospace and defense applications, one needs to understand how GPUs function. At a high level, they lend themselves to two broad classes of processing, both of which are needed by defense applications: (1) Rendering images for display (2) Accelerated floating point math operations
What is involved in rendering an image?
An image on a flat screen monitor can be derived via a 2D or 3D computer model. Creation of complex objects usually involves the utilization of very simple shapes, such as triangles, that serve as fundamental graphic building blocks. These objects are then immersed in a scene that defines the overall lighting, surface textures, and point of view. One of the most popular techniques for immersing the objects within a given scene first involves object shading and then rasterization, which geometrically projects the 3-D objects and the scene onto a 2-D image plane, i.e. the monitor. In contrast to these computer-generated images, image signal processing and computer vision applications receive a continuous stream of imaging data from a video camera or electro-optic focal plane array. Two dimensional signal processing techniques are then applied for edge detection and motion blur correction (in addition to myriad other application specific algorithms). The enhanced image is then rendered to a display for use by the human operator. 22 | RTC Magazine JUNE 2015
Figure 1 Greater shading capability enhances image quality.
The original intent of GPUs, and what remains as their core function in commercial applications today, is image rendering. Projecting 3D computer images in motion onto a 2D surface, so as to be convincing to the human eye, is a commonly used but highly compute intensive application. To render a moving image, for example, requires a tremendous number of calculations per frame as the GPU renders simple polygons to create more advanced objects, maps textures to simulated surfaces, and then rotates these shapes within dynamically changing coordinate systems. Image signal processing and computer vision perform different operations, but are equally intensive in terms of computation throughput requirements and use math algorithms highly similar to those used by image rendering. Rendering video frames requires the continuous streaming of data. By design, GPUs are optimized for streaming processing. To manage these data streams they first boost throughput by parallelizing their compute engines via a massive pipeline architecture. Then they add the high-bandwidth, high capacity memory that is central to this model given the relentless flow of high resolution imagery.
Figure 2 Core i7 Architecture Diagram
In recent years, the streaming processing capability of GPUs has been further enhanced by the incorporation of “programmable shaders.” These shaders perform highly sophisticated shading effects (e.g. volumetric lighting, normal mapping, and chroma keying); they are optimized at the silicon level to execute the algorithms associated with this type of processing. Powerful new GPUs include large numbers of these shaders to help accelerate the rendering of highly complex, life-like images (Figure 1).
How, and why, does a GPU accelerate floating point math?
With the advent of programmable shaders, which are inherently adept at vector and matrix math, the use of GPUs to work on problems outside of rendering graphics has become a reality. Vector and matrix data manipulation are fundamental to linear algebra, filtering, and transforms, which are all components of digital signal processing (DSP). While data formats were originally integer based, a growing need for high dynamic range imaging resulted in the development of floating point data formats. The use of floating point data set the course in motion for GPUs to be used as floating point math accelerators in a multitude of commercial and defense related high performance compute applications. When used in this fashion, a GPU is often referred to as General Purpose GPU ( GPGPU). Thanks to the sheer number of shaders in GPGPUs, coupled with a high throughput streaming pipeline architecture, it’s now possible to perform scalable, massive parallel processing that would otherwise far outpace the floating point performance of SIMD units found within standard CPUs. Discrete GPGPUs are often coupled with high throughput, high capacity GDDR5, a type of synchronous graphics RAM based on DDR3 SDRAM. This is required for buffering high frame rates of high resolution graphics data, but is also highly advantageous for buffering the ingest and egress of wideband sensor data. Until very recently, GPUs have only existed as unique chips. As discrete pieces of silicon, GPUs have traditionally relied on external host CPUs, typically Intel-based, since they themselves are not governed by an operating system. The host CPU directs the instructions to be executed by the GPU, as well as identify-
ing the input source and output destination for data streams. GPUs are often deployed on full length PCI cards, placed in Intel-based workstations. They are also incorporated directly onto CPU motherboards. MXM (Mobile PCI Express Module) is a modular format for GPUs that, in addition to use in high-end consumer products, is also used in high performance embedded computing (HPEC) applications. One example is a single MXM module on a 3U OpenVPX carrier board. In another example, another two MXM modules are hosted on a 6U OpenVPX carrier. These carriers are typically placed in adjunct slots alongside Intel SBC or Intel/FPGA DSP boards with a multi-lane PCIe super highway providing the interconnect for streaming data ingest/egress. Rendered graphics destined for displays are output directly from the GPUs over display signal ports. More recently, ARM cores that do run operating systems are also finding their way into discrete GPUs. And, as will be discussed later, there are other architectural approaches that provide new ways to integrate GPUs into systems.
Programming a GPU
Within the software domain, the most popular and ubiquitous API for drawing and rendering graphics is undoubtedly OpenGL, which is maintained by a not-for-profit consortium called the Kronos Group. However, when it comes to math acceleration, there are two main choices. One option is Compute Unified Device Architecture (CUDA) from the GPU silicon manufacturer, NVIDIA. The other option, a bit newer and also from the Kronos Group, is Open Computing Language (OpenCL). CUDA strictly targets NVIDIA GPUs for use as GPGPUs. CUDA is based on the C programming language and is predicated on a parallel computing programming model designed to gain massive throughput by executing many threads concurrently. The big advantage to CUDA is that it exposes optimized, intrinsic functionalities buried within the NVIDIA GPU silicon. For example, CUDA enables thread usage of shared memory regions, a previously cited omission of GPUs. In general, reviews from CUDA developers have been very favorable within the High Performance Computing (HPC) community. On the other hand, a big disadvantage with CUDA is that it is proprietary and closed to silicon other than NVIDIA GPUs. OpenCL, also based on C, provides parallel computing constructs. The main differentiation between CUDA and OpenCL
Figure 3 A Silicon View of the Core i7 Architecture
RTC Magazine JUNE 2015 | 23
TECHNOLOGY CORE HETEROGENEOUS SYSTEM ARCHITECTURE 128 MB). Outside of using external DDR3 memory, the method for getting into and out of the Core i7 is through lots of PCI Express Gen 3 lanes. The embedded GPU within a Core i7 is available in several different sizes; one of the more popular sizes is the GT2 (a.k.a HD Graphics 4600), which has 20 shader processors, referred to as Execution Units (EU). These EUs produce >350 GFLOPS of single precision floating point processing. Additionally, the GT2 supports three display ports for rendering graphics (Figure 3). Figure 4 The CHAMP-AV9 6U OpenVPX DSP Module
lies in the fact that OpenCL targets and executes across a whole spectrum of heterogeneous platforms including GPUs, CPUs, DSPs, and even FPGAs. Because of its openness, OpenCL is portable and has the ability to bridge heterogeneous computing elements within the same system or even the same silicon. The disadvantage of OpenCL, which can sometimes be experienced in the level of abstraction from the underlying silicon and optimization mileage, will vary depending on OpenCL implementation by the associated silicon vendor. Great progress is being made in this regard by the various chip manufacturers and the community is growing at a much faster rate due to the variety of target silicon that is available.
How GPUs have evolved
Like other silicon devices, GPUs have seen, and continue to see, a steady increase in core count within a fixed power footprint, which is driven by lithography advances that increase die density. This increased core count creates an ever greater performance-to-power (i.e. FLOPS to Watt) ratio in all device architectures, with GPUs currently in the lead. As CPU cores (e.g. ARM) find their way onto GPU dies, GPUs are achieving a new level of autonomy. This is enabling GPUs to assume functions within a system well beyond that of a mindless Giga/Tera FLOPS monster. Historically, Intel CPUs have been coupled on motherboards with discrete GPUs from NVIDIA or AMD. While Intel’s integration of the GPU device onto the Mobile Class die was partly spurred by marketplace contentions, there are also definitive technical advantages to subsuming the GPU, such as removing PCB complexities and reducing thermal dissipation. The aerospace and defense industry is a direct beneficiary of this development as the Core i7 now provides a very powerful heterogeneous CPU+GPU core in which the GPU can be used to drive monitors or to process extreme sensor feeds. The Intel Core i7 Gen 4 (Haswell) contains four x86 cores, each with its own dedicated AVX2 SIMD unit and each with an exclusive L1/L2 cache (Figure 2). There is a larger L3 cache (4-8 MB) that is “shared” among all four cores and the internal graphics processor (integrated GPU). This sharing is accomplished via a high speed ring bus (> 300 GBytes/sec) that serves as the data transport mechanism. Additionally, some of the Core i7 chip variants also have embedded DRAM (eDRAM) that effectively functions as a Level 4 cache (victim cache to L3, up to 24 | RTC Magazine JUNE 2015
Advantages for aerospace & defense electronics
Not every aerospace and defense application is a good candidate for eschewing a discrete NVIDIA or AMD GPU in favor of the embedded Intel Mobile Class GPUs. Those applications that require a discrete GPU include those needing TFLOPS of processing and/or GBytes of external GDDR5 DRAM (supported by MXM modules with the larger discrete GPUs). However, there are applications than can greatly benefit from the onboard GPU in the Core i7. For these applications the GFLOPS performance, excluding CPU AVX2 units, meets the need and the memory capacity is sufficient. For SWaP-constrained aerospace & defense applications, one obvious advantage of Core i7’s is the removal of an entire adjunct GPU board (or more), which equates to an entire FRU slot for a deployed chassis, and saves size, weight, power, and overall cost for the entire system. Another key advantage provided by an onboard GPU is the extremely low latency made possible by its proximity to the CPU cores. With all the CPU cores and the GPU interconnected by a lightning-fast ring bus and passing data at the caching level, latency benchmarks are greatly improved when compared to data transport to/from an Intel CPU device on one board and a discrete GPU on hosted on a second board and interconnected via PCI Express.
Example use cases
GPUs are increasingly being used in aerospace & defense applications, as image renderers (GPUs) and math accelerators (GPGPUs). Meanwhile, both the discrete GPUs and the integrated GPUs are growing in terms of performance and memory capacity. Which type makes the most sense is really a question that needs to be answered by the requirements of the particular program. Today, we are seeing GPUs being used to render video displays for 360° situational awareness inside modern military platforms. This enables the pilot or driver to effectively “see through” the ceiling, walls and floor of a vehicle. Even more popular, is the use of GPUs to capture image sensor data (e.g. via gigapixel cameras), followed by real-time image manipulation, optimization, and display. This latter application is becoming particularly popular with Unmanned Aerial Vehicles (UAVs) tasked with carrying multiple camera types (i.e. electro-optic and infrared). These cameras need to be ortho-rectified and stitched together, just for starters. Sensor data other than standard imagery is also a target for
GPUs. STAP and SAR radar, which are hungry for FLOPS, are seeing pulse compression and Doppler processing occurring in GPUs. SIGINT applications requiring high throughput, wideband frequency domain analysis are also being targeted by GPUs. The embedded GPUs are increasingly attractive for some applications because of their proximity to the CPU cores all on the same die. Applications with stringent latency requirements, in addition to processing throughput, can greatly benefit from a heterogeneous processor such as the Intel Core i7, thanks to the tightly coupled ring bus infrastructure between the embedded GPU and the AVX2 enabled x86 cores. Electronic warfare (EW) applications, such as Cognitive EW, that had been dismissive of discrete GPUs due to high latency, are now considering the integrated device as it gives them the throughput of the GPU, the cognitive capabilities of the CPUs, and the low latency of the ring bus interconnected caching. OpenCL, as previously discussed, is the software enabler giving developers the access they need to realize the benefits of this heterogeneous device. An example of a design implementation incorporating embedded GPUs is Curtiss Wright’s CHAMP-AV9 Intel Core i7 Multiprocessor 6U OpenVPX DSP Board (Figure 4). This module brings two Core i7 processors onto a single PCB and is designed to withstand the severe environments typical of aerospace & defense applications. The combined GFLOPS metric for just the AVX2 SIMD units on the board’s two Haswell Core i7’s equates to 614 GFLOPS. What’s more, if the Core i7s’ embedded GT2 GPUs are used as GPGPU math accelerators, we see an overall total of 1,318
GFLOPs of processing power. Alternatively, if the GPUs were leveraged to render displays, the CHAMP-AV9 provides for a total of 6 individual display ports, three per Core i7 device. One important consideration to take into account when designing with the Core i7 is the importance of providing ample memory throughput and capacity, as well as high speed I/O, and lots of it. Rarely are GPUs compute bound; they are much more likely to suffer from being memory bound or I/O bound. The CHAMP-AV9 employs up to 32 GBytes of DDR3 to tackle memory capacity in addition to the routing of all genres of high speed I/O on and off module. Signal integrity over an extended temperature range is also of particular importance as the board routes 1,600 MHz memory lanes, PCIe Gen 3, Display Port, and 40GigE/ InfiniBand in a very tight 6U OpenVPX footprint. The card employs Curtiss-Wright Fabric40™ technology to address this issue and ensure high signal integrity at the extreme signaling rates used by high bandwidth fabrics. System designers must regularly evaluate the many choices of processing elements available on the market, selecting the architecture that best meets the needs of a specific program. GPUs integrated within Intel’s Core i7 processors are a recently available processing variant, with significant advantages to many types of aerospace and defense applications. SWaP savings, high performance, low latency and enhanced security are all characteristics of these integrated GPUs. Curtiss-Wright Defense Solutions Ashburn, VA. (661) 705-1142 www.cwcdefense.com
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TECHNOLOGY CONNECTED OPTICAL CONNECTIVITY IN SYSTEM DESIGN
Harnessing Optical Links for Embedded Systems Advances in optical interface technology boost performance levels to help meet increasing data rates and signal bandwidths while improving signal integrity and security, and greatly extending distance between system components. New specifications are defining open industry standards that will offer many advantages over traditional copper connections. by Rodger Hosking, Pentek
One major shortcoming of copper cable is signal loss, which becomes a serious limitation for higher frequency signals and longer cable lengths. Across a span of 100 meters, optical cables can sustain data rates up to 100 times higher than copper cable. Because copper cables radiate electromagnetic energy, eavesdropping on network cables is a major security concern, not only for military and government customers, but also for corporations, banks, and financial institutions. Advanced signal sniffers in vehicles and briefcases are hard to detect and restrict. Optical cables are extremely difficult to “tap” without damaging the cable, resulting in immediate detection. Signals flowing in copper cables are also susceptible to contamination from nearby sources of electromagnetic radiation, such as antennas, generators, and motors. This is critical for military and commercial aircraft and ships, as well as manned or unmanned vehicles, which are often packed with dozens of different electronic payloads. Optical cables are completely immune to EMI and even lightning discharges. A summary of the advantages and disadvantages is given in Table 1. Physically, optical cables are much smaller and lighter than
Figure 1 Pentek 52611 Quad SerialFPDP 3U VPX Module supports four full-duplex LC optical cables for connections between chassis, each operating at over 400 MByte/s.
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copper cables—especially important for weight-sensitive applications such as weapons, unmanned vehicles, and aircraft. Optical cables will operate just as well when submerged in seawater, and are completely immune to electrical shorting, which is especially important where explosive vapors may be present. To ease installation through conduits and passages, optical cables have smaller diameters and can withstand up to ten times more pulling tension than copper cables. Driven by huge commercial markets for data servers, storage networks, telecom systems, and home and office internet and entertainment systems, optical interfaces are replacing older copper connections for good reasons: cost and performance. As the use of optical cables becomes more widespread, the cost per length can be much lower than copper cables that depend on commodity metal pricing. As is often the case, industrial, military and government embedded systems are now taking advantage of the many benefits of this rapidly advancing commercial technology.
An optical cable is a waveguide for propagating light through an optical fibre. It consists of a central core clad with a dielectric material having a higher index of refraction than the core to ensure total internal reflection. Optical cables use either multimode or single-mode transmission. Multi-mode cables accept light rays entering the core within a certain angle of the axis. They travel down the cable by repeatedly reflecting off the dielectric boundary between the core and the cladding. The core diameters are typically 50 or 62.5 μm, and the wavelength of light is typically 850 nm (Figure 1). Single-mode cables propagate light as an electromagnetic wave operating in a single transverse mode straight down the fibre using typical wavelengths of 1310 and 1550 nm. The core diameter must be no greater than ten times the light wavelength, typically 8 to 10 μm. Although single-mode cables can carry signals over lengths 10 to 100 times longer than multi-mode, the transceivers are more expensive. Hundreds of different types of optical cable connectors exist
Interface Transceiver Cost
High but dropping
PC Network Interface Cards
Integrated in PC or laptop
Usually optional at $100-$200
Power over Ethernet
Supported at low cost
Cable Loss - 100 meters
Max Transmission Distance
100 m (cat 6)
300 m (multi-mode)
EMI Susceptibility Risk
EMI Radiation Risk
Security / Eavesdropping Risk
Cable Cost per Length
Cable Weight per 1000 m
60 to 600 kg
Supports current flow if shorted
Table 1 Advantages and disadvantages between copper and optical interfaces
in the market, each addressing specific applications and environments. The challenge is connecting the ends of two optical cables to retain the maximum fidelity of the light interface, in spite of human factors, tolerances, contamination, and environments. Special tools and kits for cleaning the ends of each optical fibre are essential for reliable operation.
Coupling electrical signals to light signals for transmission through optical cables requires optical transceivers. Most systems require full duplex operation for each optical link to support flow control and error correction. A pair of optical fibers, often bonded together in the same cable, supports transmit and receive data flowing in opposite directions. Although several analog light modulation schemes (including AM and FM) have been used in the past, now almost all transceivers use digital modulation. Optical emitters simply translate the digital logic levels into on/off modulation of the laser light beam, while the detectors convert the modulated light back into digital signals. This physical layer interface for transporting 1â€™s and 0â€™s is capable of supporting any protocol. The latest transceivers use laser emitters to support data rates to 100 Gbit/s and higher, and each generation steadily reduces the power, size and cost of devices. Different technologies are required for emitters and detectors, but both are often combined in a single product to provide full-duplex operation. Optical transceivers thus provide a physical layer interface between optical cables and the vast array of electrical multi-gigabit serial ports found on processors, FPGAs, and network adapters. As a result, optical transceivers are transparent to the protocols they support, making them appropriate for a virtually any highspeed serial digital link. Electrical signals of the optical transceivers connect to the end point device, which must then handle clock encoding and recovery, synchronization, and line balance at the physical layer. Data link layer circuitry establishes framing so that data words can be sent and received across the channel.
Choosing the right optical protocol
Protocols define the rules and features supported by each type of system link, ranging from simple transmission of raw data to sophisticated multi-processor support for distributed networks, intelligent routing, and robust error correction. Of course, heavier protocols invariably mean less efficient data transfers and increased latency. Generally, it is best to use the simplest protocol that satisfies the given system requirement. As an example of a lightweight protocol, Aurora for Xilinx FPGAs features on-board link-layer engines and high-speed serial transceivers. Aurora is intended primarily for point-to-point connectivity for sending data between two FPGAs. It includes 8b/10b or 64b/66b channel coding to balance the transmission channel, and supports single- or full-duplex operation. Aurora handles virtually any word length and allows multiple serial lanes to be bonded into a single logical channel, aggregating single lane bit rates for higher data throughput. Data rates for each serial lane can be 12.5 Gbit/s or higher. Extremely simple and with minimal overhead, Aurora is very efficient in linking data streams between multiple FPGAs within a module, or between modules across a backplane. Stepping up in complexity is the SerialFPDP protocol defined under VITA 17.1 It addresses several important needs of embedded systems, including flow control to avoid data overruns, and copy mode to allow one node to receive data and also forward it on to another node. The copy/loop mode supports a ring of multiple nodes eventually completing a closed loop. The nominal data rate on each lane is 2.5 Gbit/s, but advances in device technology now support rates over twice that speed. Infiniband defines a flexible, low-latency, point-to-point interconnect fabric for data storage and servers with current rates of 14 Gbit/s, moving up to 50 Gbit/s in the next few years. Channel speeds can be boosted by forming logical channels that bond 4 or 12 lanes. The venerable Ethernet protocol still dominates computer networks, with 10 GbE now commonly supported by a vast range of computers, switches, and adapters. Even though Ethernet suffers from high overhead, making it somewhat cumbersome for high data rate low latency applications, its ubiquitous presence virtually assures compatibility.
New features for VITA 49 â€“ VITA Radio Transport (VRT) protocol
Approved as an ANSI standard in 2007, VITA 49 defines standardized packets for connecting software radio systems for communications, radar, telemetry, direction finding and other applications. The original specification addressed only receiver functions. Receive signal data packets deliver digitized payload data, a precise time stamp, and identifiers for each channel and signal. Context packets include operating parameters of the receiver including tuning frequency, bandwidth, sampling rate, gain, antenna orientation, speed, heading, etc. One notable shortcoming of the original specification was its inability to control the receiver. RTC Magazine JUNE 2015 | 27
TECHNOLOGY CONNECTED OPTICAL CONNECTIVITY IN SYSTEM DESIGN VITA 49.2, a new extension to VRT now in balloting, adds control packets for delivering operational parameters to all aspects of the radio equipment, as well as support for transmitters (Figure 2). The new stimulus packets contain streaming digital samples of signals to be transmitted. Other new packets, called capabilities packets, inform the host control system of the available hardware in the radio along with the allowed range of parameters for control. Lastly, spectrum packets from the receiver deliver spectral information to help simplify spectral survey and energy detection operations required by the control system. With this latest extension, VRT provides a standardized protocol for controlling and configuring all aspects of a software radio transceiver. One major objective is enabling a common radio hardware platform to handle a wide range of applications simply by implementing new host software algorithms that exploit VRT protocols to achieve the required modes of operation.
New Optical Interfaces for VPX
Although optical interfaces using various connectors and cable types have been deployed in embedded systems for years, most of them use front panel connections. This can be a maintenance issue and is often not permitted in conduction cooled systems. The VITA 66 Fiber Optic Interconnect group has developed a set of standards that bridge optical connections directly through the VPX backplane connector. The first three are variants for 3U and 6U systems and are based on MT, ARINC 801 Termini, and Mini-Expanded Beam optical connector technology, respectively. The metal housings are physically dimensioned to replace one or more of the standard MultiGig RT-2 VPX bladed copper connectors. The high-density MT variant defined in VITA 66.1 provides the highest density of the three, with up to 12 or 24 pairs of optical fibers, while VITA 66.2 and 66.3 each provide 2 pairs. A fourth standard soon to be released, VITA 66.4, uses the MT
VITA 57.1 High Pin Count FMC Site
4GB DDR3 SDRAM 128
Flexor Virtex-7 FPGA VX330T or VX690T
12x Gigabit Serial I/O x8 PCIe Gen3
Firefly Optical Transceivers 12 Optical Full Duplex Lanes VITA 66.4
VPX P2 (1/2)
VPX P2 (1/2)
3U VPX Backplane
Figure 2 New extensions to the VITA Radio Transport protocol define standardized packets for control and status of radio receiver and transmitter equipment, as well as digitized receive and transmit signal payload packets for added flexibility.
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Figure 3 Pentek Model 5973 3U VPX Virtex-7 FMC carrier is the industryâ€™s first VITA 66.4 optical backplane product. Samtec FireFly optical transceivers deliver data rates up to 12 GByte/s full duplex to the backplane supporting a wide range of protocols implemented within the FPGA.
ferrule but with a metal housing half the size of VITA 66.1, thus occupying only half of the 3U VPX P2 connector position. These housings are available from major vendors, including TE Connectivity and Molex. To simplify implementation, Samtec offers its FireFly Micro Fly-Over system. It consists of a 12 pairs of optical fibres installed in an MT ferrule. One 12-lane optical flat cable connects to a small VCSEL laser emitter module and the other connects to a detector module. Figure 3 shows an implementation of the emerging VITA 66.4 standard, the Pentek Model 5973 3U VPX Virtex-7 FMC carrier. Here the electrical interfaces of the FireFly emitter and detector modules are connected directly to the GTX serial transceiver pins of the Virtex-7 FPGA. Today, FireFly transceivers are rated for 14 Gbit/s with 28 Gbit/s versions coming soon. With the 5973 operating at nominal data rates of 10 Gbit/s through each optical fibre using Aurora protocol, the backplane throughput is 12 GByte/s, simultaneously in both directions. The first version of this product uses multi-mode transceivers and cable to support cable lengths of 100 meters or more. Single-mode transceivers will extend the distance to several kilometers. A wide range of MT optical cables and connector products allow board-to-board connections across the backplane, and backplane-to-chassis connections for external MTP cables to remotely located systems. The 12 GByte/s VITA 66.4 optical interface compliments the 8 GByte/s Gen 3 x8 copper PCIe interface on VPX P1, offering plenty of I/O for demanding applications. System engineers can now choose between optical and copper links to solve high data rate connectively requirements and take advantage of the benefits of each technology. Pentek Upper Saddle River, NJ (201) 818-5900 www.pentek.com
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RTC Magazine JUNE 2015 | 29
TECHNOLOGY IN SYSTEMS AUTOMOTIVE SYSTEMS
Compliance with ISO 26262 Causing Headaches? Here’s help. The vast increase in the software content of automobiles along with stringent requirements for safety and reliability has added complexity to the process of development and compliance with standards. Any serious operation will require tools to track development and document compliance. by Mark Richardson, LDRA
Software code is a major component of any car or truck in production today and when that code works, vehicles can parallel park themselves, automatically adjust speeds, and switch from electric to gas power in an instant. When code fails, however, tragedy can occur. In one recent example, faulty electronic throttle source code was blamed for causing unintended acceleration, leading to a wrongful death suit. As a result of the injuries or deaths caused by these types of events and because of the cost of litigation, governments, automakers, and consumers are now placing a much greater emphasis on safety. Safety has become a significant factor in the development of automobile systems and, with the ever increasing use of E/E/PE systems in areas such as driver assistance, braking and steering systems and safety systems, this significance is set to increase.
Test Phases 4-8 Item integration and Testing
4-7 System design
Scope of Part 4
6-6 Specification of software safety requirements
Scope of Part 6
6-7 Software architectural design
6-8 Software unit design and Implementation
6-11 Verification of software safety requirements
6-10 Software integration and testing
6-9 Software unit testing
Guidelines for Assessing Risk
The ISO 26262 standard provides detailed industry-specific guidelines for the production of all software for automotive systems and equipment, whether it is safety critical or not. It also provides a risk-management approach including the determination of risk classes, known as automotive safety integrity levels (ASILs) which are similar in nature to the safety integrity levels (SILs) specified in the IEC 61508 standard. The four levels of ASILs (A-D in ISO 26262) specify the necessary safety measures for avoiding an unreasonable residual risk, with D representing the most stringent level. The ASIL is a property of a given safety function, not a property of the whole system or a system component. Each safety function in a safety-related system needs to have an appropriate ASIL assigned with the risk of each hazardous event evaluated based on the following attributes: • Frequency of the situation (or “exposure”) 30 | RTC Magazine JUNE 2015
Figure 1 You can map the scope of the ISO 26262 part 4 and part 6 onto the familiar V development model.
• Impact of possible damage (or “severity”) • Controllability The values that are determined for these three attributes, then in turn, determine the appropriate ASIL that is assigned for a given functional defect. This then determines the overall ASIL for that safety function. ISO 26262 translates these safety levels into safety-specific objectives that must be satisfied during the development pro-
1. Introduction 2. Software Description 3. Software Lifecycle 4. Other Considerations 5. Software Lifecycle Environment
Figure 2 Here’s an extract from an SPP Template specifying the design and coding guidelines.
cess. An assigned ASIL therefore determines the level of effort required to show compliance with the standard. So, the effort and expense of producing a system critical to the continued safe operation of an automobile (e.g., a steer-by-wire system) is necessarily higher than that required to produce a system with only a minor impact in the case of a failure (e.g., the in-car entertainment system). Part 4 of ISO 26262 focuses on the product development at the system level and part 6 relates to the product development at the software level. A handy illustration from Wikipedia shows how the scope of these documents maps onto the familiar “V” model (Figure 1). Now that the risk is known, what steps are needed to demonstrate compliance to the ISO 26262 Functional Safety Standard? There’s an industry mantra that quickly sums up what’s needed: • Say what you do • Do what you say • Show what you did (i.e., show that you met the objectives for the specific ASIL)
Subsequently, each of these sub-sections has a series of steps that it must follow to achieve compliance and safe practice. Table 1 outlines the steps required and defines the expected content for each step. Figure 2 provides a snapshot of how the SPP looks when fleshed out. Clearly, proper process involves tracking a lot of details. Traditionally, companies managed these artifacts with Excel spreadsheets that they would update as work was completed. However, with the increased complexity of software development, such methodologies are prone to creating errors. Modern software tools can capture these requirements, add placeholders for the various artifacts that will need to be produced, and automatically update process status as code, tests, etc. are completed. For compliance, this process also automatically documents updates throughout the software development lifecycle, removing a significantly time-consuming step in the certification process.
Do What You Say
Once you’ve outlined your processes in the SPP, you need to follow them. Both the SPP and OPP are approved by the relevant regulatory oversight body. It is important to collect and collate evidence that the processes were followed. Often, it can help to use software tools that provide process compliant templates for documents identified in the SPP. Be aware that the SPP specifies that a “Design and coding guidelines” document is required. Any violations need to be corrected, but in case of undecidable rules (MISRA-C: 2012) or specific instances where a deviation from a non-mandatory rule is needed, then a justification needs to be added. In addition, as you’re implementing your plan, you always
Say What You Do
In short, you must describe your processes in your plans. This requires the initial creation of a Software Project Plan (SPP), essentially a sub-plan of the Overall Project Plan (OPP), which addresses the software-related requirements of ISO 26262. The SPP needs to cover all the sub-clauses and activities defined to satisfy all the applicable sub-clause requirements. Any activities that are not required for all ASILs can be tailored out per ISO 26262-2. The SPP should include at least the following five sections:
Figure 3 The LDRA Certification Management System enables companies to organize their compliance process, providing compliance plans, process checklists, and problem reports to help you manage certification planning, development, verification, and regulatory activities.
RTC Magazine JUNE 2015 | 31
TECHNOLOGY IN SYSTEMS AUTOMOTIVE SYSTEMS Objectives
Ties into the objectives defined in ISO 26262-6
Lists the required and optional data used as input to the clause-specific process
Cites step-by-step instructions for successful execution of the clause in accordance with the assigned ASIL and applicable requirements and recommendations
Requirements and Recommendations
Cross-references the ISO 26262-6 requirements & recommendations to the SPP process paragraph that addresses them
Lists the required and optional data created or updated as output from the clause-specific process
Identifies the work product reviews used to check that the data is ready for use in downstream processes
Phase Exit Review
Identifies all process-compliance reviews used to show that all elements of the clause-specific process have been successfully completed
Table 1 After creating a Software Project Plan, you need to detail each step per these components.
need to track that youâ€™ve adjusted your processes to the risk levels associated with that piece of software. Table 2 outlines the risk levels and shows how effectively tools can help implement the necessary compliance checks:
Show What You Did
The third step: document what you did. In this step, you must ensure you can show consistent reviewed data, provide checklists for the required document content, and show impeccable record keeping for your document reviews. Tools, such as the LDRA tool suite, neatly dovetail with the LDRA Certification Management System, as a review and analysis management system that helps record review attendance, provide checklists for all SPP defined reviews and document process reviews (Figure 3). Tools that manage change control, track issues through resolution, and provide records of process compliance can save companies thousands of hours of documentation effort and up to 50 percent of their process costs.
Table 2 The complexity of software has made software test tools a necessity. Here you see the potential efficiency gains that can be made in gaining compliance for specific programming requirements.
TRACE32 for AMP
TRACE32 for SMP
Debug & Trace
32 | RTC Magazine JUNE 2015
TRACE32 for AMP
A tools-based methodology can be used to cost-effectively manage an ISO 26262 compliant product development life cycle. The methodology must be based on a compliance management system that provides a roadmap to help manage the software planning, development, verification, and regulatory activities. Using this roadmap, development teams can walk through the fully compliant plans, document checklists, transition and peer review checklists, standards and other required lifecycle documents, such as requirement specifications. When expanded to include deterministic software verification tools, the compliance management system can also streamline verification processes, further reducing hundreds of hours of documentation effort and achieve up to 50 percent reduction of planning costs.
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RTC Magazine JUNE 2015 | 33
TECHNOLOGY DEVELOPMENT MOBILE SYSTEMS
Design Once, Use Many: The Need for a Common Hardware/Software Solution for Mobile Computing Enterprises are increasingly seeking common hardware and software platforms to support their business class applications. Today’s current challenge is the lack of flexibility with mobile hardware designs that support both small and large screen form factors across ruggedized devices. by Geoff Goetz, Bsquare
If there is one constant in the world of enterprise computing, it is the rapid rate of change. New and better mobility solutions are gathering, analyzing and taking action on ever increasing amounts of data. New hardware form factors - based on multiple operating systems – are emerging to offer increased speed and functionality. And new applications are being developed to support and customize all of the above. As enterprises work to manage all of this change within their available resources, one reality is clear. A common platform for enterprise applications, one that cuts across multiple form factors and leverages existing infrastructure investments, would save OEMs and their customers time, money and frustration. This is particularly true in the market for durable and rugged class handheld devices and industrial tablets, which see constant use on the front lines of data acquisition and management.
Market Trends and Realities
Industry analyst VDC’s most recent estimates quantify a 1.1 million installed base of rugged tablets, and an installed base of an additional 15 million rugged handheld devices. In this category, Microsoft holds approximately 85% of the market share with Windows Compact or Windows Embedded Handheld 6.5, the leading OS for rugged handhelds, and Windows 7/8 the leading platform for rugged tablets. The majority of currently available devices, especially handheld terminals, utilize previous generation operating systems that are technologically out of date. While these operating systems still have several years of availability remaining, the success of current generation operating systems such as Android, iOS and Windows Embedded 8.1 Handheld are in question.
34 | RTC Magazine JUNE 2015
A potential way forward is the Windows Embedded 8.1 Handheld Program. However, only a limited number of OEMs have access to this operating system. Additionally, the OS requires the use of Qualcomm processors, which bring inherent engineering and supply chain challenges. This is leading to very limited adoption of Windows Embedded 8.1 Handheld at the OEM and enterprise levels. Windows 10 Embedded is on the horizon as the next generation operating system. Although technology previews of Windows 10 are currently available, as of this writing there is no official release date nor specific data on processor support. This creates further uncertainty with device manufacturers and enterprises alike who need to make decisions on their own device and application roadmaps. In the face of all this ambiguity, enterprises are examining how to best take advantage of new mobile devices while leveraging existing lines of business applications. And these new durable class devices are arriving at an alarming clip. iOS and Android-based devices are being deployed in growing numbers, but facing challenges. There are limited enterprise class applications for these operating systems, and IT departments struggle to integrate them. Because these iOS and Android devices are designed primarily for consumer use, they may require an accessory sled or custom bumper to behave as a ruggedized device. Not surprisingly, they face high failure and damage rates when they are deployed in the market and dropped, smashed or even stolen. The theft rate for iPads and Android tablets in commercial use is quite high – adding to increased investment needs on the part of the customer.
Figure 1 5” tablet with Windows 8 desktop
In summary, the market need is growing while the hardware capabilities and operating systems are being challenged as never before. Add to this the need for custom applications that can be deployed across multiple form factors, and you have an environment for OEM and enterprise dissatisfaction.
The Customer’s Perspective
OEM and enterprise customers are straightforward about their needs: they must get to market faster on the most current devices possible. Because it has been a significant length of time from the last major improvement in silicon and OS options for handheld devices, there is a need to rapidly deliver next generation devices. Ideally the OEMs would find a single, combined hardware and software platform with which to create a portfolio of devices that share common applications, user experiences, device management and security. In reality, many ‘new’ handheld terminal device introductions are in fact based on older silicon or OS, or are consumer class devices devoid of the features and functionality required for true integration into the enterprise. And it is becoming the end of an era. The more traditional handheld devices and applications are reaching the functional end of life, the hardware is reaching the end of its manufacturing cycle, and the operating system and applications features and functionality are outdated. The need for seamless integration across multiple form factors is particularly pressing. Most enterprise organizations have a growing mobile workforce, and those workers are using a variety of tablets, smartphones and other handheld devices. Some of the devices are based on Windows, others on Android and still others on iOS. How to support this collection of devices, collection of operating systems and myriad of applications is a constant puzzle that drains time and resources. Ideally the latest generations of technology would be available to, and easily integrated by, these OEMs and enterprises. With the release of Intel’s latest mobile optimized Atom solutions, device manufacturers and enterprises now have a silicon base on which to develop and deploy lines of business solutions using the latest mainstream operating systems such as Windows Embedded 8.1 and Android 4.4. Access to this generation of hardware and software solutions now allows for the development of cross-platform solutions that scale from the smallest
of handheld terminals to tablet size and beyond. For example, the development of a line of business application for a Windows 8.1 environment can now be easily scaled from a desktop to a handheld terminal through relatively minor variations in how the application is rendered on multiple screen sizes. To extend this concept, the use of multiple platform development tools such as Xamarin allows for code reuse across differing operating systems, furthering the concept of a true cross platform solution. The hardware design of ruggedized devices could use improvement. This is where the consumer devices excel: they have a functional elegance that embodies the best of industrial design. However, they are not durable enough to be practical in a rugged commercial environment. Customers want the simplicity of the consumer design with the ruggedness of a durable device. Supply chain flexibility is another top priority for these OEMs and enterprises. An open supply chain that enables them to source products and services through their existing relationships gives them great flexibility in licensing and the ability to support lower volume manufacturing scenarios but is often not available. The applications that run on handheld terminals are another important consideration. Significant investments are made in application design, deployment and training so it is crucial that legacy desktop applications are able to flow into the mobile environment. However, moving legacy ‘mobile’ applications requires time consuming rewriting, regardless of the targeted operating system or device type. How an enterprise manages its applications across multiple form factors and operating systems can define a project’s success or failure. A summary of these factors and considerations can be seen in Table 1.
A Way Forward: A Common Reference Platform
Bsquare MobileV offers a robust, production-ready reference platform running on the Intel Atom Z3745 processor and Windows Embedded 8.1 or Android 4.4. MobileV shortens time to market, lowers development cost and enables differentiated user experiences. It also delivers cross-platform legacy and modern application support for OEMs who build durable and rugged class handhelds and industrial tablets. MobileV provides a common reference platform for OEMs building multiple device form factors including durable and
Figure 2 5” tablet with Bsquare MobileV UX experience implemented on Windows 8
RTC Magazine JUNE 2015 | 35
TECHNOLOGY DEVELOPMENT MOBILE SYSTEMS rugged class handhelds and industrial tablets. The solution combines Microsoft Windows Embedded 8.1 or Android 4.4 with cutting-edge Intel mobile board reference designs from Aava Mobile, a global leader in tablet and handheld design, along with Bsquare proprietary MobileV UX software. The technical specifications for the 5” form factor represent one of the first mini-tablets of this size on the Intel and Windows 8 platform. Technical highlights include the Intel Atom Z3745 quad-core CPU, a 4.7” multi-touch display at 1280x720 pixels, 2 GB RAM, 8MP main and 2MP front cameras, extensive interfaces and sensors to support vertical market use-cases. The standard reference design also allows for inclusion of a 3G/LTE modem for cellular data. OEMs will also appreciate that this platform has an extended life cycle more in line with enterprise requirements, unlike other consumer grade silicon offerings. The reference design also delivers characteristics necessary for harsh environment use cases such as ruggedized capabilities such as IP67 ratings, drop resistance and extended temperature operative and storage capabilities. A reference design includes all the production-ready design files, bill of materials, schematics and Gerber files required to produce the reference design in 5”, 8” or 10” form factors. Most OEMs will choose to wrap their design in a custom casing that meets their individual branding and usage requirements.
Reducing Development Costs and Time to Market
Getting to market as quickly as possible, and on the most current technology, is one of the top customer concerns. MobileV significantly shortens the traditional OEM development cycle because it is built upon the familiar Microsoft Windows and Android operating systems and leverages production ready Aava Mobile board design files. The customer’s overall cost is lowered by leveraging both internal hardware and software designs across multiple platforms, which helps reduce risk when these
proven designs are reused. The hardware manufacturing supply chain is simplified, especially when a design is aggregated over multiple devices. OEMs are experiencing six months or more reduction in their development cycle by eliminating the need for repeat design and layout. When workers use multiple devices, a consistent interface and experience improves the quality of their output. MobileV UX software is an application layer that extends Windows Embedded 8.1 technology and functionality to small screen enabled devices such as ruggedized handheld terminals and tablets. It enables unified user experiences and profiles across devices and OS platforms, providing a consistent experience and reducing learning curves. In Figures 1 and 2, one can see that the Windows 8 desktop, although fully functional, may be difficult to use on a mini-tablet form factor. Mobile UX is implemented with a familiar tile-based interface to simplify app launching, branding, the integration of ‘live tiles’ with web services and the use of user profiles. For consistency, customers can use this experience across their entire portfolio of Windows-based mobile device form factors. Platform flexibility is another market driver. With MobileV OEMs can increase platform flexibility through the MobileV UX software which delivers multiple display size and resolution, branding, user profiles and support for legacy and modern applications. BBsquare Bellevue, WA (425) 519-5900 www.bsquare.com
Mobility: Bridging the Gap Solutions
• Legacy HW platforms/OS
• Fast TTM
• Fragile, costly consumer BYOD
• Cutting-edge Intel silicon
• Apps that are not designed first for Mobile
• Modern Apps built for the cloud and Mobile
• Short silicon life cycle • IP ownership
36 | RTC Magazine JUNE 2015
• Cross-platform OS support
Issue: Briding the gap to modern mobile devices and modern apps
• Data Insights • Long life cycle • Re-use of hw designs
A truly modern mobile platform
Barriers to modern mobile solutions
Table 1 Bridging the gap from desktop to mobile solutions.
PRODUCTS & TECHNOLOGY
200MSample/s Rugged Portable RF/IF Signal Recorder
A new rugged portable recorder is suitable for wideband signal recording and playback in signal intelligence and RF testing applications. The RTR 2726A from Pentek implements a new packaging scheme that boasts a smaller, lighter chassis. Enhanced capability permits up to eight recording and playback channels configurable with the right combination for a specific mission or application. An optional DC power supply enables use in ground or airborne vehicles without inverters. At the heart of the RTR 2726A are Pentek Cobalt Series Virtex-6 software radio boards featuring A/D and D/A converters, Digital Downconverters (DDCs), Digital Upconverters (DUCs) and complementary FPGA IP cores. This architecture allows the system engineer to take full advantage of the latest technology in a turnkey system. The RTR 2726A features a portable, lightweight housing measuring only 16.0” W x 6.9” D x 13.0” H, weighing just less than 30 pounds. This extremely rugged workstation is reinforced with shock absorbing rubber corners and an impact-resistant protective glass for its high resolution 17” LCD monitor. The hot-swappable Solid State Drive (SSD) array is available in 1.9 to 15.3 TB configurations and supports RAID levels 0, 1, 5, or 6. Available I/O includes VGA video, six USB 2.0 ports, two USB 3.0 ports and dual Gigabit Ethernet connections. All Talon RTR portable recorders are built on a Windows 7 Professional workstation with an Intel Core i7 processor and provide both a GUI (graphical user interface) and API (Application Programmer’s Interface) to control the system. Systems are fully supported with Pentek’s SystemFlow® software for system control and turn-key operation. The software provides a GUI with point-and-click configuration management and can store custom configurations for single-click setup. The software also includes a virtual oscilloscope and signal analyzer to monitor signals before, during and after data collection. The data format used for storage follows the NTFS standard, allowing users to remove drives from the instrument and read the data using standard Windows-based systems, eliminating the need for file format conversion. SSD storage options range from 1.9 to 15.3 TB capacities. The RTR 2726A has an 18 to 36 VDC power supply option for vehicle powered applications. Optional GPS time and position stamping is available. Customers can select the recording I/O performance that best matches their recording system requirements. The Talon RTR 2726A starts at $49,995 USD.
4-CH 12-bit 80 MS/s PCI Express Digitizer Boasts High Sampling Rate
A new high-speed PCI Express digitizer features four simultaneously sampled 80 MS/s input channels with 12-bit resolution, 40 MHz bandwidth, and up to 1 GB DDR3 onboard memory. The PCIe-9814 from Adlink Technology delivers compellingly accurate high dynamic performance in 76 dB SFDR, 64 dB SNR, and -75 dB THD, with up to 640 MB/s data streaming and value added functionality, enhanced price/performance, and maximum optimization for radar testing, power management monitoring, and non-destructive testing. The PCIe-9814’s 80 MS/s sampling and 40 MHz signal bandwidth easily meet the requirements of medium frequency (0.1mHz to 30mHz) radar signal reception from IF radar receivers. The PCIe-9814 provides external digital trigger input for synchronous trigger radar signaling, while three extra synchronous digital inputs receive radar synch pulse signals or GPS IRIG-B code to support radar signal markers or synchronous time stamping used in radar testing. The PCIe-9814’s FPGA-based 31-order FIR digital filter supports noise reduction when signal content is 20 MHz or less. Noise effects are reduced efficiently and signal visibility increased by rejecting out-of-band and background noise and unexcepted high frequency signals, all with no extra programming demands. The FPGA-based FIR digital filter performs much faster than on the host, with no host CPU bandwidth occupied. The PCIe-9814 supports Windows 8 and Windows 7 operating systems and is fully compatible with third-party software such as LabVIEW™ and Visual Studio.NET®. In addition, ADLINK’s measurement APIs allow easy conversion of basic voltage/time measurement results with no need for extra programming. System development is easier than ever before. ADLINK Technology, San Jose, CA (408) 360-0200. www.adlinktech.com
Pentek, Upper Saddle River, NJ 201-818-5900. www.pentek.com
RTC Magazine JUNE 2015 | 37
PRODUCTS & TECHNOLOGY
Analog Devices Blackfin ADSP-BF706 EZ-KIT Audio Evaluation Board
The ADSP-BF706 EZ-KIT Mini Evaluation Board from Analog Devices aids in the development and testing of the 32-bit, 400 MHz ADSP BF706 Blackfin DSP that delivers 800 MMACS of processing power at less than 100 mW. This mini evaluation board contains all the communication interfaces and external connections needed for DSP audio application design, including an Arduino compatible interface. The board offers a complete, small-form-factor, low-cost starter platform for evaluation of the ADSP BF706 Blackfin DSP processor. The ADSP-BF706 EZ-KIT features on-board, high-quality audio I/O, 1,160 KBytes of on chip internal SRAM, 4 MBytes of quad SPI Flash and connections for EPPI0, SPORT, SPI, I2C, and general-purpose I/O (GPIOs). The USB bus-powered board also features an on-board JTAG/SWD debug port through a separate USB interface, and an ADAU1761 SigmaDSP low power stereo audio codec. The ADSP-BF706 EZ-KIT board also accommodates the installation of 0.1-inch stackable headers for interfacing with Arduino compatible shields that are compliant with the Arduino Uno R3 shields interface. When used with the Analog Devices CrossCore Embedded Studio (CCES), the ADSP BF706 EZ-KIT Mini Evaluation Board offers advanced application code development and real-time debug capabilities. The CCES development environment allows designers to create, compile, assemble, and link application programs written in C, C++, and assembly code. The software package also includes DSP Concepts’ graphical-based Audio Weaver software tool that provides a full-featured audio module library with efficient code generation and profiling. Analog Devices, Norwood, MA (781) 329-4700. www.analog.com
4Mbit Asynchronous SRAMs with On-Chip Error-Correcting Code
A line of 4Mbit asynchronous SRAMs includes error-correcting code (ECC) that enables them to provide the highest levels of data reliability, without the need for additional error correction chips—simplifying designs and reducing board space. The devices now sampling from Cypress Semiconductor ensure data reliability in a wide variety of industrial, military, communication, data processing, medical, consumer and automotive applications. Soft errors caused by background radiation can corrupt memory content, resulting in a loss of critical data. A hardware ECC block in Cypress’s new asynchronous SRAM family performs all error correction functions inline, without user intervention, delivering best-in-class soft error rate (SER) performance of less than 0.1 FIT/Mbit (one FIT is equivalent to one error per billion hours of device operation). The new devices are pin-compatible with current asynchronous fast and low-power SRAMs, enabling customers to boost system reliability while retaining board layout. The 4Mb SRAMs also include an optional error indication signal that indicates the correction of single-bit errors. The Cypress 4Mb asynchronous SRAMs are available in three options—Fast, MoBL and Fast with PowerSnooze™—an additional power-saving Deep Sleep mode that achieves 15 uA (max) deep-sleep current for the 4Mb SRAM. Each of the options is offered in industry standard x8 and x16 configurations. The devices operate at multiple voltages (1.8V, 3V, and 5V) over -40°C to +85°C (Industrial) and -40°C to +125°C (Automotive-E) temperature ranges. The new SRAMs are currently sampling in industrial temperature grade, with production expected in July 2015. These devices will be available in RoHS-compliant 32-pin SOIC, 32-pin TSOP II, 36-pin SOJ, 44-pin SOJ, 44-pin TSOP II and 48-ball VFBGA packages. Cypress Semiconductor, San Jose, CA (408) 943-2600. www.cypress.com
38 | RTC Magazine JUNE 2015
PRODUCTS & TECHNOLOGY
Exerciser Helps Developers Improve Power Efficiency of PCIe® Devices
A new protocol exerciser offers a broad range of PCIe test tools for validating Gen1, Gen2 and Gen3 operation for all lane widths up to x16. The U4305B PCI Express protocol exerciser tools from Keysight Technologies address PCIe developers’ needs, including providing ways to test new technologies like Non-Volatile Memory Express (NVMe) and L1 substate operation. Starting with the early PCIe implementations, low power states have always been important to developers. Now, PCIe has new standards for extremely low power called L1 substate. Using a sideband signal, CLKREQ#, to allow devices to shut down the clock and even remove keeper voltages, new PCIe devices are more power efficient than ever. The U4305B exerciser is designed to verify these low-power implementations. A built-in test bench allows users to generate automated tests of PCIe or NVMe operations. The test bench comes with scripts that validate the operation from ASPM or PCI-PM L1 substates. These prewritten tests exercise each state to provide pass/fail results that report on control register operation as well as operation of each L1 substate entry/recovery. An LTSSM test package is available for the U4305B. The package allows engineers to perform link negotiation testing that can thoroughly test a DUT’s LTSSM functions. It also can verify PCIe state transitions and validate state timeouts. More than 50 predefined LTSSM tests assess the DUT’s operation. For testing NVMe, the U4305B exerciser can emulate either the host or device to submit and execute NVMe commands or create error test sequences. Standardized NVMe testing not only improves adherence to the specification and increases device interoperability, but also decreases test time by providing tests that give developers insight into device operation. Keysight’s implementation uses the NVMe conformance tests as defined by the University of New Hampshire (UNH) Interoperability Lab (IOL). These tests provide pass/fail/warning results with detailed diagnostic information to improve NVMe validation. Engineers can configure the Keysight U4305B exerciser to provide subprotocol layer test and debug for legacy and next-generation PCIe devices. The U4305B exerciser for PCIe is an advanced traffic generator that developers can use to send and respond to TLP, DLLP and physical-layer packets to stimulate PCIe devices and systems. Prices start at $24,793. Keysight Techologies, Santa Rosa, CA (800) 829-4444. www.keysight.com
HMI Panel PC for Trains, Offers Interoperability for Multiple Applications
Specifically designed for transportation systems, a new advanced touch-screen HMI offers a flexible building block platform enabling developers of train control systems to quickly adapt functionality to different needs such as train functionality operational displays for drivers, passenger information displays and onboard computers. The TRACe HMID104-CK from Kontron an EN50155-certified fanless operational panel PC display is that delivers a unified architecture approach with the full standardized TRACe family of products, enabling maximum interoperability. These features allow OEMs and integrators to do away with unnecessary development costs while helping to accelerate time to market, from application design to deployment schedules. Cost reductions in the certification phase can also be achieved by leveraging the same TRACe architecture for various applications. Kontron’s TRACe transportation computing platforms integrate comprehensive health management capabilities that provide a modular and scalable set of uniform test routines to assess the health status and configuration of the complete system. Equipped with a dedicated microcontroller and sensors to monitor all vital functions, TRACe health management features continuously monitor and report the status of the TRACe system while running normal operations. Based on Kontron’s COM Express Computer-on-Module (COM) integrating the Intel Atom E3845 processor, the TRACe HMI offers excellent processing performance and low power consumption providing an ideal high performance per watt ratio. Delivering a highly rugged design, the complete system is EN50155 Class Tx certified and supports extended temperature operation (-40°C to +70°C / 10 min @ +85°C) ensuring safe deployment in trains, trams and underground vehicles. This fanless and maintenance-free driver console combines cost optimization with modularity and upgradability. It features a capacitive-touch 10.4-inch TFT (SVGA 800x600) display with anti-vandal glass along with an UIC612 keyboard. Resistive touch screen and/or no-keyboard variants are also available on demand. TRACe-HMID104-CK offers all necessary interfaces including two gigabit Ethernet (GbE) ports and optional serial interfaces, USB ports, audio and GPIOs. It also features flexible I/O (3x MiniPCIe slots), wide range power supply (from 24VDC to 110VDC) and modular design as well as optional support for the full range of field buses such as MVB, TRDP, IPCom, Profibus, and CANbus. In addition, the TRACe-HMI has a soldered 2GB DDR3 ECC system memory and an on-board high reliability 8 GB SLC solid state drive as well as embedded Linux or WES8 operating systems. Thanks to its modular, low power and robust design, the Kontron TRACe HMI matches long-term program lifecycle needs of 20 years or more with very high availability and outstanding MTBF.
Kontron, Poway, CA (888) 294-4558. www.kontron.com RTC Magazine JUNE 2015 | 39
PRODUCTS & TECHNOLOGY
Complete Solution for USB Type-C to DisplayPort Adapter Cables
A complete silicon and software solution for USB Type-C to DisplayPort adapters (dongles) enables connectivity between a USB Type-C receptacle and a DisplayPort (DP) or Mini DisplayPort (mDP) receptacle, allowing emerging Type-C notebooks and monitors to be interoperable with older products. The EZ-PD™ CCG1-based Type-C to DisplayPort Cable solution from Cypress Semiconductor includes USB Billboard Device Class, which allows the adapter to communicate status to a host that does not support DP. This solution uses Cypress’s EZ-PD CCG1 (CYPD1120) Type-C Port Controller to support DP as one of its Alternate Modes and the CY7C65210 Full-Speed USB 2.0 controller to support the USB Billboard Device Class. Cypress demonstrated that its Type-C to DP solution is interoperable with the Apple MacBook, the Google Chromebook Pixel and multiple other systems at the recently concluded VESA and USB-PD Interoperability events in Milpitas, California. The USB Type-C standard is gaining rapid support with top-tier PC makers by enabling slim industrial designs, easy-to-use connectors and cables, the ability to transmit multiple protocols, and 100W power delivery (PD)—a significant improvement over the previous 7.5W standard. The Type-C standard’s 2.4-mmhigh connector plug is significantly smaller than current 4.5-mm USB Type-A standard connectors. It also allows for transport of USB signals and PCIe or DP signals on the same connector. The CYPD1120 device is available in a 35-ball CSP and 40-QFN package, while the CY7C65210 device is available in a 24-pin QFN package. Cypress Semiconductor, San Jose, CA (408) 943-2600. www.cypress.com
40 | RTC Magazine JUNE 2015
Full Speed Debugging of 1mm pitch BGA132 is made easier with Probe Adapter
A new Probe Adapter which allows high-speed testing of NAND Flash while accessing the signals using testers via test pads. Features of the PB-BGA132E-NANDFLASH-01from Ironwood Electronics include shortest possible trace length for maximum speed, low inductance, low capacitance, blind and buried via PCB design technology. This probe adapter is designed to interface 1mm pitch Ball Grid Array packages to SMT pads on the target PCB while bringing the signals out for probing. Ironwood’s PB-BGA132E-NANDFLASH-01 Probe Adapter consists of rigid flex PCB with solder balls on the bottom side. The probe adapter can be soldered to the target system board in place of BGA132, 1mm pitch, 11x17 array, 12mmX18mm body using standard BGA soldering methods. Nand flash can be soldered on the top side of probe adapter that employs a flex wing design to deliver all data, address, control, and other signals to test pads on 0.4mm centers. The flex wing test pads are interfaced to logic analyzer or other test equipment using appropriate cable connector. Alternatively, this probe adapter can be used inside a BGA socket for solderless solution. The PB-BGA132ENANDFLASH-01 adapter is priced at $2400 USD in quantities of 1to 10 parts. Ironwood Electronics, Eagan, MN. 952-2298200. www.ironwoodelectronics.com
Data Acquisition Instrument of the Month The ePC-Duo is a user-customizable, turnkey embedded instrument that includes a full Windows/Linux PC and supports a wide assortment of ultimate-performance XMC modules. With its modular IO, scalable performance, and easy to use PC architecture, the ePC-Duo reduces time-tomarket while providing the performance you need. Distributed Data Acquisition â€“ Put the ePC-Duo at the data source and reduce system errors and complexity. Optional GPS-synchronized timing, triggering and sample control is available for remote IO. Limitless expansion via multiple nodes. Up to 4 HDD for data logging.
For More Info Visit: intelligentsystemssource.com/epc-duo
Company...........................................................................Page................................................................................Website congatec, Inc....................................................................................................................... 4...........................................................................................................................congatec.us Dolphin...................................................................................................................................29................................................................................................................. dolphinics.com Intelligent Systems Source.............................................................................. 4, 25, 41.......................................................................intelligentsystemssource.com Interdrone..............................................................................................................................21.................................................................................................................. interdrone.com Lauterbach...........................................................................................................................32.................................................................................................................lauterbach.com Novasis...................................................................................................................................43.....................................................................................................................novasom.info One Stop Systems.......................................................................................................5, 14................................................................................................onestopsystems.com RTECC............................................................................................................................20, 33, 42................................................................................................................ RTECC.com Somnium............................................................................................................................... 19......................................................................................................................ow.ly/M9PrW Super Micro Computers, Inc..................................................................................44...............................................................................................................supermicro.com Trenton Systems.............................................................................................................. 2......................................................................................................trentonSystems.com Product Gallery.................................................................................................................29......................................................................................................................................................
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42 | RTC Magazine JUNE 2015
Call: (949) 226-2000
The medical industry has a unique demand for highest safety and reliability meeting regulatory requirements. Applications range from demanding computing requirements for optical Analysis to low power mobile diagnostic and supportive equipment. The NOVAsom8© is a module card designed with a System On Module (SOM) architecture based on quad core ARM Cortex-A9, 64 bit memory until 2 GB and 3 graphic engines that is perfect for medical applications.
Designed with the latest generation, high performance microprocessor. NOVAsom8© can be used in many distinct industrial applications. On-board connectivity solutions, advanced multimedia and other standard peripherals allow our customers quick and easy From the integration into numerous innovative, high-tech product applications.
NOVAsom8© is based on Freescale processors that are focused on industrial products and market segments requiring stability and long product life cycle.
Data Center to the Battlefield. www.novasom.info
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