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EtherCAT Links Ethernet to Industrial Applications PC/104 Adds OneBank for Performance and Economy Can CPUs Move in on the Turf of FPGAs? The Magazine of Record for the Embedded Computer Industry

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Wireless Protocols Weave the Web for the Internet of Things

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Pushing the Envelope on Graphics Processors and Opening the Way for Neural Nets by Tom Williams, Editor-in-Chief




EtherCAT Allows Ease of Use and Real-Time Performance for Distributed Systems by Daron Underwood

CONNECTED The Three (no, Four) Most Important TECHNOLOGY BLUETOOTH, WI-FI AND ZIGBEE Aspects of Software for Wi-Fi 18 The Three (no, Four) Most ImportEnabled Devices ant Aspects of Software for Wi-Fi Enabled Devices


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Intel vs. ARM—Will the Bear Strike Back?


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Latest Developments in the Embedded Marketplace

PRODUCTS & TECHNOLOGY Newest Embedded Technology Used by Industry Leaders

The Internet of Things and Wireless Communication Standards by Cees Links



OneBank: Combining Economy and Performance for Stackable Systems by Jonathan Miller


36 36 Intel Architecture versus the FPGA: The Battle of Time, Complexity and Cost

Intel Architecture versus the FPGA: The Battle of Time, Complexity and Cost by Matt Stevenson

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Intel vs. ARM—Will the Bear Strike Back? by Tom Williams, Editor-In-Chief

Intel must be feeling like a bear being circled by wolves. The wolves are named ARM and they are gradually tearing meaty chunks out of the x86 bear. But beware of getting a bear cornered. A cornered bear can lash out with some pretty mean claws as well. For some time there has been a battle going on in the embedded space between the Intel Atom family of x86 low-power processors and a variety of ARM architecture-based devices, which are increasingly centered on the ARM Cortex M and R series cores. Intel’s advantage has been that the embedded world has largely been derived from that of the PC—high-volume, low-cost devices as well as widely used peripheral technologies like USB and PCI and now PCI Express. ARM’s big selling point has been its low power consumption, which despite all its efforts, Intel has never been able to match. This difference is being increasingly exacerbated with the surge in mobile devices, wireless connectivity and the need to save power at every step. This and the flattening of the PC market has allowed ARM and its many licensees to make steady gains. Add to this mix, Intel’s old nemesis, AMD, which has successfully marketed lines of processors based on its clean room-developed version of the x86 instruction set. Now even AMD is starting to move into the ARM arena. It appears that so far Intel’s strategy has been to more aggressively and specifically target the embedded arena with such things as Atom and Core-based SoCs that incorporate a range of on-chip peripherals and increasingly to move into the server arena with powerful versions of its multi-core Xeon processors. Unfortunately, the lust for power-savings is also now rampant in server farms, which consume enormous amounts of electricity and dissipate ungodly amounts of heat—all of which can be visualized as dollar signs by their managers. And now ARM is targeting the server arena with a new line of 64-bit ARM cores and AMD, among oth6 | RTC Magazine APRIL 2015

ers, have started offering processors targeting the server market based on these new cores. Another thing that Intel has to contend with is the emergence of heterogeneous system architectures (HSAs) that integrate such elements as graphic processors, DSPs and FPGAs on the same die. This has led to the emergence of the HSA Foundation, among whose goals are the establishment of standards and open-source software tools to address the combination of CPUs with parallel elements on the same chip. Two of HSA’s founding members are ARM and AMD. But don’t count Intel out yet. The bear may be cornered, but it’s getting ready to strike. There are rumors floating around the industry—and by the time of publication they may be more than rumors—that Intel is in talks to purchase Altera, a major producer of FPGAs. If true, it makes sense on so many levels. Intel and ARM have fundamentally different business models. Intel has its in-house technology, which it will not license to anyone—the bear. ARM manufactures nothing itself but licenses its IP out to a host of different manufacturers—the wolves. To compete, Intel needs the in-house capability to integrate its processor technology, and all its legacy software, to programmable logic on-chip. Both Altera and its major rival Xilinx currently offer families of CPU/FPGA hybrid processors on which the CPU is an ARM device. For Xilinx, these are the Zynq products and for Altera they are the SoC FPGA products. No FPGA company will be able to license something like Atom or Core i5 IP from Intel to build a competing device. So if Intel does acquire Altera, you can expect it to, of course, continue to support and develop Altera’s technologies and serve its customers. There were predictions that after its acquisition of Wind River, it would drop lines that served other processors, but that did not happen. We can, however, expect to see a discontinuation of ARM-based SoC FPGAs

for a line of hybrids based on Atom and Core architectures. Originally, it looked like the rivals were going to duke it out in the embedded arena and that is certainly happening. Now, however, with products like AMD’s Opteron A1100, which is based on the 4- or 8-core 64-bit ARM A57 core and Xilinx with a device based on a quad-core Cortex-A53, attention is clearly turning to the server market as well. Currently, AMD’s parallel processing element is the multicore Radeon GPU architecture it acquired from ATI, which also lends itself very well to intensive numeric processing. If Intel does acquire a major programmable logic house like Altera with its built-in expertise, it will be able to turn out hybrid processors with a huge range of specific (network server) functions as well as generally programmable and configurable devices. An added advantage is that FPGAs consume less power than the Xeon devices and while not as low as ARM, can make a good case in terms of compatibility with legacy software. So far programmable logic companies have licensed CPU (ARM) technology. They must therefore make exact decisions as to which core(s) to license. There could be an interesting advantage when a company with complete control over a vast family of CPUs and specific devices with combinations of onchip peripherals and I/O also actually owns a programmable logic company. The possibilities could be endless . . . and as powerful as the claws of a bear.


Solar Power Now Has Economic Advantage and is Looking at a Boom in US There are several new economic indications that solar energy may be on the verge of a major boom. Deutsche Bank, for example, has produced a 175 page report that suggests solar generated energy will be the dominant source of energy worldwide within the next 15 years. Not only that, but the solar industry will generate $5 trillion in revenue in that time while displacing fossil fuels. The analysts at Deutsche, led by Vishal Shah, state the solar market potential is massive. Even today, at only 1%(130GW) installed of the possible 6,000GW, it still produces $2 trillion annually. They also predict that in the next 15 years, the market in solar will increase 10 fold. Now a new report from the National Bank of Abu Dhabi—which one would normally expect to be a big player in oil and gas—says that “fossil fuels can no longer compete with solar technologies on price,” and that the majority of the $48 trillion needed to meet global energy demand over the next 20 years will come from renewables. “Cost is no longer a reason not to proceed with renewables,” the report says. In some instances, the price of renewables are remarkably low. “The latest solar PV project tendered in Dubai returned a low bid that set a new global benchmark and is competitive with oil at US$10/barrel and gas at US$5/MMBtu.” This was a 200MW bid by ACWA Power at $00584/kwh (5.84c/kwh) without subsidies. Of course, sunnier countries will have lower costs, but over time even cloudier places will see solar eclipse dirty sources. The growth in photovoltaic was evident at all scales of deployment, from smaller residential installations to massive utility-scale solar farms. Only natural gas accounted for a larger percentage of new generating capacity than solar, but the gap was only 10%. Some further statistics: The US installed 6,201 MW of solar PV in 2014, up 30% over 2013, making 2014 the largest year ever in terms of PV installations. Solar provided roughly one third of all new electric generating capacity in the US in 2014 and more than one third of all new electric generating capacity in the US came online in the same year. By the end of 2014, 20 states eclipsed the 100 MW mark for cumulative operating solar PV installations and California alone is home to 8.7 GW.

Cypress, Spansion Merger Creates $2 Billion Player in MCUs and Specialized Memories for Embedded

Cypress Semiconductor and Spansion have announced that they have closed the merger of the two companies in an all-stock, tax-free transaction valued at approximately $5 billion. The merger is expected to achieve more than $135 million in cost synergies on an annualized basis within three years and to be accretive to non-GAAP earnings within the first full year after the transaction closes. The combined company will continue to pay $0.11 per share in quarterly dividends to shareholders. Cypress President and CEO T.J. Rodgers said, “We closed this merger even more quickly than originally anticipated, accelerating our strategic and financial roadmap. From Day One, the new Cypress will capitalize on its expanded product portfolio and leadership positions in embedded processing and specialized memories to significantly extend its penetration of global markets such as automotive, industrial, consumer, wearable electronics and the Internet of Things.” “Consider the automotive market, where Cypress has a dominant position in capacitive touchsensing controllers and SRAMs for infotainment systems, and Spansion is the leading supplier of flash memory and microcontrollers for infotainment, body and climate control systems, instrument clusters and advanced driver assistance systems,” Rodgers said. “The new Cypress will be the number three chip supplier worldwide of memories and microcontrollers to this business.” “Spansion’s exceptional team and technology leadership in high-performance memory and MCUs will complement Cypress’s strong capabilities. This merger was an important step forward in Spansion’s transformation into a global embedded systems leader,” said Kispert, CEO of Spansion and a member of the Cypress board of directors. “Together, we can significantly enhance our value to our customers and deliver a more robust and broader product line to meet their embedded requirements.”

PICMG Ratifies PICMG 3.7 AdvancedTCA Extensions Specification for Telecom & Data Center Applications

the PICMG has announced the adoption of AdvancedTCA Extensions (PICMG 3.7)

specification. PICMG 3.0 AdvancedTCA (ATCA) was originally created in 2003 to meet the needs of the telecom market for an open standard computing platform. To better address markets other than telecom, and to utilize the available depth in server cabinets, PICMG developed a set of extensions to the existing ATCA specification. The extensions include; a dual-sided shelf that can hold up to 28 Front Boards (existing ATCA boards) in a 19” cabinet, new board types, additional power and cooling, options for data center optimized input voltage range, and an increase in the Base Interface bandwidth. All of these extensions to ATCA were developed with backward compatibility in mind. The original ATCA specification allows for boards that are more than one slot wide, but gives almost no information about how to make them. The ATCA Extensions specification gives detailed implementation information and examples for wider boards that can dissipate up to 800 watts each. There has been lot of interest in increasing the size of an ATCA board to accommodate physically larger DIMMs and bigger processor heat sinks. Changing the board size would break backward compatibility and fragment the ATCA market. A better solution is a dual-sided shelf defined in PICMG 3.7. The ATCA Extensions dual-sided shelf can be viewed as two ATCA systems back-to-back with common mechanics, Hardware Platform Management and power input. PICMG 3.7 meets the market need for increased board space and power while maintaining backward compatibility with existing ATCA boards and software. This will speed adoption because a large selection of blades is already available. The new board types defined in ATCA Extensions will allow for much higher performance systems, and extend the life of ATCA products. A presentation explaining many of the features of ATCA Extensions can be found in the “AdvancedTCA” section of the PICMG web site, RTC Magazine APRIL 2015 | 7


IBM Acquires AlchemyAPI, Enhancing Watson’s Deep Learning Capabilities IBM has acquired AlchemyAPI, a provider of scalable cognitive computing application program interface (API) services and deep learning technology. The acquisition will accelerate IBM’s development of next generation cognitive computing applications. The acquisition also significantly expands the Watson ecosystem, welcoming 40,000 developers who have innovated on the AlchemyAPI platform to the IBM Watson developer community. Financial terms of the deal were not disclosed. IBM will integrate AlchemyAPI’s deep learning technology into the core Watson platform, augmenting Watson’s ability to quickly identify hierarchies and understand relationships within large volume data sets. The technology is expected to enhance Watson’s ability to ingest, train and learn the “long-tail” of various data domains – including general business and target industries, as well as address the need to manage constantly evolving ontologies. In addition, the acquisition will greatly expand the number and types of scalable cognitive computing APIs available to IBM clients, developers, partners and other members of the Watson ecosystem. This includes language analysis APIs to address new types of text and visual recognition, and the ability to automatically detect, label and extract important details from image data. Watson is a commercially available cognitive computing capability representing a new era in computing. The system, delivered through the cloud, analyzes high volumes of data, understands complex questions posed in natural language, and proposes evidence-based answers. Watson continuously learns, gaining in value and knowledge over time, from previous interactions. IBM is delivering new Watson services and APIs through the Watson Zone on Bluemix, the company’s digital innovation platform that enables developers to rapidly build, deploy and manage apps across any combination of public, private and hybrid cloud. Thousands of developers, entrepreneurs, data hobbyists, students and others have already built more than 7,000 apps powered by Watson to date. 8 | RTC Magazine APRIL 2015

Certified Intel Industrial Solutions System Consolidation Platform

A fanless, embedded computer is the first hardware platform to be certified for the Intel Industrial Solutions System Consolidation Series. The MXE-5301 from Adlink supports a wide temperature range and offers a fanless and cable-free design, making it suited for industrial applications. Intel’s industrial workload consolidation platform with the MXE-5301 enables the combination of several applications—or workloads—and their respective host operating systems into a single computing solution. What were once multiple, separate systems can now be combined into just one platform using advanced hypervisor technology that allows host operating systems to coexist. For the customer, workload consolidation reduces the number of individual devices, allowing a single, smaller footprint and lowered system and environmental complexity. In addition to the current collaboration on the workload consolidation program, Adlink is also announcing its promotion by Intel to Premier Member in the Intel Intelligent Systems Alliance. From modular components to market-ready systems, Intel and the 250+ global member companies of the Alliance provide the performance, connectivity, manageability, and security developers need to create smart, connected systems. Close collaboration with Intel and each other enables Alliance members to innovate with the latest technologies, helping developers deliver first-in-market solutions.

Driverless Car Completes Cross-Country Trip A self-driving car has completed a 3,500-mile trip from San Francisco, California to New York, setting the North American record for longest drive ever by a driverless car. Delphi Automotive’s self-driving car, which is modeled after a 2014 Audi SQ5 and debuted at CES 2015, features six long-range radars, four short-range radars, three vision-based cameras, six lidars, a localization system, intelligent software algorithms and a full suite of Advanced Drive Assistance Systems. The car can manage four-way stops, merge onto highways, and steer around unexpected presences in the roadway, such as a bicyclist. And it seemed to do all this fine along its record-breaking trip, as there were no incidents reported. Although there were several humans in the car in case precautions were needed. Delphi described the trip as the car’s “ultimate test” as it would be “challenged under a variety of driving conditions from changing weather and terrain to potential road hazards - things that could never truly be tested in a lab.” Delphi gathered more than 2 terabytes of data that it can use to improve its future automated driving systems. Admittedly, Delphi’s test involved mostly highway driving, so there was minimal exposure to difficult scenarios that can pop up in city and even urban driving. But this also isn’t Delphi’s first rodeo. Delphi has driven back and forth between San Francisco and Los Angeles numerous times, testing its system all the way down I-5. And ABC News reports that the only time a human driver needed to take over the car on a recent eight-mile test drive was when the car had to unexpectedly merge into another lane due to road construction.


Lumeta Announces Strategic Partnership with Nordisk Systems Lumeta, a specialist in network situational awareness, has announced a new strategic partnership with solution provider Nordisk Systems. As part of the Security solution offered by Nordisk, the Lumeta network situational awareness platform empowers Nordisk’s customers with authoritative network infrastructure and cybersecurity analytics upon which they can build a strong network security program. Because of the constant state of network change, IT professionals require complete and accurate visibility into the shape and scope of a network in order to maintain security, compliance and availability. The Lumeta network situational awareness platform recursively indexes a network to provide an accurate cybersecurity posture of network architecture and network segmentation policies, violations and vulnerabilities. “Nordisk has decades of proven experience. Lumeta’s technology along with Nordisk’s consulting expertise and Security Assessments provide the foundational elements of any secure network infrastructure,” said Pat Donnellan, CEO at Lumeta. “We look forward to delivering opportunities together.” “Our goal is to help our customers keep their data safe and secure from internal and external threats,” said Deney Dentel, President and CEO at Nordisk Systems. “Lumeta will identify 100% of network connections and devices, giving customers the strong intelligence required for vulnerability management and risk mitigation.”

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Pushing the Envelope on Graphics Processors and Opening the Way for Neural Nets NVIDIA targets the autonomous vehicle with processor and neural net learning advances and partnerships with multiple auto manufacturers. by Tom Williams, Editor-in-Chief

NVIDIA, long a key player in the graphics processor (GPU) arena, is coming out with ever more powerful processors build on its well-known and widely used CUDA architecture, is now making a major push into the quest for the driverless car. In doing so, they are leveraging the inherent processing power of their newest GPUs as well as enabling the use of neural network processing on their architecture and quite probably giving a big boost to the use of neural nets and artificial intelligence in a wide range of application areas. At its recent GPU Technology Conference in San Jose, NVIDIA unveiled a number of new products with advanced graphics, intensive numeric processing and neural network capabilities, in a surrounding context of advanced automotive technologies that will one day soon cultivate in the driverless car. In addition, it became clear that, while the initial focus is on automating the automobile, the type of “deep learning” of which these new processors are capable will be able to address a wide range of heretofore intractable problems. Sharing the stage for part of the keynote address with NVIDIA CEO Jen-Hsun Huang was the CEO of Tesla Motors, Elon Musk. Tesla is, of course, known for its pioneering work in electric vehicles and most recently for its Tesla Model S, which at a mere $80,000 is pushing the price tag for EVs lower, with a new model coming out that is supposed to land in the range of around $50,000. Musk’s message the day, however, it to reinforce NVIDA’s push for the autonomous vehicle. One of Musk’s points is that there is a need to establish a hardware platform that can be used for continuous software updates. He notes, “The car will get smarter and smarter with the current hardware suite. Even with just what we have, we’ll make huge progress in autonomy. We can make car steer itself on freeway, do lane changes. Autonomy is about what level of reliability and safety we want.” With current processors, he says, having

10 | RTC Magazine APRIL 2015

Figure 1 NVIDIA’s new GeForce Titan X boasts 3072 CUDA cores for only $999.

autonomy in the 5-10 MPH range it is relatively easy because a car can stop within the range of sonic sensors. The big hurdle is the 10-50MPH range because situations can be quite complex. Then in the freeway environment over 50MPH it gets easier because the range of possibilities gets smaller. But, he notes, that environment could be handled with today’s processors. Now surprise, surprise, NVIDA is announcing the Drive PX, a single-board computer targeted specifically at developing autonomous vehicles. The Drive PX uses dual Tegra X1 processors, the 64-bit version of the Tegra announced last year, the X1 has 8 64-bit ARM cores and a GPU with 256 CUDA cores for processing power of one TeraFLOPS and a video throughput of 1.3 gigapixels/second. It can handle the input from 12 two-megapixel cameras at 60 fps. The Drive PX, however, is intended for use

within the automobile where it will execute the driving software developed on systems using neural networks and deep learning software. NVIDIA has been actively partnering with Tesla on developing such software as well as with Audi and BMW. Developing such code requires much more processing horsepower than would currently run conveniently on even the dual-Tegra horsepower of the Drive PX. In that context, NVIDIA is announcing ever more powerful processors with the announcement of the new GeForce Titan X processor, which, for starters boasts 8 billion transistors (Figure 1). While the Titan X is being promoted for its truly powerful capabilities in the gaming arena and for implementing virtual reality, its 3072 CUDA cores make it a powerful tool for neural networks and the deep learning utilized by the advancing automotive automation as well as for added topics in science and engineering. With 12 Gbytes of on-board frame buffer memory and a memory speed of 7 GBytes/s, the Titan X appears to be the latest and perhaps final processor that will be based on NVIDIA’s Maxwell architecture. Still in the future is the Pascal, which was discussed last year as becoming available this year. It would appear that that schedule has been revised a bit as the Pascal is now slated for availability in 2016. Pascal will represent another large advance as it is projected to use NVIDA’s new NVLink technology. NVLink is expected to increase data rates from 5 to 12 times that of current PCIe 3.0. Putting this fatter pipe between the CPU and GPU will thus allow data to flow at more than 80GBytes/s, compared to the 16GBytes/s available now. The GPU will be able to access memory at near the bandwidth of the memory and will enable a faster data link between GPU and CPU. The NVLink model will also implement unified memory, in which the developer can treat GPU and CPU memory as a single block. The new Pascal GPUs will also feature 3D memory, which stacks DRAM chips into dense modules with wide interfaces, and brings them inside the same package as the GPU. The new memory chips are expected to have multiple times the existing bandwidth, about 2.5 times the current bandwidth and size and have 4 times the energy efficiency of today. This makes possible more compact GPUs that put more power into smaller devices. The result: several times greater bandwidth, more than twice the memory capacity and quadrupled energy efficiency. The Maxwell architecture is inherently parallel, which has long been known to lend itself to advanced high-speed graphics processing. It also is an appropriate architecture for implementing neural networks. Neural nets have been implemented to a certain extend on traditional CPU architectures and as such have been well used to advance the knowledge about neural nets. Now, however, massive parallel architectures are becoming available to enable the implementation of truly deep learning as the speed and density needed for such things as object recognition and classification in real-time environments like that of the autonomous vehicle.

Figure 2 The DIGITS Devbox is specifically designed for developing deep learning neural net applications with four Titan X processors.

Software for such object recognition and vehicle control applications can simply not be mastered using an “if-then” structure, which would have to expressly define all cases and variations in objects. The deep learning approach’s neural nets learn many levels of abstractions ranging from simple concepts to complex ones. Each layer categorizes some kind of information, refines it and passes it onto the next, hence the term “deep learning.” Thus the first layer might be simple edges, the next simple shapes composed of edges, the next might be features like eyes or noses. At deeper layers these might be composed into faces or individual objects. Applications in facial recognition, genetic analysis, speech recognition and translation and many more are then possible. In the case of automotive automation, the ability to read street and speed signs, distinguish pedestrians and all manner of other objects is essential and now possible. NVIDIA is offering two new products to help create such deep learning neural network-based systems. The first is a software tool called DIGITS Deep Learning GPU Training System, which lets users get quickly started implementing and developing neural nets. The second is a targeted system specifically designed for developing deep learning neural nets called DIGITS Devbox, which is a desktop system that comes with four Titan X processors, 64 Gbytes of DDR4 memory and is preloaded with the DIGITS software (Figure 2). The Devbox sells for $15,000 and is available only to qualified customers. The idea is that applications created by training the neural networks on the Devbox can be loaded onto a more compact embedded computer such as the Drive X. DIGITS guides users through the process of setting up, configuring and training deep neural networks, handing the underlying details so that scientists can focus on the research and the results. Preparing and loading training data sets with DIGITS,

RTC Magazine APRIL 2015 | 11

EDITORS REPORT NEURAL NETS ENABLE AUTONOMOUS CARS whether on a local system or from the web is simplified by an intuitive user interface and workflow management capabilities. The system provides real-time monitoring and visualization so users can fine-tune their work. It also supports the GPU-accelerated versions of Caffe, a framework used by many scientists and researchers to build neural nets. At the keynote address, which was delivered on a Tuesday, Tesla’s Elon Musk hinted at an upcoming announcement from his company. He remarked that we are very close to a self-driving car from a technology standpoint. However, the social and regulatory factors that must be overcome will put it off for some time. The following Thursday, Tesla revealed that it will be sending software upgrades to users that will enable them to drive hands-free on the Interstate and operate the car autonomously on private property. It would seem that this corresponds to the 0-5 and over 50 MPH ranges referred to above. It notably does not include the 5-50 MPH range that is still problematic. Regulators are said to be scrambling to deal with the Interstate capability because there are actually many states with no laws against it. California, however, where most Tesla S models are sold, does have laws requiring specially-trained drivers in autonomously controlled vehicles. That would allow autonomous operation on private property but would be risky

12 | RTC Magazine APRIL 2015

otherwise. Still, it does look like we are on our way to fully autonomous cars—for those who would actually want them— far sooner than anticipated. And Elon Musk predicts that with some two billion cars on the road, any transition will take years. However, he says, “In the distant future, (legislators) may outlaw driven cars because they’re too dangerous.”

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EtherCAT Allows Ease of Use and Real-Time Performance for Distributed Systems Leveraging the compatibility of Ethernet with additional Real-time protocol, EtherCAT has become an attractive and widely used replacement for proprietary field buses. With today’s multicore processors, it is also now possible to implement it almost completely in software. by Daron Underwood, IntervalZero Inc.

For equipment and machine builders, Real-Time Ethernet standards deliver undeniable value because they enable performance far superior to previous field bus architectures and, better still, because they allow equipment manufacturers to replace proprietary components with commoditized parts, dramatically reducing costs of equipment, manufacturing and field support. To date the Ethernet for Control Automation Technology (EtherCAT) standard has enjoyed the most rapid adoption, creating some separation from other real time Ethernet standards. According to EtherCAT Technology Group (ETG) benchmarks, EtherCAT offers the best performance of any available standard. And superior performance is only a part of the reason for EtherCAT’s success. EtherCAT’s incredibly rapid rate of adoption and gains in market share are achieved because it is viewed as the most open standard. Most Real-Time Ethernet standards are still largely controlled by a single industrial automation supplier that did the hard work of developing the standard in the first place. However, because of its standards independence from the industrial automation vendors, more motion drive vendors have embraced and support the EtherCAT standard than any other Real-Time Ethernet standard. Coupled with its superior performance, this support and commitment from the ecosystem make EtherCAT the leading standard. EtherCAT’s ecosystem support is derived from its importance to machine builders. Indeed, EtherCAT tips the balance of power toward the machine builder and away from the industrial automation vendor by eliminating vendor lock-in and giving machine builders more freedom. It allows machine builders to optimize the cost and performance of their machines by mixing and matching motion drives and other components rather than being forced to buy a bundled package from a single vendor.

14 | RTC Magazine APRIL 2015

Figure 1 In EtherCAT, slave devices read the data addressed to them while the frame passes through the node. Similarly, input data is inserted while the telegram passes through. The frames are only delayed by a few nanoseconds.

First, let’s understand the value of Real-Time Ethernet and then from that context we can better understand the differentiated value of EtherCAT and how to best implement it on a PC. The cost of a traditional proprietary field bus I/O card and field bus cable far exceeded the cost of a NIC card and Ethernet cables. Because Ethernet-based TCP/IP had become the de facto standard for corporate networks, the hardware components used in those networks – copper and fiber, CAT5 cables, RJ45 jacks, NIC cards, Ethernet switches – were seen as essential for reducing the costs of a machine’s bill of material if they could be used in a machine that demanded real-time control in a distributed setting. These components had become ubiquitous, high quality and most importantly because of the volume, extremely low cost. Yet while Ethernet seemed like the obvious choice for cost and quality reasons, machine builders had a major concern. The Ethernet protocol (CSMA/CD) was not deterministic, raising issues of scalability, performance and safety. The collision detection

model could not satisfy the real-time needs nor the tight time deadlines required by most industrial machines – particularly those relying on motion control. Without those capabilities the breakthrough architecture would remain just an idea. In recent years, Industrial Ethernet solutions have begun to supplant conventional field buses in next-generation machine designs, as newly developed standards overcome concerns about efficacy, performance and safety. And Real-time Ethernet – and EtherCAT in particular – have enabled a more efficient architecture that can be implemented entirely in software and that can run on commodity Industrial PCs. There is a chicken and egg problem with most standards and the Real-time Ethernet standards are no exception. For a standard to be effective, there must be a critical mass of vendors that adhere to the standard, but vendors do not want to invest in a standard until it has critical mass. Consequently, while many Real-time Ethernet standards are solid, they lack that critical mass of adoption by an ecosystem of vendors. And this is why EtherCAT is differentiated when it comes to servo controls, motion and I/Os. An examination of the EtherCAT architecture and it’s key value components explains why.

EtherCAT Features

Like most field buses, EtherCAT uses the concept of master and slaves. The EtherCAT master does not require special hardware and can be designed solely in software on a COTS system with one or more standard Ethernet ports. Slave devices use an EtherCAT Slave Controller (ESC), which processes the frames in hardware, ensuring predictable performance. The EtherCAT master sends a telegram to the first slave device, which reads from/writes to the appropriate area and then passes the telegram to the next slave (Figure 1). This process continues until no more device nodes are detected and the telegram is then sent back to the master. Some of the main features that distinguish EtherCAT from standard Ethernet include: Fewer Network Constraints: In many Industrial Ethernet solutions, the use and topology of switches and hubs limits the network. With EtherCAT, the application defines the topology, removing the need for switches and hubs and thereby eliminating network constraints. Real-Time Performance: Importantly, EtherCAT has exceptional real-time performance. It uses a single telegram which all nodes can read/write to as it passes by. Node latencies are constant and very small – less than 500ns regardless of the size of the telegram. Built-in Safety: Functional Safety over EtherCAT (FSoE) is supported as part of the network architecture. The EtherCAT safety technology conforms to IEC61508. Safety applications can support up to a SIL 3 level of integrity. Node Synchronization: EtherCAT uses a mechanism based on distributed clocks (DC). The clocks are calibrated in hardware based on the first slave device. This mechanism achieves system jitter that is less than us.

High Availability: EtherCAT supports cable redundancy by allowing a master to control two ports. The second port is connected to the end device of the line topology, thereby creating a ring. Multiple masters are also possible enabling automatic failover in the case of a master failure. In summary, EtherCAT is superior to other field bus solutions currently available not only because of its greater real-time performance, but also because of its ability to scale across multiple use cases—from I/O-only systems to very high-precision motion control. With its unique architecture, EtherCAT can easily scale up to much larger numbers of devices while incurring relatively small additional latencies. This feature alone sets it apart from the other Ethernet-based field buses available today. Importantly, the EtherCAT standard has managed to build the largest critical mass of vendors and that provides leverage. If a Servo drive manufacturer does not offer an EtherCAT- enabled solution, they are at a severe competitive disadvantage. Increasingly machine builders are demanding EtherCAT as part of the solution. Via plugfests and working sessions for vendors, the EtherCAT standards body, the EtherCAT Technology Group (ETG), has done an excellent job of ensuring that the entire architecture simply works. The vendors that provide their qualified EtherCAT slaves – like Servo drives – can simply plug onto the network and work with any qualified EtherCAT Master. The goal is to make it as simple to plug a Servo drive onto the network as it is to plug a PC onto the corporate TCP/IP network, Along with plugfests, which are informal, ETG also requires each device be tested by the manufacturer for conformance using the ETG supplied Conformance Test tool. Although it is not mandatory, device manufacturers are encouraged to submit their devices to one of the EtherCAT Test Centers (ETC) for formal third-party tests, which, if successful, result in a certificate of conformance. This is crucial to the customer base as it instills confidence in device interoperability and also signals the device manufacturer’s commitment to the technology. It is important to note that EtherCAT is only part of the value and solution for machine builders. Today it is possible for machine and equipment builders to contain all of their control logic in software – ending the long dependence on proprietary chipsets, boards, and networks. A machine’s control logic and Human Machine Interface (HMI) can run on a single industrial PC and communicate using an open-standards communication and I/O interface, to any remote device that is part of that equipment. And, as we’ve seen – with the arrival of real-time Ethernet – the solutions can also be deterministic. Tight synchronization of control messages between the PC and remote devices (e.g. motion control) can be done in real-time, with tightly bounded cycle times and event response. All real-time logic can run on commercial off-the-shelf PCs and network components. No proprietary communications boards; no proprietary control cards; no arrays of DSPs or FPGAs; no second PC with a stand- alone RTOS. RTC Magazine APRIL 2015 | 15

TECHNOLOGY IN SYSTEMS CONTROL NETWORK DEVELOPMENT This architectural breakthrough allows machine builders to capture their intellectual property and value in software components, while also dramatically reducing costs by eliminating proprietary hardware. Also, because the solution on the PC is completely software based, patches or fixes can be downloaded remotely rather than performing a board replacement. This reduces support costs even further. ALL HARDWARE

e.g. RTE Card RTE card manufacturers provide the cards and drivers that allow RTX to access Real-Time Ethernet




e.g. Soft RTE Protocol Stack Motion Card

e.g. Soft RTE Protocol Stack & Soft Motion Logic

e.g. Bundled RTE & Motion Logic

Communications completed via NIC card but control logic still handled in DSPs or FPGA

All control logic executes on standard open x86 and NIC card. Machine builder still integrates solution

All control logic communications is pre-integrated and provided by vendor

Table 2 Table to clarify

Two important technology advances – multi-core chipsets and Real-time Ethernet – have enabled this long-desired software-only architecture. There are four key elements in this deterministic architecture: • Microsoft Windows OS • A symmetric multiprocessing-enabled real-time extension to Windows, such as IntervalZero’s RTX64. • Multi-core x86/x64 chipsets • Real-time Ethernet capability. An RTOS extension to Windows such as IntervalZero’s RTX64, which runs on multiple cores, is an essential component of this architecture. Critical to satisfying performance and safety demands, such an RTOS extension allows the control logic (e.g. motion control or digital music transformation) to run as a software component on a Commercial Off-the-Shelf (COTS) x86/ x64 system across one or more cores. RTX64, for example, has drivers that enable real-time communication to support any of the protocols listed above, eliminating the need for proprietary communications boards and field buses. And the Windows 64-bit OS is a critical component to protect the future investment for the equipment builder. With Intel and Microsoft’s investments in the Internet of Things (IoT) and Industrial Ethernet standard for vision – known as GigEVision – the demands for memory will far exceed the capacity of the traditional 32-bit x86 systems. Machine equipment companies have a range of choices regarding how they take advantage of software-centric architectures’ capabilities. At one end of the spectrum, machine builders may want only Real-time Ethernet access, and at the other end of the spectrum builders may want a completely pre-integrated solution. Table 2 shows examples of actual deployment scenarios. Each has its strengths. For example, the time to market and the flexibility to make

16 | RTC Magazine APRIL 2015

field fixes dramatically improves as the machine builder moves closer to an all-software model. And while the upfront costs increase with that approach, it is important to recognize that the ongoing costs are dramatically lower. These tradeoffs need to be evaluated in context of each machine design and market. Until recently, Real-time Ethernet has been the final, missing link to an architecture for machines and equipment with distributed deterministic requirements. Ethernet is familiar, universal and extremely cost-effective. Protocols like Profinet, SERCOSIII and EtherCAT have overcome the limitations that would prevent Ethernet from being deterministic. By adding Real-Time Ethernet to an RTX64-enabled solution, customers can build breakthrough systems that outperform prior systems and do so at a fraction of the cost and complexity by using commercial off the shelf components like IPCs, NIC and CAT5 cables. The EtherCAT standard is a real win for the machine builder because they achieve breakthrough performance, eliminate vendor lock-in, establish a platform that supports emerging standards (like GigEVision), and dramatically lower all costs. IntervalZero Waltham, MA (781) 996-4481 EtherCAT Technology Group Port Orchard, WA (877) 384-3722

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The Three (no, Four) Most Important Aspects of Software for Wi-Fi Enabled Devices With the increasing complexity of wireless connectivity and the almost universal need for devices to connect over the IoT, ease of integrating standard communications is becoming essential. Wi-Fi has grown to a wide-ranging specification that can best be tamed using pre-developed software. by Costas Pipilas, Econais

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Figure 1 “Word cloud” of related terms in IoT device communication, Internet, and Cloud connectivity.

In the real world, time is money, and they are both in short supply for designers who are under tight constraints when designing new Wi-Fi connected devices. Add to this increasingly challenging equation the required element of talent, and it turns out that you would need to be a certified genius to build and maintain a successful Wi-Fi solution from scratch that adhered to all the basic, advanced, and evolving standards requirements involved in an 802.11 product. And that would just be getting to the point of having a device that can connect and exchange data back and forth with other devices, which brings us to all the useful standards for allowing devices to interoperate quickly, easily, and consistently for all users. This can often appear as a complex and confusing “word cloud” with all kinds of related terms (Figure 1). Let’s assume for now that the hardware design is solid, the antenna design is good and will pass FCC, CE, IC, TELEC, RoHS, REACH and any others (like conflict metals requirements), and let us then focus on the software needs of a Wi-Fi enabled device. Consider terms like Apple Bonjour, MQTT messaging protocol, WPS Configuration, ProbMe, WPA Enterprise (TLS, TTLS, EAP), Security Certificates, Roaming support, Serial to Wi-Fi, Secure sockets with TLS support, TCP and UDP protocols, SPI, UART, Over The Air (OTA) system updates, Wi-Fi Direct (P2P), and Wi-Fi Monitor mode (Sniffer Mode). This truly is a case where a Wi-Fi product is 80% hardware and 80% software and 100% about compatibility. For starters, let’s break the primary capability areas of software for Wi-Fi products into three categories: core Wi-Fi functionality, interoperability standards support and advanced features supporting configuration, control, and security. A fourth emerging aspect of Wi-Fi devices that is almost all software based is Cloud/IoT/IoE/M2M connectivity, so let’s add a fourth category, Internet/Cloud connectivity (Figure 2). In order to assess the minimum requirements of a module, and compare apples to apples, the designer should create

a list with which to do comparisons. Table 1 is a high level Pre-Checklist for the ideal IoT module that would effectively eliminate any and all hardware effort and limit development to the software and internet/Cloud connectivity elements to Wi-Fi enable the device: Let’s presume this list of items is in place. Beyond the physical connection of the pins of the module to the rest of the circuitry, what is left to do is to load the code into the module. Note that we are assuming in this case that there is a host processor in place and the module is primarily going to be used as a smart serial/Wi-Fi connection. Otherwise the code for the embedded 32bit MCU would need to be developed as well and the rest of the hardware design fleshed out which would be a separate embedded hardware design article. Let’s just assume the hardware design is done and the module is being dropped in to enable the device with Wi-Fi connectivity, and ultimately, connection to the Internet and Cloud services.

Core Wi-Fi Functionality

Now that we know that we have solid hardware for our module to develop and deploy our design, we need to make sure the core 802.11/Wi-Fi features are in place, accessible, and up to date with the newest standards to make sure the device will function in as many environments as possible (new networks and legacy networks). So we need to confirm that the module supports the following items at the core level. Ideally, this support is included for free as part of the software provided with the module (Table 2).

Interoperability Standards and Support

For devices to communicate with other devices or within a wireless network, they need to have methods and protocols that allow them to interoperate using standard and mutually agreed upon messaging formats. Within Wi-Fi networks there are both basic and advanced capabilities that can be implemented or provided to extend the use of the device for home, commercial,

Figure 2 Wi-Fi based IoT devices require many different types of software in order to effectively communicate their application’s data to local peer devices, wireless network, and up to the Cloud.

RTC Magazine APRIL 2015 | 19


Figure 3 Any and all electronic/electric devices are fair game for connecting to the IoT by the simple addition of a Wi-Fi module. Many of the future IoT devices are things we haven’t even thought of yet. Software that is packaged with the hardware modules makes it simple to enable both existing and future products for Wi-Fi.

and industrial purposes (Table 3). As the use of IoT devices increase, user adoption will largely be driven by the ease and speed of establishing and using the devices in existing and future networks and networked devices. Amongst the myriad rapidly evolving standards and advanced features, it is important that developers provide users the ability to leverage as many of these capabilities given the variety of environments in which devices will be expected to be installed. Some of these advanced features are listed in Table 4.

Internet/Cloud connectivity

The ultimate vision of IoT devices is to be connected to the larger public Internet (world wide web) and be able to easily connect with devices anywhere at any time to leverage the sharing of data to better optimize their own operation (or inform CHECKLIST ITEMS


Available from distributors

In mass production

Development Kits

Application Examples

Technical Support

Manufacturer Representative Support

FCC (CE/IC/TELEC) Certified

RoHS/REACH Certified

Export (CCAT) Approved for Mass Market use

Conflict Minerals (Sn, Au, Ta, Tg) CMRT Certified

802.11 verified

32bit MCU embedded

Flash memory

Integrated Antenna

Tiny footprint

Tiny power consumption

Table 1 Key IoT device features that should form the base for any Wi-Fi module.

20 | RTC Magazine APRIL 2015




Part of the ieee 802.11 Specification that govern wireless networking transmission methods specification, 802.11B specifies throughput up to 11 mbit/s.


Amendment to ieee 802.11 And specifies throughput to up to 54 mbit/s, the available throughput is shared between all transmitting devices.


Amendment to ieee 802.11 For using multiple antennas to increase data rates with a significant increase in the maximum net data rate from 54 mbit/s to 600 mbit/s with the use of four spatial streams at a channel width of 40 mhz.

Software enabled Access Point (SoftAP aka. legacy AP)

Software that enables a device to perform as a wireless access point that was not originally designed or intended to be a wireless access point – sometimes referred to as a “virtual router” or “hotspot”.

Wired Equivalent Privacy (WEP)

Security algorithm for wireless data confidentiality similar to wired networks, wpa superseded wep.

Wi-Fi Protected Access (WPA) and Wi-Fi Protected Access II (WPA2) (WPA/ WPA2-PSK)

Security protocols for secure communications on wireless computer networks, Pre-Shared Key mode (PSK, Personal) typically used in home and small business networks don't use 802.1X authentication server each wireless network device encrypts the network traffic using a 256 bit key.

Wi-Fi Protected Setup (WPS)

WPS 2.0 with PIN or PBC (push button) Provisioning.

Table 2 Core Wi-Fi software functionality that should be at the base of every implementation.

the operation of other devices). In order to get beyond direct personal connections to devices, resources must be available to talk outside of the local area network. The prevailing view is to have these devices talk to Cloud storage locations to capture and share the data with other devices that are also connected to the Cloud (Table 5).

All Wrapped up in a Single Package

Ideally, all of the capabilities from the core Wi-Fi functionality all the way to the evolving Cloud provider connectivity should be provided “out of the box” to a developer so that they need not worry about having to develop, test, and maintain these on their own. In the case of the Econais WiSmart offering this is definitely the case. An increasing number of designers are planning on devices operating autonomously as well as connected to Cloud services – the devices have to be smart enough to perform their functions should they lose connection to their peers in the local network as well as if they were to lose connection with the internet/ Cloud. In effect, these devices need to fail “Smart”. Additionally, the vast amounts of data that will be generated from myriad devices all over a home, commercial, mobile, or an industrial setting, will require that the devices be smart enough to identify “events” that need to be communicated to peer devices, to other devices remote from the local network, or even into the Cloud. The collected data may be held locally (where transmission bandwidth costs are high), not transmitted at all (where power and storage are too expensive), or real-time (where the bandwidth is inexpensive and readily available). It is important to keep in mind the evolving expectations of networks of IoT devices that will increasingly benefit from knowing about and communicating with their peers, operating on their own when a connection may not be available and communicating globally through the Cloud. The libraries for all of these capabilities are provided without

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Application Programming Interface (API)

Includes definitions of inputs, outputs, types, operations, routines, protocols, and tools to help build software applications. API’s can make building connections and software much quicker and easier by providing source code library of components that can be connected together to build a desired application.



Cloud services/connectivity (i.e. Xively, Ayla, Mode and Kaa)

Supplied software and API’s to access IoT directory services, data services, trust engines for security, web-based management applications and other services. IoT platforms as a service (PAAS) messaging built on MQTT, REST, WebSockets, etc.

Dynamic Host Configuration Protocol (DHCP) Client

Network protocol used to request and receive dynamically generated network configuration parameters - typically IP address distributing network configuration parameters, such as IP addresses for interfaces and services.

Message Queue Telemetry Transport (MQTT)

Light weight-messaging protocol for use with TCP/IP protocol, using publish-subscribe method, designed for connections with remote devices with limited bandwidth and low resources in remote locations.

Network protocol used to provide dynamically generated network configuration parameters to client devices that request them automatically in real-time.


DHCP Server

Architecture that provides for the basic HTTP function (i.e. GET, PUT) that is used by web browsers to access and communicate with servers and webpages.

Handles IP assignment and reassignment as well as requests and replies for communications from device applications to communicate with other devices and resources on the network.


DNS Client

Protocol for full-duplex communication over TCP (similar to web browser and web server communication) allowing for real-time communications and keeping an open connection.

File Transfer Protocol (FTP) client

Protocol used to transfer computer files from one device to another device over the network; FTP can be secured with SSL/ TLS (FTPS).

multicast Domain Name System (mDNS)

Used to resolve host names to IP addresses in small networks that do not have a name server and provides for zero configuration.

HTTP Client

Used most commonly to access websites on the internet as a web browser would retrieve information from a website.

Real-Time Operating System (RTOS)

An operating system (OS) included for handling real-time processing of data with little to no delay.

SPI to Wi-Fi

Taking SPI communication and communicating over Wi-Fi to network or other Wi-Fi capable device.

Universal Asynchronous Receiver/Transmitter (UART) to Wi-Fi

Taking serial or parallel data and communicating data over Wi-Fi to network or other Wi-Fi capable device.

TCP/UDP sockets

The standard communication method over TCP or UDP.

Web Configuration

Ability to allow browsers to access the device to configure settings manually.

Table 3 Advanced hardware features supporting configuration, control, and security.



Advanced Power Save Engine

Advanced configurability to manage power saving modes and settings.

Apple Bonjour

Zero-configuration networking enabling automatic discovery of devices and services on a local network.


Leveraging network information to configure resources in the network.

Configurable Web Server

Ability to establish and customize web server in device.

Enterprise Security

Ability to establish and manage certificates in larger business or corporate networks.

Extensible Authentication Protocol (EAP)

Used for authentication, defines message formats.

Fast Soft/Hard Cut Roaming

Providing devices the ability to switch between access points (APs) in a network.

Firewall Protection

Provide the missing layer of security for IoT, block packets by IP, port, protocol and other criteria.

Hypertext Transfer Protocol Secure (HTTPS)

Communications protocol for secure communication by layering HTTP over SSL/TLS protocol to prevent wiretapping and man-inthe-middle attacks.

Over The Air Updates (OTA)

New firmware/software secure deployment from HTTP or FTP server.


Patent Pending, Out of the Box Connection & Mass Configuration Technology.

Secure Sockets Layer (SSL) Encryption

Cryptographic protocol for secure communications over a network - uses a symmetric key approach.

Transport layer security (tls)

State of the art encryption, data protection and integrity, removes backward compatibility to ssl and associated security risks of ssl.

Wi-fi direct p2p client and group owner (go)

Connect directly to other devices without the need of a router. The group owner works as an access point in wi-fi direct.

Wi-fi monitor (sniffer) mode

Capture and log network traffic to identify ssid’s, packet headers, and other statistics on the network.

Wpa/wpa2 enterprise (tls, ttls, eap)

Used in enterprise networks and employ an authentication server with provides increased security and protects against vulnerabilities like dictionary attacks.

Table 4 Advanced features increasingly under demand in wireless connectivity.

22 | RTC Magazine APRIL 2015

Table 5 Resources needed to be able to talk to the Cloud outside the local network.

additional expense for the use of the software on the WiSmart Wi-Fi modules. The Econais libwismart API is a comprehensive and continuously enriched middleware library that enables developers, designers, engineers to simplify and speed the design process with application examples, free toolchain, API’s, etc. In addition, the built in support for IoT device design and additional support resources like Design Support (no matter what size company or product you are working in), online Knowledgebase, and Technical Support, enables device designers to quickly and cost effectively deliver high quality IoT devices and systems. If you had given yourself a quiz on all the terms above before you read all of the descriptions (or even now after you have read them), how many would you have gotten right and how many would you be able to implement by yourself? How large a team would you need to implement, test, verify and support all of the ones relevant to your application? How big would the team and talent need to be to support and maintain the variety of capabilities needed to cost effectively roll out web connected Wi-Fi devices? It makes a lot of sense to consider a Wi-Fi connectivity solution that includes all the software and tech support built in so that your team could get on about the business of getting your device up and running and on the internet as quickly and securely as possible. Econais San Jose, CA (408) 726-3600

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RTC Magazine APRIL 2015 | 23


The Internet of Things and Wireless Communication Standards History has shown that standards wars are costly for both winners and losers alike and will be no different for the IoT. Standard wars are also costly because they delay markets developing as consumers and industries will sit back and wait until “things have settled.” The IoT is an exciting opportunity, and applications are already emerging left and right, but for mass adoption, unified standardization will be essential. by Cees Links, GreenPeak Technologies

One of the things that is often puzzling regarding technology standardization initiatives is the fact there seem to be waves of battling and then waves of useful cooperation. The classic example is the so-called “war” between VHS and Betamax (circa 1980) that resulted in delaying the development of the home video market for quite a while. More recently (around 2007) there was another standards war, this time for optical DVD’s between Blu-ray and HD-DVD. When you look back and analyze the results of these two technology conflicts, it is apparent that standard wars are not effective and that even the winners suffer from long delays of market acceptance and growth. The rising tide of economic activity that results from industry agreement based on uniform standards is always in sharp contrast to stalling markets when standards or pseudo “proprietary standards” compete. Standard wars usually end when a large company or a dominating party in the market makes a choice and creates critical mass. In 1999 Apple decided to use Wi-Fi in its new laptops and, within a matter of months after that decision, HomeRF was effectively gone from the marketplace. Something similar happened with Betamax and HD-DVD, when “Hollywood” put its weight behind VHS and Blu-ray. But these types of swings in favor of one or the other usually only happen after years of stalemates and expensive mudslinging from the trenches.

What is the Internet of Things Battlefield, and who are the leading Players?

After a serious standards war there always seems to be a period of cooperation. The original DVD standard (1995) came together without a lot of fighting, probably because large companies still had vivid memories of the VHS/Betamax war and the economic loss it created. Therefore the market acceptance of the DVD was stunningly fast and videotapes disappeared almost

24 | RTC Magazine APRIL 2015

Figure 1 Overview of the different IoT wireless communication standards mapped on the ISO layering model.

overnight. Figure 1 shows an overview of the most important contenders around the IoT Wireless Communication Standards. For reason of simplicity I have left out the cellular standards, although they do play an important role in the IoT (and the so-called M2M business) as well. However, any contention amongst these standards is a separate chapter. I also left out RFID, also very useful for the IoT for security purposes, but less contentious as it is more like an electronic bar code replacement instead ofdoing real (two-way) communication. Also for simplicity I have left out the proprietary pseudo standards like ANT+, Z-Wave and EnOcean, for the simple reason that like other “non-standard” proprietary standards, I expect they will disappear in a few years. Therefore, the battlefield can be split up into three horizontal combinations of layers: (1) the Physical/Link Layer (“the connector”), (2) the Network/Transport Layer (“the wireless cable”) and (3) the Application Layer (“who is doing what to whom”).

The Physical/Link Layer

There have been several critical Physical/Link Layer (Figure 2) battles in our industry. In 1999 Bluetooth (Bluetooth SIG) was fighting Wi-Fi (IEEE 802.11). That ended when both found their own solid application space and were able to retrench for maybe a next round (Wi-Fi Direct attacking Bluetooth). In the 1990’s Ethernet (IEEE 802.3) was fighting with Token Ring (IBM) and ARCnet (Datapoint). So, with IEEE 802.15.4 becoming dominant in the low-power networking market, there is no surprise that two alternatives, Wi-Fi (with “low power Wi-Fi”) and Bluetooth (with Bluetooth Low Energy) are both sharpening the knives to get a piece of the action as well. But it is fair to say that in this layer, the open worldwide standards—mostly IEEE based—are dominating, and actually there is not so much a war anymore, as most of the contentions are being resolved within standardization bodies. Even though the three major IEEE-based standards are still competing to capture as large as possible application domain, all three – IEEE 802.11/Wi-Fi (content sharing and distribution), 802.15.4/ZigBee (low power sense & control networking) and Bluetooth (wearables) – seem to have found their core application space and will be with us for quite a long time to come. The Network/Transport Layer There have also been some important Network/Transport layer battles in the past. This is a somewhat more obscure area that once was dominated by companies like LAN Manager (IBM, Microsoft), Netware (Novell) and a few others until this field was “democratized” by the Internet Engineering Task Force (IETF) with TCP/IP, that we know as today’s IPv4 or the more recentIPv6, the IETF contribution to the IoT. The IETF also has produced a standard that is called 6LoWPAN (IPv6 over Wireless Personal Area Networks), essentially allowing IPv6 traffic to be carried over low power wireless mesh networks (Figure 3). Recently Google/Nest has adopted 6LowPAN as part of Thread, giving it instant credibility and putting it in direct competition with ZigBee PRO, another contender for this space. ZigBee PRO and Thread (based on the same IEEE 82.15.4 Physical/ Link Layer) have certain advantages over each other. Supporting IPv6, Thread is well integrated in the IP world. In contrast, ZigBee is already widely adopted, integrated with a really broad and thoroughly tested application library (see below) and with proven security and ease of use features, while also very capable of bridging into IPv6. At this moment the Google/Nest Thread Alliance is trying to rally as many members in order to build momentum, but the uptake has been relatively slow: less than 100 members so far, where ZigBee has more than 400 members. Interestingly, many of these Thread members are also ZigBee members! Until the Thread standard is published, the situation will continue to be unclear, and as indicated earlier, creates a wait-and-see attitude in the IoT market, unfortunately slowing down its development. To make the situation even more confusing, there is also another party in this space trying to enter this war at the Network/

Figure 2 The Physical Link Layer.intensive systems with limited power consumption.

Transport Layer. In the Bluetooth SiG there is a serious effort to make Bluetooth “networking capable”. In other words, Bluetooth is trying to enable its networking layer to support not only a set of “wearables” around a single device, but also to extend this to a larger set of independent devices working together in a mesh network. Although completion is not expected before 2017, it will further muddy up the water. The question also is whether Bluetooth Mesh is technically possible. Bluetooth, like Wi-Fi, is “connection-oriented”, while IEEE 802.15 for ZigBee and Thread is packet-oriented, which is very suitable for meshing protocols. Wi-Fi meshing (under IEEE 802.11s) failed miserably in 2001, because overcoming “latency” was too serious a challenge for connection-oriented protocols. At this moment the main differentiator of Bluetooth meshing seems to be the Bluetooth logo. To many people, this new Bluetooth initiative sounds like a repeat of an earlier effort (around 1997-2000) of Bluetooth to displace Wi-Fi by adding networking features: “Bluetooth will wipe Wi-Fi from the face of the earth”, was the slogan that time. As we all know: that project to replace Wi-Fi failed miserably. At this moment, Bluetooth Mesh looks more like an effort driven by engineers searching for an interesting project than fulfilling an unresolved need of the market. This new effort may soon dissipate, just as Bluetooth previously stopped competing with Wi-Fi.

The Application Layer

To really understand the battling at the Application Layer (Figure 4) it is probably good to look at the picture again but instead of looking horizontally, it is better now to take a vertical view to understand what is going on in this space. The Application Layer is the collection of commands and expected results of devices (“things”) communicating with each other. It is the most complex layer, because it covers so many different devices in so many different applications over such a wide range, that at this moment it is hard to see what the real requirements will end up being. Smart systems for the home are totally different compared to smart systems for buildings, or for smart cities (managing streetlights or parking garage vacancies), while industrial RTC Magazine APRIL 2015 | 25

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Figure 3 The Network/Transport Layer

sensors are a separate class on their own. It is no surprise that the Application Layer is vast and diverse. And there is also a lot of continuing learning going on in this layer as well, including interfacing with the cloud, analytics, social media, smart phone apps, etc. The first and most mature contender in this space is the so-called “Cluster Library” that is a part of the ZigBee standard (ZCL). In the ZigBee 3.0 version, this Cluster Library is completely integrated – including the so called application profiles of Home Automation and Lighting, supplemented by Green Power for ultra-low power (e.g. batteryless) applications, and ZRC for ultra-low latency applications, as required for Remote Controls. This ZigBee Cluster Library is very complete and includes very well thought-out security and ease of installation features. Today, it has by far the largest installed base of vendors. The next contender is Apple Home Kit. It is a contender and not so much a standard because Apple Home Kit is proprietary to Apple. Nevertheless, because of Apple’s strong market presence and “following”, Apple Home Kit is developing a clear market presence with applications built on top of Wi-Fi and Bluetooth for networking and low power wearables. Today, Home Kit is not integrated with IEEE 802.15, but it does contain the bridging capabilities to integrate with ZigBee and the ZigBee Cluster Library. The third player in this Application Layer field is the Open Interconnect Consortium driven by Intel and supported by others like Cisco and Samsung. This is a group that recently started their activities and has expressed – like Apple – for a preference for Wi-Fi and Bluetooth as well, with future plans for ZigBee. It has announced IoTivity, an Open Source Project under the Linux Foundation that helps perform Application Layer device identification on the network. The last contributor in this field is the AllSeen Alliance, which interestingly enough, also operates under the umbrella of the Linux Foundation. Their work originally started as the AllJoyn activity under Qualcomm, but they quickly realized that the market is too large, too diversified and too dependent on the development of a complete eco-system, and that pulling this off alone would be too daunting a task. As a result, Qualcomm

has donated all the work done until that time to this AllSeen Alliance that they still continue to chair, but that is further an independent activity. Some observations can be made about all these initiatives to fill in the Application Layer. To start with, there is quite an overlap in membership between these Application Layer contenders, even to the point that not only does the market, but also some of these participating companies seem to be confused as well. For instance, many of the 400+ ZigBee members are also members of the OIC and the AllSeen Alliance, bridging the gaps in between. In addition to these overlaps, these different frameworks also have slightly different focus and are partially complementary. The ZigBee Cluster Library is very focused on describing the functionality of the simple devices (lamps, thermostats, etc.) and as such it is very complete and has matured over years. Apple’s Home Kit is focused on presenting the devices to the user (per house, per room, etc.) and not surprisingly, builds this framework as an extension of the smartphone – using the smartphone as the center of the eco-system. Now, this plays very well for wearables (smartphone “accessories”), but how this for instance would play in the Smart Home still remains to be seen. Nevertheless, both with the market success of the Apple Phone and the fact that Apple is a product company, Home Kit may be with us for quite some time to come. The OIC/IoTivity and AllSeen/AllJoyn activities are probably the most overlapping. Both are focused on special features for discovery of the devices on the network and finding out how these devices communicate, which puts them on an immediate competitive path. Both of them started by/driven by chip companies – contrary to Apple Home Kit. The question is whether they will continue separately in the longer term because both have a relationship with the Linux Foundation. Merging the two together with the ZigBee Cluster Library might be a possible way to go, enabling them to stay competitive with the Apple “proprietary” Home Kit. Embracing the ZigBee Cluster Library, to make use of its maturity and years of real-use hardening, would make sense for any of these frameworks, while the ZigBee Cluster Library can “benefit” from the larger

Figure 4 The Application Layer

RTC Magazine APRIL 2015 | 27

TECHNOLOGY CONNECTED BLUETOOTH, WI-FI AND ZIGBEE framework perspective brought via Wi-Fi and Bluetooth, as this Cluster Library can run over Wi-Fi and Bluetooth alike. An interesting last observation is that Google/Nest is completely absent from this Application Layer, and therefore (theoretically) could work with any of the other already defined application layers. However, the consequence of this absence is that Thread is not a complete standard and that on its own it will not enable interoperable products. Once the Thread standard is released it still will require integration with an Application Layer of some sort. Again it makes sense for Thread to also embrace the ZigBee Cluster Library as only then it would make it into a “complete” standard, or into a standard at all…. So, is this going to be real war or is there going to be reconciliation? Hopefully for all the companies that are looking forward to reap the benefits of the IoT, it is going to be the latter. The sooner this complex material is sorted out, the better it will be. GreenPeak San Ramon, CA (925) 230-6844

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OneBank: Combining Economy and Performance for Stackable Systems The longevity and wide use of the PC/104 form factor has been largely a result of its ability to adapt to advances in technology while retaining backward compatibility to earlier modules. The advent of the OneBank connector is an adaptation for board space and cost that fits in smoothly with existing systems. by Jonathan Miller, Diamond Systems

The PC/104 form factor, with its unique stacking I/O concept, has been a successful mainstay of small form factor embedded systems for over 20 years. This surprising longevity is due to the powerful combination of benefits that PC/104 provides, including small size, rugged design, use of popular “desktop” or PC bus technologies, and wide range of compatible products from an impressive number of participating vendors worldwide. PC/104 is, in its essence, the repackaging of PC technology in a physical format conducive to use in industrial and military applications, including both vehicle and stationary systems. The use of PC technology in PC/104 is an advantage whose importance cannot be overstated. The size of the PC market attracted a huge number of semiconductor and software companies, offering embedded systems users access to a universe of low-cost yet high performance features that all worked together easily. This accelerated the adoption of computers into the industrial world and helped usher in a quantum improvement in the quality of life for global civilization. Although a 20 year lifespan may impart an impression of “old technology”, PC/104 has in fact evolved over this time to stay current with advances in bus technologies, so that it remains as relevant today as it was in 1991. The term “PC/104” actually refers to a family of form factors and bus connectors, all adhering to the basic 3.55” x 3.775” (90 x 96mm) physical size (Figure 1). The original PC/104 form factor utilized the ISA bus, which was the dominant expansion bus for desktop PCs at the time it was invented. When the PCI bus was introduced and became mainstream a few years later, PC/104 evolved to include it on a second connector, resulting in the PC/104-Plus standard. PC/104 evolved once again in 2007 to include the latest arrival on the desktop: PCI Express, or PCIe. The ISA connector, having long since been eliminated from the desktop world, was removed, and a new PCI Express connector was inserted in its

30 | RTC Magazine APRIL 2015

Figure 1 Family of PC/104 form factors from left to right: PC/104, PC/104-Plus, PCI/104-Express, and OneBank. Single-connector configurations may also be used.

place. Although the ISA bus is no longer used in desktop and notebook computers, it still enjoys extreme popularity in the embedded world, due to its simplicity and low cost, plus the desire of embedded customers for long term support. Single board computers with the PC/104 ISA bus connector, using the latest embedded processors such as Intel E3800 “Bay Trail”, are still being introduced today. The PCIe/104 connector, as it is commonly called, consists of a pair of 3-bank surface mount high speed connectors (top and bottom sides of the board). The connectors originally contained a combination of PCIe x1 and x16 lanes. The first bank contains four PCIe x1 links, and the second and third banks contain the PCIe x16 signals. As embedded technology continued to evolve, it became necessary to provide more options to work with a wide range of peripheral chips and modules. So the original connector pin assignment was renamed Type 1, and a new Type 2 arrangement was offered. Type 2 converted the PCIe x16 lanes into a combination of PCIe x4/x8, LPC, USB 3.0, and SATA interfaces. Now the PC/104 Consortium could offer system designers a

STK1 / PEG_ENA# 54 56 GND PEx4_0T(0)p 58 PEx4_0T(0)n 60 62 GND PEx4_0T(1)p 64 PEx4_0T(1)n 66 68 GND PEx4_0T(2)p 70 PEx4_0T(2)n 72 74 GND PEx4_0T(3)p 76 PEx4_0T(3)n PE 4 0T(3) 78 80 GND SATA_T0p 82 SATA_T0n 84 86 GND SSTX0p 88 SSTX0n 90 92 GND Reserved 94 Reserved 96 98 GND SATA_DET#0 100 SATA_PWREN#0 102 104 GND LPC_CLK GND PEx4_0R(0)p PEx4_0R(0)n GND PEx4_0R(1)p PEx4_0R(1)n GND PEx4_0R(2)p PEx4_0R(2)n GND PEx4_0R(3)p PEx4_0R(3)n GND SATA_R0p SATA_R0n GND SSRX0p SSRX0n GND LPC_DRQ# LPC_SERIRQ# GND LPC_FRAME# 3.0V Battery GND

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

USB_OC# 3.3V USB_1p USB_1n GND PEx1_1Tp PEx1_1Tn GND PEx1_2Tp PEx1_2Tn GND PEx1_1Rp PEx1 1Rn PEx1_1Rn GND PEx1_2Rp PEx1_2Rn GND PEx1_1Clkp PEx1_1Clkn +5V_SB PEx1_2Clkp PEx1_2Clkn DIR SMB_DAT SMB_CLK SMB_ALERT

106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156

Figure 2 PCIe/104 Type 2 (left) and OneBank (right) connector pinouts. The OneBank connector pinout is identical to the first bank of both Type 1 and Type 2 PCIe/104 connectors.

comprehensive solution for board to board connection using the complete range of popular “desktop” bus technologies. Customers, however, value not just capabilities but also cost and size. On a small board like PC/104, with only 13.4 square inches of total area and about 11 linear inches of available board edge for I/O connectors, the size of bus connectors becomes a real concern as processors, and the SBCs built around them, become ever more integrated. It’s not uncommon for a PC/104 size SBC today to include 2 or 3 different display options, 4 USB ports, 4 serial ports, 1 or 2 Ethernets, SATA, power in, and perhaps some GPIO. All those connectors require space along the board edges for convenient access. With the top and bottom edges mostly occupied with the expansion bus connectors, only about 5.7 linear inches remains on the left and right sides for I/O connectors. Fitting all the required I/O connectors into that

+5 Vollts

+5 Vollts

105 STK2 / SDVO_DAT 107 GND 109 PEx4_1R(0)p 111 PEx4_1R(0)n 113 GND 115 PEx4_1R(1)p 117 PEx4_1R(1)n 119 GND 121 PEx4_1R(2)p 123 PEx4_1R(2)n 125 GND 127 PEx4_1R(3)p 129 PEx4_1R(3)n 131 GND 133 SATA_R1p 135 SATA_R1n 137 GND 139 SSRX1p 141 SSRX1n 143 GND 145 LPC_AD0 147 LPC_AD1 149 GND 151 LPC_AD2 153 LPC_AD3 155 GND

STK0 / WAKE# GND PEx4_1T(0)p PEx4_1T(0)n GND PEx4_1T(1)p PEx4_1T(1)n GND PEx4_1T(2)p PEx4_1T(2)n GND PEx4_1T(3)p PEx4_1T(3)n PE 4 1T(3) GND SATA_T1p SATA_T1n GND SSTX1p SSTX1n GND Reserved Reserved GND SATA_DET#1 SATA_PWREN#1 GND

+5 Voltts

53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103

small space poses a significant challenge. In addition to their relatively large size, the PCIe/104 connectors, being sole source and high performance, pose additional challenges to vendors seeking to implement low-cost solutions. PCIe/104 has found great traction in markets which value ruggedness and performance over economy, such as military and transportation. That leaves unaddressed a significant portion of the embedded market still seeking the benefits of PC/104 but not willing to pay the higher price. The PC/104 consortium responded to these two challenges by implementing a new, smaller and lower cost version of PCIe/104, called OneBank. The goals of the OneBank project were straightforward: Provide a smaller, lower cost way to achieve PCIe/104 stackable expansion, and maintain compatibility with existing PCIe/104 products to protect both vendor and customer investment in existing products and applications. The pinout of the PCIe/104 connector provided an easy way to accomplish these goals with minimal impact to overall performance. The most popular interfaces, including 4 PCIe x1 links and 2 USB 2.0 links, were already present on the first section, or “bank”, of the connector, along with 5V power, 3.3V power, and 5V standby power. Consequently, the first bank was sufficient for a large number of embedded applications without requiring any changes. Therefore it was decided to eliminate the two additional banks and retain only the first bank (Figure 2). This resulted in a size reduction of 60% and a cost reduction of similar magnitude. A newly tooled set of connectors from Samtec made OneBank a reality and ensured full physical compatibility between OneBank and “standard” PCIe/104 boards. The smaller OneBank connector yields a valuable 1.7” of

OneBank™ 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

+12 Voltts

106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156

Bank k1

SDVO_CLK GND PEx16_0R(0)p PEx16_0R(0)n GND PEx16_0R(1)p PEx16_0R(1)n GND PEx16_0R(2)p PEx16_0R(2)n GND PEx16_0R(3)p PEx16_0R(3)n GND PEx16_0R(4)p PEx16_0R(4)n GND PEx16_0R(5)p PEx16_0R(5)n GND PEx16_0R(6)p PEx16_0R(6)n GND PEx16_0R(7)p PEx16_0R(7)n GND

Bank 2

STK1 / PEG_ENA# 54 56 GND PEx16_0T(0)p 58 PEx16_0T(0)n 60 62 GND PEx16_0T(1)p 64 PEx16_0T(1)n 66 68 GND PEx16_0T(2)p 70 PEx16_0T(2)n 72 74 GND PEx16_0T(3)p 76 PEx16_0T(3)n PE 16 0T(3) 78 80 GND PEx16_0T(4)p 82 PEx16_0T(4)n 84 86 GND PEx16_0T(5)p 88 PEx16_0T(5)n 90 92 GND PEx16_0T(6)p 94 PEx16_0T(6)n 96 98 GND PEx16_0T(7)p 100 PEx16_0T(7)n 102 104 GND

PCIe/104 Type 2 USB_OC# PE_RST# 3.3V 3.3V USB_1p USB_0p USB_1n USB_0n GND GND PEx1_1Tp PEx1_0Tp PEx1_1Tn PEx1_0Tn GND GND PEx1_2Tp PEx1_3Tp PEx1_2Tn PEx1_3Tn GND GND PEx1_1Rp PEx1_0Rp PEx1 1Rn PEx1_1Rn PEx1 0Rn PEx1_0Rn GND GND PEx1_2Rp PEx1_3Rp PEx1_2Rn PEx1_3Rn GND GND PEx1_1Clkp PEx1_0Clkp PEx1_1Clkn PEx1_0Clkn +5V_SB +5V_SB PEx1_2Clkp PEx1_3Clkp PEx1_2Clkn PEx1_3Clkn DIR PWRGOOD SMB_DAT PEx_x4_Clkp SMB_CLK PEx_x4_Clkn SMB_ALERT PSON#

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

Bank 3

105 STK2 / SDVO_DAT 107 GND 109 PEx16_0R(8)p 111 PEx16_0R(8)n 113 GND 115 PEx16_0R(9)p 117 PEx16_0R(9)n 119 GND 121 PEx16_0R(10)p 123 PEx16_0R(10)n 125 GND 127 PEx16_0R(11)p 129 PEx16_0R(11)n 131 GND 133 PEx16_0R(12)p 135 PEx16_0R(12)n 137 GND 139 PEx16_0R(13)p 141 PEx16_0R(13)n 143 GND 145 PEx16_0R(14)p 147 PEx16_0R(14)n 149 GND 151 PEx16_0R(15)p 153 PEx16_0R(15)n 155 GND

+5 Vollts

STK0 / WAKE# GND PEx16_0T(8)p PEx16_0T(8)n GND PEx16_0T(9)p PEx16_0T(9)n GND PEx16_0T(10)p PEx16_0T(10)n GND PEx16_0T(11)p PEx16_0T(11)n PE 16 0T(11) GND PEx16_0T(12)p PEx16_0T(12)n GND PEx16_0T(13)p PEx16_0T(13)n GND PEx16_0T(14)p PEx16_0T(14)n GND PEx16_0T(15)p PEx16_0T(15)n GND

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

+5 Voltts

53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103

PCIe/104 Type 1 USB_OC# PE_RST# 3.3V 3.3V USB_1p USB_0p USB_1n USB_0n GND GND PEx1_1Tp PEx1_0Tp PEx1_1Tn PEx1_0Tn GND GND PEx1_2Tp PEx1_3Tp PEx1_2Tn PEx1_3Tn GND GND PEx1_1Rp PEx1_0Rp PEx1 1Rn PEx1_1Rn PEx1 0Rn PEx1_0Rn GND GND PEx1_2Rp PEx1_3Rp PEx1_2Rn PEx1_3Rn GND GND PEx1_1Clkp PEx1_0Clkp PEx1_1Clkn PEx1_0Clkn +5V_SB +5V_SB PEx1_2Clkp PEx1_3Clkp PEx1_2Clkn PEx1_3Clkn DIR PWRGOOD SMB_DAT PEx16_Clkp SMB_CLK PEx16_Clkn SMB_ALERT PSON#

+12 Voltts

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

PE_RST# 3.3V USB_0p USB_0n GND PEx1_0Tp PEx1_0Tn GND PEx1_3Tp PEx1_3Tn GND PEx1_0Rp PEx1 0Rn PEx1_0Rn GND PEx1_3Rp PEx1_3Rn GND PEx1_0Clkp PEx1_0Clkn +5V_SB PEx1_3Clkp PEx1_3Clkn PWRGOOD Reserved Reserved PSON#

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

xxx xxx

4 PCIe x1 2 PCIe x4 PCIe x16 2 USB 2.0 2 USB 3.0 2 SATA 1 LPC 1 SMB Misc. Power/Ground

Figure 3 Diamond Systems ATLAS N2800 SBC in OneBank form factor. OneBank connector is in lower left corner.

RTC Magazine APRIL 2015 | 31


Figure 4 Lane shifting ensures each board has access to an available PCIe or USB link. Boards mounted above the host processor use the first link, and boards below use the last link. A top/bottom signal on the connector determines which link is selected.

board edge back to the board designer, an increase of almost 30%. This extra space can support up to 3 I/O connectors on each side of the PCB, significantly simplifying the design of SBCs with high I/O integration. An example of a OneBank SBC is the Atlas N2800 board from Diamond Systems (Figure 3). As can be seen, the smaller OneBank connector in the lower left corner of the board makes room for two additional I/O connectors along the bottom edge. The OneBank connector inherits all of the design features of the full-size PCIe/104 system. One important feature is lane shifting. Unlike the multi-drop nature of ISA and PCI, PCIe and USB are point to point buses. Each device (I/O board) requires its own dedicated link to the host processor. In a multi-board system, how does a board know which link to use? Lane shifting

Figure 5 Diamond Systems E104-MPE-04 OneBank quad Minicard carrier utilizes 22mm stacking height connectors to provide adequate room for Minicards and I/O cables.

32 | RTC Magazine APRIL 2015

eliminates the problem. Each board always takes its host interface from the same position on the bus connector. It then shifts the remaining lanes over before passing them on to the other connector on the other side of the board. Figure 4 illustrates how lane shifting works. In this manner, each board is automatically given access to a dedicated host connection without any configuration required by the user. OneBank boards offer two board-to-board spacing heights: The original PC/104 0.6” / 15.24mm and a larger 0.866” / 22mm. The standard 0.6” spacing is more common and provides compact, high-density board stacks. The extended 22mm spacing enables the use of mezzanine sockets on OneBank boards, such as PCIe MiniCards and SATA disk-on-modules. One example of a 22mm board is the E104-MPE-04 PCIe/104 quad minicard carrier from Diamond Systems (Figure 5). Using this carrier,

Figure 6 Two OneBank formats are defined: OneBank alone (left) and OneBank with PCI-104 (right).

one “slice” of a OneBank stack can contain up to 4 I/O modules, resulting in unprecedented levels of feature density. (One of the sockets is dual-mode and can also support an mSATA flashdisk.) As with “standard” PCIe/104, OneBank boards may be implemented either with or without the PCI-104 connector on the upper edge of the board (Figure 6). A OneBank board containing the PCI-104 connector will generally treat it as a “pass-through” connector, meaning the connector will pass the PCI bus between boards above and below without actually using them. This enables a system designer to include a mix of PCI104 and OneBank boards in the same stack. OneBank boards may be combined with “standard” PCIe/104 boards in a stack. Figure 7 shows boards of each type mated. When the two types of boards are mixed, the “standard” boards should be installed first (closest to the SBC), and the OneBank boards should be installed last (in the outermost positions of the stack). How many OneBank boards can be used together in a system? The answer may be derived from the signals on the connector: 4 PCIe x1 links + 2 USB 2.0 links means 4 PCIe I/O modules + 2 USB I/O modules may be used, for a total of 7 boards (includ-

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1TB DDR4-2133MHz memory in 24 DIMM slots 1 PCI-E 3.0 x16, 1 PCI-E 3.0 x16 “0” slot; and 1 PCI-E 3.0 x8 slot (TwinPro™) 4 ports NVMe 8 SAS 3.0 (12Gbps) ports with LSI® 3108/3008 controller, with optional SuperCap (CacheVault) 8 SATA 3.0 (6Gbps) ports with Intel® C612 controller 12 (TwinPro) or 6 (TwinPro²) hot-swap 2.5” HDD drives per Node FDR (56Gbps) InfiniBand, Dual 10GBase-T or Dual Gigabit Ethernet LAN options Redundant Titanium (96%+) / Platinum (95%+) Level Digital power supplies Integrated IPMI 2.0 plus KVM with dedicated LAN GPU/Xeon Phi™ option SATA-DOM and mSATA support Up to 36 Cores per system and 145W TDP dual Intel® Xeon® Processor E5-2600 v3 product family

© Super Micro Computer, Inc. Specifications subject to change without notice. Intel, the Intel logo, Xeon, and Xeon Inside are trademarks or registered trademarks of Intel Corporation in the U.S. and/or other countries. All other brands and names are the property of their respective owners.


Breaking the Chains! Open and Flexible System Architecture for Safe Train Control Rugged Computer Boards and Systems for Harsh, Mobile and Mission-Critical Environments n

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Compliant with EN 50155

34 | RTC Magazine APRIL 2015

Figure 7 OneBank and standard PCIe/104 boards can be combined together in a system. Here a OneBank board is installed above a standard PCIe/104 board.

ing the processor), or 8 if you add a DC/DC power supply. That should be plenty for all but the most I/O-intensive applications. If the PCI-104 connector is also present, then an additional 4 PCI-104 I/O modules can be added to the stack. Although OneBank was just introduced in January 2015, boards are already available from multiple vendors, including Diamond Systems, VersaLogic, Advanced Micro Peripherals, and Sundance Multiprocessor Technology. The range of available products includes SBCs, serial port modules, minicard carriers, FPGA modules, USB ports, and video capture modules. This quick adoption is an indication of strong vendor support that will result in a wide range of products and long lifetime for the OneBank form factor, valuable benefits that users of PC/104 already know well. The OneBank specification is available for free download at as part of the newly released PCI/104-Express Specification Version 3.0. There are no royalties or licenses required in connection with the use of the OneBank connector by board designers. Diamond Systems Mountain View, CA (650) 810-2500




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RTC Magazine APRIL 2015 | 35 #52DAC


Intel Architecture versus the FPGA: The Battle of Time, Complexity and Cost The continued evolution of Intel architecture (IA) enables electronic OEMs to consider it for applications previously requiring an FPGA. The benefits brought by IA are decreased development time, lower project cost, and high performance with feature integration. by Matt Stevenson, WIN Enterprises

36 | RTC Magazine APRIL 2015

vironment. All of the devices and interfaces are well defined, allowing direct code migration with other IA platforms. Software development kits can be utilized to add more features and speed development. In addition, IA processors provide ready access to a wealth of existing applications, solution suites, operating systems, tools and utilities that come from a well established IA ecosystem of software and hardware developers.

FPGA Advantages

Figure 1 The Classic FPGA schematic with Configurable Logic Blocks (CLB), I/O Blocks (IOB) and interconnecting metallic matrix. External Flash is used to retain the FPGA’s memory which is volatile.

“Clay is fashioned into vessels; but it is on their empty hollowness that their use depends.” -- Tao Te Ching, Lao Tzu FPGAs have no intended function when you buy them; but they gain value through their impressive potentiality. They have broad flexibility and can be applied to virtually any digital processing problem. They arrive at their impressive flexibility through three interconnected physical features, each of which is configurable: • Tens of thousands or more of Configurable Logic Blocks (CLB) • Thousands of configurable I/O Blocks (IOB) • A metallic matrix that surrounds CLBs and IOBs interconnects all the FPGA’s elements and is also configurable (Figure 1). The IA microprocessor and FGPA are applied in substantially different ways. The FPGA is characterized by its extreme flexibility and an ability to handle massively parallel processing tasks that are often repetitive in nature. The extreme flexibility means developers essentially handcraft the chip. Features are built using sections of Logic Blocks. This enables the developer to optimize code size and operating efficiency within the bounds of the selected FPGA. Layouts are made as elegant and unconvoluted as possible so as not to impede performance. Given proper design technique, the fact that the FPGA layout is largely handcrafted and optimized by the developer renders I/O functions highly unconstrained. The latest generation of IA processors with their large internal cache and powerful, general purpose multi-core architecture, still provide programmers with a flexible and familiar work en-

FPGAs can do virtually any task, and though incredibly complex, their manufacturers have adopted techniques to ease the development task. Rather than requiring the developer to handcraft every single feature, FPGAs can now be purchased with a number of dedicated functional units, such as embedded processing cores, DSP blocks with multipliers, Ethernet controllers, DSP cores, and RAM blocks. In addition, FPGA manufacturers now produce chips preconfigured with support for certain features, such as: serial processing, I/O optimization, digital signal processing (DSP), and various feature combinations. FPGAs provide their high performance by enabling a high task count per clock cycle. This serves many applications well. Networking applications, for instance, like high-speed processing of small packets, and similar instances where the parallel execution capabilities can be leveraged to increase output for a given cycle. The use of higher-end FPGAs is generally limited to products that can support the higher unit cost incurred due to a long development time and the testing required across development



Unit Price

High-end FPGAs are expensive relative to IA processors and cheaper FPGAs are too limited.


Projects often require several highly trained specialists of inherently expensive skill sets.

Longer Development Cycles

The ammount of expertise and setup required typically result in a much longer development cycle.

Expansive Proprietary Development Tools

Development boards and software module licenses are often expensive upfront costs.

Product Selection

It can be hard to identify the correct FPGA since much of the design process must begin before the selection.

Complex Languages

Develpment languages (HDL, VHDL, Verilog) are complex and designed to model electronic systems.

Table 1 The Drawbacks of FPGA Implementation

RTC Magazine APRIL 2015 | 37


Figure 2 Intel QuickAssist Technology Acceleration Abstraction Layer (AAL) block diagram.

and production phases. High FPGA development cost can be amortized over larger production runs, but often when the production numbers get really large either an IA or ASIC approach is likely to be considered. ASIC’s are more efficient because they eliminate the waste of the FPGA’s unused transistors. Although these savings are minimal, production cost for these dedicated, more streamlined devices is lower. However, ASIC’s present even greater development cost with even longer development time than the FPGA. Also, once an ASIC is produced, it can not be modified. IA and FPGA solutions are always modifiable, IA through the use of socketed CPUs, or for either approach, by simply modifying the software. Naturally, there are drawbacks to the FPGA.

as Linux, C and C++. The three development languages of the FPGA world, i.e., HDL, VHDL, and Verilog, are not standard programming languages. They are meant for designing electronic devices. Programming an FPGA is more akin to designing an ASIC or a CPU chip from scratch than writing an application that runs on a preconfigured processor. When a solution provider decides to use an FPGA, there is an element of line balancing from the human resource perspective. Assuming the project is to be done in-house, the new project will typically be competing for scarce resources. If in-house talent can’t take on the project in the required timeframe, it will have to be outsourced or a new hire(s) made. Typically, the IA approach to development is much less constrained due to the relative abundance of this type of expertise and the lesser time demands of the project. In general, developers who work with FPGA’s are highly trained and highly paid—and for good reason. Just selecting and sizing the optimum FPGA for a particular project is difficult and time consuming. A summary of some of the drawbacks to using an FPGA is given in Table 1.

The Advantages of Using IA

When would an FPGA be the better choice for your project? The FPGA will continue to be appropriate for environments where a system must react to events with ultra-tight timing parameters and where massive I/O with the least possible latency is a critical need, as in certain networking applications. The major advantages of IA as a development environment are: • Ease of Use -- IA presents a familiar development environment with no shortage of affordable experts.

FPGA, Like Driving the Streets of Boston

Designing an FPGA is like driving the streets of Boston. If you haven’t done it many times before, it’s going to be a painful experience. FPGA implementations are more complicated and difficult than programming and debugging IA microprocessors. You select an FPGA only when the extra speed and lower latency are more critical than shorter development time. FPGA’s are good choice when you need to perform a little processing on a lot of data. The closer the application is to a straight I/O function, the better. IA and other x86 CPUs are good when you need more sophisticated processing. Another potential counter-indication for the use of an FPGA is the need to perform floating point calculations. FPGA’s can do these functions, but find them resource intensive. Any throughput advantage gained risks being compromised or lost. Chip selection is further complicated by the nonstandard architectural terms used by the major FPGA vendors. For example, Xilinx® uses the term Logic Cell while Altera® uses Configurable Logic Block (CLB). Also, the basic features such as the number of look-up-tables (LUTs) per logic block can vary from manufacturer to manufacturer. Lastly, the FPGA programming languages are not intuitive and do not resemble the familiar languages of the IA world, such 38 | RTC Magazine APRIL 2015

Figure 3 The Intel Data Plane Development Kit enables integrated networking across the four Enterprise workloads. Solution providers utilizing DPDK in various software suites include: Wind River, 6WIND, Radisys and Tieto.

quickly and easily design a full range of communications solutions, including secure routers, high-performance web appliances, and hot-pluggable blades, to support scalable, high-capacity routing.

Intel DPDK Accelerator Abstraction

Figure 4 WIN SoNIC is a reference platform for Intel-based Next Generation Communications Platforms. The board is an advanced networking preprocessing card that can be used with new and existing servers.

• Ubiquity -- more than any other architecture, IA pervades hardware and software systems. • Aggressive Development -- Intel continually pushes development for higher performing, lower power consuming, and more feature-integrated processors. There is certainly room for both approaches. For example, WIN Enterprises uses FPGAs in its single board computers (SBC) and systems for gaming applications. These manage several functions, such as various digital GPIOs to/from lamps, meters, solenoids, motors, buttons, switches and sensors and other functions like battery-operated intrusion detection, hardware intelligence and random number generation. FPGAs are also used by the company in custom network platforms for network acceleration. An example of how IA can be used as a viable alternative to FPGAs is their use for the development of networking products that support Intel’s Next Generation Communications platform. This is an environment where products must support system-wide scalability, security (IPS, IDS), flow classification, virtualization, SSL acceleration and termination, high-speed routing and forwarding, etc. In today’s resource constrained world of Enterprise IT and call centers, systems not only need to scale, they need to scale without adding additional complexity or operating costs. The nature of IA has changed greatly from the early days of x86 processors. As chips and their components have continued to shrink, new powerful features have been integrated to keep the overall size more or less the same. In addition to more powerful chips, another result is that manufacturers don’t have to continually retool to accommodate a continued miniaturization of processors.

Integrated Intel QuickAssist

Intel QuickAssist Technology, an Accelerator Abstraction Layer (AAL), is now integrated into many high-end IA processors and chipsets. Intel QuickAssist Technology supports IPsec, SSL, and wireless security protocols to provide integrated security and data compression (Figure 2). When Intel Quick Assist Technology is combined with the Intel Data Plane Development Kit (Intel DPDK). OEM are able to more

In the Next-Generation Network (NGN) a major need is to deal with the convergence of virtualized IT Data Centers and telecommunications networks. These previously disparate networks must now converge to handle all types of information and services such as voice, data, video, etc. By their nature telecom networks tolerate extremely little latency and have significantly higher throughput needs than most IT data networks. To a large extent, the integration challenges define the Next-Generation Network. An enabling technology for the development of Next Generation network solutions is the Intel Data Plane Development Kit (Figure 3). The Intel DPDK is used by Intel ecosystem members like 6WIND, Wind River and others to develop packet processing software and software solution suites. In turn, this software is used by OEM customers and end-user companies to implement integrated, security-centric enterprise and call center solutions. These companies are members of the Intel Internet of Things Solutions Alliance, which helps members working together on new solutions. For instance, WIN Enterprises, another IoT alliance member, provides board- and platform-level hardware devices that support the networking and packet processing software developed by these partners. This work is helping to provide the transition to the Next Generation Network. Application areas where solution providers can consider an IA approach have broadened. They include enterprise, data center and edge networking applications, such as: • SSL Acceleration and termination • Routing and forwarding • Flow classification • Layer 4 Packet Processing • VLAN • Security (IPS, IDS) • SSL Encryption • Network & Storage Data Compression • WAN Optimization • TCP/IP Offload • Virtualization • Pattern Recognition & De-duplication As an example of a Next Generation Network product that WIN Enterprises has developed is the WIN SoNIC preprocessing card. It can be used with new and existing servers to enhance network performance. Customer-specific variants of the WIN SoNIC reference design have been developed, such as a blade with multiple instances of the acceleration card (Figure 4). These board-level products present customers with an attractive alternative to FPGA solutions which would be more costly RTC Magazine APRIL 2015 | 39

INDUSTRY WATCH PROCESSORS VS. FPGAS and time consuming to develop. Customers gain the advantages of IA such as future-proofed scalability and advancements in security. Moore’s Law will continue live and evolve, inviting continued feature integration into IA processors. As previously mentioned, FPGAs can now be ordered with microprocessors included; and keeping things symmetrical, Intel has announced that it will integrate an FPGA into an Intel Xeon processor E5 as a means to

further accelerate application performance. This means IA and FPGA will be in the same socket. When available, this will give developers serving the Enterprise and datacenter segments with another option. WIN Enterprises, North Andover, MA (978) 688-4884.

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ADL Embedded Solutions, Inc. Phone: (858) 490.0597 Email: Web: 40 | RTC Magazine APRIL 2015

Scalable GigE Switches • Stacking, expandable 1 Gbps Ethernet switches • Board-level 10-pin headers or RJ-45 jacks • Eight ports per board, and expandable in groups of eight • Can be used standalone or with a host computer • Link, activity, and speed LEDs for each port • Stackable PCI Express (PCIe/104) expansion • Enclosure configurations with D-sub receptacles, RJ-45 jacks or watertight military cylindrical connectors • Fanless -40 to +85°C Operation • AS9100 & ISO 9001 Certified

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Copyright Š 2014 High Assurance Systems, Inc.APRIL All rights2015 reserved RTC Magazine | 41


USB Type-C Controller in Ultra-Small Package for USB 3.1 Cables and Cable Adapters Ultra-Compact Fanless Quad-Core Embedded Computer based on Atom SoC E3845/E3826

An ultra-compact fanless embedded platform is based on Intel Atom SoC E3845/E3826 processors, delivering impressive computing performance. The MXE-200/200i Series from Adlink Technologieshas an aluminum housing that withstands industrial grade EMI/EMS (EN 61000-6-4, 61000-6-2) and is fully operable under harsh conditions. Meeting a wide variety of specific industrial needs, the rugged MXE-200/200i series combines controller and gateway functions in one unit, significantly reducing space/wiring and device costs. The MXE-200/200i provides superior construction to withstand industrial grade EMI/EMS (EN 61000-6-4/EN 61000-6-2), making it a reliable embedded platform for use in harsh environments. The MXE-200/200i also optimizes MTBF with an extended operating temperature range of -20°C to 70°C, outstanding vibration/shock sustainability of 5 Grms and up to 100 G, and long-term availability. Full support for the Intel® IoT Gateway, integrated Wind River® Intelligent Device Platform XT, McAfee Embedded Control, and Adlink’s proprietary Smart Embedded Management Agent (SEMA) Cloud solution all maximize manageability and security, protecting customer assets and increasing business value for a world of applications. The MXE-200i’s proven versatile connectivity for wired and wireless communication delivers the benefits of the most reliable ready-to-use M2M solutions. The MXE-200/200i features two GbE LAN, two COM, two USB 2.0 and one USB 3.0 host ports, four optional isolated DI and four isolated DO w/ interrupt support, dual mini PCIe slots with one mSATA support and USIM socket support communication with connections such as WiFi, BT, 3G and LTE, to ensure interoperability between systems and maximum industrial connectivity to meet specific industrial needs. The Adlink MXE-200 Series models, MXE-201 and MXE-202, are equipped with quad-core Intel Atom processor E3845 and dual-core Intel Atom processor E3826, respectively, and the MXE-202i with dual-core Intel Atom processor E3826 with Wind River IDP XT 2.0 preloaded.

ADLINK Technology, San Jose, CA (408) 360-0200. www.adllinktech.cpm

42 | RTC Magazine APRIL 2015

Cypress Semiconductor Corp. (NASDAQ: CY), the USB market leader, today sampled An ultra-small footprint, integrated USB Type-C cable controller solution includes power delivery (PD). Optimized for 2.4-mm thin USB Type-C cable connectors, the programmable EZ-PD CCG2 controller from Cypress Semiconductor is fully capable of supporting any USB Type-C Downstream Facing Port (DFP) or Upstream Facing Port (UFP) applications. EZ-PD CCG2 is available in a 3.3 mm2 Wafer Level Chip Scale Package (WLCSP) and is the first programmable solution to fully integrate both the Type-C transceiver and termination resistors needed for Type-C communication. The USB Type-C standard is gaining rapid support with top-tier PC makers by enabling slim industrial designs, easy-to-use connectors and cables, the ability to transmit multiple protocols, and 100W PD—a significant improvement over the previous 7.5W standard. However, the Type-C standard requires an electronically marked cable assembly (EMCA) that can report the characteristics a cable supports, such as current carrying capability, protocols supported, and vendor identification. A standard microcontroller may be used for the EMCA implementation, but it makes the design complex by requiring multiple external ICs and passive components. The Cypress EZ-PD CCG2 Type-C controllers solve this challenge with unprecedented integration and bill-of-materials savings with only five or fewer external components required. This makes them suited for passive and active EMCA cables, as well as for cable adapters that enable users to connect devices with a Type-C port to devices with DisplayPort or HDMI ports. The EZ-PD CCG2 controller comes with on-die System Level ESD protection (8kV Contact Discharge, 15kV Air Discharge), eliminating the need for external components for this protection and resulting in a smaller footprint and bill-of-materials reduction. The controller has an ARM Cortex-M0 core and 32kB of Flash, providing design flexibility with firmware that can be upgraded during product development, in the production line, or in the field. This feature is particularly helpful for future USB-IF specification changes, which can be addressed simply with a firmware revision to achieve compliance. The CYPD21XX CCG2 Type-C Cable controller will be available for production in June. CCG2 is available in 20-ball WLCSP and 14-pin DFN packages.

Cypress Semiconductor, San Jose, CA (408) 943-2600.


System Analyzer to Speed Optimization of IoT Applications

A real-time performance monitoring tool for IoT systems helps identify and optimize areas where optimization of highly networked activity is critical for the success of the system. ViewX can from Express Logic be used to optimize IoT systems using Express Logic ThreadX RTOS and NetX TCP/IP protocol stack on most 32-bit architectures with dynamic data capture easily defined by the user. With such analytical capabilities, ViewX gives developers system transparency into the complex workings of a highly networked IoT application. ViewX, a host PC-based application, tracks target system events and provides visibility into those events in graphical or spreadsheet format. Users control the types of data collected and displayed, the format of display, and the frequency of data capture and collection. Data is collected by an agent thread that transfers snapshots of activities to the host via WiFi, Ethernet, USB, UART, or JTAG. The snapshot capture, upload, and display can be periodic, at user-specified intervals, on demand or can be archived on the host for subsequent analysis. ViewX captures three categories of data, giving the user many ways to optimize a system. First, with insight into CPU activity, ViewX shows developers which threads are using most of the CPU cycles and which threads might not be getting enough CPU time to complete their activities. In addition, ViewX shows each thread’s stack usage, enabling optimization of memory use by thread stacks. Allocating too much memory for a thread’s stack wastes memory, while allocating too little can lead to stack overflow. Finally, ViewX captures metrics that show network throughput, packets sent/received/re-transmitted, or dropped, and packet pool use. If the packet pool is exhausted, network transfers can be impacted while waiting for memory to be returned to the pool. This is particularly helpful for IoT as many small IoT devices don’t have the luxury of large memory and deep queues for re-transmission. When a packet is queued for re-transmission, that means one less packet is available for a new reception or transmission. ViewX helps solve this problem by making resource utilization and throughput completely visible at all levels of communication/system load. Designed to be flexible, ViewX can analyze and show the behavior of systems running on over 20 architectures, including ARM architectures, MIPS, Tensilica, ARC, along with many more. As well, the agent thread retrieves only that data specified by the user through the ViewX interface, but its ANSI C code enables it to be easily customized to dynamically include or exclude information. ViewX will be licensed at prices starting at $5,000 for three developer seats.

Fanless Embedded System with 5th Generation Core SoC and 4K Display Support

A compact fanless appliance has the ability to serve the distributed computing needs of various vertical segments such as manufacturing, retail and medical. The PL-80670 from WIN Systems belongs to the new generation of Intel 14nm IoT solutions that provide enhanced graphics and increased compute performance. This new generation of Intel processors maintains backward capability with devices using previous generation processors. PL-80670 features a rugged aluminum chassis that’s just 225mm (W) x 140mm (D) x 35mm (H) and appropriate for deployment in harsh environments. Key features include a fifth Generation onboard Intel Core series SoC supported by up to 8GB of 1600MHz DDR3L memory. It supports a 4K resolution display via HDMI 1.4a and a 2x HDMI, 1x 2.5” removable HDD driver bay and SATA, 2x MiniPCIe. Interfaces include 4x USB, 4x COM and 2x GbE LAN. The unit can take DC 8V~32V input. WIN Enterprises, North Andover, MA (978) 688-2000.

Express Logic, San Diego, CA (858) 613-6640.

RTC Magazine APRIL 2015 | 43


COM Express Module Brings New Performance to Applications Constrained by Power and Size

A new Type 10 Mini COM Express module is based on the NVIDIA Tegra K1 system-on-chip (SOC) - enabling it to deliver 326 GFLOPS of performance, well beyond the performance typically associated with Mini COM Express. The mCOM10K1 from GE Intelligent Platforms is tarkgeted for applications where very high performance in data-intensive applications, rugged reliability in harsh environments and very compact size need to be combined. In addition to extending GE’s COM Express offering, the mCOM10K1 also brings GE’s powerful general purpose processing on a graphics processor (GPGPU) capability within reach of the significant number of applications where power consumption needs to be 10 watts or less. In the commercial environment, devices with the level of capability of the mCOM10K1 will be key enablers for the Industrial Internet and the Internet of Things, and will see deployment in industrial process automation, automotive and transportation, medical imaging and so on. In military/aerospace, target applications include image and video processing, sensor processing and electronic warfare. The mCOM10K1’s on-board components are specifically selected for their reliability in demanding conditions. Unlike solutions designed for benign environments, the processor and memory are soldered to the board for maximum resistance to shock and vibration. Extended mechanical construction protects the module, which is designed for optional conformal coating to provide additional resistance to moisture, dust, chemicals, and temperature extremes. With full CUDA support, Tegra K1 brings two compute-intensive benefits. First, GPGPU code can be easily ported to other platforms, meaning that an application need be developed only once for a broad range of performance/watt solutions. Second, it leverages the extensive infrastructure of third party tools and open standards libraries that mean that application development is faster and at lower cost. The mCOM10K1 features 2 GB of memory; integrated HDMI and LVDS interfaces; Gigabit Ethernet; a SATA interface; PCI Express (Gen 2); and five USB ports and a USB 3.0 port. GE Intelligent Platforms, Charlottesville, VA +44 (0) 1327 322821.

44 | RTC Magazine APRIL 2015

Software Life Cycle Traceability Gives Customers Leading Edge in Critical Software Verification

A leading-edge software life cycle traceability and verification system enables developers to bidirectionally link industry-standard objectives, functional requirements, design, code, and test artifacts to the people responsible for those activities. By helping define, enforce, and demonstrate a comprehensive verification workflow, TBmanager from LDRA provides companies with the audit trail needed to achieve regulatory compliance of safety-critical standards. TBmanager enables development and verification organizations in industries such as aerospace, automotive, industrial controls, rail and medical to expedite development, improve product quality and decrease potential qualification and certification costs. By seamlessly and bidirectionally linking system artifacts across the software life cycle, TBmanager gives developers immediate visibility of and access to project status in terms of both process and the artifacts being produced and maintained. As a result, project managers can immediately analyze the impact of a requirements change on design, code, and verification activities. For compliance management and verification activities across the software life cycle, TBmanager imports and leverages requirements from both requirements management and authoring tools, such as IBM Rational DOORS, IBM Rational RequisitePro, and Microsoft Office products. With links connecting the requirements to all other system and software artifacts, developers gain visibility into the software life cycle both up- and downstream. TBmanager captures and aggregates results from the LDRA tool suite’s in-depth static and dynamic analysis tools to provide detailed code quality analysis and structural code coverage analysis as well as unit and integration testing processes and the resulting artifacts. LDRA Technology, Atlanta, GA (855) 855-5372.

RTC Magazine APRIL 2015 | 45


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April 2015