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Intel Pushes the Performance Envelope Smart Controllers Connect Solar Power to the Grid Vision Systems Move into Manufacturing The Magazine of Record for the Embedded Computer Industry

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Vol 15 / No 11 / Nov 2014

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The Magazine of Record for the Embedded Computing Industry




Intel Firmware Support Package for the Internet of Things by Jiming Sun, Intel


Keeping Pace with Intel’s High Performance Focus by Austin Hipes, Unicom Engineering



Graphics Processing Fuels Growth in Embedded Computing





by Manish Bhardwaj, Texas Instruments



“Dot-Org” Boards—A Symptom of Advancement and a Source of New Designs








Latest Developments in the Embedded Marketplace All I Want for Christmas

Microcontrollers Ease the Design of Solar Micro Inverters

Making Machine Control Implementation Accessible to Product Developers by David Stonier-Gibson, CEO, SPLat Controls


Newest Embedded Technology Used by Industry Leaders

Graphics Processing Fuels Growth in Embedded Computing by Barbara Schmitz, MEN Mikro Elektronik



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Overcoming the Limitations of Vision Systems in Manufacturing by Alex Liang, Adlink Technology

Overcoming the Limitations of Vision Systems in Manufacturing RTC Magazine NOVEMBER 2014 | 3


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Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2, Scotts Valley, CA 95066 Phone: (831) 335-1509 Published by The RTC Group Copyright 2014, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

U.S. Postal Service Statement of Ownership, Management and Circulation Required by 39 USC 3685. 1)Title of Publication: RTC magazine. 2) Publication Number 1092-1524. 3) Filing Date 10/01/2011 4)Frequency of issue is monthly. 5)Number of issues published annually: 12. 6)Annual subscription price: n/a. 7)Complete Mailing Address of Known Offices of Publication: The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County. 8)Complete Mailing Address of Headquarters of General Office of Publisher: The RTC Group 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, California. 9) Publisher: John Reardon, The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, CA 92673. Editor: Tom Williams,905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, California. Managing Editor: Sandra Sillion. The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, CA. 10) John Reardon, Zoltan Hunor. The RTC Group; 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, California. 11)Known Bondholders Holding 1 Percent or More of Total Amount of Bonds, Mortgages, or Other Securities: None. 12)Tax Status: The purpose, function, and nonprofit status of this organization and the exempt status for federal income tax purposes has not changed during the preceding 12 months. 13)Publication Title: RTC magazine. 14)Issue date for Circulation data: 9/1/14 RTC magazine. 15a)Extent and Nature of Circulation: average number of copies each issue during preceding 12 months (Net press run): 17167. Number copies of single issue published nearest to filing date: 16,000 b)1. Paid/requested outside-county mail subscriptions stated on form 3541. (Include advertiser¹s proof and exchange copies)/Average number copies each issue during preceding 12 months:16473, number copies of single issue published nearest to filing date: 15145 b) 2. Paid in-county subscriptions (include advertiser¹s proof and exchange copies)/average number copies each issue during preceding 12 months/number copies of single issue published nearest to filing date: n/a. b)3. Sales through dealers and carriers, street vendors, counter sales and other non-USPS paid distribution/average number copies each issue during preceding 12 months: n/a, number copies of single issue published nearest to filing date: n/a. b)4. Other classes mailed through the USPS/ average number copies each issue during preceding 12 months: 675, number copies of single issue published nearest to filing date: n/a. c)Total paid and/or requested circulation [sum of 15b. (1), (2), (3) and (4) average number copies each issue during preceding 12 months: 16473, number copies of single issue published nearest to filing date: 15145. d1) Free distribution outside of the mail (carriers or other means)/ average number copies each issue during preceding 12 months: n/a, number copies of single issue published nearest to filing date:n/a. e) Total free distribution (sum of 15d. and 15e.)/ average number copies each issue during preceding 12 months: 675, number copies of single issue published nearest to filing date: 834. f) Total distribution (sum of 15c and 15e)/ average number copies each issue during preceding 12 months:17,148 number copies of single issue published nearest to filing date: 15,979. g) Copies not distributed/ average number copies each issue during preceding 12 months: 20, number copies of single issue published nearest to filing date: 20. h) Total (sum of 15f and g)/ average number copies each issue during preceding 12 months: 17,168 number copies of single issue published nearest to filing date: 16,000. i) Percent paid and/or requested circulation (15c divided by 15f times 100)/ average number copies each issue during preceding 12 months: 96.1%, number copies of single issue published nearest to filing date: 94.8% 16. Publication of statement of ownership. Publication will be printed in the November issue of this publication. 17)Signature and title of the editor, publisher, business manager or owner: James Pirie (Managing Editor)10/01/2014. I certify that all information furnished on this form is true and complete. I understand that anyone who furnishes false or misleading information on this form or who omits material or information requested on the form may be subjected to criminal sanctions(including fines and imprisonment)and/or civil sanctions (including multiple damages and civil penalties). James Pirie Managing Editor

Intelligent Networking

Peet to Peer Tranfers

Reflective memory multicast RTC Magazine NOVEMBER 2014 | 5


“Dot-Org” Boards—A Symptom of Advancement and a Source of New Designs by Tom Williams, Editor-In-Chief

Recently I had the opportunity to have a prolonged discussion about open source software and whether it made sense to download and use an open source operating system as the foundation for commercial products. My opinion was emphatically that it did not. To create a commercial product with a unique value added, it is not practical to download an OS, configure it with needed components from other sources, test it, document it and be prepared to support it for customers. That is especially so when the customers are buying your product for its perceived value added, which is not the value of the underlying operating system. Somewhat less well known is the world of open source hardware. This is a world of very low-cost processor boards with a complement of interfaces, peripherals, schematics and tools. Such boards are mostly supported by groups of enthusiasts and serious developers. The boards have names like Anduino, Gizmo, BeagleBoard, Minnowboard and Raspberry Pi. They include modern, powerful CPUs and MCUs and in some versions come complete with development kits. Many of them are openly available from their own organizations as well as well-known distributors and even from It has long been possible for hobbyists to purchase PC motherboards and tinker away at building their own PCs. With this new generation of boards, they now have low-cost access to modules that can be used for embedded systems as well. And in many cases, they also have access to a community of tinkerers and developers through 6 | RTC Magazine NOVEMBER 2014

web-based associations where they can share ideas, designs, software and even finished projects. They can find and acquire such things as compatible displays. That is why I have given these things the nickname “dot-org boards.” One might think that with Christmas coming such boards and kits are just being recommended for the geeky kid in the family (well, it’s worth considering). However, it is worth noting that many of these boards come with complete schematics and bills of material. It is even possible to download the Gerber files that can then be modified and used to manufacture the board supplied in the kit or to modify that design and produce a custom board. Some kits come with expansion boards that plug into the main board and allow the user to wire wrap prototype designs. These could then be easily added to the CAD file to produce the desired design. Even if such efforts with the particular processor supplied do not result in a finished product, imagine the advantages of such a kit for a design team on a short budget. An individual engineer convinced of a concept that he or she wants to use to convince the boss could conceivably develop it at home and then triumphantly bring the design into work. A small team could be charged with putting together a prototype for proof of concept. The possibilities are endless. We now have that same concept coming from the other end. There are embedded software tool vendors who have seen that it is necessary to go beyond simply supporting families of processors with their tools, which

they certainly do. A number of them are also now supplying development kits that include a set of tools such as an RTOS, file system, graphics tools, a TCP/IP stack and a set of peripheral drivers for a specific OEM board module. Again, that module has a popular processor and a set of the more commonly used peripherals. The point is to help the developer get started with a design even though it may or may not use all of the peripherals on the board and maybe not the specific ones supplied. However, with a board and a set of targeted tools he or she can get a big amount of work done battling the time-to-market monster. Then the design can be refined once there is confidence in its basic nature. There is also a cultural aspect to all this. With their ease of use and especially with their price, kits like these are getting into the hands of kids, who are already more computer savvy than any of us dare imagine. Schools are starting to take advantage of them and science fairs are showing the results. What was once considered the realm of advanced engineers and scientists is now becoming commonplace for bright kids, hobbyists and tinkerers much like the ham radio technology of the past. What that also means, of course, is that what we now consider “cutting edge” has simply moved on with the design of SoCs and other deeply integrated silicon. It is unlikely that Amazon will ever be selling a fab facility, but we can certainly expect the current phenomenon to produce some amazing results down the road.


Robust Security Risk Assessment Framework for Medical Devices

The Medical Device Privacy Consortium’s Product Security Working Group has developed a robust framework for medical device manufactures and developers to assess the security risks associated with the use of medical devices. The framework is included and described in a white paper recently published by the Consortium. The framework addresses two problems facing the medical device industry when assessing security risks associated with the use of medical devices. First, there is a shortage of guidance on assessing impact to the confidentiality, integrity and availability of information in the context of medical devices. And second, there is a need for accurately and universally assessing likelihood of harm due to minimal experiential data specific to medical devices. In addition, the framework is designed to be easily adoptable and familiar to the medical device industry, and to apply to all medical devices throughout the product lifecycle. “Our goal is to provide industry with a common methodology to assess security risks associated with medical devices specifically. The framework is intended to yield a more grounded and actionable assessment of security risk by addressing certain problems facing most manufacturers, including assessing impact to information confidentiality, integrity, and availability, and determining probability,” said Michael McNeil, Global Product Security & Services Officer at Philips Healthcare and chair of the Consortium’s product security working group. Members of the Consortium include Abbott Laboratories, Boston Scientific, GE Healthcare, Medtronic, Philips Healthcare, Siemens Healthcare and St. Jude Medical. 8 | RTC Magazine NOVEMBER 2014

VITA Members Complete First VPX System Management Interoperability Workshop The VITA trade association has announced completion of a successful first VPX System Management Interoperability Workshop (VSM-IW) to test compliance of relevant VPX products to the VITA 46.11 System Management for VPX standard. In a VSM-IW, VITA member companies who build VPX chassis and modules that comply with VITA 46.11 come together to systematically test the interoperability of their chassis and module combinations. VITA member Mercury Systems hosted this first VSM-IW in Burlington, MA. Other participants included Elma Electronic, Extreme Engineering Solutions and Pigeon Point Systems. The VITA 46.11 specification was approved by its Working Group in November 2013 as a Draft Standard for Trial Use (DSTU), along with an explicit plan to organize a first VSM-IW as part of the effort to achieve full ANSI/VITA ratification. As preparation for the workshop, the VITA 46.11 Working Group developed a set of test plans for key functional areas of the standard and then used those plans to guide the testing. The test plans used in the VSM-IW highlighted where the DSTU can be clarified and improved to enhance interoperability for products built to the standard. VITA 46.11 was intentionally modeled on the hardware management layer of AdvancedTCA (ATCA), a PICMG-developed open modular platform that is in its second decade of broad worldwide use in telecommunications and other applications. PICMG authorized VITA to leverage the hardware management portion of the ATCA specification as well as test plans used in dozens of similar interoperability workshops for ATCA and related platforms since 2002. The VITA 46.11 specification adapts the ATCA management architecture and test plans to the special needs of critical embedded systems. The two main layers of VITA 46.11 are: 1) Chassis Manager, which manages and represents a chassis to upper level management 2) I ntelligent Platform Management Controller (IPMC) integrated into each VPX module and representing that module to the Chassis Manager. The standard defines two tiers of functionality for each layer to enable implementation flexibility. This VSM-IW tested the interoperability of two independent Chassis Manager implementations and four IPMC implementations. The testing included a 16-slot OpenVPX chassis filled with modules from multiple vendors, including both tiers of IPMC functionality.

Elecsys Announces M2M Communications Agreement With AT&T Elecsys, a provider of industrial machine to machine (M2M) communication technology solutions, data acquisition systems, and custom electronic equipment for critical industrial applications, has announced that it entered into a Machine to Machine (M2M) Wireless Communications Agreement with AT&T. The agreement enables Elecsys to provide industrial M2M communications devices equipped with its new embedded 4G data modem on the digital cellular networks operated by AT&T and its partners around the globe. The agreement provides Elecsys with direct data access to cellular networks in over 160 countries around the world, including Canada, Mexico, Saudi Arabia, the United Arab Emirates, Oman, Brazil, and South Africa. The Elecsys Director Z4 industrial data communications gateway, used in many industries such as oil and gas pipelines, and the Elecsys RFM-100 remote monitoring system, deployed to monitor railroad wayside equipment, have already been certified for use on the AT&T network. Elecsys plans to certify all of its current M2M products for deployment on the AT&T network over the coming months.


New AXIe Specification for Low-Cost Instrumentation and Switching The AXIe Consortium announced a new specification, AXIe-0, suitable for low-cost instrumentation and switching. Titled “Low Cost Instrument and Switch Architecture,” AXIe-0 retains the module size and board area of the current AXIe-1 Base Architecture, while delivering a cost effective platform for vendors and users not needing the full capability of AXIe-1. Von Campbell, Chairman of the AXIe Consortium and R&D Manager at Keysight Technologies, said, “The AXIe-0 specification is part of the ongoing efforts of the Consortium to broaden the use of AXIe. This new low cost instrument and switch architecture enhances cost effectiveness and improves ease of implementation for vendors wanting to take advantage AXIe’s space, power, and form factor for products that don’t require the high speed data infrastructure. These products include electronic switching, loads, frequency converters, and a wide set of custom functionality designed by system integrators.” Of particular note is the upward compatibility model of AXIe-0 to AXIe-1. All AXIe-0 modules can be mixed and matched with AXIe-1 modules in an AXIe-1 chassis. Essentially, AXIe-0 is a subset of the AXIe-1 specification. It uses LAN for communication to each module, and all modules appear as LXI instruments to system software. Non-ASCII communication and use of the AXIe trigger bus enables high-speed switching and triggering, either with other AXIe-0 products, or with AXIe-1 modules in a combined system. Creative choosing of functionality has allowed significant backplane, power, and management cost savings. Key applications enabled by AXIe-0 include large switching systems, RF Interface Units for aerospace and defense, and custom modules developed by system integrators and end users. With AXIe offering the same slot width and large board area as VXI, AXIe-0 is an ideal transition platform for VXI depot test applications, or any instrumentation requiring the large module size. AXIe-0 retains the same scalability of AXIe-1, ranging from small horizontal 2-slot chassis to large 14-slot systems. A preliminary AXIe-0 specification may be found on the AXIe Consortium website. AXIe is an instrumentation standard based on AdvancedTCA (ATCA) with extensions for instrumentation and test. The mission of the AXIe Consortium is to provide an open standard that creates a robust ecosystem of components, products, and systems for general purpose instrumentation and semiconductor test. AXIe leverages existing standards from PXI, LXI and IVI.

QuickLogic Partners with Peel to Embed its SmartIR Technology into Sensor Hub Solutions QuickLogic has announced that it will embed SmartIR technology from smart home control leader Peel into its sensor hub solutions. The partnership will enable smartphones, tablets and wearable devices using QuickLogic’s ArcticLink 3 S2 platform to function as smart remote controls. In addition to delivering the benefits of a remote control, Peel’s technology lets users customize the programming guide to their local TV provider’s channel lineup on their mobile device and track the shows and movies they watch to determine their preferences. Using their viewing habits as a guide, Peel’s integrated app can recommend additional content that users might like. OEMs using QuickLogic’s ArcticLink 3 S2 sensor hub platform can deliver these features without the need to add an additional chip. QuickLogic will be integrating Peel’s SmartIR technology into its pre-verified ArcticLink 3 S2 sensor hub catalog CSSP solution. With this solution, mobile device OEMs who want to provide smart remote functionality get a complete, pre-verified single-chip solution with all necessary drivers and software. The single-chip approach speeds development time while reducing bill of material (BOM) costs and total device power consumption.

Microchip Partners with LDRA for Functional Safety LDRA has become a partner and trusted adviser to Microchip Technology Inc., enabling customers to meet functional-safety requirements. Microchip, a provider of microcontroller, mixed-signal, analog, and Flash-IP solutions, recommends LDRA tools for applications that must comply with functional-safety standards, including ISO 26262 for road vehicles, IEC 61508 for industrial safety systems, and EN 50128 for rail transportation systems. The partnership offers seamless integration of the LDRA tool suite with Microchip’s award-winning MPLAB X Integrated Development Environment and MPLAB XC compilers. The LDRA tools focus on compliance while leveraging the MPLAB tools for comprehensive support of Microchip’s line of more than 1000 8-bit, 16-bit and 32-bit microcontrollers and DSCs. Microchip’s customers now have easy access, directly from the Microchip store, to the LDRA tools that enable coding standards compliance. For instance, LDRArules with an integration plug-in for the MPLAB X IDE (part #SW500320) is available now on Other software quality tools for dynamic coverage analysis, as well as unit/integration testing, are available directly from LDRA. In its role as trusted advisor, LDRA has delivered a series of educational seminars and training for Microchip’s field application engineering team. These seminars cover compliant application-development processes and identify the steps developers must take to enforce programming guidelines, measure code coverage and complexity, perform unit test, and verify a software application. Because the LDRA tool suite is fully integrated with Microchip’s MPLAB development software, customers can easily learn how to apply coding standards and automated software verification on their Microchip devices in order to achieve safety-critical compliance. RTC Magazine NOVEMBER 2014 | 9


All I Want for Christmas by Colin McCrackin

Fully decked out from head to toe. No, it’s not Fashion Week. Call it what you want – wearable tech, smart garments, e-textiles, whatever - it’s more than just a trip to the mall for the holiday shopping season. It is yet another “$20 billion by 2020” market. Or is it merely the same market research outfit that brings the same report from industry to industry? If the shoe fits, wear it. Once again, it looks like Apple will get credit for reviving a product category in which others floundered for many years. At the very least, they will take the high road in the smart wristwatch category and merely “watch” all the others carve out slices of the low price fitness pie. From bar brawls over Google goggles all the way to textiles sending text messages, it’s clear that our society has a one-way ticket to somewhere. How does the wearable tech industry intersect with embedded technology? It appears that the mature Micro Electro Mechanical Systems (MEMS) and Micro Systems Technology (MST) industry is poised to get pulled into this space in a big way. And MEMS / MST already did meet its $ billion market growth projections. Just imagine the ways to weave microsensors, accelerometers, actuators, transducers, gyroscopes, microphones, energy harvesting components, GPS receivers, hygrometers, and temperature sensors into fabrics. In this case, “fabrics” are not high-speed serial or optical backplanes or network topologies, but the shirts on our backs.

10 | RTC Magazine NOVEMBER 2014

What do we do with the sensor data collected? This is where our friend the embedded hyper-coder comes in. She or he cranks out 10,000 lines of code that runs on a die the size of a pin head with embedded SRAM and Flash. Enjoy watching the flex circuits bulge while pumping iron in the gym, with the security of knowing you are forever tethered to the cloud. Your doctor and loved ones monitor your EGC, heart rate, respiratory and glucose vitals remotely with their smart phone apps. Now that’s “connected”. And personal, without being too personal. Transmitters draw gobs of power. But where very low data rates are involved, amplifiers can operate at a very low duty cycle, off most of the time until needed. In fact, why not operate the embedded processor this way too? Leave just enough running to detect a wake event, then power on the system briefly until the processing and networking tasks complete. Wait, this sounds like what a PC does. That’s where the resemblance ends, as a microcontroller is much better suited to meet the size, weight, power, cost and timing budgets. Ever try jogging with a computer or tablet? Distributed and purpose-built systems are the only way forward. Wearable tech is no place for Big Data, Big OS, or Big BIOS. Leave that for the cloud and your desktop. Let’s use uA / MHz (microamps per megahertz) as our unit of measure for these embedded systems.

Security will play an important role with wearables, as with IoT edge nodes. Anything connected to the internet is, well, … yes, you guessed it, vulnerable to hackers. A lot is at stake when we’re talking about circuits strapped to our bodies. Some measure of protection is realized where the IP network ends and gives way to local low-speed interconnects on the other side of the local controller. The smart textiles and wearable tech industry is heading toward us like a freight train. And maybe it’s a good thing. Some of us could stand to lose a few pounds, and fascination with new fitness gadgets just might be what gets us off the couch this winter. Don’t believe it? We’ll see what’s under your tree this year.

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Figure 1 A sample boot flow illustration

Intel Firmware Support Package for the Internet of Things There are a number of unique firmware requirements for embedded systems and IoT that do not require the familiar BIOS but rather domain- and application-specific needs. Specific firmware support addresses these unique needs in the embedded and IoT space. by Jiming Sun, Intel

12 | RTC Magazine NOVEMBER 2014

Figure 2 Interfacing the Intel FSP

When the Intel Firmware Support Package (Intel FSP) was first introduced in October 2012 at Intel Intelligent Systems Summit event held in Taiwan, the immediate response was, “Not again, Intel’s embedded organization seems to come out with a new firmware initiative every two years”. At that time, the Intel Bootloader Development Kit (Intel BLDK) was still in distribution. “Will Intel FSP stay as a long term initiative?” “Will Intel change direction again in two years after we implement the solution based on it?” These were a couple of typical questions asked in the next two years when Intel FSP was presented in technical conferences and customer meetings, including many RTECC events. Since the BIOS has been so successful in the PC industry in the last three decades, people have the perception that they need to have a BIOS to work with Intel microprocessors. Sometimes this was what Intel wanted to persuade them to do as well because the Unified Extensible Firmware Interface (UEFI) firmware stack is well tested and there is a strong ecosystem to support it. However, the question embedded customers frequently ask is: “Can I use a different firmware stack for my unique design if BIOS does not meet my needs?” This is the question we want to address here.

Unique Firmware Requirements for Embedded Systems It is always fascinating to see what embedded system developers do and design. It turns out that that many embedded systems are relatively closed systems with dedicated functions, and they are highly customized for their business purposes. That means there are some unique firmware requirements that you don’t typically see in a PC firmware: • PC firmware typically deals with open systems with open bus and device standards. However, embedded systems and

IoT typically have closed or proprietary solutions in them. • PC firmware is ready to deal with devices coming and going any time; embedded systems and IoT typically have limited expansion and fixed configurations. • PC firmware constantly deals with a changing environment to dynamically adjust system power and performance levels, but some embedded systems need to be deterministic and predictable. Therefore changing speed or execution path is not allowed. • PC firmware deals with a lot of corner cases because it needs to anticipate many permutations of devices, OS, applications, and user behaviors. However, typical embedded systems or IoT have pre-defined usage cases. • PC firmware components are mostly designed to be reused, but most embedded systems and IoT firmware are highly customized to optimize for certain design goals. These are just a few examples of the requirement differences between embedded and PC firmware; obviously not all embedded systems have the same requirements. The main point here is: the one-size-fits-all model does not usually work for embedded developers. Every developer needs to analyze and pick a firmware solution that is the best to match his or her needs. The options might be: Real-Time OS, Open Source firmware stacks (including Open Source EDK, coreboot, U-boot, etc.), and even proprietary solutions. The other aspect of embedded system design is the domain knowledge and domain-specific features accumulated in the firmware stack over the years. These domain knowledge-based features are frequently distinctly different from application to application and from market to market. A company that has been in a vertical market segment for a while most likely has accumulated valuable experience and intellectual properties. They don’t want to re-do or port these over to a different firmware stack if they can avoid it. Therefore, allowing them to protect

RTC Magazine NOVEMBER 2014 | 13


Figure 3 Intel FSP Configuration

their investment in firmware is a must for vendors who are trying to help them to adopt a new silicon architecture.

Intel Firmware Support Package Now, Intel has offered the industry a solution to allow existing firmware investment to be preserved. The solution is called the Intel Firmware Support Package or Intel FSP. The idea of Intel FSP is to provide the developers an encapsulated bundle of features that deal solely with silicon initialization which only Intel knows how to do effectively. In the past, when a developer received a new set of Intel chips, they had to figure out how to program the chips by reading technical documents, comparing the sample code, porting the firmware, and even asking for help from the BIOS vendors or software vendors to help them implement the silicon initialization part of the firmware. Obviously, this does not mean that, with Intel FSP, the developers do not have to read documents anymore, but for any standard designs where the developers only care about getting chips functional quickly so that they can start developing value-added software features, Intel FSP can dramatically cut down the time required to learn how to program a new set of chips. Intel FSP includes all the silicon initialization code that provides basic functionality. For example, after the execution of Intel FSP code, the memory will be fully functional and the firmware stack owned by the developer can use the memory to run value-added features and to discover the topology of system buses and devices. There should be no need to refer to confidential programming documents that the developer may or may not have access to.

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What Does Intel FSP Do? As described before, Intel FSP carries out CPU initialization, memory initialization, and companion chip initialization. Also, it will grab microcode patches and apply them after matching CPUID with the silicon on the circuit board. The microcode patches can be updated separately so that Intel FSP can work with the latest CPU you have on your board even though Intel FSP was released earlier. Beyond Intel’s silicon initialization, it is up to the firmware stack to implement the rest of the platform firmware code; for example, platform initialization, power management, secure boot, device discovery, boot device selection, and OS loading. Intel FSP is not a stand-alone boot firmware; it needs to be integrated into a firmware stack of choice. Some developers might be bothered by the fact that Intel FSP does not include all the features as the reference BIOS does, but this is only one of the ways that Intel designs to support developers’ needs. If a developer wants to see all the reference code from Intel, the reference BIOS option is still offered. Intel FSP is the vehicle to support the developers who have an existing firmware stack, or decide to use a different firmware solution than BIOS. Intel FSP is not a replacement for BIOS; it is designed to provide a building block for people to easily overcome the first step of initialization. As shown in Figure 1, the typical boot flow involves the following boot steps: 1. The host firmware stack switches to 32-bit protected mode after reset. 2. The host firmware stack discovers Intel FSP (details will be documented in the porting guide). 3. The host firmware stack jumps to TempRamInit API.

Figure 4 Contents of Intel FSP Kit

4. Intel FSP loads microcode patches, and turns on cache as temporary memory; it could be something other than cache in future CPUs. 5. Intel FSP returns control back to the firmware stack. 6. The host firmware stack carries out pre-memory initialization (such as security check, turn on LED backlight, spin up hard drives, etc.) 7. The host firmware stack calls FspInit API. 8. Intel FSP carries out memory initialization, CPU initialization, and chipset initialization. 9. At this point, memory is fully available, and the root level bus bridge is fully initialized for further bus enumeration and device discovery. 10. The host firmware stack can choose to initialize the rest of the platform and then boot to an OS. 11. After PCI bus enumeration and before booting an OS, the host firmware stack can call back to Intel FSP via NotifyPhase API to lock certain registers to protect system configuration from being tempered by the OS or applications. The Intel FSP box in the middle, even though looks big, is actually pretty small (about 100KB to 250KB depending upon which memory technology is used), and it uses about 100 milliseconds to 300 milliseconds to complete the execution also depending upon the memory configuration. When the developer has a memory-down (soldered down) and fixed memory configuration, the time spent in Intel FSP can further be shortened by 50 or 60 milliseconds after saving the memory configuration in a non-volatile storage or Flash ROM. As shown in Figure 2, there are 3 interface APIs for the host firmware to jump to or call when integrating with Intel FSP. The first two APIs were described in the previous boot flow section,

the last API is a unique API, which allows the host firmware to call back to Intel FSP to lock down important registers and do some final clean-up before giving control to an OS. The output of Intel FSP is a data structure in the format of Hand-Off-Block (HOB) defined in the openly available UEFI Specification. For example, the memory parameters discovered and trained by Intel FSP will be made available via HOB so that the host firmware can pick them up from here, save them, and use them for other parts of platform initialization. Part of Intel FSP is a data region that contains all the configuration settings (Figure 3).This part of the configuration region can be modified statically with a binary configuration tool (BCT), or dynamically by the host firmware stack. The BCT is available for download at the same web site as Intel FSP (http:// configurable features, such as: ECC versus non-ECC, SPD ROM I2C address, ME size, Fast-Boot mode, are presented in a GUI based BCT, in both Windows and Linux versions. A command line version is also available upon request. Using Intel Atom Processor E3800 (formally known as Bay Trail) as an example, once you download the self-extracting kit from Intel’s web site, the kit will expand to a file structure as in Figure 4 and there are: an integration guide, several header files and sample code, a Boot Setting File (BSF), microcode patches, and optionally a graphics component, such as VGA BIOS. The integration guide provides the step-by-step instructions about how to integrate Intel FSP into the host firmware stack; the BSF is the file that contains all the configurable features, and the header files can be used by the host firmware to leverage the existing data structure provided by Intel FSP. The BCT can be used to manipulate the data inside BSF and it also allows the

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Figure 5 FSP integration example

developer to rebase Intel FSP to another location in the ROM if the default location needs to be changed.

An Example in Integration The Intel FSP is agnostic about which host firmware stack it is being integrated into, but Intel has been using coreboot as an example to demonstrate the steps. The open source firmware community, coreboot, was created by Ron Minnich in 1999, using the LinuxBIOS name; it was renamed coreboot by Stefan Reinauer in 2008. The source code is mostly in C language compiled and built with the gcc tool chain. A unique feature of coreboot is its module payload concept, which allows you to integrate a payload based on a specific OS or application. For example, Google’s Chromebook has a “Depthcharge” payload specifically designed to load ChromeOS. The pre-requisite of building coreboot is to set up a Linux or Cygwin-type of Linux environment under Windows. At the command line of Linux or Cygwin, you have the following steps to take care of the build environment (Figure 5): (1) Clone the coreboot git repository, by running the command: > git clone It might require you to config proxy if you run this command behind a firewall. (2) Once the coreboot source code tree is duplicated on your work space for coreboot, you need to build the tool chain by running the following commands: > cd coreboot > make crossgcc (3) It will take a while for the tool chain to be downloaded and built on your machine. (4) Once the tool chain and the source code are available, you need to download Intel FSP that you are interested in building from Intel’s web site.

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(5) In parallel to the “coreboot” directory that was created in step (1), you need to create a new directory, and name it “intel”. (6) Then, you need to move the files from Intel FSP kit to the “intel” directory tree that you have just created: The example in Figure 5 could be different from project to project, and the box on the right hand side can be customized to your own firmware stack, whether or not it is an RTOS or your proprietary source code. (7) Once all the Intel files are in place, all you have to do is to go back to the “coreboot” directory, and run: > make menuconfig (8) This will show the GUI based coreboot configuration menu for the build environment. (9) After you carefully change all the components inside the menuconfig configuration, you can exit it and save it to the .config file inside the directory. (10) Now, you can try to run “make”, and a coreboot.rom will show up in the “build” directory under coreboot. This example may be shown as a simple ten-step operation, but there are many places that could take a while to debug to resolve all the issues. Once this is done, you have a pretty consistent environment for all future projects.

Intel FSP Development Options snd Ecosystem In the last few years, Intel has been working with a few ecosystem partners to enable them to support developers’ needs in Intel FSP integration with different firmware stacks, such as: Wind River Systems, Sage Engineering, Waris Technology, Mobica, Ircona, Eltan, Insyde, ByoSoft, and AMI. If you have your own firmware engineering resource and would like to integrate Intel FSP into your firmware, you can

certainly do so by following the instructions provided in the Integration Guide of each Intel FSP release. Or, you can contact one of the ecosystem partners listed on Intel’s FSP distribution web site to help you with the integration effort. Some of these vendors also provide different levels of turn-key solutions, such as: board support package and web-based firmware build tools to help you build firmware for your particular system.

Intel Santa Clara, CA. (408) 765-8080

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Figure 1 Overview of Intel Xeon Processor E5-2600 v3 product family (Haswell). Courtesy Intel.

Keeping Pace with Intel’s High Performance Focus Intel’s methodical approach to process technology advancement and enhancement of its CPU microarchitecture give OEMs a predictable model through which they can plan product roadmaps that include performance increases and cost reductions. by Austin Hipes, Unicom Engineering

Last year, Intel introduced its next-generation microarchitecture codenamed Haswell. While the 1st rollout of this new microarchitecture focused on desktop and notebook platforms, Intel has just recently released new Haswell CPUs specifically designed to address the dual processor server market. This new roll-out of Haswell-based CPUs, the Intel Xeon E5-2600 V3 processors, illustrate Intel’s commitment to pushing performance standards higher and in turn, elevating the level at which its OEM partners must perform (Figure 1). Of course, marching in lock-step with Intel inevitably pays dividends for its partners as well as the customer base. In other words, it’s safe to assume with many new product launches that performance will increase handily, while the pricing of the upgraded architecture actually becomes more favorable for consumers, offering better performance at the same price point of their previous upgrades.

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Key to this formula is Intel’s unique “Tick-Tock” model, which delivers continued innovations in manufacturing process technology and processor microarchitecture in alternating “tick” and “tock” cycles. A “tick” cycle advances manufacturing process technologies to enable new capabilities such as higher performance and greater energy efficiency within a smaller, more capable version of the previous “tock” microarchitecture. The alternating “tock” cycle uses the previous “tick” cycle’s manufacturing process technologies to introduce new innovations in processor microarchitecture to improve energy efficiency and performance, as well as functionality and density of features (Figure 2). While this provides a roadmap for increased performance, it also helps Intel partners maintain some predictability in their own product cycles as they strive to embed technologies that match the performance standards of Intel’s latest product launch.

More Performance and Better Value

So, what does this mean for customers and the OEMs that support them? To better understand the translation, let’s consider the latest Intel microarchitecture release codenamed Haswell. The E5 2600 V3 processors featured as part of this release offer up to 18 physical cores per CPU. Along with more cores come faster memory and a faster interconnect between the CPUs in the system. This provides substantially more compute power, which will enable 40 GbE to be a practical reality in standard server platforms. This is a tremendous benefit when you consider growing trends like the “Internet of Things” that continually increases network throughput. With more traffic and more systems to process, 40GbE provides the ability to add more capability to systems – rather than adding more servers – to handle this increase in traffic. E5-2600 V3-based servers also bring a needed increase in performance in non-volatile storage technology with native support for DDR4 NVDIMMs. DDR4 NVDIMMs provide an industry-standard way of storing data in high-speed RAM without the fear of losing the data in the event of a power or node failure. In addition to DDR4 NVDIMM support in new E5-2600 V3-based dual processor server platforms, the performance of SSDs is increasing with the addition of NVMe support, giving multi-lane PCIe access directly to SSD storage. This results in lower latency and provides more bandwidth to a solid state drive than SATA or SAS would, in effect creating multiple tiers of high performance storage depending on what each unique system actually requires. Unlike some previous generations of PCIe SSD storage, NVMe SSDs are offered in hot-swap 2.5” hard drive form factors, as well as traditional PCIe add-in Cards (AICs). In this new 2.5” form factor, OEMs are able to take advantage of the newer, high performance SSD architecture while maintaining high levels of serviceability and drive density typically associated with SAS and SATA drive types. For customers seeking higher performance, the cost typically becomes more expensive per gigabyte. A logical approach to managing these costs is via a tiered storage model that keeps the most frequently accessed data on the most expensive tier, where fast access is possible, and moves less sensitive data to outer tiers which have reduced performance but lower costs per gigabyte. While the value component improves with each subsequent release, so does the process behind which those upgrades are delivered. By providing customers with the next generation of Intel processors and ensuring the corresponding system upgrades incorporate the latest microarchitecture, Intel delivers a balanced platform that prevents choke points from developing.

Creating New Levels of Efficiency

As new technologies emerge, along with the new microarchitecture, it helps design partners like Unicom Engineering plan the customers’ next transition for increased performance at near the same price, or substantially increased performance

Figure 2 Intel’s “tick-tock” model alternates between improvements to manufacturing/process technology and enhancements in processor microarchitecture. Courtesy Intel.

over their previous generation of products to keep their solution on the cutting edge .The corollary to this is if customers do not require increased performance, then it is possible to scale them into a lower tier system so there is the potential of paying less for the same performance level they are accustomed to. In looking at three rapidly-growing markets – storage, information security and communications – each require more capacity and all industries expect to acquire it at a decreasing cost per session, gigabyte of storage, and gigabit of throughput. Having more cores and bandwidth available in a system means each node can have more throughput as a whole, allowing a storage appliance, for example, to handle more directly connected bulk storage.. More CPU cores, more network bandwidth, and more memory bandwidth means customers can go to a higher sequence of either encryption or security transactions. Simply put, each system can perform more work or handle more bandwidth. Looking specifically at the communications infrastructure, Intel’s customers can do more transcoding, more encryption, and more ostentations with the new Haswell microarchitecture in a single box than they’ve ever done before. They can handle more subscribers, or the same number of subscribers at a higher workload than possible under the previous platform. For roughly the same power, price and physical footprint, they can handle more transactions.

Intel’s Commitment to Partners Runs Deep

Not only is there the ability to choose between greater power and performance, but also the ability to match price points to specific performance needs. For example, if a customer was seeking a brand new architecture, OEMs can recommend they hold off for the appropriate number of months until they can get Intel’s latest and greatest. Plus, as the actual product release draws near, Intel begins to feed more details into the marketplace: 18-24 months out, the projected timing of the new technology cut-in date is known; one year out, it becomes clearer; 6 months usually signals final feature decisions and 3 months until launch, everything is locked down. Thirty days prior to the product launch, all pre-production equipment has been evaluated. By maintaining this consistency in upgrade

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TECHNOLOGY CORE INTEL PUSHES THE ENVELOPE FOR PERFORMANCE being cognizant of the soon-to-be-changing microarchitecture. In many ways, customers and OEM partners move with Intel on a rapidly shifting paradigm. But Intel’s focus on maintaining productive relationships with all members of its deployment chain ensures its performance is always an asset and not a hindrance to supporting evolving requirements for increased productivity at a lower cost threshold. UNICOM Engineering Canton,MA. (781) 332-1000

Figure 3 Example of advanced motherboard with V3 CPU and the ability to readily accept the next generation V4. Courtesy Intel.

deployments, Intel OEM partners can better advise customers on what technology investments to make and when. Intel’s Embedded Alliance is another innovation the company provides to OEM partners in order to maximize the potential of new upgrades and releases. Affording its partners access to all of the products on the Intel Embedded roadmap lets OEMs know that Intel will guarantee availability of those products for at least seven years after product launch. Some customers want an architecture that will be stable for a long time, enabling OEMs to leverage their relationship with Intel to help customers choose products that are going to be available for multiple years. This drives stronger relationships across the distribution chain, and builds trust in Intel’s solutions, even as they continue to drive new levels of architecture performance. The Haswell E5-2600 V3 CPUs are built on the same Intel 22nm tri-gate transistor technology process as the previous release of E5-2600 V2 Ivy Bridge processors, so the manufacturing process maturity enables the release of new features on a stable platform. Intel makes this possible by adhering to a very predictable schedule that sees the release of the next CPU every 18-24 months. Additionally, the majority of the time that there is a new “Tick” process die shrink, the new model CPUs are able to be installed into the same physical platform as the “Tock” microarchitecture that proceeded them. The motherboards that take V3 CPUs are expected to take future generation “V4 CPUs” with little or no platform modifications required (Figure 3). So, now is the time for OEMs to begin working with customers to evaluate the new architecture that is going to handle two generations of CPUs and is going to be the primary platform architecture for the next 3.5 to 4 years. This is a busy time for OEMs as they simultaneously work with the existing Intel platforms while

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Microcontrollers Ease the Design of Solar Micro Inverters Designers frequently encounter challenges when creating solar micro inverters based on embedded processors. A number of these can be explained by way of insight into power stage design and control. by Manish Bhardwaj, Texas Instruments

Figure 1 PV grid-tied inverter for each panel has a DC-DC stage and a DC-AC stage.

Solar micro inverters are a quickly growing segment of the solar power industry that is transforming design processes as we know them. Instead of connecting all solar panels in an installation through a central inverter, solar micro inverter systems place smaller, or “micro,� inverters in line with each individual solar panel. There are many benefits of using solar micro inverters, including the improvement in efficiency under partial shading conditions, improved reliability and greater modularity. However, they can be extremely challenging to design. The controller must use complex algorithms to control the power stage, synchronize with the grid using software phase locked loop (SPLL) and track to the maximum power point of the panel. I t must also execute complex state machines, which increase the computational load on the embedded processor. The solar panel, or photovoltaic (PV) panel, as it is also commonly known, is a DC source with nonlinear voltage (V) versus current (I) characteristics. Some major challenges in PV inverter system design are extracting as much possible power from the 22 | RTC Magazine NOVEMBER 2014

panel by operating it at the maximum power point (MPP), as well as converting the power efficiently, allowing a clean current to be fed into the grid. A typical PV grid tied inverter consists of a string of PV panels tied together to a single inverter stage; these are called string inverters. Since these systems are not able to track to the MPP under partial shading conditions, attention and preparation are needed when installing these types of inverters. An emerging standard involves using inverters dedicated to each individual PV panel, also called micro inverters. These inverters ease the constraints on installation, and because dedicated MPP tracking (MPPT) can be performed through each panel, the system efficiency increases.

Solar Micro Inverter Hardware Design

Typical panels provide an output between 20 and 40V. This voltage must be boosted to approximately 320-400V and then inverted to feed current into the grid. Thus, a typical solar micro inverter has two stages: a DC-DC stage and a DC-AC stage, as shown in Figure 1. Several solutions are available to ease the design of solar power systems. One solution used specifically for those developing solar micro inverters is the C2000 Solar Micro Inverter Development Kit from Texas Instruments (TI). This kit integrates a

Figure 2 TI Solar Micro Inverter Development Kit power stage diagram

high gain clamped flyback stage, switching at 100 KHz to boost the voltage from the panel to a bus voltage for the inverter. The clamped flyback stage is used to reduce the voltage stresses on the MOSFETs. Due to the high gain in the power stage, small changes in the pulse width modulation (PWM) duty affect the output voltage by a large amount. Hence, the effective PWM resolution is reduced

whereas the ADC resolution remains unchanged

as the control for MPPT works on the input. The resolution of the PWM must be greater than the ADC to avoid limit cycle behavior, which is why TI’s C2000 Piccolo TMS320F28035 microcontroller (MCU) integrates a high-resolution PWM module. This module enables the effective number of bits for the PWM to be more than what the central processing unit (CPU) clock can provide for the given switching frequency. Additionally, the panel must be isolated from the grid to adhere to strict utility requirements. Transformer size is inversely related to the frequency of operation, and thus the trend is to use higher switching frequency for the power stage to achieve compact isolation of the panel from the grid. A schematic of the power stages on a solar micro inverter kit is provided in Figure 2. To avoid issues with ground current faults, a grid clamped RTC Magazine NOVEMBER 2014 | 23


Figure 3 Control diagram of a PV micro inverter

inverter stage is used to link to the grid. The switched current from the inverter is filtered using an output filter. The filter affects the quality of the current injected into the grid, and hence it must be designed carefully. The output filter can be designed using just an inductor (L), an inductor and capacitor (LC), or an inductor capacitor inductor (LCL) combination. LCL filter increases the complexity of the control because it has inherent resonance that can be detrimental to the stability of the inverter. However, it is often preferred as it can reduce the total size of the output filter. Resonance in the LCL filter can be damped using passive damping. This is done by adding power resistors in the filter structure. However, this results in reduced efficiency. Alternatively, active damping solutions involve using additional sensors such as those that measure capacitor current, which increases system cost. A complex pole zero pair in the compensator can be used to damp the resonance as well, though this increases the compensator complexity. This approach is preferred as it enables use of LCL filter without adding passive damping, which reduces efficiency and does not entail using additional sensors, and modern MCUs can easily manage the increased complexity of the controller.

Control and Software Design

Implementing the control loops of multiple power stages as well as implementing the algorithms necessary for grid connection and MPPT can consume substantial CPU bandwidth. TI’s C2000 MCU solar software library offers optimized functions (assembly optimized where applicable) for executing the key blocks used in the PV inverter control in fixed- and

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floating-point format. The blocks include an adjustable notch filter, which is used to eliminate any impacts of AC power ripple on the control variables. Compensators such as two-pole two-zero (2p2z) and three-pole three-zero (3p3z) compute the effort based on reference and feedback. SPLL locks in the grid phase, MPPT algorithm and power monitoring. In addition to the control loops, it’s also important to implement a state machine in order to start the inverter. Figure 3 shows a high-level control diagram of a solar micro inverter. The current compensator must be designed with a high bandwidth because the goal of the PV inverter is to feed a clean current into the grid. Figure 4 illustrates the current control Figure 4 Feedback linearization for inverter current control loop

Figure 5 Closed loop inverter current frequency response

diagram for a grid connected inverter. Due to grid voltage variations, the current compensator loop is subject to disturbances. A typical PI compensator is not able to track to the reference current with zero steady state error, so the effects of grid voltage disturbance must be taken into account. This is achieved by first assuming the current compensator bandwidth is significantly higher than the grid voltage frequency and linearizing the feedback. Therefore, the current compensator is thought of as generating the reference across the LCL filter and the actual duty cycle computed for the inverter voltage using the formula:

Where D is the inverter duty cycle, VDC the DC bus voltage, v8 is the grid voltage, i*g is the inverter current reference, ig is the inverter current reference, VLCL is the voltage across the LCL filter, Gp is the plant model of the LCL filter, Gc is the current compensator used and vi is the averaged inverter output voltage.

Figure 6 (a) Steady state inverter voltage and current (b) inverter stop, start and MPPT tracking

designers. To help mitigate common challenges, this article has presented various reasons for power stage selection, identified the need for high-resolution PWM for a high-gain DC-DC stage, offers a solution to complexity in grid current control using feedback linearization, and illustrates a comprehensive control scheme for solar micro inverters. Texas Instruments Dallas, TX. (972) 995-2011

Conclusion and results

Figure 5 shows the frequency response of the closed current loop, which includes the damping of the LCL filter and the feasibility of high bandwidth as a result of the feedback linearization. Figure 6(a) displays steady state voltage and current of the micro inverter and highlights good power factor achieved and total harmonic distortion (THD). Figure 6(b) shows the starting and stopping sequence of the inverter by displaying the inverter current and panel current as the micro inverter sequences through the state machine. Designing embedded solar inverters can pose a challenge to RTC Magazine NOVEMBER 2014 | 25


Making Machine Control Implementation Accessible to Product Developers In the real world where time is money and systems are becoming more complex, product developers are looking to the controller vendor for more out of the box functionality to help speed up time to market. This is all the more pressing now that control designs often include a graphical human-to-machine interface (HMI). by David Stonier-Gibson, CEO, SPLat Controls

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control system, controls are often implemented by product developers who have little relevant training or understanding of the deeper issues of control systems. Certainly, they are experts in the functionality of the product they are designing, but that expertise often does not extend to the electronic controls. This dilemma has only increased with the advent of ultra-cheap embedded computer boards with cutie-pie names, which place significant computing power, but not understanding, within grasp of developers working on products slated for quantity production. How then to make a controller system that can be incorporated into a machine design by application domain experts and maximize the chances of a successful outcome? One early effort in that direction, in the industrial automation domain, was the venerable PLC (see “In the Beginning was the PLC,” p.xx). The PLC was however never intended as an embedded controller for individual products made in quantity. Attempts to leverage PLC technology into true embedded controls applications often makes for a poor fit and expensive hardware over-design. It also does nothing to help the expert in the domain of the end product. Let’s explore then the various attributes and design strategies for an embedded controller system that enables a domain expert to leverage his expertise and implement a successful machine controller.

Guidelines along the Path Figure 1 A simple LED flashing program (top) is quite self-explanatory when the language is designed for real-world control. The program can be single stepped within the SPLat IDE and the results observed on the I/O simulation window (bottom)

Designing an effective and affordable control system for a “machine” whether it be an air conditioner, a spa bath, or a turnstile that is to be manufactured in quantity presents lots of challenges. For the controller to do a good job, it must react predictably to real-time events as well as do many things at once, without faltering. It usually needs state awareness, so it can respond in the context of past events. It must tolerate sensor faults and operator mistakes without becoming dangerous. And it must continue to operate 24/7/365 in the face of sometimes unanticipated events. Last, but not least, users need it to be easy and intuitive to operate, and that often means it needs a slick user interface. Bottom line: We expect the reliability, dependability, and usability of something even as humble as a dishwasher to exceed by far what we have regretfully come to accept as normal on our desktop computers. But despite all of these demands on and intricacies of a

In computer programming languages like C/C++, the very first step is the time-honored “Hello World” program. In controls programming, the equivalent involves a real-world outcome like a flashing LED or clicking relay. When you un-box your first sample controller, the time spent simply getting a flashing light or clicking relay should be a short but excellent investment. If you have to spend hours and hours of hands-off study before getting a gratifyingly observable — or audible — result, you may abandon the project before it is even started properly. So aim for that tiny initial step to familiarize yourself with the product and its tools. The clickety-clack relay is the first small step, and a significant one. But it is not the last. The golden rule of a successful control implementation is to keep on taking only small steps. This applies from everything as basic as ensuring the sensors are all wired to the correct inputs in the prototype before attempting to test a program using them, to building up your program step by step, module by module. This is where you will get the benefit of a control product whose support tools support interactive I/O testing and modular programming. Break your program down into small, manageable chunks along functional lines. For example, the modules in a coffee machine might be “boiler control”, “grinder”, “reservoir monitor”, “brew sequencer”, and “user interface”. Good choices in this system partitioning or “factoring” will put you in good stead later, so invest time in this critical planning stage.

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TECHNOLOGY IN SYSTEMS GRAPHICS FOR ADVANCED APPLICATIONS A lot goes on in a controller. Much, though, is just drudge housekeeping work such as initializing the processor hardware, which has nothing to do with the actual application. There is also a layer of activities that are fundamental to practically all controller applications, such as contact de-bounce, pulse counting and timing, and driving expansion modules and displays. Selecting a control system that quietly takes care of these under the hood, leaves you free to concentrate on the logic of the final control function, slashing possibly days of learning off your time to market. The 500-pound gorilla, though, is multitasking. Practically every embedded control application needs it. Yet in most controller products, and programming languages, multitasking requires a bolt-on Real Time Operating System (RTOS), separate from the controller hardware and the programming language. Picking the best RTOS is difficult, and really does require a high degree of expertise, so the consequences of a bad choice can be dire. The hazards that can arise in multitasking systems, such as resource locks and priority inversions, can be extremely subtle and often not strike until well after a product has been in service for some time. The result is costly recalls and possibly a complete program re-write — existential threats to start-ups and even small, established companies. Very few off the shelf controllers include an integral multitasking system, let alone one that is easy to learn, easy to use and hazard proof. What happens if you get stuck and need some assistance? Selecting a controller vendor with proven one-on-one application support and one who allows you access to knowledgeable and experienced engineers, can make all the difference to the success of your product development. Good support goes much deeper than just helping resolve sticking points. When the vendor’s engineers bring extensive experience to the table, they can often suggest innovative solutions. This could be a better way to structure the program, or a cheaper way of providing the needed sensors or actuators. It is very tempting to always want the highest possible speed, the largest possible memory, and the latest operating system. That’s what impresses colleagues and garners headlines. Yet the cost of those fashion items is often complexity and its attendant dangers. A spa bath doesn’t need a 1GHz processor on a 12-layer board and 1-microsecond response time. What it really needs is to work reliably and to be competitively priced. A product development has a much better chance of success if the emphasis is on a controller with robust I/O circuitry and a safe programming environment, rather than impressive headline specs. The SPLat Controls product is a range of board level embedded controllers and add-on boards that was designed from the ground up to be accessible to end-product developers. A novice can write useful programs for simple time- and event-triggered sequences after a couple of hours study using a simplified instruction set called FastTrack. Many SPLat customers have brought successful products to market using nothing more than FastTrack. One small step up the concept ladder from FastTrack is the tightly coupled cooperative multitasking system MultiTrack, which introduces

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just two more instructions. MultiTrack allows up to 64 concurrent tasks in a simple round-robin sequence that is comfortably free of the hazards of priorities and pre-emption.

FastTracking Results Many controllers, even today in the era of IoT and M2M, still perform nothing more than simple sequences, perhaps timed or governed by external events (inputs). SPLat’s FastTrack instruction subset was designed just for such cases, and is used in hundreds of machine designs around the world. FastTrack was inspired by a customer’s program that was simply waiting for an input, turning on some outputs in sequence for preset times, then going back to wait for a new input. FastTrack consists of just 14 instructions, and can be learned by a novice in a couple of hours. Here is the whole list:

On 5 Turn output 5 on Off Actuator Turn the output named “Actuator” off Pause 37567 Pause the program that many 10mS intervals GoTo LineName Jump elsewhere in the program WaitOn 5 Wait for input 5 to come on WaitOff 5 Wait for input 5 to turn off WaitOnT 5,3456 Wait for input 5 to come on, but with a timeout WaitOffT 5,3456 Wait for input 5 to turn off, but with a timeout GoIfT LineName Test if WaitOnT/WaitOffT timed out, jump accordingly GoIfF LineName Test if WaitOnT/WaitOffT timed out, jump accordingly GoIfInOn 5,LineName Conditional jump based on an input state GoIfInOff 5,LineName Conditional jump based on an input state SetMem 15,100 Set memory (RAM) location 15 to 100 DecMGoIfNZ 15,LineName Decrement memory, conditionally jump (loop counter)

The Pause and Wait instructions are blocking. But if used in a MultiTrack task, they block only the task they are part of. The SPLat system provides not only conventional programming tools, but also tools that reflect the real world and facilitate target machine interaction (Figure 1). A minimal flashing LED program, the “Hello World” of embedded controls, is easily understood when the language is transparent and the development environment provides a representation of the real world inputs and outputs. The I/O display also allows direct interaction with a connected controller board — click an output (LED) on the computer and the corresponding physical output will toggle on/off. Turn on a physical input

Figure 2 Finite State Machines (FSM) are an indispensable tool in the embedded controls programmer’s toolbox, yet even many professionals fail to exploit the technique due to the way it is presented by academia (Wikipedia article, top). SPLat’s FSM designer, Tabula (bottom) represents an FSM as a simple executable table. All the housekeeping code is generated quietly under the hood, leaving the programmer free to concentrate on the logic.

pin, and the on-screen representation (DIP switch) will follow. The SPLat system is built around a proprietary language, optimized for embedded control and accessibility. The language uses a virtual machine (VM), which trades speed for comfort. It allows a lot of functionality to be hidden under the hood, completely transparent to the application programmer. Inputs are de-bounced, floating point divide by zero doesn’t lead to a crash. Fatal runtime errors, including stuck loops, are intercepted with a predictable behaviour, and the multitasking “just is”. Many other under the hood services encompass serial communications — including Modbus — timers and event counting. Most embedded control systems need to somehow or other cope with states during machine operation — re-



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RTC Magazine NOVEMBER 2014 | 29

TECHNOLOGY IN SYSTEMS GRAPHICS FOR ADVANCED APPLICATIONS sponding to current events in the context of past history. The most successful paradigm for handling states is the Finite State Machine (FSM). An example of an FSM programming tool is Tabula (Figure 2), which allows an FSM to be expressed as a table that the programmer can interactively step through to verify its behavior. The maker of, say, a beer bottling and capping machine understands bottling machines, and will embody that understanding in the controls he designs. Conveying the subtleties of bottling beer to a programmer who knows nothing about bottling machines can be just as difficult as the other way around. Simon Ross, founder of start-up MicroBrewTech in New Zealand, had exposure to a mix of programming languages, including PLC ladder language, before he started developing his bottling machine for microbreweries (Figure 3). Thanks to the accessibility of the SPLat system, he was able to quickly develop a sophisticated

multi-tasking controller with color touchscreen using a beta prototype of SPLat’s HMI430 controller/touch screen combo product. Simon’s preference for the SPLat stems from his observation that, “With SPLat I can make a change and know it will work. In ladder, I have to go back down several layers to raw relays and timers, and it becomes that much harder to know for sure that it will immediately do what I want.” With proper support and a safe programming platform, it is possible to enable the real domain expert to take the lead on the control component. SPLat Controls Seaford, Victoria, Australia +61 3 9773 5082

In the Beginning was the PLC

Figure 3 Using a SPLat HMI430, a sophisticated controller with color touchscreen for this beer bottling machine was developed by the machine’s actual designer rather than by a programmer with no knowledge of beer bottling

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In the late 1960’s, minicomputers were becoming cheap enough to consider for “embedded” applications. $25,000 for a PDP8 with 4K of memory seemed like a steal. But the computers were unreliable – typical warranties were 3 months – and difficult to program. Then in 1968, Modicon in Massachusetts developed a product called a Programmable Logic Controller (PLC). This was effectively a minicomputer, but one built so robustly that it could survive the rigours of the factory floor. But the real genius was in the relay ladder logic language that was subsequently developed to program the PLC. That language closely reflects the relay ladder diagrams that the plant engineers of the time used to design their relay based control panels. That meant that a plant controls engineer could quickly learn how to program a PLC, leveraging all his existing knowledge and experience. The success of PLCs is largely attributable to its accessibility to those who needed to use them. PLC ladder programming is also one of the very few programming paradigms that are inherently multi-tasking. This happens because a ladder program is one big infinitely repeating loop — the most primitive possible multitasking structure. This structure however makes it difficult to program states and sequences in ladder logic, and is why ladder logic has over the years been supplemented with special function blocks like flip flops, counters and sequencers. PLC ladder programming is also the antithesis of structured, modular programming, and has difficulty expressing the sophisticated algorithms and calculations needed in modern embedded controls.

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RTC Magazine NOVEMBER 2014 | 31


Graphics Processing Fuels Growth in Embedded Computing The growing demand for graphic displays from embedded systems in both the consumer and industrial space presents challenges for system designers. Fortunately a convergence of innovative connectors and low-power, highly integrated processors is enabling developers to meet that demand with small, powerful and rugged solutions. by Barbara Schmitz, MEN Mikro Elektronik

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Figure 1 HD graphics are quickly pushing data throughput past previous levels as the expectation for high-quality visual content grows in many industries.

Regardless of the modern mobile application in question, whether it be fleet management of agricultural machines, passenger information in buses or video surveillance of trains, the trend is clear…system efficiency is a critical component to today’s embedded computing industry. One of the key drivers in this area is the growing amount of visual data that is being incorporated into embedded systems. And graphics mean higher throughput. Slide shows and short films are not sufficient anymore; nowadays, complex, real-time 3D graphics or videos in HD quality are needed, as well. (Figure 1) The proliferation of smart phones and portable tablets in the consumer market is shaping the expectations of how information is communicated in related industries as well. Visual access to data is increasingly becoming the anticipated ‘norm’, with many systems incorporating enhanced electronic elements, while integrating a display function to keep pace with growing user demands.

Grinding Through Graphics In this new age of advanced imagery, strong processors alone are not enough; visually-intensive applications require dedicated graphics hardware. Today, many chipsets have an integrated graphics controller and, therefore, are a good, cost-effective solution for small and medium sized system requirements. As a rule, in this architecture, the CPU and graphics controller share the main memory. But when high resolution displays—or even several screens with different, high-resolution visual content—are to be controlled at the same time, the bandwidth of this shared memory reduces both the performance of the CPU and of the graphics unit. So, independent graphics controllers with an integrated video memory become the preferred option. If you choose an external graphics controller, the data transfer rate of the connection between the chipset and the graphics controller is the critical performance factor. For this reason, connector technologies have led the development of many of the modern buses. First, the PCI bus, then the AGP bus, and finally PCI Express were all pushed on decisively by graphics cards and the need to efficiently, and effectively, connect the CPU with the graphics component. Data throughput is still at the forefront of connector technology, especially with the

RTC Magazine NOVEMBER 2014 | 33

TECHNOLOGY IN SYSTEMS GRAPHICS FOR ADVANCED APPLICATIONS specification. But, the connector offers advantages that are more far-reaching than just facilitating data throughput in CompactPCI Serial systems. In fact, it has proved very useful in a new line of box and panel PCs from MEN Micro. The uniqueness of this computing family, and why the connector is so beneficial, is that the external interfaces are separated from the main board. Depending on end user requirements, many different versions based on the system core are possible.

The Whole Package

Figure 2 Modern CompactPCI Serial connectors handle data rates as high as 12 Gb/s or more.

advent of high-speed serial connections quickly becoming the universally accepted data transfer route. Contrary to other serial interconnects—such as SATA and USB 3.0 for example—PCI Express is not limited to a single lane (a differential receive and transmit signal line pair) but can combine up to 16 of these lanes in parallel to control the graphics card (PCI Express x16). Using this data transfer structure, the migration from legacy, parallel CompactPCI platforms to modern CompactPCI Serial-based ones became easier.

Specification Specifics Graphics extensions are just one reason for the development of the CompactPCI Serial architecture. Being just as robust and modular as its predecessor CompactPCI, the enhanced specification offers even more performance and serial interfaces. CompactPCI Serial transfers the CompactPCI architecture to serial high-speed connections and offers better support for serial point-to-point structures. An outcropping of this new specification is an enhanced connector, specifically for CompactPCI Serial, that has, in turn, played an important role in the development of several embedded systems. (Figure 2) This connector scales to data rates of 12 Gbit/s and more without making space-wasting shields necessary. At the same time, it offers a much higher density than the conventional 2-mm signal connectors typically usually used for CompactPCI. To make sure that conventional CompactPCI interfaces like PCI Express, SATA and Base-T Ethernet are not supplied alternatively, but in parallel—meaning at the same time—connectors with high contact density on the system slot interfaces must be used. The new connector features enhanced thermal management properties and a rugged housing that combine to significantly increase reliability, enabling CompactPCI Serial to be considered for rugged applications not typically associated with its legacy

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These industry-ready box and panel PCs use a flexible, modular concept that allows different processor performance, interfaces and power supply types as well as display interfaces and system sizes to be developed easily and cost-effectively. The pre-integrated display computers are especially useful in meeting the changing demands of the many industries that are increasingly incorporating visual technologies. These systems are both modular, so that unique attributes can be tailored to specifically match an application, as well as rugged to withstand wide temperature ranges, severe shock and vibration and harsh environmental elements, such as dirt, dust and humidity. For example, the innovative modular concept that separates the external interfaces from the main PCB offers the highest flexibility. This way, the interfaces can be configured individually and adapted quickly to all requirements without additional development overhead. A major area where panel PCs are currently deployed is in mass transportation. They cover a diverse range of functions from infotainment systems, digital signage platforms, ticketing machines interfaces to driver desk applications and passenger area supervision on a vehicle or the platform itself. (Figure 3a & 3b) The design is always accomplished without fans, using conductive cooling to spread the dissipated heat to the outside of the housing—the box computer itself serves as the heat sink. Thanks to this conduction cooling, the device operates at temperatures from -40°C to +85°C. The electronic components are fully designed for demanding environments and even resist shock and vibration. Standard versions comply with the EN 50155, class Tx railway standard and are prepared for e-Mark certification.

Increasing Graphics Requirements Functioning as independent computers, box PCs take on a variety of tasks. As graphics data becomes increasingly more important in these tasks, the connector needs to keep pace with data transfer demands. Offering medium to high graphics performance, these computers are ideal as onboard computers or content servers. They can communicate with the control room via a wireless connection and send information to several displays. After all, DisplayPort supports HD resolutions of 1920x1080 pixels with a cable length of 45 feet.

(APU) chip is a critical component in the pre-integrated display PC concept. As its name suggests, the chip enables enhanced processing performance with exceptionally low power consumption. The APUs make computing performance scalable thanks to their compatibility. A resolution of 2560x1600 pixels on several monitors is possible, even on devices suitable for vehicles. By housing both the actual x86 CPU and a GPU from AMD’s Radeon range, AMD’s APU reduces the common 3-chip solution—consisting of a processor, Northbridge and Southbridge— to a small-footprint, 2-chip solution while providing the performance level of a dedicated graphics card. As an example, AMD’s Embedded G-Series 1-GHz dual-core G-T40R with integrated Radeon HD 6250 graphics processor has a maximum thermal design power (TDP) of just 5.5 watts. More powerful processing capabilities are easily incorporated into the modular panel PC design concept, with advanced embedded APUs, such as the G-T48N that combines a 1.4-GHz dual-core CPU and a Radeon HD 6310 dissipating up to 18 W, serving as the heart of a system. Thanks to advancing technologies that are keeping pace with growing data demands, users have many possibilities to effectively employ enhanced graphics performance without the frustration of data bottlenecks. And by using standard components that can be flexibly integrated together, innovative ideas and technologies make cost-effective and robust graphics solutions possible.

Figure 3a & 3b Consumer-facing industries, such as mass transportation, are some of the more heavily-invested forerunners to incorporate advanced graphics in computing technologies.

MEN Micro Blue Bell, PA. (215) 542-9575

Therefore, many applications in buses and trains are implemented using this type of box computer, making the connector’s ruggedness a critical feature to ensure reliable operation. A single computer controls, for example, two monitors in a bus via DisplayPort. They keep the passengers informed on the course of the route and display the stops and stop requests. In the meantime, informational videos are shown. Whenever the train is in the depot, the data is updated via WLAN. The connector is constantly moving data from the external graphics platform to the main processing hub within the system.

One Chip, Two Functions Wherever more performance is required, the scalable concept of these box PCs is of great benefit. AMD is way out in front of this concept at the moment. The Embedded G-Series combines each single- or multi-core CPU with a graphics processor of the Radeon range. This fusion concept of AMD’s Accelerated Processing Unit

RTC Magazine NOVEMBER 2014 | 35


Overcoming the Limitations of Vision Systems in Manufacturing Advances in low-power CPUs such as the Intel Atom E3840 series have made it possible to integrate high resolution, fast frame rate and image processing functions into compact smart cameras, greatly improving application and cost of vision systems for manufacturing operations. by Alex Liang, Adlink Technology

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Suppliers in the world of manufacturing are continuously in demand of increased solution flexibility and productivity, reduced cost, and the ability to support adjusted production schedules – in essence, ever-advancing automated processes throughout the production chain. One area of automation that is helping suppliers meet their goals is automatic inspection by machine vision, which is leading the charge toward the “smart factory.” The conceptual smart factory is a place where errors resulting from human manual operations are all but eliminated, quality consistency is improved, productivity is increased, production costs are reduced, and customer satisfaction is improved. With all of those boxes checked, operations in a smart factory clearly benefit from a distinct competitive advantage over the, well, less smart factory. Time and money are always key factors defining that competitive advantage, and it is important for system implementers to recommend a machine vision system that effectively minimizes cost and time-to-implementation. Multiple solution options— with their own advantages and disadvantages—currently exist for machine vision applications. Embedded vision systems provide great computing performance, but with a larger footprint, more complex deployment, and higher price tag. Industrial smart cameras offer compact size and fanless operation, but require a lower power, lower performance ARM-based CPU with limited memory—and therefore limited imaging capabilities. However, the convergence of high performance and low power consumption on new processors has opened up the possibility for an industrial smart camera solution that offers the best features from both larger embedded systems and smaller conventional smart cameras, providing a new alternative for machine vision applications. So, what are the essential requirements in the smart factory? And what types of vision systems could be selected to meet those requirements? High efficiency and throughput are critical for the higher productivity most industrial manufacturers pursue. However, there is a cost. In terms of conventional machine vision systems, high resolution and high frame rate are hard to achieve at the same time. Ruggedness and reliability are essential to the operating environments of industrial production, which are often challenging for automatic systems. For example, a food and beverage production facility is likely to present damp conditions with extreme temperatures, while machine tooling environments are often dusty with metal or other intrusive particulates present. If the vision system is to be installed adjacent to production equipment, a higher degree of imperviousness to such elements is needed. Integration with third party equipment: A production line usually involves a series of operations from manufacturing, machining, pick and place, and inspection to packaging. For instance, in computer numeric control (CNC) turning operations, a number of different machines are used with an external controller, such as conveyors or robotic arms to move components

Figure 1 A production line involves a series of operations that require communication between devices and systems in order to achieve a smooth, automated process.

from machine to machine and align them under the guidance of industrial cameras before cutting operations commence. After turning, the objects are conveyed to the next operation stand for flaw inspection. Finally, approved products are sent to packaging and undergo barcode reading for shipping. Integration of and communication among the different systems involved is a challenge for all smart factories (Figure 1). Faster development of software solutions and related compatibility issues are critical factors, dictating success or failure of the implementation. Shortening development time and reducing system development costs are distinct challenges.

Types of Vision Systems To be a configurable vision system means to integrate with an industrial PC and different functional modules, such as motion controllers, frame grabbers, data acquisition modules, and serial communication cards, providing the best flexibility and choice. The configurable vision system could integrate with the latest server-grade CPU and high-bandwidth PCI Express gen 3 technology to deliver the highest computing power, compared with embedded vision systems and smart cameras. Such a system is generally used to connect to high-resolution industrial cameras, such as Coaxpress and CameraLink, to carry larger-sized images, or other systems that require high throughputs. However, the disadvantage of the configurable vision system is that it requires installation in a rackmount industrial chassis, which gives it a larger footprint. Another type of vision system is the smart camera. Smart cameras are small, compact, all-in-one vision systems that incorporate lens, image sensors, system storage and processors into a single device, a combination of camera and computer. RTC Magazine NOVEMBER 2014 | 37

INDUSTRY WATCH MACHINE VISION IN MANUFACTURING frame rate. To achieve both, a more advanced CPU is needed with costs raised accordingly. Striking the delicate balance necessary among these factors and achieving optimal efficiency with reasonable cost structure is an important issue faced by system developers on an ongoing basis. Intel’s introduction, in the fourth quarter of 2013, of the high compute performance, low power consumption Atom processor E3840 series has ushered in a new category of vision system that features small and compact all-in-one systems with full PC functionality, high resolution and high frame rate multitasking, flexible expandability, and easy deployment. The new generation x86 smart camera represents a combination of the advantages of the existing lower power, lower performance, smaller form factor ARM-based smart camera with the higher performance, larger footprint, costlier embedded vision system. The x86 smart camera offers a highly integrated, high performance, compact vision system based on Intel architecture—a new market trend.

Figure 2 Global shuttering is the more efficient manner in which pixels collect light, but this method cannot generally be supported by ARM-based industrial smart cameras.

And the generally easy-to-use applications are included, which means the user may not need to have programming skills. Conventional smart cameras are often single-purposed and dedicated to simpler image tasking, such as gauging, counting, alignment, or barcode scanning. Conventionally, smart cameras have made use of a low power ARM-based or single-core Intel Atom microprocessor with limited memory, in consideration of size and ruggedness. Due to their minimal expandability, realization of additional functions requires installation of more system units. A third type of vision system, which can strike a balance between the capabilities and requirements of the smart camera and the configurable vision system, is the embedded vision system. Embedded vision systems are comprised of an industrial PC connected to high-resolution industrial cameras. Embedded vision systems typically feature a high-performance processor running a standard PC operating system with multiple vision channels supported to deliver a full set of image processing functions. See Table 1 for a comparison. Embedded vision systems are, however, often more costly and complicated to deploy. An increased footprint compared with a smart camera solution is also a disadvantage in often space-constrained production floors. The potential need for more cables and for fans also affects system reliability. In addition, embedded systems tend to be less rugged and are not ideal for harsh environments, such as production areas with humidity and dust.

Is it possible to find a solution that has it all? In reality, vision applications are often a marriage of high resolution with lower frame rate, or lower resolution with higher

38 | RTC Magazine NOVEMBER 2014

Breaking the Boundaries of Smart camera and Embedded Vision Systems The x86 smart camera defines a new category of vision system that singularly realizes high performance, maximum integration, easy deployment, space efficiency and minimal total cost of ownership, well beyond what conventional systems can achieve. New generation x86 smart cameras run on quad-core Intel Atom E3845 processors with serious improvements on CPU and GPU performance while conserving power expenditure. The new processors provide the palm-sized x86 smart cameras with the combined advantages of both conventional smart cameras and embedded vision systems. The FPGA co-processor and the GPU engine’s built-in CPU help to offload tasks from the main CPU, releasing resources for

Figure 3 With versatile open architecture, programs written by developers can easily migrate to different devices, shortening software development time and reducing total cost of system expansion.

more advanced computing. Multitasking is thus viable, allowing the x86 smart camera, though small in form factor, to simultaneously manage gauging, counting, alignment and 2D barcode reading operations. We can see the improvement in a number of key factors. First, conventional smart cameras usually run on a single-core Atom processor or ARM-based processor with considerations for size, power and heat dissipation. However, these conventional smart cameras have limited computing power and are often used only in simple image applications dealing with individual tasking of gauging, counting, alignment, or barcode scanning. The new generation x86 smart camera equipped with the Intel Atom E3840 series has doubled performance over previous generation processors while retaining a power consumption under 10W, enabling multitasking in a fanless small system for the first time. Multitasking systems can reduce the number of installations, an economical advantage in terms of total cost of ownership (TCO). Image sensors are the eyes of the vision system so larger sensors can acquire more image information and deliver higher image quality. In the past, with conventional smart cameras focused on simple imaging tasks, the size of image sensors was not an issue. However, with the implementation of high-end and high-speed applications, image sensor size becomes critical for image quality. Higher performance enables the use of a global shutter. Rolling shutters and global shutters differ in the way their pixels collect light. Rolling shutters collect light in sequential rows, with each row starting and finishing collection slightly different from each other. Global shuttering pixels start and end light collection during exactly the same period of time (Figure 2). Conventional smart cameras, whose limited computing power is insufficient to process large amounts of image data, have tended to adopt rolling shutter function. Even so, the inability of rolling shutters to remove residual signals, such as blur/skew/ wobble/partial exposure effects, when dealing with fast-moving objects has excluded conventional smart cameras from use in high-speed industrial applications. Currently, however, with the improved CPU efficiency of new generation Intel Atom processors, small form factor smart cameras are able to support global shutter deployment. While image quality is critical for accurate automatic inspection and analysis, limits of optical conditions (light source or lens) frequently cause acquired images to exhibit inconsistent brightness, leading to misjudgment in analysis. If the vision system can automatically optimize acquired images before submission for analysis, accuracy of image analysis is significantly enhanced. In conventional vision systems, captured image data is processed by the CPU. When processor resources are insufficient, the amount of image data able to be processed is reduced. Thus, conventional smart cameras must frequently compromise either image resolution or frame rate. The use of an FPGA co-processor by new generation x86

Figure 4 As one example of a new generation x86 smart camera, Adlink’s NEON-1040 features 4MP 60fps global shutter sensor and the Intel Atom quad-core 1.9 GHz processor, offering minimal footprint and rugged IP67-rated construction.

smart cameras greatly improves image processing efficiency by offloading image matrix operations from the CPU to an FPGA (image pre-processing), freeing CPU resources to carry out more advanced algorithmic operations. The FPGA co-processor can carry out image pre-processing tasks such as look up table (LUT), region of interest (ROI) and shading correction, with these smaller vision systems accordingly realizing faster and more complex applications. The new generation Intel Atom E3840 processors adopt a GPU driver, which offloads media processing tasks from the CPU, tripling graphic processing performance over previous generation processors. With built-in Intel HD Graphics 4000 technology, the GPU can process video encoding, compression and transmission across multiple channels simultaneously. This performance improvement empowers small vision systems to record, store and analyze media data, resulting in a “smarter� factory. The new generation also presents advantages in terms of display, instruction length and system storage. Conventional smart cameras transmit data only via an Ethernet cable connected to the control center. If the vision system can also connect with HMI or a screen at the production line via VGA or Ethernet port and display image data simultaneously, operators can view inspection results and find problems earlier. As image analysis applications are required to manage large amounts of data, most mainstream software tools in this segment utilize 64-bit instructions. System storage capacity can determine whether the vision system is able to run a full PC operating system and third party APIs in addition to the amount of image samples the system

RTC Magazine NOVEMBER 2014 | 39

INDUSTRY WATCH MACHINE VISION IN MANUFACTURING isolated digital I/O, maximizing communication and integration with other devices on the production line. To develop a smart factory environment for modern mass production process, the implementation of automated inspection is crucial in guaranteeing manufacturing quality and productivity, a primary requirement in enhancement of corporate competiveness. Time and money are always key factors defining competiveness, and it is important for system implementers to choose a system that effectively minimizes cost and time-to-implementation. New generation x86 smart cameras define a new category of vision system that singularly realizes high-performance, maximum integration, easy deployment, space efficiency and minimal total cost of ownership, well beyond what conventional systems can achieve (Figure 4).

Table 1 Configurable vision systems, embedded vision systems, and smart cameras all offer benefits and pitfalls that will determine the best choice for a specific vision application.

must store for matching and comparison.

Total Cost of Ownership Total cost of ownership is not determined solely by the nominal price tag of the system, but rather a combination of factors, including space usage, peripheral support, system expandability and software development costs. The physical size of the vision system, including external cabling, should be considered as production space cost. External wiring and cabling, as well as extended peripherals such as PWM light source controllers, must also be taken into account. The number of channels the vision system provides defines its expandability. Conventional smart cameras, though cheaper in single unit price, present the need for more system units to accomplish necessary expansion, such that actual system costs are much higher. New generation x86 smart camera systems provide multiple channels and a GigE port that supports an additional slave camera, obviating the requirement to install additional system units, reducing average channel expansion costs. Another important factor is software development and versatility. As mentioned, a manufacturing facility comprises multiple operation stands, among which effective communication and integration determines actual factory efficiency. If existing software resources can easily migrate across systems, human resource and development costs in deployment are dramatically reduced. The new x86 smart camera provides compatibility with GeniCam and GenTL standards for image acquisition, as well as an intermediate platform with the same API to communicate with 3rd party software (Figure 3). New generation x86 smart camera systems can provide an I/O topology similar to those in embedded vision, including GigE, VGA, RS-232, USB ports and

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ADLINK Technology, San Jose, CA (408) 360-0200.



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Rugged VPX Carrier Cards for PMC or XMC Modules with High-Speed PCIe

Two new 3U VPX carrier cards provide a simple and cost-effective solution for interfacing a PMC or XMC module to a VPX computer system. The VPX4810 and VPX4812 carrier cards from Acromag route power and interface bus signals to a plug-in mezzanine module through the VPX card slot connector. An 8-lane PCIe bus Gen 2 interface enables rapid data throughput. By inserting PMC/XMC industrial I/O and configurable FPGA modules from Acromag or other vendors on the carrier, developers can now leverage hundreds of available function modules in a VPX platform. Conduction-cooled and REDI models offer an extended operating temperature range of -40 to 85°C. Designed and manufactured lead free in the USA these carriers are suitable for high-performance industrial, defense, scientific research, and telephony systems requiring high-speed I/O. The VPX4810 and VPX4812 support any standard IEEE-1386.1 module for great flexibility to address I/O signal processing tasks. Both the VPX4810 and VPX4812 carrier cards conform to VPX VITA 46.0, 46.4 and 46.9 specifications and optionally VITA 48 for Ruggedized Enhanced Design Implementation (REDI). Front and rear-panel I/O access can be accommodated; however, the front I/O option is only available on air-cooled models. Both models are compatible with a number of VITA 65 OpenVPX module/ slot profiles. The VPX4810 has 64 I/O lines (P14, VITA 46.9) are supported via the P2 VPX connector. The VPX4812 I/O is supported via the P16 XMC connector. Pricing starts at $1300 for an air-cooled version with a 0 to 70°C range. Acromag Wixom, MI. 248-624-1541

A high performance 3U PXI Express (PXIe) embedded controller is equipped with the quad-core fourth generation Intel Core i7-4700EQ processor and operates at up to 3.4 GHz (in single-core Turbo Boost Mode). With four links x4 or two links x16 and x8 PCI Express Gen 2 link capability, up to 8 GByte/s of total system throughput and up to 16 GB of DDR3L 1600 MHz RAM, the PXIe-3985 is suitable for applications requiring intensive data analysis or processing and high-speed data streaming, such as in wireless, radar, or RF testing environments. Based on PCI Express technology, the Adlink PXIe-3985 can offer four links x4 or two links x16 and x8 PXI Express link capability for interfacing with a PXI Express chassis backplane. When configured in this combination, with a high performance PXI Express chassis such as the Adlink 3U 18-slot PXES-2780 chassis, maximum system throughput of up to 8 GByte/s is enabled, providing an effective solution for high bandwidth applications requiring intensive data analysis or processing and data streaming. In addition, the PXIe-3985 features up to 16 GB of 1600 MHz DDR3L memory capacity, ideal for seamless execution in memory-intensive applications. The Adlink PXIe-3985 provides versatile I/O capability, including dual DisplayPort connectors with 4K 2K support, dual GbE ports, GPIB, four USB 2.0 ports, dual hi-speed USB 3.0 ports, and trigger I/O for advanced PXI trigger functions. Easy connection with external, standalone instruments or devices, and innovative designs—such as dual BIOS backup—reduce maintenance efforts, with fast and easy swapping of battery, storage device, and SODIMM modules to deliver high availability in testing systems. The PXIe-3985, supporting Windows 7 32/64-bit operating systems, provides optimal performance when installed in the Adlink 3U high capacity 18-slot PXES-2780 chassis or compact 9-slot PXES-2590 chassis. These combinations offer an ideal operating environment for a wide variety of testing and measurement applications. ADLINK Technology, San Jose, CA (408) 360-0200.

RTC Magazine NOVEMBER 2014 | 41


Company...........................................................................Page................................................................................Website Acces I/O Products, Inc.............................................................................. 17..................................................................................................... Acromag................................................................................................................. 21......................................................................................... congatec, Dolphin.....................................................................................................................5...................................................................................... High Assurance Systems..........................................................................43.................................................................................. Intelligent Systems Source...................................................................... 20................................................ MSC Embedded Inc........................................................................................4........................................................................... One Stop Systems..................................................................................... 29, Pentek, Inc............................................................................................................. 2.............................................................................................. Real-Time & Embedded Computing Conference................40, Trenton Systems................................................................................................ 7......................................................................... RTC Products Gallery....................................................................................33....................................................................................................................................... RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to The RTC Group, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.

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42 | RTC Magazine NOVEMBER 2014

Embedded and IoT Engineering is Hard – Are you Asking the Right Questions?

Building great embedded devices, including for the Internet of Things, is hard. What about security? Will your device meet performance, reliability, and cost requirements? Do you need an operating system, networking, a file system, a UI, or remote management?

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