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Energy Harvesting Powers Low-Energy Nodes Modular Systems Power Flexible Automation Moving Mobile Medical Devices to Android THE MAGAZINE OF RECORD FOR THE EMBEDDED COMPUTING INDUSTRY

AUDI CONNECT NVIDIA Brings High Performance to Embedded/Mobile


An RTC Group Publication

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VOL 15 / NO 8 / AUG 2014


2U Rackmount Computers

Support More PCIe x16 Cards



Trenton's TRC2005 2U rackmount computer now supports up to four, PCIe x16 plug-in option cards. This expanded support for COTS PCI Express x16 cards enhances high-end data gathering, video imaging and network communications capability in a compact rackmount enclosure. System features include:

The TVC2404 is Trenton's latest in a long-line of scalable video wall controllers. Built on the rugged yet compact TRC2005 base chassis, the TVC2404 is typically configured with a singleprocessor system host board and our recent BPC8219 PCI Express backplane. The hardware combination of the TVC2404 enables:

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The Magazine of Record for the Embedded Industry




NVIDIA’s Tegra K1: A Game-Changer for Rugged Embedded Computing Dustin Franklin, GE Intelligent Platforms


Parallel Processing Platform Opens Bridge to High Performance Embedded Systems Tom Williams


NVIDIA is in a cooperative development project of a vehicle vision system with Audi. Object detection and recognition learning is being carried out on a multi-GPU system running neural networks. The results can then be ported to a Tegra K1-based vision system that fits in a small enclosure in the vehicle. Research and development in this area is ongoing.



Practical Energy Harvesting Implementations for Sensor Nodes Using Low-Energy MCU and RF Devices Matt Saunders, Silicon Labs









The Advent of Wearable Devices: Chasing the White Rabbit Named SWaP


Wireless Energy Harvesting Opens Market for Devices on the Internet of Things – and PLM Helps it Grow Marlee Rosen, Rosen Associates

Latest Developments in the Embedded Marketplace


Type 10? Not Again!

Newest Embedded Technology Used by Industry Leaders

28 Wireless Energy Harvesting Opens Market for Devices on the Internet of Things – and PLM Helps it Grow


For Control Systems, Put the Focus on Innovation, Not Integration Brian Phillippi, National Instruments


Matching I/O and Processor Performance Removes Data Processing Bottlenecks Vincent Chuffart, Kontron



32 For Control Systems, Put the Focus on Innovation, Not Integration


Porting Class III Medical Software to Android Sri Kanajan, SRI Ventures, Shrirahng Khare, Persistent Systems, and Richard Jackson, Biolase

RTC Magazine AUGUST 2014 | 3


PUBLISHER President John Reardon, Vice President Aaron Foellmi,


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The Advent of Wearable Devices: Chasing the White Rabbit Named SWaP BY TOM WILLIAMS, EDITOR-IN-CHIEF

It seems that when the topic of conversation turns to wearable devices, there can be a mixed reaction ranging from fascination and speculation of the possibilities that could be opened up to some level of discomfort mixed with skepticism. Is there really a demand for all kinds of small devices buried in clothing, attached to the skin or worn in some way as jewelry? The emerging answer appears to be a resounding “yes.” While the biggest push for wearable devices is coming from the medical sector, there is also a wide variety of ideas and actual devices from other sectors as well. As it turns out, people have been using a wearable medical device for centuries—a device known as eyeglasses, which was first developed in 13th-century Italy. As we all know, thanks to highly integrated electronics, this device has undergone recent enhancements . . . Again historically, and this time in terms of electronic progress, the next most widely used and accepted wearable device has been the hearing aid. Beyond the days of the ear trumpet, there were early attempts at vacuum tube-based hearing aids with transistor-based models coming out in the mid-1950s. These usually took the form of a box with a knob worn around the neck and a set of ear buds. Since then things in the world of hearing aids have changed dramatically. Today’s digital hearing aids, which can sell from around $2,000 to $7,000, incorporate multiple microphones and preamps, codecs, digital signal processors, speaker amplifiers and battery and power management. Some even incorporate RF-based remotes to select different modes such as to facilitate hearing 6 | RTC Magazine AUGUST 2014

at a table in a crowded restaurant, for example. And wearing a box around the neck will no longer do. The device must be as invisible (read small) as possible, cause no discomfort, and require minimal attention to battery replacement. In fact, that is the list of requirements for just about any wearable device, which is why in many cases energy harvesting is also being intensely explored for powering them. That, in turn, further reduces the acceptable power consumption of wearables. In fact, it sends us into an ever deeper rabbit hole of increased functional demands, which means higher levels of integration within the same or even smaller size constraints, greater device complexity, and ever tighter power restrictions—a place where it really is necessary to believe two impossible things before breakfast. Such demands really place strains on the traditional idea of the ASIC, a chip totally fabricated for a specific application, because each enhanced feature requires a new spin of the entire chip. And as those chips get more complex, the cost and timeto-market of the respins become truly daunting. And that complexity is starting to involve more than just adding peripheral functions. We are seeing increasing examples of hybrid architectures in small devices—CPUs combined with graphics processors (GPUs) or with DSPs and often with semi-peripheral microcontrollers, all with a mix of different controller, peripheral and I/O. The hardware and functional complexity leads inevitably to increased software complexity with its accompanying need for increased memory, be it volatile or nonvolatile. That inevitably leads to

more power consumption, which calls for better and more efficient power production and power management. The Holy Grail in terms of wearable technology is to be able to rely completely on energy harvesting. While there have been major advances all around in solar technology, the small, flexible panel has not quite made the price breakthroughs that have happened with such things as rooftop solar panels. There is, however, progress being made for the non-reptilian user in terms of energy harvesting from body heat. Such a strategy will probably be very necessary for devices that may be implanted, such as alert devices for seizures and/or cardiac conditions and even fitness monitors. There is even development going on for an implantable device that releases daily doses of birth control hormone into the body and will last for 16 years. When a woman wants to conceive, she turns it off with a remote control and then back on again. There is also work going on with the technology used to meter ink in ink-jet printers for use in monitoring medical doses into the body via implants that would be left in place for years. In some cases, such sensors can use conditions to trigger communication with another battery powered worn device like a watch, which can then communicate with a smartphone to signal alarms and/or transmit data to a remote monitoring or treatment center for action. Other applications like fitness are already appearing in wrist bands, smartphones and shoes, so wearable devices are definitely here to stay. The challenge will be to keep up with consumer expectations while that elusive white rabbit remains just out of reach.


Mentor Graphics Expands Automotive Portfolio, Acquires XS Embedded Mentor Graphics has announced the acquisition of XS Embedded (XSe), a company with over ten years of direct experience in the automotive electronics design industry across twenty automotive programs that combine hardware and software expertise. XSe brings a pioneering approach to accelerate system design and verification by providing automotive-grade hardware and software. Mentor is now well positioned to address the cross-functional collaboration needs required to address the trends toward integration of Advanced Driver Assistance Systems (ADAS), Driver Information and Infotainment domains. Modern automotive systems push the technology envelope with feature-rich embedded systems that combine high-quality graphics, domain-specific audio, multimedia, mobile device integration and connectivity. The design challenges are tremendous with millions of lines of code per vehicle, cross-domain function consolidation, mixed safety criticality, security, and the use of heterogeneous multicore SoCs. These challenges are exacerbated by extraordinary cost pressures and a traditional development lifecycle for systems that is measured in years while automotive consumer expectations require the latest in technology to be ever present. XSe has pioneered a new approach that provides Tier 1 suppliers with reference platforms that approach A-sample quality. By taking advantage of this automotive-ready reference platform, Tier 1 suppliers can not only drastically reduce time to SOP, but also improve architectural optimization, the partitioning of software, and ultimately reduce design costs. XSe achieves this by partnering with key semiconductor vendors to supply truly automotive-grade hardware, such as XS AXSB based on the Texas Instruments Jacinto 6 platform, and integrating optimized IP including the XS OPTstack software, a flexible software stack designed to be quickly ported and optimized to underlying hardware.

Eurotech Sharing M2M Open Standard Framework with the Eclipse Community Eurotech has announced its role and contribution to Eclipse Kura, an open source incubator project aimed at providing an OSGi-based container for M2M applications running in service gateways. Deploying and configuring one device to act as a node in the Internet of Things is relatively easy. Doing the same for hundreds or thousands of devices, supporting several local applications, is not so easy. This is where the new Eclipse project Kura comes in. Kura offers a platform that can live at the boundary between the private device network and the local network, public Internet or cellular network, providing a manageable and intelligent gateway for that boundary, capable of running applications that can harvest locally gathered information and deliver it reliably to the cloud. Through the Kura project, Eurotech will provide a set of common services for Java developers building M2M applications, including I/O access, data services, network configuration and remote management. Developers working with Kura will find that, as it is within an Open Service Gateway initiative (OSGi) container, they will be working with a standard framework for handling events, packaging code and a range of standard services. An application in Kura is delivered as an OSGi module and is run within the container along with the other components of Kura. Using the Eclipse Paho MQTT library, Kura provides a store-and-forward repository service for those applications to take the information gathered from the locally attached devices or network-attached devices and sending that data onward to MQTT brokers and other Cloud services. Applications can be remotely deployed as OSGi bundles and their configuration imported (or exported) through a snapshot service. The same configuration service can be used to set up Kura’s other OSGi-compatible services—DHCP, DNS, firewall, routing and Wi-Fi—which can be used to manage the networking setup of a gateway and provision private LANs and WLANs. Other bundled services available include: position, a GPS location service to geolocate gateways; click, a time service to ensure good time synchronization; db, a database service for local storage using an embedded SQL database, as well as process and watchdog services to keep things running smoothly. To talk to network attached devices, applications can use Java’s own networking capabilities to plug into existing device infrastructure. By abstracting the hardware using OSGi services for Serial, USB and Bluetooth communications, Kura gives application developers portable access to a wide range of common devices, though they can still use Java’s own range of communications APIs when appropriate. An API for devices attached via GPIO, I2C, PWM or SPI will allow a system integrator to incorporate custom hardware as part of their gateway. The Kura package is completed with a Web front end that allows the developer or administrator to remotely log in and configure all the OSGi-compliant bundles, and which developers can utilize to provide a Web-facing aspect to their own application’s configuration needs.

Companies to Collaborate on IoT Modules Greenvity Communications and Brain & Iris Technologies (BITPL) of Pune, India, have announced that they have entered into a memorandum of understanding for joint development of Internet of Things (IoT) products, consisting of smart meters, lighting nodes, and wireless and powerline communications (PLC) modules. Through this joint development, Greenvity and BITPL expect to generate synergy through aggregating their respective strengths, which will allow them to capture a significant share of the global market for smart meters and communication modules. Greenvity’s innovative and patented hybrid communication technology

8 | RTC Magazine AUGUST 2014

integrates standards-based PLC and wireless technologies for robustness and extended range, enabling faster time-to-market and flexibility for OEMs and ODMs to customize and scale up or down the modules and the baseline software to fit specific applications. Their total turnkey IoT solutions include SoCs, modules, software and mobile apps that enable any home device or IoT device to be smart and controllable for energy-saving and home and building automation purposes. BITPL has developed various IoT applications in energy management, metering and powerline communication-based remote management of nodes. First prototypes of smart lighting nodes are expected to be ready by Q3 2014, followed by field trials. Integration of Greenvity’s technologies with the smart meters already developed by BITPL will make this product a formidable force in the emerging global smart meter market.

congatec Certifies Qseven Module for Intel Gateway Solutions for the IoT congatec has announced that the conga-QA3 Qseven module based on the Intel AtomT processor E3800 family is now certified for the Intel Gateway Solutions for the Internet of Things (IoT). The company has combined its embedded computer with the validated software package from Intel, Wind River and McAfee to provide new services based on the connection of devices with each other and the cloud. The bundle includes McAfee Embedded Control, which, among other things, includes dynamic whitelisting to prevent the execution of unapproved code while at the same time allowing policy-based updates. The combination of reliable hardware and a consistent software package, starting with the firmware and operating system, forms a “root of trust” for IoT applications. By bundling a baseboard that incorporates a Trusted Platform Module (TPM) chip, congatec helps ensure that applications can be operated with maximum data security. The 70 mm x 70 mm Qseven conga-QA3 module from congatec using processors from the Intel AtomT processor E3800 product family, bundled with the MB-Q7-2 baseboard from TQ Systems, together provide an ultra-compact hardware kit. Use of these Intel AtomT processors yields a very economical and extremely powerful embedded PC. The integrated Gen 7 Intel graphics technology sets new standards for graphics-intensive applications in the low-power segment. The compact baseboard design (measuring 100 mm x 100 mm x 23 mm), plus the numerous interfaces and functions, allows rapid and inexpensive implementation of powerful, yet passively cooled embedded systems such as Box PCs, as well as customized solutions.

Embedded Vision Growth Predicted Across Various Application Markets Shipments of embedded vision devices in the automotive, industrial automation, physical security and business intelligence markets are forecast to exceed 14 million units in 2018, up from almost four million units this year, according to research by IHS Technology. Utilizing a combination of embedded systems and computer vision, embedded vision enables devices to use video inputs to better understand their environment, applying logic and decision making to video signals. The maturity of embedded vision algorithms varies by application market. For instance, while embedded vision technology has been active for some time in markets like physical security and industrial automation, the consumer industry represents more of an emerging opportunity. However, despite the synergies in algorithm requirements across application markets, there are very few vendors that are active across multiple applications. In some markets, like automotive, the long sales cycles and high-qualifying requirements have limited new competition. In others, such as physical security, the fragmented equipment market means that algorithms need to be optimized for a large number of products, which can act as a barrier to new entrants. While the software and hardware vendors in embedded vision are unlikely to move into every application market overnight, developments in the automotive space, in particular, should help spur more accurate and reliable algorithms across the embedded vision industry. This trend, combined with increased awareness in the consumer market for augmented reality and gesture recognition, means that demand for embedded vision devices will grow rapidly in the decade ahead.

Altera and Lime Microsystems Team Up on Development of Wireless Networks Altera Corporation, and Lime Microsystems, a provider of field programmable RF transceivers, have entered into a strategic cooperation agreement focused on jointly developing and promoting programmable solutions for a diverse range of broadband wireless markets. The agreement will result in the development of optimized field programmable radio frequency (FPRF) transceivers, digital RF and baseband solutions that will enable system designers to reduce their overall costs, lower power, shorten timeto-market, and customize designs for key wireless infrastructure, enterprise, military, industrial, test and medical applications. As demand for mobile data traffic continues to increase, small cell wireless backhaul systems are projected to handle a quarter of mobile traffic by 2016, according to analyst firm Infonetics. This trend is reshaping mobile networks, and carriers are looking for ways to simplify complexity and costs of small cell deployment. Altera’s high-performance FPGAs, coupled with single-chip RF transceiver technology from Lime Microsystems supporting all mainstream global wireless communication standards, will simplify small cell deployment and enable the creation of lowcost mobile networks. Additionally, Myriad-RF, which was founded by Lime Microsystems and is a family of open source hardware projects for the prototyping and creation of fully configurable wireless platforms, also will give developers easy access to Altera/Lime optimized reference designs, boards, and software stacks and drivers to quickly, easily and affordably build next-generation wireless systems. The two companies will produce reference designs that can be further customized for specific applications and features. This will expand Altera’s FPGA customer base to include wireless applications beyond carrier grade base stations and remote radio units. These applications include enterprise wireless networks, small cell carrier grade infrastructure, military communication systems, software defined radio, and machine-to-machine (M2M) applications in the industrial, test and high-end consumer space.

RTC Magazine AUGUST 2014 | 9


Type 10? Not Again! BY COLIN MCCRACKIN

Our board-level standards organizations have really outdone themselves this time. The PICMG trade group wins the prize for the first to reach a double-digit pinout type for a standardized off-board interface. COM Express Type 10 wins by a landslide over a stackable architecture from the next closest purveyor of pinout proliferation. Incompatible signaling definitions on the same connector pins comes with a “plug-n-pray” user experience. Here is the part where Skype users and text messagers can drop in a “dull” (eye-rolling) or a “face palm” (head-shaking) emoticon. The Homer Simpson-inspired “D’oh” works too. Okay, there’s some smoke and mirrors here. Several numbers were skipped on the way to this great achievement. As engineers and developers, we like to leave room for “future expansion.” While Type 10 is the single connector migration path for Type 1, more or less, Type 6 is the two-connector quasi-compatible migration path for Type 2. The thinking is that in another few years when the chip buses change again, Type 6 can post-increment by 1 (“6++” for you application developers) and the same goes for single connector usage (“10++”). Let’s use the more generally abstracted variable form, “COM++.” While at first it appeared that Type 10 was too expensive and too tall (Z-height) compared to the latest crop of DIMM-PC card edge form factors that were poised to kill it, Intel’s new Bay Trail platform is giving Type 10 a big shot in the arm.

10 | RTC Magazine AUGUST 2014

This year, Bay Trail stacks up as a strong retort to AMD’s eKabini SoC launch for applications requiring modest or no graphics. Scalability from single core 1.46 GHz to quad core 2 GHz in the same package allows a Type 10 module to hit a broad part of the market. Half a megabyte to 2 Mbyte of L2 cache and fast DDR3L 1333 memory speed combine with blazing I/O bandwidth from four PCIe Gen 2 lanes to dual SATA II 3 Gbit/s to USB 3.0 to give OEMs a large performance boost over previous Atom and Celeron processors. Module manufacturers stuff 1 Gbyte to 4 Gbyte of RAM on Type 10 boards, and many of these models also cram in 4 Gbyte of affordable eMMC single-chip flash on board, which can hold most embedded operating systems. One Gigabit Ethernet interface is the norm, and the low 5-10 watt power dissipation allows a simple low-cost flat heat spreader plate to be the thermal solution. Some manufacturers provide more features via a board controller IC, such as dedicated I2C controller, hardware multi-stage watchdog timer, and non-volatile storage for anything from encryption keys to manufacturing data. In PICMG vernacular, it’s actually inadequate to refer only to a module’s pin assignment type. While the electrical characteristics are critical, so are the mechanicals. Type 10 modules are implemented in the newest “Mini” size: 84 x 55 mm. They come with mostly new mounting holes, so be sure to buy the COM.0 R2.1 spec before launch-

ing into a re-layout of carrier boards based upon Basic (125 x 95 mm) or Compact (95 x 95 mm) sizes. Although at this time there aren’t as many off-the-shelf Type 10-compatible carrier boards as for Type 6, more will come, especially after the launch of an award-winning carrier board the same tiny 84 x 55 mm Mini size with rich I/O and locking headers. The thin, light COM + carrier approach is poised to steal market share from the stackables community, where size, weight, power and now cost are important. As usual, system OEMs have more product choices due to this additional form factor fragmentation. Reducing system size and weight has its benefits, certainly. Why not just let the market decide what modules will win? Already, many of the highest volume embedded computer module manufacturers are shipping Bay Trail with commercial and I-Temp alike in both this +12V rectangular Mini shape and in the +5V square Qseven form factor. With rapidly growing production quantities of each shape, there won’t be a VHS – Betamax shakeout; rather both form factors will achieve their cost and profit targets and thrive. With Mini, the Million Module March may move massively into the market mainstream of modular manufacturing. Say that 20 times rapidly.

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NVIDIA’s Tegra K1: A Game-Changer for Rugged Embedded Computing

The migration of a powerful parallel GPU architecture along with a compatible software platform and computing model into a low-power ARM multicore SoC, promises to bring a range of capabilities into the mobile and embedded arena that have so far not been possible. BY DUSTIN FRANKLIN, GE INTELLIGENT PLATFORMS

FIGURE 1: Simple TK1 block diagram.

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FIGURE 2: The launch of Tegra K1 sees the possibility of a range of GPU-based solutions with substantially different capabilities—but with code compatibility enabling one development for multiple deployments.

Military and aerospace embedded computing customers are increasingly embracing GPU technology for applications—such as radar, sonar and ISR (intelligence, surveillance, reconnaissance)—that can readily benefit from the very high degree of parallelism offered by graphics processors. Such applications are widely known as GPGPU—general purpose computing on a graphics processing unit. Historically, as any PC gamer will confirm, this extensive compute capability has come with challenges in power consumption and heat dissipation. Increasingly, these are of concern to military and aerospace customers, who are looking to deploy highly capable embedded computing solutions on smaller, lighter weight platforms that do not have significant power at their disposal and that are problematic to cool. Size, weight and power (SWaP) have become, in many such environments, a more important decision criterion than, for example, performance/watt.

192 Cores, 327 GFLOPS: Less Than 10W of Power NVIDIA’s Tegra K1 (TK1) is the first ARM system-on-chip (SoC) to support an integrated Compute Unified Device Architecture (CUDA). With 192 Kepler GPU cores and four

ARM Cortex-A15 cores delivering a total of 327 GFLOPS of compute performance (Figure 1), TK1 has the capacity to process lots of data with CUDA while typically drawing less than 6W of power, including the SoC and DRAM. CUDA is a parallel computing platform and programming model developed by NVIDIA that gives program developers direct access to the virtual instruction set and memory of the parallel computational elements in CUDA GPUs, and allows them to be used for general purpose processing. To appreciate the enormity of what NVIDIA has achieved: a 6U VPX multiprocessor single board computer featuring earlier GPU technology consumes approximately 100 watts to deliver 645 GFLOPS of performance. In other words: twice as much compute horsepower, but with over ten times the power consumption. Such platforms, with their raw compute capability and flexibility, will continue to be at the heart of many leading-edge embedded computing deployments. There are, however, a growing number of applications being envisaged for the future that will significantly benefit from “only” half the processing performance if the power/cooling ratio can be reduced so substantially. The Tegra K1, then, brings game-changing performance to low-SWAP and small form factor (SFF) applications in the sub-10W domain, all the while supporting a developer-friendly Ubuntu Linux software environment delivering an experience more like that of a desktop rather than an embedded SoC. Tegra K1 is plug-and-play and can stream high-bandwidth peripherals, sensors and network interfaces via built-in USB 3.0 and PCIe Gen2 x4/x1 ports. TK1 is

RTC Magazine AUGUST 2014 | 13


FIGURE 3: Sensor processing pipeline implemented using Tegra K1 for autonomous navigation.

geared for sensor processing and offers additional hardware-accelerated functionality asynchronous to CUDA. This includes H.264 encoding and decoding engines, dual MIPI CSI-2 camera interfaces and image service processors (ISPs). There are many exciting embedded applications for TK1 that leverage its natural ability as a media processor and low-power platform for quickly integrating devices and sensors. As GPU acceleration is particularly well-suited for data-parallel tasks like imaging, signal processing, autonomy and machine learning, Tegra extends these capabilities into the sub-10W domain. Code portability is now maintained from NVIDIA’s high-end Tesla HPC accelerators and the GeForce and Quadro discrete GPUs, all the way down through the low-power K1 (Figure 2). A full build of CUDA toolkit 6 is available for TK1 that includes samples and math libraries such as Compute Unified Fast Fourier Transform (CUFFT), Compute Linear Unified Basic Linear Algebra Subprograms (CUBLAS) and Non Paged Pool (NPP) memory as well as NVIDIA’s NVCC compiler. Developers can compile CUDA code natively on TK1 or cross-compile from a Linux development machine. Availability of the CUDA libraries and development tools ensures seamless and effortless scalability between deploying CUDA applications on discrete GPUs and on Tegra. There’s also OpenCV4Tegra available as well as NVIDIA’s VisionWorks toolkit.

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Additionally, the Ubuntu 14.04 repository is rich in prebuilt packages for the ARM architecture, minimizing time spent tracking down and building dependencies. In many instances applications can be simply recompiled for ARM with little modification, as long as the source is available and doesn’t explicitly call out x86-specific instructions like SSE, AVX, or x86-ASM. NEON is ARM’s version of SIMD extensions for Cortex-A series CPUs. So what are the practical possible applications for Tegra K1? Let’s consider a couple of case studies that highlight TK1’s ability to easily integrate sensors and support high-bandwidth streaming.

Case Study #1: Robotics/Unmanned Vehicle Platform Embedded applications commonly require elements of video processing, digital signal processing (DSP), command and control and so on. In this example architecture with Tegra K1, CUDA is used to process imagery from high-definition GigEVision gigabit cameras and simultaneously perform world mapping and obstacle detection operations on a 180° light detection and ranging (LIDAR) scanning rangefinder, a remote sensing technology that measures distance by illuminating a target object with a laser and analyzing the reflected light (Figure 3). Additionally, devices such as GPS receivers, inertial measurement units (IMUs), motor controllers and other sensors are integrated to demonstrate using TK1 for autonomous navigation and motion control of a mobile platform such as a robot or unmanned vehicle. Teleoperation capability is provided by applying Tegra’s hardware-accelerated H.264 compression to the video

and streaming over Wi-Fi, 3G/4G, or satellite downlink to a remote groundstation or other networked platform. This architecture provides an example framework for perception modeling and unmanned autonomy using TK1 as the system’s central processor and sensor interface. It’s Tegra’s low power consumption and minimal heat dissipation that make it an attractive processor for confined environments such as robots or small unmanned vehicles, giving them a local processing capability that would previously have been unthinkable. The scanning LIDAR produces range samples every 0.5 degree over 180 degrees. These are grouped into clusters using mean shift and tracked when motion is detected. CUDA was used to process all range samples simultaneously and perform change detection versus the octree-partitioned 3D point cloud built from previous georeferenced LIDAR scans. This produced a list of static and moving obstacles refreshed in real time for collision detection and avoidance. A radar-like plan position indicator (PPI) is then rendered on the OpenGL side (Figure 4). This particular LIDAR was connected via RS-232 to a serial port; other LIDARs support Gigabit Ethernet as well. The open-source SICK Toolbox library, which compiles and runs out of the box on TK1, was used for connecting to the sensor. Having easy access to LIDAR sensors provides TK1 with sub-milli-

meter accurate readings to exploit with CUDA for real-time 3D environment mapping and parallel path planning. On the imaging side, Tegra K1 has a number of interfaces for streaming high-definition video, such as CSI-2, USB 3.0 and Gigabit Ethernet. Frame grabbers for other media like HD-SDI, CameraLink, LVDS and others can be integrated with TK1 via its PCIe Gen2 x4 port. For this case study, testing was carried out with multiple Gigabit Ethernet cameras from GigEVision-compliant vendors. These had resolutions ranging from 1920 x 1080 up to 2448 x 2048, and the testing found an individual ARM CPU core sufficient per Gigabit Ethernet port for handling network protocols and packetization using the sockets API. Using the cudaMallocManaged() feature new to CUDA 6, the video stream is depacketized by the CPU into a buffer shared with the GPU, requiring zero copies to get the video “into GPU memory.” In the case of TK1, it’s physically all the same memory. Using freely available libraries like OpenCV, NVIDIA NPP and VisionWorks, users have the ability to run a myriad of CUDA-accelerated video filters on-the-go including optical flow, SLAM, stereo disparity, robust feature extraction and matching, mosaicking, and multiple moving target indicator (MMTI). Trainable pedestrian and vehicle detectors can run in real time on TK1 using available Histogram of Oriented Gradients (HoG) implementations. There are many existing

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RTC Magazine AUGUST 2014 | 15


FIGURE 4: LIDAR-driven PPI display visualizes static and moving obstacles in the platform’s environment.

CUDA codes available that previously ran on discrete GPUs and are now able to be deployed on Tegra. In addition to LIDAR devices and cameras, TK1 supports navigational sensors such as GPS and IMU for improved autonomy. These are commonly available as USB or serial devices and can easily be integrated with TK1. One quick way to make a GPS-enabled application is to use libgps/ gpsd, which provides a common software interface and GPS datagram for a wide class of National Marine Electronics Association (NMEA)-compliant devices. Meanwhile IMU sensors are integrated to provide accelerometer, gyro and magnetometer readings at refresh rates of up to 100 Hz or more. TK1 fuses the rapid IMU and GPS data using high-quality Kalman filtering to deliver real-time interpolated platform positions in 3-space, and then uses these interpolations to further refine visual odometry from optical flow. While less standardized than the NMEA-abiding GPS units, IMU devices commonly ship with vendor-supplied C/C++ code intended to link with libusb, a standard user space driver interface for accessing USB devices on Linux. Such users pace drivers leveraging libusb require little effort to migrate from x86 to ARM and enable developers to quickly integrate various devices with TK1. Some examples include MOSFET

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or PWM motor controllers for driving servos and actuators, voltage and current sensors for monitoring battery life, gas/ atmospheric sensors, ADCs /DACs and more, depending on the application at hand. Also, Tegra K1 features six GPIO ports for driving discrete signals, which are useful for connecting switches, buttons, relays and LEDs. This case study accounts for common sensory and computing aspects typically found in robotics, machine vision, remote sensing and so on. TK1 provides a developer-friendly environment that takes the legwork out of integration and makes deploying embedded CUDA applications easy while delivering superior performance.

Case Study #2 : Tiled Tegra Some applications may require multiple Tegras working in tandem to meet their requirements. Clusters of Tegra K1 SoCs can be tiled and interconnected with PCIe or Ethernet. The size, weight and power advantages gained from implementing such a tiled architecture are substantial and extend the applicability of TK1 into the datacenter and high-performance computing (HPC). Densely distributed topologies with 4, 6, 8 or more K1 SoCs tiled per board are possible and provide scalability beneficial for embedded applications and HPC alike. Consider the example based on an existing embedded system, employing six Tegra K1s (Figure 5). The six TK1s are interconnected via PCIe gen2 x4 and a 32-lane PCIe switch with nontransparent (NT) bridging and DMA offload engines. This, along with a lightweight userspace RDMA library, provides low-overhead inter-processor


Tegra K1

Tegra K1



Tegra K1




Tegra K1


Switch NT




PCIe expansion


Tegra K1

Tegra K1


FIGURE 5: SWaP-optimized tiled architecture, six Tegra K1’s interconnected with nontransparent PCIe switching and RDMA.

communication between the TK1s. Meanwhile sensor interfaces are provided by a Gigabit Ethernet NIC/PHY connected to each Tegra’s PCIe gen2 x1 port. There’s also a spare PCIe x8 expansion brought out from the PCIe switch for up to 4 Gbyte/s of off-board connectivity to user-determined I/O interfaces. A tiled solution like this is capable of nearly 2 TFLOPS of compute performance while drawing less than 50W, and represents a large increase in the efficiency of low-power clustered SoCs over architectures that utilize higher-power discrete components. The decrease in power enables the placement and routing of all components on board, resulting in connectorless intercommunication with improved signal integrity and ruggedization. Useful for big data analytics, multi-channel video and signal processing, and machine learning, distributed architectures with TK1 offer substantial performance gains for those truly resource-intensive applications that require computational density while minimizing SWaP. The ground-breaking computational performance of Tegra K1, driven by NVIDIA’s low-power optimizations and the introduction of integrated CUDA, leads a new generation of embedded devices and platforms that leverage TK1’s SWaP density to deliver advanced features and capabilities. NVIDIA and GE have partnered to bring rugged SFF modules and systems powered by TK1 to the embedded space. Applications in robotics, medical and man-wearable devices, software-defined radio, security, surveillance and others are prime candidates for acceleration with Tegra K1. Beyond this, TK1’s ease-of-use promotes scalable, portable embedded systems with shortened development cycles, only furthered by the wealth of existing CUDA libraries and software that now run on Tegra. The powerful GPU-based multiprocessing platforms of today will continue to be favored in deployments in which the maximum possible pure processing capability is an absolute requirement. There can be little doubt, though, that Tegra K1 offers significant opportunity to bring powerful, rugged embedded computing to places and applications where it was previously impossible.

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Parallel Processing Platform Opens Bridge to High Performance Embedded Systems

The Compute Unified Device Architecture from NVIDIA has enabled supercomputing levels of graphics and numeric processing on desktop and rack-mount systems. Now it is moving to a new class of mobile processors and enabling huge new levels of performance. BY TOM WILLIAMS, EDITOR-IN-CHIEF

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Of all the vague expressions that have been bandied about lately, perhaps none is more unclear than the phrase “high-performance computing.” First of all, it is connected to time. The concept of a 2 GHz x86 would have been a fantastic dream 15 years ago. And, of course, that also makes it relative. “High performance” is higher than what is at any given time considered “normal performance.” That being said, it is nonetheless justifiable to characterize the idea of “high performance” by virtue of the tasks a system can perform. It definitely takes a higher class of performance to tackle a higher class of operations such as robotic vision compared to running a vending machine. Despite all this, we can definitely say that embedded computing is entering a phase of “high performance,” where it is gaining the ability to take on tasks that have never before been possible on a small, mobile embedded system. As with the trend in multicore processors, performance is gained not so much from clock speed as from parallelism—the development of processing units and supporting software that can perform compute-intensive operations on massively parallel platforms. One of the leaders of this charge is NVIDIA with its recently introduced Tegra K1 processor (Figure 1). NVIDIA is well known for its graphics processing as well as for its high-end CPU technology. In fact, 18,688 of its Tesla K20X GPUs paired with 18,688 AMD Opetron 16-core CPUs are incorporated in the Titan, the fastest supercomputer in the U.S., which was built by Cray for the Oak Ridge National Laboratory. Each Tesla K20X has 2,688 CUDA cores, the units of parallel architecture that are at the heart of NVIDIA’s technology. The Compute Unified Device Architecture (CUDA) is the platform that gives programmers writing in C and C++ access to the parallel processing aspects of the GPU. And it is CUDA that forms the bridge between the high-end NVIDIA processors and the Tegra K1. While NVIDIA processors are technically referred to as GPUs, CUDA also enables highly parallel numeric processing for addressing a vast array of applications. The architecture has undergone advances with such names as Tesla, Fermi and Kepler. The Tegra K1 has 192 Kepler CUDA cores. NVIDIA has actually developed two pin-compatible versions of the Tegra K1—a 32-bit and a 64-bit version, both based on the ARM instruction set. The 64-bit version appears to be scheduled for later release and is a dual Super Core CPU based on the ARMv8 architecture. The 32-bit version uses a 4-Plus-1 quad-core ARM Cortex A15 CPU first used in the Tegra 4. This arrangement enables power saving by using variable symmetric multiprocessing (vSMP) for performance-intensive tasks on the quad-core complex, and can also switch to the (plus-1) “battery saver” A15 core for lower-performance tasks. NVIDIA states that it has optimized the 4-Plus-1 architecture to use half the power for the same CPU performance as the earlier Tegra 4, and to deliver almost 40% more performance at the same power consumption. Unlike the previous Tegra processors—which were very popular in applications like tablets and are used in the Tesla S class electric automobile—the Tegra K1 is compatible with CUDA. That means that CUDA-based software, especially

Main Memory 1


Copy processing data


Copy the result

Instruct the processing

Memory for GPU GPU Execute parallel in each core


Processing flow on CUDA

FIGURE 2: The CUDA processing flow copies data from main to GPU memory and the CPU instructs the process to the GPU. The GPU executes parallel in each core then copies the result from GPU memory to main memory.

libraries, tools and many applications, can be moved to the K1. Again, 192 cores are not 2,688, so the performance is not comparable. But, the performance in the embedded space—delivering approximately 327 GFLOPS—definitely qualifies as “high.” In addition, other APIs supported by NVIDIA are available to the Tegra K1. These include OpenGL, originally developed by Silicon Graphics. It was designed to interact with graphics processing units (GPUs) and is widely used in CAD, scientific simulation and video games. In addition, there are APIs targeted at vision such as OpenCV and NVIDIA’s VisionWorks. Then, of course, there is CUDA. CUDA offers a general-purpose interface for programming on the GPU, but is not specific to graphics. It does require some extra effort on the part of the programmer to figure out which parts of his or her code are inherently parallelizable. Then a precompile macro is used to tell the compiler which parts to run on the GPU and which on the quad core CPU. The precompile constructs move the code to the GPU memory and copy the results back to main memory (Figure 2). The ability to do high-intensity parallel numeric processing as well as high-end graphics is important in a wide range of applications. For example, global climate simulation done on a full-blown supercomputer entails a huge amount of computing before the results

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FIGURE 3: The Jetson TK1 Development Kit will put powerful GPU development tools into the hands of anyone from engineers to hobbyists.

are ever displayed graphically. The same can be said for gaming where trajectories of flying robots, vehicles and debris must be computed before each step where they are rendered in their new positions on the screen.

Development Direction and Support NVIDIA, of course, has ideas about where the new Tegra K1 will be applied, and these include computer vision for robotics, surveillance and security, defense and image processing for portable medical devices. However, NVIDIA’s product manager for Jetson Tegra K1, Jesse Clayton, readily admits, “We think we know what Tegra K1 will be useful for, but we hope and expect to be surprised at what people will do with it.” Clayton also reports that as of the date of our interview, “We’ve blown out order predictions for the development kit.” And they haven’t even tried offering it via Amazon yet. To that end, NVIDIA has released its Jetson Tegra K1 development kit at a price of $192, which makes it easily available to everyone from the research scientist to the home hobbyist (Figure 3). The board features 2 Gbytes of memory plus 16 Gbytes of eMMC along with Gigabit

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Ethernet, USB 3.0, SATA, miniPCIe, RS-232 as well as a set of expansion ports for displays, GPIO and high-bandwidth camera. On the software side, the kit comes with the CUDA platform, OpenGL 4.4 and the NVIDIA VisonWorks toolkit. It also supports Linux for Tegra release 19 that comes with a Tegra Linux driver package, which includes a kernel image, boot loader, NVIDIA drivers and flashing utilities. Development is recommended on a host PC running Ubuntu Linux. While power consumption is a key issue for embedded and mobile development, Clayton notes that they have not yet done extensive experiments to see what the maximum power draw can be. However, they have had it in the range of 6 to 7 watts. For power management, there is a way to lock the clock at a certain level to experiment with optimizing power. There is also a clock governor in the Linux version that works with heuristics to determine when an increased work load may require cranking the clock up and where a drop in the work load would allow turning the clock down to conserve power. “But sometimes,” Clayton says, “the user will want to lock the clock at a certain level and can also do that.”

A TQMP2020 module with a Freescale QorIQ can save you design time and money In addition there is also the Jetson Pro kit, which is primarily oriented toward development of automotive systems such as in-vehicle infotainment, advanced driver assist systems (ADAS) and collision avoidance. The kit includes the Jetson main board with Tegra K1 processor, a breakout board with many connectivity options, a discrete CUDA-capable GPU, Wi-Fi, Bluetooth and GPS antennas, and touchscreen capability. The Jetson Pro kit also supports Linux and Android and is compliant with the in-vehicle open source development platform supported by the GENIVI Alliance. The Jetson Pro kit is available for approved developers, Tier 1 suppliers and automobile manufacturers. One of the advantages of the CUDA “bridge” that has already been demonstrated is in the cooperative development of a vehicle vision system with Audi. Object detection and recognition learning is being carried out on a multi-GPU system running neural networks. The results can then be ported to a Tegra K1-based vision system that fits in a small enclosure in the vehicle. Research and development in this area is ongoing. So we can definitely state that “high-performance computing” is entering the world of mobile and embedded systems—because it breaks the barriers for tasks that were previously not feasible. Stand by for that already high bar to be raised even higher in the future. NVIDIA Santa Clara, CA (408) 486-2000


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Practical Energy Harvesting Implementations for Sensor Nodes Using Low-Energy MCU and RF Devices The choice of RF and MCU solutions in today’s market is vast. But when time is taken up front to establish what is really required from the MCU and RF components in an embedded design powered by harvested energy sources, it becomes clear that one size does not fit all. BY MATT SAUNDERS, SILICON LABS

FIGURE 1: A typical energy harvesting sensor node.

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While energy harvesting is certainly not a new concept, recent advances in performance versus energy consumption for both RF and microcontroller (MCU) devices mean that building an energy harvesting application, such as a sensor node, is now much easier to do. In addition, the resulting application is much more capable than previously possible for the same harvested energy. As a result, there are an increasing number of applications where energy harvesting is becoming a viable solution for powering the sensor node, locally processing the acquired data, and transmitting it back to a collection point. Consider an embedded energy

harvesting system as shown in Figure 1. Some of these elements, for example the energy harvester itself, will be common to any energy harvesting design. Where will you obtain the required amount of harvested energy to power the sensor node? From a light, thermal, vibration or RF source? Table 1 summarizes the potential power to be harvested from these common sources. For this example we will assume we are using a solar harvester. In addition to the harvesting source, the application will also require some form of energy storage, quite likely a capacitor bank, or possibly a small rechargeable battery. The storage is required as the harvester will to har-

FIGURE 2: Cortex-M3 versus Cortex-M4 for 512-point FFT.

vest energy continuously, but the application itself will likely have activity spikes with a majority of time spent in sleep modes. Beyond these application elements, the developer’s challenge is then to select and design with components that will deliver the required results using the available energy. Here there are some key factors to consider. The chosen devices must operate with an extremely low standby current; they must use the lowest possible amount of power while active; and they must be able to switch between active and standby modes extremely

quickly. The more time a device takes to transition from a standby mode to an active mode, the more energy is wasted.

Adding an RF Link When considering the RF component of this design, a key element will be choosing a protocol that provides enough bandwidth to transmit the required data but with minimal overhead to reduce overall consumption as much as possible. ZigBee and Bluetooth are both good options for low-power and battery-powered appli-

FIGURE 3: Low-Power ADC strategies on EFM32 MCUs.

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Figure 4: Current consumption versus sample frequency. The numbers of the graph lines correspond to the methods shown in Figure 3.

cations, but a more lightweight wireless connectivity technology might be a better choice for energy harvesting. The requirements of an energy harvesting application fit nicely with a simple, proprietary sub-GHz solution. If we assume for this design that there is minimal data to be transferred because of local signal processing (more on this point later), then the RF component will spend a majority of its time in standby modes waking up only to transmit short bursts of preprocessed data. As such, two significant parameters to consider are the consumption in standby mode and the consumption in transmit mode. For these reasons, an energy-efficient sub-GHz transceiver, such as the Si4464 device from Silicon Labs, is a good candidate. The Si4464 offers a standby mode of just 50 nA, minimizing the drain on harvested energy resources when not transmitting or receiving, and it has a fast wake-up time of 450 ÂľSec to move from standby mode to being operational. This level of wireless energy efficiency enables the designer to minimize the consumption of the RF component in the application and focus on capturing and managing the data.

Choosing the Right MCU Moving on to the MCU, the sensor node will pro-

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vide localized data processing to reduce the overall volume of traffic transmitted by the RF network. An ideal candidate for such an implementation is an MCU built on the ARM Cortex-M4 core, which has a range of dedicated DSP functions enabling signal processing to be achieved in many fewer clock cycles than on a non-DSP-capable MCU. Figure 2 shows the time taken to perform a 512-point fast Fourier transform (FFT) on a Cortex-M3 core-based MCU, and the same routine performed on a Cortex-M4. The CPU clock speed is the same in both cases. As the figure shows, processing time on the Cortex-M4 is much less than on the Cortex-M3, resulting in better energy efficiency when using the DSP-based Cortex-M4. To underscore the benefits of using a more capable core with DSP functionality, consider the use of Silicon Labs’ EFM32 Wonder Gecko MCU in an energy harvesting application. However, the core alone is not the only factor in achieving the best energy efficiency. There are other areas to consider as well, such as the consumption required for signal acquisition (and the technique used as a result) and the interaction between MCU peripherals, enabling the MCU to remain in low power modes for longer periods of time.

FIGURE 5: LESENSE operational concept.

Energy-Efficient Signal Acquisition Considering the task of signal acquisition, optimizing for energy efficiency could be accomplished in a variety of ways. Assuming it is an analog signal to be acquired, it makes sense to look at using an analog-to-digital converter (ADC), or a special-purpose interface for signal acquisition. Starting with the ADC, there are several techniques that can be used to get the data into the MCU. Figure 3 shows this process graphically. The first option, and most conventional, is to trigger the ADC captures with a timer and transfer them on the DMA, resulting in an energy consumption figure of 165 µA to obtain 1K samples per second. While this makes good use of peripheral interaction, it does not use any special features on the MCU. The second method offers an improvement in consumption while achieving the same measurement frequency, this time by using Energy Mode 2 (EM2) on the MCU to remain in standby until an interrupt wakes it up. The interrupt could come from a variety of sources including a timer that is functional in EM2. EM2 gives a standby consumption of 900 nA, but enables the MCU to get back to full speed operation in just 2 µSec. This results in an excellent balance between time spent in ultra-low-power modes and energy expend-

ed to switch from EM2 back to full-speed operation, reducing energy consumption to 60 µA to collect the 1K samples per second—a significant drop from the first implementation. This method is likely the most suitable as many embedded applications are interrupt-driven, but depending upon specific circumstances in the application, there are options to reduce the consumption even further. The third example could be considered an “optimized loop” and again uses EM2, but this time instead of waiting for an interrupt, it uses the Wait for Event (WFE) instruction that is part of the Cortex-M instruction set. The WFE instruction enables the MCU to respond to an external or internal event identical to those generated by an interrupt. However, in this scenario, instead of making the transition from the main loop into an interrupt, the MCU can wake up from EM2 and simply execute the next instruction, removing the interrupt latency. While this approach will not suit all applications, where it can be used it again drops the power consumption, this time to less than 20 µA to achieve the same 1K samples per second. Making a careful analysis of how often you need to sample a signal, and MCU power consumption in various modes to achieve that consumption, can be very

RTC Magazine AUGUST 2014 | 25


FIGURE 6: Energy-efficient use of LESENSE.

useful in determining which acquisition method is best suited to your application. Figure 4 shows the current consumption versus the sample frequency for the three techniques described previously. As the graph shows, there are crossover points where it makes sense to switch from one method to another to achieve the best results in terms of energy efficiency. In addition to using the ADC for signal acquisition, the chosen MCU may have additional specialist peripherals. In the case of the EFM32 Wonder Gecko MCU, there is the option to use the Low Energy Sensor Interface (LESENSE) to capture signals coming into the MCU, and only wake the MCU when there is something of interest for the MCU to process. Figure 5 shows the LESENSE concept, in this case looking at an analog signal coming into the MCU. A standard method of dealing with such a signal is to poll the input and continually check to see if the threshold desired has been passed. However, this technique is not energy efficient. Using an autonomous sensor interface capability like LESENSE, the MCU can be configured to remain in a low-power mode (such as EM2, used in the ADC techniques) and only wake the MCU when the threshold has been crossed. Or more usefully, it can be configured to count the number of times the threshold has been crossed and only wake

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the MCU after, for example, five counts. This approach enables a more energy-efficient solution. For example, when the MCU is woken up by the LESENSE peripheral, it will know specifically what to do next and will begin directly managing that part of the application. Figure 6 shows how using an MCU peripheral such as LESENSE can make a very significant difference in an energy harvesting application. The two examples show a measurement of the voltage rail feeding the MCU, supplied by the energy reservoir in the application. In both examples the application is acquiring signals through the LESENSE peripheral at 5 Hz. In the first example it wakes the MCU up on every acquisition, and it can be seen that after a short time the energy reservoir is depleted and the MCU enters reset. In the second example, the LESENSE peripheral is configured to only wake the MCU on every fifth capture. The same amount of data is captured and passed to the MCU to act on, but in this second example the MCU does not enter reset and the application remains functional continuously. A much more energy-efficient solution can be achieved by intelligent use of the MCU’s resources. While the amount of energy we can efficiently harvest from readily available sources for embedded applications has not increased significantly, in recent years the energy requirements of key system components such as MCUs and RF ICs have decreased significantly. This trend











TABLE 1: Energy Harvesting Sources.

toward more energy-efficient IC components enables much more intelligent and useful embedded systems powered by energy harvesting than ever before. With the rapid growth of the Internet of Things market, being able to design self-sustaining sensor nodes has become essential. Certain devices offer considerable advantages over others for building energy-efficient systems.

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Wireless Energy Harvesting Opens Market for Devices on the Internet of Things – and PLM Helps it Grow As many “things” on the Internet of Things become smaller, more mobile and even wearable, they proliferate in the billions. The opportunities are immense, but in a world market with hugely diverse suppliers and users, an appropriately scaled product life cycle management system is essential. BY MARLEE ROSEN, ROSEN ASSOCIATES

FIGURE 1: The TEG shirt illustrates energy harvesting wearable technology with the shirt’s fabric to turn the body’s heat into energy.

The Internet of Things is part of the evolution of the Internet where items are interconnected—from your stove to your toilet or shoes to your shirt—and the future may be found in connecting parts of our everyday lives. But how do we power these devices? Energy harvesting is a terrific solution that derives energy from solar, thermal, kinetic and other sources. It captures it and stores it for small, wireless autonomous devices, such as those used in wireless sensors networks and wearable electronics. From a product design perspective, the opportunity is immense. Imagine these sensors embedded in everything from structures to vehicles to clothing. An office in a skyscraper might alert someone that lights have been left on;

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a vehicle might alert you if the child safety lock has been tripped, or your favorite radio talk program starts in 5 minutes; sneakers could let you know when you’ve reached their optimal mileage threshold. Or what if tunnels could be capable of alerting someone if stress-related cracks formed; or couches could sing out after they’ve swallowed your keys; or you had the option to send text messages or emails with “wearable” technology that is battery-free?

Wearable Technology Opportunity Wearable technology is forecast by Juniper Research to hit $1.4 billion this year, and they predict that figure will hit $19 billion by 2018. This industry is a prime example of the

opportunity that energy harvesting brings with the additional layer of complexity and coordination within the product design process. More and more electronics are being integrated into clothing, either for functional or fashion reasons. For example, music players are being integrated into coats, and fashion designers are using electroluminescent and LED displays, often linked to music, to create active clothing. Much of this requires power, and being able to harness vibration, thermal or solar energy to power displays and wireless links directly, or to recharge thin, light lithium polymer batteries, provides a key step forward for the technology. No one wants to have to plug their shirt into the mains to recharge it, and providing that power from the environment can significantly extend the charging cycle. This also needs a step forward in some of the energy harvesting technology, particularly solar cells. While the efficiency of such cells has increased so that they can generate useful power from indoor lighting, glass or crystalline silicon-based devices can be heavy. However, a new generation of amorphous flexible cells is becoming increasingly popular to integrate into clothing to supply power. One such example comes from researchers at the Australian National University, who have developed a thin, flexible solar panel called Sliver Cell. The technology has been developed for military use as wearable solar panels



to power equipment, and it creates a step to more rugged yet flexible cells. TEGwear technology is another example of a unique thermoelectric energy harvesting technology designed to power body-worn electronic devices. It gets integrated into wearable form factors, such as wristbands or clothing, and absorbs heat from the body, which is converted into electrical energy that serves as an always-available renewable power source (Figure 1). Similar to sunlight exciting electrons in a solar cell, body-heat absorbed by TEGwear technology excites electrons and optimizes this energy for body-worn medical, fitness and safety-related electronics. While the clothing design is not in need of support of a Product Lifecycle Management (PLM) system, the 16 onestage thermopiles, each sandwiched between 2 cm hot and cold plates, could absolutely benefit from PLM in the design of the cold plates that are glued onto a carbon fabric. These cold plates usually will be sewn on the inner side of the shirt to carry heat away and provide the temperature difference. This two-layer construction makes the shirt comfortable and means it can be washed and ironed. Any changes to the engineering of the thermopiles are tracked and carefully audited within the PLM system. This is why device manufacturers in communication, fitness, sports and health industries that have an interest in wearable technology combined with energy harvesting

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RTC Magazine AUGUST 2014 | 29


Figure 2: Product Lifecycle Management software brings product information together in a central location to efficiently manage the product development process.

technology will have great interest in how PLM has the task of supporting, managing and often controlling the entire product creation chain. Expect to see exponentially growing energy harvesting usage for such wearable applications in telemedicine systems and m-health or mobile health initiatives in the form of bracelets, watches and headbands.

Medical Devices Applications Providing a constant energy source is a key design challenge for implantable medical devices.According to the Department of Electronic and Computer Engineering at Hong Kong University of Science and Technology, energy harvesting and power delivery for implantable medical devices will utilize different state-of-the-art mechanisms that are becoming more and more available to do “in-body” energy harvesting as well as “out-of-body” wireless power delivery. For medical devices, energy harvesting technology would eliminate the need for bulky batteries and the risk of battery-related defects. “Energy harvesting is becoming an increasingly viable source of power for a variety of devices, especially where the environmental and economic costs of maintaining batteries is untenable,” says Bob Gohn, vice president of Pike Research. “Consumer products such as laptops and mobile phones are already being powered by energy harvesting technology.” Gohn believes medical device will be the next market to capitalize on the benefits of energy harvesting.

sensors and some of the newer cutting-edge products are looking to PLM to streamline and optimize their design process and ultimately help them get to market faster. However, they may not have the budget of a Boeing or Ford, so a PLM solution geared to address an SMB’s needs would be more appropriate (Figure 2). One example of this is emerging wireless electricity provider WiTricity’s use of Omnify Software to bring their technology to market quicker. They are using this software to automate engineering change orders and product documentation management as well as to centralize information for design teams. They estimate that they could not fully function without this PLM tool, as it is essential to keeping electrical and mechanical design teams in sync, and engineering processes controlled and transparent. This in turn allows WiTricity to bring safe, efficient operation of wireless electricity over large distances to their customers (Figure 3). In addition, energy harvesting companies like Lord MicroStrain Sensing Systems are using Omnify Software for managing the product lifecycle of their smart, wireless sensors that are in use in such applications as advanced manufacturing, off-highway vehicles, commercial and military manned and unmanned vehicles, civil structures and downhole tools. Lord MicroStrain’s design and engineering team was able to enhance and enforce business processes using a PLM system, as well as develop advanced integrations with their engineering design and manufacturing environments.

PLM to Bring Energy Harvesting and Smart Technology to Market With these cutting-edge products comes an opportunity for emerging startups and a wide variety of small and medium size businesses to deliver new or enhanced products and gain a competitive advantage. Software in the form of PLM can help to efficiently develop these products for a successful launch. Omnify Software is one PLM provider that quickly saw how it could help these SMBs do just that by providing an alternative to traditional PLM designed for larger companies. Manufacturers of electronic devices,

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Figure 3: PLM is helping to bring WiTricity’s cutting-edge wireless electricity to market faster.

The PLM software implementation has resulted in a decrease of MicroStrain’s BOM processing time from two to three days to just minutes. The engineers can access approved parts stored in PLM from within their CAD program. The BOMs generated from the engineering systems are imported into PLM for approval, and the released BOM data is sent directly to the ERP for a completely automated and streamlined process. They found their PLM solution helped them to get to market first, stake a larger market share, and maximize profit margins.

Demand Grows from Industrial to Consumer Market Device designers will be looking at using energy harvesting technology for wireless, battery-less storage devices. Existing energy harvesting applications include vibration-based wireless train measuring systems, wireless sensors distributed citywide to implement smart cities, oil field monitoring systems and windup laptops for use in remote regions. This will be augmented with consumer demand for smartphones, tablets, laptops, digital cameras and home entertainment devices. However, this is a price-driven and time-driven market. To help them ensure a first mover advantage, they have also come to realize that it is absolutely paramount to invest in product lifecycle management to be able to invent while at the same time accelerating their time-to-market. PLM really helps minimize costly product errors and manufacturing delays, which for the consumer electronics sector is critical, since their product innovations are typically complex and have frequently changing parts. Manufacturing for consumer electronics and wearable devices is taking place in shifting global locations, with components coming from possibly anywhere around the world along with sales happening everywhere. PLM


enables manufacturers to streamline and manage global supply chains by providing visibility across the enterprise’s entire product lifecycle, even in other countries.

Future Projections Keep your eyes peeled for business opportunities as this new market emerges. Powering small electronic devices such as wireless sensors, smart-building and industrial equipment controls, wellness and wearable monitors, will proliferate the market and create a positive impact. Not only does it protect the environment by reducing CO2 emissions, while eliminating batteries and power cabling, it will also finally enable the Internet of Things (IoT) ecosystem and ignite the creation of many new products. Not too far in the future, we will see hundreds of millions of these kinds of devices deployed in environments such as office buildings, houses, hotels, industrial sites, transportation infrastructure and electric vehicles. Analysis shows that the energy harvesting market will grow to $4.2 billion within five years including the emergence of thousands of developers and design engineers involved throughout the value chain. The development cycle for devices will shorten even further. PLM will be a tremendous benefit to managing the design and production process for companies to stay competitive and bring these timely devices and technology to market in the quickest manner possible. Rosen Associates Tampa, FL.


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03.06.2014 12:28:45

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Robots welding in a car factory.

For Control Systems, Put the Focus on Innovation, Not Integration Rather than try to create control systems by integrating disparate parts, which then must be configured, tested and separately programmed, engineers would do better to start with an integrated high-performance platform and then concentrate on creating innovative solutions in software. BY BRIAN PHILLIPPI, PRODUCT ENGINEER, NATIONAL INSTRUMENTS

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Today’s control engineers are tasked with increasingly complex challenges and face incredible pressure to simplify system designs. To keep pace with this heightened complexity, advanced technologies have emerged that make it possible for control engineers to overcome common challenges. From banks of relays to programmable logic controllers (PLCs) or programmable automation controllers (PACs), these tools traditionally help develop solutions. Although inevitably new systems become too complex for the available technology, so control engineers need to create custom solutions with the combination of several tools. It is from these solutions that advanced technologies continue to evolve to simplify and create efficiencies. One of the latest examples of this is the PAC, which offers processor-based computing with the reliability of a PLC. Based on increasingly complex challenges, sometimes traditional PACs cannot keep pace with advanced technological needs. To solve these challenges, control engineers have started adding custom hardware to high-powered PACs to ensure tighter control, integrated monitoring or custom communication. By creating a custom solution, control engineers can typically solve the problem, although they spend a significant amount of time creating or iterating on the tools used to innovate rather than focusing on the innovation itself. There is a clear trend toward systems that are dynamic, complex, distributed and interconnected. Systems that bridge the cyber and physical world are known as cyber-physical systems and include applications such as smart machines or smart factories. Of course, cyber-physical systems applications are all around us and include applications beyond the industrial automation industry, such as the smart grid, vehicle traffic networks, smart buildings, cooperative robots, telecommunications, automotive systems and avionics. These systems often require a combination of advanced control, data acquisition, condition monitoring, machine vision and advanced motion. In addition, multiple systems need to communicate and interact with each other and the outside world to work most effectively. This concept is commonly understood as the Internet of Things (IoT). To keep up with this accelerating trend, engineers cannot continue to spend time piecing together disparate systems made of PACs or PLCs and custom hardware. Instead, they must focus on innovating advanced systems to solve today’s grand engineering challenges. Fortunately, there is a better way to harness the flexibility of custom design while still enjoying the benefits of off-theshelf hardware like a PAC or PLC. This system combines the flexibility of a user programmable FPGA with the reliable nature of a PAC. This may sound unfamiliar to control designers who are more accustomed to ladder logic than logic gates, although all PACs, PLCs and embedded controllers contain processing elements. Some even contain FPGAs or ASICs used for signal processing and timing, though the chips are not user programmable. These different processing elements are analogous to a basic tool like a hammer. When walking down the tool aisle at the hardware store, a breadth of hammers hang on the wall. While most of these could serve other hammer functions (e.g., driving nails or breaking apart objects), it is critical to use the right tool for the job. PC-based automation is like a general-purpose claw

FIGURE 1: Using a platform-based approach, Viewpoint Systems and The Gleason Works created a smarter machine and significantly reduced development time.

hammer, meaning, it is versatile enough for most applications but it is deficient in more advanced operations as it is too harsh to properly function as a dead blow mallet, too light to act as a sledge and too small to serve as a good framing hammer. For a broad range of applications, the standard floating point processor is suitable, although it falls short with applications that require high-speed timing, triggering, tight latency, fast control loops or custom protocols—this is where a user programmable FPGA is beneficial. Floating point processors can also be used for signal and control processing, however these are costly compared to an FPGA or DSP used for repetitious algorithms. While FPGAs are good for processing-intensive algorithms, they are limited in runtime flexibility. It is the combination of these processing elements combined with the user’s ability to program them that make new PACs, PLCs and embedded controllers an ideal foundation for a platform.

Meeting the Challenge Although there have been tremendous advancements in technology, the trend toward cyber-physical systems presents a real challenge. As the pace of change accelerates, newer, more complex technology emerges faster than ever. Many organizations are falling further and further behind the technology curve, as achieving high-quality results is increasingly expensive and the vast majority of custom development time is allocated to low value tasks. Piecing together a complex system through different vendors and custom hardware is possible, but at what cost? When the next unexpected upgrade comes around, due to a part going end of life (EOL) or a new customer requirement, control engineers are faced with a new set of similar

RTC Magazine AUGUST 2014 | 33


FIGURE 2: The NI CompactRIO performance controller is the latest realization of a next generation hardware and software platform.

problems. If a critical part does go EOL or vendors decide to change their communication protocols, the entire system is at risk of being compromised. When this occurs, control engineers must solve a similar set of challenges every time based on a small piece of the system changing. In addition, creating and maintaining a system like this requires large specialized teams that are both costly and inefficient, as each member of the team must become an expert in a certain piece of the system, including domain experts, VHDL programmers, test engineers, validation engineers, documentation and support. System designers can look to the mobile phone industry to see that platforms are the key to rapid innovation. If we flash back 10 years, before iOS or Android, every phone was built from scratch. Each domain expert or app developer first had to figure out how to interact with all of the different hardware and operating systems before they could begin thinking about how to create differentiating features. As a result, the feature set was extremely limited and the most expensive phones were only feature-rich enough to check email and act as a PDA. A few years later, Apple did something revolutionary— they created a single platform that eliminates the need for a designer to solve low-level tasks like repeatedly interacting with different hardware. Instead, this platform-based approach helps designers focus on innovation through software. By simplifying the hardware design, developers can use many of the same software building blocks to focus on

34 | RTC Magazine AUGUST 2014

differentiating a portion of the system. Apple could upgrade the hardware, provide new sensors and more processing power, and allow the software to evolve seamlessly with the hardware. Over a million apps later, domain experts are still discovering new ways to innovate. With a unified platform, the same approach can be applied with industrial automation, which makes it possible for control engineers to focus on innovation rather than integration. Applying the platform principle to industrial automation also gives a new meaning to the term “modular system.” With a platform, the hardware and software are modular and reusable. This means engineers can save development time by reusing many of the core software blocks to build a system, which makes it possible to spend time innovating in places where they can create differentiation. A modular hardware and software platform integrates many of the previously disparate systems into a single system to innovate upon. This approach also simplifies custom design because it allows domain experts to work on the software and hardware development without a computer science or VHDL background. In addition, domain experts can tap into a worldwide network of system integration partners that are skilled in providing startup assistance, training and support. This platform-based approach is available and it includes customizable off-the-shelf hardware that combines the reliability and control of a PAC with the flexibility of an FPGA. Platforms are proven to simplify the complexity of system design while increasing efficiency. One such platform is available with the NI CompactRIO software designed controller, which is based on the NI LabVIEW reconfigurable I/O (RIO) architecture. This tightly integrates a real-time processor with a user programmable FPGA that is connected to modular I/O and programmed with NI LabVIEW system design software. This powerful platform facilitates rapid

algorithm engineering and openly supports multiple models of computation. Even more, the hardware and software platform is organized around an agile, platform-based “design V” methodology with integrated simulation and verification tools that reduce development cost and risk while facilitating high-quality results. An example of this platform used to design complex smart machines comes from the collaboration of Viewpoint Systems and The Gleason Works (Figure 1). These companies created a smarter machine that defied the conventional approach to gear lapping. Instead of relying on passive physics to lap the gears, which would lead to a tradeoff between refined gear surfaces or spacing errors, Viewpoint and Gleason created a smarter machine to achieve the best of both worlds. Using advanced order analysis to monitor and control the lapping process, they were able to produce higher quality gears in 30 percent less time. NI’s platform-based approach of combining off-the-shelf CompactRIO hardware and LabVIEW software continues to expand with the new CompactRIO performance controller, which integrates the latest technologies including Intel Atom dual-core processors and Xilinx Kintex-7 FPGAs (Figure 2). With this powerful processor, engineers can simplify the complexity of their system by adding vision acquisition and processing capabilities. In addition, with support for an embedded UI and a built-in display port, engineers can further

National Instruments Austin, TX. (512) 794-0100




simplify their system by driving their local HMI directly from the controller. This new controller is suitable for applications in harsh environments and provides flexible, high-performance data transfer with modular C Series I/O. By using a platform-based approach, engineers can port code seamlessly while benefiting from the latest technology. With industries such as steel milling, energy, transportation, mining, textiles and semiconductor, the need for smarter machines is driving the demand for improved machine control design technology. PACs and embedded controllers using the latest hybrid processing technology can help advance and simplify machine design by shifting the architecture from several disparate systems mixed with off-theshelf and custom technology to fewer, more consolidated software-designed controllers. This next generation platform of embedded controllers will not replace many of the old stalwarts of the process world. Rather, these controllers are ideal for the next generation of smart machines and are best suited for more advanced designers looking to get to market faster using a simplified architecture.


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Matching I/O and Processor Performance Removes Data Processing Bottlenecks PCIe 3.0 and attention to signal integrity prove high-speed VPX for connected embedded designs. BY VINCENT CHUFFART, KONTRON

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Offering application-enabling data transfer performance, VPX VITA 46 is one of the first modular computer open standards to define a connector and backplane infrastructure that allows data transfers at rates in excess of one gigabit per physical channel. With this advance, VPX systems are able to implement the same state-of-the-art interconnect technologies that currently exist in server and consumer PC arenas. As a result, VPX users greatly benefit from the same level of performance for input/output, graphics and computer data exchanges, while the ratio of I/O throughput to CPU processing speed remains coherent. These values address key design requirements in the growing realm of connected embedded applications, which often require non-stop, high-speed performance in rugged, automated settings. With high data rates over VPX, designers have access to a long-term deployment path for high-speed data transfer applications. At the same time, Generation 3 Peripheral Component Interconnect Express (PCIe 3.0) is emerging as a leading serial link technology for VPX, relying on point-to-point connections to manage high bandwidth traffic. This design approach is particularly important in proving VPX for high level sensor processing common to connected embedded applications.

Processing High Data Rates in VPX Platforms The VPX specification acknowledges that high-performance data processing applications must not be bottlenecked with limited I/O performance. After having successfully addressed the 5 Gbit/s level for PCIe 2.0, VPX is now ready to adopt the higher data rates required by the latest version of two fundamental protocols including PCIe 3.0 at 8 Gbits/s and Ethernet at 10 Gbits/s. This affords a design advantage in moving away from parallel bus architectures, and lets systems instead rely on higher performance switch fabric options. Switch-based fabrics allow seamless implementation of all routes to and from boards dynamically—creating the bandwidth required for any application’s data flow, all within the same hardware. For designers of connected embedded systems, this enables a new breed of unparalleled applications for high-performance data processing platforms. Apart from VITA 46, OpenVPX VITA 65 (built on top of the VPX norm) is the subsystem level standard specifying how VPX modules and backplanes interoperate, in which protocols and with what pin assignments. The current ANSI ratified OpenVPX version is “ANSI/VITA 65-2010 (R2012) OpenVPX System Specification” approved in 2012. This R2012 version of VITA 65 defines a nomenclature for daughter modules and backplanes up to a rate of 6.25 Gbaud, which is sufficient to run protocols such as Serial RapidIO and PCIe Gen2. The next revision currently under consideration includes support for PCIe 3.0 and 10G Ethernet up to a rate of 10 Gbits/s. The rise of VPX in industrial deployments has been a long time coming, and overall VPX revenues were projected by industry analysts to match VME by 2012. This shift is related primarily to military design and hasn’t evolved as expected based on cuts and ongoing uncertainty in military program spending. New data from IMS Research shows that 2016 is a more likely timeframe for a VME to VPX crossover, with

FIGURE 1: Built around PLX ExpressLane PCIe 3.0 switches, Kontron’s VX3042 and VX3044 Intel Core i7based single-board computers (SBCs) routinely achieve 5.6 gigabytes per second (Gbyte/s) in data throughput between any boards in a VPX rack.

other market sectors picking up on VPX technology as well. Members of the VITA Standards Organization are reporting VPX design wins that illustrate the potential of this platform for industrial arenas. Where an existing distributed application might exchange information on Gigabit Ethernet, for example as implemented on most VME or CompactPCI platforms, VPX platforms can implement the TCP/IP protocol over the PCIe 3.0 infrastructure. This simple method taps into high-speed PCIe 3.0 bandwidth for data transfers by selecting a different IP address to connect to the other boards, handled by VXFabric, Kontron’s open infrastructure, which implements efficient inter-board communication at hardware speed. No software coding changes are required, protecting applications from obsolescence as well as the complex, low-level details of the current generation of PCIe silicon management.

Building Value with Switch Fabric Options Switched fabric bridges current gigabit Ethernet on the backplane (in industrial platforms such as VME, cPCI, VPX) and the next data plane generation of 10G and 40G Ethernet. Industrial applications seeking a cost-effective performance jump can today access 10G and 40G performance in compact VPX-based systems. Featuring low power consumption and harsh environment capabilities, rugged VPX and PCIe 3.0 work together to address all fast and low latency peer-to peer inter computer node communication within a chassis. This holds promise for enabling significant advances in image processing—for example 3D reconstruction applications such as radar and sonar—while also reducing system footprint. PCIe 3.0 is the enabler here, facilitating point-to-point connections between boards as a means of managing high bandwidth traffic. Backplane routing is specific to each application, and is used to create connections between boards that match the application’s data flows. PCIe 3.0 switches

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FIGURE 2: None of the VITA 46 or VITA 65 standards specify the requirement for high-speed interoperability of modules and backplanes; this includes timing, eye openness, jitter budget and more general electrical channel characteristics. Rather they point to the electrical requirements inside the existing base protocol standards such as PCI Express or Ethernet 802.3, and also to the VITA 68 standard, currently a draft.

allow systems to combine different data types in a single converged pathway. For example, data (compute, communication or storage) is created and consumed as PCIe on each of the slots in the rack, delivering efficiency both in hardware architectural and software usage. Proving this in defense electronics, Kontron has developed a set of VPX modules that take advantage of these high data rates over the VPX backplane. The PCIe 3.0 protocol operating at 8 Gbits/s and the Ethernet 10GBase-KR links were successfully qualified at extended temperature environments (Figure 1). The availability inside a VPX chassis of a high number of switched 10 Gbit/s Ethernet links is changing the way parallel processing can be organized. A flat CPU board interconnect could be easily set up using standard software architecture. In a real-world scenario proven by a Kontron-designed reference system called StarVX, more than 20 CPU boards could compute in parallel, exchanging data at Gigabyte speed without any bandwidth limitation due to the target board position (Figure 2).

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Designing each channel—or single differential copper pair—requires attention to a variety of factors to ensure ideal signal integrity for high-speed I/O processing in a rugged VPX system. For example, stubs can limit channel performance; higher I/O speeds demand stubs to be virtually nonexistent in order to avoid influencing signal integrity. Stubs are short conductive tracks that don’t belong to the main signal path. Actually, any protrusion from the smooth path of the signal transmission line is considered a stub and can have a direct negative impact on signal processing. At 10 Gbits/s, with signal traveling in copper at close to half the speed of the light, each bit transiting over the backplane is separated from the next bit by less than 2 cm. For example, short stubs of 5 mm would typically reflect part of the signal back to main path and to the transmitter, thereby affecting half of the length of a following transitioning bit, in addition to the losses resulting in the main direction forward. It sounds simple, yet stubs are everywhere. The connector contact itself, depending on its technology, could be a source of stubs, for example a rear VPX connector with populated contacts. Even a metalized via drilled in the PCB, enabling transition from one layer to another, could create a significant stub. The backplane itself, typically 5 mm thick when it is designed to host front and rear VPX connectors, will also exhibit stubs at the VPX connector via unless they are removed by using techniques such as blind via or back-drilling (Figure 3). Impedance mismatch inside vias—or the transitions between boards—must remain consistent; differential impedance of pairs carrying data must be 100 ohms +/- 10% according the IEEE 802.3 standard. This is a critical design detail, as impedance discontinuities along the signal path create partial signal reflections and ringing, resulting in degradation of attenuation and return loss parameters. However, inside the via of VPX connectors, both at the

FIGURE 3: These views illustrate how design techniques such as blind and back-drilled vias can eliminate signal integrity issues caused by stubs.

module connector and the backplane connector, differential impedance is generally much lower and runs in the range of 80 ohms and below. Good signal design practices will also focus on managing crosstalk, PCB losses and length mismatch. Appropriate gaps and reference planes manage crosstalk, and the right PCB materials help avoid high attenuation that could lead to high Inter Symbol Interference (ISI), a phenomenon defined as distortion due to differing attenuation of bit sequences. Most protocols do not require a precise differential pair length adjustment. However, the plus and minus components of the pair should be the same. Length mismatch directly impacts the eye width, and accordingly, the bit error rate, and requires greater compensation when it occurs inside the connector itself.

with reference systems and defense electronics deployments, this combination of technologies provides significant opportunity and advantage for designers—supporting innovation and allowing access to a new breed of applications for high-performance data processing platforms. Kontron Poway, CA. (888) 294-4558

Proving Performance for Industrial Embedded Applications Connected embedded systems must frequently be designed to withstand the toughest environmental conditions: extended temperature ranges (-40° to +85°C), humidity, vibrations and power fluctuations. Even heat build-up and energy absorption have to stay within narrow ranges, for example in remote deployments or harsh manufacturing settings, where only passive cooling technologies are permitted. Rugged VPX fits the bill; it supports PCIe 3.0’s high-speed connections in harsh environments, and VXFabric readily bridges the gap between this disruptive technology and currently deployed applications exchanging data on gigabit Ethernet. Further, TCP/IP applications run unmodified on proven, ruggedized VPX platforms, protecting software investments over long-term deployments. 10 Gbit/s baud rates are starting to be deployed over the VPX infrastructure, which allows standard protocols such as Ethernet and PCIe to run at scalable speeds defined by the number of lanes forming a port. Carrying multi-gigahertz signals, VPX connectors and backplanes are enabling systems where boards no longer share available bandwidth and are capable of one or more dedicated 10 Gigabit connections via Ethernet or PCIe. Processing rates are backward compatible with speeds of the previous generation protocol, and can be activated only where necessary in the critical portion of the data path. The CPU to I/O ratio is kept in the same range as non-embedded computer equipment, based on cost-effective, standard software architectures. Proven RTC Magazine AUGUST 2014 | 39


Porting Class III Medical Software to Android Android is quickly becoming the de facto standard for companies that want to build mobile applications. This is especially true for medical device companies that need a mobile device OS that has a rich set of supported hardware and can be ported across multiple devices with ease. BY SRI KANAJAN, SRI VENTURES, SHRIRAHNG KHARE, PERSISTENT SYSTEMS, AND RICHARD JACKSON, BIOLASE

FIGURE 1: Implantable defibrillator system—implantable device (IMD), programmer.

It is often desirable and now quite possible for a company to develop an application for a custom device and then quickly port a scaled-down version of the application to an Android smartphone platform. Here we will describe an approach to moving Class III medical software to Android from the perspective of the design methodology, software architecture and automated verification framework. The solution is presented in the context of a Class III medical software application case study that was successfully ported to an Android 4.1 tablet platform. Implantable defibrillators are devices that are implanted into the human patient. This device continually monitors the heart’s electrical rhythm for potentially life threatening rhythms that may cause death. In the event that such a 40 | RTC Magazine AUGUST 2014

rhythm is detected, the device provides shock therapy in a timely fashion to save the patient’s life. This implanted device can be accessed and monitored through a wireless connection with a mobile programming device. This device is typically called the programmer. Figure 1 shows an illustration of the system. The target platform is a tablet with Android 4.1 software based on Java with a USB-based radio card. The wireless protocol used between the programmer and implanted device is a custom protocol that conforms to the Medical Implant Communication Service (MICS) specification. The methodology utilized for this project complies with the FDA guidance documents and external standards. Figure 2 describes the set of standards that drive the development methodology that was used. The key characteristics below dominate the development process for both production code and verification assets. An example screen shot of the final application is shown in Figure 3. 1. Requirements 2. Traceability of Requirements to Design Artifacts 3. Accountability: Reviews are documented and review meeting attendees are recorded such that there is a trace of who, how and when decisions were made. 4. C  hange Management: All product modifications are recorded in the form of change requests or change orders that capture all aspects of that change’s lifecycle, including independent verification of the change. 5. Risk-Based Development Process: The degree of code verification coverage of a specific software component is determined by the component’s risk level. Standard risk analysis techniques such as FMEA and fault trees were applied. 6. Peer Review: All work output (requirements, design, code, test procedures) are peer reviewed by at least one independent reviewer.

Software Architecture Given the set of requirements, the next challenge was to establish a robust architecture. The key technical architectural drivers include temporal determinism, reliability and availability, fail safety, extensibility, portability, reusability and testability.

FIGURE 2: Standards driving the development process.

The resulting software architecture based on these drivers is illustrated in Figure 4. The Android OS is an open and widely used OS that can be customized for the needs of a safety-critical, soft real-time system, and can also be ported quickly to other hardware platforms such as smartphones, hence the decision to use Android. The architecture is a highly customized model, view and controller framework where the feature state machines that react to the user interactions and interact with the model data elements through getters and setters, represent the Controller. There are a number of data management classes (e.g., ACS/Communication system, Session Manager) that represent the model. The view is at the top level of the architecture and would primarily handle all the user interaction. This system is a soft real-time system. For example, the live electrocardiogram (ECG) drawing requires data to be streamed from the implanted device and then rendered onto the display in real time. Critical commands from the tablet to the implanted device must be processed within a deterministic deadline. In addition, the application must be secure from interruption or corruption or unintended use. For example, the user must not be able to install unauthorized applications or switch to other applications during run time. In order to guarantee these requirements, a few key architectural changes were performed. First, non-relevant Android applications that could take up processing time were removed. Then any hardware features not required by the application were disabled. This was done to ensure singular control of the tablet by this application

upon power on. This also required special authority from the Tablet OEM via the use of an enterprise software development kit and signing of the custom OS shell with the OEM platform key. It was also necessary to minimize the garbage collection execution time. And that required minimizing any dynamic object creation and destruction. The solution was to employ an object pool design pattern where objects that are regularly generated (e.g. GUI event objects, ECG objects and communication system message objects) are reused through a managed object pool. This minimized the fragmentation of memory and the pile-up of unreferenced objects that would cause additional effort for the garbage collector. The default Android GUI design pattern is to use multiple activities and multiple views. However, this approach incurs significant heap and context switching overhead as each

FIGURE 3: A screen from the final android application.

RTC Magazine AUGUST 2014 | 41


is a major differentiator between class III medical or other regulated industries and commercial software development. The degree of control would not have been possible without a working partnership with the OEM.

FIGURE 4: Software architecture.

activity is a separate thread. The solution was to use a single activity, multiple view design pattern. Figure 5 illustrates the differences between the standard Android framework (left) and the framework we employed (right). Another key to the success of the software architecture was the development of a strong partnership with the tablet vendor, Samsung. The tablet vendor provided APIs and customization support to ensure a locked down environment as well as support for integration of the USB-based radio card. The idea of ensuring a controlled execution environment

View 3

Light weight view switching with no lifecycle management Controller

Life cycle management


View 2

Using Lightweight GUI Framework

View 1

Activity C

Activity B

Activity A

Using Standard Activities

Frequent activity switch causes GC to be called often leading to degradation of system performance


No heap calls Hence no GC

Preallocated Memory

System Heap

FIGURE 5: Standard multiple view multiple activity android GUI framework vs. case study’s lightweight GUI single activity multiple view framework.

42 | RTC Magazine AUGUST 2014

Automated Verification Framework The verification of Class III medical software is a challenging task. Test automation is critical to ensure a quick verification of software changes and to make testing repeatable. However, in order to build automated verification tests, a robust automated verification framework is necessary. Here we look at our automated verification framework for Android and some of the strategies employed to verify specific requirement types. A single run of the entire automated test suite took 16 machine days or 2 calendar days with 8 concurrent machines and 2 managing engineers. The categories of verification performed on the system included: • Requirements-based tests (Mostly Automated) • Integration tests (Mostly Automated) • Stress tests (Totally Automated) • Unit test (Totally Automated) • System tests (Manual) • Exploratory testing (Manual) Since this project was a port onto a new platform while maintaining similar requirements, the test case descriptions and manual test procedure descriptions could be ported with minor modifications. The degree of test coverage for all test categories was at a minimum maintained at the same level as the legacy platform but improved where required. Figure 6 illustrates a legacy manual test procedure that verifies a set of requirements. This test procedure was then automated

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Instructions Criteria Launch programmer software on programmer.

Acceptance Criteria


Pass/ Fail


Traceability to Requirements Tag Tag

The error, log, and halt screen is displayed


Take radio board out of programmer Select “Scan for devices” button from the start menu. 20/8200

Verify GUI on error, log, and hault screen

The screen shall have a red background



Verify GUI on error, log, and hault screen

The screen shall contain white text in Roboto font


FIGURE 6: Example of a legacy manual test procedure and traceability to requirement tags.

by developing a Java test script using the automated test framework. The automation framework was developed in order to ensure the maximum degree of automation to verify all the requirements. For requirements where the cost of automation was deemed too large (for example, automating the visual inspection of the real-time ECG graph would be very complex), a semi-automated approach was required—one that included operator input during the segments where manual verification was needed. Figure 7 illustrates the automated verification framework.

Validation of the Automation Framework The correctness of the test execution results depends heavily on the correctness of the automation component that FIGURE 7: Automated Test Framework.

is being verified. Therefore, if a safety-critical component of a high risk level is being verified by the automation framework, then all the components within the automation framework that is utilized for the verification of that component need to be validated via the same verification process as required for the process documents defined in Figure 2. However, the FDA guidelines do recommend a less burdensome approach to verification. For example, note that the framework illustrated in Figure 7 contains a mix of in-house developed utilities such as the telemetry message verification (sequence verifier), and off-the-shelf components such as adb and Robotium Solo. Depending on the risk level, off-the-shelf components can be verified through documenting the degree of industry usage and the evaluation of the published defect list of that software. Thus mature software with significant industry usage would have a low likelihood of major defects. Another strategy to minimize verification burden is to look for opportunities to verify the component downstream. For example, if every screenshot is verified manually through visual inspection, then the tool used to capture the screenshot can be deemed to be validated downstream as part of the screenshot verification protocol. In either approach, it is valuable to document the set of components, the risk level of the component, the verification strategy, and the reasoning behind the strategy choice. Here we have examined a case study where a Class III medical device system was ported over to an Android platform. The combination of development methodology, software architecture and automated verification framework, enabled a successful outcome. These concepts may be applicable for other companies that face similar challenges of porting their legacy technology to the modern mobile tablet or smartphone-based platforms.

SRI Ventures Menlo Park, CA (650) 859-2000 Persistent Systems Santa Clara, CA (408) 216-7010 Biolase Irvine, CA. (888) 424-6527

44 | RTC Magazine AUGUST 2014

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RTC PRODUCT SHOWCASE Dual 100 GigE FPGA-Based Adapter for Network Monitoring and Cyber Security

An all-in-one instrument integrates a mixed-signal oscilloscope, function generator, digital multimeter, programmable DC power supply and digital I/O. Users interact with VirtualBench through software applications that run on PCs or iPads. The device provides the most common functionalities affordably and opens up new possibilities for how engineers can use benchtop instruments. Because VirtualBench uses today’s consumer computing platforms, engineers and scientists can take advantage of the latest technologies like multitouch displays, multicore processors, wireless connectivity and intuitive interfaces. The simplification and increased capability through software leads to more efficient circuit debugging and validation. National Instruments’ software-based approach to test and measurement offers a software user experience that is more intuitive, creating efficiencies that go above and beyond simply having these five devices in a single device. Key benefits include the fact that VirtualBench takes up minimal space on a desktop or benchtop, and the consistent, user-friendly interfaces simplify instrument configuration. VirtualBench offers new capability and convenience with a consolidated view of multiple instruments, visualization on larger displays and quick functionality to save data and screenshots. In addition, it integrates seamlessly with National’s LabVIEW system design software. VirtualBench is now available worldwide for $1,999; the VirtualBench app for iPad will be available in the App Store later this summer.

A new Dual 100G deep packet inspection (DPI) Adapter/ NIC is optimized for 200 Gbit/s lossless packet capture and packet processing for network monitoring and cyber security applications. The ANIC-200K from Accolade Technology introduces the Turbo Packet Processor (TPP) implemented in a state-of-the-art FPGA. The TPP design is based on a high-performance, multi-stage pipelined architecture consisting of a packet parser and processing stages. The TPP also features a high-performance DMA engine configurable for ring buffer or scatter gather DMA operations. The ANIC-200K is a 100 GigE PCI Express Card designed for demanding Network Monitoring and 100G Network Interface (NIC) applications. It features Dual CFP2 Interfaces that support SR10, SR4, LR4 and ER4 modules. The ANIC-200K’s architecture is based on a scalable pipelined architecture, implemented in an FPGA supported by a high-performance DDR3 Memory subsystem. In Monitoring applications, the ANIC-200K offloads Host CPUs in applications that demand full 200 Gbit/s lossless packet capture onto the adapter buffers and 100 Gbit/s transfer across the PCIe bus into host buffers. It also features a high-performance TX-DMA capability, which operates on a ring buffer or in scatter-gather mode. Host offload functions for packet capture include time stamping, packet filtering, packet slicing and hash-based classification. The ANIC-200K features a high-performance DMA subsystem for efficient burst transfers of data across the 16-lane, Gen 3 PCI Express Bus. The ANIC-200K presents data in a programmable organization of ring buffers that enable load balancing to optimize the use of multicore CPU resources. The ANIC-200K’s target applications include network forensics application performance measurement, next generation firewalls and video stream monitoring. It is targeted for use in test and measurement equipment, cyber defense, VOIP monitoring and quality of service. This also includes telecom infrastructure monitoring and Big Data analytics.

National Instruments, Austin, TX (512) 794-0100.

Accolade Technology, Mansfield, MA (844) 399-9903.

Five Instruments with a Single Software-Based, All-in-One Device

RTC Magazine AUGUST 2014 | 45

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High Performance Computing Integrated Into Compact Rugged COM Express Module A high-performance, Intel Core i7-based Rugged COM Express module is designed for robust, mission-critical operations. The CB70C from MEN Micro is a VITA 59: RCE design that combines with advanced Intel processors to provide state-of-the-art PC technology in a rugged small form factor with scalable performance using 1, 2 or 4 processing cores, depending on system requirements. The Intel Core i7 family provides a core frequency of up to 1.2 GHz and a Turbo Boost frequency of 3.1 GHz. The processors also support Intel AMT, Open CL 1.1 and highend graphics. The BIOS with integrated AMT support can be easily and cost-effectively adapted to the final application. A board management controller supervises board functions and temperatures. The new module offers a number of I/O interfaces including PCI Express, LVDS, DDI, VGA, HD audio, SATA, Ethernet and USB for exceptional flexibility in system design. The board boasts up to 16 Gbytes of directly soldered main memory and supports other memory like USB Flash on the carrier board. The CB70C is compatible with COM Express Basic modules of pin-out Type 6. VITA 59 RCE: Rugged COM Express, currently in preparation, ruggedizes the common and well-accepted Computer-on-Module concept to enable this cost-effective technology to be employed in harsh environments and applications. Embedded in a conduction-cooled cover and frame with a thermal connection to the PCB, the CB70C operates over a wide temperature range of -40° to +85°C. This secure cover also provides 100% EMC protection as well as resistance to high levels of shock, vibration, dust, humidity and chemicals. Pricing for the CB70C is $2,125. MEN Micro, Blue Bell, PA (215) 542-9577.

High-Performance, Low-Power Intelligent Box PC, Based on Fourth Generation Core Processor A high-performance and low-power intelligent Box PC is powered by the fourth generation Intel Core ultra-low TDP (ULT) SoC processor formerly codenamed Haswell. The WEBS-5481from American Portwell is a suitable fanless controller for applications in digital signage, surveillance, image processing and machine automation industries. The WEBS-5481 is powerful but not power hungry; it utilizes the dual-core fourth generation Intel Core processor with Turbo Boost Technology 2.0 (selected CPU SKUs), Hyper-Threading Technology and Enhanced Intel SpeedStep Technology. By adopting Intel’s SoC platform, which integrates CPU and PCH into a BGA package, WEBS-5481 is much smaller, sleeker and lighter compared to its previous generation. In addition, the elimination of the 2-chip platform enables a more effective thermal design for the WEBS-5481 intelligent Box PC. WEBS-5481 also offers clear and concise video and graphics capabilities that take full advantage of the fourth generation Core processor with integrated HD4400 graphics engine, which outperforms its predecessor by over 20%. In addition to the built-in triple-display interfaces, two additional display devices are made available by Portwell’s graphics modules; thus, it can support up to five display outputs by extended mode in the OS. Product reliability and stability are definitely uncompromised; WEBS-5481 is rated IP40 and certified by industrial product quality tests, such as an anti-vibration test of up to 5 Grms and an anti-shock test of 50G. Portwell’s WEBS-5481 has proven itself to be a perfect solution for video/graphics-demanding and automation control systems. The versatile WEBS-5481 system supports many other important features, including up to 16 Gbyte of DDR3L memory, triple display with DVI-D, HDMI and DisplayPort, 5.1-CH audio, and dual Intel Gigabit Ethernet ports. It also offers rich compact I/O functions including 2 x SATA, 2 x USB 3.0, 2 x USB 2.0, 1 x 8-bits GPIO and 6 x COM ports. To enhance system flexibility, customers can further augment functions per their specific needs via two antenna interfaces and an onboard SIM card holder for Wi-Fi or 3G/GPS module, and two mini PCIe sockets for expansion; one or more PCIe expansion cassettes can be offered by counterparts of WEBS-5481 for hungry demand. American Portwell, Fremont, CA. (510) 403-3399.

46 | RTC Magazine AUGUST 2014

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Smart Module Integrates a Bluetooth 4.1 Low Energy Stack for Use with or without a Host MCU An integrated Bluetooth 4.1 Low Energy (BTLE) module offers stack and onboard support for the common SIG low-energy profiles, and speeds time-to-market while ensuring Bluetooth compatibility, eliminating expensive certification costs and reducing development risks. The RN4020 module from Microchip Technology is also pre-loaded with the Microchip Low-energy Data Profile (MLDP), which enables designers to easily stream any type of data across the BTLE link. Because the RN4020 is a stack-on-board module, it can connect to any microcontroller with a UART interface, including hundreds of PIC MCUs, or it can operate standalone without an MCU for basic data collection and communication, such as a beacon or sensor. This standalone operation is facilitated by Microchip’s no-compile scripting, which allows module configuration via a simple ASCII command interface—no tools or compiling are required. The designers of cost-sensitive embedded applications are

looking for turnkey solutions that make it easy to add the low power consumption and simplicity of Bluetooth LE connectivity, which enables several years of operation from a single battery and has a large installed base of compliant smartphones, tablets and computers. Example markets that need these low-power wireless command-and-control solutions include home automation and appliances; medical and wearable devices; toys, tags, fobs and remote controls; pulse and proximity sensor-based systems; and even industrial applications. The RN4020 Bluetooth LE Smart module includes all of the hardware, software and certifications that designers need to easily add this low-energy connectivity to any design, while easing End Product Listing (EPL) via QDID Bluetooth compatibility testing. All of the programmable profiles are stored and selectable on the module, including Microchip’s flexible MLDP and the common Bluetooth SIG low-energy profiles. In addition to common public profiles, private services can be created via the ASCII command interface. The RN4020 also provides a built-in PCB antenna with 7 dBm transmit power and a receive sensitivity of -92.5 dBm, enabling operation over 100 meters in a compact form factor of only 11.5 x 19.5 x 2.5 millimeters. Microchip also announced today the flexible RN4020 Bluetooth Low Energy PICtail/PICtail Plus daughter board, which is available now for $49. This board enables code development via USB interface to a PC, and over the onboard In-Circuit Serial Programming interface for Microchip’s PICkit or MPLAB REAL ICE tools. It also leverages customer investments in Microchip’s existing development boards with a PICtail interface, such as the Explorer 16, PIC18 Explorer and PIC32 I/O Expansion Board. Additionally, the onboard eXtreme Low Power (XLP) PIC18 microcontroller allows the PICtail board to run in standalone mode, powered by USB from the host, enabling portable demonstrations and proofs of concept. The RN4020 Bluetooth Low Energy Module is available today for $6.78 each in 1,000-unit quantities. Microchip Technology, Chandler, AZ. (480) 792-7200.

Highly Integrated Wi-Fi (SiP) Module Features Low Standby Power Requirements A very small and highly integrated 802.11b/g/n Wi-Fi System in Package (SiP) module offers compact solutions for the Internet of Things. The EC19W01 from Econais offers low power drain and features fully integrated MCU, Wi-Fi, cloud connectivity, flash and antenna that is fully certified with FCC, EC, IC and TELEC. The EC19W01 incorporates the latest Wi-Fi 802.11b/g/n standards and features to give designers a full array of options for embedding the module in their designs to get their devices on the Internet and in the Cloud as smartly as possible. Features

include AirPlay, Wi-Fi Direct, ProbMe configuration, full TCP/ IP stack, HTTPS/SSL, DHCP Client/Server, WPS, legacy Wi-Fi Client and SoftAP modes with WPA/WPA2 support, Serial to Wi-Fi, Cloud Service Support and more. Very compact, the EC19W01 is 14 x 16 x 2.8 mm in size. Engineering samples and production quantities of the EC19W01 are available now. The EC19W01 Development Kit (EC19W01EVB) is also available from Econais and through their global representative and distribution network of partners.

Econais, San Jose, CA (408) 827-8331.

RTC Magazine AUGUST 2014 | 47

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Instrument Measures Temperature, Velocity and Pressure at Same Time A new instrument measures the temperatures of solid materials and surrounding air, while also tracking air velocity and air pressure. Measurements are taken simultaneously at multiple points to accurately profile heat sinks, PCBs and card racks for testing and characterization. Developed by Advanced Thermal Solutions (ATS), the iQ-

CompactPCI Serial PMC Module Carrier A new peripheral slot board for CompactPCI Serial systems acts as carrier card for a PMC-style mezzanine module. PMC modules are provided with a legacy PCI interface and are widely in use for industrial and scientific applications. The SK1-Chord from EKF Electronik supports the most common 32-bit 33/66MHz PMC modules. The SK1-Chord is equipped with a PCI Express to PCI bridge for conversion of data from the CompactPCI Serial backplane, to the onboard PCI parallel bus. The PMC module fits on the PMC connectors J11/J12 at 10 mm height. The SK1Chord can be installed into any peripheral slot of a CompactPCI Serial backplane. EKF Elektronik, Hamm, Germany +49 (0)2831/6890-0.

48 | RTC Magazine AUGUST 2014

200 is a laboratory-grade instrument that simultaneously captures thermal data from up to 12 thermocouples, which can be J, K, T and E types. The thermocouples provide surface area temperature measurements on heat sinks, components, housing parts and other locations to track heat flow or detect hot spots. Surface temperature data is recorded from -40° to 750°C. At the same time, air temperature is measured via 16 hot wire anemometer ports using ATS single-sensor technology. There is no need to change sensors when measuring different velocity ranges. The standard range for air velocity measurement is 0-6 m/s (1,200 ft/min). For custom calibrations, the available range is from 0 to 50 m/s (10,000 ft/ min). The iQ-200 can be used with ATS’ low-profile candlestick sensors. Four additional ports on the iQ-200 support differential or absolute pressure transducers to capture pressure drop data along circuit cards, assemblies and orifice plates. Pressure measurements are taken from 0 to 1,034 Pa (0 to 0.15 psi). IQstage software manages the incoming data from multiple sensing devices, and provides detailed graphical presentation on monitors and documents. The iQ-200 connects via USB to any conventional PC for convenient data management, storage and sharing. List price thermal is $24,500, including 12 J-type thermocouples, 16 candlestick sensors and 4 differential pressure sensors. Advanced Thermal Solutions, Norwood, MA (781) 769-2800.

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150W Medical Grade Desktop Power Supply Meets Efficiency Level VI The PEAMD150 Series of AC/DC adapters from The Power Partners provides 150W in a compact 7” x 2.56” x 1.57” case. The PEAMD150 Series is approved to the highest safety standards, including EN/ES60601-1 3rd Edition with Means of Patient Protection (2 x MOPP), and meets FCC Class B limits of both radiated and conducted EMI. Class I and Class II AC inlets and single output voltages from 12 VDC to 48 VDC are available, making the PEAMD150 Series ideal for a variety of medical and dental products for home health care or hospital/office/lab-based applications.

The Series is compliant to the latest Energy Star Efficiency Level VI standards for average efficiency and standby power. Comprehensive protection circuitry, including overvoltage, overload and short circuit protection, is inherent in the design. MTBF is specified at >100,000 hours at full load. The PEAMD150 Series provides a highly reliable and energy-efficient solution at a reasonable cost of less than $45.00 in OEM quantities. Power Partners, Hudson, MA. (978) 567-9600.

PICMG 1.3 SHB with BGA-Mounted Intel 4th Gen Processors A full-size PICMG 1.3 single host board (SHB) incorporates ball grid array (BGA)-mounted, 22nm, 4th Gen Intel Core i7/i5/ i3 processors. BGA mounting (i.e., soldered) provides greater reliability in challenging and mobile environments than socketed processors, which may become dislodged. Other advantages of BGA processor mounting include lower thermal resistance, lower unwanted inductance and superior electrical performance. In addition, it incorporates the Intel QM87 PCH chipset and up to 32 Gbyte 1600 MHz DDR3 memory. Designed to support applications requiring the maximum in data access, the MB-80560 is especially strong in I/O capability. For instance, I/O for the device includes: 4x SATA3 with RAID, 6x COM, USB 3.0 and 2.0 configurable to 12x, 1x LPT and 2x GbE LAN.

In addition to providing a range of performance between 1.6 and 3.3 GHz, the Intel i7/i5/13 processors have rich support for the Intel Advanced Technologies, such as Virtualization Hyper-Threading, Intel 64 and more. The Celeron processor enables a particularly cost-effective option at 2.20 GHz performance. The Intel 4th Gen processors provide low-power processor options from 25W to 47W. OEMs will find the device ideal for high-performance, low-power, low-heat and mobile workstations. All versions of the MB-80560 have integrated graphics support. Display support includes DVI-D and VGA with optional DP support (via pin header). Win Enterprises, North Andover, MA (978) 688-2000.

RTC Magazine AUGUST 2014 | 49

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Company Page Website Access I/O Products, Inc................................................................................................................ 39......................................................................................................................................... Advanced Micro Devices, Inc...................................................................................................... 52............................................................................................................ Cadia................................... congatec, Inc...........................................................................................................................................4, Creative Electronic Systems......................................................................................................... 27................................................................................................................................................ Dolphin Interconnect DVCON.......................................................................................................................................................... Lauterbach Development Men Micro, Inc.......................................................................................................................................... 17........................................................................................................................... MSC Embedded, Inc.............................................................................................................................4................................................................................................................ One Stop Systems, Inc....................................................................................................................7, Pentek............................................. Real-Time & Embedded Computing Trenton Systems......................................................................................................................................2.............................................................................................................. TQ Systems Product Showcase.................................................................................................................................21.............................................................................................................................................................................. WDL Systems.....................

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Thinking about how to take advantage of “The Cloud” in your Embedded Application?

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AMD Innovation Continues Introducing the 2nd Generation AMD Embedded R-Series APU

The 2nd generation AMD Embedded R-series APU (previously codenamed “Bald Eagle”) delivers breakthrough graphics performance and power efficiency for a new generation of embedded systems designed to provide ultra-immersive HD multimedia experiences and parallel processing compute performance. The AMD R-series APU offers next-generation performance-per-watt compute efficiency in the x86 product category by allowing system designers to take advantage of Heterogeneous System Architecture (HSA). AMD’s 2nd generation AMD Embedded R-series APU is a revolutionary leap in processing performance, power efficiency and multimedia immersion for embedded gaming, medical imaging and digital signage applications.

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