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The magazine of record for the embedded computing industry

December 2013

CompactPCI Serial: Mating Legacy with Faster System Interconnect

WiGig Boosts Wi-Fi for a Faster Wireless World Open Hardware Speeds the Design Process An RTC Group Publication

OpenCL for FPGAs— Part 2

CompactPCI Serial:

Mating Legacy with Faster System Interconnect

43 Mini-ITX Motherboard with Fourth Generation Core Processors



Rugged Switch Solutions Lower Cost of Gigabit Ethernet in SWaP-Optimized Packages


High-Speed, Multichannel LVDS Recorders for R&D, Ground, Ship & Airborne Applications



6Editorial It’s Not Your Father’s 8-Bit Microcontroller Any More Insider 8Industry Latest Developments in the Embedded Marketplace

10 & Technology 40Products Newest Embedded Technology Used by Industry Leaders Small Form Factor Forum Happy Holidays from SF3

EDITOR’S REPORT The Advent of Commercial SoCs

SoCs Take on the 12 Microcontroller Duty of In-Depth Software Support



CompactPCI Serial

Open Hardware Speeds Design Activity


CompactPCI Serial Leverages Legacy Architecture to Meet Current High-Speed Demands Barbara Schmitz, MEN Micro

Serial Allows Easy and Flexible Implementation 18 CompactPCI of Faster Point-to-Point Communication Systems Sandra Korsinek, Kontron


Connects with Wi-Fi to 24 WiGig Shape the Wireless World Tom Williams

Tom Williams

Hardware Platforms 28Open Promise Faster, Lower-Cost and Successful Designs David Anders, Circuitco

TECHNOLOGY DEVELOPMENT Optimizing Power and Performance

Power Management 32Advanced Brings Improved Performance to Highly Integrated x86 Processors Ben Boehman, AMD

INDUSTRY WATCH Developing Code for Hybrid Architectures FPGAs to the (Relative) 36Bringing Masses—OpenCL for FPGA Part 2 Ron Huizen, Bittware

Digital Subscriptions Available at

Cover: The CPS3003-SA CompactPCI Serial SBC from Kontron (left) and the F22P CompactPCI PlusIO CPU from MEN Micro (right) RTC MAGAZINE DECEMBER 2013


DECEMBER 2013 Publisher PRESIDENT John Reardon,


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Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2, Scotts Valley, CA 95066 Phone: (831) 335-1509

ƒ OpenGL® ES 1.1/2.0, OpenVG™


Untitled-3 1

To Contact RTC magazine:

8/14/13 2:16 PM

Published by The RTC Group Copyright 2013, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


It’s Not Your Father’s 8-Bit Microcontroller Any More


hose of us who came into what is now called the embedded computer industry oh so many years ago, initially became accustomed to think of an embedded controller as a relatively small device with a fairly singular dedicated purpose. Little modules buried in machines and making them hum. How rapidly and profoundly that has changed. The urge arose to embed machine intelligence into practically everything large, small and in-between and it is still happening. I am reminded of the old Monty Python skit about the Society for Placing Things on Top of Other Things where the officer comes into the meeting and notes, puffing unctuously on his pipe, that on the way there he noticed quite a number of things that were not on top of other things and that this was not acceptable. Well today we literally have vacuum cleaners that run Linux, but there are still quite a number of things . . . They are not little things either, and the intelligence that resides in them is no longer dedicated to a single purpose. We have entered the age of highperformance embedded computing. That sounds all very nice, but what is it really? First of all, it challenges the assumption that there might be more computing power available in a given processor or system than anyone might really want to embed somewhere. There is no end of large, complex, connected and vital systems, machines, vehicles, industrial operations, medical devices and more that can benefit from ever more embedded computing power. Serving those needs is limited only by the ability to cram ever more performance into ever smaller and lower power packages and harness it with software applications and connectivity. This is the result of the ever ongoing progress of Moore’s Law— the inexorable progress of ever-increasing density of integration on silicon. The world of embedded is moving from what was systems based on modules or boards, to one based on systems-on-chip. Of course, those systems-on-chip can also be placed on boards and modules that can in turn be integrated into even larger systems. And so it goes. At the same time, what we once tended to think of at the mention of the term “SoC” is undergoing a change as well. Once, it seems, SoC seemed at least partially synonymous with ASIC. That is, a highly integrated silicon device that included a CPU core and a selected mix of on-chip peripherals and memory, which was able



Tom Williams Editor-in-Chief

to execute code from off- or on-chip memory, operate its own I/O and pretty much act as a stand-alone embedded computer. These devices, however, were usually not general-purpose but, due to limited silicon area and the use of a specific selection of on-chip functionality, were targeted at a specific application. Thus the close association with ASIC. Both SoCs and ASICs required high volumes to justify the expense of development, the fabrication and the risk of errors that could force a re-spin of the design. Now thanks to Moore’s Law, that is changing too. It is now possible to integrate all kinds of things onto a single silicon die, many of which would have been difficult to imagine fitting onto a reasonably sized circuit board not so long ago. So now we see devices appearing that have a 32-bit core with cache and flash memory, with on-chip DRAM, with a host of peripherals, network controllers, high-speed interfaces such as USB, large amounts of digital I/O, graphics accelerators, A/D converters and more. These are connected to high-speed internal buses, and sometimes there are even small embedded microcontrollers whose sole purpose is to manage the power consumption among so many on-chip functions. And these devices are certainly not ASICs; they are commercial, mass-produced parts offered for general sale, albeit usually in families with a choice of variants. Now the OEM gets an interesting choice. Where once a single-chip solution might have seemed out of the question due to the volume/cost issue, one of these devices could look very attractive from a cost, size and power perspective even if the target design didn’t use 30 percent of the on-chip functions. At that price, who cares? And especially since the semiconductor vendors who are starting to roll out such devices must, must, must supply the underlying software infrastructure of RTOS, drivers and libraries, which are as complex and varied as the on-chip silicon, the OEM can feel doubly blessed. Here is a cost-effective single-chip solution with a platform interface that lets him quickly start at the point of value added for a target product. Of course, that is not the only choice for the OEM. The choices are just bigger and more attractive for getting ever more and higher computing power into smaller spaces for greater connected intelligence from the smallest parts of the Internet of Things to the Cloud. Because, as I’m sure we have all noticed, there are still quite a number of things. . .

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INSIDER DECEMBER 2013 OEM Market Makes up over 85% of Global Automotive Electronics Automotive Electronics are increasingly utilized in today’s automobiles. Beginning with the requirement of providing enhanced engine control, the current breed of automobiles has become more and more reliant on electronics, enabling them to go faster, even while providing the highest levels of safety. According to a report from Research and Markets, today’s contemporary cars have evolved into electronic machines, with more and more operations being controlled with electronic control units (ECUs). For instance, a premium segment car can comprise up to 150 such ECUs for controlling virtually all vehicle-related aspects. These can include an engine control unit for managing a car’s efficiency, a steering and surround view system for preventing accidents, a telematic system offering information related to local hot spots, an electronic stability/traction control for maintaining appropriate steering control, and sensors for deploying airbags in the event of a collision. The global market for Automotive Electronics, estimated at $191.3 billion in 2013 and forecast to be $204.6 billion in 2014, is further projected to reach $314.4 billion by 2020, thereby maintaining a CAGR of 7.3% between 2012 and 2020. OEM Automotive Electronics, accounting for an estimated share of 86.3% in 2013 equating to $165.2 billion in the overall Automotive Electronics market, is forecast at $177.2 billion in 2014 and expected to register a 2012-2020 CAGR of 7.6% in reaching a projected $277.1 billion by 2020.

ARM-Based Telecom to Attack the Cloud— Virtualized Everything and Software Defined Everything

With the advent of 64-bit versions of the ARM architecture, the idea that seems to connect ARM to smaller, mobile and embedded devices is being revised as it is attracting serious attention in the server space. Dell, for example, has demonstrated design aimed at precisely that arena, and the newer processors are moving into areas of the Cloud by virtue of their power to performance ratio. Now MontaVista has announced support for the game-changing ARMv8 architecture. Carrier Grade Edition (CGE) 7 Linux now also includes advanced virtualization features to enable seamless hardware acceleration for the performancesensitive Software Defined Network (SDN) and Network Function Virtualization (NFV) market. MontaVista software solutions are deployed by leading Telecom Equipment Manufacturers (TEMs) that are building next generation routers, switches, security and application gateways,



and 3G, 4G/LTE equipment for service providers and enterprise. The exponential rise of connected devices is adding tremendous demands on network infrastructure. Service providers are looking to TEMs to provide dynamic and scalable systems that will address the changing demands of the market. Advanced system-on-chip (SoC) virtualization with seamless application layer support of network acceleration hardware is key for the performance-based SDN architecture and NFV-enabled systems of tomorrow. “Deterministic and scalable CGE Linux is a critical component to virtualizing the converged compute, network and storage solutions. Highly optimized clouds for the telecom market will require advanced virtualization support across multiple architectures with transparent support for hardware-based network acceleration. Only MontaVista offers seamless, tightly coupled hardware abstraction with advanced virtualization across multiple processor platforms,” said Sanjay Raina, president of MontaVista Software.

IAR Program Targets Entrepreneurial Organizations Focusing on Green Technology

Many of the most innovative advances in renewable energy and clean-tech fields over the past twenty years have been developed by small, entrepreneurial technology companies and individuals. To support and further this progress, IAR Systems has created the IAR Green Innovation Program to allow engineers easier access to world-leading embedded development tools including the powerful C/C++ compiler and debugger tool suite IAR Embedded Workbench and the highly sophisticated state machine tools IAR visualSTATE. By significantly enhancing development productivity, IAR Systems’ development tools help green entrepreneurs bring their ideas from prototype to commercialization stages and provide a reliable path to high volume deployment. The program will award selected companies with up to $25,000 worth of IAR Embedded Workbench or IAR visualSTATE licenses for the duration of the project.

To be selected as a member of the program, the applying organization should be in the areas of environmental monitoring, renewable and clean energy systems, systems that optimize energy efficiency, recycling, climate-related disaster recovery, and green quality of life improvements for people in developing and third-world countries. The organization could be a research center, a university program, or a startup company with 10 or fewer employees. Program information is available at “For 30 years, IAR Systems has contributed to future-proof development projects around the world by continuously delivering world-leading development tools with the broadest architecture support to the market,” says Mike Skrtic, responsible for IAR Green Innovation Program and Strategic Account Manager, IAR Systems. “IAR Green Innovation Program is one step further to take responsibility for the future and to encourage developers who lead the way towards a more sustainable planet.”

ViaSat and Green Hills Software Team to Deliver Secure Android Smartphone

Green Hills Software and ViaSat have announced an agreement to deliver military-grade security for Android smartphones and tablets. The Integrity Multivisor separation-kernel has been selected as the hypervisor solution for the ViaSat Secured, a mobile enterprise system that addresses the stringent security, privacy, manageability and usability demands for dual-use—personal and business—smartphones and tablets. ViaSat Secured offers a carrier-agnostic suite of the latest and most popular mobile devices so that users may switch between personal and corporate use.

ViaSat Secured devices are preprogrammed with Green Hills Software’s Integrity Multivisor, a foundational firmware layer of data protection and isolation below the mobile operating system, which enables either a secure single or dual persona solution that cannot be achieved with container-based offerings. ViaSat Secured devices are managed with ViaSat network management, which includes firmwareover-the-air update (FOTA) and enterprise policy management services, as well as an open application programming interface (API) for integrating with popular enterprise Mobile Device Management (MDM) products. Whether devices are corporate or personally liable, the use of the secure dual persona and enterprise management technology is designed to give consumers complete confidence in the privacy of their photos, contacts, email and other information while enterprise and government IT administrators manage the device’s business persona with assurance in the security of enterprise data both within the device and across the corporate network. This solution represents a broad collaboration, not only between ViaSat and Green Hills Software, but also across multiple worldwide mobile network operators and major mobile device OEMs.

Health Care Major Driver of Global Image Sensor Market

Image sensors have been present since the advent of digital cameras and image reproducing devices. Since the early 1990s, image sensors have evolved from a simple single array CCD to complex 3D array digital SLR image sensors. Apart from cameras, image sensors are experiencing a heavy adoption in applications such as security and surveillance, automobile drive

assistance and machine vision. All these applications are driven by the demand for a system and process automation. The healthcare segment is also identified as one of the major industry vertical markets for image sensors. Image sensors assist in endoscopy, dentistry, oncology, X-rays and microscopy. A new report from Research and Markets looks at the image sensor market by technology, applications and geography. The research conducted suggests that the healthcare devices are the major drivers of the enterprise image sensor market. The introduction of low-cost CMOS resulted in the emergence of the integrated camera market. These miniature cameras are integrated into multimedia devices such as mobile phones, tablets, PDAs and notebooks. This segment of the image sensor is a high-volume segment as identified from the research findings. The report forecasts the volume as well as the value-based market for the image sensors used for consumer applications. The total image sensors market is also segmented according to various technologies and capabilities that the sensors exhibit. The report includes quantitative data analysis for the sensor types such as CCD, CMOS, Hybrid and CID. The demand for X-ray receivers and infrared cameras has given rise to various image sensors operating at different wave lengths. Three types of image sensors are included for analysis: visible, infrared and X-ray. The total market is also divided by substrate type (Silicon and Indium Phosphide), array type (linear, 2D, and 3D) and by formats (VGA and PAL). The division and analysis of the market by sensor types and technologies gives an indepth understanding of emerging sensor types, flagship sensor types and declining sensor types.

eSOL Seeks ISO 26262 Automotive Safety Standard Certification for RTOS and IDE

eSOL, a developer of realtime embedded software solutions, has announced that it is seeking ISO 26262 automotive functional safety standard certification for its eT-Kernel real-time OS (RTOS) and its eBinder IDE. eSOL hopes to offer its eT-Kernel Platform Automotive Safety Package to users of the eT-Kernel Platform in the second quarter of 2014—as soon as the third-party certifier determines that eSOL’s RTOS and IDE meet Automotive Safety Integrity Level (ASIL) B requirements. The eT-Kernel Platform, which contains the eTKernel and eBinder IDE, serves as the basis for the eT-Kernel Platform Automotive Safety Package. eSOL’s eT-Kernel Platform Automotive Safety Package consists of documents including safety manuals and reports that will substantially reduce costs for car manufacturers and automotive device suppliers obtaining ISO 26262 certification for products such as Advanced Driver Assistance Systems (ADAS). eT-Kernel RTOS features high reliability and fast real-time capability. Thanks to its scalable architecture, the multi-profiled eT-Kernel is compliant with POSIX, uITRON and T-Kernel. Its tightly integrated eBinder IDE, designed specifically for developing RTOS-based software, ensures efficient development with high-quality results. The eTKernel Platform, already used in many in-vehicle automotive infotainment systems, will allow developers to meet ISO 26262 auto safety requirements for their automotive systems while securing proven reliability and real-time capability.

STMicroelectronics and Memoir Combine Memory and Semiconductor Process Technologies

STMicroelectronics has announced its close collaboration with Memoir Systems, which has made its Algorithmic Memory Technology available for embedded memories in application-specific integrated circuits (ASICs) and Systems on Chips (SoCs) manufactured in ST’s fully depleted silicon-on-insulator (FDSOI) process technology. When integrated into products made using ST’s FD-SOI, Memoir’s Algorithmic Memories deliver uncompromised performance as a result of FD-SOI’s recognized power and performance advantages. Moreover, combining FD-SOI’s extremely low Soft Error Rate and ultra-low leakage currents creates a uniquely compelling value proposition for mission-critical applications, including networking, transportation, medical and aerospace programs. “On its own, FD-SOI process technology produces ASICs and SoCs that run faster and cooler than devices built from alternative process technologies,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics. “In adding outstanding third-party intellectual property from Memoir Systems, we are making FD-SOI even more appealing and demonstrating how simple porting is.”




FORUM Colin McCracken

Happy Holidays from SF3


was the night before shipping, the deadline was near Not a creature was stirring but one engineer His systems were staged in burn-in with care In hopes that a serial console prompt soon would appear Small form factors were nestled all snug in their racks While delusions of interoperability pervaded each stack Ops started the bake and then left for the night While the engineer settled down to consider his plight When out on the floor there arose such a clatter He sprang from his bench to see what was the matter Away to the chamber he flew with his flash Checking for failures, he re-booted the batch The glossy datasheets on the engineer’s bench Hinted at plug-and-play with the modules entrenched When what to his wondering eyes should appear But an LPC super I/O and eight COM-port gear With a Win32 driver, migration was quick He knew in a moment to use a USB stick More rabid than squirrels his vendors once came Selling I/O he had purchased by name: Now, ARINC! Now, PATA! Now, DO-160! On, COM ports! On, 1553! On A-to-D! On top of each stack, screwed to the wall A thermal solution that’s excessively tall As wide temp now dictates a heat transfer plate Both to a COM module and enclosure must mate So up like a smokestack, the modules they grew With a tray full of cables and pin/socket connectors too! He scratched his head and was turning around When the custom BIOS re-flashed with a bound He stressed out while awaiting re-boot His 5-vendor COMe RFQ had become moot A bundle of cables he had flung on his back And he looked like a peddler just opening his pack He thought back on how he got into this mess The “legacy-free” mantra pushed by COM Express The promise of inter-op’rability



With the carrier design guide from the PIC-M-G The words of his boss were doomed to repeat “Your stacking approach is way obsolete The size, weight, and power budget must shrink.” The consultant appeared before he could blink His eyes—how they twinkled! His design skills—how merry! His schematics like roses, his layout a cherry A wink of his eye and a twist of his head The consultant said we had nothing to dread He spoke not a word but went straight to his work And redesigned the baseboard; then turned with a jerk “In COM Ex Type III, IDE is not there This pinout type uses a differential pair…” He dipped into his bag of proven design tricks Then pulled out a heat spreader plate for x86 He spun the design, a right jolly old elf Now smaller than the stack built commercial off-the-shelf As he sprang to his sleigh, the consultant gave a whistle And away he flew like the down of a thistle Leaving behind our poor engineer To debug the pilot ’fore the end of the year Integration had our friend jumping through hoops Of the finest standards from many trade groups And then in a twinkling he heard in his head A voice reminder of an SF3 column he’d read About ISA vampires and legacy I/O The LPC COM ports need BIOS initialization to flow He plugged his flash drive into each system’s port With new firmware, the serial ports didn’t abort The characters were displayed through console redirection And he restarted the burn-in after one last inspection Then our hero exclaimed ere he drove out of sight “Happy troubleshooting to all during many a long night!”

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EDITOR’S REPORT The Advent of Commercial SoCs

Microcontroller SoCs Take on the Duty of In-Depth Software Support

risk of costly errors. There have also been some interesting efforts to make microcontrollers configurable as in the case of the Programmable SoC or PSoC from Cypress Semiconductor, which started with an 8051 core and added an area where developers could configure a custom mix of peripherals. This has expanded into ARM-based 32-bit designs and has been followed by efforts from other vendors such as Xilinx, Altera and Microsemi to mate multicore CPU architectures on the same die with a rich FPGA fabric. All of these directions have definite promise and all also run up against the issues of increasing software complexity. For 8-bit parts the software issues were relatively simple. You chose an RTOS and then wrote application code that would include drivers for the on-chip peripheral mix. If the OEM product line included designs that used several variants, there was an issue managing the corresponding software versions, but it was certainly not insurmountable. Today, however, the rapidly increasing scale of silicon

Today’s 32-bit microcontrollers have integrated so many on-chip peripherals, functionality and interconnects that they require very large amounts of software components that can all work together just to get customers up and running. by Tom Williams, Editor-in-Chief


onsider the humble microcontroller. From its early 8-bit origins in the late 1970s, through workhorse 16-bit versions and today appearing in powerful 32-bit incarnations, the microcontroller unites CPU architecture with selected on-chip peripherals and functions targeted for control tasks in a very wide range of applications. The problem has been that the range of applications is so wide and varied that it takes a huge combination of peripherals and functions to meet the exact demands of a specific control application. Traditionally, the die space available has been inadequate to accommodate the full range and mix of such on one device. This has, on one hand, led to a situation where there are catalogs full of variants based around a common CPU architecture like that of the famous Intel 8051. On the other hand, of course, is the option of an ASIC/SoC design, which requires huge volumes in order to justify the expense of development, fabrication and the



MIPS32 microAptiv Core • •

200 MHz, 5 Stage Pipeline 32-bit CPU + DSP Trace ETAG

Inst. Cache

Data Cache


DMA 8 Ch.

Crypto Engine


High Speed USB

CAN 2.0b (2)

Ethernet MAC

2 Ch. DMA

2 Ch. DMA

8 Ch. DMA

4 Ch. DMA

2 Ch. DMA


HIGH-SPEED BUS MATRIX 2 MB Flash Prefetch Dual Panel Live Update




12-Bit ADC PMP Comparator (2) 28 Msps, 4-Wire Debug 6 S/E



Output Compare PWM (9)

Timer (9) IC (9)

I2C (5) I2S/SPI (6)


FIGURE 1 The Microchip PIC32mz family is based on the 32-bit MIPS microAptiv core with an added DSP engine. It includes two internal buses and a wide variety of on-chip peripherals, devices and interfaces, all of which require software support.


FIGURE 2 The multimedia expansion board attaches to the Starter Kit CPU board and supports Wi-Fi, Bluetooth, capacitive touch graphics interface, stereo audio and a 3-axis accelerometer.

integration is resulting in new generations of microcontrollers that incorporate large numbers and a wide variety of on-chip peripherals, buses, interfaces, coprocessing units and functions. The software complexity that arises from this can be truly daunting, forcing semiconductor vendors to directly address it. One example is a new family of 32bit microcontrollers being rolled out by Microchip Technology, the PIC32MZ family. While introducing new and advanced lines of microcontrollers is nothing new for Microchip, the PIC32MZ line signals levels of integration that require several decisions. One is more philosophical in that it appears that a device with this much on-chip functionality moves from being referred to as a microcontroller to being considered a true system on chip. In other words, the level of device integration that was once needed for something to be called an SoC is now available as a commercial product (Figure 1). The family is based on the 32-bit MIPS32 microAptiv core, which Microchip licensed from MIPS Technologies. The core is specifically designed to optimize the balance between code with both 16- and 32-bit instructions resulting in an average reduction in code density of 30 percent when using mixed instruction

sets. The 200 MHz five-stage processor performs at a rate of 330 Dhrystone MIPS and includes a DSP engine with 159 new DSP instructions. In addition to on-chip cache are also 512 Kbytes of SRAM for such things as handling multiple protocol stacks, audio buffering and frame buffering for graphic displays. The 2 Mbyte on-chip flash memory is in a dual-panel configuration so that one half can be written to for updates while the processor is running, thus allowing live updates without powering down. Microchip is also characterizing the PIC32MZ line, which at introduction consists of 24 variants, as either cryptoenabled or non-crypto-enabled. The cypto engine can be selectively programmed for desired tasks such as secure boot. Eight family members are equipped with an onchip crypto engine that offloads the core to provide encryption for secure connections. Part of the reason for this distinction, of course, is that the crypto-enabled devices are subject to export restrictions.

On-chip connectivity includes a high-speed bus matrix for communication among on-chip elements such as the SRAM, flash, 10/100 Ethernet MAC, dual CAN controller, USB 2.0 and a 12-bit 48 MS/s ADC that supplies up to 48 channels for support of complex mixed signals. Many of these elements are equipped with DMA for accelerated throughput. The onchip peripheral buses support timers, I2C, SPI and others. It becomes pretty clear from this list of features that this is a system on chip. One reason we can call it an SoC is simply that ten years ago there was no way you could have gotten all this stuff on a single piece of silicon. And this is not an isolated phenomenon. The recently introduced Intel Bay Trail is an Atom-based SoC as well. Given the richness of onchip devices, the developer now gets to consider—even though there may be quite a number of functions on the device that he will not use for his specific application—whether selecting such a device can

APPLICATION LAYER • Implements the overall desired behavior • No direct HW access enables easy porting across Microchip parts

COMMON SYSTEM SERVICES • Manages shared resource modules to avoid conflicts • Provides common functionality to avoid duplication



• Implements complex libraries & protocols (USB, TCP/IP, Graphics, etc.) • Provides highly abstracted application program interface

DEVICE DRIVERS • Provides simple & abstracted interface to peripheral • Manages peripheral access control to avoid conflicts









PERIPHERAL LIBRARIES (PLIB) • Access library that provides low-level direct access to a peripheral • Provides common functional interface for PIC32 cross-family compatibility











FIGURE 3 The MPLAB Harmony software framework includes a host of interactive tested components including specific device libraries, device drivers, middleware and a selection of tested RTOSs. Microchip serves as the first line of support for all components.



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be justified in terms of cost and time-tomarket.

The Software Shadow of the SoC

Did we just mention “time-to-market?” Well there simply is no such thing as time-to-market if the engineers have to sit down and adapt an RTOS, write drivers and middleware, then test everything to make sure the components work together. It is even too much to ask that these be procured from independent vendors and then integrated and tested. And this would have to be done for each variant and probably for each design project. In the past, Microchip has been very good about supplying a dedicated integrated development environment (IDE) for all of its products from 8-bit on up. Called MPLAB X, the complementary suite provides compilers, debuggers, simulators, code navigation tools emulators and a whole host of development tools for the entire line of microcontrollers—even those we are calling here “SoCs.” In addition, Microchip also supplies starter kits in the form of singleboard modules with the processor and debugger support. The starter kit for the PIC32MZ—with crypto and non-crypto versions available—connects with the host system via a USB cable and has an interface for connecting application-specific expansion boards. Then all the tools in the MPLAB X IDE can be used from a Windows-based PC to develop on the actual target device. In the case of the PIC32MZ, Microchip is also providing a multimedia expansion board that works with the starter kit (Figure 2). It includes an LCD display and a VGA camera, 24-bit stereo audio and even a 3-axis accelerometer plus WiFi and Bluetooth wireless capability. This recognizes that the SoC family’s target markets include, in addition to the traditional areas like factory and building automation and transportation, consumer audio, automotive and home automation. All of the latter come with user expectations that assume a rich graphical user interface. For such a complex device, however, even the richest set of development tools does not solve the issue of the need for enough underlying software support to al-

low the developer to quickly begin focusing on his or her value ad, which is the actual application, without first getting all the underlying operating system, driver and middleware software running reliably. To address this, Microchip has introduced a major additional software offering called MPLAB Harmony, which operates with MPLAB X and comes mostly complementary with the purchase of the processors (Figure 3). The key concepts for Harmony are “compatible, interoperable, reusable, modular and tested.” Thus, several thirdparty RTOSs including Micrium RTOS and Express Logic’s ThreadX are brought in and certified to work with the hardware as well as with the other software components (drivers, middleware, etc.) supplied by Microchip. They must then be certain to communicate and work in all combinations of functionality supported on each device variant. At the same time, although several vendors are also available for support, Microchip makes itself the first line of support for all Harmony components. What is important to note here as an indicator of industry direction, is the amount of resources that must be devoted to supporting something as complex as a family of SoCs with the needed software components. This cannot be offered as an option or an add-on but as an integral part of the product. The stakes have definitely been raised for semiconductor vendors who now must take on the role of software suppliers in order to offer platforms on which developers and OEMs can begin adding value. Microchip Technology Chandler, AZ (480) 792-7200

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CONTEXT CompactPCI Serial

CompactPCI Serial Leverages Legacy Architecture to Meet Current High-Speed Demands While CompactPCI Serial sets a new stage for system processing into the future, it gets its roots from the original CompactPCI specification that held its own for more than 20 years. by Barbara Schmitz, MEN Micro











IEC-61076-4-101 2-mm CONNECTORS

PICMG 2.16


PICMG 2.20



PICMG 2.30





ith a few years and several new product developments under its belt, CompactPCI Serial continues to prove itself as a significant step forward for embedded computing platforms, especially as high-speed data requirements continue to increase. Of course, there is also CompactPCI PlusIO, which bridges the gap between the original spec and the new, updated one. Together, these three form PICMG’s family of CompactPCI specifications (Figure 1). Collectively, what this family of specifications does, in fact, is protect those two decades of technology investments by providing a migration path from legacy CompactPCI systems to high-speed serial-based ones. Most of this is already known by the industry, so it seemed appropriate to highlight some information about CompactPCI Serial that may not be widely understood. CompactPCI Serial defines the same two standard board sizes as CompactPCI: single and double Eurocards. The smaller format (100 mm x 160 mm 3U) is particularly suited for compact and mobile applications. In the fields of servers, telecommunications and measurement, larger card formats (233 mm x 160 mm 6U) may even be an advantage, since the electronic components need more space and can draw more power.

FIGURE 1 CompactPCI Serial was developed with a clear path toward the future, while ensuring backward compatibility with legacy CompactPCI systems.

Compatibility of Formats

The two formats are also electrically and mechanically compatible. This means that you can insert 3U boards into 6U systems without restrictions. The connector types and even the pin assignment

are identical. The only difference is that for 6U boards, an optional connector (P0) was added on CompactPCI Serial to beef up the power supply and to provide additional Ethernet channels as an infrastructure bus for server applications. However,


FIGURE 2 The specially designed CompactPCI Serial connector significantly increases reliability with its rugged housing and enhanced thermal management properties.

3U boards with CompactPCI Serial are not inserted at the bottom as they are for CompactPCI, but at the top, as was the case for the older VMEbus standard. There are two reasons for this. In terms of power, it is necessary to enhance the power supply for 6U boards. 3U boards are supplied via the P1 connector. For 6U, this connector needs to be extended. Also, for EMC reasons and to avoid influencing data transfer on the serial interconnects, the power supply connections have as large a distance as possible to the critical signal paths. It is only logical to place the additional P0 connector directly next to P1, i.e. below P1. This makes the board grow toward the bottom. It is important to note that P0 is the only electrical extension of 6U boards compared to 3U boards. All features of CompactPCI Serial such as eight PCI Express links, eight full-mesh Ethernet, eight SATA and eight USB interfaces are available in 3U systems just as in 6U systems. The build-up of hybrid boards simply calls for this top to bottom arrangement in CompactPCI Serial. The upper area of a 6U board accommodates the new AirMax connectors, while the lower area uses the common 2 mm connectors of CompactPCI in their standard positions.

Power Dissipation and Power Supply

While power dissipation from 12V is limited to 60W for 3U boards, 150W are permitted for 6U—sufficient even to supply power-hungry server chipsets. The 150W is also the physical limit for aircooling of boards that fill up a 19” rack by 4 HP each. Consequently, a 19” enclosure

with 20 6U slots could generate a theoretical thermal output of 3000W. The new AirMax connectors, developed specifically for CompactPCI Serial, do not have special power supply pins. Voltage is supplied using standard connectors suited for signal transmission. The connectors withstand a current load of 1A per pin at 85°C. The mechanical design of the connectors has the contacts placed individually, without thermal coupling. If one contact connection heats up more than another, the internal resistance increases, and the current finds its way over to cooler contacts. This guarantees that the load is spread equally over all contacts. The connector type chosen for P0 is identical with P1 (Figure 2). As a result, the connector has 72 contacts and could connect up to 24 differential signals. Its pins increase the 12V supply, but also the 5V standby supply. A 6U board may draw a total power of 25W from the 5V standby, which is also a concession for server chipsets. A total novelty lies in two redundant, isolated 48V power supplies. They are intended to support different telecom standards, and especially solutions such as Power-over-Ethernet (PoE). A 6U board can provide almost 100W over the backplane. This hardly has an impact on the thermal balance, because PoE supplies power for external devices and the 48V are controlled. Two rows of P0 are reserved for two additional Ethernet channels. These add to the eight defined channels to form a full-mesh network. While these channels build up the multiprocessing network of

CompactPCI Serial, the two additional channels can be used for integration into existing CompactPCI systems based on the PICMG 2.16 standard, but also for system administration. Parallel CompactPCI systems still use the IPMB, an I²C bus, to do this. However, Ethernet is increasingly becoming the standard of choice here too. Intel calls this technology Active Management Technology (AMT). This enables it to update software even when a system is switched off.

Sustainability and Compatibility

The different formats and options for signal routing show that modular industrial computer systems need flexible concepts. High demands have accompanied the development of CompactPCI Serial from the start, regarding both existing and future technologies, but also with respect to more special requirements. There is, of course, compatibility with parallel CompactPCI—PICMG 2.0—as well as compatibility between 3U and 6U boards. 6U hybrid boards act as a bridge between existing systems and the modern serial interfaces, and there are different connector arrangements for customized I/O boards. There are also backplane extensions, e.g., by additional Ethernet channels and PoE for newer technologies. CompactPCI Serial is mechanically based on the IEEE 1101 standard, the standard for 19-inch systems and Eurocards, making mezzanine modules developed for these types of boards also compatible with CompactPCI Serial. This is particularly important for backward compatibility to existing solutions. The most important types of such mezzanines are PMCs, XMCs and MModules, all of which fit on Eurocards. In general, a single Eurocard can accommodate one PMC/XMC or one M-Module, while a double Eurocard can carry two PMCs or XMCs, or four M-Modules. The electrical control of mezzanine modules based on modern serial interfaces is especially easy. For XMC modules, you only have to connect the right lines and generate the power supply locally. Of course, hot-plug support is possible too. For modules based on older, paralRTC RTCMAGAZINE MAGAZINE DECEMBER OCTOBER 2013



FIGURE 3 Harsh environments demand exceptional thermal and mechanical performance.

lel buses, you need a bridge. PCIe-to-PCI bridges for PMC modules are available as standard components. For M-Modules, you should choose FPGA-based solutions. Because of the specific CompactPCI Serial connector, the usable component space is a little bit smaller than with parallel CompactPCI and VMEbus boards. This is why for CompactPCI Serial, the P1 connector was placed at the lower edge of the 3U board, since it was the only connector necessary for peripheral boards. As this connector is only 13 mm wide, and a margin of 2.5 mm each is reserved for support rails, this leaves a width of 82 mm usable for components. A PMC/XMC module with a width of 74.5 mm comfortably fits on the board. Of course, this also goes for an M-Module with 53 mm width.



The same is basically true for double Eurocards. Since 6U boards expand 3U boards at the lower edge, connector P1 is located quite at the center of the 6U board. This has no importance for PMC/ XMC modules. Two of these modules find space on a double Eurocard. A maximum of three M-Modules are possible on a 6U board.

Individual Rear I/O for 3U and 6U

The original CompactPCI standard already provides the ability to connect I/O for peripheral slots also using the backplane. The number of free pins, however, is very limited, especially with 3U solutions. CompactPCI Serial offers the option of using close to 100 pin pairs or 200 single pins—even for 3U boards—on

connectors P2 to P5. These pins are all embedded with ground pins and are therefore shielded. For 6U boards, more than 300 pin pairs or more than 600 single connections are available. Of course, the I/O signals benefit from the excellent transmission behavior and from high signal frequencies. This allows for data rates of 12 Gbit/s and more for differential signals. In the 3U area, rear I/O combined with conduction cooling is needed for systems in harsh environments. I/O signals are normally connected exclusively via rear I/O. Conduction cooling is an effective way for systems to meet both the thermal and the mechanical requirements, for instance, for applications on aircraft, trains or agricultural machines (Figure 3).


Rear I/O in the 6U area is very im- High Customization portant for many applications. Telecom Rear I/O technology does, however, applications, for example, only allow front incorporate two major difficulties. In I/O for service purposes. The reason for common CompactPCI systems, all sigthe use of modular systems based on plug- nals must be brought from the front to the in cards is actually the extremely short backplane. The backplane’s connectors time needed to exchange boards in the route the signals onto the rear I/O adapter. case of needed service. With parallel CompactPCI, the rear Thanks to the hot-plug capability I/O and also the PCI bus signals are fixed of CompactPCI Serial, you do not even to 2 mm connectors. These are not well have to switch off the power to exchange suited to support the high bandwidth of a board. Many connections at the front, digital communication or to handle highly which would have to be removed before sensitive signals in the field of measureexchange, could completely undo this ad- ment engineering. vantage. The solution is rear I/O. This is why CompactPCI Serial comIn measurement and instrumentation pletely does without a definition of the there is yet another motivation for rear rear I/O connector, and even leaves out I/O. A board with an analog front end the backplane in this area. The individoften needs an adaptation for measuring ual connector of the front board directly values that are different for every applica- meets the corresponding connector of the tion. You can very well accommodate line rear I/O board. drivers on a tailor-made rear I/O adapter. This approach does have benefits. This leaves the front for convenient status Having nothing to do with rear I/O, the displays. backplane becomes smaller and less exLCR-F-11201 Military Ad A_LCR-F-11188 Military Ad 12/2/13 4:32 PM Page 1







pensive. As not all the slots may use rear I/O, because they do not need it, no connectors are reserved for rear I/O at all. As technology moves forward, and the world demands quicker access to more information, technologies that can transform themselves to meet the changing times will ultimately be those that succeed. By ensuring it is backward compatible with its predecessor, while incorporating advancements that will make it an asset to embedded system designers well into the future, CompactPCI Serial is ideally positioned to maintain its place on the forefront of technology innovations. MEN Micro Blue Bell, PA (215) 542-9575

Designed per MIL-STD-810, MIL-STD-901, MIL-STD-167 and MIL-STD-461 to perform in the harshest environments Conduction, convection or liquid cooled ATR enclosures in standard or custom sizes VME, VME64x, VPX and CPCI architectures to the latest VITA and PICMG specifications Backplanes – sizes 3U and 6U, various slot configurations per functionality and payload LCR’s integrated system designs are born rugged...not recycled commercial products Perfect for airborne, ground mobile and UAV applications LCR’s complete line of integrated military systems, from off-the-shelf to fully customized, are ideal for all aspects of mission-critical computing such as weapons control, navigation, intelligence, surveillance and reconnaissance. To learn more about what we can do for you and your application, contact us today.

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CONTEXT CompactPCI Serial

CompactPCI Serial Allows Easy and Flexible Implementation of Faster Point-to-Point Communication Systems For industrial OEMs, CompactPCI Serial opens up a new realm of design possibilities and high-performance applications that can capitalize on a proven standard with a healthy ecosystem enhanced with new options for high-bandwidth I/O. by Sandra Korsinek, Kontron


he industrial embedded market continues to be a booming business— keeping designers busy developing systems that increase efficiency, reliability, productivity and performance in a diverse range of applications and industries. As the embedded market grows, so too does its demand for more sophisticated technologies that include evolving and emerging network capabilities that must meet requirements for new trends such as cloud computing and mobile communications that rely on IP/Ethernet-based communications and increased bandwidth support. A prime example are today’s vision systems that are not only enabling more efficient production processes, but also providing resource tracking and asset management, along with data gathering and sharing, which are the foundation for detailed and useful analytics. According to a recent report by Markets and Markets, the global market growth for machine vision systems and components is expected to increase by 8.2 percent—to more than $5B in revenues—from 2013 to 2018. This growth potential gives industrial OEMs a big motivation to advance these designs and technologies. Applications of



FIGURE 1 The new CompactPCI Serial connector is a major enabler in improving design flexibility. Courtesy Mouser Electronics

machine vision range from automotive, electronics manufacturing, packaging and medical technology, all the way to surveillance, traffic and road safety engineering and general healthcare. These essential systems handle localization and identification, measurement and inspection tasks. For many industrial designs, CompactPCI has held a long and strong foothold in this arena because of its ability to successfully keep pace with the needs of the industry. This holds true for the lat-

est specification, CompactPCI Serial, defined by the vendor-independent PCI Industrial Computer Manufacturers Group (PICMG) in order to handle the high data throughput that characterizes vision systems and other complex industrial applications. New and faster point-to-point industrial applications are now possible with CompactPCI Serial-based platforms. These now capitalize on the fundamental change from bus-based systems to more integrated, serial communication-based systems that leverage an efficient star topology. Understanding the differences and significant new value of CompactPCI Serial offers a worthwhile competitive edge for industrial OEMs.

CompactPCI’s Successful Role in Industrial Deployments

In 1995, PICMG completed the CompactPCI industrial computer bus specification (PICMG 2.0) specifically for highend industrial-grade computer systems, which leveraged the parallel PCI bus to connect the system slot for the processor board with up to seven peripheral boards. PICMG also defined the related board and system sizes, connector and pin-outs and rear I/O capability requirements for build-


FIGURE 2 The Kontron CPS3003-SA CompactPCI Serial processor board offers a flexible solution for OEMs, who still rely on classic CompactPCI.

ing modular computer systems. Later specification versions included hot swap capabilities and system management. Designers found the robust features of the PICMG 2.0 specification especially well-suited for modular, harsh environment high-end computer systems. High reliability and enhanced shock and vibration capabilities are ensured by means of a pin-and-socket connector with card guides on both sides and by a face plate that solidly screws into the card cage that firmly holds the cards in position. In addition, cards are mounted vertically allowing for natural or forced air-flow cooling. These features have made CompactPCI the most accepted modular standard supported by a large and well-established ecosystem guaranteeing availability and assured supply. The latest PICMG CompactPCI Serial specification was adopted in 2011 as the logical evolution from the proven parallel bus to one that supports the latest point-to-point serial connections.

Leveraging CompactPCI Serial Advantages

As mentioned earlier, next-generation machine vision systems offer higher resolutions, frame rates and processing speeds that optimize quality inspection and pick and place tasks. Their complex algorithms enable real-time contour detection in 3D to create faster and more reliable form and position control on the industrial factory line. The implementation of such highly complex tasks is possible only by the usage of very powerful computer systems, including for example, multiple GigE vi-

sion cameras offering high resolutions and color depth, or today’s ultra-fast USB 3.0 cameras. New CompactPCI Serial boards are an ideal solution for these systems as they now communicate in the system via a backplane with Gigabit Ethernet, PCI Express, SATA and USB connections. To make it especially future-proof, this standard was defined to already support the latest interface versions such as USB 3.0, SATA 6 Gbit/s and PCI Express 3.0. By using these serial ports, it is now possible to transmit several gigabytes per second of data compared to a CompactPCI system with a 32-bit / 66 MHz PCI bus where the highest possible data throughput is 0.264 Gbyte/s. The serial backplane connections provide another advantage for enhanced design flexibility, allowing scalable modular system solutions that can be extended if required at any time. For example, it is possible to initially implement systems with a single processor board and later add several boards that work in parallel. As a result, new flexible and more powerful system configurations are possible with CompactPCI Serial. Enabling these advantages is a completely new connector that delivers higher signal density and supports faster transmission frequencies in the latest point-topoint connections such as PCI Express, SATA, Ethernet and USB (Figure 1). The specification replaces the 2 mm hard-metric connectors with higher-density connectors capable of delivering transmission frequencies of 12 Gbit/s that also provides the needed shielding and impedance control. A single connector hosts from 72 up to 96 pins, and a single 3U board can host up to six connectors that together deliver

600 pins or 184 differential pin pairs for building various communication paths to the backplane.A further advantage with the connector is that it gives the headroom required to support future increases in data rates without the need to change the connector interface. PICMG members understood that even though these frequencies may not be needed today, the design of the connector would guarantee its applicability for the future. The new connector is essential since these connections are all available directly on chipsets and CPUs and are now prevalent in nextgeneration embedded systems. As the next-generation evolution to the successful and highly accepted CompactPCI specifications, CompactPCI Serial gives developers a powerful new platform for high-performance installations requiring massive bandwidth. Importantly, it also provides an attractive and easy migration path allowing existing CompactPCI-based deployments to more easily meet increased performance demands. Its boost in performance opens new possibilities to designers in terms of cutting-edge, high-end system configurations that offer much higher levels of performance. Further, CompactPCI Serial’s supporting infrastructure and ecosystem has grown to now support a comprehensive range of standardized and modular embedded computing resources. The CompactPCI Serial specification includes several other important advancements beyond the connector, such as a guide element on the backplane and its backward compatible features. The specification defines the system slot as the central star point for PCI Express, SATA and USB, and Ethernet, which are realized as

FIGURE 3 Using a CompactPCI Serial CPU card with a CompactPCI peripheral module lets both classic and serial modules work together.




single star or full mesh on the backplane. It is easy to see that because all interfaces are available simultaneously, performance can be considerably improved.

CompactPCI Serial in Action

Virtually any information/communication technology (ICT) application in the industrial computing market segment can benefit from the openness, longevity, modularity, robustness and reliability CompactPCI Serial delivers. These key advantages especially help applications that require high-speed serial interconnects for network, storage or PCIe data throughput. Migrating from CompactPCI to CompactPCI Serial is easily possible by adding a second backplane into the chassis—one backplane for classic CompactPCI and the second backplane for CompactPCI Serial. The only additional building block required is a bridge between CompactPCI Serial and CompactPCI. This bridge functionality can be simply implemented, e.g. as a feature of the processor board’s extension card.


Untitled-2 1



Further, new design possibilities are enabled with the presence of rear I/O and the addition of fat pipe capabilities and multiple peripheral slots. As CompactPCI Serial is compatible with the mechanical form factors defined in the IEC 1101, no changes are necessary to existing housing or cooling and systems can be reused from the standard CompactPCI platform. With a support infrastructure of available building blocks, CompactPCISerial-based system configurations are only limited by OEM ingenuity and market demand. CompactPCI Serial supports a range of expansion cards that can be connected to any one of the supported interfaces (Figure 2). Designers have the option to use the Kontron CPS3003-SA, for example, in combination with a CompactPCI extension module (Figure 3), allowing both the Serial boards as well as classic CompactPCI boards to operate together in a hybrid system. A single 3U CompactPCI Serial slot board can host up to six connectors (P1-P6). Typically, a 3U system

board is equipped with all six connectors. On the other hand, a 3U peripheral module often comes with just the mandatory P1 connector allowing connectors P2 to P5 to be specified for user-defined I/O on these peripheral cards. This solution prevents the need for any redesign or replacement so OEMs can easily continue using their existing CompactPCI boards. This flexibility helps developers realize a much wider range of high-end industrial system configurations including scalable multiple CPU implementations, control room multi-display monitoring systems, high-bandwidth wireless communications that incorporate WLAN, UMTS, or LTE parallel working radio modules, FPGA data sampling cards and graphics-based applications. Illustrated by a multiprocessing implementation, CompactPCI Serial enables this design to incorporate up to eight slave CPU boards connected to the master board via 1G, or in the future even 10G Ethernet. This configuration can use nine Intel Core i7 CPU boards to deliver up


10/9/12 2:51 PM


to 36 high-performance cores and up to 144 Gbyte of memory. Adding an external switch would enable any of these processor cores to work on any task regardless of where the data for that task is located in memory—meaning this type of system design can easily shift tasks between processors to efficiently balance workloads. CompactPCI Serial introduces a high-performance Ethernet network of up to 10G on the backplane to allow system designers to stay ahead of rising transaction and traffic loads—considering future performance requirements in advanced embedded system designs and communication networks. Currently, CPU boards are not equipped with 10G Ethernet controllers because the power consumption of these components is prohibitively high. To realize 10G communication today, CompactPCI Serial defines two slots that are connected to the system slot via PCI Express x8 links. These “fat pipe” slots are ideally suited for implementing 10G communication via 10G network controller boards. The PCI Express x8 interface even provides enough headroom to transfer the data coming from two 10G Ethernet interfaces. This solution maximizes the usage and longevity of systems and helps to reduce the end-customer’s total cost of ownership.

Standard Platforms Meet Future I/O and Bandwidth Needs

CompactPCI Serial leverages the benefits of the latest I/O technology enhancements for new high-performance installations that require massive bandwidth. It also provides a needed way to boost performance in existing CompactPCI deployments with a standards-based platform that takes advantage of huge bandwidth improvements with PCI Express (up to 8 GT/s), SATA/SAS (up to 6 Gbit/s), USB 2.0/3.0 and Ethernet up to 10 Gigabit. Supporting newer serial point-topoint interfaces, CompactPCI Serial was defined to help ease the computing evolution from bus-based systems that use dedicated peripheral components to complex, serial communication-based systems that leverage a more efficient star topology. Because SATA, USB and Ethernet com-

ponents use their own dedicated communication line, industrial end-users benefit from higher data rates without the bandwidth losses that can occur with a parallel PCI protocol. Kontron Poway, CA (888) 294-4558

Full range of CompactPCI® 19" system solutions based on Intel® and PowerPC® architectures CompactPCI® PlusIO: 100% compatible to CompactPCI® 2.0 CompactPCI® Serial: PCI Express®, Ethernet, SATA, USB on the backplane Designed for harsh environments: extended temperature range, shock, vibration, chemical resistance, humidity




CONNECTED Wireless Standards

WiGig Connects with Wi-Fi to Shape the Wireless World The promise of no wires underfoot—and many other connectivity advantages—is moving closer to reality with the continuing advancement of 60 GHz WiGig, now part of the Wi-Fi Alliance, and the growing involvement of peripheral protocols. by Tom Williams, Editor-in-Chief


t is almost certain that the vast majority of you reading this article have, at one point or another, cursed the infernal wired mess that hides behind your television, PC and other gizmos. A wirefree revolution has been quietly creeping

up on all of us and has taken a huge leap toward mainstream adoption. The development of a new high-speed wireless technology operating in the 60 GHz range now falls under the aegis of quite possibly the largest, slickest and best established


BASEBAND & LOWER MAC (802.11B / A / G / N / AC) 2.4 GHz

5 GHz

A Strong Technology with Lots of Applications


FIGURE 1 The different frequency bands and the corresponding technology (802.11 a / b / g / n / ac and 802.11ad/WiGig), with the common upper MAC layer that helps manage operating in these multiple frequency bands.



wireless organization on the planet. This is, of course, the Wi-Fi Alliance and the technology that could do away with all unnecessary cabling, WiGig of course. But will it achieve all that has been promised? An analogy might be that WiGig is currently the most talented College player in the NFL Draft; we have still yet to determine whether all that potential will be fulfilled for it to become Most Valuable Technology in the years to come.

This may seem to be bestowing the WiGig technology with a lot of credibility. This is because the organization previously responsible for its development, the WiGig Alliance, achieved a lot in just four years. It defined the specifications for the new WiGig technology and these were later used by the IEEE to define 802.11ad. It is also designed to include session transfer to Wi-Fi networks operating in 2.4 and 5 GHz (Figure 1). A second point worth noting about the design of the WiGig specification is that there are a number of Protocol Adap-


The Market Is Strong with This One

It is a simple idea. WiGig will wirelessly interconnect home entertainment and office devices, like PCs, tablets, smartphones and displays. And it will do so wirelessly thereby entirely removing the need for wires. The connectivity is adaptable and efficient and is designed to be low power using “beamforming” to target its radio beams for the best direction and performance by bouncing the signal off of the most appropriate reflector or surface at the best angle. Imagine a flashlight in your hand with walls, floor and ceiling made up of mirrors. You won’t need to “connect” your devices together or to the Internet anymore—they will always be connected and always be readily transferring data. With this in mind, who would need a laptop and a tablet? Your tablet can just connect to your display when you get to your desk! These concepts are very powerful and ABI Research believes the market is huge. It forecasts that there’ll be annual shipments of 1.8 billion devices with both WiFi and WiGig support by 2016 (Figure 2).

Now with Brawn Behind the Brains

To compound all of the strengths, the WiGig Alliance Board of Directors this year took perhaps one of the wisest


TRI-BAND 60 GHZ 11AD/WiGig, 11AC (5 GHZ) AND 11N (2.4 GHZ)

4000 3500 3000



DUAL-BAND 11N (2.4 GHZ) + 11AC (5 GHZ)



tion Layers (PALs) that allow for lots of fun and exciting things to begin happening. The wireless display extension (WDE) is designed for the transmission of ultra high definition video, and the Video Electronics Standards Association (VESA), designers of DisplayPort, are the new, yet already very successful, kids on the block with this focus. VESA now has a liaison agreement with the Wi-Fi Alliance to collaborate on development of a wireless version of their new video transmission technology over the 60 GHz airwaves. So, that means future VESA products may also use WiGig. There are also similar PALs for bus, secure digital and serial extensions (WBE/ WSE), and a lot of promise that other industry organizations will take on the challenge of transferring their technologies from a cabled to a wireless medium.

2000 1500 1000 500 0 2010









FIGURE 2 A prediction by ABI Research of the billions of WiGig units that will be shipped in the coming years.

yet greatest gambles for the success of the technology. Prior to this year, the WiGig Alliance has been in complete control of the development and promotion of the technology. A fiercely independent organization, it was small, maneuverable and quick to talk about the life-changing attributes of WiGig. While being relatively maneuverable, it did include top-level membership from some of the biggest players in the industry including chip makers and manufacturers of consumer electronics like Intel, AMD, Broadcom, Huawei, Cisco, Samsung and Qualcomm Atheros to name just a few. Wi-Fi Alliance and the Wireless Gigabit (WiGig) Alliance have now consolidated activity within the Wi-Fi Alliance. The agreement was built on more than two years of collaboration between the organizations, in which the Wi-Fi Alliance had always played a strong role in developing an interoperability certification for 60 GHz products. At the time of the unification announcement this past December to January, the then Chairman of the WiGig Alliance, Ali Sadri, commented: “We set out four years ago with the simple goal of realizing a global wireless ecosystem of interoperable, high-performance devices that would operate seamlessly. In that time there have been many challenges to overcome, but we have now created a market that simply did not previously exist. Consolidating activities with the Wi-Fi Alliance at this juncture will

ensure WiGig’s mainstream success to the benefit of technology users everywhere.” An optimistic statement, but the founder and director of the WiGig movement had a lot to be thankful for. The technology was and is now in an exceptionally strong position. According to ABI Research, WiGig was exactly what the WiFi Alliance was interested in to expand to include a 60 GHz solution. The WiGig Alliance knew that becoming a part of Wi-Fi would allow it to hang on the coattails of the most ubiquitous connectivity technology in the world. But will changing the captain of the ship steer a course toward rocks or the promised land? There seems to be quite a bit of momentum built up behind WiGig. At the recent Intel Developer Forum, both Intel and Panasonic demonstrated their latest WiGig technologies. While Intel displayed the WiGig streaming capability, Panasonic was readying their chip set for sampling in 2014. In October, Cadence Design Systems introduced a line of lowpower analog IP to support wireless technologies including WiGig. Blu Wireless has joined the 60 GHz Baseband market by successfully raising $3 million of funding. Behind the company are industry heavyweight Sir Robin Saxby, former CEO and chairman of ARM, and Glenn Collinson, founder of UK-based wireless chip company CSR. USB, perhaps the world’s most popular interface, has billions of devices in the PC market. In September, the Wi-Fi AlliRTC RTCMAGAZINE MAGAZINE DECEMBER OCTOBER 2013




Kiosk Sync & Data Exchange

INSTANT WIRELESS SYNC IP-based P2P applications Using I/O PALs Display

WIRELESS DISPLAY HD streams over HDMI or DP using A/V PALs

Distributed Peripherals

CORDLESS COMPUTING Combination of display using A/V PALs, sync and I/O using I/O PALs


NETWORKING Using native WiGig/802.11ad WI-Fi session transfer

FIGURE 3 The updated usage models image, which shows the use cases for WiGig.

ance formally transferred the WiGig Serial Extension Specification to the USB Implementers Forum (USB-IF). “The USB-IF is pleased to accept the transfer of the WiGig Serial Extension Specification from Wi-Fi Alliance, and it shares the commitment to enhance wireless connectivity with USB devices,” said Jeff Ravencraft, USB-IF president and COO. “The forthcoming Media Agnostic USB Specification will give consumers more flexibility to wirelessly connect their USB-enabled devices.” The Wi-Fi Alliance has a lot to gain by cooperating with the USB-IF.

A Wireless Future?

It seems certain that one way or another, the wire-free dream will be realized and a whole load of exciting new applications will be created along the way. The next year will be an interesting time for the fledgling WiGig technology, and there is hope that consolidation of activities in the Wi-Fi Alliance will bring greater efficiency, ensure closely harmonized connectivity and application-layer solutions using the technology, and leverage WiGig technology know-how across the range of Wi-Fi technologies. The key may be in not delaying the certification process so that we can finally start embedding certified



products in a new and even more popular generation of devices.

About the Technology – The Essentials

The WiGig specification utilizes the unlicensed 60 GHz band worldwide to provide data rates up to 7 Gbit/s. Based on the 802.11 standard, it includes native support for Wi-Fi over 60 GHz; products with triband radios will be able to transparently switch among 2.4 GHz, 5 GHz and 60 GHz networks ensuring optimal performance. The technology specifications also include PALs that define wireless implementations of A/V and I/O interfaces, facilitating advanced applications such as wireless docking, high-speed synchronization and connection to displays (Figure 3). The WiGig specification builds on the strong security mechanisms used in IEEE 802.11. WiGig uses Galois/Counter Mode, a highly efficient mode of operation that is designed to support communication speeds of 10 Gbit/s and above, provides strong encryption based on the Advanced Encryption Standard (AES), is government-recommended, and can be implemented in hardware for performance and efficiency. WiGig devices can take advantage

of a new scheduled access mode to reduce power consumption. Two devices communicating with each other via a directional link may schedule the periods during which they communicate; in between those periods, they can sleep to save power. This advanced capability allows devices to more precisely tailor their power management to their actual traffic workload, and it is especially important for cell phones and other handheld battery-powered devices. It also transfers data at far higher throughput compared with existing wireless technologies, meaning transmission duration will be less. Wi-Fi Alliance Austin, TX (512) 498-9434 VESA Newark, CA (510) 651-5122 ABI Research New York, NY (516) 624-2500



Open Hardware Speeds Design Activity

Open Hardware Platforms Promise Faster, Lower-Cost and Successful Designs The availability of advanced embedded CPUs on ready-made platforms along with software and full sets of design documents sets the stage for accelerating time-to-market and lowering costs for a wide variety of design projects. by David Anders, Circuitco


e’ve all heard those marketing buzz words and phrases like “synergy,” “paradigm shift” and “disruptive innovation.” In the tech industry, you can’t attend a meeting without hearing one. Recently a new buzz word has been added to the list—“open.” Open software has become essential and present in most technology professional’s daily work, but the term open is now beginning to be applied to hardware. The term “open hardware platform” is being used more often to talk about everything from major silicon vendors’ reference platforms to simple accessory boards for common retail products. So some of you might be wondering, what exactly is “open hardware,” what are the benefits of using it, and what does the future hold for it? All valid questions, which we hope to address here. Many of the major silicon vendors such as Intel, Texas Instruments, Samsung and AMD actively support projects that are open hardware compliant, and more are joining the game as the open hardware buzz word gains more media coverage. So what is driving this media coverage and attention? Projects such as the Arduino (Figure 1) and the BeagleBoard (Figure



FIGURE 1 The Arduino is based on the Atmel ATmega32u4 microcontroller. It contains all components needed to support the microcontroller and connects to the development system via a USB cable.

2) have been around since as far back as early 2006. These early projects were some of the first to adopt the open hardware license for their unique projects targeted at low-cost development platforms and grassroots community environments. Since then, the “Maker Movement” has continued to drive the demand for low-

cost open hardware platforms for people to “hack” on. The interesting thing is that because of the low-cost nature of these platforms, professional developers have begun to adopt them as starting points for building commercial products. An interesting side effect is that as more professional devel-


FIGURE 2 The ARM-based BeagleBone family now comes in four versions: The original BeagleBoard, the BeagleBoard-xM, the BeagleBone and the latest version, the BeagleBone Black pictured here.

opers use the low-cost platforms, more silicon vendors have noticed and have begun providing more and more support for these open hardware projects. Recently Intel has taken notice of the open hardware market and has worked to introduce the Atom-based MinnowBoard (Figure 3) as well as the Arduino-compatible Galileo board (Figure 4). As with anything, when large companies get involved, each company has begun to have their own description of what exactly constitutes an open hardware platform. Because the word open is somewhat vague as it applies to hardware, the Open Source Hardware Association has created some guidelines and definitions to assist in educating developers. Their definition includes a wide range of items that help determine if a piece of hardware is truly open, but it really boils down to two specific issues: documentation and derived works. Documentation is a key item, as all of the design files needed to recreate the piece of hardware have to be open licensed and available. This means that the schematic capture, board layout, bill of materials, Gerber files and any other data needed to create the piece of hardware are available to the general public without signing an NDA or click through license. This means anyone can recreate

the hardware from scratch. In addition to the documentation being open, the ability to create new works based on the design without having to pay royalty or license is essential. This means that the piece of hardware can be extended and evolve into commercial products. Another aspect of the open hardware definition includes some requirements

for making sure that all of the software required to make the hardware work is available. The software doesn’t have to be open source licensed. This is often the case with some hardware platforms that are based on FPGA devices. Lastly, providing attribution and credits for the original work is a major item for the definition. After all, the hardware design is basically being given away for free, and those who are doing that want to get some recognition for their work. So as a professional developer, one of the questions that often gets asked is, “How does open hardware benefit me at work?” This certainly is a good question. One of the benefits is speed. Because of the open nature of these types of hardware, the amount of time a developer needs to select a hardware design, customize it and have prototypes ready is greatly reduced. The entire development process is reduced because not only is the design “ready to go,” but it is also tested. The testing is where the community aspect of open hardware comes into play. By having literally “the world’s eyes” looking at the design, most design flaws and bugs are quickly found and fixed, rolling the changes back into the original design. As the design is often adopted for multiple uses, you also get longevity out of the product, as updates with new components

FIGURE 3 The MinnowBoard is based on the 1 GHz Intel Atom E640 with 1 Gbyte of DDR2 RAM. The CPU also has an integrated graphics media accelerator.




FIGURE 4 The new Intel Galileo is Arduino-compatible but is based on the new Intel 400 MHz Quark SoC X1000.

as well as software support are continually fed back to the original product. A further advantage is that many of the hardware designs such as the BeagleBone Black have a wide range of accessory boards—known as “Capes”—already designed to assist in developing proof of concept and testing. These accessory boards can range from simple 0.1” prototype boards to larger more complex boards such as those that integrate on board FPGAs. Once a proof of concept has been developed using the base board and various accessory boards, the design files can be taken and used to combine them into a single hardware implementation. Combining all these factors together gives a developer a solid advantage when considering the time-to-market for creating a design from scratch verses using an open hardware platform. As the idea of open hardware continues to evolve and more companies become familiar with the concept, the future and direction is expanding the horizons and possibilities. Companies like Texas Instruments have been early adopters of this type of platform, but others like Intel are beginning to see strong value in the open hardware platform, and this is driving other companies to experiment with it as well. We can expect to see almost all major silicon vendors as well as many engineering service provides begin to adopt open hardware as a business model to gain



market share. As noted earlier, quick timeto-market and high return on investment for open hardware makes it a very attractive solution. In addition, open designs are expanding from just single board computer reference designs to other products such as digital oscilloscopes, logic analyzers, JTAG debuggers and other essential hardware tools. This Maker Community continues to grow and is driving both demand and development for a wide range of both tools and reference platforms to be used with their personal projects, which ultimately lead to professional developers. There is an astounding amount of information available on the Net about open hardware. Like many other things discussed on the Internet, some of the information is good and others not so good. Understanding what open hardware is, why it is beneficial to a professional developer, and where the future of open hardware is headed, are some of the things that this article has hopefully provided some assist on, with the intention that in your next meeting you can properly interject between the usage of the other buzz words and phrases, your own statement about open hardware. Circuitco Richardson, TX (214) 466-6690

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TECHNOLOGY DEVELOPMENT Optimizing Power and Performance

Advanced Power Management Brings Improved Performance to Highly Integrated x86 Processors Complex heterogeneous processors can leave a large amount of performance headroom untapped when workloads don’t utilize all cores. Advanced power management for x86 processors allows dynamic allocation of thermal budget between cores for improved performance. by Ben Boehman, AMD


nyone with experience implementing microprocessors knows the importance of proper power management. From simple application processors to high-end server processors, the ability to down-clock, clock-gate, power-off or otherwise disable unused or underused hardware blocks is key to limiting power consumption. Motivations may range from energy savings in data centers to battery life improvements for mobile devices, but reducing power and increasing efficiency is always welcome. This capability has become increasingly important as processors integrate more, varied functional blocks. Typical x86 processors widely used in both consumer and embedded applications are a perfect example: Integration of network and security engines, memory controllers, graphics processing units (GPUs) and video encode/decode engines has effectively turned them into heterogeneous



compute units that excel at a wide variety of workloads. The notable thing about traditional reduction-based power management is that a particular functional block is only turned off when unused, or downclocked when higher performance is not needed by the application. What about applications that desire more performance? Shouldn’t saving power in one area allow you to utilize it in another? How to specify power usage is a big conundrum with these highly integrated processors. If the worst-case power for each individual hardware block in a heterogeneous processor were added up, the total could be several times the achievable worst-case power for the whole device. Of course, it is nearly impossible to write software that will simultaneously utilize all functional blocks to their fullest extent. Simply feeding the various compute engines and I/O ports with enough data to keep them all 100% utilized would likely

exceed the available bandwidth of internal buses. Central processing unit (CPU) cores manage data movement, and time spent there is less time spent executing higher-power instructions. Different instruction sequences can incur vastly different power usage and further complicate specifying processor power. For example, complex floatingpoint instructions burn much more power than a simple I/O data read because of the large difference in transistor logic they activate during execution. The combination of varying instruction types and utilized hardware blocks makes the actual power usage of the processor highly workloaddependent, and is why you will rarely see a “typical” power specification for this device type. Still, implementers expect a maximum power specification on which to base their design. The pragmatic approach for silicon providers is to survey real-world application software to establish a more realistic worst-case power usage and add some guard-band for safety. Both AMD and Intel use this type of methodology and specify it as thermal design power (TDP). TDP is essentially the maximum sustained power a processor can draw with “real-world” software while operating under defined temperature and voltage limits.

FIGURE 1 Integration of large GPU cores, as done in AMD R-Series APUs, increases the potential for unused power budget.









The majority of embedded x86-based systems are power-constrained in some way, such that designers often look for the best performance they can get in a given power envelope, at a price they can afford. This worst-case power limit translates directly into a performance limit for a given processor product by effectively defining the maximum operating frequency. Using TDP as a worst-case power specification instead of the cumulative per-block maximum power helps to increase that operating frequency, but it’s also based on an assumption of the software workload. Applications that utilize fewer hardware blocks, or utilize them to a lesser extent, will use less power and effectively leave performance headroom on the table. The recent move by AMD to integrate discrete-class GPUs with x86 processor cores in accelerated processing units (APUs) underscores this power management challenge. Some APUs contain a GPU that makes up more than half of the silicon die and a proportional amount of the power budget. A much larger potential for underutilization of the APU’s power envelope exists in this scenario if the software workload is highly CPU-centric or GPU-centric. The trend toward integration of these complex, heterogeneous cores is likely to continue and necessitates a means of harnessing the excess thermal headroom (Figure 1). AMD Turbo CORE technology— which is available only on AMD R-Series APUs—and Intel’s Turbo Boost technology came onto the scene a few years ago to address underutilized TDP headroom. Both use similar concepts, but I’ll examine the former, as it has recently been updated. AMD Turbo CORE began with a simple core-counting mechanism that allowed some CPU cores to use higherfrequency “boost” states while other CPU cores were idle. This approach only affected the CPU cores, and was primarily targeted at accelerating single-threaded applications that didn’t leverage a multicore architecture. Generational improvements have increased the granularity and effectiveness of the technology by adding more boost states for CPU and GPU cores,






FIGURE 2 Applications with a low CAC can leave unused TDP and temperature headroom. New power management techniques can exploit both for improved performance.

real-time power and temperature monitors, and enabling dynamic power budget allocation between cores. Increasing performance by boosting to higher frequencies is relatively simple since the use of multiple performance states (voltage and frequency operating points) has been around for a while. However, the complexity lies in determining when and which cores to boost. For the AMD Embedded R-Series APUs, the process starts by dividing the processor into separate thermal entities: one for each CPU core-pair and one for the GPU. I/O power is small by comparison, so it is defined as a fixed value based on characterization to reduce complexity (Figure 2). An integrated microcontroller manages AMD Turbo CORE calculations, allowing a more complex and therefore more effective algorithm. In order to decide if boosting a given core is possible,

power usage of each thermal entity must be determined. On-die analog power measurement at many amps is not practical in a 32nm SOI process, and external measurement is not possible because the various cores share power rails. Alternatively, proprietary activity monitors integrated throughout the processor architecture model current logic activity as an AC capacitance. The CAC monitors effectively profile the running application to determine if it is one of those “worst-case” workloads that defines TDP or something less laborious. Static power of the core is determined by transistor leakage at a given voltage and temperature, which can be characterized for the device and hardcoded into the algorithm as a function of temperature. A calculated temperature value from a previous iteration is used for reasons that will be explained later. Total instanRTC RTCMAGAZINE MAGAZINE DECEMBER OCTOBER 2013













M x86












Tcalc<> Tmax?









Pboost0 Pboost1 Pboost2 P0 P1 ...

FIGURE 3 AMD Turbo CORE algorithms use a variety of frequency, voltage, temperature and logic activity inputs to dynamically determine which cores need a performance boost and how much thermal headroom is available.

taneous power of the thermal entity can then be calculated by P=CAC*V2*f + Pstatic Total power for the APU equals the summation of the power for each thermal entity and the I/O power offset. The instantaneous power calculation result is compared to an allocated power budget for the thermal entity, as well as the device’s thermal design current specification to ensure that current demand does not exceed what the voltage regulator can provide. If either value is too close to the limit, firmware can impose throttling by reducing the core’s performance state. The ability to boost the performance state is maintained when headroom exists on both parameters. Even if an application with a high CAC may drive the APU to consume the full TDP, operation at this level may occur in bursts or be preceded by idle time such that the die temperature at the start of the high CAC period is far below the maximum specification. The latest version of AMD Turbo CORE also takes the opportunity to boost in this scenario by actually allowing brief excursions above TDP when there is adequate temperature headroom. After all, the purpose of a TDP limit is only to ensure die temperature stays in check. Real-time temperature values from around the thermal entity provide a scaling factor to the power calculation so that they influence the boost decision without controlling it directly.



Derivation of a calculated temperature comes from application of the calculated power to a reference thermal solution model. Reducing the influence of actual die temperature on the boost algorithm is an intentional tradeoff to increase deterministic performance of the device. The calculated temperature is then combined with temperature data from other TEs to determine if thermal headroom exists. Other thermal entities can act as heat sources or sinks, depending on their temperature state, and therefore must be considered. Temperature offsets are also included to account for sensor tolerance and to make sure that the maximum junction temperature is never exceeded. The calculated temperature is compared to predefined thresholds to determine the amount of boost that is possible (Figure 3). The final stage of AMD Turbo CORE technology is called Intelligent Boost. It uses a proprietary algorithm to improve efficiency by only allowing a core to boost if it can translate that higher frequency to increased performance. If each thermal entity control loop operated independently under a demanding workload, all cores would attempt to boost until they reach their maximum performance state or until the device thermal limit is reached. It is very unlikely that the application will be perfectly balanced, but rather limited by one core type (CPU or GPU) being saturated. Intelligent boost examines the workload at a very high frequency to give more thermal budget to the core that needs it the

most by preventing the other cores from boosting more than necessary. Efficiency is therefore maximized without affecting overall processer performance. With an understanding of how boost technologies work, designers should consider where it could affect their application or design practices. A common concern is that designers may have become accustomed to the idea that the power draw of their software application shouldn’t come close to driving a processor near its TDP, leading them to design to a lower specification. Historically, this may have been safe, but boost technologies will tend to drive the processor closer to TDP than before by allowing the active cores to consume more power. Operating closer to TDP may sound like a bad thing, but keep in mind that performance is gained with the increase in power. An example could be a machine vision application achieving higher frame rates for faster recognition. Total processor power might increase in that scenario, but it doesn’t materially increase with applications such as media playback in a digital signage player. Fixed, periodic workloads may complete faster at a higher power level, but when the burst of activity is over, cores then spend more time in lower-power idle states. So the average power is approximately the same. Applications like this can still benefit from boosted performance through better responsiveness. Some designers will dislike the idea of variable performance, especially in realtime applications, but the potential delta is


actually quite small in the AMD case. The CAC value of the application has the biggest impact on how much a core will boost, and it is very deterministic in behavior on a given processor model. Testing an application on the target processor is a simple way to determine actual performance. The temperature-based boost scalar is the only mechanism that provides variability, and it is intentionally limited to minimize its impact. While users will not see a significant performance delta across the operating temperature of the processor, any variation that does exist can be seen when operating the device near its maximum die temperature. It may also be worth pointing out that the temperature-based boost scalar described only serves to increase boost but does not gradually scale down performance if the maximum die temperature is exceeded. A separate and less granular hardware thermal control mechanism can be used to drop cores to minimum performance states in the event of an over-temperature condition. For applications that

are very sensitive to deterministic performance, the boost features can always be disabled. Moving beyond performance benefits, the ability of AMD Turbo CORE algorithms to control average power consumption of the processor has also enabled a new and interesting feature on the latest generation of AMD APUs, called configurable TDP. It essentially provides the system designer a knob to modify the processor TDP to better fit the needs of the application. A useful example might be a system design with a thermal budget for a 20W processor but vendor offerings that only include 15W and 25W options. Configurable TDP enables flexibility so the designer isnâ&#x20AC;&#x2122;t forced to choose a lower-performing 15W option in order to remain within the 20W power budget. Instead, the 25W processor might be used but configured for 20W. AMD Turbo CORE technology will dynamically provide the processorâ&#x20AC;&#x2122;s best available performance while keeping thermal dissipation under the specified amount. Support

Solid or Spin...

for configurable TDP and the level of configurability varies by processor model, but it can be a very useful feature for those that support it. System designers should keep these new concepts in mind when choosing and implementing embedded x86 processors. Power management isnâ&#x20AC;&#x2122;t just about saving power anymore. Advanced Micro Devices Sunnyvale, CA (408) 749-4000



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Developing Code for Hybrid Architectures

Bringing FPGAs to the (Relative) Masses—OpenCL for FPGA Part 2 OpenCL provides a more traditional software programming environment, opening FPGAs to a much larger potential developer base, while also shortening development cycles by allowing FPGAs to be programmed in a high level parallel programming language. by Ron Huizen, Bittware


ith their programmable hardware resources, FPGAs can be customized to a specific application and outperform central processing units (CPUs) and graphics processing units (GPUs) while using a fraction of the power. The major issue with deploying FPGAs to a broader user base is their reliance on specialized programming languages known as hardware description languages (HDLs) such as VHDL and Verilog. While strong arguments can be made for their power efficiency and performance versus general purpose CPUs and GPUs, the pushback is always the same—the skill set needed to use them is too specialized and development cycles are way too long. The first part of this article in the November issue explored how OpenCL allows FPGAs to be programmed in a Clike language, thus opening them up to a much wider base of programmers, and allowing them to be more readily deployed in places that have typically used CPUs and general purpose GPUs Part 2 of this article discusses how OpenCL for FPGA can be used to address more than just the CPU accelerator market by including extensions for streaming I/O, support for multiple FPGA systems, and by using embedded ARMs as the OpenCL host, allowing the benefits of FPGA technology to be brought to an even larger group of users.



Streaming I/O (aka OpenCL Channels)

Traditional OpenCL uses a host and accelerator model, with all data for the accelerator coming from the host, and all processed results sent back to the host. As discussed in Part 1, host code can be written in any programming language the user desires and interfaces with the OpenCL environment through a defined application programming interface (API) for managing the accelerators. This API includes calls for data movement, loading code and scheduling and coordinating execution. Each device supplier provides support for their own accelerator, including a compiler for the accelerator code and the backend for the host API. Suppliers must follow the OpenCL standard to ensure portability (hence it is a “standard”), but can also add their own optimizations, including pre-written libraries. The accelerator code is written in a language derived from C (actually C99), with some extensions. While this model works for a true CPU accelerator, it’s not very helpful when the application requires that the FPGA must interface directly with real-world inputs without having to go through a host. This is a typical scenario since the historic use of an FPGA in many systems was only for interfacing with I/O devices. Over the years, as FPGA processing performance

has increased, more and more I/O processing and front-end stream processing has been moved to the FPGAs. However, the bulk of the processing has often been left for programmable processors due to development complexity. Since OpenCL overcomes this complexity, enabling the OpenCL environment to directly interface with external data within the FPGA is key to unlocking much higher system performance and efficiency. This was recognized as such an important need that it is now in the OpenCL Revison 2.0 provisional standard under the term “pipes,” and is also supported by Altera via an OpenCL vendor extension for what they call “channels.” Channels, or pipes, allow an OpenCL kernel to directly read from or write to what is essentially a FIFO. The other side of this FIFO then connects, via prewritten logic, to real-world I/O. This means external data can come directly into the FPGA, be processed in an OpenCL kernel, and then sent back to the outside world, all requiring no data flow with the host. The underlying support for the I/O device is implemented by FPGA developers and locked down in the Board Support Package (BSP) with the rest of the OpenCL infrastructure (Figure 1). Note that using channels does not supersede the traditional OpenCL data flow model, it just opens up a new method for getting data into and out of a kernel. Any


















ON CHIP MEMORY INTERCONNECT FIGURE 1 Partitions showing locked external interfaces and kernel code with added external I/O logic for a channel in the lock down region.

combination of data flows can now be provisioned. Streaming OpenCL channels also allow direct kernel to kernel data flows. Previously, data for each kernel had to be independently read from memory, processed and written back; the next kernel then had to read the memory to do its processing, and write its results back. For some applications, this could make the external memory bandwidth the limiting factor. With kernel to kernel streaming, data passes directly between kernels without having to go back to external memory, thus removing that potential bottleneck. Additionally, OpenCL channels allow any custom FPGA logic to interface with an OpenCL kernel. This means that one can have an FPGA team and software team, and use OpenCL as the interface mechanism between the two groups. The FPGA team does their work first, locks it down in the OpenCL BSP, and hands

it off to the software team who can then develop the processing algorithms in OpenCL. As discussed in Part 1, this work flow allows the FPGA implementation to be guaranteed to meet timing, which means the software team does not have to keep throwing things over the wall to the FPGA group to implement, integrate and test—the OpenCL environment has done that work for them. Streaming OpenCL channels add various data flow options to the traditional OpenCL model including kernel to kernel, kernel to FPGA logic, and the ability to directly interface an FPGA with external I/O. This opens the OpenCL development environment to an endless number of possibilities. In many systems, the data flow with the host is a bottleneck, since the real-world data comes from an input device, is sent to the host, then passed down to the accelerator, back to the host, and finally back to an output device. Now

the input, output and processing device can all be the same. It can also dramatically shift the CPU to accelerator ratio, as the accelerators can now actually be full data processing systems, with the CPU just providing overall control of the system. There are many application examples where this feature can be used, including video processing, network processing, signal processing and real-time control systems.

Multiple FPGA Systems

The OpenCL standard allows for multiple accelerator devices in a system, but the early releases of Altera’s OpenCL SDK assumed just one FPGA accelerator per system. Thankfully, the latest release of the tool provides support for multiple FPGA devices in a system allowing one to build extremely powerful FPGA processing platforms and use OpenCL to program them. RTC RTCMAGAZINE MAGAZINE DECEMBER OCTOBER 2013


INDUSTRY WATCH In a simple use case, each FPGA is an independent device, and all data flows are with the host. To unlock the power of multiple FPGAs, however, Altera’s channels extension can become extremely useful, as one can directly connect multiple FPGAs (i.e. not over PCIe) and have data flow between them. For example, BittWare’s TeraBox (see sidebar “Platform with Sixteen Stratix V FPGAs Hits 20 TeraFLOPS”) can have 16 large FPGAs with high-speed serial connections between them all—OpenCL with channels can be used to leverage this as a software programmable platform to achieve unprecedented performance, latency and efficiency. As a standard feature of the OpenCL API, host code can interrogate a system to find out how many and what type of accelerators are present. This allows one to develop an OpenCL host program that dynamically adjusts to make use of the accelerator resources available. For example, a financial demonstration program (Asian options) running on BittWare’s TeraBox, which can be provisioned with 1 to 16 FPGAs, automatically adjusts to the number of FPGAs present, with performance scaling linearly. Note that this demonstration program happens to be one that is compute-bound, so it scales nicely with the compute power available. Other applications may be limited by factors such as host or memory bandwidth—but further note that it may be possible to use OpenCL channels to overcome those limitations!

Complete OpenCL System on an FPGA

As detailed in Part 1 of this series, an OpenCL system consists of a host and one or more accelerators. Typically this is a general purpose CPU with a GPU or FPGA on a plug-in board. With the recent introduction of hard embedded processor systems in FPGAs, however, the FPGA can be a complete OpenCL system unto itself. Altera now has beta support for running OpenCL on their Cyclone V SystemOn-Chip (SOC) device, with an embedded ARM processor. The ARM acts as the OpenCL host, with the FPGA fabric as the accelerator. It would also be possible to use a second embedded ARM core



as an OpenCL accelerator, so one would have an ARM host, coupled with both ARM- and FPGA-based accelerators, all in a single device. With upcoming Arria 10 and Stratix 10 devices promising dual core ARMs running at 1.5 GHz, it is easy to see how one can build a very powerful standalone OpenCL processing system in an FPGA. By making use of OpenCL channels to integrate custom I/O in the FPGA fabric, and then using OpenCL programming to harness the processing power of the FPGA from the ARM, one can start to see how this technology can make the power of FPGAs available to the wider base of embedded software programmers. The OpenCL initiative has made significant headway in the quest to use FPGA technology in spaces traditionally dominated by programmable processors. With the addition of streaming I/O, support for multi-FPGA systems, and using embedded ARMs as OpenCL hosts, traditional barriers to broader FPGA deployment are being moved aside. BittWare Concord, NH (603) 226-0404 Altera San Jose, CA (408) 544-7000

Platform with 16 Stratix V FPGAs Hits 20 TeraFLOPS A multi-FPGA system for high-performance computing and network processing applications provides up to 16 Altera Stratix V FPGAs in a single system, for 20 TeraFLOPS of total processing power, along with 6.5 Terabits/s of memory bandwidth and 1.28 Terabits/s of I/O—all in a turnkey rackmount solution. The TeraBox from BittWare features up to eight full-size dual Altera Stratix V GX/GS PCIe boards—BittWare’s S5-PCIe-DS (S5PEDS). Along with two Altera Stratix V FPGAs

per board, the S5PE-DS also provides an extremely flexible memory configuration with eight SODIMM sites each supporting DDR3 SDRAM, RLDRAM3, or QDRII+. The TeraBox supports up to a system total of 512 Gbytes spread over 64 banks for 6.5 Terabits/s of memory bandwidth. The system arrives fully tested and configured, and includes complete development software support with BittWare’s BittWorks II Toolkit, allowing users to immediately focus on their specific application development. Features include 20 TeraFLOPS processing: 16x Altera Stratix V GX/GS FPGAs with up to 15 million logic elements (GXAB) and up to 62,000 multipliers (GSD8). Among other things, this enables 1.28 Terabits/s of I/O— 128x 10GigE, 32x 40GigE, or 32x QDR/FDR InfiniBand. The board has 6.5 Terabits/s memory bandwidth with 64 banks of DDR3-1600 (512 Gbytes), RLDRAM3 and QDRII+ memory options. Software support includes Windows and Linux 64 drivers, interface libraries and hardware management along with the application-ready FPGA framework for Stratix V.



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TECHNOLOGY Two DSP-Based 4/8-Axis Advanced Pulse-Train Motion Controllers

A pair of 4- and 8-axis motion controllers has been announced by Adlink. The AMP-204C and AMP-208C digital signal processing (DSP)-based 4/8-axis advanced pulse-train motion controllers enable high pulse output and encoder input frequency up to 6.5 MHz and 20 MHz, respectively. The AMP-204C and 208C leverage Adlink’s Softmotion technology and easy-to-use utility to offer comprehensive and application-oriented motion functionality. This reduces development time and cost up to 25% while maintaining superior throughput and accuracy. In addition, customer-reported testing shows a reduction in time required for completion of action using the AMP-204C and 208C as compared to other motion controllers, enabling at least 10% growth in productivity. The pair features high-speed, enhanced precision control and competitive pricing for a superior cost-performance ratio. The AMP-204C and 208C feature advanced synchronous motion control performance combined with point-table functionality integrating multi-dimensional interpolation; for instance, 3D linear/circular/ spiral interpolation with enhanced trajectory and velocity planning is used for contouring applications in semiconductor, display and conventional manufacturing industries. The AMP-204C/AMP-208C also support pulse-width modulation (PWM) control with three different control modes for frequency or duty cycle, benefiting laser engraving/ marking/cutting applications. Moreover, hardware-based, high-speed

position comparison and trigger output up to 1 MHz are applicable in AOI applications, and 16 additional onboard digital input & digital output channels make the AMP-204C/208C more economical than a full D I/O card. The AMP-204C/208C’s MotionCreatorPro 2 Windows-based application development software package provides a Setup Wizard, shortening system installation and evaluation time and allowing full monitoring of onboard DSP and I/O consumption via a system diagnostics page. Powerful sampling page and graphic tools deliver real-time motion and I/O status and conduct further motion flow analyses. ADLINK Technology, San Jose, CA. (408) 360-0200.

COM Express Features HighPerformance Quad-Core Intel Celeron and 4.5 Watt SDP

A new high-performance COM Express module is available in seven variants based on the new Intel AtomT processor E3800 product family and Intel Celeron processor N2920 formerly codenamed “Bay Trail.” The congaTCA3 COM Express Type 6 Module from congatec offers a compelling entry price for this form factor. And the Intel Celeron N2920 1.6 GHz quad-core variant features a scenario design power (SDP) of only 4.5 watts. SDP provides realistic information on average power consumption in practice. Innovations include a large L2 cache shared by multiple cores and a faster Intel HD graphics unit compared with the previous generation. This turns new applications into visual experiences.

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The modules support Intel Advanced Encryption Standard New Instructions (Intel AES-NI) set, which is more relevant than ever in practical application. This allows developers to offload particularly compute-intensive packaging and encryption routines of the wellknown cryptographic algorithm Advanced Encryption Standard (AES) into hardware, thereby enabling high-performance encryption without putting a significant burden on the CPU cores. The conga-TCA3 COM Express module provides up to 8 Gbyte fast DDR3L memory

and two SO-DIMM sockets. The integrated graphics supports DirectX 11, OpenGL 3, OpenCL 1.2 and high-performance, flexible hardware decoding to decode even multiple high-resolution full HD videos in parallel. Up to 2,560 x 1,600 pixels with DisplayPort and 1,920 x 1,200 pixels with HDMI are natively supported in the processor. It is also possible to connect up to two independent display interfaces via 2x 24-bit LVDS. Thanks to native USB 3.0 support, the modules achieve fast data transmission with low power consumption. A total of eight USB 2.0 ports are provided, one of which is designed for USB 3.0 Superspeed. Five PCI Express 2.0 lanes and two SATA interfaces with up to 3 Gbit/s enable fast and flexible system extensions. The Intel Ethernet Controller I210 helps with software compatibility. A CPI 5.0, I2C bus, LPC bus for easy integration of legacy I/O interfaces and Intel High Definition Audio complete the feature set. Volume pricing starts below $200. Congatec, San Diego, CA. (858) 457-2600.


FPGA COTS PCIe Board for HPC, Military/Government and Network Processing Applications

A new PCI Express COTS board is powered by two of Altera’s 28-nm Stratix V FPGAs. The S5-PCIe-DS (S5PE-DS) from BittWare is a Gen 3 PCIe x16 card with an extremely flexible memory configuration. Eight SODIMM sites enable up to 64 Gbytes of DDR3 SDRAM, up to 4 Gbytes of RLDRAM3, and/or up to 256 Mbytes of QDRII+. Providing additional flexibility are four front-panel QSFP cages, allowing four 40GigE, 16 10GigE, or four QDR/ FDR InfiniBand interfaces direct to the FPGA’s built-in PHYs for the lowest possible latency. With almost 2 million logic elements available (952,000 per FPGA), the board is suitable for high-performance computing, and with the reduced latency provided by the network interfaces, ideal for high frequency trading, military/government agency secure communications and network processing applications.

Major features of the S5-PCIe-DS include the two high-density Altera Stratix V GX/ GS FPGAs and the PCIe x16 interface supporting Gen1, Gen2, or Gen3. There are four QSFP+ cages for 4 x 40GigE or 16 x10GigE or 4x QDR/FDR InfiniBand direct to the FPGAs for lowest possible latency. In addition, there are eight SATA connectors with up to 6 Gbit/s each and timestamping support. Utility I/O includes: USB 2.0, RS-232 and JTAG, and memory options offer up to 64 Gbytes of DDR3 SDRAM with ECC; up to 4 Gbytes RLDRAM3 and up to 256 Mbytes QDRII+. BittWare, Concord, NH. (603) 226-0404.

FPGA Board Kit Based on a Xilinx Artix-7

The Nexys-4, a complete, ready-to-use digital circuit development platform based on the latest Artix FPGA from Xilinx, brings high performance to a student-focused FPGA design kit. With its large, high-capacity FPGA, generous external memories, several built-in peripherals and a collection of USB, Ethernet and other ports, the Nexys-4 can host designs ranging from introductory combinational circuits to powerful embedded processors without needing any additional components. Based on the Xilinx Artix-7 100T FPGA, the Nexys-4 is optimized for high-performance logic and offers seven times the capacity, and more resources, than its predecessor (the Nexys3). The Nexy4 also offers an improved collection of peripherals including 16 user switches, 16 user LEDs, two 4-digit seven-segment displays, an XADC Pmod header for digitizing analog signals, two tri-colored LEDs, a micro SD card connector, 12-bit VGA output, mono PWM audio output, a PDM microphone, a 3-axis accelerometer and a temperature sensor. The large FPGA and broad set of peripherals make the Nexy4 an ideal host for a wide array of digital systems, including embedded processor designs based on Xilinx’s MicroBlaze. Nexys-4 is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE toolset, which includes ChipScope and EDK. Xilinx offers free WebPACK versions of these toolsets, which means that designs can be implemented in either version at no additional cost. The Nexys-4 board is priced at $159 for academic purchases and $299 for all other customers. The Nexys-4 board is available as of now. Diligent, Pullman, WA. (509) 334-6306.

Analog IC Enables Automotive ODB-II Remote Diagnostics from Cell Phones

A new automotive integrated circuit is an ODB-II Diagnostics Interface/Controller. The JV700 from JVD Semiconductors is a custom Analog ASIC that resides in a small dongle that plugs into the vehicle’s ODB-II connector (typically located under the dash). The JV700 incorporates all the critical analog functions required to interface and communicate through the ODB-II connector with all major automotive buses. The chip receives instructions to configure a complex array of low RDS(on) MOSFET switches that properly align the chip’s five bus transceivers to the correct ODB-II pins based on the vehicle’s make, model, year and VIN. The JV700 then communicates the vehicle information via a serial bus to a nearby microcontroller where the data is processed and communicated via Bluetooth to a cell phone or mobile computer for viewing. Diagnostic Trouble Codes (DTCs) are how ODB-II identifies and communicates to technicians where and what onboard problems exist. The first number in the DTC indicates whether the code is an SAE generic code (applies to all ODB-II systems) or is specific to the vehicle manufacturer. The remaining three numbers provide information regarding the specific vehicle system and circuit. While these communication protocol standards are universal, not every make and model uses the same pins on the ODB-II connector to access the information, making universal diagnosis all but impossible without the circuitry found in the JV700. To further complicate diagnostic testing, there remain several pins in the ODB-II connector that are unspecified and their use is left to the vehicle manufacturer’s discretion. These unassigned pins are available for use by the manufacturer for things such as airbags, alarms, remotes and more, and their use varies widely among the world’s car manufacturers and even among different models produced by a single manufacturer. The JV700 can connect and communicate with the unassigned pins to read and manage the peripheral information as well. JVD Semiconductors, San Jose, CA. (408) 263-7704.




3U CompactPCI System Offers Ultra-Flexible Modularity in a Compact Size A new, control 3U CompactPCI cabinet computer with Intel Celeron 807UE processor offers customers a compact-sized industrial computer with all the flexibility of a modular 3U CompactPCI server. That makes the CPPOCKET from Kontron a highly customizable solution with standard building blocks that are easily combined. OEMs and system integrators can leverage the entire ecosystem of 3U CompactPCI and define their dedicated wall mount system within minutes, reducing design and system integration effort to a minimum. By downgrading system functionality from a server to a box-sized CompactPCI platform, the intelligent modular system has also been cost-optimized— a perfect fit for price-sensitive applications such as machine and factory control, programmable logic controllers and inspection systems. The Kontron CP-POCKET includes versatile expansion options enabled by rugged CompactPCI peripheral boards. Accessible from the front without the need to remove the enclosure, the boards are easily swapped in a matter of seconds. This simplifies system assembly and maintenance. With its three CompactPCI expansion slots, the CP-POCKET easily supports applications with high I/O requirements. Kontron’s latest CP-POCKET model integrates the 3U CompactPCI Kontron CP3003-V. It includes the Intel Celeron 807UE processor with 1.0 GHz and the Intel QM77 Platform Controller Hub. A smart cache of 1 Mbyte and up to 4 Gbyte of DDR3 SDRAM memory with as much as 1333 MHz guarantee high data throughput. The Kontron CP3003-V comes as a double-slot version (8HP) offering a comprehensive range of interfaces at the front panel: Displays can be connected on one VGA and two DisplayPort interfaces. Peripherals connect over one USB 3.0 port, two USB 2.0 ports and one serial port. Three Gigabit Ethernet ports enable horizontal and vertical integration in automation networks. Optional storage media such as a CFast module and one 2.5-inch HDD/SSD can be integrated on board and do not require an expansion slot, leaving more headroom for specific extensions. The Kontron CP-POCKET with CP3003-V supports Linux, Microsoft Windows 7 and Windows Embedded Standard 7. It can be ordered as a pre-validated platform off the shelf or as an application- ready platform including expansion boards, an OS and certification as required. Kontron, Poway, CA. (888) 294-4558.

Rugged Systems Meet Cisco’s Embedded Router Specs

A 5-port Fast Ethernet router system is based on the Cisco 5915 ruggedized embedded router. The HDC5915-5 HiDAN from RTD enables the deployment of Cisco Mobile Ready Net capabilities in mobile, air, ground and unmanned applications. RTD’s waterproof, milled aluminum packaging and cylindrical connectors create an ideal chassis for this advanced Cisco 5915 system. This compact system pairs the proven ruggedness of RTD products and enclosure technology with the robust quality and performance of Cisco’s 5915 Router. The HiDAN HDC5915-5 offers reliable operation in extreme temperatures and under high shock and vibration conditions. Features include the rugged waterproof enclosure and the integrated Cisco 5915 Embedded Services Router (ESR) with Cisco IOS software, Cisco Mobile Ready Net capabilities and highly secure data, voice and video communication. The five Fast Ethernet Ports (10/100) come in the form of three switched ports for local connections (Layer 2) and two routed ports for remote connections (Layer 3). The router also supports auto-negotiation of speed and duplex. In addition there is a serial console port, LED indicators and a console port for programmability. RTD Embedded Technologies, State College, PA. (814) 234-8087. www.rtd/com



Starter Kit for Multicore ARMBased Qseven Modules

A complete, out-of-the-box starter kit for Qseven modules is based on the Freescale i.MX6, which contains a Cortex-A9 RISC CPU with one, two or four cores. Using the MSC Q7-SK-IMX6 starter kit from MSC Embedded makes it easy to evaluate and test applications. The Q7-IMX6 module is very simple because the kit includes all necessary components for the immediate operation of the Qseven module: a compact Qseven baseboard with power supply, a Qseven heat spreader, an SD Card with bootable Operating System and a Resource CD with drivers and documentation. Also, the starter kit includes all parts required for the development of applications with the Q7-IMX6 module. An optional TFT kit can be provided including a suitable cable set to directly connect the LCD with the Qseven Baseboard of the Starterkit. The MSC Q7-SK-IMX6 Starterkit is available in versions for Linux and Windows Embedded Compact 7, with an Android version currently in discussion. The kit consists of a compact application baseboard (MSC Q7-MB-EP4) providing the most relevant interfaces such as DVI/HDMI and LCD graphics, LAN, USB, UART, CAN and SDIO. The suitable Heatspreader for the Q7-IMX6 module provides for basic cooling or adaptation of a dedicated cooling solution. A standard 12V power supply is enclosed connecting to the baseboard. The 8 Gbyte Flash SD Card contains the appropriate boot loader and bootable Operating System: either Linux based on the Yocto Project or Windows Embedded Compact 7. In all cases, the accompanying Resource CD includes all documentation and drivers required to immediately start working with the Q7-IMX6 module, plus sample schematics and a collection of technical notes. The MSC Q7-SK-IMX6 is available at a sample price of $275. MSC Embedded, San Bruno, CA. (650) 616-4068.


Mini-ITX Motherboard with Fourth Generation Core Processors   A mini-ITX motherboard supports a fourth generation Intel

Core i7/i5/i3 processor and mobile Intel H81 Express chipset. The Core processors provide up to a 15 percent better performance than the previous generation. The MB-73340 from Win Enterprises is designed to support a range of solutions that require high performance, low power, excellent graphics and efficient connectivity in a small form factor. Applications include markets such as kiosk, retail, medical, military, industrial control and security. Key features include the fourth generation Intel Core LGA 1150 Socket and Intel H81 Express chipset. The board has 2 x DDR3 1600 MHz / SODIMM up to 16 Gbytes and one external HDMI/VGA/DVI-D/24-bit Dual Channel LVDS interface. There are six COM ports, eight USB ports, and LPC and SMBus. In addition the board has two SATA 6 Gbit/s and two 3 Gbit/s SATA ports along with two Intel energy-smart GbE LANs. In addition there is a PCI Express X16 slot and a PCI Express X1 slot. High-end 3D graphics capability is supported by 1 x external HDMI/VGA/DVI-D/24-bit Dual Channel LVDS. An optional PCIe riser card enables OEMs to add features, i.e., 1 x PCI Express X16

slot , 1 x PCI Express X1 slot, and 1 x Full-size Mini-PCIe with PCIe X1. Robust storage space is provided by 2 x SATA 6 Gbit/s 2x SATA 3 Gbit/s. WIN can modify the board when it’s ordered in OEM quantities. WIN Enterprises, North Andover, MA. (978) 688-2000.

Ultra-Low-Density FPGAs Enable Always-On Sensor Solutions

A line of new ultra-low-density iCE40TM FPGAs deliver flexible, single-chip sensor solutions for making a new generation of contextaware, ultra-low-power mobile devices possible. The new additions to the iCE40 FPGA family from Lattice Semiconductor allow customers to integrate more functions into a smaller space. In packages as small as 1.4 mm x 1.48 mm x 0.45 mm, they are small enough and affordable enough to fit almost anywhere, reducing board space and system complexity. With hard IP for strobe generators, I2C and SPI interfaces, the new iCE40LM FPGAs deliver near-zero latency to the mobile market, enabling context-aware systems with the real-time capturing of user and environmental inputs with minimal delay or error. This gives designers a platform for their mobile products to deliver media-rich experiences based on movement, travel direction, location and other interactions with the environment. The small size of the new iCE40 FPGAs enables integration of advanced functions such as IrDA, barcode emulation, service LED and more in a single chip with available logic for additional customer-defined functions. Moreover, Lattice has demonstrated that the iCE40LM FPGA solution can reduce power consumption by 100x over traditional application processor-only implementations, thus increasing battery life to bring more value to the end user. The new iCE40LM FPGAs give mobile device system architects the ability to add and/or customize sensor management functions and capabilities using a single, simple platform that can be implemented across different designs. The new additions include the iCE40LM 4K, iCE40LM 2K, iCE40LM 1K FPGAs and consume very little power, under 1 mW in active mode. All iCE40 devices are supported by the company’s iCEcube2 design software (release 2013-08) and Lattice Diamond Programmer v3.0.

Designed to offer a highly productive, integrated development environment for the mobile designer and optimized for Lattice’s iCE40 FPGA architecture, the easy-to-use iCEcube2 software is a world class design flow for the mobile designer. The Lattice Diamond Programmer is compatible with iCEcube2 software and enables device programming for Lattice devices, simplifying the most common steps, including: setting up device information (cable, port etc); selecting the programming data file to use; and programming single or multiple devices. Lattice Semiconductor, Hillsboro, OR. (503) 268-8000. FIND the products featured in this section and more at




PC/104 PSU Modular Power Supply A modular PC/104 Power Supply Unit (PSU)

can be purpose-built for individual systems to provide optimal DC/DC efficiency and variable wattage outputs on any of the voltage-rails. The lower voltages are typically provided on the individual PC/104 cards from a single rail on the PC/104 Bus-Stack using small DC/ DC converters. This typically means that the other voltage rails are 100% idle, simply consuming energy and generating heat. The SMT1024 from Sundance can be built and even upgraded after deployment with any

combination of 30W of +3.3V; 30W of +5V; 30W of +12V or a nominal 3W for the -12V voltage-rail to offer legacy PCI/104 compatibility. The SMT1024 overcomes another design requirement of the modern embedded system in respect to 1500V total I/O isolation between the “Consuming” power and the “Providing” power. This has been enabled with Traco Ultra Compact DC/DC converter modules with 92% efficiency, at full industrial temperature range and fully protected for surge transients up to EN-61000-4-5 level. Additionally, the SMT1024 has thermal protection that will shut down the PSU at 115 degrees (Celsius).  The SMT1024 has an optional Power-over-Ethernet (PoE) module, based on the Infomart PEM3100 series modules, which replaces the typical AC/DC brick PSU and at the same time connects to an infrastructure network, either locally or globally. Pricing for SMT1024 starts at $395.00 for a single power-rail. The SMT1024 and all its variations are available on typical 6-8 weeks lead-time. Sundance Poughkeepsie, NY (914) 495-1011



40G AdvancedTCA NPU Blade for High Throughput Packet Processing

An AdvancedTCA (ATCA) packet processing blade features dual 32 core NPUs for parallel processing and up to 320G switching capability. The aTCA-N700 from Adlink Technology delivers advanced packet and security processing capabilities for high-performance, highthroughput, low-latency applications in broadband infrastructure elements, such as wireless access point controllers, network security platforms, deep packet inspection, IPTV, LTE gateways and media servers. The Adlink aTCAN700 is compliant to the ATCA Base Specification (PICMG 3.0 R.3.0) and the ATCA Ethernet Specification (PICMG 3.1 R2.0) and is powered by dual Cavium OCTEON II CN6880 processors, each with 32 cnMIPS64 V2 cores and a highly optimized architecture for deep packet inspection, network security and traffic-shaping applications. The aTCA-N700 optimizes performance with a powerful local management processor (LMP), a quad-core Freescale QorIQ P2041, which makes local management more flexible and convenient and allows the Cavium processors to focus on packet processing. For Ethernet connectivity, the aTCA-N700 utilizes the high-performance Broadcom BCM 56842 Ethernet switch to connect the CN6880 packet processors, backplanes and I/O ports, with the switch fabric providing up to 320 Gbit/s bandwidth. For data transfer, the aTCA-N700 uses dual Fabric Interface channels (2x 40G) in addition to two base interfaces (2xGbE), which provide both speed and flexibility. Flexible RTM support is also provided to facilitate maximum I/O density and supply up to 160 Gbit/s of total available bandwidth. Adlink has prepared Application Ready Intelligent Platform (ARIP) solutions that integrate both hardware and software to facilitate better performance, reduce risk and cost of ownership, and help system providers to speed time-to-market of their products, such as WiFi access controllers and deep packet inspection platforms. Other suitable applications include IP radio network controllers, LTE gateways, security gateways, high-density media gateways, media servers, IPTV infrastructure components (e.g., edge routers and media switches) and WiMAX ASN gateways. ADLINK Technology San Jose, CA (408) 360-0200


Qseven Module with SingleChip, Quad-Core Intel AtomT E3800 family

A new Qseven module is based on the Intel AtomT processor E3845. The congaQA3 modules from congatec are fitted with ceramic capacitors making them suitable for industrial mobile applications in harsh environments. New features include an ample L2 cache, which can be shared by multiple cores, and a much faster Intel HD graphics unit compared with the previous generation. This turns new applications into visual experiences. The modules support Intel Advanced Encryption Standard New Instructions (Intel AES-NI) set, which is more relevant than ever in practical application. This allows developers to offload particularly computeintensive packaging and encryption routines of the well-known cryptographic algorithm Advanced Encryption Standard (AES) into hardware, thereby enabling high-performance encryption without putting a significant burden on the CPU cores. The conga-QA3 comes in five different Intel Atom processor-based versions

(formerly codenamed “Bay Trail”) for high scalability. It ranges from the entry-level single-core Intel AtomT processor E3815 with 1.46 GHz and a low power consumption of 5 watts, up to the quad-core Intel AtomT processor E3845 with 1.91 GHz and 10 watts. The Qseven modules are each equipped with 2 Gbyte of DDR3L memory and up to 16 Gbyte eMMC 4.5 for mass storage. Depending on which processor is used, versions with 8 Gbyte of RAM are available. The integrated graphics are significantly more powerful than the previous model and sup-

port DirectX 11, OpenGL 3, OpenCL 1.2 and high-performance, flexible hardware decoding to decode even multiple high-resolution full HD videos in parallel. Up to 2,560 x 1,600 pixels with DisplayPort and 1,920 x 1,200 pixels with HDMI are natively supported in the processor. It is also possible to connect up to two independent display interfaces via 2x 24-bit LVDS. Thanks to native USB 3.0 support, the modules achieve fast data transmission with low power consumption. One of the five provided USB 2.0 ports is executed as USB 3.0 Superspeed. Three PCI Express 2.0 lanes and two SATA interfaces with up to 3 Gbit/s enable fast and flexible system extensions. The Intel Ethernet Controller I210 guarantees the best software compatibility. Completing the feature set are: MIPI camera interface, I2C bus, LPC bus for easy integration of legacy I/O interfaces and Intel High Definition Audio. Volume pricing starts below $200. Congatec San Diego, CA (858) 457-2600

HetNet Solutions Portfolio for Accelerating Deployment of Next Gen Wireless Infrastructure A portfolio of programmable solutions is aimed at building smart, low-power cellular equipment needed to support the global rollout of Heterogeneous Networks (HetNet). In collaboration with Azcom Technology, the HetNet Solutions Portfolio from Lattice Semiconductor enables system designers to implement best-in-class solutions for connectivity, control path and power management while accelerating their development with system-level reference designs for multi-mode LTE small cells. Service providers around the world are deploying a mosaic of wireless equipment in both indoor and outdoor environments including office buildings, public facilities and underground areas to support the explosive growth in mobile data traffic. According to the Small Cell Forum in a report released at this year’s Mobile World Congress, the small cell market alone is expected to generate $22 billion by 2016. The Lattice HetNet Solutions Portfolio enables designers of small cells, low-power remote radio heads, distributed antenna systems and active antennas, to achieve the lowest BOM, power consumption and smallest footprint for the connectivity, control path

and power management functions of their systems. Complementing the ASICs and SoCs used for complex data path functions, Lattice’s industry-leading FPGAs, CPLDs and programmable power management devices meet requirements for small form factor, low-cost and ultra-low power. Combined with soft IP for connectivity, control path and data path functions optimized for low complexity HetNet applications, the LatticeECP3, MachXO2 and MachXO3 FPGA families, Lattice power management devices and Azcom reference platform give developers everything they need for affordable innovation of HetNet systems. The Lattice HetNet Solutions Portfolio is supported by the Lattice Diamond software. Optimized for Lattice’s low- and ultralow-density FPGAs, the software comprises leading-edge design and implementation tools optimized to allow electronic system designers to meet their power, size and cost goals. Lattice Semiconductor Hillsboro, OR (503) 268-8000

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Two-Channel Analog RF Tuner for Communications, Radar and Signal Intelligence Systems

A new 2-channel analog RF tuner accepts RF signals over the range of 400 MHz to 4 GHz, amplifying, filtering and downconverting them to an IF signal suitable for A/D conversion by any of several Pentek signal acquisition modules. The Model 7120 from Pentek is packaged in a shielded PMC/XMC module with front panel connections for easy integration into RF systems without the use of an external tuner. The 7120 accepts RF signals on two front panel SSMC connectors. Low noise amplifiers are provided along with two programmable attenuators allowing downconversion of input signals ranging from -60 dBm to -20 dBm in steps of 0.5 dB. The Model 7120 input frequency is programmable across the 400 to 4000 MHz band with a tuning resolution of less than 100 KHz. An optional five-stage lowpass or bandpass input filter can be specified

with several available frequency and attenuation characteristics for RF image rejection and harmonic suppression. The Model 7120 includes a programmable low noise LO frequency synthesizer. It accepts a 10 MHz reference from either a front panel reference input, or from or an onboard 10

Rugged Switch Solutions Lower Cost of Gigabit Ethernet in SWaP-Optimized Packages Two new cost-effective rugged Gigabit Ethernet (GbE) Switch solutions speed and ease the integration of modern networking technology into defense platforms. The SMS-652 Rugged Switchbox subsystem and VPX3-652 GbE Switch module from Curtiss-Wright Controls Defense Solutions represent new GbE Switch line replaceable unit (LRU) and line replaceable module (LRM) solutions that dramatically lower the cost of adding network connectivity into new and legacy platforms. These COTS GbE Switch solutions are designed to meet the continuing technology refresh requirements of defense and aerospace systems integrators facing increased size, weight, power and cost (SWaP-C) pressures. The SMS-652 Rugged Switchbox is a fully MIL-qualified standalone 16-port GbE Switch LRU that can be quickly and easily integrated into airborne, ground and naval platforms. Housed in a compact sealed enclosure, the SMS-652 is ideal for airborne communications systems, sensor data acquisition and data processing applications, on platforms such as UAVs, where there is limited available space for larger subsystems. For systems integrators designing with VPX technology, the new VPX3-652 GbE Switch LRM provides up to 20 ports of Ethernet connectivity in a single 3U slot with a very low power footprint. The VPX3-



MHz oven controlled crystal oscillator, which provides an exceptionally precise frequency standard with excellent phase noise characteristics. Output is provided as baseband I and Q at bandwidths up to 390 MHz. Alternatively, either the I or Q output can be used as a real IF output signal. User provided output IF filters support custom output bandwidths for specific application requirements. Because of the gain, filtering and translation provided by the 7120, the output is well-matched to the A/D inputs of high-performance signal acquisition products from Pentek, including the popular Cobalt and Onyx families. The Model 7120 PMC/XMC module is designed for air-cooled, conduction-cooled and rugged operating environments. It is available as a 3U/6U Compact PCI (Models 7220/7320/7420), 3U VPX (Model 5220), PCIe (Model 7820) and AMC (Model 5620). Pricing starts at $4,995. Pentek, Upper Saddle River, NJ. (201) 818-5904.

652 GbE Switch is ideal for use in space-constrained embedded C4ISR and EW subsystems to support network communications both within the subsystem and to connect externally to other subsystems within the platform. Curtiss-Wright offers both LRU and LRM configurations to enable system integrators to choose, depending on their unique platform requirements, whether to deploy a standalone GbE Switch LRU or to add GbE Switch functionality into a new or existing chassis via a modular (card-based) solution. Both configurations are based on the latest high-performance GbE networking technologies and are offered in SWaP-C optimized packaging to deliver the highest port count density at the lowest power and cost. Both the SMS-652 and VPX3-652 feature extremely low power and fast boot architectures. They also support a wide range of managed networking features, including VLANs, QoS, multicast, spanning trees and jumbo frames. To reduce cooling requirements and eliminate wasted power, both also feature Energy Efficient Ethernet technologies for system-wide power savings. And their built-in cable diagnostics provide an unprecedented new level of system diagnostics. Curtiss-Wright Controls Defense Solutions Ashburn, VA (613) 254-5112


12-Channel High-Speed CAN Bus PMC / XMC

A conduction- or air-cooled XMC or PMC has 12 high-speed ISO 11898-2 CAN bus channels to inaugurate it as a CAN bus XMC. The XPort9200 from Extreme Engineering Solutions triples the number of CAN bus channels previously available from any COTS conduction- or air-cooled PMC module. All 12 isolated CAN bus 2.0A- and 2.0Bcompliant channels support speeds up to 1 Mbit/s and can be accessed through the PMC P14, XMC P16, or front panel connector. The XPort9200 can be mounted on any module that supports an air-cooled or conduction- cooled (VITA 20) XMC / PMC site. This enables access to at least 12 high-speed CAN channels for a significant number of COTS VPX, VME, CompactPCI (cPCI) and systemlevel products, including the X-ES fourth generation Intel Core i7 processor-based 3U VPX XPedite7570 and 3U cPCI XPedite7530. When configured as an XMC, the XPort9200 supports a VITA 42.3-compliant x1 PCIe interface through its XMC P15 connector and routes all 12 CAN bus channels to its XMC P16 connector. When configured as a PMC, the XPort9200 supports a 32-bit PCI interface through its PMC P11 and P12 connectors and routes all 12 CAN bus channels to its PMC P14 connector. Front panel I/O and on-card termination are also available as a configuration options. The XPort9200 eases system integration by utilizing industrystandard NXP SJA1000-compatible CAN controllers. This facilitates full support of Linux SocketCAN and helps to simplify software portability. Wind River VxWorks and Microsoft Windows drivers also are available. Extreme Engineering Solutions Middleton, WI (608) 833-1155

Wideband Software Radio Module for UAV, Radar and Communications

A single-channel, high-speed data converter XMC FPGA module can receive and transmit at the same sampling rate, supporting signal bandwidths up to 400 MHz. The Model 71730 from Pentek is a 1 GHz 12-bit A/D, 1 GHz 16-bit D/A module that is based on the high density Xilinx Virtex-7 FPGA. The Model 71730 appeals to customers that need the wider symmetrical bandwidth for both input and output signals. In combination with the Virtex-7 FPGA, additional memory and the PCIe Gen 3 interface, this Onyx board offers the performance that many wideband communications systems require. The Model 71730 comes preconfigured with a suite of built-in functions for data capture, synchronization, time tagging and formatting, making the board an ideal turn-key interface for radar, communications or general data acquisition applications. The Model 71730 features an A/D acquisition intellectual property (IP) module for easy capture and data moving and a sophisticated D/A waveform playback IP module that allows users to easily play back waveforms from onboard memory or the PCI Express interface. These modules greatly enhance the functionality of the Model 71730 and reduce the development time and effort to module deployment. GateXpress PCIe Configuration Manager is an FPGA-PCIe hardware engine for managing the reconfiguration of the FPGA. At power up, the GateXpress manager immediately presents a PCIe target to the host computer for discovery and enumeration, giving the FPGA time to load from FLASH. Once booted, the GateXpress manager offers multiple options for dynamically reconfiguring the FPGA with a new IP image, handling the hardware negotiation and streamlining the loading task. GateXpress also allows dynamic FPGA reconfiguration through software commands as part of the runtime application. Software support packages are available for Linux and Windows operating systems. Pricing starts at $19,495. Pentek, Upper Saddle River, NJ. (201) 818-5900.

Ultra-Fast Booting Intel Core i7Based SBCs

A new line of single board computers supports Fast Boot with Intel’s Firmware Support Package (FSP). With the integration of Intel’s FSP into its Intel Core i7-based boot loader solutions, Extreme Engineering Solutions enables ultra-fast boot times for Intel Core i7-based Single SBCs. The newly released FSP from Intel also opens the door for additional Intel-capable boot loader options beyond the legacy BIOS vendors. This facilitates an expanded ecosystem of both proprietary and open source boot loaders that can be more easily streamlined and tailored for industry-specific needs. The availability

of open source options, such as coreboot, has the added benefit of simplifying access to boot loader source code and increasing code traceability for not only the OEM, but also for the end user. Intel recently developed the FSP as a means to encapsulate the necessary initialization for an Intel processor and chipset into a single release package that any boot loader solution can build upon. Previously, this type of low-level chipset configuration was only released by Intel to a small number of BIOS vendors, who each build their own proprietary boot loader solutions and usually tailor them for the needs of the PC market. This would typically lead to a significant resource investment from the embedded OEMs to modify a complex BIOS

solution for the needs of their customers. However, Intel’s approach with the FSP enables the creation and development of streamlined boot loader solutions that will not only provide faster, more reliable and more deterministic boot times, but also reduce development time and costs. The initial products from X-ES that will be supporting an FSP-based boot loader solution will be third generation Intel Core i7-based (formerly “Ivy Bridge”) products, including the 3U VPX XPedite7470 and rugged COM Express XPedite7450. FSP support for fourth generation Intel Core i7-based (formerly “Haswell”) products, such as the 3U VPX XPedite7570, XPedite7501 XMC, 6U cPCI XCalibur4500 and 6U VME XCalibur4530 will follow. Extreme Engineering Solutions. Middleton, WI (608) 833-1155. RTC RTCMAGAZINE MAGAZINE DECEMBER OCTOBER 2013



High-Speed, Multichannel LVDS Recorders for R&D, Ground, Ship & Airborne Applications

A family of high-speed turnkey recording systems handles low-voltage differential signaling (LVDS) digital I/O. The Talon family from Pentek includes the Model RTS 2718 commercial rackmount, the Model RTR 2738 rugged portable and the Model RTR 2758 rugged rackmount recorders. Using state-of-theart disk storage technology, these systems are highly flexible and achieve aggregate recording rates up to 4 Gbytes per second.

As complete recording systems, the Talon recorders are suitable for capturing any type of streaming sources including live transfers from sensors or data from other computers. The built-in Windows 7 Professional workstation with an Intel Core i7 processor gives the user flexibility in routing recorded data to other drives, networks and I/O channels. Plus, post-processing and analysis tools installed on the workstation can immediately operate on the recorded data. Pentek’s SystemFlow recording software simplifies user operation, and the API allows system integrators to add the recorder as a peripheral to a larger system. The recorders are offered in many different configurations for operation not only in the lab but also in the field and on board vehicles, ships and aircraft. The SSDs we use in the ruggedized recorders are immune to shock and vibration and are ideal for severe environments.

Nano-ITX Board Offers a Low Power Solution with Increased Processing Performance

A Nano-ITX embedded system board is based on the Intel Atom processors E3800 product family (formerly codenamed Bay Trail, 5W~10W). The new Intel Atom processors integrate the Intel Gen 7 3D graphics engine that improves the performance to double that of the previous generation. It supports one single-channel 24-bit LVDS connection, one DisplayPort (DP) on rear I/O with resolution up to 2560 x 1600 and one onboard VGA port with resolution up to 1920 x 1200. The 204-pin non-ECC SODIMM provides maximum memory,


Pentek Upper Saddle River, NJ. (201) 818-5900

making it capable of supporting up to 4 Gbyte of DDR3L, all within a compact 120 mm x 120 mm footprint. The NANO-6060 Nano-ITX embedded board from American Portwell not only operates with thermal design power (TDP) under 10W for fanless applications, but also supports a wide industrial temperature range from -40° to 85°C for rugged applications. With its superior, up to quad cores, processing power and high capability, it generates and delivers greater and faster performance than the previous generation. The single/dual/quad-core Intel Atom processor E3800 product family provides low power consumption and advanced performance. The Portwell NANO-6060 is an off-the-shelf product designed with up to quad-core Intel Atom processor and can serve as an ideal embedded platform to be integrated into many of today’s intelligent embedded systems. Portwell also places the processor/chipset on the backside of the NANO-6060 board, which improves system thermal design. It enables true fanless configuration on an embedded solution. In addition, the NANO-6060 supports DC 12V input, one non-ECC SO-DIMM memory slot for DDR3L SDRAM up to 4 Gbyte, half-size mini-PCIE socket, dual display support by DP/VGA/LVDS, two Gigabit Ethernet, one RS-232/422/485 selectable COM port, four USB 2.0 ports, two USB 3.0 ports and one micro SD socket. It also provides one PCIE x1 slot for riser card expansion. American Portwell Fremont, CA (510) 403-3399


Data files include time stamping as well as recording parameters and optional GPS information. Files are stored in the native Windows NTFS format, allowing drive units to be read directly by PCs and eliminating the need for file conversion. Files can also be transferred from the system through Gigabit Ethernet, USB ports or written to optical disks using the built-in 8X double layer DVD±R/RW drive. Talon recorders capture data at a very high rate using the latest generation of high-capacity disk drives. The rugged portable (Model 2738) and rugged rackmount (Model 2758) are configured with SSDs (solid state drives) while the commercial rackmount (Model 2718) is configured with HDDs (hard disk drives). The drives are hot-swappable and can be easily removed or exchanged during or after a mission to retrieve recorded data. Prices start at $35,690.


Fully Packaged Rugged Ethernet Switching and Routing Solutions A complete lineup of Victory-compliant network switching and routing solutions includes the XPand6206, XPand6207 and XPand6208 from Extreme Engineering Solutions as fully integrated, ready-to-deploy, systems. These systems are high-performance small form factor (SFF) networking solutions that function as secure, standalone and fully managed switches and routers. They provide a combination of performance, size and capability unmatched in the industry and include features such as 10 Gigabit Ethernet, the fourth generation Intel Core i7 processor and a removable Solid State Drive (SSD). These fully packaged solutions integrate the Victory-compliant XChange3013 and XChange3018 3U VPX switches and routers to enable maximum networking performance and versatility using industry-standard COTS components. All three systems deliver full wire speed across all of their networking ports and support jumbo packets up to 13 Kbyte. They also support IPv6, Energy Efficient Ethernet (EEE), and a comprehensive set of IETF RFCs and IEEE protocols. The XPand6206 maximizes connectivity with support for twenty 10/100/1000BASE-T Gigabit Ethernet ports. The XPand6207 emphasizes network performance with 10 Gigabit Ethernet support, providing six 10GBASE-T 10 Gigabit ports and twelve Gigabit Ethernet ports. The XPand6208

is a fully managed 10 Gigabit and Gigabit Ethernet switch and router that also integrates the fourth generation Intel Core i7 Processor-based XPedite7570 3U VPX module and XPort6193 removable Solid State Drive (SSD). When these systems are configured as fully managed Layer 2 switches, support for features such as fast boot, flow control, MAC bridging (IEEE 802.1D), port mirroring, port authentication (IEEE 802.1x), VLANs (IEEE 802.1Q), Quality of Service (QoS), GVRP, MVRP, port and protocol classification (IEEE 802.1v), GARP, MRP, GMRP, MMRP, LACP, RMON, STP, RSTP, MSTP, RPVST+, AgentX and IGMP are included. When configured as a

Layer 3 router, support for Multicast and Unicast Routing features such as DVMRP, IGMP, PIM-DM, PIM-SM, PIM-SSM, MLD, RIP, BGP, OSPFv2/OSPFv3 and VRRP are added. Extreme Engineering Solutions Middleton, WI (608) 833-1155

RTC PRODUCT GALLERY Featuring the latest technologies in Solid State Drives

FIND the products featured in this section and more at

USB Wi-Fi Modules 802.11b/g/n Compliant

Radicom Research, Inc. Phone: (408) 383-9006

• USB 2.0 hot swappable interface • Compatible with USB1.1 and USB2.0 host controllers • Up to 300Mbps receive and 150Mbps transmit rate using 40MHz bandwidth • Up to 150Mbps receive and 75Mbps transmit rate using 20MHz bandwidth • 1 x 2 MIMO technology for exceptional reception and throughput • 2 U.FL TX/RX antenna ports • Wi-Fi security using WEP, WPA and WPA2 • Compact size: 1.0” x 1.0” x 0.25” (Modules) Web:



Advertiser Index GET CONNECTED WITH INTELLIGENT SYSTEMS SOURCE AND PURCHASABLE SOLUTIONS NOW Intelligent Systems Source is a new resource that gives you the power to compare, review and even purchase embedded computing products intelligently. To help you research SBCs, SOMs, COMs, Systems, or I/O boards, the Intelligent Systems Source website provides products, articles, and whitepapers from industry leading manufacturers---and it's even connected to the top 5 distributors. Go to Intelligent Systems Source now so you can start to locate, compare, and purchase the correct product for your needs.

Company Page Website Advanced Micro Devices, Inc............................................................................................. 52................................................................................................ Aries Electronics Inc.......................................................................................................... Commell........................................................................................................................... Congatec, Inc..................................................................................................................... 4.............................................................................................................. Digital Signage Expo.......................................................................................................... Dolphin Interconnect Solutions............................................................................................ 2.......................................................................................................... Embedded World 2014...................................................................................................... Extreme Engineering Solutions........................................................................................... 51............................................................................................................. Intel.................................................................................................................................. Intelligent Systems Source................................................................................................. 31................................................................................... Lauterbach........................................................................................................................ 22........................................................................................................ LCR Embedded Systems, Inc............................................................................................. 19........................................................................................ MEN Micro........................................................................................................................ 23........................................................................................ MSC Embedded, Inc........................................................................................................... One Stop Systems, Inc....................................................................................................... Pentek, Inc......................................................................................................................... Phoenix International......................................................................................................... 35........................................................................................................... Raytheon.......................................................................................................................... 35........................................................................................................... Real-Time & Embedded Computing Conference.................................................................. 11................................................................................................................ Solid State Drives Product Showcase................................................................................. 49........................................................................................................................................

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Module and System-Level Solutions from Intel® and Freescale™ Single Board Computers


4th Gen Intel® Core™ i7-based 3U VPX SBC with XMC/PMC


Freescale QorIQ T4240-based 6U VPX SBC with dual XMC/PMC

Secure Ethernet Switches and IP Routers


Secure Gigabit Ethernet router XMC utilizing Cisco™ IOS®


3U VPX 10 Gigabit Ethernet managed switch and router

High-Performance FPGA and I/O Modules


Xilinx Virtex-7 FPGA-based XMC with high-throughput DAC

High-Capacity Power Supplies


3U VPX 300W power supply with EMI filtering for MIL-STD-704 & 1275

Rugged, SWaP-Optimized, COTS-Based Systems


Sub-½ ATR, 6x 3U VPX slot system with removable SSDs


SFF 2x 3U VPX system with removable SSD and integrated power supply


SFF Intel® Core™ i7 or Freescale QorIQ-based system with XMC/PMC

Extreme Engineering Solutions 608.833.1155

Designed, manufactured, and supported in the USA

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