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The magazine of record for the embedded computing industry

November 2013

Small Displays Pack Powerful GUIs ATCA Gets Hardware Management Boost Ethernet Teams with PCI Express An RTC Group Publication


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6Editorial Coming Changes in the Energy Industry Bode Well for Embedded Insider 8Industry Latest Developments in the Embedded Marketplace

10 & Technology 42Products Newest Embedded Technology Used by Industry Leaders Small Form Factor Forum ARMed and Dangerous



GUIs for Small Devices — Expanded Functionality in a Tighter Space Tom Williams



Small Panel Display Technology

Advances in ATCA


Smart Panel Technology: Intelligent Control Solutions Offer Both Flexibility and Reliability Cy Hung, Adlink Technology

up to Four Independent Full HD Displays from a Single 18 Drive CPU Module Michael Miller, MSC Embedded

TECHNOLOGY CONNECTED Advances in System Connectivity Do You Communicate 22 How to Your Peers? David Hinkle, Elma


Leveraging Mainstream PCI Express Advances in Embedded Systems

ATCA Hardware 30Boosting Platform Management for Power Subsystems Mark Overgaard, Pigeon Point Systems

TECHNOLOGY DEVELOPMENT Developing Code for Hybrid Architectures

for FPGA – Bringing FPGAs 34OpenCL to the (Relative) Masses—Part 1 Ron Huizen, Bittware

INDUSTRY WATCH Battery Technology Widens Options

Batteries: New 38Rechargeable Choices, Complex Decisions Todd Sweetland, Electrochem Solutions

Larry Chisvin, PLX Technology

Digital Subscriptions Available at RTC MAGAZINE NOVEMBER 2013


NOVEMBER 2013 Publisher PRESIDENT John Reardon,


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Tom Williams Editor-in-Chief

Coming Changes in the Energy Industry Bode Well for Embedded


aw economics is starting to drive the move toward renewable energy sources. The coming shift to solar and wind will open huge opportunities for embedded technologies as well. If the price course of the automobile industry followed that of digital electronics, you could buy a Rolls Royce for $1.25.” That remark made in a conference some 15 years ago has stuck with me even if the identity of the speaker has not. I constantly marvel when after describing some new innovation, a colleague says, “Yeah, that’s real neat, but it’s cost-prohibitive.” Just wait. It will either die a quick death (so many do), or it will plummet in price and become so widely adapted as to seem part of the wallpaper. We have now reached a major milestone on the downward cost curve of another silicon technology: solar power. In fact, the cost of crystalline silicon solar cells has dropped 99% since 1977, with a projected cost of $0.74 per watt for 2013. This finally makes solar energy less expensive than burning coal while also reducing CO2 emissions at no cost to customers—and that is even before figuring in the environmental costs. If any further proof is needed, the utility Xcel Energy has submitted a proposal to Colorado to install 170 megawatts of solar and 450 megawatts of wind as the most cost-effective new power resources. For the first time, a utility has made such a proposal based strictly on economic considerations and not to meet any state-imposed renewable energy standards. In addition, the utility has decided to close its last remaining coal-fired plant by the end of 2013 rather than convert it to natural gas. These developments are not the results of any greenie tree huggery; they are cold, rational business decisions. And, of course, they have implications for the embedded industry, which will become even more engaged in building out the Smart Grid with its monitoring, networking and intelligent distribution technologies and its security requirements. Further along, the intelligence of the Smart Grid will spread from a utility-centric model to a much more distributed model in which individual homes and businesses, from their rooftops, will draw, store and distribute power in a vast dynamic distributed matrix—all of it controlled, monitored and metered by many millions of communicating embedded devices.



This will, of course, cause upheavals as most disruptive technologies do. The investment banking arm of Citibank recently released a report titled, “Energy Darwinism—the Evolution of the Energy Industry,” which predicts that today’s utilities could lose up to half of their addressable market to solar, storage, distributed generation and energy efficiency. That is, if they do not adapt by supplying such things as rooftop panels and microgrids and offering services for dynamic distribution instead of fighting it. It is instructive to note that among the factors mentioned is also energy efficiency, an element that increasingly occupies the attention of customers but has not been a high priority for utilities—for reasons that should be clear. Here again, the embedded computer industry has been at the forefront with intelligent power management in even the smallest devices as well as supplying systems for monitoring and control for large installations. The issue of storage is the one that is perhaps least developed. Storage is considered important to deal with intermittency, as can occur with wind power. Here again, the Smart Grid will be critical to route excess energy to storage and distribute it where needed. So this may not be as inhibiting a factor as previously thought. The Citibank report, however, suggests that widespread adoption will cause wind to behave more like a baseload running more continuously due to aggregation. Again, such a scenario will require intelligent management, communications and control. And storage is one of the aspects of technology that is making rapid advances even if it is behind the power sources on its cost curve. Electric vehicles also appear to be one of those technologies that may be turning the corner. Just because an S Class Tesla costs $80,000 today does not in any way mean that things will stay that way. It is always interesting to observe how technology influences business models, and it can certainly be called “Darwinian.” These technologies, for example, could completely change the nature of what we think of as an electric utility. And it is important to note that it is not only new technologies, but known technologies achieving cost/performance points and finding combinations with other technologies (e.g., solar with Smart Grid) that can cause some huge transformations. I think that is what we are looking at here and it will be fascinating to watch.



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INSIDER NOVEMBER 2013 SGET Team SDT.01 Finalizes Design Guide for the SMARC Standard The Standardization Group for Embedded Technologies (SGET) has announced the publication of the SMARC Carrier Design Guide 1.0. The guide has become available just eight months after the publication of the Computeron-Module specification for extremely energy- and space-saving ARM/SoC designs. It serves to support developers in all carrier board design issues. The SDT.01 group of the SGET paid particular attention to including numerous circuit references, which OEMs can use directly in their own designs to further minimize their development efforts. The Carrier Design Guide is now an official document of the SGET, which carrier board developers can obtain free of charge from the SGET website. The 126-page publication of the SMARC Carrier Design Guide provides complete vendor-independent standardization for the application-specific carrier boards, which is required for scalable Computer-on-Module designs. The SMARC Carrier Design Guide 1.0 offers comprehensive information for developers of custom-designed carrier boards for SMARC modules. In combination with the SMARC specification and the module vendors’ product manuals, the design guide will greatly simplify design efforts and guarantee optimal interchangeability of Computeron-Modules from different manufacturers. For reference, it includes numerous connection diagrams and external switching circuits plus descriptions of ideal implementation solutions for all SMARC interfaces. The SMARC Carrier Design Guide was produced by the different manufacturers of the SGET Standardization Group SDT.01 to ensure that carrier boards are developed according to best practice principles. As this is also dependent on the carrier board design, it was essential that a carrier board design guide be officially published in addition to the Computeron-Modules specifications.

Curtiss-Wright Acquires Parvus Corporation

Curtiss-Wright Controls has announced that it has acquired 100% of the shares of Parvus Corporation (Parvus), a business unit of Eurotech S.p.A., for $38 million in cash. Parvus is a designer and manufacturer of rugged small form factor computers and communications subsystems for the aerospace, defense, homeland security and industrial markets. The acquired business will operate within Curtiss-Wright’s Controls segment. Founded in 1983, Parvus designs and manufactures open standard-based modules and systems for command, control, communications, computers, intelligence, surveillance and reconnaissance (C4ISR) applications in the defense market and various applications in the aerospace, homeland security and general industrial markets. The company’s SWaP-optimized so-



lutions, including rugged processor systems, mobile networking subsystems and industrial grade board-level PC/104 modules, are used in critical defense applications such as unmanned systems and tactical C4ISR payloads. Product applications for the industrial markets include system monitoring, diagnostics, communications, networking and vetronics subsystem control, most notably to commercial transportation customers. Their capabilities include rapid turnkey subsystems integration and development services, and the design of complete embedded computer systems tailored to meet specific customer requirements through the use of off-the-shelf building blocks and technical expertise. Parvus, headquartered in Salt Lake City, Utah, has approximately 50 employees and is expected to generate sales of approximately $23 million in 2013.

Microsemi Licenses Secure Semiconductor Design IP from Cryptography Research

Microsemi and Cryptography Research have announced an agreement under which CRI will provide Microsemi access to CRI’s secure semiconductor intellectual property. The CRI design tools will enhance Microsemi’s security portfolio and ability to create extremely tamper-resistant semiconductors for certain government applications, making chips significantly more difficult to emulate, clone or reverse engineer. “Microsemi is delighted to bring another new security offering to the government market,” said Charlie Leader, vice president at Microsemi. “The tamper resistance and cryptographic security technologies that CRI has designed into these licensed design tools and products will enable Microsemi to deliver products that further protect our

government customers’ critical systems from serious threats.” Microsemi is already a licensee of CRI’s differential power analysis (DPA) countermeasures for its field programmable gate array (FPGA) solutions. The company’s SmartFusion2 systemon-chip (SoC) FPGA is the first SoC FPGA to provide countermeasures against DPA attacks using CRI’s technology. Microsemi provides security wherever data is collected, communicated or processed, and whenever accuracy, availability and authenticity are essential. For more than 10 years, the company’s security experts have been providing information assurance (IA) and anti-tamper (AT) cryptographic solutions and services to fortify critical program information and technology. Microsemi security products are used by U.S. federal organizations and commercial entities in applications requiring a high level of electronic security including financial, digital rights management, gaming, industrial automation and medical.

Shipments of Consumer M2M Devices Predicted to Reach 13.8 Million in 2017

According to a new research report from Berg Insight, shipments of consumer M2M devices with cellular connectivity reached 5.3 million worldwide in 2012. In the next five years, shipments are forecasted to grow at a compound annual growth rate (CAGR) of 21.1 percent to reach 13.8 million devices in 2017. This relatively new breed of connected devices—neither classified as handsets, PCs, tablets nor traditional M2M devices—has strong growth potential. Today, e-readers and PNDs are the most common consumer M2M devices already shipping in millions. The consumer device market is changing rapidly and dedicated

devices are facing fierce competition from multipurpose devices such as smartphones and tablets. Introducing wireless connectivity is one strategy to meet this threat, and new connected products such as the Galaxy camera range from Samsung as well as smaller scale success stories such as the PocketFinder from Location Based Technologies, show the market potential for cellular connected consumer devices. Emerging device categories such as personal tracking, wearable technology and digital cameras are well suited for embedded cellular connectivity and have high growth potential in the coming years. Berg Insight predicts that by 2017, smart watches will be the most sold consumer M2M device category before personal tracking devices, accounting for 23 percent and 17 percent respectively of total annual shipments. An increasing share of all content and services are delivered through the cloud, and cellular connectivity gives the freedom of being connected everywhere. The 3G-connected Kindle ereader from Amazon is the most sold consumer M2M device to date. Mobile data plans, which let users buy a bucket of data to share across several devices, as well as pay-per-use models are other promising business models for consumer M2M devices. It is not always possible to hide the cost of data such as in the case of the Kindle, but the relationship between the benefits and costs needs to be both clear and fair in order for users to be willing to pay extra for wireless data.

Elma Joins AXIe Consortium to Help Grow Existing Ecosystem

Elma Electronic Inc. has joined the AXIe Consortium to help promote and develop a robust ecosystem of AXIe products and systems for general purpose

instrumentation and automated test equipment. AXIe is an open system modular instrumentation standard based on AdvancedTCA that delivers high-performance instrumentation for aerospace defense, high-energy physics, semiconductor test and other industries. Drawing on its extensive experience with AdvancedTCA systems, Elma has developed several important products to assist system integrators in quickly developing and deploying AXIebased systems. An Intelligent Platform Management Interface (IPMI) shelf manager card offers a redundant IPMB (Intelligent Platform Management Bus) for chassis developers needing power management, cooling control, electronic keying and event sensor logging. For module developers, a new IPMI controller mezzanine card fits a standard AXIe-based module and can quickly deploy the required IPMI functionality, so users can focus on the unique attributes of their designs and provide customers with more value. AXIe uses the same PCIe fabric and programming as PXI while enabling horizontal configurations for minimal rack space and vertical layouts for large systems. In addition to easily integrating with PXI, LXI and IVI, AXIe is compatible with AdvancedTCA. It offers high-speed trigger, timing and local bus parameters as well as accommodates larger boards for the highest rack and power densities per rack inch. Founded in 2009, the AXIe Consortium currently consists of a highly focused group of companies joined together with the mission of facilitating the uses and benefits of AXIe-based systems to a variety of industry segments.

Integrated-Motor Market to Expand by More Than 40 Percent in Five Years

Integrated-motor suppliers offering this compact motor type

with built-in electronics can look forward to a 40 percent increase in total market revenue by 2017, even though growth as a whole appears to be moderating, according to a new report from IMS Research. Revenue for the integratedmotors market is projected to reach $553 million by 2017, up from less than $400 million in 2012. Brushless motors currently lead the way in growth with more than 70 percent of additional market revenues from 2012 to 2017 expected to come from the sales of AC brushless servo and DC brushless integrated motors. For perspective, these products represented only 56 percent of market revenues in 2012. Overall market growth last year, however, was limited by the recession in Europe, which accounted for 65 percent of total market revenue in 2012, noted the recently published report entitled “Integrated Motors – World – 2013.” Business will remain tepid this year, after which higher growth is expected from 2014 to 2017 as the market expands at more than 7 percent each year. Despite the rise, projected growth rates remain below historical levels. IHS has tracked the integrated-motor market for more than a decade, and yearly growth rates in the past have averaged in the double digits. In particular, the market rose by more than 300 percent between 2002 and 2011.

Oracle Demonstrates Performance and Capacity for Next-Gen Telecomm Services

A recent independently certified performance test on Oracle’s Acme Packet Net-Net 6300 confirmed that the high-end session border controller (SBC) platform meets or exceeds performance and capacity requirements for deployment in emerging services such as Voice over Long-

Term Evolution (VoLTE), Rich Communication Services (RCS), video calling and other IP-based communications services. The Net-Net 6300 was tested for session establishment rates, session capacity and registration capacity using a mix of signaling traffic that would typically be found in tier one communications service provider (CSP) networks. Net-Net 6300 enables large CSPs to scale their service delivery infrastructure to address the increasing complexity and volume of session traffic—signaling and media—which characterizes real-time communications as it continues to transition from circuit-switched to all-IP networks. The performance test results show that Net-Net 6300 can improve performance and capacity up to ten times that of Oracle’s Acme Packet Net-Net 4500. The platform leverages Oracle’s SBC software to help service providers maximize revenues and minimize capital and operating expenditures. The Illinois Institute of Technology (IIT) Real-Time Communications (RTC) Lab conducted the test with the results validated by Current Analysis. The test results show that NetNet successfully achieved a session establishment rate of 1,000 sessions per second with media and 2,400 sessions per second without media, consistently handling high call traffic volumes over an extended period. The test also achieved a registration rate of 7,800 registrations per second leading to a potential registration capacity of 1,900,000 endpoints. This demonstrates that Net-Net 6300 can support a high number of simultaneous end users during periods of high registration, such as after a power outage.




FORUM Colin McCracken

ARMed and Dangerous


mbedded engineers and developers have what it takes to conquer their application challenges. They are equipped with all the tools and weapons to slay dragons and bugs alike. They command a huge fleet of platforms containing 5090% of what the mission needs, and then build the rest themselves. The few. The proud. The embedded engineers. While Intel’s “Bay Trail” and AMD’s “Kabini” SoC families represent formidable enemies to ARM, the embedded theater is not about bits and bytes and battery hours and watts. During the 68K versus x86 wars early in the PC Dynasty, it was all about software. As before, it’s not about the best architecture on paper, such as instruction pipeline, cycles per instruction / instructions per cycle, multiple register files, out-of-order execution, register renaming, complex addressing, and the like. And yes, certainly OEMs’ processor selections played a role. But the value proposition was driven by end users’ experiences and the applications they could run. As the PC Dynasty reaches twilight and the Tablet Dynasty takes over, it’s all about software all over again. Google’s Android OS and Apple’s iOS will influence the embedded market for many years to come. In an epic twist of fate, last epoch’s winners Intel and Microsoft find themselves outside the gates looking in, trying to find a way into the low power and small form factor fortress. Recent innovations such as fingerprint recognition introduced by Apple and HTC are merely the next wave of Android and iOS features. While securely unlocking phones is handy for consumers, the technology has great potential for the broad embedded market. We think of security in terms of hackers and large IP networks. But physical authentication can provide another class of security to a wide range of machines and instruments as the technology becomes pervasive. Although iOS may remain closed and unavailable to embedded OEMs, Android has caught the attention of many a device manufacturer across market segments. We become so accustomed to how our gadgets operate, such as by clicking, scrolling and zooming in and out with our fingers, that we expect future embedded systems to behave the same way. We see new features like multi-touch capability in Linux 3.x and we can imagine use cases like soldiers zooming in and out to read schematics on rugged tablets, and doctors enlarging scan images from ultrasound machines.



It’s important that we redirect our sense of “platform” back toward software, rather than hardware. The preponderance of software available for ARM processors is what builds the value of the ARM architecture. Let’s not consider Mini-ITX or COM Express as platforms. Processors and boards merely run the code. There, human-years of investment in software development and validation is substantial compared to board and even chip designs. Faced with plenty of low-power processor architecture choices, OEMs can’t help but notice ARM’s ecosystem momentum for ultra-low-cost 32-bit embedded applications. Although late to the game with 64-bit support, the ARM architecture previously captured so much low-end software and middleware that the platform could simply grow with the times into 64-bit support when needed by the market. The same goes for security features (TrustZone) and high-performance graphics. While software is indeed the 800-pound gorilla, hardware guys need to chart their design courses. ARM SoCs are all over the map in terms of expansion buses and I/O. Though the smartphone and tablet market has locked the feature sets as the desktop PC market did for x86, many silicon vendors are not chasing the competitive tablet space with their ARM-based chips. Machineto-machine, automotive and other applications dictate completely different I/O. Board vendors who want to create and/or follow form factor standards need to be very selective about the processors they support. It shouldn’t take a 300-pin connector to bring ARM SoC signals off a module. How board vendors can be profitable supporting small volume OEMs presents a new challenge to x86 board houses. While Intel and AMD are mounting attacks on the traditional embedded ARM space, the ARM empire is threatening a full-on assault against the underbelly of the traditional embedded x86 space. Nowhere is the ecosystem more evident than at the many annual ARM shows and conferences including the recent ARM TechCon 2013 in Silicon Valley. ARMed with compilers, JTAG debuggers, OSs, middleware, processors from dozens of silicon vendors, off-the-shelf modules and even tiny Pico-ITX SBCs, warriors in the ARMy are conquering territory previously held by other processor architectures in many low- to mid-performance embedded applications.

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GUIs for Small Devices—Expanded Functionality in a Tighter Space The functionality of mobile and handheld devices keeps growing and well-designed graphical interfaces are meeting the challenge, presenting users with a familiar mode of operation. Now a tool specifically designed for such needs is available. by Tom Williams, Editor-in-Chief


here was a time, but that time is past, when graphical displays in embedded systems were relatively rare and touchscreen user interfaces were completely unheard of. Today, of course, we have become accustomed to interacting with devices in home and industry through a graphical user interface (GUI). It is becoming almost a reflex. Who among us has not at one point sat in front of a laptop running Windows 7 and reached out with a finger to make the screen scroll? C’mon! We are witnessing a convergence of trends. One is a blurring of distinction among embedded devices that are increasingly showing up in consumer products— from smartphones, tablets and home appliances to industrial control systems and a vast array of handheld mobile devices. Another is the increasing richness in features of many small systems. There is literally not enough physical room on the surface of these things to fit all the buttons and switches that would be needed to operate them.



The solution of a graphical GUI seems natural to a population of users already accustomed (if not addicted) to the smartphone/tablet touchscreen world. This has come to be known as the “iPhone effect” and is influencing GUI design across the board. This has also spawned the “bring your own device” (BYOD) phenomenon where access to a company’s applications and even to control of medical and factory equipment is enabled from an employee’s smartphone or tablet (Figure 1). Until now, most GUI development tools have been oriented toward the desktop and embedded solutions have been derived from these, and that has meant a fairly big footprint in terms of memory and resource usage. Now, however, Express Logic has introduced a low-overhead runtime engine and development tool called GUIX, which runs on Express Logic’s ThreadX RTOS, and a PC-based development suite called GUIX Studio. GUIX is initially targeted for the ARM Cortex-M class of processors and the mid-

range Texas Instruments and Renesas processors. Eventually, of course, the plan is to adapt it for all the CPUs that Express Logic supports. GUIX runs natively on the processor and is compiled from ANSI C source code. Its central function is to write graphical data to a block of display memory and to pass events back to the application’s event handler. Inputs can be touchscreen or pen-down events, which GUIX passes to the application. It would simply communicate, for example, “User picked entry #32.” The application developer must decide what action is to be taken. The application will then do whatever operations are required and pass pixel data on the results back to the GUIX API layer to write the appropriate pixel data to the display memory. Of course there is a wide variety of different LCD displays, but they mostly operate by reading pixel data in their memories (or from system memory), interpreting it and putting the resulting colors at the appropriate pixel locations. GUIX supports all the common formats from 1-bit per pixel up to various 24- and 32-bit pixels with RGB, BGR, etc., by supplying drivers for the different formats to write that pixel data to display memory.

FIGURE 1 The functions displayed on this medical device may not be the only ones that it supports. A hierarchy of widgets and controls can be accessed to sequence through a wide variety of available functions. The display data is linked to the application logic via APIs that can transmit data, commands and resulting displays between screen and code.


The data flow in GUIX involves input drivers such as touchscreen or timer drivers that invoke GUIX APIs to inject events into the framework. Application threads also invoke GUIX APIs to create and display screens according to the internal processing of the application. GUIX widgets react to user input to generate signals that are routed back to application event handlers. A hardware-specific, optimized graphics driver writes the pixel data to display memory from where it is rendered to the screen by external or onboard dedicated hardware, depending on the specific display used (Figure 2). We already mentioned the lack of surface area for all the buttons some devices would need. Of course, there is not much surface area on a small device display either. However, a GUI can deal with almost any level of complexity by implementing a display hierarchy where, for example, selecting a certain widget would lead to a screen displaying a variety of options and operations associated with the choice. A good part of the art of designing GUIs is to set up and organize a logical hierarchy and to manage it via the application. GUIX provides the ability to transition between screens and can stack screens instead of having to regenerate the pixel data each time. The ability to stack screens is, of course, dependent on resources, such as how much RAM you want to devote to stacked screens. It can perform much faster if, for example, you are drilling down in a menu from screen to screen.

A Desktop Development Tool

While it is possible to define widgets and screens in code using GUIX, it would be quite time-consuming. A desktop development tool called GUIX Studio allows rapid prototyping of designs in a WYSIWIG environment and can then generate the code to be dropped into the application. GUIX studio lets you specify things like button size, shape, color, position, etc., and the function that gets called by a given widget. It also lets you define and organize the display hierarchy so that it can be quickly mated to the applica-

Input Drivers

Application Threads

Application Threads

GUIX Event Router

GUIX API Layer GUIX Framework and Widget Library

GUIX Graphics Driver

Graphics Data Memory


LCD Screen

The GUIX data flow diagram.

tion’s API. In this sense, it is keeping the display data separate from the application code. The data is married to the code using GUIX studio in the course of developing the application. In addition, GUIX Studio has integrated font generation that lets developers generate their own in monochrome or anti-aliased formats. Fonts can include any set of characters including Unicode characters. In addition, developers can import graphics from JPG, BMP or PNG files and convert them to compressed GIUX pixel maps. There are also widget types available that can incorporate proprietary graphics for custom look and feel. It is also possible to customize existing stock GUIX widgets. The GUIX Studio environment running on a PC is able to generate the code that runs on the native processor and can be used in two ways. It can be used alone, in which case there is some additional coding involved in mating it to the target application and the ThreadX RTOS. Or it can be used on the PC along with a PC version of ThreadX. Since GUIX is coupled with ThreadX on the target, this means the generated GUI code should match the RTOS with no issues. Since this is actually all compiled C code, it is possible to run the GUI in the RTOS environment with the application

on the PC and have it all work like it will on the target system. This has other advantages. Since it is not necessary to be a programmer to work on designing a GUI with GUIX Studio, other team members involved with product development can get involved with defining the user interface. Since the code that defines the user interface is completely distinct from that of the application, there is little opportunity for non-programmers to interfere with the application logic. They can, however, help define the system’s functionality by designing screens and widgets and communicating their desired functions to the programming team. The distinction between display data and code also comes in handy when testing for certification and compliance for things such as medical devices. Making changes to the internal processing of the code need not entail making corresponding changes to the display data as long as it is already designed to display the desired inputs and outputs. Express Logic San Diego, CA. (858) 613-6640. [].





Small Panel Display Technology

Smart Panel Technology: Intelligent Control Solutions Offer Both Flexibility and Reliability By separating the control unit, which runs the display and control programs, and the communication unit, which accesses the devices under control, modern panel PCs can address a wide range of industrial, medical, transportation and other control applications. by Cy Hung, Adlink Technology


he Industrial PC (IPC) industry is a competitive and demanding market that continues to evolve with a wide variety of solutions. Relative to traditional automation applications, the maturation of PC and networking technologies has enabled the IPC industry to expand into new vertical markets, such as automotive, medical and information technology (IT). Across markets, smart control has become a key aspect of today’s IPC system designs, where the central control unit can operate with a longer up-time, lower power consumption and low radiation emissions, and must be built to industrial grade standards (Figure1). In an IPC design, the control unit can be viewed as the command center for directing traffic and data transfers between individual devices within a system. Today, embedded systems and general purpose systems form the two major directions for IPC design and overall advancements in computing technologies. The control unit can be further classified into single board (main board, module board) and equipment categories, whereas the Panel PC and Box PC are differentiated by the level of integration of the system. Evolution of the control unit is an ongoing process



FIGURE 1 Smart control is a key aspect of today’s system designs built to industrial grade standards.

that conforms to a wide variety of market demands. While the general purpose PC design is focused on pushing for more speed and compute capabilities, industrial embedded system design offers added complexity through restrictions on form factor and requirements for longevity and remote control capabilities.

The Panel PC is currently constrained by the single board control unit and lacks the necessary expandability and customization features to meet industrial application demands. Thus, up to this point, customized systems have been developed from scratch in order to accommodate specific application requirements.


FIGURE 2 Today’s COTS all-in-one smart panel systems offer high flexibility and reliability with SFF I/O boards and expansion ports.

However, over the past several years, commercial off-the-shelf (COTS) displays have evolved into highly integrated smart control units, or smart panels, that offer expansion capabilities for customization, as well as small form factor (SFF) and low power board designs suitable for embedded IPC systems (Figure 2).

Ultra-Low-Power SMARC Offers New Possibilities in SFF Design

In terms of small form factor offerings, computer-on-modules (COMs) are an attractive option for IPC designs. One of the most recent COM standards, Smart Mobility Architecture (SMARC), was developed to provide a smaller profile and lower power alternative to current COM standards—such as COM Express—in order to develop ultra-low-power applications for small, thin form factor mobile or stationary devices, such as instrumentation, emergency medical devices, industrial tablets and human machine interfaces (HMI). The SMARC standard was established by the Standardization Group for Embedded Technologies (SGET), comprised of leading embedded companies and including ADLINK. In its initial stage, SMARC merely defined the standard processor architecture of ARM and system on chip (SoC). However, with the launch of SoC for x86, which offers much lower power consumption, the industry will see a more rapid response to the standard and market demands for the SMARC with x86 SoC combination. As an example of a COTS smart panel design, a SMARC dual module design

can feature a single board CPU module (SMARC module) connecting to a baseboard through a 314-pin B-to-B connector. The SMARC module is 82 x 80 mm and designed for low power consumption and high expandability. Although market demand dictates the application of either an embedded or general purpose system, the SMARC design with dual module configuration is able to fulfill a wide range of system requirements for both types of systems. For instance, in automated automotive control applications, the onboard embedded system can be used for monitoring and information feedback on an individual vehicle; whereas, a general purpose system is better suited for processing a fleet of vehicles for real-time monitoring of driver and vehicle behaviors. The baseboard can be designed around the control unit to include the basic I/O ports (USB, LAN), wide input voltage (e.g., 9-36 VDC input), touch control chip and communication modules such as Wi-Fi, Bluetooth, high-speed uplink packet access (HSUPA), LTE etc. based on customer specifications. Furthermore, this baseboard can also offer expansion ports to support additional applications after designs are finalized. In industrial automation systems, the power source can be isolated with a connector board to avoid unnecessary damages and losses. In home automation systems, the digi-

tal or analog I/O board can be designed with various switches to corresponding signals. These are just some examples of the flexibility and versatility offered by the dual-module design with expansion ports that can quickly fulfill customer and market demands (Figure 3). Thus in an industrial automation scenario, for example, each segment can use different embedded control units based on diverse mission requests to reduce costs. Because high-performance computational needs and capabilities are required by master control, standard control units can be used for real-time messaging (Figure 4). While the SMARC module offers performance upgrade options, system reliability and stability are also key aspects of the control unit, which smart panel design can address through cooling and fan modules. The fanless SMARC module dissipates heat through the metal casing. Even with the low power consumption design, the choice of metal and thermal coefficient is critical for an effective cooling performance. Using an aluminum magnesium alloy with cooling fins on the back plate can quickly remove heat from the source and improve product stability. As the SMARC module houses the main sources of heat (CPU and RAM), thermal and casing designs can be simplified with reduced time-to-market for customers.

FIGURE 3 The SMARC design with dual module configuration will be able to fulfill a wide range of system requirements




Control & Communication

FIGURE 4 Example of an industrial operation where different stages can take advantage of different control unit configurations.

Standards based FPGA Development Platforms for Transportation Management & Control Systems

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Untitled-2 1



Driven by the IT revolution, HMI has evolved from the man-machine interface (MMI) of the 70s and the human-computer interface (HCI) to greatly change our lives and professional careers following the industrial revolution. From the earliest text interface with keyboard and mouse, to the touch interfaces of today’s products, the HMI has been continuously revolutionized and refined. Today’s smart panel designs offer control and communication interfaces to guarantee consistency and visibility for the operator. The control interface is enabled by a resistive or capacitive touch screen. Resistive technology relies on a drop in voltage in a pair of X and Y driver circuits due to pressure exerted on the touch screen. The controller then calculates the coordinates by the voltage drop ratio. In other words, coordinates are calculated from the change in current due to exerted pressure on the touch panel. A capacitive touch screen features a screen surface coated with a capacitive material, forming a uniform electric field discharged from the four corners. Once a conductive object (e.g. the human finger) comes into contact with the panel surface, a small amount of current flows onto the object, changing the capacitive properties. The controller then calculates the X and Y coordinates by the current flow ratio. The communication interface offers low, intermediate and high-end display panels. For example, the high-end displays feature higher brightness and better visibility for outdoor applications or on a ship/vessel. Overall, today’s smart panel technology greatly improves control unit design in order to offer a higher degree of customization to both embedded and general purpose IPC systems. Generally speaking, the levels of smart controls and performance are the main criteria when selecting a controller, and current smart panel designs offer complete, integrated, intelligent solutions for fast time-to-market. ADLINK Technology San Jose, CA. (408) 360-0200. [].

7/9/13 10:56 AM



Small Panel Display Technology

Drive up to Four Independent Full HD Displays from a Single CPU Module Demanding visualization applications often require up to four high-resolution displays. High-performance COM Express processor modules with AMD’s Embedded R-Series Accelerated Processing Units (APUs) that have a wide range of digital display interfaces are suitable for these complex tasks. by Michael Miller, MSC Embedded


he requirements for the communications interface between human and machine in the industrial environment are characterized by the capabilities of television and personal computer technologies from the consumer sector. Professional display systems may not be inferior to television or video entertainment systems, but at the same time they must fulfill high industrial requirements in terms of robustness and durability. This is true particularly for applications in automation technology and process visualization, but even more so in the fields of digital signage and point of information (POI). Today, high-resolution full HD visualization is standard, and even higher resolutions such as 4K (four times the resolution of HD) lie just around the corner. Therefore, industrial solutions are needed in order to quickly and simply implement these requirements in new projects. In the past, it was often common that the graphics integrated on the board had sufficient resolution for driving the display systems. Additional, external graphics cards were used for more demanding systems. However, through the fusing together of CPU and graphics units into one chip and the ongoing miniaturization from a three-chip to a single-chip solution, new products are coming onto the market that are now also designed for more demanding requirements. The direction



FIGURE 1 Increasingly popular video walls consisting of at least four high-definition displays benefit greatly from the ability to control all four displays from a single module.

of development in this area is clearly defined: Higher resolution displays and the capability to drive multiple displays. The design cycle of human machine interface (HMI) systems can be optimized by the use of a high-performance processor module that integrates all standard

PC functions. The Computer-on-Module (COM) is easily mounted via a standard connector on a baseboard, on which all application-specific functions are implemented. The embedded modules, which come in standardized form factors, are available in different versions with a


choice of processors. The established PCI Industrial Computer Manufacturers Group (PICMG) COM Express form factor is offered for high-end platforms. Although two graphics interfaces (VGA and LVDS) were sufficient for the first COM Express modules, additional digital interfaces were added in the latest revision of the specification. With the shift from Type 2 pin-out to Type 6 pinout in the new COM Express profile, up to three digital display interfaces are supported in addition to fast USB 3.0. Digital display interfaces, especially DisplayPort (DP), have basically replaced analog interfaces. However, due to compatibility issues, VGA has not yet been completely eliminated. An additional embedded DisplayPort (eDP), which optionally can also carry low-voltage differential signaling (LVDS), is provided for a device internal display. DisplayPort (DP), specified by the Video Electronics Standards Association (VESA), is an interface for the transfer of audio and video signals between processor and display. Image data with a resolution of up to 4096 x 2160 pixels at a frame rate of 60 full frames per second can be transferred using DP. 3D applications with full HD images at 120 Hz are also possible. The usable resolution is, for the most part, independent of the cable length. The maximum data rate of DisplayPort (DP) is 5.4 Gbit/s. Systems that can drive multiple independent displays from a single CPU module can be built using the additional digital display interfaces. No external components such as an external graphics card are necessary for these solutions. This reduces costs and facilitates streamlined system integrations. At the same time, the long-term availability of the devices, which is still a problem for graphics cards, is improved. In principle, only three full HD monitors can be driven from the three DisplayPort (DP) interfaces. However, in many cases—for example, building a 2x2 video wall—it is better to be able to connect four independent HD displays together (Figure 1). Furthermore, multi-monitoring applications with four displays are rapidly gaining importance. For example, processes can be visualized on one screen, and camera images, status indicators or

a Windows application displayed on the other screens. Alternatively, it is also possible to drive a 4K monitor with a resolution of 4096 x 2160 pixels. A high-performance COM Express processor module (Figure 2) in compact form factor, based on AMD’s Embedded R-Series Accelerated Processing Unit (APU), can be used to drive the HD displays. The APU features very powerful graphics and high parallel computing performance with low power dissipation. Although only three DisplayPort (DP) outputs are available, four independent full HD displays can be driven— without an external graphics card. Several possibilities for the realization are, in principle, available. First, thanks to the multi-stream transport (MST) technology, a DisplayPort (DP) hub mounted on the carrier board or mounted externally delivers two separate streams for the two monitors. Onboard mounting of the MST hub obviously increases the system costs. The remaining two outputs (DP0 and DP1) continue to deliver DisplayPort (DP), High-Definition Multimedia Interface (HDMI) or Digital Visual Interface (DVI). Another option is the use of a DisplayPort (DP) daisy chaincompatible monitor. The display is connected to the DP2 output and also drives the fourth monitor.

FIGURE 2 The MSC C6C-A7, a COM Express Type 6 high-performance module family in a compact form factor, is based on AMD’s Embedded R-Series Accelerated Processing Units (APUs).

The third solution is achieved without additional hardware or special monitors. Three DVI monitors are driven directly via the three digital ports. A fourth display uses part of the multi-functional PCI Express x16 signals (PEG) as DVI port (GFX connections in Figure 3). At least two of the displays must have the same resolution, otherwise the effort required for the special graphics driver will be too complex. The latter cost-optimized solution is implemented in MSC Embedded’s highperformance MSC C6C-A7 COM Express module family, based on AMD’s Embedded R-Series Accelerated Processing Units (APUs) with quad-core or dualcore processors. By means of MPEG4-, MPEG2- or H.264-decoding, two full HD video streams can be decoded simultaneously. A video compression engine (VCE) accelerates the encoding of HD video streams and enables real-time transcoding. By mounting additional, external graphics cards for driving four or six monitors, up to ten displays can be driven with the Computer-on-Module (COM). AMD Eyefinity technology is a solution developed by AMD that supports the drive of multiple displays using a single enabled AMD R Series APU. This technology is now available on a COM Express compact form factor. Eyefinity allows the connection of six independent display contents on just one graphics processing unit (GPU). Due to the simple configuration and flexible upgrade possibilities, the monitors can be used in various landscape and portrait modes. Thanks to the software, for example, the distortion that occurred with video walls caused by the monitor frames can simply be “calculated out” and thereby compensated for. For applications with vast amounts of data—for example, high resolution image acquisition— besides the CPU cores, the high-performance arithmetic units of the graphics controllers can be used for floating point, vector and image processing tasks. This is possible thanks to uniform programming for various high-performance hardware architectures through the vendor-independent, non-proprietary programming platform Open Computing Language OpenCL. OpenCL is an open and royalty-free programming standard maintained by the




DDR3 Ch. A


DDR3 Ch. B Sandy Bridge-Mbl Ivy AMD Bridge GFX [8x] PCIe[0:3]




RESET#, Status/Ctrl

FAN Connector








FCH Hudson D3




4x USB 2.0 / 4X USB 2.0/3.0



VGA Translator


4x SATA-6G




2x PCIe x1





SPI Bus 2xExpressCard support, Misc.



PCIe x1




4x USB 3.0





HD Audio









Board Controler




VGA Main Link

COM Express Connector A/B Type 6


LVDS Translator



Embedded DP1 R-Series DP2 GFX [4x] DDP_B APU GFX [4x]




4x PCIe x1

DP/eDP/LVDS (2ch/24bpp)

JTAG/ Debug

COM Express Connector C/D Type 6


µSD Card Socket



FIGURE 2 Block diagram of the MSC C6C-A7 CPU module with digital display interfaces.

Khronos Group. The Khronos Group is focused on the creation of royalty-free open standards for parallel computing, graphics and dynamic media on a wide variety of platforms and devices. The OpenCL specification consists of the language specification as well as Application Programming Interfaces (APIs) for the platform layer and the runtime. The language used is based on a subset of ISO C99, which is a popular programming language among developers. Thanks to the hardware-independence and easy portability of OpenCL, companies can reuse their substantial investment in source code and thereby significantly optimize development time and time-to-market of modern, complex



image processing systems. In order to use the advantages of OpenCL, COM Express processor modules with AMD’s Embedded R-Series APUs support this standard. Furthermore, appropriate starter kits and carrier boards are offered for early evaluation and for prototyping of COM Express module-based systems. The capability to drive four full HD displays is interesting in a wide range of applications such as process visualization, medical technology for complex image processing and in monitoring systems, for example, flight control systems. Additional applications can be found in the fields of infotainment, point of sale (POS), point of information (POI) and kiosk sys-

tems in transportation and casino gaming applications with multiple distributed displays. MSC Embedded San Bruno, CA. (650) 616-4068. [].

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CONNECTED Advances in System Connectivity

How Do You Communicate to Your Peers? In OpenVPX Systems, Ethernet over PCIe is a growing trend. by David Hinkle, Elma


penVPX provides many choices on how to use the high-speed interconnects provided in the standard’s various backplane profiles for your data plane fabric. Generally speaking, when you are designing a solution, you have to choose the protocol you want to use to communicate over the data plane in order to find products with the hardware layer that provides the needed capability. So, if you want to use PCIe (PCI Express) for your data plane fabric, you would look for boards that have the hardware on the boards to provide PCIe ports to that fabric. Likewise, if you want to use Socket Based Application

Socket Library

Ethernet on your data plane fabric, you would look for products with Ethernet chips on the boards. From a hardware perspective, these two protocols appear to be mutually exclusive, forcing you to choose one or the other for data plane traffic.

Have Your Cake and Eat It Too

Both PCIe and Ethernet, ubiquitous protocols used in solutions in the embedded market, are well understood by application developers, and customers have many legacy applications that have implemented these protocols. Wouldn’t it be convenient to use both protocols over

Embedded Application Direct IPC Library

User Design

DCOM Library


Network Applications

the same hardware layer, without any additional effort by the developer? Before we go there, however, let’s talk about the possible uses of both of these protocols. First, let’s look at PCIe. Most people accept it as a very high speed way to communicate from a host root complex CPU board to some end nodes performing a variety of possible I/O tasks.Developers just assume there will be driver support to make this all happen, which is true in most operating systems available in the embedded computing space. The application developer is able to use these resources without much additional

User C/C++ Applications

Virtual Ethernet

I/O Device

Transfer Layer

Frame Pool


OS System Modules


Concurrent Technologies’ Modules

IDC Memory Copy Engine

Platform DMA

FIGURE 1 Typical Layer Stack (diagrams courtesy of Concurrent Technologies and Interface Concepts).




Shared Memory

Fabric Interconnect Communication Modules VPX/AMC/VXS on Ethernet/PCIExpress/Serial RapidIO

Kernel Modules

Kernel Functions

Socket Layer TCP/IP Stack


Switch DMA



Aperture Manager

TECHNOLOGY CONNECTED effort; life is good in an orderly hierarchal PCI domain where you have a single root complex and multiple end nodes providing I/O such as graphics boards or storage controller boards. But when you need multiple processing boards in your solution and you start adding peers, you quickly run into issues, such as how to handle communication between the multiple root complexes. Generally, this is easily solved by using the concept of non-transparent PCIe nodes, which basically isolates the two domains. These multi-domain/root complex designs are very common, but communicating from one domain to the other creates a need to develop code to set up and configure the various bridges/switches in these domains. This is so that the nontransparent node will allow applications to pass traffic through a non-transparent node and access things on the other side. This is fairly well understood by PCIe device driver developers, but not necessarily by the application developers, who only want to use some resource on the other side of a non-transparent node. So projects with non-transparent nodes in a multi root system that will require access through non-transparent bridges to other devices need a device driver-type developer resource who understands how to develop drivers to configure the devices in the system. The need for this additional configuration and device driver work is nothing new here; it has been happening this way for years in the PCI space. What is compelling and makes someone consider adding this type of driver support to their solution is that PCIe’s performance has continued to double from GEN 1 to GEN 2 and now GEN 3. This allows for higher speed bandwidth of up to 8 Gbit/s per lane, and because PCIe easily scales from x1 (one lane) to x16, it’s just understandable that application developers would want to take advantage of that performance to communicate to their peers over PCIe. Ethernet, on the other hand, is the de facto protocol used by many application developers when a solution requires sending and receiving data to other peers in a multi SBC system solution. The software model for communicating over Ethernet to another SBC is well understood by application developers where the usual challenge they have is meeting the performance requirements.

While Ethernet has continued to increase in performance with many 10G Ethernet ports becoming available in embedded solutions, it has not grown at nearly the rate of PCIe. Higher speed Ethernet solutions such as 40G Ethernet are available in the general market, but not readily available to the embedded market. The hardware costs of these higher performance Ethernet chips are also a concern. When looking at the cost to implement boards with these 10G and up chips, it is not nearly as attractive as the much lower cost and higher performing PCIe chips, which are used everywhere. Another issue to consider is the overall latency introduced by the standard Ethernet stack’s interaction with the CPU over these chips. Many of the newer chips have “offload” engines to help, but at an added cost.

You Really Can Have It Both Ways

Now back to the original thought of having your cake and eating it too. What if you could use the application developer’s knowledge of implementing software using Ethernet but provide a “middleware” layer to replace the Ethernet hardware layer, which would preserve the standard APIs everyone is used to? Figure 1 shows some typical stack breakdowns of middleware from a couple of vendors that provide this capability for their products. As noted, several companies already offer this “middleware,” with some going beyond just Ethernet over PCIe and providing a host of options to the application developer for communicating to a peer. But basically, for Ethernet over PCIe, they all use the low-cost, low-latency PCIe hardware to communicate at the physical layers and present the upper layer Ethernet APIs to the application developer, as if they were working with hardware-enabled Ethernet ports. Some of the companies providing products that support their own SBCs and switches include Concurrent Technologies with its FIN-S (Fabric Interconnect Networking Software) and Interface Concept’s Multiware offering. Several other SBC and switch vendors providing solutions to the VPX market also provide this capability. Although companies each have their own middleware version, the common thread is that—from the perspective of

the application developer—they are using a standard, well-known API to communicate, just as if they were using an Ethernet hardware-enabled board. This provides portability of applications, which is key to many projects as they move forward to new architectures that try to improve performance.

The Proof Is in the Pudding

A couple of examples of Ethernet over PCIe performance support why this is a growing trend. First, PLX indicates in a presentation regarding performance that it has seen Ethernet over PCIe 2.x on a x8 port at around 40 million, 64-byte random writes/sec and 21 Gbit/s throughput (2x 10 Gb Ethernet). Also, Concurrent Technologies recently shared performance information in a white paper it developed highlighting their product. In that white paper, the company indicated that it has run benchmarks showing performance of Ethernet (packet sizes over 2K) over PCIe GEN 2 x4 ports outperforming a 10 GbE PCIe GEN 2 x8 Ethernet card by almost 2 to 1. Also shown is the CPU utilization comparison clearly demonstrating that, at the higher packet sizes, Ethernet over PCIe can drop CPU utilization to around 5% vs. a 10 GbE utilization of around 10%. Most of the performance numbers indicate what can be done with GEN 1 and GEN 2 chips. With GEN 3 now more readily available and providing yet again a doubling of bandwidth at a cost point much lower than what you would need to pay for a 10 GbE chip solution, the performance that customers are looking for is now available.

So Who Needs It?

Applications where streaming I/O is needed would greatly benefit from Ethernet over PCIe and represent an area that is becoming increasingly prominent in the VPX space. As a solution provider, Elma Electronic integrates payload boards from multiple vendors in order to provide the solution our customers demand. OpenVPX provides a rich selection of solutions from multiple vendors (Figure 2). Mixing vendors is generally a non-issue. An issue that often arises when defining a solution with RTC RTCMAGAZINE MAGAZINENOVEMBER OCTOBER 2013


TECHNOLOGY CONNECTED with multiple SBC boards; it works out of the box with the added middleware. For those problems needing multiple SBC board solutions that need to pass data at high speeds between them as well as still needing the old traditional host peripheral structure that PCIe provides, it is time to explore this new capability and enjoy the ease of use and resulting performance. FIGURE 2 SBCs from both Concurrent and Interface Concept. They use the latest Intel chip (fourth generation) along with their respective middleware packages.

peer-to-peer communication is providing a solution that application developers can start working with—an applicationready system. We had to propose one of two choices, either they had to develop the device driver level code, or Elma needed

Untitled-7 1



Microchip Technology Chandler, AZ. (480) 792-7200. [].

to create it for them at an additional cost. We now can solve the problem by including middleware to ease their development. This gives the customer comfort in knowing that they do not need to do “custom” driver work to make their system operate

7/9/13 11:03 AM

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CONNECTED Advances in System Connectivity

Leveraging Mainstream PCI Express Advances in Embedded Systems Embedded systems can take advantage of the solutions being driven by the data center market, using the high-volume cost points and powerful components in ways that are an even better fit to the embedded market than they are in their original usage.

by Larry Chisvin, PLX Technology


here has been a trend in the embedded world to use high-volume devices and software whenever possible for the dedicated, closed systems that populate this market. Except for successful consumer devices, the volumes of embedded products do not warrant having customdesigned components beyond the specialized functions that are unique to the platform. This approach allows the designers of embedded systems to make use of the wide range of high-performance, low-cost, power-efficient components, software development systems (compilers and debuggers) and analysis equipment. This is especially true in the area of interconnect, since it is difficult, expensive and time-consuming to create a dedicated method of interconnection when there are so many existing methods to provide this capability. Embedded system designers would prefer to focus their limited engineering dollars on where they add value, rather than in reinventing transport mechanisms that provide limited additional benefits. Some examples of general-purpose embedded interconnect usage are AdvancedTCA (ATCA) and PXI Express. ATCA provides the traces for a variety of different existing interconnect standards, specifying an efficient form factor but al-



lowing standard components to be used to construct the backplane. PXI Express takes the PCI Express (PCIe) standard as its basis and adds measurement and automation improvements. There are several recent trends in the interconnect world that have a direct and beneficial application to embedded platforms. These are being deployed in the data center, where the volume being driven by the explosion Figure 1 of Internet-related traffic is high enough to justify the expense of

creating specialized subsystems. But the same constraints that are forcing the innovation—power and space at affordable cost points, coupled with high performance— apply directly to many embedded applications. As difficult and expensive as it is to apply power and to cool a data center rack, for example, it is even more challenging in an embedded context, where the power and cooling distribution may be limited—and in many cases the system is powered by a battery. Compounding the difficulties, some

CPUs all have common access to the storage and comm CPU


PCIe Switch Network

Converged subsystems

CPU Comm

Data sent to storage with or without processing

Data Input

FIGURE 1 A converged system uses a common interface fabric so that functional components have equal access.

TECHNOLOGY CONNECTED embedded applications cannot provide a fan or heat-sink due to size constraints. The trends that are addressing these constraints are convergence and shared I/O—two sides of the same valuable coin.

Convergence: A Question of Efficiency

Convergence describes an approach to interconnect where the building blocks are separated—or disaggregated—rather than combined into fully functional subsystems. An aggregated system is best understood by looking at a client server, or traditional rack-based data center server. Each motherboard or blade has a CPU, storage and communications, and is self-contained. This is convenient and allows the system to use the same components and subsystems as the even higher volume client server systems, but it is highly inefficient for a number of reasons. For one thing, aggregation tends to delay innovation in the majority of the functions. Since it is time-consuming and expensive to create new blades and motherboards, designers tend to wait until a new processor is available and then include the most up-todate storage and communication devices on the same board at that time. Since the communications and storage devices deploy improvements on their own cycle, they are by definition not going to be updated when the newest innovations are ready; they have to wait until a CPU is ready. Storage technology in particular is changing rapidly as solid-state drive (SSD)based systems are being rapidly brought to market. This constraint is especially inefficient in embedded applications, since the storage subsystem is often the critical part of the package, where large amounts of data are being acquired for later processing. And embedded systems often have very long lives, so the subsystems become obsolete long before a new system is ready to be deployed. The mix of processing power, storage capability, communication speed and interconnect protocol varies depending upon the application. Since it is too expensive and complicated to provide systems with a sufficient number of permutations, and since there is usually some minimal amount of each function that is needed, there is almost always going to be wasted capability somewhere in the system. As

Figure 2

Special Purpose Processing Storage µCPU

PCIe Switch Network

Expansion Capability

High Perf CPU Comm Data Input

FIGURE 1 Creating Powerful Hybrid Systems by adding functions as needed.

true as this is with a data center application, it is even more so in an embedded context, since—unlike the data center—you cannot dedicate boxes to specific applications that better suit the configurations needed. In an embedded product, you often only have that single system. It is difficult to expand or upgrade the system quickly and easily, since you cannot just add more storage, for example, without getting more of the other components you don’t need. Convergence solves these problems. In a converged (and disaggregated) system, the individual subsystems—processing, storage and communications—are separated and interact through a common, high-speed, low-latency interconnect (Figure 1). Each subsystem can be upgraded or expanded based on the newest technology, and as needed for the application. For example, a protocol analyzer can be tuned to have extremely high-speed storage, in which the raw data is streamed to fast SSD devices, where it is analyzed in a non-realtime manner. Or it can be enhanced to offer very high processing capability, where the data is inspected and analyzed in real time. It has become clear over the past several years that the most effective converged interconnect in the data center world is PCIe. This interconnect is fast. It can scale up to 64 Gbit/s in each direction with an easily deployed x8 Gen3 connection. It is low-latency (~150ns/switch hop) and is already a native connection on almost every device necessary to create a compelling embedded system. There are technologies that will be deployed over the next several

years that will enable PCIe to provide an even more complete fabric for the data center, such as ExpressFabric from PLX Technology, and embedded applications can take advantage of these same enhancements to create powerful dedicated systems.

Shared I/O: The Enabler of Truly Converged Systems

One such enhancement is the ability to share I/O devices across multiple CPUs in a system. The discussion above explained why it is more efficient to disaggregate the elements of a system, but it pretty quickly becomes clear that this only makes sense if you can share the storage and communication among multiple processing elements. Otherwise, you will still be limited in the amount of I/O that you can use in a system. In this way, sharing I/O is a precondition to a truly converged system. In the data center world, processing elements have grown so power-hungry that they cannot be housed in densities that allow efficient deployment. This is even more of a factor in embedded applications, where the constraints are generally more stringent for the reasons explained above. Data center systems are experimenting with a concept called microservers, where a larger number of less-powerful CPUs are connected together, and this provides a lowerpower and more cost-effective approach where the application is either inherently distributed, or where a large single application can be decomposed and processed in parallel. Because of the value of this apRTC RTCMAGAZINE MAGAZINENOVEMBER OCTOBER 2013


INDUSTRY WATCH proach, microserver platforms are coming to market in record numbers. The applications that satisfy this approach in the data center—such as Web hosting—are a subset of the total. Embedded systems, however, are an attractive match for this new approach. Most embedded applications are bounded and predictable (unlike a general purpose server in a cloud data center), and because of this they can be written to take advantage of the underlying hardware that makes up a microserver. A data analysis platform, for example, is inherently well-suited to a decomposed approach, where separate data streams can have their own dedicated processing engine instead of sharing a much larger CPU. Alternatively, the application can be written to allow portions of the processing to be done in parallel by a large number of smaller CPUs. Data analysis can often be implemented in a vector processing manner, which is highly amenable to decomposition and parallelism. The number of processors in such a system can scale up to hundreds of devices, with thousands of processing cores being involved in the computation. In order to efficiently enable the vast number of processing engines to operate, they need to have common access to the

information in the system. The data flowing in comes from a communication device or a special purpose acquisition front end. It is saved in—and processed from—the storage subsystem. This can be enabled by a “fabric” that has shared I/O capability (Figure 2). Here, again, PCIe with some standards-based enhancements is a compelling solution to this problem. There already exist commodity devices and software to allow multiple CPUs to share storage and communication devices, and a fabric can quickly and easily be created to allow a high-performance, low-latency flow from input, through processing, into storage and back out for further analysis. PCIe has a number of further benefits coming from high-performance computing technology that are advantages for the embedded world. SSDs have been created by taking flash memory and enabling it to be accessed in a manner that is similar to hard discs. In the high-performance enterprise arena, the fastest-growing segment of this market hooks SSDs directly to PCIe. So, once you already have the PCIe backbone, it is quick and easy to hook up large, powerful SSD arrays to your system. The other technology that can be leveraged is a general-purpose graphics processing unit (GPGPU), where graphics

processing engines have been repurposed to handle tasks that are highly parallel in nature. Once again, this describes many applications in test and measurement systems. The GPGPU devices are connected to the system—and to each other—through wide PCIe interfaces. And the most powerful part of the solutions that have been described here is that they can be combined as necessary to get the right mix of processing (high-performance CPU, microserver or GPGPU), storage and communication. Modular systems can even be deployed that allow a system to be upgraded in the field, or by the customer, so that the basic platform can have an extremely long life. PLX Technology Sunnyvale, CA (408) 774-9060 [].

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SYSTEMS Advances in ATCA

Boosting ATCA Hardware Platform Management for Power Subsystems A new set of extensions to the AdvancedTCA specification includes additional means for power management and supports a new generation of sensors for more comprehensive monitoring and control of power consumption.

by Mark Overgaard, Pigeon Point Systems Figure 1









where the base ATCA specification covers only DC-powered shelves. Another extension area is enhancing the sensor facilities of the Intelligent Platform Management Interface (IPMI) so that sensor values larger than 8 bits can be represented. One key goal is to enable integration of the wide ranging sensors defined by PMBus, an open protocol based on I 2 C for communicating with power conversion and other power-related devices. PMBus-compatible physical sensors are already being implemented in ATCA power subsystems from the bulk AC power supplies at the shelf level to the -48V power input modules on individual ATCA boards and the 12V point of load controllers that provide power for specific board subsystems. ØA8











ore than ten years after its adoption on the last day of 2002, AdvancedTCA will get a significant set of extensions later this year in PICMG 3.7, the AdvancedTCA Base Extensions specification, now nearing completion within PICMG. Among other things, these extensions enable larger and more powerful ATCA shelves, such as a single shelf with 16 double-wide boards (each board drawing up to 800 watts!), with 8 of them installed on each side of a dualsided shelf. A subset of these extensions relate to hardware platform management for the power-related aspects of these shelves, which potentially consume more than 12 kW each. Many of the extensions described here could be added via software changes to the hardware platform management layer of some currently shipping ATCA platforms. One area of these management enhancements concerns “power geography,” rounding out the capability for shelves and boards to self-describe their power characteristics to enable more accurate operational tracking and diagnosis. These power geography enhancements also include coverage for AC-powered shelves,

FIGURE 1 Power architecture for example PICMG 3.7 shelf.

Leveraging the Power Geography

Figure 1 shows the power subsystem of an example PICMG 3.7 shelf that includes four double-wide board slots. In each of those slots, a blue connector— called a Zone 1 connector in ATCA—on the backplane mates with a corresponding connector on the board to provide management and power connections for that board. Each board spans two slots, but connects to the backplane in only one of



Voltage Ranges: Minimum, Nominal, Maximum


Expected Voltages: Installation-configured for each feed


(39, 53, 72) Satisfies ATCA legacy voltage range Design Voltages: Factory-defined for the shelf and for each -48 V FRU


(39, 53, 72) Supports ATCA legacy voltage range












(43, 48, 57) Supports enterprise voltage range


FIGURE 2 Expected and design voltage ranges in PICMG 3.7 enable detection and management of mixed voltage range configurations.

them. A slot position without a Zone 1 connector, for instance slot ØA1, is called a void slot. This example is assumed to show just one side (side A) of a dual-sided PICMG 3.7 shelf; the slot numbers include an “A” to indicate that. There are four -48V feeds in the example shelf, two from each of the Power Entry Modules (PEMs); each feed supplies one of the two power inputs on each board. The PEMs themselves are each powered by three AC Power Supply Units (PSUs). In a shelf built in accordance with the PICMG 3.7 enhancements, all elements shown here are fully self-describing, including which PSUs are connected to which PEMs, and which feeds from those PEMs are connected to which board inputs. With current ATCA, in contrast, AC PSUs are not addressed at all and the power path from a specific PEM output to a specific board input in a particular slot is not self-describing. The missing information can complicate power management and problem diagnosis in a shelf. Figure 2 shows another extension

in PICMG 3.7 where new or augmented data structures record the voltage ranges for which boards and shelves are designed and within which they are expected to operate in a particular installation. The design voltage ranges are established at the factory and the expected voltage ranges are configured when a shelf is installed and connected to a power source. In PICMG 3.7, it is possible to build shelves and boards that support a more restricted voltage range than ATCA. For example, designing for the enterprise voltage range (-43V to -57V) can allow cost savings compared to supporting the full ATCA legacy voltage range (-39V to -72V). What happens if a board designed for a restricted range (such as the enterprise voltage range supported by the board installed in slot A4 in this example) is installed in a shelf that implements a wider voltage range? With the information available in PICMG 3.7, a shelf manager could choose not to enable power to such a board at all, to avoid risking an unacceptable operating environment for the board. What if the example shelf shown

in the figure is installed with no power source for PEM B? The expected voltages for the two feeds from that PEM would all be configured as zero. A PICMG 3.7 board can use a new Intelligent Platform Management Interface (IPMI) command to query the shelf manager for the expected voltages on its feeds. The shelf manager uses power geography data to identify the correct feeds and retrieves the expected voltages that have been configured for those feeds. In this case, when a board in the shelf detects zero volts on an input feed that has an expected voltage of zero, there is no need to raise an alert.

Extended IPMI Sensors in Hardware Platform Management

IPMI sensors that provide numeric sensor values are based on an 8-bit raw data value and a set of coefficients that can be applied to that value by a client application. This produces a processed value with appropriate scaling to reflect physical measurement units such as volts or amperes. For some physical measurements (including the temperatures typically measured in an ATCA shelf), 8 bits of raw data is sufficient for management purposes. In the power area, however, there is often a need to size data values for worstcase conditions while maintaining accuracy for finer granularity assessments. The physical devices used to monitor powerrelated properties in some currently shipping ATCA shelves capture greater than 8-bit data for voltage, current and power measurements. However, that data has to be reduced to 8-bit data for reporting via IPMI. For example, the 16-bit hardware sensor in some currently shipping PEMs can measure power in 0.2W increments, but when reduced to 8-bit data the IPMI sensor can only report power in 51W increments, thus sacrificing potentially important accuracy. The PMBus architecture, which was designed for and by power monitoring specialists, defines two fundamental raw value formats. The PMBus direct format uses 16-bit signed raw values while the linear format uses an 11-bit mantissa and a 5-bit binary scale factor— both signed integers. Like IPMI, PMBus defines a set of coefficients and a conversion formula RTC RTCMAGAZINE MAGAZINENOVEMBER OCTOBER 2013



based on those coefficients to calculate processed values of sensor measurements. Furthermore, the PMBus coefficients and conversion formula, while similar to IPMI’s, are sufficiently different that PMBus-based sensors cannot be accurately represented with the existing IPMI coefficients and conversion formula. Figure 3 shows the main levels of ATCA power subsystems, from the onboard power domains (such as one supporting a particular CPU socket), through overall board-level power, to the PEMs and PSUs that supply feeds in the overall shelf. As noted in the figure, there are existing power monitoring devices and products at all these levels that either: 1) support greater than 8-bit data without using PMBus or 2) implement PMBus and therefore trigger a need to accurately represent the measurements collected by PMBus-based sensors.

to be converted as extended IPMI raw values, the scaling factor needs to be applied at that time. Given a binary scaling factor ranging from 16 bits of negative scaling to 15 bits of positive scaling, a scaled 11-bit mantissa can require up to 42 bits. The 11-bit mantissa could be shifted left by 15 bits (with a positive scaling factor of 01111b) or right by 16 bits (with a negative scaling factor of 10000b). Therefore the raw value storage must be at least 42 bits in size. As a result, an extended IPMI sensor based on a PMBus linear format data needs to be configured for at least six-byte raw data, rounding up from 42 bits to the next 8-bit boundary of 48 bits. The measurement of energy consumption is one area where the extended IPMI sensor facility is especially imporFigure 3

Available Power Features Supports > 8-bit Data

Extended IPMI Sensors in PICMG 3.7

Based on the needs described above, PICMG 3.7 defines facilities for extended sensors that support raw data values that are two to eight bytes in size, versus the one-byte limit for raw data values in normal IPMI sensors. For any given sensor, the size of raw values is fixed within that range, as appropriate for the measurements that particular sensor needs to represent. For instance, an extended IPMI sensor representing a physical PMBus current sensor that returns raw data in the 16-bit direct format could be configured for two-byte raw data. The coefficients for an extended IPMI sensor are represented in the same fixed size as the raw data. In addition, an extended IPMI sensor can be configured to use either the normal IPMI conversion formula (with extended size coefficients) or the PMBus conversion formula. The combination of larger raw data values and the option to use the PMBus conversion formula allows PMBus sensor values to be fully and accurately represented by PICMG 3.7’s extended IPMI sensors. With the PMBus linear format, specific raw values in a stream of sensor measurements could potentially have any values for the 11-bit mantissa and 5-bit scale factor fields. When such raw values need



tant. An energy consumption measurement can be considered the sum of a series of instantaneous power measurements over a known period of time. The longer the measurement time, the larger this sum can be, with a corresponding increase in the number of bytes needed to represent it. With the 64-bit raw sensor values supported in extended IPMI sensors, it should be feasible to implement realistic energy consumption measurements with reasonable assumptions on how frequently a client application needs to retrieve an accumulated energy consumption total to ensure that a rollover of the 64-bit integer sum is not missed, thus avoiding an incorrect energy reading. Client applications can use floating point computation to maintain arbitrarily large sums





Power Domain

FIGURE 3 Availability of > 8-bit or PMBus-based raw sensor values for devices used in various ATCA power subsystems.


Solid or Spin...

with acceptable accuracy. Most microcontrollers used as local IPMI management controllers do not have floating point support in hardware and IPMI assumes that only integer arithmetic is supported. The Service Availability Forum’s Hardware Platform Interface (HPI) is widely, but not universally, used as the foundation of system management applications above an ATCA shelf manager. At the HPI level, sensor values are represented natively as either already processed 64-bit integers or floating point numbers. Any processing implied by IPMI or PMBus conversion formulas and coefficients is applied in the HPI implementation layer below the application code. When that implementation layer is augmented to support the extended IPMI sensors here, existing HPI applications can use the resulting sensor values without needing any changes.

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TECHNOLOGY DEVELOPMENT Developing Code for Hybrid Architectures

OpenCL for FPGA – Bringing FPGAs to the (Relative) Masses—Part 1 OpenCL allows FPGAs to be programmed in a C-like language, opening them up to a much wider base of programmers, thus allowing them to be deployed in places that would normally be owned by CPUs and general purpose GPUs. by Ron Huizen, Bittware


ield Programmable Gate Arrays (FPGAs) have become very powerful and power-efficient processing engines. With their programmable hardware resources, they can be customized to a specific application and outperform Central Processing Units (CPUs) and Graphics Processing Units (GPUs) while using a fraction of the power. The major issue with deploying FPGAs to a broader user base is their reliance on specialized programming languages known as Hardware Description Languages (HDL) such as VHDL and Verilog. These languages can be looked at somewhat like assembly level languages when compared to traditional high level programming languages, requiring specialized skill sets and indepth knowledge of the underlying hardware. While numerous attempts have been made to develop tools that can convert from traditional programming languages to HDL for FPGAs, or from some other higher level tool such as Simulink, none



of these have grabbed a widespread foothold, and they generally still require some FPGA expertise. In May of this year, Altera publically released their OpenCL Software Development Kit, which brings OpenCL programmability to the world of FPGAs. FPGAs continue to grow in size and capabilities with every new generation. As an example, Altera’s recent announcements for their Stratix 10 family, based on 14 nm Intel technology, promise up to 4 million logic elements, built-in hardware support for floating point (10 TeraFLOPS), 56 Gbit/s transceivers and embedded ARM cores. While these FPGAs provide tremendous capabilities, the complexity of FPGA development still causes concern for those looking to deploy them in what are traditionally programmable processor (CPU, GPU, DSP) domains. Large potential markets for these big FPGAs have gone relatively untapped, as people shy away from the development

complexity. While strong arguments can be made for their power efficiency and performance versus general purpose CPUs and GPUs, the pushback is always the same—the skill set needed to use them is too specialized and development cycles are way too long.

The OpenCL Solution

In an attempt to address these concerns, both Altera and Xilinx joined the OpenCL consortium to explore developing OpenCL support for their FPGAs. Why OpenCL? Three solid reasons come to mind, all related to OpenCL’s definition, per the Khronos Group, as “the open standard for parallel programming of heterogeneous systems.” That’s quite a mouthful, so let’s break it down. Started by Apple, and now managed by the Khronos Group, with members including Intel, AMD, NVidia, IBM, Texas Instruments, Freescale, ARM, Altera, Xilinx and many more, OpenCL is a true open standard. Such widespread support is crucial, as it allows users to choose the underlying hardware that best fits their application, and quickly try new technologies as they emerge. OpenCL developers are not locked into one processor supplier, or even one processing technology, and can upgrade to new processors and technologies as they emerge. Supporting OpenCL opens the world of FPGA technology to a whole new group of developers. Instead of trying to introduce yet another new programming concept, you can leverage an existing open and proven methodology. OpenCL is designed specifically for parallel programming, making it ideal for FPGAs, since one of the major means to performance in FPGAs is their ability to massively parallelize. Previous attempts in C to HDL conversion tools have suffered from the inability of the source language to specify the parallelism. An OpenCL compiler for FPGA can make use not only of standard pipelining techniques for generating logic from linear code, but can also take advantage of the parallelism specified by the programmer. Finally, OpenCL is designed to be


OpenCL Program Kernel Code

Host Code

OpenCL Compiler

Standard C Compiler


Host Binary

HDL Build

Program File

x86 Workstation BittWare S5-PCle-HQ


FIGURE 1 OpenCL program flow for kernel and host code.

used on heterogeneous systems. What’s a heterogeneous system? It’s simply a big word for a system with different types of processing elements, for example CPU + GPU, or CPU + FPGA, or CPU + GPU + FPGA. OpenCL programs consist of code that runs on a host, and code that runs on accelerators (the kernels). The host is typically a general purpose CPU, while the accelerator can be a GPU, another CPU

(or core on a multicore CPU) or now, an FPGA (Figure 1). We all know that no one processing technology best fits all applications, so OpenCL allows one to mix and match processing technologies while maintaining a common development language. Users can easily port their code from one accelerator to another, allowing them to quickly choose the best platform for their application. Note that with em-

bedded ARM cores, an FPGA can actually be its own heterogeneous system— that concept will be discussed more in Part 2 of this article.

OpenCL Basics

OpenCL, as mentioned previously, consists of host code and accelerator code. Host code can be written in whatever programming language the user desires




Host program

X86/ External Processor

Prebuilt with HDL tools




External Memory Controller & PHY

External Memory Controller & PHY

Off Chip Interconnect

Accelerator/ Datapath Computation

Accelerator/ Datapath Computation

On Chip Memory

Accelerator/ Datapath Computation

Arbitration Network

OpenCL compiler generated kernels

On Chip Memory Interconnect

FIGURE 2 Partitions showing locked external interfaces and kernel code.

and interfaces with the OpenCL environment through a defined application programming interface (API) for managing the accelerators, which includes calls for data movement, loading code, and scheduling and coordinating execution. Each device supplier provides support for their own accelerator, including a compiler for the accelerator code and the backend for the host API. While suppliers can add their own optimizations, including prewritten libraries, they must adhere to the OpenCL standard to ensure portability. The accelerator code is written in a language derived from C (actually C99), with some extensions. There are two things needed to support OpenCL. First is the compiler, which



is device/technology specific, so Intel would do one, NVIDIA would do one, Altera would do one, etc. The board support package would then need to be ported for that device on a particular board. For programmable processors, creating a compiler and subsequent board support package is not that difficult, but for FPGAs it is a much more difficult job. The reason is that OpenCL is essentially a software programming language based on C, so it therefore maps nicely to programmable processors. For the FPGA, Altera is actually generating hardware (logic) specific to the written kernel code—they are not simply putting programmable processors in the FPGA. Likewise for a board vendor with an FPGA, the infrastructure

needed to support OpenCL must be developed and locked down, whereas with a programmable processor, this is usually supported in silicon. After several years of development, and over a year of beta release with a large group of users, Altera publically released their OpenCL Software Development Kit (SDK) for FPGA in May of this year. At the heart of this tool is Altera’s OpenCL compiler, which generates Verilog for user-written OpenCL kernels. These generated kernels then get automatically integrated into a pre-written FPGA project, which provides the OpenCL infrastructure support. This support typically includes external memory and PCIe interfaces. Part 2 of this article will discuss

TECHNOLOGY DEVELOPMENT extensions that allow for streaming I/O interfaces and kernel to kernel channels. A key to Altera’s OpenCL approach, and one that differs from other HDL generators, is that the OpenCL programmer directly generates the FPGA programming file without seeing any VHDL, Verilog, or synthesis tools. The FPGA board developer, such as BittWare, does the hard work upfront, creating the OpenCL board support package using standard FPGA methods (VHDL or Verilog), which include the base project that the OpenCL compiler generated kernels get placed in. All the external interfaces in this project are physically locked down so that they are guaranteed to meet timing in subsequent builds, and the OpenCL compiler then can fill the remainder of the part with the generated kernel code. Figure 2 shows this partitioning. Using this methodology means that the software developers do not have to keep throwing their generated code over the wall to an FPGA team to get it working on the board. Instead, they directly create the FPGA load. They will not see timing errors in their FPGA build as the external interfaces have been locked and the kernel clock is adjusted by the tool to meet timing. Running the Altera OpenCL compiler is a two-step process, the first of which is compiling the OpenCL kernels to Verilog. This first step is quite quick (minutes) and will tell you, once you’ve gotten past any syntax or semantic errors, how fast your kernel will run as well as how many resources it used. The second step is a more traditional FPGA compile, which can take as long as traditional FPGA builds (hours). The good news is that once the first phase passes, you know the second phase will complete, it just may take some time. It is recognized that traditional CPU and GPU programmers aren’t used to this long second compilation phase, and initiatives to allow more rapid build cycles are being explored. It should be noted that Altera’s OpenCL Compiler is actually generating logic to implement the kernels. It is not filling the FPGA with fixed processing cores that then run compiled code (as per GPU), but is instead generating hardware

that specifically implements the kernel. This is the key reason why FPGAs can outperform CPUs and GPUs, and at a much lower power usage. Altera’s OpenCL initiative has addressed two of the primary concerns for people adopting FPGA technology in spaces traditionally dominated by programmable processors. First, it provides a more traditional software programming environment, opening FPGAs to a much larger potential developer base. Second, development cycles can be dramatically shortened by allowing FPGAs to be programmed in a high level parallel programming language. Porting algorithms to FPGA using VHDL and Verilog can be a painstaking process, and every time anything changes, it is not insignificant work to implement the change. Using OpenCL, development cycles can be cut from many months to a few weeks or even days. Altera’s OpenCL SDK is available now, and is supported on BittWare’s Stratix V PCIe Half Size board, the S5PHQ. A special OpenCL Developers Bundle is available from BittWare, which has everything you need to get up and running, including the OpenCL SDK. Part 2 of this article in the December issue will explore how OpenCL for FPGA can be used to address more than just the CPU accelerator market by including extensions for streaming I/O, support for multiple FPGA systems, and using the embedded ARMs as the OpenCL host. BittWare Concord, NH (603) 226-0404. []. Altera San Jose, CA (408) 544-7000].





Battery Technology Widens Options

Rechargeable Batteries: New Choices, Complex Decisions Designers of mobile and handheld devices face an array of alternatives for cell chemistry, packaging, capacity and counterfeit protection

by Todd Sweetland, Electrochem Solutions




World Battery Demand $40,000 $35,000 $30,000 Millions

he good and bad news for designers of medical equipment and other devices using rechargeable batteries is that there are more and better choices than ever. However, these also bring some new and difficult tradeoffs. Whether the battery is the primary power source, or functions as an AC-line backup, aggressive design goals combined with regulatory requirements are placing larger demands on battery performance and capability. The first area of dramatic change is cell chemistry. Sealed lead acid (SLA) and nickel-cadmium (NiCd) cells have served the industry for many years, but the lithium-ion (Li-ion) chemistry has already overtaken the nickel-based cell market and is predicted to be as large as the SLA market by 2017 (Figure 1). Li-ion has two strong advantages compared other battery chemistries. First, it has much greater energy density measured by both weight and volume. These are not slight or moderate improvements; the improvement is by a factor of 2 to 4 times (Figure 2). As a further advantage, the nominal voltage output of a lithium-based cell is around 3.6 volts, compared to just 1.2V for NiCd and 2V for SLA. As a result, a single cell may be sufficient, thus simpli-


Alkaline Zinc-Carbon / Zinc-Chloride Lithium Other primary Lead-Acid Lithium-Based* Nickel-Based** Other secondary

$20,000 $15,000 $10,000 $5,000 $0 1997


2007 Year



FIGURE 1 Chemistries graph.

fying design and packaging, if its amphour capacity is adequate. Further, the self-discharge rate for Li-ion is just onethird that of NiCd, a major advantage for products that “sit on the shelf� for a long time and then will be unexpectedly turned on in a critical-use scenario.

Note that Li-ion is not a single chemistry, but rather a family with variations in chemistry, anode and cathode materials, and construction, all offering tradeoffs in shelf life, self-discharge rate, current capability, temperature range and other parameters. Figure 3 shows the


For many designs, the battery pack is allocated in whatever space remains in the enclosure after the electronics have been designed. Not only is the higher energy density by volume of Li-ion an advantage here, but there is also flexibility in available cell shapes along with multicell package options. The most obvious cell shape is the well-known cylindrical style (Figure 4). Whether individually or in multicell packs, this cell is used in many consumer products, so it has the highest production volume, lowest apparent cost and largest number of suppliers. Two common standard sizes are available, designated as the “18650” (18 mm diameter, 65 mm length) and the “26650” (26 mm diameter, 65 mm length). This cell shape offers high capacity, up to 3 Ahr for the 18650. The downside is that in multicell configurations—whether in series for higher voltage or parallel for increased current—space is wasted between the cells when they are in a pack. An alternative is the lithium polymer cell, which is not a different material but a physical structure. This cell construction can be used for very thin sheet-like cells, to fit tight spaces and also provide high packing density and effectiveness. There are drawbacks, however. The thin construction can be damaged, the cells can swell; they are manufactured in smaller volumes and are thus more costly; energy density is lower, and custom form factor may be hard to support long term, compared to more common shapes and sizes.

Volumetric energy density (Wh/I)

Cell Packaging to Fit the Space

Improvements in Energy Density

600 500

Lithium Ion

400 300 NiMH NiCd

200 100 0


50 100 150 200 250 Gravimetric energy density (Wh/kg)

FIGURE 2 Energy density graph.

Typical Cathode Voltage profile

4.5 4 Voltage vs. Li/Li+

voltage (potential) and capacity of various Li-ion chemistries in use or being researched A brief word about safety: Although we won’t cover it here, the safety of Liion cells and battery packs is an issue that is always part of the consideration. There are several layers to making sure these energy sources remain safe, from using materials such as heat-resistant separators, to construction with pressure-relief valves, to supervisory electronics including internal positive temperature coefficient (PTC) fuses and external monitoring of temperature and other parameters.

3.5 3 LiCo02 LiNi0.8Co0.202 NMC (111) LiMn204 LiFeP04

2.5 2 0 FIGURE 3




80 100 120 140 160 180 200 220 mAh/g

Voltage capacity chemistry comparison graph.

Finally, there is “prismatic” packaging, which is a thicker version of the lithium polymer cell and available in some standard sizes. It has similar features to the lithium polymer cell, but has somewhat higher energy density, due largely to the higher ratio of internal content volume to package surface area (Figure

5). It too is prone to swelling—up to 6 to 10% over time.

Custom Configurations Key to Capacity

Every multicell pack—whether for increased voltage or current—faces tradeoffs in performance and cost. Many RTC RTCMAGAZINE MAGAZINENOVEMBER OCTOBER 2013



Counterfeiting: An Aftermarket Issue with Design-in Implications

Designers of medical electronics must also consider the battery packs that will eventually replace the OEM ones shipped with the product, as good practice requires replacement typically after between two and five years. The problem is that for suc-



Capacity (mAh)

cessful products—even They can use specialized or holographic lathose with custom-de- bels, but these can be counterfeited as well, signed packs—there are and most users don’t check anyway. The many vendors of sub- next step up is a solution that is “transparstandard replacement ent” to the user, with an electronic ID code FIGURE 4 FIGURE 5 packs. The scenario in the battery pack, which the equipment Cylindrical image. is common: someone must read back and validate. Again, proPrismatic image. needs a replacement viding a fake basic-ID code is not a chalpack, they go online and see what claims lenge for counterfeiters. of today’s electronic devices have high As a result, battery vendors often work to be a form, fit and functional replacepeak-current demands, even if the averwith equipment OEMS to embed cyclic rement but for far less than a battery pack age current is low or modest. dundancy checks (CRC) techniques similar purchased directly from the OEM. It’s a Most batteries are rated at what is to checksums used to verify memory and win-win-lose: the buyer gets a replacement called “1C.” For example, a 1000 mAh data streams integrity against bit errors. pack at far less cost than expected, and battery would provide 1000 mA for one It works like this: the product (acting as a the substitute-pack vendor gets solid profit hour when discharged at the 1C rate. In host) queries the battery pack (in the role margins. Only the person who relies on the theory, it would also provide 500 mA for of responder); then the pack (a peripheral) equipment and its battery suffers. two hours at a 0.5C discharge rate. But must return battery information including The reality is that these replacement the relationship is not linear, due to insuch things as product code, model numpacks are counterfeits and have numerous ternal energy losses and voltage drops, ber and identification code, along with the potential shortcomings, including reduced which may cause the battery to reach its checksum value. This challenge/response basic capacity, diminished performance low-end cut-off value sooner. Current requirements also affect in- across many parameters, inadequate inter- technique increases the counterfeiter’s ternal construction of a single cell as well nal-cell and full-pack electrical and ther- difficulties, but since it is static, it can be as multiple cells. In order to accommo- mal protection, inadequate contact welds decoded and then re-created on the bogus date the high discharge rates and associ- that fail prematurely, and packaging that packs. The much-more secure approach adds ated voltage drop due to internal cell re- can leak. They may work for a while, but elements that the CRC approach lacks. It sistance as well as IR drop in conductors, long-term performance is doubtful. As a consequence, OEMs often requires a “secret,” which the host and pethe cell’s internal topology may have to be modified to shorten path lengths, worked with pack manufacturers to pro- ripheral share; a truly random input, and a its chemistry may have to be modified vide some type of protection against use complex algorithm that generates an outto use smaller particles and thinner, of such counterfeit units. This has to be put sequence based on a string of input bits lower-resistance materials may be used. worked out at the design stage, of course, and the secret—and this algorithm should Lithium polymer may be a good choice since it affects the design of the electronics not be workable in reverse to determine the secret by working from the observed outin these cases. Externally, the situation hardware and firmware in many cases. OEMs have various options of increas- put to the inputs. Note that the algorithm is reversed: heavier conductors may be needed to wire multiple cells together to ing effectiveness to counter this problem. itself does not have to be a secret, and may minimize IR losses. Temperature is always a consideration as well, as capacity and thus runtime drop Effect of Temperature and Discharge Rate on Capacity (2400mAh Rated Cell) along with the ambient temperature. While the specific values differ with cell chemistry, configuration and manufacturer, Fig3500 ure 6 shows the effect from 45° down to 5°C for a 2400 mA cell discharged at 2.4A 3000 (1C). The impact is dramatic, as capacity 2500 drops to about one-fifth of its value at 45°C. 45˚C 2000 25˚C



1000 500




1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5

Temp discharge rate graph.

Current (A)


even be in the public domain in what is called public-key encryption; a version of this technique is used in many automobile keyless entry implementations. The preferred public-domain encryption algorithm is the SHA-1/HMAC, part of a family of secure hash algorithms developed by the National Security Agency (NSA) in the early 1990s. While there is a small component cost to implementing SHA-1, it provides significant protection against use of counterfeit cells, so many vendors have embedded it in their battery fuel-gauge ICs. While basic battery operation may seem to be simple electrochemistry, a reliable rechargeable battery pack that meets the multiple, often conflicting needs of OEMs is not. It is a complex blend of sophisticated chemicals, materials, packaging, connectors and electronics for safety and validation, all of which must perform across a wide range of applications, environments, duty cycles and discharge rates. The “best battery” is often one that has been custom designed in discussion with an experienced manufacturer who can help balance the tradeoffs and constraints, to find an acceptable “sweet spot” of power, performance parameters and price. Electrochem Solutions Clarence, NY. (716) 759-5800. [].

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TECHNOLOGY Enhanced Shelf Management for ATCA and eATCA Systems Using Atom C2000 Family

An enhanced ATCA / eATCA system management module is based on the new Intel Atom processor C2000 product family. The SMM-5060 module from Advantech provides ATCA-compliant management while optimizing user experience and integrating added value features. With these enhancements, the SMM-5060 enables faster development and deployment of high-performance networking elements based on the popular ATCA standard, yet also improves the total cost of ownership by simplifying field maintenance and service operations. The SMM-5060 acts as a centralized access point simplifying tasks such as system health monitoring, inventory control and performing platform firmware or BIOS upgrades of blades. Advantech’s unique SoL Proxy software allows controlling the consoles of each blade over the system via a single, protected SSH session. Gone are the days when users needed to establish up to 16 sessions, one per blade, using a raw RMCP+ protocol to manage an ATCA system. Using a single SSH session drastically simplifies the service access to a complex platform like ATCA and makes it much handier to use. With the new Intel processor’s sup-

port for hardware offload, management traffic to and from the system can be encrypted and decrypted on the fly, yielding utmost operational protection as users gaining access to the Shelf Manager have full control over the platform. Support for RADIUS and TACACS/+ authentication simplifies the integration into secure management frameworks deployed in the networks. With up to eight cores in 22nm technology, the new Atom C2000 processor provides sufficient processing power to host additional custom or third-party software components on the SMM-5060. At the same time it offers outstanding performance per watt and price-performance ratios through the tight integration of on-chip functions like four GbE ports and crypto acceleration. Hard disks or SSD drives can be connected to the SoC’s integrated SATA ports enabling the SMM-5060 to function as a network boot and file server to the system’s ATCA blades. This is designed to greatly reduce costs by eliminating the need for dedicated drives on ATCA blades and allows workloads to be dynamically assigned to individual blades. For example, Advantech’s specialized remote BIOS access features supported on their MIC-533x series of Intel Xeon processor E5-2600 based blades allow the SMM-5060 to automatically select the most optimized BIOS and platform configuration, which yields the optimal performance for a given workload. Advantech, Irvine, CA. (949) 420-2500. [].

ATCA Blade Targets Communications Applications for 40G Internet Bandwidth

A high-performance AdvancedTCA (ATCA) processor blade features the dual Intel Xeon E5-2600 v2 product family (formerly “Ivy Bridge-EP”) of processors paired with the Intel Communications Chipset 8920 series (formerly codenamed “Crystal Forest Server Refresh”). The aTCA-9700 from Adlink Technology offers enhanced thermal and power management capabilities for energy efficiency, while still supporting the intensive computing requirements of carrier-grade media server, networking and wireless infrastructure applications. The aTCA-9700 supports a dual-dual star 40G Fabric Interface and is designed with dual Intel Communications Chipsets 8920 for 40G IPsec performance. These capabilities enable FIND the products featured in this section and more at



telecom equipment manufacturers and network equipment providers to develop powerful, high-bandwidth solutions for mission-critical applications and offer a smooth upgrade and growth path. The new Xeon processors for large-scale communications infrastructure systems provide more cores within the same thermal envelope, thus providing exceptional overall power efficiency. This is the first Intel Xeon processor family with extended lifecycle support to offer 10-core/single-socket to 20-core/dual-socket configurations. When pairing these processors

with the Communications Chipset 89xx series, this platform provides hardware-based acceleration and the general purpose processing needed for today’s demanding communication workloads. The aTCA-9700 40 Gigabit Ethernet processor blade offers eight channels of VLP DDR31866 and REG/ECC memory up to 128 Gbyte, and provides versatile connectivity through quad 40GBASE-KR4 Fabric Interface channels, dual Ethernet 10/100/1000BASE-T Base Interface channels, and dual front panel 10/1001000BASET egress ports. Additional I/O includes two USB 2.0 ports, VGA, USB1/2, LAN1/2 and COM1/2 (mini-USB) on the front panel. Onboard bootable storage of 16G SATA flash (up to 64G) is included. Support for Intel Hyper-Threading Technology and QuickPath Interconnect provides increased performance from both single and multi-thread workloads while maintaining thermal and energy efficiency. ADLINK Technology, San Jose, CA. (408) 360-0200. [].


3U OpenVPX High-Speed Data Recording Engine

A high-speed, rugged 3U OpenVPX Data Recorder captures high-volume, continuously streaming data without interruption, making it suitable for speeding and easing the integration of high-throughput reliable data recording into deployed 3U VPX COTS systems. The VR1257 from Curtiss-Wright Controls Defense Solutions enables system integrators to quickly and cost-effectively add high-performance data recording. Suitable for use in both lab development and rugged deployed environments, this rugged SWaP-optimized data acquisition solution targets demanding ISR applications, such as radar, sonar, FLIR and Infrared (IR) sensor data capture in aircraft, ground vehicle and base stations. The VR-1257 is a high-performance recording engine designed for use in harsh-environment air- and conduction-cooled applications. The rugged board features an Intel Core i7 processor and supports system expansion via an XMC/PMC mezzanine site. The mezzanine module interface provides eight lanes of Gen2 PCIe to support a wide range of highspeed data fabrics such as sFPDP, Gigabit Ethernet (GbE) and 10 GbE. For applications with unique I/O requirements, our Customer Programmable Software API is available to ease and speed the development of high-speed recording systems. When combined with Curtiss-Wright’s VPX3-FSM 3U VPX Flash Storage Module, the VR-1257 provides a complete secure data recording solution for SWaP-constrained deployed applications. The VPX3-FSM secures critical data stored on its high-performance/ high-capacity solid-state SATA drives with FIPS 140-2 validated AES-256-bit encryption. The VPX3-FSM, a 1” pitch conduction-cooled solid state storage device, utilizes high-reliability SLC NAND flash designed for the most demanding applications. The FSM can be configured as either four separate SATA drives (4 x 256 Gbyte) or as a single SATA drive. Curtiss-Wright Controls Defense Solutions, Ashburn, VA. (978) 952-2017. [].

Security Solution for Smart Home Devices

A software firewall protects connected Smart Home devices from Internet-based attacks. Floodgate at Home from Icon Labs features the Icon Labs suite of security products that provides device protection, management and incident reporting to home users and service providers via a secure web page. Floodgate at Home is an OEM software product licensed and embedded by manufacturers of Smart Home IoT devices. Manufacturers can embed Floodgate in the tiny processor and communication chips found in Smart Home devices like thermostats, window alarms, temperature sensors, home health sensors, etc. Once the device is connected to the web, the end user, home system integrator or service provider sets up the security arrangement—limiting access to a few specific people, phone numbers, or the IP address of a specific laptop or tablet. Floodgate at Home protects home premises equipment against the growing number of Internet-based attacks. By stopping communication from unapproved devices, Floodgate at Home blocks unauthorized access, protects against automated hacking drones, and can even prevent the device from being discovered by hackers. Floodgate at Home is available now. It is designed for use in embedded systems and can be used with operating systems such as Embedded Linux, Integrity, VelOSity, VxWorks, LynxOS, MQX, or eCos, or devices without an operating system. Icon Laboratories, West Des Moines, IA. (515) 226-3443. [].

Quad Core HPEC Platform Doubles Performance

A rugged dual-node quad-core 6U OpenVPX high-performance embedded computing (HPEC) deployed server platform, the DSP281, is the third in a new family of products from General Electric Intelligent Platforms to harness the increased performance of fourth generation Intel Core i7 (‘Haswell’) chip sets. The DSP281 brings more than double the theoretical peak performance of its predecessor within the same size, weight and power (SWaP) envelope. Deployed on manned and unmanned airborne, ground and naval platforms, it can enable optimum benefit to be derived from the significant volume of data obtained from large numbers of high-resolution sensors by providing meaningful information in an actionable time frame to decision makers and war fighters across an asymmetric, dynamic and rapidly changing threat landscape. It also brings high levels of data security with GE’S new onboard Security Hub and full support for the latest Intel platform security features. GE’s HPEC architecture, as implemented in the DSP281, can scale from one to many processor nodes per enclosure via RDMA-enabled InfiniBand and Ethernet dual port network interface cards, delivering very high interprocessor bandwidth at extremely low memory to memory latencies. In addition, system integrators can minimize card count by mapping multiple platform functions such as control, DSP, image and video processing and graphics onto one or more DSP281s in order to reduce spares and simplify logistical support in the field. The DSP281 is supported by GE’s unique AXIS Advanced Multiprocessor Integrated Software development environment. AXISPro includes a high-performance IPC middleware and GUI for task level programming and fast prototyping to reduce development cost and shorten time-to-solution of multicore, multithreaded and multi-node distributed system architectures across multiple operating systems including Linux, Windows and VxWorks, and includes quick start signal and image processing examples to further accelerate time-to-solution. General Electric Intelligent Platforms, Huntsville, AL. (780) 401-7700. [].




High Speed Digitizing and Signal Generation FMC I/O Module

A high-speed digitizing and signal generation FMC I/O module features four 310 Msample/s A/D channels supported by sample clock and triggering features. The VITA 57.1 FMC-310 from Innovative Integration supports receiver IF frequencies of up to 155 MHz. Support logic in VHDL is provided for integration with FPGA carrier cards. Specific support for Innovative carrier cards includes integration with Framework Logic tools that support VHDL/Verilog and Matlab developers. The Matlab BSP supports real-time hardware-inthe-loop development using the graphical block diagram Simulink environment with Xilinx System Generator for the FMC, which are integrated within the FPGA carrier card. The FMC-310 addresses the needs of many customers in a variety of markets, Wireless, Industrial Control, Military Hardware, Medical Imaging, Telecom/Intelligence and Test & Measurement. The sample clock is from either an ultra-low-jitter PLL or external input. Multiple cards can be synchronized for sampling. The FMC-310 power consumption is 6W for typical operation. The module may be conduction-cooled using the VITA 20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation are from -40° to +85°C operation and 0.1 g2/Hz vibration. Conformal coating is available. Support logic in VHDL is provided for integration with FPGA carrier cards. Specific support for Innovative carrier cards includes integration with Framework Logic tools that support VHDL/Verilog and Matlab developers.

dual channel LVDS. Sound is provided by analog audio in and output. An additional loudspeaker port (1 watt) can drive smaller loudspeakers directly—i.e., for making acoustic acknowledgement or for speech output, which can make a separate amplifier superfluous. For OS and application data there are up to 16 Gbyte NAND Flash memory on board plus a microSD slot. Hard disks or DVD players can be connected via 1x SATA and 1x mSATA. Beside two Fast Ethernet interfaces with an optional switch, it also offers 2x CAN bus as well as a SIM card slot for MiniPCIe modem cards. Peripherals can be connected by the 5x USB 2.0, 2x RS-232 or 1x RS-435. 26x GPIOs, I²C, UART and SP output round off the feature set. The motherboard KTAM3874/pITX comes with Linux, Android and Windows WEC7 support and a minimum of seven years long-term availability.

An ultralow-density FPGA family is aimed at expanding system capabilities and bridging emerging connectivity interfaces using both parallel and serial I/O. By matching advanced, smallfootprint packaging with on-chip resources, the MachXO3 family from Lattice Semiconductor puts affordable innovation into the hands of system architects by simplifying the implementation of emerging connectivity interfaces such as MIPI, PCIe, GbE and much more. The ultra-low-density MachXO3 FPGA family gives customers a single programmable bridge that lets them build differentiated systems using the latest components and interface standards. With advanced package technology solutions that eliminate bond wires to enable lowest-cost and increased I/O density in a small footprint, the MachXO3 family can be used across market segments, including consumer, communications, compute, storage, industrial and automotive. Lattice’s MachXO and MachXO2 families of instant-on, non-volatile programmable devices provide system architects complete, low-cost options to expand general purpose I/O, bridge interfaces and minimize total system power. Leveraging a low-power architecture built on 40nm process technology to deliver lower cost with increased performance for power sensitive applications, the new MachXO3 family delivers a new set of capabilities that enable system engineers to do even more in a smaller footprint. The new 640-to-22K logic-cell family makes use of the latest in package technology to not only deliver tiny 2.5 x 2.5 mm waferlevel chip-scale packaging, but also 540 I/O count devices, as well as devices with 3.125 Gbit/s SERDES capabilities to cover the full spectrum of bridging and interface requirements in consumer, industrial, communications, automotive and compute markets. The devices are supported by Lattice Diamond software, as well as IP and application expertise both in-house and by third parties. Pricing starts below $1.00 in high volume.

Kontron, Poway, CA. (888) 294-4558. [].

Lattice Semiconductor, Hillsboro, OR. (503) 268-8000. [].

Innovative Integration, Simi Valley, CA. (805) 578-4260. [].

Pico-ITX Motherboard with Ti Sitara 3874 Accelerates Development of ARM-Based SFF Designs A Pico-ITX motherboard is equipped with the Ti Sitara 3874 processor and provides tablet PC class performance and a comprehensive range of standard and embedded computing interfaces. With its Pico-ITX compliance, the KTAM33874/pITX from Kontron offers OEMs the possibility to realize cost-efficient SFF embedded appliances based on a standardized form factor. OEMs can now exploit the whole ecosystem, which to date has been used for x86 technology. The Kontron PicoITX board based on the ARM Cortex A8 single-core processor boasts a low TDP (Thermal Design Power), which makes it extremely suitable for compact, fanless applications. It is also the first Kontron motherboard designed from scratch for the extended temperature range of -40° to 85°C. The new Kontron embedded motherboard KTAM3874/pITX is available with the single-core Texas Instruments Sitara 3874 microprocessor (MPU) for the extended temperature range with 800 MHz Cortex-A8 technology. In terms of graphics, it offers 3D graphic acceleration and supports up to two independent displays both with resolutions of 1080p (full HD) connected via HDMI 1.3a and 24-bit



FPGA Family Offers Advanced, Low-Cost per I/O Connectivity Interfaces


10/40 Gigabit Ethernet Switch for OpenVPX

A new 10/40 Gigabit Ethernet switch is designed to significantly enhance and standardize data throughput in network-centric OpenVPX applications. The main features of the fully managed Layer 2/ Layer 3 Switch Kontron VX3920 are its 24 high-throughput 10 Gbit/s ports to the data plane. These can be scaled through channel bundling up to as high as 40 Gbit/s bandwidth. By using this new rugged switch for inter- and intra-system communication, OEMs can achieve a significant performance boost for their applications. Also, other highly individual data buses can now be replaced. Application areas include high-performance embedded computing (HPEC) systems for radar, sonar and image processing, “vetronics” systems (vehicle electronics) as well as rapidly deployable networks for flexible communication in the field. With up to 60 Gbit/s data throughput provided by one rear I/O module with 40 Gbit/s Ethernet QSFP+ and two 10 Gbit/s SFP+, it also enables a powerful networking for complex system clusters, which are found on larger military intelligence and surveillance applications such as naval vessels. The non-blocking L2/L3 Gigabit Switch VX3920 offers 24 x 10 Gbit/s ports to the backplane. These can also be bundled in groups of four on data leads with 40 Gbit/s. For system interconnection, 2x SFP+ cages for 10 Gigabit Ethernet are offered on the front. These can be used with cost-saving copper cables or fiber-optic cables for long distance networking. An optional rear transition module con-

ducts a 40 Gbit/s Ethernet QSFP+, two 10 Gbit/s SFP+ and one RJ45 1000Base interface. On the front side, there is a separate 1000 base RJ45 port available for switch-management via SNMP, telnet and command line interface. For management and debugging there is an EIA-232-port, which can also be routed to the backplane. Two master/slave capable I²C buses allow communication with Kontron’s VPX Chassis Monitoring Board CMB. The Kontron VX3920 switch is available as an air-cooled version for environmental temperatures of 0° up to +55°C and as a rugged condition-cooled (RC) version for the extended temperature range (-40° up to +85°C). Kontron, Poway, CA. (888) 294-4558. []

Point Tool Automates Test Generation and Unit Test Management An integrated framework for automating the generation and management of unit tests separates unit testing capabilities from the rest of the tool suite. LDRAunit from LDRA delivers a focused test management tool that addresses a need for software unit test without requiring investment in a complete tool chain. Such flexibility forms an attractive solution for companies that are committed to software quality though not necessarily required to certify to a specific standard. LDRAunit follows typical unit testing methodology by taking the smallest piece of testable software in an application, isolating it from the remainder of the code, and determining whether it behaves as expected. LDRAunit tests code units separately before integrating them into modules and then systems to simplify identification of which part of the code might be failing to deliver expected results. Using control flow and data flow analysis techniques, LDRAunit automatically generates tests in the application language—whether C, C++, Ada, or Java—and makes them capable of executing on the host or target. The tool also automates stub generation for artifacts such as methods, constructors, system calls and packages that are managed within a user interface. In addition, through eXtreme Testing capabilities, LDRAunit applies a range of return and global parameter values to the managed stubs for fully testing stub behavior and configurable exception handling to ensure that all code can be tested, hence minimizing the need for manual intervention. By storing groups of tests as sequences, LDRAunit contains all of the information required to rerun test cases and store the results for regression verification and requirements-based testing. LDRAunit can also measure and report structural coverage metrics including procedure call, statement, branch/decision, modified condition/decision coverage (MC/DC), and linear code sequence and jump (LCSAJ). Coverage data can be presented through a combination of built-in reports, custom

reports using a results application programming interface (API), and flow and call graph displays. Developers can use results to populate compliance reports that give overall pass/fail metrics for industry standards, such as DO-178B/C, with line-by-line views that detail specific statements, branches, and conditions executed by individual tests and combinations of tests. LDRA, Atlanta, GA. (855) 855 5372. [].

FIND the products featured in this section and more at




Rootkit Detection System Powered by the LynxSecure Separation Kernel

A new security solution is designed to help detect the stealthiest of advanced persistent threats (APT), the rootkit. Built on the LynxSecure 5.2 separation kernel and hypervisor, the RDS5201 from LynuxWorks is a small form factor appliance that has been designed to offer a unique detection capability that complements traditional security mechanisms as they try to protect against the growing number and complexity of cyber threats. The RDS5201 Rootkit Detection System is a custom-built hardened appliance that detects low-level, zero-day rootkits—the lethal payload of most APTs. The detection is direct—i.e., not done by statistical analysis or other indirect techniques—and is coupled with immediate, automated, live visual forensic data. The RDS5201 serves as a smart proactive sensor against APT attacks in IT networks and reduces the agonizing detection of APTs from weeks/months to seconds, and is the first and only technology capable of detecting and alerting against such threats in real time. Rootkits work at the lowest levels of the operating system (OS) they intend to attack. Common detection and prevention mechanisms are part of the “attack target,” allowing rootkits to disable the installed anti-malware client applications. The only way to overcome low-level rootkits is by allowing the security application to execute with a higher security privilege than the attacked OS; provide complete control of the platform hardware; and monitor all activities of the OS and its applications. It must also be self-protecting, non-bypassable and tamper-proof. The RDS5201 is based on the LynxSecure separation kernel and hypervisor that offer a non-detectable secure platform used to exercise potential infections and includes the introduction of the patent pending rootkit detection feature from the 5.2 release. These stealthy threats are revealed as they attack their virtual victim. LynxSecure is the most privileged monitor in the RDS5201 platform, and constantly monitors for malicious and irregular activity in key disk areas (MBR, key blocks and sectors); physical memory areas; CPU instructions and data structures; interrupt data structures, etc. This detection is completely OS agnostic, as it’s situated below any of the guest OS. Upon detection, the RDS5201 immediately alerts and sends an automated live forensics report to its dashboard. The report contains visual representation (such as the clean and infected disk sectors in-memory data structures), allowing rapid and focused threat response. The RDS5201 can also be connected to other network protection systems such as SIEM and threat management systems, offering an early warning mechanism that complements and enhances existing security solutions. LynuxWorks, San Jose, CA., (408) 979-3900. [].



Raspberry Pi chipKIT Expansion Board with Prototyping-Friendly 32-bit MCU Package

Microchip Technology Inc., a leading provider of microcontroller, mixed-signal, analog and Flash-IP solutions, announced the expansion of its Arduino-compatible chipKIT platform ecosystem, including a new Raspberry Pi tool that it co-developed with partner element14—the chipKIT Pi Expansion Board. On the software side, volunteers from the chipKIT and Arduino communities collaborated with Microchip’s engineers to expand the free chipKIT Multi-Platform IDE (MPIDE), to allow users to create, compile and program Arduino sketch-based chipKIT applications within the Raspberry Pi operating system. The chipKIT MPIDE is open source and compatible with the Arduino programming language and development environment. Both of these tools are based on Microchip’s 32-bit PIC32 microcontrollers (MCUs) in prototyping-friendly, low-pin-count SPDIP packages, which were previously only available with 8-bit MCUs for the Arduino community. This enables all users—including hobbyists, academics, makers and professionals—to benefit from the PIC32’s high performance, memory and integrated peripherals while using the basic hobbyist prototyping equipment that is found in most home workshops. The Raspberry Pi is widely viewed as one of the easiest and most affordable computers on which to program, and recently shipped more than one million units in less than a year on the market. element14’s chipKIT Pi Expansion Board enables the development of 3.3V Arduino-compatible applications for the Raspberry Pi using a 32-bit, highperformance MCU in a prototyping-friendly package. Because the Raspberry Pi’s processor is a 3.3V chip, its digital I/O and communications (I2C, UART, SPI) pins require 3.3V. This means that existing prototyping-friendly Arduino boards, which are all based on 5V 8-bit MCUs, require users to create or purchase additional components to translate the voltages. The chipKIT Pi can interface directly to the Raspberry Pi I/O Expansion header without any additional components, reducing both cost and design complexity. In addition to being 3.3V compatible, the chipKIT Pi is also the only Arduino-compatible board that brings a 32-bit MCU in a prototyping-friendly package to Raspberry Pi users. Previously, hobbyists, academics, makers and professionals who wanted to develop Arduino applications for the Raspberry Pi using prototyping-friendly, throughhole packages were forced to use boards based on 8-bit MCUs. The chipKIT Pi’s 32-bit PIC32 MCU is in an SPDIP package, so even nonexperienced users can easily swap out the pre-populated PIC32 with a new one—without having to replace the entire board. Microchip Technology, Chandler, AZ. (480) 792-7200. [].


Automotive SoC for Automotive HMI, Infotainment and Integrated Dashboard Solutions

mSATA Solid-State Drives— Small-Footprint, with Power-Fail Protection

A series of reliable, small footprint and low power draw solid state drives are ideal for embedded storage in rugged, space-conscious environments. The SSDs, mSATA solid state drives, features a 6 Gbit/s Serial ATA (SATA) interface. The s260 drives from sTec are designed to tackle a range of embedded-storage applications, including operating-system booting, data logging, code-storage/application hosting, caching and fast data backup. The s260 drives, which comply with the JEDEC-defined MO-300A and MO-300B (mSATA mini) standards, draw just 1.5W, a fraction of the power required by rotating-disk storage. Additionally, they deliver reliability through sTec’s patented PowerSafe technology and support industrial temperatures, ranging from -40° to 85°C. These features combine to meet the demands of embedded designs in remote and/ or space-constrained systems where access is limited, airflow is restricted and heat exacts both performance and durability penalties. The s260 mSATA SSDs, using highly reliable single-level cell (SLC) and enterprise multilevel cell (eMLC) flash memory, are available in a range of capacities—between 16 Gbyte and

200 Gbyte—to enable flexible, cost-efficient designs. Their powerful error-correction coding (ECC) scheme helps assure data integrity. mSATA is a JEDEC-compliant SSD format that leverages the widely used SATA standard, which continues to be used across a wide range of applications and enjoys support in the majority of off-the-shelf system boards. Increasingly replacing parallel ATA (PATA) in embedded systems, SATA drives are a logical drop-in replacement for conventional storage for OEM and industrial system designs with size and/or power constraints. sTec’s new s260 mSATA SSDs provide the same advanced flash management technology and data integrity of its other high-performance and high-reliability enterprise SSDs, in a size less than half of the industry-standard 2.5-inch form factor. sTec, Santa Ana, CA. (949) 476-1180. [].

Low Cost, Rugged 4-Port Opto-Isolated Serial PCIe MiniCard A rugged, low-cost 4-port multiprotocol opto-isolated serial port module is available in the popular PCIe MiniCard form factor measuring 30 x 51 mm. The DS-MPE-SER4OPT from Diamond Systems offers four RS-232/ RS-485 opto-isolated serial ports in a PCIe MiniCard. Each port offers 16C550 compatibility and ultra-deep 256-byte TX/RX FIFOs. Maximum data rates are 1 Mbit/s in RS-232 mode and 10 Mbits/s in RS-485 mode. The board is available preconfigured for four RS232 ports, four RS-485 ports, or a combination of two RS-232 and two RS-485 ports. I/O signals are provided on two miniature latching connectors, with two ports per connector. Each pair of serial ports on the DS-MPESER4OPT offers up to 500V isolation from system ground. Opto-isolation increases reliability in applications with long cable runs, where a difference in ground potential can cause significant ground loop currents, damaging non-isolated boards and equipment. Isolation on this miniature board is achieved through a combination of highly integrated isolated power + data components, careful component placement and layout, and a safetyenhancing insulation film on the bottom side,

which prevents accidental contact with components on the carrier board. Extended temperature capability of -40° to +85°C enables the board to operate in environments with extreme temperature swings, such as vehicles or outdoor installations. In addition, the board may be custom-configured with 0-ohm resistors in place of jumper blocks for increased ruggedness in high-vibration environments. The DS-MPE-SER4OPT’s key features and functions also include a programmable slew rate that minimizes ringing on long or un-terminated cables, +/-500V ESD protection on all ports and support for Windows Embedded Standard 7, XP, Vista and Linux 2.6.xx. Diamond Systems, Mountain View, CA. (650) 810-2500. [].

An automotive System-on-Chip (SoC) is designed to address growing integrated dashboard and information device market demands. Capable of delivering more than 12,000 Dhrystone million per second (DMIPS) and twice the graphics performance of previous generation high-end devices, the R-Car M2 from Renesas supports high-definition navigation, real-time voice control and other advanced features to provide enhanced connected user experiences within the car. An R-Car M2 software development board is also now under development and will be available in December 2013 to further simplify and speed the development cycle for designers working with the R-Car M2 SoC. With the newest member of its R-Car series, Renesas aims to expand and reinforce the ecosystem led by the R-Car Consortium, the partner program of operating system (OS) and software providers. The new R-Car M2 features a dual ARM Cortex A-15 core and Renesas SH-4A core configuration—a CPU combination that delivers both the performance and pricing desired for mid-range automotive solutions. With the R-Car M2 SoC, Renesas continues to develop robust solutions designed to support the growing demand for “smarter,” feature-rich in-car systems. To help improve the user’s development efficiency, Renesas has organized an R-Car consortium that includes OS and middleware providers, and system integrators to support development in automotive information device manufacturers. In addition to the new SoC, Renesas plans to expand the R-Car Consortium, doubling overseas partners from 15 to 30, and a total number of partner companies from 99 to 120, by the end of December 2013. Renesas Electronics, Santa Clara, CA. 408-588-6000. [].

FIND the products featured in this section and more at




USB Lab Instrument with Six-In-One Function

A low-cost PC-based instrument provides the features of six devices in one USBpowered compact box: 2-channel 11-bit 2 MSa/sec 200 kHz oscilloscope, 2-channel spectrum analyzer, 2 MSa/s 8-bit arbitrarywaveform/standard-function generator with eight digital I/O lines. The CGM-101 CircuitGear Mini from Saelig also functions as a network analyzer and a PWM output source—all for less than $100! The oscilloscope and waveform generator can also work together to form a vector network analyzer. The USB interface allows the recording, output and printing of all waveforms or even updating the firmware as new features become available. The CGM-101 CircuitGear Mini’s Oscilloscope capability provides a two-channel 11bit 20mV/div to 5V/div 200 kHz basic scope (+/-0.25Vp-p to +/-25Vp-p with 1X Probe; +/250Vp-p with 10X Probe). It also offers marker measurements and triggering (normal, auto, single-shot and pre-trigger) with a time-

1U Rackmount Network Communication Appliance Provides Network Security Solution

A new 1U network appliance supports the new Intel Atom C2000 product SoC family (formerly codenamed “Rangeley”). It comes with great processor scalability from 2 to 8 cores and Intel QuickAssist Technology function, at only maximum of 20W power consumption with the 8-core SKUs. The CAR-2050 from American Portwell also provides high flexibility by supporting two swappable Portwell NIC modules, two standard NICs, two 3.5” HDD or four 2.5” HDD and four DDR3 w/ECC long DIMM sockets. The new CAR-2050 1U network appliance is the appropriate solution for network security applications such as firewall, VPN,



base adjustable from 500ns/division to 20s/division. A 1k sample/channel data buffer allows pre-trigger signal or “strip-chart” viewing. X-Y Plot, spectrum analysis, and waveform math are also included. The two-channel FFT spectrum analyzer offers marker measurements and, when used with the internal signal generator, displays Bode plots and performs vector network analysis, showing gain and phase values in real time. The CGM-101’s Signal Generator is an 8-bit 0 Hz to 200 kHz signal source, offering sine/square/triangle/sawtooth waveforms to +/-2.75V, as well as being capable of outputting arbitrary or preloaded waveforms like ECGs. Connecting the generator signal to a circuit under test enables measurements with the oscilloscope and/or spectrum analyzer. The CircuitGear Mini also offers eight TTL I/O lines for PWM or other uses such as trigger in/out. The visual interface software provided makes control and display of information very intuitive, and users of bench-top instruments will immediately feel comfortable with the on-screen controls. The oscilloscope, generator and digital I/O are operated from a custom open-source Tcl/Tk software GUI included with the hardware, which runs under Windows, Linux, Unix and Mac operating systems. Because the software is Open Source, the code can be read and even added to or customized. The command set is compatible with Matlab, LabView and virtually any programming language. Saelig, Fairport, NY. (585) 385-1750. [].

IDS/IPS, anti-spam, anti-virus and UTM, WAN, and network management applications such as routers, RAS gateways, QoS, server load-balance, wireless controllers, and industrial automation control via Ethernet TCP/IP. The Intel Atom processor C2000 SoC with Intel QuickAssist Technology provides hardware-based crypto acceleration (encryption/decryption) that offloads cryptographic processing from the CPU core, to meet the increasing needs of the network security market. The CAR-2050 also delivers great computing performance by utilizing the new 8-core Atom C2000 SoC technology with 1M L2 Cache per two cores, x16 Lanes and four controllers. In addition, it provides flexibility

DC/DC Converters Offer Wide Input and Output Ranges

A new series of DC/DC converters offers a new input voltage range, 125 VDC to 475 VDC, with output voltages from 5 VDC to 200 VDC with 50 watts of output power. The HiQP series of modules from Pico Electronics offers the new higher wide input voltage range of 125 VDC to 475 VDC to Pico’s present lineup of wide 5 VDC, 12 VDC, 24 VDC and 48 VDC inputs with regulated output voltages from 5 VDC to an outstanding high voltage output to 500 VDC at power ratings up to 50 watts. All these electrical characteristics are combined in a miniature, 2.5” x 1.55” x 0.5” encapsulated module and offer many additional standard features. These include: safety related over temperature protection, over and under voltage protection and short circuit protection. There is also a 5% trim capability, a remote shutdown option, a 3-volt reference pin and a special bias control pin for use in a capacitor charging design. The unit can be upgraded for military or other critical applications with selection of the expanded operating temperature option of -55°C to +95°C case operating temperature. It will also meet MIL-STD 202 Vibration, Shock, Humidity and Altitude by design and is available with selected MIL-STD 883 Environmental Screening as an option. Pico Electronics, Pelham, NY. (800) 431-1064. [

system configuration options with a maximum of 22 ports by two swappable slots for Portwell’s NIC modules and six onboard ports with two segments of intelligent bypass function, and it also supports two standard fullheight PCIe cards and two 3.5” HDDs or four 2.5” HDDs. The bypass function of Portwell’s own design ensures important networking tasks never stop working even when the appliance experiences a software crash or power failure. The CAR-2050 comes with Portwell’s latest 3rd generation bypass interface. It supports Normal, Bypass and Open modes, and it allows users to adjust the bypass setting either via BIOS or operation system. American Portwell, Fremont, CA. (877) 278-8899. [].


Infection Control System Reduces MRSA Infections 56 Percent

MRSA is a bacterial infection that is becoming resistant to antibiotics. While 25 to 30 percent of people may carry the bacteria, it can become life threatening to those weakened by disease or surgery. “For years, hospitals have kept a sharp eye out for MRSA, urged staff to clean their hands and cleaned rooms as thoroughly as we could. But this doesn’t always work,” says Cone Health Executive Vice President and Chief Medical Officer Dr. Mary Jo Cagle. “Adding pulsed xenon ultraviolet light to the mix is an innovative approach, and one that we find works well.” A study by Cone Health looked at MRSA infection rates during a six-month period from July 2011 to Jan. 2012 at The Moses H. Cone Memorial Hospital, Wesley Long Hospital and Annie Penn Hospital. The rates of hospital acquired MRSA infections were monitored before and after the additional infection preventions were put into place. Pulsed xenon ultraviolet light was provided using room disinfection devices developed by Xenex Healthcare Services. Xenex’s patented pulse xenon UV disinfection system is a pesticidal device used for the advanced environmental cleaning of healthcare facilities. The Xenex system has been repeatedly shown to integrate smoothly into hospital cleaning operations because of its speed and ease of use. In this study, once the patient left, the room was thoroughly cleaned with traditional cleaning methods. Then the vacuum-cleaner sized Xenex device was brought in and used in three different areas of the room, adding a total of 10 minutes to the room cleaning time. The device flashes a broad spectrum, high intensity ultraviolet light, which reaches high-touch surfaces and many areas out of reach of housekeepers. The germicidal light destroys the ability of pathogens—such as MRSA—to reproduce. Xenex Healthcare Services, San Antonio, TX. (210) 538-9300. [].

Rugged 5-Port Ethernet Switch in PC/104 Form Factor

A PC/104 five-port 10/100/1000 Ethernet switch features a PCI/104-Express stackable bus structure. Four Ethernet ports are available on board, and one port is available to the host CPU through a x1 PCI Express Gigabit Ethernet controller. This design allows the CPU to use the switch without the need for external cables. The LAN25255 from RTD can also be used as a standalone 4-port Ethernet switch. This Ethernet switch is available in a stackable, milled aluminum enclosure. Customers can choose from screw-down 9-pin D-sub connectors, or standard RJ-45 jacks. Features include the PCI/104 Express bus structure, -40° to +85°C operation and four 1000/100/10 Mbit/s Ethernet Ports plus 1 host port. The module uses a BroadCom BCM53115 Gigabit Ethernet Switch with unmanaged operation and the Intel WG82574IT PCI Express Ethernet controller for interface to host cpuModule. It also includes onboard LEDs with resistor option for external LEDs RTD Embedded Technologies, State College, PA. (814) 234-8087. [www.rtd/com].

Dual Channel Camera Link Embedded Vision System

A new compact Camera Link embedded vision system features a 3rd generation Intel Core i7/i5 quad core processor, two independent Power over Camera Link (PoCL) ports, and rich I/O capability. The third generation Intel quad-core processor delivers high computing power, and Camera Link connectivity provides image transmission with no CPU loading, making—along with Direct Memory Access (DMA)—the EOS-4000 suitable for speedy and accurate high-resolution performance supporting industrial automation and medical imaging environments.

The EOS-4000 streams raw image data over dedicated point-to-point link topology, with no network latency or protocol overhead, and also implements DMA solutions to rearrange data for efficiency. Transmission of image data from cameras to the system memory is executed without utilizing any CPU resources, and the EOS4000 supports 64-bit memory addressing and RAID technology (dual SATA interface), benefiting vision applications with a large address space. Rich I/O capability includes one encoder input, two trigger inputs, four RS-232/422/485 ports, two USB 3.0 ports, dual storage (two SATA interface and one CFAST slot), an internal USB port, and 1 Kbit programmable EEPROM. Easy to integrate and deploy, the EOS-4000 also provides management of copy protection and software license authentication for system development, further accelerating time-to-market.

The EOS-4000 additionally offers 64 optocoupler isolated digital I/Os and supports software configurable digital filter function (0.25 μs-131 ms) securing recognition of input signals carrying noise or chatte—a requirement for demanding industrial environments. With optional Microsoft Embedded Standard 7, File-Based Write Filter (FBWF), and thread-safe I/O function, the EOS-4000 provides a stable, secure, high performance software operating environment. The included CamCreator utility enables setup, configuration, testing, and system debugging with no software programming requirement. Combining increased computing power with multichannel connectivity and a ready-to-deploy application platform, the EOS-4000 delivers embedded vision suited for high-speed and large image machine vision applications. ADLINK Technology, San Jose, CA. (408) 360-0200. [].



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Company Page Website Advanced Micro Devices, Inc............................................................................................. 52................................................................................................ Acces I/O Products, INC.................................................................................................... 41................................................................................................................... Artila................................................................................................................................. 33................................................................................................................ Axiomtek........................................................................................................................... Creative Electronic Systems............................................................................................... Commell........................................................................................................................... Congatec, Inc..................................................................................................................... 4.............................................................................................................. Digital Signage Expo........................................................................................................... Dolphin Interconnect Solutions........................................................................................... 51......................................................................................................... Elma................................................................................................................................. Extreme Engineering Solutions............................................................................................ 2.............................................................................................................. Intel.................................................................................................................................. Intelligent Systems Source................................................................................................. 25................................................................................... Lauterbach........................................................................................................................ 28........................................................................................................ MSC Embedded, Inc........................................................................................................... Noser Engenieering........................................................................................................... One Stop Systems, Inc....................................................................................................... Phoenix International......................................................................................................... 33........................................................................................................... Real-Time & Embedded Computing Conference.................................................................. 11................................................................................................................ Com Express and Carrier Board Design Product Showcase................................................. 29........................................................................................................................................

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RTC Magazine  

November 2013

RTC Magazine  

November 2013