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Managing the Workhorses: Blades and Backplanes Use I2C to Manage Small Systems Building Blocks Make Systems for the Digital Home

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6Editorial Intelligent Systems – The Power of a Name 8

Industry Insider Latest Developments in the Embedded Marketplace

10 & Technology Newest Embedded Technology Used by 44Products Industry Leaders Small Form Factor Forum Vote!

EDITOR’S REPORT Digital Home Opportunity for OEMs


Digital Home Devices to Offer Increased Opportunities for Embedded OEMs Tom Williams

Technology in Context


Blades and Backplanes

I2C in Small Systems

LAN-Attached 16 Standardized Management Controllers Yield xTCA Performance and Serviceability Gains

Mark Overgaard, Pigeon Point Systems

Card Instantiates the Next 22 PCIe Generation Communications Platform from Intel Chiman L. Patel, WIN Enterprises

TECHNOLOGY CONNECTED Computing vs. Electrical Power

Power Debug to Optimize Software for Minimal Power 26 Use Consumption Anders Lundgren and Lotta Frimanson, IAR Systems


Need a Many-Core Strategy?

Old-Timer in the Background 34The – I C Bus as a Cost Cutter on Small Form Factors 2

Ross Watanabe, congatec

TECHNOLOGY DEPLOYED Pre-Integrated Systems the Ground Running: Pre-Integration Speeds System 40Hitting Development Susanne Bornschlegl, MEN Micro

Industry watch Automotive Systems

and Multimedia Collide in 54Safety Next-Generation Automobiles David Kleidermacher, Green Hills Software

Jeff Milrod, BittWare

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Intelligent Systems – The Power of a Name


he German novelist Thomas Mann once remarked on the power of names. “There is something mysterious about names,” he said in his novel, Joseph and His Brothers. He noted that having the ability to name something gives one almost the power of conjuring, of creation. There is a phenomenon we have been witnessing taking shape for some time that has now received a name. That name is “Intelligent Systems,” and the wizard who has bestowed it is Intel. Many of us have at least been aware of the evolution that is taking place in our world due to the proliferation of computer intelligence, from the old days of mainframes to the ubiquitous PC to the incredibly vast array of embedded systems on out to some of the tiniest and everyday devices like toasters and gas pumps. And we have been aware of the spread of connectivity that has spawned expressions like “the Cloud” and “the Internet of Things.” We are aware that connectivity and intelligence are spreading, but now things are coming into focus with some interesting implications for the future... and a name that can sharpen that focus. For a good long time we have steadfastly differentiated between what we call “embedded systems” and the rest of the world, mostly such things as consumer electronics and IT. Thanks to the vast spread of intelligence and connectivity, such distinctions are increasingly difficult to make. What we are coming into, thanks to this proliferation, is a world flooded with enormous amounts of data. That data is generated by devices from the smallest remote sensor network to large enterprise computing centers and everything in between. Ironically, the existence of such huge volumes of data is demanding even more computing power and performance simply to deal with it. Embedded devices and the Internet of things are definitely a part of this development but are not the only part. This is especially true since most consumer devices now include microprocessors or microcontrollers and have Internet connectivity. On the other end, that connectivity delivers and requires data that comes via huge server farms or enterprise installations that move data and form the basis for an expanding field of creative applications—all of which form a feedback loop for more intelligence and more connectivity. Consumer devices like smartphones and tablets can now be used to remotely control and monitor industrial processes, medical instrumentation and more. The data they deliver for their intended appli-



Tom Williams Editor-in-Chief

cations serves as fodder for creative ideas to combine and use it in new ways for even more applications. And we’re just getting started. What Intel, to its credit, has done is to articulate this phenomenon with a simple name and to make some concrete moves toward common methods of adapting and managing connected devices and the “Big Data” that they represent with what it calls its Intelligent Systems Framework. In addition, it has been lining up partners including OEMs, system vendors and system integrators into an organized effort—one that may well result in future industry standards. Now, the cynical may dismiss such moves as marketing strategies and it would be idiotic not to recognize such motivations. But this phenomenon is far too big for one company to “own,” even a company the size of Intel. On the other hand, it took a company of Intel’s stature to articulate some of the large tasks that need to be done to make a new world of ever-growing data manageable and to initiate ways of moving toward that. Many people and many organizations will need to work in a sense of mutual interest and shared creativity to build out a world of data that can benefit everyone. And here I realize that I am repeatedly using the word “data” rather than “devices.” Devices, while essential, are also almost incidental to the generation and flow of data because the data, and the control it bestows, will be what we concentrate on to build applications. Devices (and servers, etc.) will be enlisted as needed to serve those ends. The world has changed. It was sneaking up on all of us for some time, and now that we can possibly agree on what to call it, we will all be able to more fully describe it and give it direction. That direction will not be determined by one group, company or individual. It will involve many issues of performance, connectivity, security and data management. The synergistic effect will be that people using data for purposes they originally intended will be able to use that data and then be inspired by data generated from different and perhaps unexpected sources to create even newer and unexpected applications. Someone once described standards as “agreement on the shape of a stadium in which to compete.” For the benefit of the industry as a whole, the concept of Intelligent Systems should evolve into an environment where innovation and creativity can prosper. It is a very big concept and a field of vast opportunity. There is a lot to do.

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INSIDER OCTOBER 2012 Android App for Automation and Control Systems Wins First Place Award At ISA ExpoControl 2012 in Mexico City, industrial automation manufacturer Opto 22 was in the winner’s circle. Opto aPAC, the company’s Android application for monitoring and managing the company’s SNAP PAC System, received the ISA exhibition’s first place award in the category of New Innovations. Opto aPAC provides real-time control system access and information to authorized automation professionals equipped with wireless, Android-based smartphones or tablets. Control engineers, maintenance personnel, instrumentation technicians and panel builders can use Opto aPAC to discover SNAP PAC controllers and I/O systems and then view, debug and fine-tune them, saving time and money during commissioning and ongoing maintenance. Opto aPAC is the first Android-based mobile app for automation and control that requires no initial configuration. Unlike mobile HMI apps where it’s necessary to first build an operator interface for the mobile device, Opto aPAC retrieves all information as soon as it is connected to a SNAP PAC control system. Opto 22 wireless controllers and I/O are not required. The Opto aPAC app is available for download now from the Android Market (

4DSP to Commercialize NASA Fiber Optic Technology

4DSP has announced that it is officially launching live industry demonstrations of licensed NASA fiber optic sensing and 3D shape rendering technology that could help radically improve efficiencies, safety and performance in a wide variety of industries. 4DSP licensed the fiber optic sensing technology in June 2011 and was granted licensing rights to NASA’s 3D shape rendering technology on July 21, 2012. Vulliez notes that NASA-licensed technology could represent a quantum leap forward for industries as diverse as automotive, aerospace, oil & gas, nuclear energy, medical devices and wind energy. Past fiber optic sensing solutions have



been limited by both processing speed and high deployment costs. 4DSP’s fiber optic sensing and 3D shape rendering technology will enable product designers in more industries to create highly scalable fiber optic sensing solutions capable of monitoring tens of thousands of sensors up to 100 times per second. Components of the technology were initially developed at NASA’s Langley Research Center, and NASA Dryden then matured and added components to the technology making it what it is today. According to the company, the NASA fiber optic sensing and 3D shape rendering technology has the potential to save industries and consumers millions, if not billions, of dol-

lars. From commercial aircraft manufacturing design to surgical endoscopes, the applications of the NASA fiber optic sensing technology are potential gamechangers.

Super Long-Life Tritium Battery to be Commercially Available

City Labs has announced that it has created a commercial version of a tritium battery called the NanoTritium, which can deliver power in the nanowatt/microwatt range at extreme temperatures for twenty years and more. It appears to have the distinction that it can be delivered to the end user without any specialized radiological training or regulatory documentation. Tritium batteries use an isotope of Tritium produced as a by-product in certain nuclear reactors in a technology called betavoltaics because the beta (electron) emitting radiation is used to produce electricity. Since Tritium has a half-life of 12.3 years, only half its fuel will be consumed in the first 12 years. Tritium is often described as one of the most “benign” radioisotopes and is used within the battery in solid form. Still, the price won’t be cheap and is initially estimated in the multithousand dollar range. Of course, one can expect that to come down as more are produced and find their way into specialized applications. These would include things like pacemakers and medical instruments that are implanted in the body, remote sensors for numerous uses such as deep water drilling and observation, security devices, sensors for structural integrity and many more where the savings for alternative shorter-life batteries and their maintenance will justify the cost.

Machinery Production Slows: Stepper Sales Boosted by Medical and Commercial Markets

According to IMS Research, recently acquired by HIS, the market for stepper systems is expected to feel the cooling trend observed in machinery production output, with stepper systems sales forecast to slow from 4.3 percent growth in 2012 to 3.8 percent in 2013. Bucking this trend, stepper sales to the medical equipment and commercial markets are gaining momentum with 2013 expectations set to outpace current performance. Industrial machinery represents the largest user of stepper systems, accounting for nearly 70 percent of stepper sales in 2011, according to IMS. Thus the steppers market is closely tied to machinery production output, which rebounded strongly after the recession. While machinery production grew 16.7 percent in 2010 and 12.4 percent 2011, the economic crisis in Europe and China’s cooling economy is slowing industrial output, and growth in this stepper systems market is forecast at 3.5 percent in 2013. Growth in the medical equipment and commercial markets will help to buoy the stepper systems market as machinery cools. Although the stronger growth of steppers in medical equipment forecast at 6 percent for 2012 is expected to continue in 2013, this market only represents 16 percent of the total steppers market in 2011. IMS Research Analyst Michelle Figgs explains, “Stepper systems are sold into a variety of applications and the forecasted market growth reflects this. As machinery production slows with the worldwide economy, the steppers market will be negatively impacted, but this will be par-

tially offset by the strength of the medical equipment and commercial markets. Therefore, the total stepper market is forecast to slow, but to a lesser extent than machinery production output.”

Kontron and Polaris Networks Demonstrate Endto-End LTE EPC Platform

Kontron showcased its technical collaboration with Polaris Networks on an LTE Evolved Packet Core platform solution that is suitable for deployment in Tier 2 and Public Safety LTE networks, at the AdvancedTCA Summit held in September. The joint demonstration combined a Kontron carrier grade MicroTCA platform (OM60601) and its various storage and multicore processor AMC modules with the Polaris Networks LTE NetEPC Solution. The Polaris NetEPC combines the functionality of the Evolved Packet Core (EPC) including the Mobile Management Entity (MME), the Serving Gateway (S-GW), the Packet Data Network Gateway (PDN-GW) and the Home Subscriber Server (HSS) as per 3GPP standards, making it suitable for Tier II-III deployments by Operators & Public Safety Departments. The Kontron 1U OM6061 MicroTCA platform features six AMC bays populated with three AM4020 processor AMC modules designed with the third generation Intel Core i7 processor. Lab validation and benchmark testing shows that the joint Kontron-Polaris solution is able to handle up to 128,000 simultaneous users, including support for all signaling procedures, such as UE Attach, Detach, Default and Dedicated Bearer Establishment, Modification and Termination, Paging and Service Requests, Handovers, Roaming, Multiple PDN Connectivity, and Trace among others.

Green Hills MULTI Tool Chain Certified as a Functional Safety Support Tool

Green Hills Software has announced that its Multi tool chain has been certified to meet the highest levels of tool qualification specified in the IEC 61508:2010 (Industrial), EN 50128:2011 (Railway) and ISO 26262:2011 (Automotive) functional safety standards. Green Hills has received certificates from both TÜV Nord and exida, making the Green Hills Multi IDE the only commercially available toolchain certified to satisfy both SIL 4 (Safety Integrity Level) and ASIL D (Automotive Safety Integrity Level) tool qualification requirements. The rising complexity of embedded software is requiring many markets and government agencies to demand product certification to proven standards for functional safety,” commented Dr. William M. Goble, president of exida. “To address this demand, Green Hills Software has worked together with exida to complete the first ever commercially available tools certification for its Multi tools offering, thereby significantly reducing the time and cost for end customers to certify their product offerings.” The availability of qualified Multi tools delivers customers significant product development cost savings by lowering cost and time-to-certification, reducing product time-to-market and reducing certification maintenance after product release. These combine to enable customers to assign their critical internal resources to unique added product value and development instead of ancillary tools efforts.

Eurotech in $60M Contract to Power Positive Train Location System

Eurotech has announced they have received a contract from Science Applications International Corporation (SAIC) for a total estimated value of 60 million USD over a 3-year period to supply the Eurotech system as the embedded platform for a Positive Train Location (PTL) system. The first few units will be delivered during the second half of 2012, and deliveries will ramp up to full operational pace in 2013. The Federal Railroad Administration and the North American railroad industry have been developing various elements for a Positive Train Control (PTC) system. The industry is now focusing on train length data accuracy and positive determination of train location through PTL projects. The first phase of the project uses the ISIS ICE, a rugged subsystem based on the low-power, high-performance ISIS single board computer, which was certified last year as one of two hardware reference designs for PTC applications. The ISIS ICE offers fanless diskless operation, combined with wireless communications, GPS options and flexible PC/104 I/O and communications expansion. The ongoing deliveries for this SAIC contract consist of the Eurotech computer on module, Catalyst TC, with custom board set and enclosure.

Event Calendar 10/29-11/1/12 MILCOM ‘12 Orlando, FL

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12/06/12 Real-Time & Embedded Computing Conference Phoenix, AZ

If your company produces any type of industry event, you can get your event listed by contacting This is a FREE industry-wide listing. RTC MAGAZINE OCTOBER 2012



FORUM Colin McCracken



is the season once again. Politicians seek elected offices, and we choose them by casting votes. Majority wins, and the weight of individual votes are equal. Winners go on to influence the direction of government. As voters, we accept the outcomes even if our candidates don’t win, but participation is nevertheless essential. As embedded system developers, we exercise our Bill of Rights by creating our bill of materials (BOM) at the system level. It’s a laundry list of all of the components that we must make or buy. From flash to processor(s) to displays to connectors to cables, the output of our R&D process is a plethora of parts for Purchasing to procure. But how does this really come to pass? There certainly aren’t governmental bodies that administer the collection of component applicants onto local ballots to pass around to system OEMs. Regulatory agencies exist in our space, yes, but they are focused on compliance. Instead, a device is defined with required features and cost targets deemed necessary to succeed in the market and meet company profitability goals. With such a set of requirements in hand, engineers select building blocks to piece together. Functional decomposition and analysis, together with inevitable architectural trade-offs, plays a major role in the identification and ultimate selection of vendors and products. But the supply chain must be a generation or two ahead in product planning and technical innovation due to their own R&D lead times, to make products available when they are needed by system OEMs. As a developer, you play a critical role in considering component candidates. Meticulously, you scour the web, call in reps, research technology trends, digest technical articles and user manuals, order samples to test, and even comb through vendor financials or other available supplier information. The extent of your “background checks” determines your reputation in the long run. Not doing your homework up front could send your product line and company in an unpopular direction.



This election season may seem overwhelming. Four years ago, maybe there was only one viable processor vendor, a few SBC vendors, a particular small flash form factor, one thermal solution, and several qualified LCDs from which to choose— such a simple ballot to fill out in hindsight. The last several years have ushered in massive competition among CPUs, module form factors, firmware vendors, OS and tool vendors, displays, connectors, ruggedized components, and the list goes on and on. Good luck with that. Besides the products and technologies, vendor “pitches” and trade show keynotes can sometimes be deceptive or elusive, like campaign slogans and statistic-slanted rhetoric concocted by marketing “spin doctors.” Some candidates, like the stackable PC/104 ISA bus for example, stubbornly will not die, even going hand-in-hand with PCI Express and USB in what seems like an impossible Hollywoodesque marriage. Sometimes you must dig below the surface and challenge conventional wisdom on your path to picking a perfect processor product. You might believe that something is dated, yet a simple search reveals widespread long-term support commitments. Old, simple technologies might always be lower cost, easier to design with, and have reduced noise susceptibility and EMI emissions, for instance. Some technology demonstrations or form factors might look like the new wave but never achieve economies of scale for cost reductions. But the net of all this is quite simple at a high level. The future of the embedded market is in your capable hands. For even though you do not invent the technologies you buy, your vote selects among competing products and innovations. The best technologies that suit the most applications will win. You vote with every design decision. Your buyer formally casts votes with every purchase order, and revenue helps competent suppliers survive and grow. In the high-tech marketplace, we don’t worry about electronic voting machines or “hanging chads.” Embedded is loaded with suppliers of all sizes serving all market segments, so every vote counts. Don’t just wait and let others set the direction for you. Get out and vote!

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editor’s report Digital Home Opportunity for OEMs

Digital Home Devices to Offer Increased Opportunities for Embedded OEMs The much touted digital home may have started off with lighting and thermostat controls, but it is rapidly expanding to more advanced security, energy management and lifestyle enhancement applications and beyond as the ecosystem grows. by Tom Williams, Editor-in-Chief


ith embedded systems spreading well beyond industrial environments, they have become pervasive in peoples’ everyday lives. The trick has been to design such systems so that the user is dealing with the external functionality and is relatively unaware that behind it lies complex electronics, microprocessors and software. So the gas pump is still the gas pump even though the display is digital and it automatically reads the credit card, prints a receipt and offers a discount on a car wash— while simultaneously displaying advertising on a screen while the vehicle is being filled. The line between what was once considered “consumer electronics,” such as TVs and stereos, has long since been breached by the invasion of microprocessors and microcontrollers into everything from toasters, toys, cash registers and tablets up to automobiles and the signs in stores. The list is endless. Small wonder then that the march of embedded has been defining what is increasingly being called “the digital home.” Since most homes now already have multiple personal computers, smartphones, tablets and, increasingly, Wi-Fi networks, the idea of adding digital control to such things as light switches, appliances, window shades,



thermostats and more is almost a no-brainer. But beyond mere convenience of controlling normal devices with a controller similar to a TV remote, there are some very compelling motivations for moving toward the digital home. These include security, entertainment control, energy management and lifestyle enhancement, especially in the areas of home health for an aging population. And now the existence of a mature ecosystem of products is making it possible for consumers as well as utilities and service organizations to offer custom solutions from the very simple to quite complex and sophisticated (Figure 1). The Z-Wave Alliance is a consortium of over 160 companies that have collaborated to build wireless home control products that conform to the Z-Wave standard, which specifies a mesh network topology and a protocol stack that is compatible and interoperable all the way up to the application layer. The alliance certifies members’ products so that they are completely interoperable. While the devices are individually relatively simple and single-function, there is a great variety and they can be combined in almost endless combinations. These can then be configured with software

into sets of coordinated, purpose-directed functions, which can then be invoked by a button on a remote, a smartphone or tablet app or a remote computer over the Internet.

A Z-Wave Home Network

For the vast majority of Z-Wave implementations, the basis is a gateway (sometimes called a bridge) that connects to the Internet via Wi-Fi and also communicates with the various devices via the Z-Wave radio mesh network. Then, of course, there is a selection of devices from simple switches to motion sensors, energy monitors, IP cameras and so on. In addition, there will be a remote-style handheld controller for convenience. Gateways come with some version of control panel software that lets the user set up and configure devices for the type of behavior that is desired. Some services like Verizon require an online subscription while others supply a basic control and setup panel and offer apps for sale to control different devices and their interactive behavior. Not surprisingly, some Z-Wave offerings are from telecom companies such as Verizon and AT&T, some can be acquired as additional services from security alarm companies, and still others are available as do-it-yourself products from companies such as Loews, Home Depot and Fry’s Electronics. In addition, there are entrepreneurs starting to form service companies that specifically do comprehensive home setup services for applications that, as mentioned before, can become quite sophisticated. For example, when combined with an alarm system, the Z-Wave devices can be configured for an “away” mode that can be invoked at the push of a button on a remote or a key fob. Such a mode could set the locks, set the lights to turn on and off at times and in sequences to look like people were at home, activate indoor or outdoor cameras, turn off AC or heating, and also activate the alarm functions with communications both to security services and to the user’s smartphone or tablet. Alternate modes can be programmed for use while people really are at home such as having motion sensors turn lights on and off. Combined with such scenarios, the possibilities of energy management are becoming increasingly attractive. Devices for monitoring power consumption are avail-

editor’s report

able for application to the whole house or to individual devices or appliances. A number of them are able to respond to alerts from electrical utilities for load shedding or thermostat adjustment in accordance with demand response arrangements as well as to respond to time of day pricing for optimum power usage. Of course, applications are also available and can be set up to give users an analysis of their home power consumption in order to help optimize their consumption. A very promising and rapidly growing area for the application of digital home control is to assist “aging in place” desires of seniors who want to continue to live independently as long as possible yet be assured that assistance is available if needed. This is separate from applications in telemedicine where the data from blood pressure meters, oxymeters, heart monitors and the like are transmitted to medical centers via the Internet. It can, of course, be used in conjunction with such devices, which generally communicate with a computer gateway via Bluetooth and an Internet connection.

Figure 1 While individual home control devices may be relatively simple and single function, they can be configured in ways to behave and interact that can result in very sophisticated applications. In addition, these devices may not remain so simple for long.


Figure 2

32 KB Flash Memory

System Clock

General Purpose Timer

Reset/ Brown

Z-Wave SW API User Application SW

Timer 0/1


8/12 Bit ADC


128 bytes SRAM


8051 Debug

Triac Ctrl

Power Mgt.

Interrupt Ctrl

SPI Ctrl



8051 CPU


RF Transceiver

Frame Handler


I/O Interfaces



Analog In


Triac Out

Block diagram of a Z-Wave module with a third generation chip based on an 8051 microcontroller core. Various interfaces are available for controlling and interacting with selected devices along with a low-power radio transceiver. Bit rates of 9.6, 40 and 100 Kbit/s are available.



editor’s report By configuring standard home control devices in specific ways, it is possible to set up systems that can monitor a home situation and issue alerts if necessary. For example, if an elderly person gets up to use the bathroom at night, it is dangerous to do so in the dark. Therefore, motion sensors can be programmed to detect someone getting out of bed and turn on selected lights in a dimmed condition so as not to blind the person with glare. It then waits a given amount of time to detect motion that would indicate a return to bed. Should, as often happens, a person slip and fall in the bathroom, they could be trapped there for days. But if motion is not detected after a certain amount of time, the system could send an email, or if more urgency is desired, place a phone call or even alert 911. All this and even more creative scenarios can be set up with just the basic Z-Wave devices and the gateway configuration software, which is designed to be intuitive for the nontechnical user. Of course, developing such software and devices, which despite their current relative simplicity will become increasingly sophisticated as well, requires effort and skill on

the part of OEMs. Currently there are well over 700 Z-Wave-compatible devices on the market with more on the way. In addition, the latest generation of Z-Wave silicon is moving to support IP while retaining backward compatibility with existing and future devices. Z-Wave technology is built around a low-power SoC design (sleep current 3.2 ÎźA) that itself is based on an integrated 8051 microcontroller core and a radio transciever. Successive generations include increasing amounts of program memory, radio frequency selections and I/O pins. All are compatible. Further power savings is due to the mesh network technology, which automatically routs the RF signal from node to node using a Tx/Rx current of 34/28 mA in the fourth generation chips. The silicon is also offered on a series of modules for easier development and integration (Figure 2). Also available to OEMs is the Z-Wave Home Control Development Kit produced by Sigma Designs. The programmer/development kit includes a reference design module, cables, antenna and other hardware needed to get started. Kits are available in different regional versions to accommodate the radio frequencies that have been allo-

cated in different geographical regions. A software development kit (SDK) is also available via download, which includes the Z-Wave protocol stack, documentation, data sheets, protocol libraries and sample applications. Not included but also required for application development is the PK51 8051 compiler from Keil Embedded Development Tools. As Z-Wave moves toward IP support in its fifth generation and builds momentum, it is clear that devices will become more complex as will their internal application code. That will mean even more opportunities for advanced configuration of different devices in increasingly diverse and specialized application scenarios. Z-Wave Alliance []. Keil Embedded Development Tools Plano, TX. (972) 312-1107. [] . Sigma Designs Milpitas, CA. (408) 262-9003. [].

Professor Artila’s Tips on Embedded Computing

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// +1 (714) 671-9996

Authorized Distributor 10/8/12 10:11 AM

ploration your goal k directly age, the source. ology, d products

Technology in

context Blades and Backplanes

Standardized LAN-Attached Management Controllers Yield xTCA Performance and Serviceability Gains LAN-attached management is leading to faster and richer system management applications in ATCA and MicroTCA systems, both of which also use ATCA cards. by Mark Overgaard, Pigeon Point Systems


very board and module built for nect to a much faster in-shelf serial the popular xTCA open modular fabric, often Ethernet. LAN-attached ecosystem must have a local man- xTCA controllers connect to such a agement controller, and each controller fabric to supplement the much slower must have an I2C-based link to its man- I 2C link. “LAN-Attached TCA Management parent. These management con- agement Controllers: How to Build and trollers and the I2C “network” that links Use Them” in the October 2009 issue of nies providing solutions now to the widespread adopthem are crucial RTC, introduces this concept, which is ion into products, technologies and companies. Whether your goal is to research the latest tion of xTCA in telecommunications already widely used in xTCA products. ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you and (increasingly) in other applications, The news now is that LAN attachment you require for whatever type of technology, drive a half billion dollar is standardized for xTCA controllers, and productswhich you are already searching for. annual xTCA market, as AdvancedT- with the recent adoption of the PICMG CA (ATCA), the dominant segment of Hardware Platform Management (HPM) xTCA, enters its second decade. xTCA HPM.2 and HPM.3 specifications. Pialso includes MicroTCA (µTCA) and geon Point Systems proposed and chairs AdvancedMC (AMC), a hot swappable the PICMG subcommittee that has demodule architecture used in both ATCA veloped these specifications. and µTCA systems. Figure 1 shows the LAN-attached At the same time, most of those management framework for ATCA and boards and modules—collectively, field µTCA, along with ways to take advantage replaceable units or FRUs—also con- of that framework. Without the management controller LAN connections, external network clients are typically limited to Get Connected interacting with management controllers with companies mentioned in this article. indirectly via a shelf manager.

End of Article



Get Connected with companies mentioned in this article.

What Applications Benefit?

Two of the applications shown in Figure 1 were introduced in the October 2009 article referenced above: firmware upgrades and serial over LAN. What new facilities in these areas result from the adoption of the Hardware Platform Management (HPM) HPM.2 and HPM.3 specifications? Both benefit from the overall strengthening of the LAN attach infrastructure in HPM.2 and the standardized IP address management facilities of HPM.3. For firmware upgrades, the most important new development is a standardized way to support the large Intelligent Platform Management Interface (IPMI) messages (hundreds of bytes in size) that are possible over Ethernet, compared to the 32 byte limit for Intelligent Platform Management Bus (IPMB) messages. This difference can contribute 20 percent or more to the 10x or more faster upgrades that are possible with a LAN attach connection.

technology in context

Overall System Manager and/or Network Client

Serial Over LAN Client Shelf Manager

Action 1

µC Data

µC Data

Action 2

Action 2

Upgrade Images

PLD Data

Serial Console Interfaces

Carrier IPMC C

Payload CPU

MMC (µC)



Console Dialogue Window

Manager Interface

Carrier Manager MCMC D


Action 1

Links to In-Shelf Ethernet

Header B



Header A


Upgrade Agent

Serial Console Interfaces

MCMC Console Pane


Payload Console Pane


Payload CPU



Shelf Manager

IPMI Messaging Trace Analyzer Trace Window

MMC (µC)

Trace for Carrier IPMC C IPMB-o/L

Figure 1 LAN-attached management framework for ATCA and µTCA shows applications for management controller LAN connections (the dashed line links).

The entire serial over LAN facility is more robust in HPM.2, including support for over 250 serial ports per FRU and a mechanism for a network client to get a list of the available ports on the board. The detailed architectural provisions in HPM.2 facilitate additional applications, such as direct interactions with a management controller by an overall system manager or other network client. An xTCA system manager can monitor dozens or even hundreds of shelves. Most of the system manager’s interactions occur with the shelf managers of those shelves to get shelf level summary information. Some system managers also rely on frequent interactions with lower level controllers. For instance, when a new shelf goes under management, the system manager may need to fetch thousands of bytes of descriptive information about its controllers; doing that over LAN can make a dramatic difference.

Then there are shelf manager interactions. Most of the messages between a shelf manager and one of its controllers are engineered for the low transfer rate of IPMB, but sometimes big or especially numerous transfers are necessary. For instance, when a new shelf starts up, the shelf manager may need to retrieve descriptions for thousands of sensors and field replaceable units (FRUs) in the shelf. Doing such retrieval via LAN can drastically reduce the startup time, making the shelf usable and fully manageable earlier. Furthermore, even though the routine messaging in a steady state shelf can be handled fine by IPMB, important messages can be seriously slowed during a period of high IPMB usage for other purposes, such as firmware upgrades or heavy system manager interactions. Both of these applications are dependent on HPM.2 compliance in the lower-level controllers and are not really feasible without such standardization.

Another class of LAN attach applications is simply not practical with only IPMB connections to a shelf’s controllers. This class includes the serial over LAN application mentioned above, in addition to IPMI message tracing. xTCA management is based on the IPMI messaging architecture and those messages can flow across a LAN connection as well as an IPMB. In either case, for system diagnosis, having access to traces of such messages can be highly beneficial; consider, for instance, the IPMB-L traffic among a Carrier IPMC like controller C in Figure 1 and its subsidiary (type A) MMC(s). Clearly, attempting to provide a trace of IPMB traffic across IPMB itself would be folly, so a LAN attach connection is vital for IPMB traffic diagnosis via traces. xTCA controllers and these applications implemented in accordance with HPM.2 and HPM.3 can be from different vendors and even completely different implementations and still be interoperable. RTC MAGAZINE OCTOBER 2012


technology in context

Extended Management Power Domain

Sideband Interface

A2F060/200/500 MMC


Serial Console Interfaces

Payload CPU(s)

Ethernet Network Controller(s)

IPMI Traffic with MMC

Figure 2

Ethernet Traffic with Payload CPU(s)

AMC Carrier Ethernet

LAN-attached MMC connected via sideband interface to shared network controller.

What Is HPM.2 and What Does it Cover?

PICMG HPM.2, the LAN-Attached IPM Controller specification, covers LAN attachment for any xTCA board or module controller and uses “IPM Controller” as a generic term to stand for all the xTCA FRU controller types. Figure 2 shows a simple LAN-attached controller, in this case an MMC. In this and the Figure 3 example, the controller is based on Microsemi Corporation’s SmartFusion intelligent mixed signal FPGA. This FPGA comes in several models, A2F060 through A2F500, which are primarily distinguished by their logic capacity. “Customizing a Microcontroller



for Hardware Platform Management” in the June 2011 issue of RTC provides more background on SmartFusion-based management controllers. In the MMC example, there are Ethernet controller(s) already on the AMC to provide connectivity for the payload CPU(s) to an Ethernet fabric implemented on the AMC carrier. The MMC shares access to that Ethernet connectivity via a sideband interface implemented in the network controller, which combines IPMI traffic with the MMC and generic Ethernet traffic with the payload CPUs so that no dedicated management Ethernet is needed to support direct interactions with the MMC. The June 2011 RTC article ref-

erenced above provides more details on sideband interfaces, including a widely implemented open standard sideband interface called NC-SI that effectively offers a 10/100 Mbit/s Ethernet connection to the network controller for the management controller. HPM.2 also explicitly covers the topic of extending the management power domain, as shown in Figure 2, to include the network controller in addition to the MMC, so that interactions with the MMC are fully viable, even if the payload CPU complex is unpowered or faulted. The AMC specification limits 3.3V management power to 150 mA, which is likely not enough for both the MMC and a gigabit class network controller. Therefore, an implementation like this probably has to supplement the management power with a portion of the 12V payload power supplied to the AMC by its carrier. Another similar challenge has to do with the electronic keying (e-keying) that xTCA uses to manage carrier and backplane links, such as the AMC carrier Ethernet(s) in this example. Normally xTCA e-keyed links are not enabled unless the payload is operational, but that would significantly reduce the utility of links used for management, since many of the most important diagnostic and performance benefits happen with the payload off either purposely or due to a fault. Figure 3 shows a more complex LAN-attached controller example: a Carrier IPMC (IPM Controller) that implements local management for an ATCA board that provides AMC slots (four of them in the example). Again, the management Ethernet traffic is shared with payload-oriented traffic, but also in this case with AMC module traffic, all enabled by an Ethernet switch that connects with the ATCA backplane’s Base Interface Ethernet. Conveniently, a management controller that supports an Ethernet-based sideband interface can use exactly the same port to make a direct connection with an Ethernet switch, as in this example. Here, the extended management power domain needs to include the base interface switch, which may require substantial power. Fortunately, the management power budget for an ATCA IPM

technology in context

AMC Module Management Sites AMC Control


A2F200/500 Carrier IPMC

Serial Console Interfaces


Extended Management Power Domain

Direct Ethernet Link

Power Control


Payload CPU(s)

Embedding Excellence

AMC Module Ethernet Links

Base Interface Switch

IPMI Traffic with IPMC

Figure 3

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LAN-attached Carrier IPMC connected via shared Ethernet switch.

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tion of the HPM.2 specification, which also covers additional advanced features, such as ways for a network client to take advantage of redundancy in network paths to a management controller.

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Where Does HPM.3 Fit In?

PICMG HPM.3, the DHCP-Assigned Platform Management Parameters specification, addresses an additional challenge not mentioned so far: how do all those management controllers get Internet Protocol (IP) addresses assigned so they can communicate over the in-shelf LANs? Every IP address has to be unique within a given network domain, and a domain (such as a large mobile switching center) could have thousands of management

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Controller is 15W, which may be enough. If not, some of the payload power budget must be used to supplement management power, and power budget negotiations with the shelf manager for this board must reflect that. Furthermore, the extended management power domain in this example extends even to the MMCs on AMC modules hosted by this carrier, as shown in the figure. The likely need for 12V payload power for LAN attach connections on those modules adds to the AMC carrier power implementation and budgeting challenge. Supporting the above facilities in an implementation-independent and interoperable fashion takes a considerable por-

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MSC Embedded Inc. direct: (650) 616 4068



3/1/12 9:52:51 AM

technology in context

Board 2, AMC 5 (B1) Board 7

Shelf Manager 2

Logical Shelf Manager (0) MCH 1 AMC 12

Logical Shelf Manager (0)

Aisle9-Frame3-Shelf2 Aisle9-Frame3-Shelf1 µTCA ATCA

Server Switch

OceanServer Digital Compass Products:

Aisle9-Frame3-Shelf3 ATCA

Board 7 Board 14, AMC 6 (B2)

Logical Shelf Manager (0) Key

Ethernet Uplink System Manager Shelf Manager Board/Module Management Controller

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1/12/10 10:03:31 AM

Example xTCA frame showing representative HPM.3-style FRU identifiers.

controllers. Figure 4 shows an example frame or rack. One key to the puzzle is the Dynamic Host Configuration Protocol (DHCP), an Internet standard for managing IP addresses and related networking parameters. In DHCP, one or more servers in a network domain are in charge of dispensing network parameters, including IP addresses; clients in the domain use a standardized protocol to discover these servers and request parameters. In order to ensure that each such client, such as a LAN-attached management controller, gets a unique set of parameters, each client must provide a unique identifier. HPM.3 defines a vendor- and implementation-independent way to identify client management controllers that allows uniqueness to be ensured, while also allowing the data base to be set up just once for a given installation, with no changes

required when boards, modules or even entire shelves are replaced. In HPM.3, management controllers identify themselves by their location. The first part of the location is a shelf address, which could be geographic coordinates that designate the aisle, frame and shelf position. When a frame of xTCA shelves, like the example in Figure 4, is provisioned or installed, non-volatile storage in each of the shelves is updated with the coordinates that uniquely identify it. If a given shelf is replaced, the replacement shelf gets the same coordinates and uniqueness is preserved. Each of the shelves in Figure 4 is labeled with a simplified shelf address. The second part of the location is the coordinates of the board or module within a shelf. xTCA FRUs can determine those coordinates from the slot in which they’re installed, so a board or module replacement doesn’t require any reconfiguration at all. The replacement board identifies itself indistinguishably from its predecessor in the same slot and gets the same address assignment from DHCP. Figure 4 shows some simplified examples of FRU identifiers. In the example, several of the ATCA boards are AMC carriers; the two AMC slots that each of them implement, according to the AMC specification, are designated B1 and B2, with corresponding numeric values of 5 and 6. Also, there are several instances of logical shelf manager identifiers; these are used to get IP address assignments for the main interface used by a system manager to connect with a shelf, independent of which of the two redundant shelf manager instances is active. Location-based identification for xTCA FRUs fits well with a frequently used approach to xTCA system architecture, where specific application responsibilities are assigned to particular slots or sets of slots in shelves and the boards in those slots handle those responsibilities. Assigning IP addresses in the same way can be very convenient. Pigeon Point Systems Oceanside, CA. (760) 757-2304. [].

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Technology in

context Blades and Backplanes

PCIe Card Instantiates the Next Generation Communications Platform from Intel Intel’s new communication platform, code named Crystal Forest, promises new abilities to handle the vastly increasing amounts of network data. A board-level instantiation now allows OEMs to quickly upgrade existing systems and points the way for future designs. by Chiman L. Patel, WIN Enterprises


ata, like the universe, just keeps expanding at an ever greater rate, pushing out from the enterprise and rushing in tsunami-like from customers and a host of other entities. User expectations are that compute resources are limitless in their ability to deliver data. At the same time, the quality and richness of information has increased as broadband data has become more the everyday norm. The good news is that if we are able to continually scale our networks to deal with the broadband data onslaught, we should soon see a world of holograms, streaming genetic code and automated highways capable of giving us a better tomorrow. However, scaling networks to meet these challenges is a daunting task. The major reason is that networks are built on complex, heterogeneous microarchitectures. This is in order to accommodate the combination of generalized and specialized networking processes, such as encryption/decryption acceleration, packet scanning, etc. In addition, individual processes typically have their own set of tools and knowledge bases making overall maintenance efforts unwieldy. The bene-



Figure 1 WIN SoNIC supports 8x PCI Express Gen2.0 connectivity. The form factor is the half-length PCIe card. Three Intel 82599ES chips (code-named Niantic) support dual 10 Gbit/s capability. The preprocessor chip is a Xeon Sandy Bridge/Ivy Bridge processor (code-named Gladden). The Cave Creek chipset features Intel QuickAssist Technology.

fits of a unified, easily scalable platform that can handle multiple workload types become obvious.

Intel Crystal Forest Platform

The Intel Crystal Forest platform leverages the strong presence of Intel within

the communications infrastructure, plus the power of multicore Xeon processors such as Sandy Bridge and Ivy Bridge, additional new technologies, and existing industry standards including PCI Express and 10G fiber-based Ethernet. The platform integrates these technologies to

technology in context

enable the consolidation of three processing workloads—application, control and packet/content. The platform provides highly efficient content processing and deep security scanning to provide secure network traffic across a variety of environments from cloud computing down to more modest SMB networks. Three things make Crystal Forest especially significant. First, it is a thoroughly backed Intel strategy for futureproofing data center networks, and it offers high-level security with a focus on deep packet inspection. In addition, it provides a unified platform to consolidate network workloads, categorize data for efficient handling, and offer new service options as well as perform more efficient customer billing.


The System on Network Interface Card (WIN SoNIC) is a board-level instantiation of the Intel Crystal Forest platform from WIN Enterprises (Figure 1). It is a networking expansion board made available to OEMs for the development of next generation network security products and 3G/4G back-haul networking systems. The board combines with new and existing servers through a PCIe slot to deliver Xeon-class preprocessing, dual-10 GbE LAN, crypto acceleration, deep-packet inspection, and the efficient disposition of data types. It also serves as an example of how the new Intel platform could potentially be used in other form factors and designs. The PCIe interface makes it quickly useable for upgrading existing systems. The ability to preprocess high-speed data streams opens up new network design possibilities for the data center. This simple, plug-and-play hardware can eliminate today’s processing bottleneck, better secure the data center from threats, and de-duplicate and compress data for greater networking efficiency. A list of features and benefits is shown in Table 1. The board utilizes the components of the Intel Crystal Forest platform including the Intel 82599 Family 10 Gigabit Ethernet Controller that supports dual 10G Ethernet ports; a Xeon Sandy Bridge/ Ivy Bridge preprocessor (code-named Gladden); and next generation commu-



Intel 32nm Xeon BGA CPU featuring 2 or 4 processing cores and HyperThreading

Scalable path provided for Intel multicore processors

Next Generation Communication chip with Intel QuickAssist Technology (codename Cave Creek)

QuickAssist 1.5 Technology accelerates cryptographic functions, high-speed data compression, and pattern matching and deep packet inspection

Intel 82599 Dual 10GbE Controller (code name Niantic)

Supports advanced technologies, including Intel Virtualization Technology for Connectivity (VT-c); FCoE, NFS, iSCSI; IEEE 1588 time sync and Intel Direct I/O technology

PCIe x8 Generation 2.0 I/F

Allows WIN SoNIC to be easily connected to existing platforms

Integrated Dual-channel DDR3 Memory Controller Power Efficient SpeedStep Technology

TABLE 1 Features and benefits of the Intel Crystal Forest platform as instantiated on the WIN SoNIC PCIe board.

nications chipset from Intel, code-named Cave Creek. Cave Creek is significant to network security because it features Intel QuickAssist Technology. Intel QuickAssist Technology accelerates cryptography processes, packet processing and deeppacket inspection. The WIN SoNIC board is easy to integrate with any server that has an existing PCIe 2.0 slot. Implementation is low-risk and economical because the board can be used with existing products to create higher performance networking solutions. However, like all higher-level hardware, it requires software to fulfill its mission.


To speed a developer’s or OEM’s time-to-market, Intel offers the Data Plane Development Kit (DPDK). The Intel DPDK is important to manufacturers who are developing mid-ware or layered software for Crystal Forest Server platforms or who are porting existing deeppacket inspection solutions to IA-based platforms. The DPDK is a set of NIC drivers and libraries designed to optimize processor core usage and throughput performance. This important tool is downloadable from Intel and has already been implemented by members of the Intel Intelligent Systems Alliance, including Wind River,

6WIND, Radisys and Tieto Corporation. These Intel Intelligent Systems Alliance members have integrated the Intel DPDK into software solutions that provide an OEM solutions provider with faster timeto-market. These and other members of the Intel Intelligent Systems Alliance can also provide application-level development to OEMs wishing these services. By way of example, WIN SoNIC supports Wind River Intelligent Network Platform 3.0. This software optimizes the Intel multicore architecture to perform packet processing. Using the software, different layers of the networking protocol stack are processed in parallel on different processing cores. This provides high overall throughput and efficiency. Most software optimized for multicore processing uses a symmetric multiprocessing (SMP) approach where each processing core is used in the same way. However, the Wind River Network Acceleration Platform uses an Asymmetrical Multiprocessing (AMP) model that establishes a management plane and separate acceleration plane. These use different operating systems resulting in faster processing and throughput. The features of the Wind River Intelligent Network Platform include: • IP Routing/Forwarding • Layer 4 Acceleration RTC MAGAZINE OCTOBER 2012


technology in context

• Custom Layer 2 and 3 Processing • IP Sec acceleration/termination • Compression • VLAN (QinQ) • 1 and 10 Gbit/s drivers • Intel DPDK

as well as software from other Intel Intelligent Systems Alliance partners.

System Components

The layout of the WIN SoNIC board and, by extension, the use of the Intel Crystal Forest platform, is shown in Figure 2. Dual, 10 Gigabit LAN capabilities are delivered through the use of the Intel 82599ES Controller chip (code-named Niantic). Future Ethernet performance will be

OEMs wishing fast time-to-market for a solution-level Crystal Forest product have a ready path with WIN SoNIC and Wind River Intelligent Network Platform,



A New Level of SSD Security

Next Generation Communication Chipset from Intel

The chipset currently code-named Cave Creek serves as the chipset to the Gladden preprocessor on the WIN SoNIC board. A major feature of the next-generation communications chipset is Intel QuickAssist 1.5. QuickAssist provides an array of impressive security features. These include encryption/decryption using AES, 3DES or (A)RC4 algorithms, hashing using MD5, SHA-1/2 or HMAC algorithms, Deflate and LZS high-speed data compression. According to Intel, the chipset handles up to 160 million packets per second on server-grade Intel dual-core processors. In addition, Intel QuickAssist Technology provides support for wireless security protocol and pattern matching to identify malicious code and anomalies. It supports VT-d and VT-c virtualization to enable flexible configuration with downstream devices and databases. QuickAssist Technology enables high-speed, secure data compression, storage and data loss prevention. This latest version of QuickAssist (1.5) supports a range of preprocessing services that include Secure Socket Layer (SSL) acceleration, deep packet inspection and flow classification. In SSL communications the processing budget weighs toward the initialization and termination of crypto services. These are initialized through public and private security keys. These processor-intensive tasks are now


Email: website:

Power Matters.


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scalable to support 20, 40 and 100 Gbit/s. The forward compatibility of Ethernet enables easy upgrade of networks based on Crystal Forest platform technology. The WIN SoNIC card utilizes the Intel Xeon BGA 2 and 4 Core processors with up to 2.6 GHz clock speed and 8 Mbyte L3 Cache (code-named Gladden). Although the standard boards have preprocessors with two and four cores, the design offers forward compatibility to support even more powerful processors as they become available. This means intense communication applications such as security and busy data center operations are supported with even more capability to come. The Intel Gladden preprocessors support HyperThreading, Trusted Execution and Virtualization technologies.

6/6/12 3:52 PM

technology in context

offloaded to the Cave Creek chipset to unburden the system. Given today’s trend toward security attacks originating from organized malicious entities, deep packet inspection can be considered one of the most important features required by data centers of all types, including high-end financial, military and governmental agencies. In deep packet inspection data frames are reviewed at the field level to detect protocol irregularities. Protocol non-compliance can mean the presence of viruses, spam or malicious intrusions. Deep-packet inspection can also be used to identify predefined conditions that require special handling such as an automated response. Shallow packet inspection is also supported by QuickAssist. This is a less resource intensive function that scans packet headers for irregularities that might indicate attempted intrusions. Shallow packet inspection is an important feature that can also be used to optimize packet routing or to collect data for statistical analysis. Flow Classification examines aggregated data flows at the packet level to determine their best handling and disposition. After data is classified it may be routed to storage or other network segments, reviewed for access control, flagged for differentiated qualities of service (QoS) or monitored for automated billing. For instance, customers with more expensive payment schedules can be given throughput privileges for video downloads or similar services.

ciation of Securities Dealers regulation states that communications with the public may not predict security performance; and yet another regulation requires email messages to be filtered based on header information such as sender and recipient fields, as well as message content. Regulations like these and others cause system bottlenecks and reductions in organizational efficiency. These processing speed bumps can be flattened out through pre-

processing using this new generation of cards. Specific vertical applications can be designed for the platform by Wind River or one of the software ecosystem members of the Intel Intelligent Systems Alliance. WIN Enterprises North Andover, MA. (978) 688-2000. [].

Usage Examples

Despite a general perception to the contrary, financial services are subject to considerable regulation. For instance, the Gramm-Leach-Bliley (Federal Modernization Act of 1999) requires the use of authentication and encryption to protect nonpublic personal information found in email. In addition, email solutions are required to provide policy-based filtering and blocking, logging and reporting. These and similar tasks can be automated by implementing WIN SoNIC and layered software from a member of the Intel Intelligent Systems Alliance or developed inhouse using the Intel DPDK. In other examples, a National AssoUntitled-7 1


7/31/12 4:43 PM RTC MAGAZINE OCTOBER 2012


connected Computing vs. Electrical Power

Use Power Debug to Optimize Software for Minimal Power Consumption With power debugging, developers can synchronize and optimize their source code to minimize energy requirements. This ensures that their project is as energy-efficient as possible without compromising the performance of the application. by Anders Lundgren and Lotta Frimanson, IAR Systems


ong battery lifetime is an essential characteristic for embedded systems in market segments ranging from medical to consumer electronics. Traditionally, minimizing power consumption has fallen to the hardware engineers. In active systems, however, power consumption depends not only on the design of the hardware, but also on how it is used— which, in turn, is controlled by the system software. Using a technique called power debugging, software developers can map the power consumption of their systems to the program’s instruction sequence, allowing them to discover and remove errors in source code that increase power consumption. These debugging capabilities result in code that is as energy-efficient as possible without compromising the performance of the application. The IAR C-SPY debugger visualizes the power consumption data both statically and dynamically in different views and provides both power profiling and debugging opportunities for an application. In this article we will show how to use the various views and interlinked features of the debugger to improve the performance



PC (program counter)

PC sample clock

power value (mA)

ADC clock ∆T Figure 1 By time stamping the sampled power values and the PC samples it is possible for the debugger to correlate power data to the source code.

of a sample system by better than an order of magnitude.

How Does Power Debugging Work?

The technology for power debugging is based on the ability to sample the power consumption and correlate each sample with the program’s instruction sequence and hence with the source code. One difficulty is to achieve high precision with sampling.

The ideal would be to sample the power consumption with the same frequency the system clock uses, but power system capacitances tend to compromise temporal resolution, making it difficult to isolate power consumption to any one instruction. From the software developer’s perspective this isn’t necessarily a problem since it is more interesting to correlate the power consumption with the source code and various events in the program execu-

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tion than with individual instructions. The resolution needed therefore is much lower than one sample per instruction. The IAR I-jet debug probe measures the voltage drop across a small resistor in series with the supply power to the device (see “Power Debugging—Minimizing Power Consumption by Tuning the Code,” view/102734). The voltage drop is measured by a differential amplifier and then sampled by an A/D converter. The key to accurate power debugging is a good correlation between the instruction trace and the power samples. The best correlation can be done if complete instruction trace is available, as is the case for ARM MCUs with embedded trace module (ETM) support. The drawback with using ETM is that it requires a special debug probe and ETM support in the device itself. A less accurate approach, but one that still gives good correlation, uses the program counter (PC) sampling facility available in the ARM Cortex-M3/ M4 cores. The data watchpoint and trace (DWT) module implements the PC sampler, sampling the PC at around 10 kHz and triggering an instrumentation trace macrocell (ITM) packet for each sample taken. The ITM is the formatter for events originating from the DWT. It packetizes the events and time stamps them. The debug probe samples the power consumption of the device using an A/D converter. By time stamping the sampled power values and the PC samples, the debugger can present power data on the same time axis as graphs like interrupt log and variable plots, and correlate power data to source code (Figure 1).

can be useful to find peaks in the power sampling. Since the power samples are correlated with the executed code, it is possible to double-click on a value in the Power Log window to get to the corresponding code. Depending on the power sampling frequency, the precision will be different, but there is a good chance that you will find the code sequence that caused the peak. A few seconds into execution we see that the application is using almost 82 mA of power (Figure 2). Somewhere at the start of the program we have set up the application to consume a lot of power.

To find the location, we set the debugger and begin stepping through the code. The Power Log window shows us that initialization of the GP I/O port increases power consumption to nearly 70 mA. GP I/O port D is only used for diagnostic outputs, which we don’t require at this point in time, so we will comment out that portion of the code. After reloading the application and running it, the Power Log window shows that consumption has dropped to less than 10 mA. Another way to cut power consumption is to reduce the CPU frequency of

Power Debugging in Action

Let’s investigate the kinds of efficiency improvements that power debugging can deliver by running through a few examples. We will be using the EFM32 Gecko development kit from Energy Micro and the IAR Embedded Workbench for ARM. Our application is a burst waveform generator for a marine sonar system. First, we download the application and then we open up the Power Log window. The Power Log window displays a log of all collected power samples. This window

Figure 2 The Power Log window shows an average power consumption of almost 70 mA after initialization prior to debugging (top). That value drops by an order of magnitude once an unnecessary GP I/O port is deactivated (bottom).



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Figure 3 Cutting CPU frequency from 32 MHz to 14 MHz reduces peak power use from 3.5 mA to 2.5 mA.

the device. Let’s investigate what happens when we reduce the frequency from 32 MHz to 14 MHz (Figure 3). First, we open up the Timeline window. In the Timeline window the power samples are displayed in a time scale together with interrupt activities and up to four user-selected application variables. Also, the Timeline window is correlated to both the Power Log window and the Source Code windows, so you are just a double-click away from the source code that corresponds to the values you see on the time line. For this application we’ll choose the Power Log and the Data Log plots. The Data Log is a log of the data breakpoints we have defined in our application. We set up one for the wave trace to show our sonar as we run our application. After startup interval of roughly four seconds, our sonar bursts begin. If we drop down to the Power Log window, we can zoom in to look at individual peaks (Figure 4). Hovering over a peak brings up a text box



that displays the statistics; in this case it shows that current usage ranges from 1.6 mA to 10 mA. Now, we change the CPU frequency to 14 MHz, then we run the application again. The minimum current remains at 1.6 mA but the maximum current drops from 10 mA to 5 mA. If we check the debug logs, the application appears to be running just fine.

Function Profiling

In a task-oriented system, it is probably more interesting to see how a particular function affects power consumption than to see statement-by-statement how the power consumption changes. The Function Profiler will help uncover the functions where most time is spent during execution for a given stimulus. In this way, we can discover sections in the application that present potential for power consumption optimization. The Function Profiler window lists the number of samples per function, the per-

cent of energy usage, and also the average values together with maximum and minimum current values. In general, optimizing for power is very similar to optimizing for speed—the faster a task is executed, the more time can be spent in a low power mode. By maximizing the idle time, we can reduce the power consumption. Let’s use our test system as an example. As we can see in Figure 3, power consumption in our waveform generator rises to 5 mA almost as soon as the device begins generating a waveform, even when the generator is between pulses. We need to find a way to correct this. The EFM32 Gecko features multiple low-power modes that offer the potential to save a significant amount of power. What we will do is modify the code to put the EFM32 into Energy Mode 2 when exiting the main loop, and we will put it into Energy Mode 1 at the end of each sonar burst. We can check the energy savings of this behavior using power profiling. In

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power profiling, we combine function profiling with power sampling to measure the power consumption per function and display that in the Function Profiler window. In the Timeline window, we highlight an area of interest—in this case, three bursts—then bring up the function profile selection. Now we can sort to discover the functions that within the selection consume the most power (Figure 5). The list shows that our modifications worked—the system now spends more than 95% of its energy in idle mode.

Waiting for Device Status

One common mistake that could cause unnecessary power to be consumed is to use a poll loop to wait for a status change of for example a peripheral device. Code constructions like the examples below execute without interruption until the status value changes into the expected state.

Figure 4 The Timeline window allows us to zoom in to resolve individual power peaks; hovering brings up a text box with specifics. Double clicking takes us to the block of source code responsible for this performance.

while (USBD_GetState() < USBD_STATE_CONFIGURED); while ((BASE_PMC->PMC_SR & MC_MCKRDY) != PMC_MCKRDY); Another related code construction is the implementation of a software delay as a for or a while loop like in the following example: i = 10000; do i--; while (i != 0);

// SW Delay

This piece of code keeps the CPU very busy executing instructions that do not do anything except pass time. Consider another example with our EFM32 Gecko connected to an LCD display. We download the code and start the application. If we check the Function Profiler window, we see that the functions that handle the LCD are at the top when it comes to power consumption. The Timeline window reveals current spikes that indicate heavy power usage. Because the current values are correlated to the executed code, we can easily switch to the corresponding source code by doubleclicking on one of the values. The code that we reach is a while loop where the processor waits for the LCD to be ready for update. Because the CPU is

Figure 5 The Power Profiler sorts the function list by greatest energy usage, showing that the bulk of system energy is consumed by idle operations

running at full speed while waiting for the LCD, the power consumption goes up. Polling of a device status change should be solved with interrupts if possible, or by using a timer interrupt so that the CPU can sleep between the polls. The power debugging methodology described above gives the embedded developer the opportunity to examine the application program code and flow with regard to power consumption. In our

primary example, system power usage dropped from 82 mA to less than 3 mA. Power debugging can detect other opportunities for improving efficiency, including optimal use of peripherals and eliminating time spent in loops. IAR Systems Uppsala, Sweden. +46 18 16 78 00. [].




connected Computing vs. Electrical Power

Need a Many-Core Strategy? Has your boss asked for a “many-core” strategy yet? Get ready. Many-core is the next step in microprocessor evolution. It will change the world for most of us. by Jeff Milrod, BittWare


ost experts agree that the era of Moore’s law driving endless performance increases of legacy processors is ending, even though the transistor count may continue to climb. Therefore, the way we approach processing must change. It is no longer likely that we will be getting a bigger hammer next year. Since we are guaranteed that the problems will continue to get bigger, the inevitable conclusion is that we need figure out how to use, and coordinate, more small hammers. In the processing world this means multicore, and eventually many-core. Although we don’t have a stable lexicon yet, multicore is typically used to refer to chips that contain a few multiples of more powerful legacy cores (Intel’s traditional Xeon, for example). Alternatively, many-core refers to a chip containing a large number of simpler processing cores. One many-core pioneer illustrates the idea by showing a swarm of army ants successfully attacking a server. Swarming a chicken is far more likely, but the contrived illustration reminds us that evolution doesn’t always lead to bigger animals. Many-core’s attraction is that it results in a larger percentage of transistors going into computational units. Thus, for any fixed die size, it boasts higher peak performance. Many-core does this extra work without burning additional power. After all, it is just using the same number of transistors more effectively. This approach can be far more efficient and be much more scalable then traditional methodologies, but only if used appropriately. Trying to code many-core processors as if they were legacy single threaded en-



gines will lead to extremely unpleasant parallel processing challenges, and ultimately to failure. New coding approaches are called for. But the problem is NOT manycore—after all, many-core only exists because it is the solution—the problem is a lack of knowledge and support for manycore. New strategies are needed to deal with this reality—new processor architectures along with new approaches to coding them. To uncover the appropriate strategy for a given many-core implementation, there must first be an understanding of the problem. Recalling that the lexicon is still undefined and in flux, applications can map to many-core in three basic ways—data parallel, task parallel and parallel processing. Which type of parallelism is appropriate will drive the strategy and selection of both processors and the programming model.

Data Parallel and Task Parallel Processing

Data parallel processing describes applications that run the same, or similar, processes many times on different data sets. This may be as simple as an application or algorithms with >90% runtime in loops... where (hopefully) each iteration of the loop is independent. Provided the parallelism is data independent (i.e., there are no “IF” statements) then every data element can be processed in the same way, and a many-core SIMD model becomes an attractive strategy. SIMD means it executes a single-instruction on multiple data simultaneously. In the “old days,” these were often called vector, or array processors. To add two vectors of

N values, each value can be added together in a sequential manner or, using SIMD, all N values can be added to each other simultaneously if you have specialized hardware to support that; many-core SIMD precursors included Motorola/Freescale’s Altivec and Intel’s MMX & SSE, which do just that. These concepts have been applied more generally by various vendors including MathStar and Clearspeed, both of which may have been ahead of their time and failed to find commercial success. The most successful implementation of many-core SIMD for data parallel applications has clearly been GPUs. Obviously, these processors were designed to parallelize graphics operations. After Nvidia released CUDA in 2007, however, these GPUs became usable for general purpose acceleration (GPGPU). For algorithms with highly structured data parallelisms that can be independently processed with no need for conditional instructions, a GPU can tremendously outperform a single or multicore CPU. As is typical, the success of GPGPU has attracted competitors. The primary many-core competition is Intel’s emerging Xeon Phi family with code names like Knight’s Ferry and Knight’s Corner. Intel’s early Phi offerings leveraged old Pentium cores boosted with a wide SIMD unit. Intel says later Phi chips will actually use Atom cores. Data parallel applications with data dependencies (i.e., with “IF” statements), however, are ill-suited to implementation on GPUs, or any other SIMD engine for that matter. While every data stream can be processed by the same algorithm, each stream needs to be processed indepen-

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technology connected

External I/O Link Port North eCore





External I/O Link Port West


Register File (64)

Segmented Memory

Network Interface & DMA


eCore 1.0



eCore 1.1

eCore 2.0











eCore 2.2

eCore 3.1


External I/O Link Port East




eCore 3.2


External I/O Link Port South Figure 1 Anemone many-core processor block diagram featuring Epiphany eCores.

dently. This requirement dictates a MIMD model, meaning a many-core processor that can independently execute multiple instructions on multiple data. This approach is far more flexible than SIMD, and supports non-structured data and conditional, or data-dependent algorithms. Where SIMD can be thought of as a special case, the MIMD model is a more general-purpose implementation of the many-core concept. A good example of a MIMD many-core processor is BittWare’s Anemone. Implementing the Epiphany many-core architecture from Adapteva, Anemone hosts 16-64 cores that are connected via a high-throughput mesh network, as shown in Figure 1. Since each core is independent it is MIMD, and since it uses floating-point cores that are C-programmable, it is easy to code. For data parallel MIMD applications, the independent cores can operate concurrently on separate channels or data sets. Lots of applications can exploit a massive number of concurrent lightweight cores. Packet processing is an obvious example. Lots of cores are a fine match to a network with lots of packets. The same analogy



applies to serving web pages or anything else optimized around channels, capacity, or throughput. Concurrent programming of many-core architectures can be quite straightforward, with independent implementations of a single program—provided that program “fits” into a single core. If the program doesn’t fit into a single core, then it must be broken down in to sub-tasks for implementation in a task parallel strategy. Task parallel processing includes a wide range of applications that contain lots of independent functions that can be run either concurrently or in a pipeline; at some point the results may be consolidated, but for the most part the application can be run with task independence. These types of problems can be thought of as non-data parallel concurrent processing with each core running a different program, which would indicate using a MIMD strategy for implementation.

Parallel Processing

Many-core strategy becomes less clear for large, performance-limited applications. Speeding up such applications requires mak-

ing a single thread of execution run faster using parallel processing. This requires multiple cores to be used in parallel to divide and conquer a bigger problem than any one of them could handle alone (think of the army ants). This is where everyone starts to get nervous, because parallel programming is challenging. But remember—many-core is not the problem, it’s the solution. In contrast, a traditional processor runs single threads as fast as possible, reducing programming effort but increasing the complexity of the underlying hardware at the cost of lower efficiency and higher wattage. This is a great implementation strategy until the single thread isn’t fast enough, or when power and thermal constraints limit performance. Then you will need to implement parallel processing on multiple processors architecturally arranged to be single-threaded. The many-core parallel program may be “more” parallel, but it brings higher efficiency and lower wattage, and can be architecturally optimized for implementing the parallelisms so that it is actually easier to program.

technology connected While inevitable, parallel processing is still quite challenging. Even in the current crop of multicore servers, it is rarely implemented. However, with proper architecture of hardware and software it can be made much less daunting. Ironically, one of the ways to reduce the challenge of parallel programming is to simplify the cores and processor memory structures, control and I/O. Legacy processors have added all sorts of “bells & whistles” to automatically manage these things for the programmer, and for single-threaded execution these abstractions can be of great benefit. When programming many-cores in parallel, however, these abstractions can cause great difficulties with coordination and synchronization. It’s nearly impossible to understand and manage interdependencies between cores when the programmer can’t actually manage the core’s operation. One example of how reduced abstractions can simplify parallel many-core implementations is caching. For legacy processing implementations, caches can improve performance by intelligently predicting and managing memory access and moving data from bulk memory into local cache. However, Wikipedia defines the “many-core” as starting at the core count at which “traditional” threaded programming techniques break down, and this is a good example of this; academics have demonstrated that cached, shared memory does not scale well. Another example of architectural optimization is I/O. Since the cores are small and efficient, they aren’t well suited to multitasking. Serving I/O could be done by dedicating some number of cores, but that reduces the number of processing cores and can further complicate the parallel programming. Better to have the I/O outsourced to a separate unit and only task the many-cores with processing and inter-core communications. The Epiphany many-core architecture used by Anemone features simple, singlethreaded cores with distributed shared memory. There is a single global address map, but the actual memory resides within a specific core. It is not a cache but local SRAM that can be globally addressed. Thus threaded, shared-memory programs still run. However, the chip does not try to perform data movement speculatively— i.e., there are no caches. Instead, program-


Anemone Many-core

Anemone Many-core

Anemone Many-core

Anemone Many-core


GigE, PCIe,...


Ext. Mem Figure 2 Anemone many-core processor tightly coupled with FPGA to offload I/O, host interfacing and external memory control.

mers must manually manage the memory hierarchy with the tools provided for doing so. Virtually any C code will run unmodified at modest speeds and the code can then be modified to DMA both working data and key loops into the appropriate cores. Bulk memory and I/O are both handled by extending the global memory map off chip via the link ports. Multiple Anemones can be gluelessly connected to expand the many-core grid, or an FPGA can be attached for off-loading the service of bulk memory and I/O. As an additional benefit, the tightly coupled FPGA can now be used to provide additional processing and implementation of special functions, as shown in Figure 2. Because Anemone uses an architecture specifically designed for many-core, it enjoys the benefits in efficiency that this technology promises. Each floating point core delivers 2 floating point operations per cycle, or 1.5 GFLOPS at 750 MHz. Thus the AN104, with 16 cores, achieves 24 GFLOPS while only consuming 1W of core power. The next generation Anemone, in development now, will have up to 64

cores with double-precision and will deliver 96 GFLOPS in only 2W of core power. There is clearly no one-size-fits-all strategy to many-core. Whether an application is data parallel, task parallel, or requires parallel processing will have a strong impact on the selection of a processor. It is likely that legacy code is not written in a style suitable for any parallelism, so job one is to decide what the application classification is. Once that is done, processors can be evaluated and selected, then, and only then, the team can start to apply the appropriate many-core programming model to eventually rewrite the code into a suitable form. Clearly, none of this is easy—but remember, many-core is the solution, not the problem. BittWare Concord, NH. (603) 226-0404. []. Adapteva Lexington, MA. (781) 328-0513. []. RTC MAGAZINE OCTOBER 2012


ploration your goal k directly age, the source. ology, d products

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systems I2C in Small Systems

The Old-Timer in the Background – I2C Bus as a Cost Cutter on Small Form Factors Surely it is a contradiction to incorporate the latest processor technology alongside a vintage I2C bus on a modern computer module. Congatec disagrees. I2C is a classic, incredibly simple 2-wire bus architecture that has proven its value since the early 1980s. by Ross Watanabe, congatec


²C is capable of assigning up to 1136 which Intel defined in 1995. The Display addresses configured as master or Data Channel interface (DDC), developed slave. While it is not the be all and end by the Video Electronics Standards Asall in communications, it interfaces pro- sociation (VESA), is effectively also an prietary functional units on the baseboard I²C. Modules from congatec support I²C, with the computer module at minimal SMB and DDC. It is possible to mix I²C cost. Is it really that simple? Yes. How- and SMB in a design—if you know what to look out for. ever, a few things need to be considered. The first pitfall lurks in the choice of Philips developed the I²C bus in the operating mode. The I²C bus is a masterearly 1980s for control tasks in televisions. slave bus with single or multi-mastering. The Inter-Integrated Circuit (I²C) bus was nies providing solutions now Single-master operation is the simplest used to parameterize functional units, ion into products, technologies and companies. Whether your goal is to research the latest method for implementing the I²C bus. But program E²PROMs and operate switches. ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you beware: ignoring arbitration and clock The bus quickly found friends. Chipmakyou require for whatever type of technology, stretching can easily lead to communicaSiemens Infineon), Motorola and productsers you are searching (now for. (now Freescale), NEC, STM and others tion errors. Processor boards need to proimplemented I²Cs in their semiconductor vide an on-bus master that transmits up chips. The first specification was released to 400 Kbit/s. All is fine as long as fast in 1992 and has been kept up-to-date slaves do their duty on the baseboard. ever since. The bus became faster and the However, later baseboard versions might number of possible functions increased to be equipped with master functions or in1136 thanks to additional 10-bit address- clude slow slaves. Full design freedom is ing. The I²C principle works today as it therefore only guaranteed with the impledid on day one and is also a cornerstone mentation of multi-master operation. Beof the system management bus (SMB), cause the I²C bus is electrically built like a wired-AND, it is hot pluggable. Missing or extra nodes on the bus do not affect the Get Connected logical communication. This saves money with companies mentioned in this article. during device development because

End of Article



Get Connected with companies mentioned in this article.

signs can be reduced to assembly variants. The master always determines the bus clock rate. The specification defines four maximum clock rates: 100 Kbit/s for Standard mode, 400 Kbit/s for Fast mode, 1 Mbit/s for Fast-Plus mode and 3.4 Mbit/s for High-Speed mode. This is where the second pitfall lies in wait. HighSpeed mode has lower power and voltage requirements while all other modes are compatible. High-speed segments need to be separated from slower bus parts with switches. To ensure smooth interplay between fast master and slow slave, the slave can slow down the master via clock stretching—provided the implementation supports it. During clock stretching the slave sets the clock rate on low until it is ready for further transmission. Flexible clock rates are a distinct advantage: Slow and fast nodes communicate with each other, and functions can be selected from the entire component range regardless of clock rates. The wide choice also has a positive influence on design costs. Clock stretching, however, can be a lethal trap if a slave takes a long rest by setting the clock rate continuously on low, thereby effectively paralyzing the bus. To

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prevent such a blockade, a timeout needs to be defined in the error handling. Speed is not one of the I²C’s strengths because the bus is error prone to fast signals. For this reason, congatec processor modules use the more moderate Fast mode with up to 400 Kbit/s. The I²C shows off its advantages best in elementary tasks. Two simple lines, up to 1136 addresses and hot-pluggability translate into space-saving designs, simple wiring, and a lot of flexibility for little money—an energetic step in cost-cutting measures. I²C works its magic in the background. It is used in smart cards as well as battery management systems. congatec modules, for instance, support a smart battery manager via the I²C bus. Typical tasks performed by the two-wire bus include setting parameters, identification of hardware components and transmission of status updates. Intelligent I²C switches eliminate the need to use jumpers. As a consequence, the error rate due to incorrect jumper combinations decreases as developers can easily configure via the software interface. The jumperless design is also more vibration resistant. Fewer errors are an active contribution to lowering total cost of ownership. Chances of encountering an I²C are high wherever realtime clocks need setting, memory is waiting for commands, sensors transmit status messages, switches are turned on and off, fans are spinning faster, speakers are getting louder or quieter and brightness and contrast levels of monitors need adjusting. While the bus used may be called a DDC or SMB, it is effectively an I²C.

Know Your Limits

Experience has shown that 30 to 50 cm is a manageable distance for I²Cs without additional drivers. Their use is therefore typically limited to the baseboard and plug-in module. A capacitive bus load of 400 pF is a further limitation. This equals about 20 to 30 nodes on the bus. So what is the use of 1136 addresses


SDA (Data) SCL (Clock) Master I

Master II

Master III




Figure 1 Electric model of I2C bus.

Application cgos.lib cgos.dll/.so

congatec CPU BIOS with CGEB extension

Application cgos.lib

BIOS extensions (e.g. Eth. boot ROM)



cgos.sys/.ko CGEB extension CGEB extension


Module BIOS (AMI/Insyde)


Hardware b

Figure 2 CGOS API, driver initialization (a) and CGOS API, driver up & running (b).

if there are only 30 nodes in the segment? There are components with addresses fixed by the manufacturer. Other circuits may have 2 or 3 freely programmable address bits while 4 or 5 bits are set. There are also components that are freely programmable. This means that there isn’t a connected node behind each available address. It is possible to divide the I²C into segments with extension modules thereby connecting more participants (Table 1).

This way the capacitive limits can be overcome while longer distances can be realized with additional drivers. I²C does not have strict baud rates like RS-232. It is a true multi-master bus with collision handling, access arbitration, flexible clock rate and synchronous, bit-serial transmission for simple communication tasks. Despite all of this, the I²C is not a field bus replacement. As shown in Table 1, the first address byte contains seven address bits RTC MAGAZINE OCTOBER 2012


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PCIe x1

Intel NM10 Express Chipset CG82NM10 PCH

Watchdog congatec Board Controller STM32F100R8




PCIe x1 If No USB 3.0

SM Bus

PCIe x1

Gbit Ethernet

PCIe x1

PCIe x1

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PCIe GBE RTL8.11 1e

PCIe x1

PCIe Switch


Hardware Monitoring

PCIe x1


LPC BIOS (Flash)

8x USB 2.0





Fan Control


Intel Atom Processor N2800 N2600 D2550

DMI x2 (N2000) x4 (D2000)


2x DP or HDMI

2x USB 3.0


DDR3-3.0 DIMM max. 4 GByte Memory Types (up to 1066MTs)

C-D Figure 3 The ARM core uses I²C even when conga-TCA is in standby mode

and one bit to distinguish between read and write. This corresponds to 128 addresses. Of these, 16 addresses are reserved, which leaves 112 free addresses. With additional 10-bit addressing, a further 1024 addresses become available. Since both types of addressing are valid simultaneously, the number of possible addresses adds up to 1136 (112 +1024 = 1136).

How Much of the I²C Is in the SMB?

Both the I²C and the SMB work with clock and data lines, and their basic electrical design and transmission schemes are identical (Figure 1). The logic 1 ground state of both buses is achieved with pull-up resistors. If the line is pulled to ground, this indicates a logical 0. Both buses are connected



via a resistor and supplied with reference voltage. This is where the similarities end. SMB participants can sink a maximum of 350 uA, whereas I²C participants must be able to accommodate up to 3 mA. The bus termination resistors are therefore different, and the influence of the bus capacitance on the signal quality is greater for SMBs. The SMB bus can disable termination altogether during idle mode. Mixed bus systems must take this into account. Otherwise, when the termination voltage is switched back on this could be misinterpreted as start or stop. Also, the clock rate of the SMB is limited to a range between 10 kHz and 100 kHz. I²C, by comparison, works from nearly 0 bit/s to 3.4 Mbit/s in High-Speed mode. For a general call the I²C master sets address 0 on the bus. This equals a

call to all slaves on the I²C bus. SMB works with an optional additional signal, the alert. The slave sends an alert, which the bus master interprets as an interrupt. The bus master responds with a confirmation, whereupon each slave sends its address to the master. The arbitration mechanism selects the slave, which then talks to the master. SMB recognizes when nodes block the bus. After a timeout of 35 µs all slaves reset their internal state machines and release the bus. I²C does not have a time out. An I²C slave is able to pull the clock line to low for an indefinite length of time. This is used during clock stretching when the I²C slave tells the master that it should wait a little longer before the next transmission. In the worst case scenario, the slave thereby blocks the bus for all.

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The Good News

Customers doing hardware design of baseboards benefit because congatec processor boards use the bus for a variety of functions. The feature connector in the starter kit includes the I²C bus signals. Developers can experiment with the bus directly on their test boards. To enable integration into operating systems congatec has developed congatec Operating System Application Program Interface (CGOS). The software interface CGOS provides access to hardware-dependent features yet is independent of the actual hardware. Figure 2 shows the principle implementation of the CGOS/CGEB interface. The CGEB (congatec embedded BIOS) code is located in the module’s system BIOS. It is 32-bit native x86 object code and executable in any kind of 32-bit protected mode environment. During driver initialization (Figure 2a), the CGEB extension will be copied to the driver’s context and becomes part of the driver (Figure 2b). This mechanism provides independence from the hardware because all low level hardware dependencies are already re-


R/W bit




General call address



Start byte



CBUS address



Reserved for different bus format



Reserved for future extensions



Reserved for future extensions



Reserved for future extensions



10-bit addressing

Address part 1

Read/Write bit


Address part 2




1. Confirmation


2. Confirmation

TABLE 1 How to achieve 1136 addresses with additional 10-bit addressing.

solved from the CGEB extension code. CGOS is the link between BIOS and operating system. It contains a specialized API for I²C functions. I²C bus type selects between SMB, DDC or Primary (true I²C). The CGOS library gives the user hardware-independent bus access. The CGOS API specifies which data is

sent; the actual signal handling is the job of the hardware. The interface works on any version of Win32 as well as the following other operating systems: • Linux (2.4.x and 2.6.x kernel) • QNX 6.x • Wind River VxWorks • On Time RTOS-32

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A concrete application example is a smart battery manager that is supported among others by the new COM Express board conga-TCA. I²C provides the user with information on AC or battery operation and battery or charging status. For the operating system to receive this data, the congatec Advanced Configuration and Power Management Interface (ACPI) must be installed at the BIOS level. The

operating system itself does not recognize the I²C bus. ACPI is a large table in the BIOS that describes access methods. When the operating system asks for the battery status, the ACPI driver calls the appropriate access method. Whether the information is transmitted via a proprietary network or via the I²C ultimately doesn’t make any difference to the operating system.

Bridge the gap between ARM and x86 with Qseven Computer-on-Modules One carrierboard can be equipped with Freescale® ARM, Intel® Atom™ or AMD® G-Series processor-based Qseven Computer-On-modules. conga-QMX6

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The SMBus is used on the new conga-TCA for hardware monitoring and fan control. Conga-TCA is the entry module into the COM Express Type 6 world. On the 95 x 95 mm small board, the workload is shared between an Intel Atom dual-core processor and a STM32F100R8 with ARM 32-bit CortexM3 from ST Microelectronics. While the computing power and powerful graphics chipset of the Intel Atom dual core shines in medical, automation, kiosk or digital signage applications, the STM32F100R8 board controller handles power consumption and battery management amongst other tasks. This division of labor also benefits the I²C. The STM32F100R8 with the notoriously energy-efficient ARM core uses I²C even when conga-TCA is in standby mode. The STM32F100R8 has two I²C interfaces. One of them is freely available to the user as I²C; the other is configured as SMB and performs boardspecific tasks. SMB is also available for user applications (Figure 3). I²C is a modern bus whose basic principle has been incorporated into SMB or DDC. The I²C bus can be operated from within the operating system or application. Around 3000 different functional blocks are available on the market. I²C is the epitome of easy communication at the board level. It remains a contemporary bus despite its age, because it has stayed technically and economically ahead in its field. congatec San Diego, CA. (858) 457-2600. [].





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technology deployed Pre-Integrated Systems

Hitting the Ground Running: PreIntegration Speeds System Development If you look for an industry-ready box PC these days, many choices abound. There’s a product for every niche, it seems. The problem is: there seem to be more and more niches. by Susanne Bornschlegl, MEN Micro


n transportation, technical requirements are growing in the areas of controls and graphics, for instance—places not typically associated with embedded computing requirements. What could be more natural than using a modular system concept to meet different computing needs, with much of the system architecture already predefined and tested? The box computer concept is a perfect example of Aristotle’s famous quote that the whole is greater than the sum of its parts. The internal boards, components and software are not viewed as individual items that will provide a function for the system, but rather as one unified structure that can be quickly, easily and efficiently implemented into a larger computing system. From a design perspective, this eliminates a great deal of frustration and time to get a complex architecture up and running. In recent years, embedded electronics have entered the stage of mobile applications. Especially in public transport, requirements keep rising. More and larger screens keep passengers informed and make electronics more in need of graphics than ever. In the background, a computer is typically connected to the actual vehicle functions and can fulfill additional tasks. Whether it be the control end accessed



by the operator, or the visual end facing the customer or user, these systems need to work reliably. Having a full unit not only built to an application’s specific requirements, but also knowing that this unit will perform as needed

pretty much out of the box, gives many design engineers comfort. This is, no doubt, contributing to the growing concepts and usage of pre-integrated systems (Figure 1). One factor driving the ability to pack more functions into one complete system is the continuing fusion of processing chips. One example is AMD’s Accelerated Processing Units (APUs). In addition to the actual x86 CPU, the chip also includes a GPU (Graphics Processing Unit) from AMD’s Radeon range with the performance level of a dedicated graphics card. This has allowed AMD to reduce the 3-chip solution consisting of a processor, Northbridge and Southbridge, which was common up to now, to a small-footprint 2-chip solution. This example of reducing a component’s footprint has enabled more electronics to be contained within one system, contributing to advancements in the preintegrated system approach, especially for embedded applications that absolutely require small form factors. More computing means more heat, typically, so chip manufacturers are also focusing on power reduction. The AMD 1.0 GHz dual-core G-T40R

Figure 1 Pre-integrated systems feature modular electronics on the inside, in a readyto-go configuration.

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The products below are a sampling of RTD’s PCIe/104 and PCI/104-Express offering. All of RTD’s board-level solutions are available in ruggedized packaging with advanced heat sinking, internal raceways, and a variety of I/O configurations. Visit to see our complete product listing.

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Figure 2 In addition to internal thermal management techniques, the flat sides of the enclosure can be utilized as heat sinks.

with integrated Radeon HD 6250 graphics, for example, has a maximum TDP (Thermal Design Power) of just 5.5 watts.

The Necessity of Continued Operation

Because the components and functionality of these box computers are contained within a sealed housing, the unit needs to perform reliably in not only rugged, and typically mobile, environments, but also over long periods of time. These pre-integrated systems are designed to be put in place and operate effectively. The time and effort spent getting the system up and run-


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ning is of no use if it constantly needs maintenance. That said, there are varying conditions these units need to accommodate, as can be seen in the requirements of a mass transit bus manufacturer, for example. These types of companies need to take a more global view than ones building systems for a factory—where the environment will remain relatively the same once identified, without the variable of weather, dust or corrosive elements. The demand for computers on board a bus in the midday heat of Dubai is vastly different than those required on a cool, rainy day in Britain.

Buses in a desert country are air-conditioned, of course, but the hot air flowing in from the outside at every stop is a strain on their internal electronics, especially if a device is installed directly above the driver’s seat. In this case, the computer can take over a number of jobs, such as registering a stop request or coordinating the display of stops according to the vehicle’s position. In addition, the device can reliably transmit passenger information or commercials to several independent displays—even in full HD resolution. It is the reduced complexity on the designer’s part to get the system implemented as well as the overall, built-in reliability of a pre-integrated system that enables this flexible operation.

Integration from the Board to the Box

Heat is forever a main cause of system failure. In many pre-integrated computer configurations, the actual design of the box itself is part of the overall thermal management. Fans, which consume additional power and are unreliable, must be serviced in regular intervals, so for a system designed to be put in place and run, there’s

5/4/12 1:53:35 PM

Technology deployed not a strong case for including them. More sophisticated cooling concepts are employed in pre-integrated systems, especially with the amount of electronics typically housed within. This starts with the design of the main board—which can employ thermally conductive materials selected to spread the heat away from the critical spots—down to the walls of the enclosure itself. With this level of integration implemented early on in the design process, particularly hot elements, like the APU, can be positioned to have a direct connection to the housing using thermal grease. Cooling fins on the housing itself can work as an additional heat sink for the entire system, enabling standard operation up to +70°C, or even up to +85°C with a small extension to the sides, which even exceeds the requirements of EN 50155 temperature class Tx. Some pre-integrated systems have been constructed in a way that enables the housing to handle up to 25 watts of power dissipation without a fan (Figure 2).

first customized versions has about double the width of the standard model to allow for a multitude of additional interfaces directly at the front panel. With the numerous options and levels of configuration, you can reduce costs by configuring the box PC for exactly the job that it is to do. These can be used to control different vehicle functions, and special enclosure models can meet more specific environmental demands, such as protection from splashing water (IP67). When imple-

mented a in mass transit application, these box and display computers can utilize railway-compliant networks and phone connections for wireless communication—in addition to the usual computer interfaces— to transfer service data to the control center or to receive traffic information. MEN Micro Ambler, PA. (215) 542-9575. [].

Pre-Integration Increases System Flexibility

With the necessary precision of these pre-integrated systems, it might seem that a drawback of this design would be inflexibility in system assembly, but the actual outcome is design flexibility in terms of I/O, data storage and even the enclosure itself. I/O can include DisplayPorts, Gigabit Ethernet ports, HD audio and USB 2.0 or even accommodations for PCI Express Mini Cards, which opens up access to wireless communication protocols such as WLAN, UMTS or GSM. If an FPGA is included in the design, UARTs, IBIS and CAN bus are other options that can be easily implemented within the system. A computer can even be configured to position itself via GPS or function as a Wi-Fi hot spot. Because of the inherent shock and vibration of many mobile environments, movable parts tend to be notable points of system failure. Depending on the actual environment and needed configurations, storage options from a typical SATA hard disk to the more rugged mSATA slot or an SD card can be used for mass storage requirements. Even the shape of the enclosure can be varied depending on the needs. One of the Untitled-6 1


10/2/12 11:42 AM RTC MAGAZINE OCTOBER 2012

JTAG Boundary Scan Tester/Programmer Relieves Users of Detailed Setup A Universal JTAG Boundary Scan Tester and Programmer can be utilized as a production run time and application development system for performing circuit card assembly (CCA) structural integrity tests or CCA programming. The available assets packaged within a small footprint make the JTS1000 from JTAG Technologies suitable for both Production and Field Testing. The JTS1000 utilizes Astronics DME’s Test EZ Software Suite for automated testing and program development. Other standard features include: • Stand-alone bench-top LXI-based system • JTAG TAPS with up to 256 programmable digital I/O channels • 6.5 digit DMM • Power and multiplexed switching • 16-port Ethernet switch • Up to 4 programmable DC power supplies • Plus various software JTAG Technologies recently introduced high-level JTAG access routines, which can be linked into the Python freeware open-source language. Called JTAG Functional Test (JFT) routines, they work at two levels (or perspectives), namely: boundary-scan pin-level and “cluster” pin-level. In the boundary-scan pin-level scenario users can set up tests with minimal knowledge of the interconnections and without reference to a design netlist. Individual pins can be driven using DriveHigh, DriveLow and HighZ, and individual pins can be read using TestHigh and TestLow. Also, groups of pins can be defined by DeclareGroup. For example, the pins of a JTAG-compliant device that connect to a (nonJTAG-compliant) DAC might be grouped and named “DAC-input.” The variable DAC-input can then be controlled using a DriveVar command. Similarly, the output of an ADC could be suitably named and read by a TestVar routine. Using JFT at this level allows design engineers to undertake debug sessions without the need to create specific test firmware or FPGA test configurations. Equally, repair or service personnel can easily create test scripts to cover well-known fault signatures. The cluster pin-level perspective takes testing to the next level/stage by allowing the user to specify pin-level and variable-level drives—testing from the device under test’s (DUT’s) point of view. JTAG Technologies, Mission Viejo, CA. (949) 454-9040. [].

Microcontrollers Deliver Highly Accurate Temperature Sensing A family of high-performance 8-bit microcontrollers (MCUs) features the latest mixed-signal breakthrough, an integrated temperature sensor with best-in-class accuracy over an extended temperature range and without the need for calibration. Offering a unique mix of integrated high-performance analog peripherals and a very fast 8051 CPU (up to 50 MIPS) in a compact package, the new C8051F39x/7x MCU family from Silicon Laboratories provides an attractive solution for optical transceiver modules, sensor interfaces and brushless dc motor applications for fans, dryers, vacuum cleaners and remote control toy vehicles. Many consumer and industrial applications require highly accurate temperature sensors to adjust for behavior shifts over temperature for onboard components such as sensors, lasers or power sources. The C8051F39x/7x MCUs’ on-chip temperature sensor provides ±2°C accuracy through an extended temperature range up to 105°C without the need for calibration. The temperature sensor reduces manufacturing cost by eliminating the need for the factory calibration step required by other MCUs. C8051F39x/7x MCUs are more than 30 percent smaller than other solutions, and the high level of integration eliminates the need for external components such as a temperature sensor, a crystal, a differential analog-to-digital converter (ADC), a voltage reference and two digital-to-analog converters (DACs), further reducing bill-of-materials (BOM) cost and PCB footprint. These on-chip analog peripherals enable developers to minimize discrete components and reduce the BOM cost by more than $0.30 (USD). In addition, the family’s crossbar technology gives developers the flexibility to assign peripherals to specific pin locations, thereby easing system layout and eliminating pin conflicts. Finer resolution pulse-width modulation (PWM) offers the ability to execute more complex algorithms, enabling a greater range of motor speeds and higher efficiency in motor control applications. The C8051F39x/7x MCUs are also designed to consume 160 µA/MHz in active mode, enabling up to an 80 percent power savings compared to competing devices. The C8051F37x devices are the first Silicon Labs MCUs with 512B of EEPROM, supporting ten times more write/erase cycles (1M vs. 100k typical) and faster programming times (3.5 ms vs. 112 ms) compared to standard flash implementations. These increased write/erase cycles are useful for applications such as wireless sensor nodes and data loggers that must constantly write to memory. The faster programming times often are needed for applications such as industrial controls and optical modules that require tight calibration loops. Silicon Labs’ development kits for the C8051F39x/7x MCU family provide everything embedded developers need to evaluate hardware and develop code including C8051F390 or C8051F370 target boards, USB debug adaptor/programmer, power supply, cables, quick-start guide and complimentary downloadable software tools. C8051F39x/37x

Analog Peripherals

10-bit 500 ksps ADC

±2°C Precision Temp Sensor

F390/2/4/6/8 and F370/4 Only

49 MHz Precision Internal Oscillator

Digital I/O

10-bit Current 10-bit DAC Current DAC


+ -

Voltage Comparator

UART SMBus0 SMBus1 SPI PCA0 PCA1 PCA2 Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5

80 KHz Low Frequency Internal Oscillator

Port 0 Port 1 P 2.0





products &

P 2.1– P 2.4*

*P 2.1–2.4 QFN24 Only

512 B EEPROM (F37x Only)

High-Speed Controller Core

16/8 kB ISP Flash

8051 CPU (50 MIPS)

Flexible Interrupts

Debug Circuitry

1024 B SRAM



Silicon Laboratories, Austin, TX. (512) 416-8500. [].




8k Color CMOS Line Scan Camera for Inspection Applications A new 8k Color CMOS line scan camera with 8k resolution and a 7 µm x 7 µm pixel size is optimized for optical design. The Piranha4 series from Teledyne Dalsa combines advancements in Teledyne Dalsa’s CMOS image sensor technology with outstanding signal-to-noise ratio for high speed inspection. The color version of this camera is suitable for automatic optical inspection of flat panel displays, electronics, printed material, solar cells, film and large format web inspection. The Piranha4 Color is based on Teledyne Dalsa’s unique CMOS bilinear line scan technology with on-chip CDS and on-chip ADC. It offers low read noise and high full well capacity, resulting in a better dynamic range for demanding applications. Programmability features of the P4 8k Color camera include exposure control, gain setting, flat field correction, white balance and color correction. Special algorithms allow defocusing capability in flat field correction and white balancing without the need to adjust the optical lens. In addition, an advanced GenICam-compliant interface makes the camera easier to set up, control and integrate. The Piranha4 line scan series includes 1k, 2k, 4k and 8k resolutions with various pixel sizes based on CMOS dual line scan technology. Teledyne DALSA, Waterloo, Ont. (514) 333-1301. [].

Tool Verifies Test Coverage Completeness

USB Portfolio with Fifteen New 8-bit MCUs

A stand-alone code coverage tool verifies that the source code of an application has been fully structurally tested. LDRAcover from LDRA responds to the needs of companies that wish to improve overall quality of code by ensuring complete testing, as well as those companies that must meet the most stringent levels of code verification in markets such as avionics, defense, industrial controls, automotive and medical devices. Because software represents such a large portion of today’s safetyand security-critical systems, many applications now contain hundreds of thousands of lines of code. Without a tool that confirms all possible lines, decisions and test paths have been fully executed during testing, software providers cannot know that an untested component will not inadvertently be called once a system is in the field, leading to the potential for critical system failure or even loss of life. Code coverage encompasses several levels of precision that range from simply showing whether a line of source code has been executed at least once by the set of test cases to the stringent requirements of modified condition/decision coverage (MC/DC), where a component is placed under exhaustive testing. MC/DC analysis is reserved for the most stringent levels of testing in DO-178B/C and ISO 26262, where failure of the software can result in loss of life. LDRAcover analysis provides multiple levels of coverage, allowing the developer to select a range of options including: • Statement—identifies missing test cases, dead code and lines of source code executed • Branch/decision—checks control-flow branches and loops • Procedure/Function Call—verifies that procedure/function calls and call returns executed • Branch Condition—checks that Boolean operands in a condition executed both TRUE and FALSE • Branch Condition Combination—checks that all unique combinations of Boolean condition operands executed both TRUE and FALSE • Modified Condition/Decision Coverage (MC/DC)—confirms that every point of entry and exit was invoked at least once, every condition in a decision has been taken on all possible outcomes at least once, and each condition has been shown to independently affect the overall decision outcome.

A line of certified full-speed USB 2.0 Device PIC microcontrollers features three new enhanced midrange 8-bit families comprised of 15 scalable MCUs ranging from 14 to 100 pins with up to 128 Kbytes of Flash. All these devices from Microchip feature internal clock sources with the 0.25% clock accuracy necessary for USB communication, which saves up to $0.15 by eliminating the need for an external crystal. Additionally, all three families are eXtreme Low Power compliant, with power consumption down to 35 µA/MHz Active and 20 nA in Sleep mode. The 14- and 20-pin PIC16F145X MCUs are Microchip’s lowest-cost and smallest form factor USB MCUs to date. Available in packages as small as 4x4 mm and featuring a wide array of integrated peripherals, the three-member family enables embedded applications that require USB connectivity and capacitive touch sensing, such as pulse oxymeters, PC accessories and security dongles. The PIC18F2X/4XK50 devices, available in 28- and 40/44-pins, offer a cost-effective, pin-compatible migration option for customers utilizing legacy PIC18 USB MCUs. The three family members feature 1.8-5V operation, and integrate a “Charge Time Measurement Unit” for higher performance cap-touch sensing as well as measurement in applications such as audio docks and data loggers. The full-featured PIC18F97J94 family is Microchip’s first to offer integrated LCD control, RTCC with Vbat, and USB on a single 8-bit PIC microcontroller. Available in 64, 80 and 100 pins, the nine-member family offers a 60x8 LCD controller (for a total of 480 segments), which eliminates the need for an external controller in applications with large segmented displays. It also integrates a real-time clock/calendar with battery back-up for end products such as home-automation/security panels, handheld scanners and single-phase energy meters. To help speed development times, the downloadable and opensource USB Framework within the free Microchip Library of Applications (MLA) includes USB drivers for many common USB classes, including HID, CDC, Mass Storage, Win-USB and Audio-MIDI. These drivers can be used with all 15 of the new PIC MCUs. In addition to providing free USB software drivers and stacks, Microchip hardware development tools are available for purchase. The Low Pin Count USB Development Kit (part # DM164127, $39.99) is available now for use with the PIC16F145X family.

LDRA, San Bruno, CA. (650) 583-8880. [].

Microchip Technology, Chandler, AZ. (480) 792-7200. []. RTC MAGAZINE OCTOBER 2012



AC/DC Power in 3 x 5 x 1.6” with up to 360 Watts A product family of high-density AC/DC power supplies offers up to 360W continuous operation. Its open frame version is in the industry standard 3 x 5 x 1.6” footprint with a fully enclosed version measuring 3.4 x 5.4 x 1.7”. The magnetics of the Cincon CMF361S series from PowerGate are tied to a baseplate underneath the PCB to provide heat-spreading and baseplate cooling while the optional U-Frame/ cover version provides additional cooling for increased output power. Open-Frame PCB Models offer 360 watts Output Power with 10 cfm airflow and a convection-cooled rating of 300W at 220 VAC / 240W at 110 VAC. The U-Frame/Cover models offer 360W convection-cooled operation at 220 VAC / 300W at 110 VAC. Detailed de-rating curves are available in the specification. The series consists of single +12 / +24 / +48V output models with 5 VSB @ 500 mA and 12V Fan Output @ 300 mA. All models feature 90-264 VAC Input Range with Active PFC, -20° to +70°C (open Frame) / -20° to +85°C (Covered) operating temperatures, Remote Sense and Remote Enable. Models are safety approved to UL/ EN60950-1 Standards and bear the CE Mark (LVD). Pricing is as low as $132 in 100 piece quantities for open frame models; $143 for covered models.

Point Tool Enforces Programming Rules A programming rule checker brings together a collection of rules from a broad spectrum of programming standards with the goal of improving software quality and consistency. Implemented as a stand-alone product, LDRArules from LDRA enables development teams to improve their software quality by selecting and adhering to relevant industry programming standards. Companies can easily configure LDRArules for a specific program-

PowerGate, Santa Clara, CA. (866) 588-1750. [].

ETX Module with Dual-Core Atom for Upgrade Path and Longer Life of ETX Systems Based on the latest dual-core 32nm process Intel Atom Processor and NM10 Express Chipset, a new ETX module from Adlink aims to further support its ETX customer base with continuing product development. The ETX-CV is targeted at replacing current entry-level and older high-performance ETX modules (up to Intel Core Duo Processor L2400). Power consumption ranges between 6 and 12 watts and is much lower than that of previous-generation products. The ETX-CV is positioned as an entry-level ETX module for generic systems but is also aimed at systems that require a full set of graphics features. The module comes with integrated support for high VGA up to 1920 x 1200 resolution (WUXGA), single/dual channel 18/24-bit LVDS and onboard DisplayPort connector. The ETX-CV conforms to the latest ETX 3.02 specification and provides two additional onboard SATA connectors while maintaining full backward compatibility with earlier ETX standards. Operating system support includes Windows XP, Windows XP Embedded, Windows 7, WinCE and Linux. Primary focus is for applications in medical diagnostics and imaging, gaming, industrial automation, test and measurement, point-of-sale (POS) and industrial control. The dual-core Atom Processor N2000 and D2000 Series on the ETX-CV replace the previous generation Atom processors N4xx/N5xx. Although much smaller in size, Atom processors share the same architecture as Intel Core2 Duo processors and additionally support Hyper Threading Technology, allowing more than one code thread to be executed at the same time on a single core. The ETX-CV’s thermal design and powerful CPU core allow it to provide the same or even better performance than earlier generation modules at more modest power consumption. The ETX-CV supports up to 4 Gbytes of DDR3 memory on a single SODIMM, incorporates an Intel-based 10/100BASE-T Ethernet port, and provides dual channel IDE, two channels SATA, four USB 2.0 ports, two serial ports, one parallel port shared with floppy, one PS/2 keyboard/mouse interface, and HD audio. The module fully supports PCI and legacy ISA based on high-speed PCI/ISA bridge and is equipped with an AMI Aptio BIOS supporting embedded features such as: Remote Console, CMOS backup for battery-less operation, CPU and System Monitoring, and Watchdog Timer. ADLINK, San Jose, CA. (408) 360-0200. [].



ming standard or choose to enforce in-house programming templates and improve their overall software development methodology. Because programming errors are responsible for more than 70% of software defects, LDRA has actively worked on a number of standards bodies and organizations to develop programming standards that achieve early error identification and correction. LDRA offers programming standard conformance for more than a dozen programming standards, including MISRA-C:1998, MISRA-C:2004, MISRA AC, MISRA C++:2008, CERT C, CERT J, CWE, HIS, JPL, JSF++ AV, High Integrity C++, SPARK Ada subset and the Ravenscar Profile. The programming standards provide programming rules across the primary languages used in embedded design: C, C++, Ada and Java. Developers can choose rules for a specific industry standard or they can select a combination of rules from a variety of standards, creating customized templates tailored for their company and projects. LDRArules documents which rules have been selected, ensuring complete transparency of what programming rules have been implemented. LDRA, San Bruno, CA. (650) 583-8880. [].


Step/Dir Control System Works with PCI and PCIe An FPGA-based 5-axis step/dir control system is designed for CNC, industrial automation retrofits and OEM systems. With the MESA 7I76 card set from Mesa Electronics, 5 axis of hardware step generators allow step rates up to 8 MHz, and step and direction outputs are differential for noise immunity. Analog spindle control and spindle encoder inputs (TTL or differential) are also provided. The PCI or PCIE host interface provides robust realtime access to the motion hardware. In addition to the motion related I/O, 32 digital inputs and 16 digital outputs are provided. These digital I/O points are isolated from the system ground and can use 5V to 32V I/O voltage. Inputs have a threshold of ½ the I/O voltage for high noise immunity. Outputs can supply 300 mA each and are short circuit protected. I/O can be expanded to more than 400 I/O points with real-time access or up to 12 motion axis. The 7I76 card set is fully supported by LinuxCNC. All FPGA firmware is open source and easily modified to support new functions or different mixes of functions. Quantity 100 pricing for the 7I76 set with PCI host adapter is $144 and for the 7I76 set with PCIe host adapter, $158. Mesa Electronics, Richmond, CA. (510) 223-9272. [].

96-line PCI Express SUMIT Digital I/O Module Offers High Density and High Performance A SUMIT-ISM-compatible 96-line digital I/O module is designed for high-speed interfacing. The PXM-UIO96-2 from WinSystems offers PCI Express expansion on a 90 x 96 mm PC/104-sized module enabled by the stackable high-speed SUMIT connector. One key feature of this card is its ability to monitor all 96 lines for both rising and falling digital edge transitions, latch them, and then interrupt the host processor notifying it that a change-of-input status has occurred. This is the most efficient way of sensing and signaling the CPU of real-time events without the burden of continuous polling of the digital I/O points. The PXM-UIO96-2 uses a Lattice Semiconductor ECP2M family FPGA with a superset of two WinSystems’ WS16C48 Universal I/O controller cores. It is wired to the PCIe x1 lane of the SUMITA connector and automatically selects the first available link. Each I/O line is programmable for input, output, or output with read-back operation. Transition polarity is programmable and enabled on a bit-by-bit basis. Each line’s transition is latched so that even short duration pulses will be recognized. Also, each output channel is latched and has an open collector driver (with a pull-up resistor) capable of sinking 12mA of current. This allows direct interface with optically isolated digital signal conditioning modules for high-density, real-world I/O support. The PXM-UIO96-2 supports Linux, Windows and other x86-compatible real-time operating systems. Free drivers are available from the WinSystems’ website. This board will operate over the industrial temperature range from -40°C to +85°C. It is RoHS compliant. The module includes the Stackable Unified Module Interconnect Technology (SUMIT) connector that was developed and standardized by the Small Form Factor Special Interest Group. SUMIT is an electromechanical connector specification that enables stacking of common serial and legacy chipset expansion buses on PC/104 and other form factor’s I/O modules for next-generation embedded systems products. Pricing starts at $195 in OEM quantities. WinSystems, Arlington, TX. (817) 274-7553. [].

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u-blox, Thalwil, Switzerland. +41 44 722 74 44. [].

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Software Tools for Complete Vibration Testing Solution A software suite provides tools to output stimuli with waveform generation for testing. The VIBpoint Framework application from Data Translation, combined with DT dynamic signal acquisition (DAQ) devices, provides a complete vibration testing solution. The software is navigated through a series of easy-touse configuration windows, allowing flexible selection of the desired acquisition, processing, plotting and display parameters. New waveform output features include continuous or burst DAC output of noise, swept sine and fixed frequency waveforms and the ability to synchronize output start/ stop with analog input, or start/stop manually. Additionally the user can specify waveform on/off time and ramp up/ramp down time and lock the total waveform duration to analysis frame time (triggered), or total acquisition time (free run). Fixed frequency options include output frequency value, sine, square, ramp or triangle wave and continuous, burst, or repeat burst output. The suite also offers swept sine options that include start/end output frequency values, single sweep or loop and linear or Log frequency change. Noise options include random, random normal, or pink noise in addition to continuous, burst, or repeat burst output. There is also the ability to select true random or pseudo random noise. Pricing starts at $1,495.

COM Express Development Platform A COM Express Development Platform enables early development and rapid prototyping for COM Express and XPand6000 Series-based systems from Extreme Engineering Solutions. The CX-DP includes all of the functionality of the XPand6000 Series with support for a COM Express module, a PMC or XMC, and an SSD, all conveniently housed in a desktop setup with standard commercial I/O connectors. With the CX-DP, the transition from development to the target XPand6000 Series system or custom COM Express carrier card is made easy. The CX-DP provides a single COM Express site with AB and CD connectors. For Freescale QorIQ-based development, the CX-DP supports Type 5FS and Type 10 COM

Data Translation, Marlboro, MA. (508) 481-3700. [].

COM Express Type 6 Module Boasts High-Performance Integrated Graphics A high-performance COM.0 R2.0 Type 6 module features an Intel Core i7/i5 processor and supports the latest digital graphics interfaces for future designs. With its high-level processing and graphics performance and long product life, the Express-HR from Adlink Technology is well suited for medical, gaming and military applications. The Express-HR’s Intel Core i7/i5 processor supports Intel Hyper-threading Technology (4 cores, 8 threads) and up to 16 Gbytes of DDR3 dual-channel memory at 1066/1333 MHz on dual stacked SODIMM sockets to provide excellent overall performance. Intel Flexible Display Interface and Direct Media Interface provide high-speed connectivity to the Mobile Intel QM67 Express chipset. Intel HD Graphics is integrated on the CPU, and a PCI Express x16 bus is available for discrete graphics expansion or general purpose PCIe (optionally configure as 2 x8 or 1 x8 + 2 x4). New with the Type 6 module are three Digital Display Interface (DDI) ports supporting HDMI, DVI and DisplayPort outputs, in addition to legacy VGA and dual-channel 18/24-bit LVDS displays. The Express-HR is specifically designed for customers with high-performance processing and graphics requirements who want to outsource the core logic of their systems and focus on their core competency for reduced development time. The Express-HR features Gigabit Ethernet, up to eight USB 2.0 ports, two SATA 6 Gbit/s ports and two SATA 3 Gbit/s ports (RAID 0/1/5/10) and support for SMBus and I2C. The module is equipped with SPI AMI EFI BIOS supporting remote console, CMOS backup, hardware monitor and watchdog timer. Adlink provides a wide range of tools to accompany the Express-HR, including the COM Express Type 6 Starter Kit that supports carrier board design and software verification simultaneously, the T6-DDI Video Adapter Card that provides easy access to the Express-HR’s DDI ports, the PCIe x16-to-two-x8 Adapter Card, and the LPC POST Debug Board. Adlink’s complete range of COM Express engineering test tools will expedite your application development. ADLINK Technology, San Jose, CA. (408) 360-0200. [].



Express modules; and for Intel CoreTM i7 processor-based development, the CX-DP supports Type 6 and Type 10 COM Express modules. It provides a single PMC/XMC site, along with a single PIM/XIM site for PMC/ XMC I/O, one RJ-45 Gigabit Ethernet connector, two USB 2.0 connectors, two DB-9 serial connectors, one mini DisplayPort connector, one eSATA connector, one PCIe Edge card slot, three internal SATA connectors, two internal USB 2.0 connectors, and a single COM Express I/O Module (CIM) site for access to I/O not available at the fixed connectors. Removing the ATX case cover provides access to internal fixed I/O and PIM I/O. An integrated fan located below the PMC/XMC site provides ample airflow for the most power-hungry modules. The CX-DP requires only +12V from the ATX power supply. It generates +5V, +3.3V and -12V supplies, avoiding voltage drops and power distribution problems commonly associated with using high-power cards and ATX supplies. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].


ATCA/AMC Management Controller Solutions for SmartFusion

COM Express & Wireless Network Showcase

Pigeon Point Systems, LLC has announced the upcoming release of significant enhancements to its AdvancedTCA (ATCA) and AdvancedMC (AMC) management controller solutions based on the Microsemi SmartFusion intelligent mixed signal FPGA. The new releases boost the performance and serviceability of LAN-attached management controllers that connect to an in-shelf LAN (such as the Ethernetbased ATCA Base Interface) to supplement the existing mandatory, but much slower Intelligent Platform Management Bus (IPMB) connection, which is based on I2C. The updated solutions cover IPM Controllers (IPMCs), Carrier IPMCs and Module Management Controllers (MMCs) for ATCA and AMC boards and modules. The updates will be released COMExpress during Q1, 2013. Engineering time significantly reduced open source standards based designs HPM.2, the LAN-attached IPM Controller specification, was adHigh capacity for application-specific opted by PICMG in August, 2012 and standardizes how xTCA manI/O on the carrier agement controllers can attach to an in-shelf LAN.HPM.3, the DHCPCarrier can be designed to fit any form assigned Platform Management Parameters specification is nearly factor complete within PICMG and Get covers how the Dynamic Host ConfiguConnected with technology and Tailored to your requirements with ration Protocol (DHCP) can companies providing solutions now COM Express modules & mezzanines be used, on an implemen- Get Connected is a new resource for further exploration Large COTS ecosystem of COM tation-independent basis, into products, technologies and companies. Whether your goal Express & XMC/PMC modules for processor and additional I/O to efficiently assign con-is to research the latest datasheet from a company, speak directly troller parameters with suchanasApplication Engineer, or jump to a company's technical page, the goal The of Get Connected is to put you in touch with the right resource. Elma Bustronic Corporation network addresses. Whichever level of service you require for whatever type of technology, E-mail: new specificationsGetstanPhone: (510) 490-7388 Connected will help you connect with the companies and products Web: Fax: (510) 490-1853 dardize functionality that you are searching for. was already implemented in many xTCA ecosystem products. USB Wi-Fi Modules Now, ecosystem participants and customers can leverage interoperabil802.11b/g/n Compliant ity among independent implementations of these specifications, which USB 2.0 hot swappable interface also add advanced features that were not previously available for LANCompatible with USB1.1 and USB2.0 attached management controllers. host controllers Up to 300Mbps receive and 150Mbps Taking advantage of HPM.2, the new with BMRtechnology releases can enable Get Connected and companies providing solutions now transmit rate using 40MHz bandwidth BMR-based managementGet controllers to is deliver the following benefits, Connected a new resource for further exploration into products, technologies and companies. Whether goal isreceive to research the latest Up to your 150Mbps and 75Mbps all in an interoperable way with other independently implemented condatasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal Get 20MHz Connected is to put you transmit rateofusing bandwidth trollers: 1) get much faster upgrades, serviceabilin touchfirmware with the right resource. boosting Whichever level of service you require for whatever type of technology, 1 x 2 MIMO technology for Getthe Connected help you connect with the companies exceptional reception and throughput ity, 2) deliver traces of IntelligentwillPlatform Management Interface and products you are searching for. 2 U.FL TX/RX antenna ports (IPMI) messaging in which they participate, and remote visibility for Wi-Fi security using WEP, WPA, WPA2 serial port traffic on a board, both aiding diagnostic efforts, 3) potenCompact size: 1.0” x 1.0” x 0.25” tially provide high-speed access to large controller data items for both (Modules) Radicom Research, Inc. the Shelf Manager and a higher level System Manager, benefiting overE-mail: Phone: (408) 383-9006 all xTCA system performance. Taking advantage of HPM.3, those benWeb: Fax: (408) 383-9007 efits can be achieved with standardized assignments of IP addresses, as well, potentially a substantial simplification in provisioning a large deployment. COM Express Custom Carrier Boards These solutions come with full reference schematics, firmware COM Express modules and Sealevel source code and FPGA design, plus comprehensive documentation, a custom carrier boards provide the year of technical support and bench top hardware. The bench top Caradvantages of custom solutions with rier IPMC can be tested directly with standard AMC modules, and the the conveniences of COTS. Connected with companies and AMC slots for additional bench topGet MMC can be installed in standard Get Connected Sealevel can include common I/O products featured in this section. with companies mentionedfeatures in this article. testing flexibility. See article in this issue of RTC magazine: “Standardsuch as serial, analog and digital I/O designed to the exact ized LAN-Attached Management Controllers Yield xTCA Performance electrical and mechanical requirements and Serviceability Gains.”

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6U CompactPCI SBC Features Third Generation Core i7 A 6U CompactPCI Single Board Computer (SBC) supports the third generation Intel Core i7 processor. Available in conduction- or air-cooled versions, the XCalibur4402 from Extreme Engineering Solutions utilizes the processor’s dual- or quad-core technology with Intel Hyper-Threading Technology, making it an excellent COTS solution for military, communications and industrial applications. The XCalibur4402 features also include a third generation Intel Core i7 processor with Intel Hyper-Threading Technology and Intel QM67 Express chipset. It supports up to 16 Gbytes of DDR31600 ECC SDRAM in two channels and up to 128 Gbytes of NAND flash and 32 Mbytes of NOR flash. The module includes Gigabit Ethernet ports USB 2.0, SATA 3.0 Gbit/s and graphics ports on the rear panel. On the front panel it also optionally offers RS-232/485 serial, 10/100/1000BASE-T Ethernet and USB 2.0 ports and it has two PrPMC/XMC sites. In-house X-ES operating system support includes a Wind River VxWorks and a Linux BSP as well as Windows drivers. Upon request, other operating systems can be supplied including BSPs for QNX Neutrino B, LinuxWorks LynxOS and Green Hills Integrity.

High Efficiency Power over Ethernet Controllers Provide up to 90W Delivered Power For devices requiring power over Ethernet (PoE), PoE+ limits the maximum power delivery (PD) to 25.5W, which is insufficient to power today’s new class of power-hungry applications, such as picocells, base stations, signage and heated outdoor cameras. Now the LT4275, LTPoE++ from Linear Technology addresses this market by expanding the power budget to four different power levels—38.7W, 52.7W, 70W and 90W—enabling complete high-power LTPoE++ systems. The LTPoE++ employs a

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XMC Module Boasts Eight 250 MSPS 14-bit A/Ds, Virtex-6 FPGA and 4 Gbyte Memory A new XMC module integrates digitizing with signal processing on a PMC/XMC I/O module. The X6-250M from Innovative Integration has a Xilinx Virtex-6 FPGA signal processing core, and high-performance PCI Express/PCI host interface. Applications include software-defined radio, RADAR receivers and multi-channel data recorders. The X6-250M has eight simultaneously sampling A/D channels that sample at rates up to 310 MSPS (14-bit). The A/Ds have matched input delays and response. The A/Ds are supported by a programmable sample clock PLL and triggering that support multi-card synchronization for large scale systems. The Xilinx Virtex-6 SX315T (LX240T and SX475T options) with four banks of 1 Gbyte DRAM provides a very high-performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates. The X6-250M has both XMC and PCI interfaces, supporting PCI Express or older PCI systems. The PCI Express interface provides up to 3.2 Gbyte/s sustained transfers rates through a x8 PCIe Gen2 interface. System expansion is supported using secondary PCI Express or Aurora port used as a private data channel or second system bus. Power consumption is 23W for typical operation. The module may be conduction-cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation include a temperature range from -40° to +85°C operation (conformal coating) and tested to 0.1 g2/Hz vibration. The FPGA logic can be fully customized using VHDL, Matlab and the Frame Work Logic tool set. The Matlab Board Support Package (BSP) supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator. IP cores for many wireless and DSP functions such as DDC, PSK/FSK demod, OFDM receiver, correlators and large FFT are available. Software tools for host development include C++ libraries and drivers for Windows and Linux (including real-time variants). Application examples demonstrating the module features are provided. Innovative Integration, Simi Valley, CA. (805) 578-4260. [].



classification scheme that simply enables LTPoE++ power sourcing equipment (PSE) controllers and LTPoE++ PD controllers to reliably communicate with one another while maintaining interoperability with IEEE standard equipment. The LT4275A (LTPoE++), LT4275B (PoE+) and LT4275C (PoE) efficiently deliver power to PD loads using just one IC. Unlike traditional PD controllers that integrate the power MOSFET, the LT4275 controls an external MOSFET to drastically reduce overall PD heat dissipation and maximize power efficiency, especially important at higher power levels. This novel approach allows users to size the MOSFET to their application’s specific heating and efficiency requirements, enabling the use of low RDS(ON) 30mOhm MOSFETs if necessary. The LT4275 recognizes a PSE as either Type 1 hardware complying with the IEEE 802.3af 13W power level, Type 2 hardware, complying with IEEE 802.3at 25.5W power level or LTPoE++ hardware complying with 38.7W to 90W power levels, and passes power accordingly. For efficient power allocation, PD users can configure a classification that represents the PD power usage. A 100V abs max rated input voltage means the LT4275 easily survives and protects PDs from the most common Ethernet line surges. A programmable auxiliary power pin with signature corrupt provides support down to 9V. The LT4275 also includes a power good output, onboard signature resistor, undervoltage lockout and comprehensive thermal protection. Linear Technology, Milpitas, CA. (408) 432-1900. [].


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A source code static analysis tool is now available for Java. CodeSonar for Java from Grammatech works on all Java code, including code written for Android. The analysis flags quality and security defects. It also works seamlessly with CodeSonar for C/C++, allowing developers to analyze code written in multiple languages and manage warnings in a single location, saving time. CodeSonar for Java also works in parallel with the popular open-source Java static-analysis engines FindBugs and PMD. Results calculated by FindBugs and PMD are automatically imported into CodeSonar, where developers can take advantage of CodeSonarâ&#x20AC;&#x2122;s advanced warning management infrastructure and reporting. Among the benefits are easier and richer annotation of warnings, tracking of code-level metrics and visualization of quality trends. Users are also able to leverage CodeSonarâ&#x20AC;&#x2122;s numerous workflow automation features, such as the automatic assignment of a warning to the developer that made relevant modifications to the file. CodeSonar for Java extends CodeSonarâ&#x20AC;&#x2122;s respected and proven functionality to encompass Java code along with C and C++. CodeSonar for Java will ship in Q4 2012.

Ruggedized VPX Driv Drive v e Storage S torage Module Whatever your drive mount criteria criteria, everyone knows the reputation reputation, value and endurance of Phoenix products. The new VP1-250X, compatible with both solid state or rotating drives, has direct point-to-point connectivity or uses the PCI Express interface with the on-board SATA controller. It is available in conduction cooled , conduction with REDI covers (VITA 48) and air cooled (shown) configurations.

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A next-generation 6U dual-slot CompactPCI processor blade showcases the development of high-performance compute blades with flexibleUntitled-1 1 expansion capabilities. The cPCI-6930 from Adlink Technology features a 1.8 GHz eight-core Intel Xeon processor E5-2448L, Intel C604 chipset, and DDR3-1333 ECC registered memory up to 48 Gbyte capacity. On-card connectivity includes four front panel GbE egress ports, 4 Gbyte soldered SATA NAND flash, optional bootable CompactFlash socket, and optional SAS/SATA direct connector for an onboard 2.5â&#x20AC;? drive to provide flexible storage capabilities. Rear I/O connectivity includes up to three SATA ports and up to eight SAS ports supporting hardware RAID via two mini-SAS connectors. The cPCI-6930 is ideal for server-grade applications, providing telecom and datacom system integrators, robust computer makers and security sectors a flexible, cost-effective solution for mission-critical applications with a reliable, smooth path for scalability and expansion. With Intelâ&#x20AC;&#x2122;s Hyper-Threading Technology, the cPCI-6930 utilizes processor resources more efficiently, enabling multiple threads to run on each core to increase processor throughput, improving overall per3UHORDGHGZLWK'26 )ODVK)LOH6\VWHP 0+]&RPSDWLEOH3URFHVVRU formance on threaded software. Intel Turbo Boost Technology allows .)ODVK.'5$0 the cPCI-6930 to run faster than the base operating frequency if operat3LQ',36RFNHW 'LJLWDO,2/LQHV ing below power, current and temperature specification limits, maxi6HULDO3RUWV mizing performance and energy efficiency. &RQVROH'HEXJ3RUW :DWFKGRJ   ELW7LPHUV High-speed data-transfer via four front panel GbE ports is enabled 9'&RU93RZHU on the cPCI-6930 by an Intel 82580EB Gigabit Ethernet controller. Two  additional GbE ports are routed to the J3 connector to support PICMG 4W\ 2.16. Additional onboard I/O includes one VGA port, two USB 3.0 ports, three USB 2.0 ports and one RS-232 serial port. The cPCI-6930 also provides a PMC/XMC expansion site supporting 64-bit 133 MHz PCI modules or PCI Express x8 XMC modules. ADLINK, San Jose, CA. (408) 360-0200. [].

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Safety and Multimedia Collide in Next-Generation Automobiles As experience-rich functionality proliferates in today’s automobiles, so does complexity and the likelihood that it could conflict with operation- and safety-critical software systems. A sure means must be found to maintain secure separation, and hypervisors offer a solution. David Kleidermacher, Green Hills Software



Safety-Critical Applications

OEM App Store ADAS


Multicore CPU





Real-Time Cluster

Multimedia Environments

Rear-View Video


t last year’s CES trade show, I saw a snazzy car demo in which each rear-seat passenger had a different high-definition movie playing on the two screens mounted on seat backs. Neither display device had a connector—the movies were being received wirelessly. Moreover, the movies were being streamed simultaneously from a 4G wireless connection to the car’s internal ad hoc wireless network. Cool stuff, especially if we neglect the data plan bill! Smartphones are being integrated into the car, not only for multimedia content, but also for automotive-targeted application and services delivery and remote control. Yes, these next-generation automotive multimedia applications are mind blowing. But they are not limited to entertainment. Let’s have a look at what is new in the area of informatics and safety. My brother just bought a car with Surround View, which provides a virtual aerial display of the car and its surroundings to aid in backing up and parking. A couple months ago, BMW announced a new iDrive system that includes 3D mapping navigation. BMW also recently introduced a heads-up display (HUD) with 3D augmented reality right on your windshield. Other Advanced Driver Assistance Systems (ADAS) include lane departure and blind spot warnings, predictive for-


Figure 1 Mixed criticality next-generation infotainment system.

ward sensing (a Nissan automobile looks two cars ahead for collision avoidance), autonomous parking (after the car has dropped you off)—just to name a few. In a nutshell, multimedia sophistication is growing rapidly in cars, providing enhanced user experiences—for entertainment, informatics and safety. These electronic systems run incredibly sophisticated software stacks, including GENIVI Linux, Android and Windows Car. While tremendously capable, we

also know these environments represent a world of rootkits, blue screens of death and Patch Tuesdays. Indeed, automotive safety applications have traditionally consisted of carefully coded real-time software, developed to stringent quality standards and executed on simple, real-time kernels such as OSEK and AUTOSAR. So how do automotive OEMs reconcile the need for safety with the desire for bells, whistles and app stores—where in-


novation is ultimately driven by consumer electronics grade, rather than automotive grade, technology? For years, automotive OEMs have sought to stovepipe and isolate the safety systems from multimedia components and other non-safety-related systems. In fact, the supply chain in the automotive world encourages this: the OEM hires different Tier-1 suppliers to build boxes for each individual function in the car and relies on incar automotive networks, such as CAN, to provide limited interactions between them. With high-end cars reaching 100 such boxes, 200 discrete CPUs across all these boxes, and numerous intra-vehicular networks connecting them all, this trend has begun to reach the limit in what can be practically developed and deployed. Electronics growth poses a significant production cost, physical footprint and time- to-market challenge for automotive manufacturers. There is another, perhaps less obvious, problem with the traditional stovepipe approach: ultimately, it stifles the passenger experience. The cluster can only display navigation information if the OEM’s RFPs for the cluster and navigation boxes included a specific requirement for such an information flow. Once the boxes are deployed, other interactions, potentially integrating and improving the overall experience of both components, become difficult or impossible, both technically and financially. The response to these efficiency challenges is to reverse the electronics growth trend and instead merge disparate functions into a fewer number of electronic components. If multiple functions can run on a single box, the physical wires become virtual wires; software improvements affect only a single box instead of multiple boxes. The performance and flexibility of communication within a single computer is far better than across a vehicular network. The consolidation trend is aided by next-generation power-efficient multicore SoCs—based on ARM’s Cortex A9 and A15—with gobs of integrated I/O such as wireless network-

ing and multicore GPU. Examples of these monsters include the TI OMAP5, Freescale i.MX 6Quad and Nvidia Tegra 3. Processor consolidation is pushing the automotive world inexorably toward mixed criticality systems in which safety, security, or real-time critical components must coexist with less critical components. For example, consolidating the infotainment head-unit with the real-time, safety-critical rear-view camera and/or driver information cluster components can result in a mixedcriticality system, as shown in Figure 1. Next-generation infotainment system architecture must ensure that consolidated components do not interact in unforeseen ways, posing a reliability risk to critical systems.

Solution: Hybrid Architecture

Open source operating systems such as GENIVI and Android are well regarded for their adherence to the latest and greatest multimedia standards and availability of third-party applications. However, we cannot depend on the multimedia OS to control all aspects of next-generation consolidated automotive systems. General-purpose operating systems cannot boot fast enough, cannot guarantee real-time response, and are not reliable enough for safety-critical functions. Therefore we need a hybrid architecture in which multimedia operating systems and their applications can peacefully coexist with real-time, safety-critical applications. Virtualization is the obvious answer to this challenge. Computer system virtualization was first introduced in mainframes during the 60s and 70s. Although virtualization remained a largely untapped facility during the 80s and 90s, computer scientists have long understood many of the applications of virtualization, including the ability to run distinct and legacy operating systems on a single hardware platform. At the start of the millennium, full system virtualization hosting unmodified, general purpose, “guest” operating systems such as Linux and Windows,

was proven practical on common PC platforms. Subsequently, hardware virtualization acceleration technologies have become common in most major microprocessor architectures. While virtualization may be best known for its application in data center server consolidation and provisioning, the technology has proliferated across desktop and laptop-class systems, and has most recently found its way into mobile and embedded environments. The availability of virtualization technology across such a wide range of computing platforms provides developers and technologists with the ultimate open platform: the ability to run any flavor of operating system in any combination, creating an unprecedented flexibility for deployment and usage.

Hypervisor Architectures

Hypervisors are found in a variety of flavors. Some are open source; others are proprietary. Some use thin hypervisors augmented with specialized guest operating systems. The goals of robust isolation between mixed criticality components within next-generation infotainment systems are achievable in Type-1 hypervisors that run on bare metal. Type-2 hypervisors run atop a general-purpose operating system, such as Windows or Linux, which provide I/O and other services on behalf of the hypervisor. Because Type-2 hypervisors, fundamentally, can be no more robust than their underlying host operating systems, which are well known to be vulnerable, they are not suitable for safety-critical deployments and have historically been avoided in such environments. Thus, Type-2 technology is omitted from this discussion. Microkernels provide a superior architecture for safety than large, generalpurpose operating systems such as Linux, Android and Windows. A microkernel runs only a minimal set of critical system services, such as process management, exception handling and interprocess communication, in supervisor mode and proRTC MAGAZINE OCTOBER 2012


Device Drivers

Guest Applications

Guest OS

Security Critical Applications

Guest OS

Guest Applications

Guest Applications

Guest Applications


Microkernel SoC Figure 2 Microkernel Type-1 hypervisor architecture.

vides an architecture that enables complex system software to run in user mode where it is permitted access only to the resources deemed appropriate by the system designer. A vulnerability or fault in one component cannot cause damage to a critical component because the infected subsystem simply does not have access to that resource. Be-


Untitled-7 1


cause the microkernel is relatively simple, it can be formally verified and certified by independent regulators to the highest levels of safety. Microkernels can therefore be used to implement system virtualization. The microkernel-based Type-1 hypervisor architecture is shown in Figure 2. Green Hills Software’s Integrity Multivisor is an example of this technology. CPU hardware virtualization assistance has been a key factor in the growing adoption of full virtualization throughout the computing world. Typical features include a true hypervisor mode that enables unmodified guest operating systems to execute with reduced privilege. For example, the CPU will prevent a guest operating system from referencing physical memory beyond what has been allocated to the guest’s virtual machine. In addition, hardware virtualization enables selective exception injection, so that hypervisor-defined classes of exceptions can be handled directly by the guest operating system without incurring the overhead of hypervisor software interposing. The TI OMAP5 and its automotive derivatives are examples of multicore ARM processors that include hardware support

for virtualization known as ARM VE— ARM Virtualization Extensions. The microkernel also provides an applications programming interface (API) and software development kit (SDK), enabling the creation and deployment of safety-critical applications (including those that follow automotive standards such as OSEK) that must meet hard realtime, safety-critical, or other stringent requirements that cannot be relegated to a general-purpose guest. In many of the aforementioned nextgeneration multimedia-rich safety systems, the microkernel must be capable of hosting its own sophisticated graphics environment, distinct from the general purpose OS used for head unit activities. For example, 3D graphics are required to implement highend safety-critical applications in clusters and heads-up displays. Therefore, the microkernel provides an OpenGL subsystem optimized for the on-chip GPUs found in common multicore application processors. The microkernel is the only software that runs in the microprocessor’s most privileged mode, i.e., hypervisor mode. Guest operating systems and their con-

10/2/12 11:45 AM



OEM App Store

Virtual Machine

Virtual Machine

Real-Time Cluster

Critical Applications

Rear-View Video

Guest OS Environments


stituent applications execute in a de-privileged mode, untrusted from the microkernelâ&#x20AC;&#x2122;s perspective. Applying the microkernel Type-1 hypervisor architecture to the aforementioned mixed criticality infotainment system consisting of the main infotainment OS, MeeGo, and safety-critical applications for rear-view camera and driver information cluster, results in the architecture shown in Figure 3. Next-generation system software architectures are required in order to ensure that future multimedia-rich automotive systems are delivered with the reliability, safety, real-time performance and controlled footprint that the automotive industry and consumers alike demand. Future in-car systems will see a convergence of safety-critical functionality with traditional telematics and digital entertainment applications. Bringing these capabilities onto a single compute platform is critical in order to minimize size, weight, power and production cost, and, ultimately, to deliver the best possible user experience. However, doing this safely requires a new systems architectural approach, at

Type-1 Hypervisor


Multicore CPU





Figure 3 Hypervisor architecture for next-generation automotive electronics.

the base of which is a microkernel-based hypervisor that can isolate and manage real-time, safety and security-critical applications alongside powerful open source multimedia operating systems.

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Advertiser Index Company Page Website ADLINK Technology, Advanced Micro Devices, Inc.............................................................................................60................................................................................................ American Portwell..............................................................................................................5............................................................................................................. Artila Electronics Co., Ltd..................................................................................................14................................................................................................................. ChinaECNet................................................................................................................... 52, Cogent Computer Systems, Inc..........................................................................................57.......................................................................................................... COM Express & Wireless Network Showcase.....................................................................49........................................................................................................................................ Congatec, Inc....................................................................................................................38............................................................................................................. Dolphin Interconnect Solutions............................................................................................4.......................................................................................................... Elma Extreme Engineering Solutions, Inc....................................................................................59............................................................................................................. Innovative Integration.........................................................................................................25.................................................................................................. Intelligent Systems Source.................................................................................................31................................................................................... JK Microsystems, Inc.........................................................................................................51.............................................................................................................. Keil, An ARM Company......................................................................................................42.................................................................................................................. Logic Supply, Mathworks, Microsemi Microsoft Windows Embedded Evolve 2012.......................................................................21................................................................................................. MSC Embedded, Ocean Server Technology, Inc............................................................................................20.................................................................................................... One Stop Systems, Phoenix International.........................................................................................................51............................................................................................................ Real-Time & Embedded Computing Conference..................................................................39................................................................................................................ RTD Embedded Technologies, Sch Super Micro Computer, Inc.................................................................................................7........................................................................................................


A seasoned embedded technology professional? Experienced in the industrial and military procurement process? Interested in a career in writing? CONTACT SANDRA SILLION AT THE RTC GROUP TO EXPLORE AN OPPORTUNITY RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.



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RTC magazine  

October 2012

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