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The magazine of record for the embedded computing industry

June 2012

PCIe over Cable: A Popular Interface Extends its Reach Embedded Technologies Fire up the Smart Grid Accelerated Processors: A New Class of Device?

An RTC Group Publication


fully-assembled turnkey solutions Run, drive, or fly your Simulink design in real time, using Rapid Prototyping or Hardware-in the-Loop simulations on low-cost PC-based hardware. xPC Target provides a library of device drivers, a real-time kernel, and an interface for monitoring, parameter tuning, and data logging. It supports a full range of standard IO modules, protocols, and target computers.

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Touch Screens Revolutionize Small Device Interfaces

52 AdvancedTCA Chassis Offers 50 Percent More Computing Density

54 6U CompactPCI Enhanced by Third Generation Intel Core Processors


56 COM Express Modules with Quad-Core Third Generation Core Processors



6Editorial Standards and Standards Groups: Are We Losing Our Way? 8

Industry Insider Latest Developments in the Embedded Marketplace


Small Form Factor Forum Standard Rules for “Industry Standards”


Products & Technology Newest Embedded Technology Used by Industry Leaders

EDITOR’S REPORT Accelerated Processors: A New Class of Devices?




PCIe over Cable

Embedded Technologies for the Smart Grid

Express over Cable 18 PCI Middleware Maximizes Application Performance

Herman Paraison, Dolphin Interconnect Solutions

as Blade-to-Blade 22 PCIe Interconnect Mark Gunn, One Stop Systems

Driving Higher Levels of 40SoCs Integration in Smart Appliances Rufino Olay and Reghu Rajan, Microsemi

Considerations for Designing 44Key Low Cost, Energy Efficient Smart Grid Devices Srinath Balaraman, Mentor Graphics

TECHNOLOGY IN SYSTEMS User Interface Design for Small Systems

Industry watch Safe and Secure Systems

the Potential of a MultiTouch Experience 26 Unlocking Computers in Safety-Critical Applications: 48Industrial Out of the Ordinary Keeping up with Embedded New User 36 Development—The Interface Mark Hamblin, Touch Revolution

Susanne Bornschlegl, MEN Mikro Elektronik

Jason Clarke, Crank Software

Family of Accelerated Processors Opens the Doors to New Embedded Possibilities Tom Williams

Digital Subscriptions Avaliable at RTC MAGAZINE JUNE 2012


JUNE 2012 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR/ASSOCIATE PUBLISHER Sandra Sillion, COPY EDITOR Rochelle Cohn

Art/Production ART DIRECTOR Kirsten Wyatt, GRAPHIC DESIGNER Michael Farina, LEAD WEB DEVELOPER Hari Nayar,


Billing Cindy Muir, (949) 226-2021

To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2, Scotts Valley, CA 95066 Phone: (831) 335-1509

Published by The RTC Group Copyright 2010, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


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6/4/12 2:04 PM







Standards and Standards Groups: Are We Losing Our Way?

Tom Williams Editor-in-Chief


ndustry standards have always been a difficult topic. The only reason we have them at all is that many markets simply wouldn’t work without them. We can’t have four versions of 120V wall outlets and plugs all competing for market share. There wouldn’t be a market to compete for. In the leading-edge computing industry it may not be so obvious because designers could possibly hesitate to introduce some real innovation for fear that it would not fit an existing standard. And, advanced though it might be, it would have to establish itself in a brand new market segment with nothing to back it up. Still, lacking existing standards that might actually cause such hesitation, many companies strike off on their own anyway into new territory hoping to attract a following that will grow into an actual recognized market. Sometimes that works, sometimes it doesn’t. To be fair, our industry has always had a bumpy ride when it comes to standards. A couple of real successes, however, have been VME and CompactPCI. Having said that it is hard to nail down exactly what set of synergistic circumstances has brought that about. It is definitely some critical mix of technology, market need and perception, personalities and commitment to name just a few. For example, a certain remark has stuck with me since the introduction of VME back in 1981. Someone whose name I have long forgotten said, “We have agreed on the design of a coliseum in which to compete.” That represents a balance of common interest and competitive, entrepreneurial spirit that has worked. The fact that VITA and its set of standards and participants have held together for all these years and continued to upgrade specifications is proof of that. A similar observation can be made regarding PICMG. I wish I could say that things were going as well in the world of small form factor modules, where it is beginning to look like we are in an unfortunate period of fragmentation. Without taking sides or passing individual judgment, it seems there are now at least four groups active in the arena: the PC/104 Consortium, the Small Form Factor SIG, to a certain extent PICMG, and now the newly formed Standardization Group for Embedded Technologies (SGET). For starters, that’s just plain too many. The reasons for this depend on whose ox is being gored or which particular interests are in play. Whatever. It’s too many.



I am certain that a big contributing factor is simply the pace of innovation in this arena. An innovator or a company thinks they have a great idea and doesn’t want to wait around while some standards committee files its nails over every miniscule point. So in addition to existing standards, we get “logo clubs” that are based on a specification that is released but called a “standard.” But there is no way to enforce such a specification and hence no way to assure a customer that there will be a second source or that the next year things will not have been introduced with incompatibilities. But that’s supposed to be one of the reasons for a standard—to build customer confidence. Now with these different groups, I am apprehensive that more than one of them may begin to claim to be the guardian of a standard previously championed by another, leading to fragmentation of standards themselves. Maybe that’s not a big worry, but it is there. Then there are conflicting interests of individual players that begin to take precedence over the common interest. It is difficult to argue with this because in any event a given company will only support the common interest if it thinks it is in its own interest to do so. An easier target—but probably as futile to deal with—are the sometimes massive egos that plop themselves in the way of cooperation. For all that, and in these difficult economic times, the situation is not good. Standards may represent the design of a coliseum to us, but to a customer they are a guide and a reassurance without which there arises doubt, lack of confidence and hesitation to invest in any of our stuff. Maybe he’d rather have something he knows will work rather than cutting-edge uncertainty. And the more cutting-edge something is, the more reassurance a customer is going to need. But we all know that. It might be tempting to just plead with everybody to sit in a circle and sing Kumbaya, but it’s really simpler than even that. If this fractioning of standards groups and goals does not somehow get resolved, everyone is going to suffer—vendors, OEMs and customers. And by extension, the broader economy will not be helped either. It might also be tempting to end with some sort of admonition, or a croak of doom. But I will be content to point to the situation. We all know it can be fixed. We can decide whether we want to play in a first-class stadium to big and paying crowds, or whether we wind up playing stick ball in the street.

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INSIDER JUNE 2012 Android Patent/Copyright Suit Remains Murky—and Potentially Ominous The titanic struggle between industry giants Oracle and Google—along with giant egos—over something like nine lines of code and other aspects of the Java implementation used in Google’s Android operating system has reached a less than conclusive interim stage with a verdict split on different points and one basic question yet unresolved. A jury in San Francisco’s U.S. District Court did decide that Google had infringed on certain general copyrights relating to Java, but could not agree on the question of whether this was or what in general constituted fair use. Oracle had been seeking $1 billion in damages. Apparently the infringement that the jury found pertains to Oracle’s copyrights on programming tools and nine lines of code. The judge in the case shot down Oracle’s billion dollar goal ruling that Oracle can only seek to claim about $150,000 for those nine lines. The bigger question, with possible industry-wide ramifications, turns on the question of the Java API. It gets complex, but the judge in the case instructed the jury to consider the question of fair use on the assumption that the API is copyrightable. The jury, however, cannot determine whether APIs are actually copyrightable. That is a matter of law for the judge to rule on. The question of API copyrightability could get very ominous. The analogy of notes (APIs) to music (actual programs) would hold that APIs being merely structural or functional as opposed to programs, which are expressive, would not be copyrightable. Declaring APIs copyrightable could have huge effects on software development if companies devised proprietary code to protect their products. Compatibility for after-market products would then be very difficult with independent applications requiring licensing, etc. And beyond the issue of software—if APIs are copyrightable, would not then processor instruction sets be copyrightable as well? That would have enormous implications for a number of very large, innovative and successful companies that have built their businesses on, for example, clean room implementations of processors based on the x86 instruction set. One has to hope that the judge very seriously considers these implications before ruling on the issue.

OpenVPX Architectural Framework Specification Updated

The VMEbus Industry Trade Association (VITA) has announced the ratification by ANSI of the second edition of the OpenVPX system specification under ANSI/VITA 65.0-2012. This is a planned update to the architecture framework that defines system-level VPX interoperability for multivendor, multi-module, integrated system environments. This release adds several profiles for payload, peripheral and switch slots, plus profiles for backplanes to accommodate the InfiniBand protocol and the VITA 67 coaxial connector type. The VITA 65 working group is continually reviewing profile candidates for inclusion in the OpenVPX specification as part



of their mission to support it as a living document that adapts to changing technology. The working group also clarified and reorganized several existing sections to improve consistency and usability of the specification. VPX is gaining design wins in many data-intensive applications where performance in throughput and high-compute density (size) are critical factors. Example applications in which VPX systems are expected to be deployed in the coming year include signal and video processing, radar, communications, transportation, and control and management. As new applications for VPX emerge, new requirements sometimes mean that new profiles must be defined to help guide the interoperability points necessary for integrating module to module, module to backplane, and chassis.

OpenVPX will continue to evolve and incorporate new fabric, connector and system technologies.

National Instruments Establishes New Vision Specialty for Alliance Partner Network

National Instruments has announced the establishment of the Vision Specialty for members of the NI Alliance Partner Network who specialize in imaging and vision systems. The NI Alliance Partner Network is a program of more than 600 accredited companies worldwide that provides engineers with complete solutions and high-quality products based on graphical system design. NI reviews the capabilities of each Alliance Partner participating in the Vision Specialty and

uses the AIA System Integration Company Certification to achieve industry validation of machine vision excellence. The NI Alliance partners participating in the Vision Specialty Program have expertise in imaging and vision systems and are experts for customers who require software development, integration or consulting services. Ultimately, they understand system-level solutions for vision applications and can specify and integrate all of the necessary system components.

Cymbet, Micross Team to Supply Embedded Energy Solutions

Cymbet has announced that it is teaming with Micross Components to distribute and package Cymbet’s entire family of EnerChip Smart Solid State Batteries and ultra-low-power management IC solutions in bare die form. Cymbet’s EnerChips are constructed on silicon wafers using semiconductor processing techniques, which makes them suitable for co-packaging with other Integrated Circuits carried on the Micross line card. Energy storage can now be embedded directly into a single miniature multichip package. Embedded energy opens up new innovative product capabilities that previously could not be realized with legacy energy storage devices. The EnerChip Solid State batteries have a footprint as small as the CBC005 bare die that is 1.375 mm by 0.85 mm by 200 microns thick. CBC012 and CBC050 provide more energy storage in similarly small footprints. In addition, Micross will be offering the CBC910 EnerChip power management IC bare die that provides all the functions listed in the Cymbet EnerChip CC series of products.

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6/7/12 1:51 PM

Mouser and TDK-Lambda Announce Partnership for Global Distribution

Mouser Electronics has announced its global partnership with TDK-Lambda to provide design engineers with reliable power solutions for their latest designs through Mouser’s ordering capabilities backed by Mouser’s customer service. TDKLambda’s products reflect the latest advancements in materials technology, process technology, evaluation & simulation technology, circuit design technology and other core technologies of the TDK Group. Their products play a role in many sectors of the industry, including telecommunications, data communications, medical facilities, testing and measurement, rail transport, automotive applications and LED devices. With its broad product line and highly regarded customer service, Mouser caters to design engineers and buyers by delivering “What’s Next” in advanced technologies. Mouser offers customers 19 global support locations and stocks the world’s widest selection of the latest semiconductors and electronic components for the newest design projects. Mouser Electronics’ website is updated daily and searches more than 8.9 million products to locate over 3 million orderable part numbers available for easy online purchase. Mouser. com also houses an industry-first interactive catalog, data sheets, supplier-specific reference designs, application notes, technical design information and engineering tools

Extreme Engineering Solutions Honored by Lockheed Martin

Extreme Engineering Solutions (X-ES) has been recognized by Lockheed Martin as an outstanding small business provider. Each year, Lockheed Martin business units in Orlando, FL and Dallas, TX nominate and select small businesses that have consistently provided outstanding support and products during the past year. Though the corporation has thousands of suppliers, only a few of the small businesses are recognized for their outstanding quality in goods and service. Executives from Lockheed Martin Missiles and Fire Control and Global Training and Logistics recently presented awards to 18 companies. “We are fortunate to have a strong base of critical suppliers that support our 14 major U.S. operations from California to New England,” said Jim Berry, president of Lockheed Martin’s Missiles and Fire Control business. “Small business firms provide unique talents that help us produce superior defense systems and advanced technologies to protect allied warfighters.” “When a customer chooses to outsource an embedded computing product to us, they are putting their trust in us. Receiving this award reinforces that X-ES is a trusted extension to the engineering groups we work with at Lockheed Martin,” states Rob Scidmore, president and CEO, X-ES. “We are honored to receive this award from Lockheed Martin and we will continue to work hard to keep their trust.”


Utilizing the same Cisco IOS software that IT staffs are already trained on, our rugged, SWaP optimized routers are battlefield-ready. The X-ES XPedite5205 PMC router module and the SFFR small form factor router platform, working in conjunction with UHF, VHF, Wi-Fi and other radio platforms create mobile ad hoc networks to provide highly secure data, voice and video communications to stationary and mobile network nodes across both wired and wireless links. Call us today to learn more.

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Colin McCracken & Paul Rosenfeld

Standard Rules for “Industry Standards”


very few years, people rush to use some word or phrase that means something different to everybody who hears it. In the political arena, the phrase du jour is “fiscal responsibility.” In the embedded market, it’s “industry standard.” With so many new “industry standards” being waved about, we really need to define some phraseology, so that system OEMs can understand at a glance what they are getting. We’d like to suggest some rules that can be adopted and used consistently throughout the industry by both suppliers and the trade press alike. Many new products today are described as meeting a new industry standard, the specification of which is published by the announcing company. Let’s get one thing straight right at the beginning: If only one company manufactures a product designed to a specific form, fit or function, it is not an industry standard, regardless of whether a “specification” has been published or not. It is and will remain a “proprietary solution” until another company builds something that is compatible. But not all compatibility is equal. Let’s say Company B introduces a product that is form, fit and function compatible with Company A. If Company B is simply distributing Company A’s product (whether or not under a new name), it is still a proprietary solution. But if Company B designs and introduces a compatible product, we have a “second source.” Note that having Company B simply endorse the specification doesn’t qualify either. They must actually design, manufacture and distribute their own product. If not, it’s still a proprietary solution. If Company C comes along and introduces a product that adheres to the specification and is not simply distributing Company A or Company B’s product, then we can finally open the door to using the term industry standard. But there are a few more rules we need to apply before we can go there. First, the specification must be freely available for download, without registration, log in or licensing of any kind. Second, the technology must be unencumbered by any patent, trade secret or intellectual property constraint. Thirdly, the copyright on the specification must be owned by an independent standards organization and not by Company A, B or C, individually or together. Fourth, Companies B and C must have designed their products



solely using the information provided in the specification and without any under the table help from Company A (including schematics or any other design material not available freely to the general public). Fifth, the specification must contain some form of license that allows it to be reproduced and distributed freely, but disallows the modification and creation of derivative works. After all, we don’t want to confuse the market with a set of “standards” that have a similar name and similar function, but are different. Note that it is OK to have a logo that is trademarked by the standards body, and is licensed for use by any vendor that wishes to indicate to the market that his product complies with the specification. It is also OK for the standards group to charge a fee for use of the logo or provide it only to members. So how does this play out in the real world? Let’s look at a couple of examples. Standards group S introduces a new specification. Until at least three companies introduce products to the market, the group can only say that a specification for a proposed new industry standard has been released. Company D introduces a new product (or family) and wishes to promote this as an industry standard. The company may have a specification available for download by any interested party. They may offer the spec to an existing standards group or create a new one. But they may not use the words “industry standard” to describe their product or specification until two other companies introduce compatible products and the specification bears the copyright of an independent standards organization. We’ll have more to say about the “create your own standards group” in a future column. So how might we begin to enforce this? It’s unlikely that the supplier community has the discipline to follow through. There are numerous violators of these rules. So we call on the trade press and editorial community to reject product press releases that use these terms loosely or improperly, and to edit technical articles to provide a precise and consistent definition for what is being offered. The cost to do this right is minimal. The value for OEMs: Priceless.

editor’s report Accelerated Processors: A New Class of Devices?

Family of Accelerated Processors Opens the Doors to New Embedded Possibilities A new family combines dual and quad-core x86 processing with high-end graphics capability that can also be used for numerically intensive applications. by Tom Williams, Editor-in-Chief




Fetch Decode Int Scheduler

Int Scheduler

FP Scheduler

L1 DCache





128-bit FMAC

128-bit FMAC

Core 2




Core 1


he concept of combining multicore x86 functionality with a powerful parallel architecture graphics processing engine on the same piece of silicon has come of age and could significantly transform the areas and applications for embedded processors. Following on its groundbreaking G-Series of what it calls accelerated processing units (APUs), Advanced Micro Devices is announcing a new series of APUs—named the Embedded RSeries. The R-Series combines even more x86 cores with advanced features integrated with even more powerful GPUs to offer a wider selection of performance, power and cost that can address a wide selection of embedded applications that increasingly rely on high-performance graphics as well as numerically intense computation. Where earlier a x86-based design that integrated graphics processing relied on the x86 CPU to interface via a North Bridge connection with a discrete graphics processor, the APU integrated both on the same chip. The GPU can, of course, be used for demanding graphics tasks as well as to offload such things as DSP operations if needed in the same code string. In the past, such operations would involve the x86 CPU sending calls to a DSP or discrete GPU to

invoke code running on the coprocessor that would then send results back to the CPU— with all the latency and overhead that would necessarily be involved. With both architectures on the same die, the application can be written as one program using OpenCL thus vastly reducing both latency and overhead. The new AMD R-Series builds on the earlier G-Series but uses a more advanced multiple pipeline x86 architecture and implements the series as a selection of dual or quad-core devices with AMDs DirectX-11 capable Radeon 7000 Series graphics engines with up to 384 parallel processing units. This integrated architecture allows a combination of dedicated and shared resources. Therefore the two or four x86 cores, each of which has four execution pipelines, a dedicated thread scheduler and a dedicated Level 1 cache, also share instruction fetch and decode, a Level 2 cache and two 128-bit floating

L1 DCache Shared L2 Cache

Figure 1 With the new dual and quad core Embedded R-Series, each x86 core has four pipelines accessed by a dedicated integer scheduler and also has a dedicated Level 1 cache. The two or four cores share a pair of 128-bit floating point units that can be combined into a shared 256-bit unit. They also share a Level 2 cache.

editor’s report

Compute Capacity Calculated1 SP GFLOPs

SIMD Engine Array





Memory Controller





Unified Video Decoder

187 178

R-268D R-252F

Platform Interfaces


G-T56N 0








Figure 2 The R-Series builds on performance and power consumption of the G-Series, whose floating point performance is at the bottom of the graph. Using a GPU with up to 384 parallel units, the high-end device can hit 578 GFLOPs per second.

point MACs, which can be combined into a 256-bit floating point unit (Figure1). In addition, the single instruction multiple data (SIMD) parallel processing GPU shares the memory controller with the x86 cores for fast access to memory as well as to provide fast communications between GPU and CPU cores. And that is before we even get to the floating point capabilities of the parallel GPU. Depending on the number of parallel processing units in a given device’s GPU, single precision floating point computation can range from 178 to 578 GLOPs per second (Figure 2). In addition, it is possible to combine the graphics performance of an APU with that of an SMD discrete GPU for even more graphics performance in terms of raw output or the number of displays that can be driven. For example, combining the performance of the high-end quad core R-464L with that of the AMD E6760 GPU would yield an additional 20% more graphics performance. That could be harnessed for raw graphical or numeric compute power or to be able to drive more displays than the four that can be directly driven from the device. Interfaces available directly on the chip include HDMI, Display Port and DVI. In addition to the four independent display ports, a x16 PCI Express port can be configured as up to four more outputs for either graphics or other I/O. This can be config-




255 237


x86 Cores

ured as up to four DVI interfaces to directly drive up to four more displays. By using a discrete GPU on a Windows 7-based board, it is possible to drive up to a total of ten displays. A selection of controller hubs will be available to provide additional I/O including SATA, VGA, USB 2.0, USB 3.0 and PCIe 4x1. There is even a hub available that supports the legacy PCI bus (Figure 3).

Additional Support Features

The ability to support such high-end graphical and compute capabilities on a single chip suggests a range of applications that can benefit from additional features required by such things as video conferencing, surveillance and other kinds of distributed applications. For example, the ability to manage distributed nodes independent of operating system state is supported by AMD’s DAS 1.0 implementation of the Desktop and mobile Architecture for System Hardware (DASH) management scheme. It allows remote operators to go into systems and reset or power down and restart them and perform remote BIOS updates among other things. A dedicated video compression engine offers hardware support for the encoding and compression needed for distributed applications such as video conferencing and surveillance where high-definition video





USB 2 PCIe 4x1 USB 3.0 Optional

Unified Media Interfaces

Controller Hub

Figure 3 The cores and the GPU (SIMD Engine Array) access memory via the shared controller, which can support 1.5V, 1.35V and 1.25V DDR3 memory. Several high-end graphics interfaces are directly available from the device with other I/O available via the controller hub.

must be rapidly transmitted across wired or wireless networks at constrained bandwidths. There are also performance enhancements for secure asset management in terms of encryption and decryption for sharing and rendering protected video content. A broad range of decode support is also provided to support low-power rendering of video content. This includes H.264, MPEG-2, VC-1, MPC, DivX, MPEG-2 IDCT+ MotionComp, Dual HD Decode (1080p+1080i) and MVC for Blu-ray Stereo 3D. Thus, in addition to the raw power of control, numeric and graphical computing, there is a range of interfaces and builtin services that address a wide and growing range of application needs on a single chip that can be run by a single set of code written in a single language, namely OpenCL. Therefore one development discipline can be used to exploit the capabilities built into something like an APU. RTC MAGAZINE JUNE 2012


editor’s report

Where from Here?

Now why, exactly, this detailed description of an admittedly major new product line? For one thing, the implications are potentially enormous. AMD is currently leading the market in this particular arena, but it is sure to attract competition. What happens then is anyone’s guess, but we can take a shot at predicting. First, there are a good many identified applications for which such a device would be a distinct advantage. These include digital signage where the ability to control multiple displays is a must and the capability for remote management is very desirable. There are increased possibilities in security and surveillance where there is a need to manage multiple video feeds. Teleconferencing, high-end casino gaming and advanced medical imaging all come immediately to mind. But along with such increased capabilities there arise possibilities we may not have thought of yet and these deserve exploration as well. It is tempting to compare the significance of the emergence of the APU as a new class of devices along with that of the applications services platform (ASP), which combines a general-purpose CPU—


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in that case an ARM architecture—on the same die with an FPGA fabric. Such devices have recently been introduced by Xilinx, Microsemi and Altera. While ASPs may address a whole different set of potential applications and are a huge step forward, they need to overcome the fact that they combine two different development disciplines—that of the programmer and the FPGA developer, which are not often mastered by the same person. Admittedly, graphics development is a more specialized discipline than general programming as well, so there will be hurdles. Here, however, the same code base can access and allocate the resources dynamically, such as by dedicating parts of the parallel engine to numeric computation and others to graphics rendering. One simple example that everyone can relate to is the now notorious game, “Angry Birds.” Anyone who has played the game has no doubt noticed that in addition to the display of flying birds and the various things they destroy to thwart the evil pigs, there is also physics at work. The boards, rocks and other objects sway and either fall or don’t fall, smash or don’t smash, according to the force and an-

gle of how they are struck. These are two different types of calculations. The same can be said of such more practical applications as computational fluid dynamics, seismic computation and display or many other sophisticated problem solving applications. The ability to combine a CPU architecture that is capable of general-purpose programming including interrupt-driven and real-time control with a graphics processor that is also capable of intense numerical computation, opens a vast number of possibilities. Consider as only one example the combination of machine vision with motion control. Video data captured by a machine’s “eyes” can be rapidly processed in the GPU’s parallel units, features or other clues extracted, and then used to direct the CPU to move arms, wheels or other aspects of a vision-directed application all on one main device under the control of a unified set of code. We leave the reader to imagine further. Advanced Micro Devices Sunnyvale, CA. (408) 749-4000. [].

5/4/12 1:53:35 PM





Extend your system’s I/O cards ‘outside-the-box’ over cable to a chassis containing additional card slots Basic to Smart expansion options for practically any environment For test and measurement, medical imaging, surveillance, aerospace and defense, telecommunications, data acquisition, high performance computing, and audio/video production congurations Rock solid expansion solution provider since 1987




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Magma is a trademark of Mission Technology Group, Inc. PCI Express is a registered trademarks of PCI-SIG. Thunderbolt and the Thunderbolt logo are trademarks of Intel Corporation in the U.S. and/or other countries.


connected PCIe over Cable

PCI Express over Cable Middleware Maximizes Application Performance New software and flexible PCI Express over cable solutions simplify interconnect requirements in high-performance embedded solutions. by Herman Paraison, Dolphin Interconnect Solutions


ystem architects increasingly look backplanes, cables and switch solutions to to PCI Express over cable as a accomplish this task. The resulting archimeans of improving real-time sys- tecture features reduced system latency ploration tem performance. The ability to parti- and increased data throughput. For interyour goal tion systems with PCI Express over cable process communication, PCI Express supk directly makes development of real-time control ports both CPU-driven programmed I/O age, the source. systems easier and faster for embedded (PIO) and Direct Memory Access (DMA) ology, applications. Yet, PCI Express has been as transports through non-transparent d products basically isolated to the I/O portion of bridging (NTB). So why are many within system architectures, with little emphasis the embedded community reluctant to use placed on inter-process communication PCI Express for inter-process communisuch as shared memory, RDMA, replica- cation, but instead focus on implementing tion, or accelerated networking perfor- a dual interconnect solution adding Ethermance. Instead, embedded system design- net or another interconnect solution? The ers introduce a separate interconnect for hesitation results from a lack of middlenies providing solutions now This increases complexware software that addresses multipromultiprocessing. ion into products, technologies and companies. Whether your goal is to research the latest architectures. PCI Express acity and cost, and limits flexibility. PCI Ex- cessing tion Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ceptance as an inter-process solution repress over cable’s cost, functionality and you require for whatever type of technology, quires new easy-to-use functional drivers characteristics suit multiproand productsperformance you are searching for. and middleware. Such middleware takes cessing applications, but it’s been slow to advantage of PCI Express unique perforgain traction. PCI Express over cable provides mance attributes while exposing standard numerous advantages. In an asymmet- interfaces to higher level applications inric multiprocessing architecture, which cluding Ethernet-based applications. This middleware is now available partitions resources into discreet known entities, PCI Express over cable enables and implements a software transport insystem architects to partition systems be- terface between applications and the PCI tween processors, I/O and memory. Sev- Express data transfer layer. The middleeral vendors offer various adapter cards, ware software interfaces with applications through shared memory libraries, Berkeley sockets and TCP/UDP functionality. Get Connected It utilizes the data transfer layer to move with companies mentioned in this article. data between processors, memories and

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I/O devices through the NTB functions of PCI Express. In addition, by using direct remote memory reads and writes and standard DMA operations (RDMA), the middleware implements a reliable and very efficient data transport for applications. These architecture layers seamlessly integrate to take advantage of the performance attributes of PCI Express and create a simplified environment for software development and support.

Software Overview

The middleware includes two key components, a Berkeley compliant sockets interface and an optimized shared memory API. Figure 1 shows the components of the software architecture based on Dolphin Interconnect Solutions shared memory programming API and middleware for PCI Express. The Berkeley compliant sockets library reduces the number of system resources and interrupts needed for data transfer in order to optimize data throughput and latency. The optimized shared memory API allows applications to safely map chunks of remote memory and supports data transfers based on PIO and DMA. It also allows triggering remote interrupts and managing events generated by the data transfer layer. Within the sockets interface, stan-

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Application MPI2

Socket Switch

Shared Memory API

TCP/IP Stack

PCIe Sockets

IP Driver

PCIe Driver

IP Driver


PCIe Express Hardware

failover Figure 1 The middleware is organized for simultaneous communication. The PCIe driver is used for setup, DMA and plug and play management. PIO transfers originate directly from the application.

Half Roundtrip Perormance PCI Express Sockets

Intel 10 GigE

Figure 2





Message Size (bytes)












200 180 160 140 120 100 80 60 40 20 0 1

Latency (microseconds)

dard mechanisms like Windows Layered Service provider API and Linux Sockets Direct enable standard applications to run over PCI Express without modification. The PCI Express middleware takes advantage of these techniques to deliver a sockets interface that significantly accelerates application performance compared to traditional 1G and 10G Ethernet hardware. Figure 2 illustrates the latency results of PCI Express sockets vs. 10 Gbit Ethernet. The sockets interface deploys differently on Linux and Windows. To implement this interface on Linux, the address family changes from the regular sockets family. The PCI Express sockets interface implements an AF_ INET compliant socket transport called AF_SSOCK. The Linux LD_PRELOAD functionality preloads the standard socket library with a special sockets library that intercepts the socket() call and replaces the AF_INET address family with AF_SSOCK. All other socket calls follow the usual code path and the PCI Express sockets module accelerates them if the destination address falls within the PCI Express network. For Windows, most applications use dynamic link libraries provided by the operating system (WS2_32. DLL and KERNEL32.DLL) for socket communication. Windows sockets are regular handles, so normal handle operations, such as closure, duplication and inheritance when a new child process is created, are applied on them. PCI Express sockets middleware intercepts the required WinSock2 API calls. During runtime, all socket calls route through a sockets switch. Basic configuration files control the communication channel. These files identify systems in the processor cluster and their associated node ID in the network. Sockets configured for a PCI Express end point route through the low latency sockets library. All other connections route back through the standard WinSock2 or AF_INET transport library and regular Ethernet. Measurements show that the redirection is virtually instantaneous and adds no overhead to system calls. An optional configuration file can explicitly enable or disable individual PCI Express sockets communication. The sockets library implements PIO

Application-to-application socket latency is as low as 1.75 Îźs and far lower than 10 Gbit Ethernet.

transfers for small messages and engages DMA engines to transmit large messages. Since the sockets interface uses standard calls, it is application transparent. The combination leads to low latency and high throughput without application changes or tuning, Figure 3 shows the results of

a LINBIT DRBD benchmark using the sockets interface. The PCI Express socket library outperforms other interconnects in write performance when using DRBD. In addition, the sockets middleware comes with built-in high availability. If the PCI Express network is unavailable, RTC MAGAZINE JUNE 2012


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socket communication reverts to the regular network stack. The Linux version comes with an instant fail-over and failforward mechanism that transparently switches between PCI Express and regular networking if the PCI Express communication is disabled, for example, due to a disconnected cable).

Shared Memory API

Setup and configuration of an NTB environment requires knowledge of chipsets, programming and PCI Express experience. Vendors of PCI Express chipsets provide example code to simplify this process, but to reach an optimal and flexible solution requires a significant amount of work. The PCI Express shared memory API simplifies the development of NTB applications for those seeking maximum performance. The shared memory API includes drivers that allow developers to allocate memory segments on the local node and make this memory available to other nodes. The local node then connects to memory segments on remote nodes. Once available, a memory segment is


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accessed in two ways, either mapped into the address space of your process and accessed as a normal memory access, such as via pointer operations, or by way of the DMA engine in the PCI Express chipset to transfer data. Mapping the remote address space and using PIO may be appropriate for control messages and data transfers up to something like 1 Kbyte, since the processor moves the data with very low latency. PIO optimizes small write transfers by requiring no memory lock down and using a write-posted store instruction, since data may already exist in the cache and the actual transfer is a single CPU instruction. A large transfer with this PIO methodology creates processor overhead, so DMA is often preferred. The DMA approach allows the CPU not to be involved in the data movement. Latencies usually increase slightly because of the time required to lock down memory and set up the DMA engine and interrupt completion time. However, more data transfers joined and sent together to the PCI Express Switch in order amortizes the overhead. The shared memory

API sets up the DMA queue and passes one or more specifications of data transfer to the DMA engine. The shared memory API also manages interrupts. The API includes management support for local and remote interrupts, along with other advanced features such as caching, managing data transfer errors, event generation and a callback mechanism. Simulator applications distributed over several systems illustrate a shared memory API implementation. The PCI Express over cable solution delivers direct system communication with the lowest possible latency and data delivery jitter using uni- or multi-cast communication. Data written to remote nodes typically arrives in remote memory within less than 0.74 microseconds as shown in Figure 4. Cacheable main system memory stores data. This gives a significant performance and cost benefit over interconnect solutions that rely on device memory for communication. Remote interrupts or polling signals the arrival of data from a remote node.

5/2/12 1:41:12 PM

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PCI Express

800 700 600 500 400 300 200 100 0

DRBD Random Write Performance

Embedding Excellence

Figure 3

MSC Embedded offers a large variety of COM products in COM ExpressTM, QsevenTM and ETX®. Our COM products are scalable, easy to install and powerful to enable long living industrial applications with an upgrade path to future needs.

DRBD random write test on Intel 10Gbit Ethernet controller, Mellanox 40Gbit InfiniBand controller and Dolphin IX PCI Express controller.

Half Round Trip Latency PCI Express 4



COM Express™ MSC CXB-6S

3 2.5

Intel® CoreTM – 2nd Generation


ƒ Multiple i5, i7 and Celeron processor options available


ƒ Single, dual and quad core solutions

1 0.5

ƒ Intel® HD Graphics 2000 / 3000 ƒ Intel® QM67 or HM65 Platform Controller Hub

0 0







Figure 4






ƒ Up to 16GB DDR3 SDRAM, dual channel

Byte Size

ƒ Four SATA-300 interfaces ƒ One PATA interface

Half round trip latency is under 1 μs with the optimized shared API library.

ƒ LVDS (24 Bit, dual channel) and VGA

ded systems and commercial applications. The powerful tool set enables PCI Express to tackle applications traditionally occupied by Ethernet or proprietary interconnects. This is the next step in the PCI Express evolution. Dolphin Interconnect Solutions Woodsville, NH. (603) 747-4101. [].

ƒ Resolution up to 2560 x 1600 ƒ Five PCI Express™ x1 lanes ƒ Eight USB 2.0 interfaces ƒ COM Express Type 2 125 mm x 95 mm (4.92 x 3.74”) V-2_2012-WOEI-5945_RTC

Since the memory segments are normal cacheable main memory, polling is very fast and consumes no memory bandwidth. The CPU polls for changes in its local cache. When new data arrives from the remote node, the I/O system automatically invalidates the cache and caches the new value. Overall, the addition of PCI Express middleware enables powerful new PCI Express over cable solutions for embed-

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3/1/12 9:52:51 AM


connected PCIe over Cable

PCIe as Blade-to-Blade Interconnect PCI Express is no longer just a component-to-component and board-toboard interconnect on motherboards, but has expanded its utility to include box-to-box and CPU-to-CPU communication. Now, a first-of-its-kind supercomputer uses PCIe as blade interconnect. by Mark Gunn, One Stop Systems


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PCIe x16, Gen3, 128

PCIe x8, Gen3, 64

IB 12X SDR, 24

PCIe x4, Gen3, 32

10Gb Eth, 10

IB 4X SDR, 8

n 2010, the Department of Energy released a specification for a high-density, liquid-cooled compute platform that can be powerful enough for high-perploration formance computing (HPC) applications your goal and cost-effective enough for general enk directly terprise applications. One of the requireage, the source. ments was that all the blades must comology, municate over PCI Express (PCIe). This d products year, the first liquid-cooled blade center using PCIe as the blade-to-blade interconnect is scheduled to ship to Stanford Linear Accelerator Center (SLAC). The 320-node blade center is housed in two 42U racks, each containing five enclosures with 16 blades each. Each blade supnies providing solutions now ports two motherboards, each with two ion into products, technologies and companies. your goalAll is to research the latest of the latest Intel 8 core Whether processors. ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you CPU boards are connected to each other you require for whatever type of technology, a series and productsthrough you are searching for. of PCIe switch boards, cables and stand-alone switches. The SLAC blade center is an open Figure 1 platform that accepts any mechanically Bus/cable interface performance comparison. conforming device. All electrical and electronic components and boards are readily replaceable, ensuring a multi-ven- storage systems or combinations thereof. refrigerant can carry off the same amount dor compatibility and multi-generational The power and cooling overhead is so low of heat as 5.5 liters of air using only a platform life. The blade center is ideal (in many cases less than 10 percent of true small fraction of the pumping energy. The for hosting high-performance computing, IT load) that it is an excellent choice for thermal resistance between the hot chips cloud computing, routing and switching, any multi-server application. The platform and cold plate is designed to be very low. is cooled by two cold plates on each front Often the returning refrigerant can be reblade. Pumped R134a refrigerant carries cooled by ambient air without the use of Get Connected away the heat via highly efficient refriger- a chiller. Typically, cooling overhead is 5 with companies mentioned in this article. ant phase change. One cubic centimeter of to 10 percent of IT load. Chips dissipating

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up to 300W each can be accommodated and cooled. The following describes the hardware and software that allow the PCIe communication between each CPU board. PCIe over cable has come a long way since its inception a few years ago. At that time it was limited to connecting a server to one or more PCIe devices over a PCIe cable, often referred to as “I/O expansion.” Pretty soon people began asking about using this technology for server-to-server communication, referred to here as “networking.” This use of PCIe over cable requires different hardware using nontransparent bridging and a software driver installed on each server in the network. A growing number of networking applications began looking at PCIe over cable because of its increased bandwidth versus 10Gbit Ethernet and its reduced cost versus InfiniBand. Figure 1 shows the bus performance characteristics of PCIe versus Ethernet and InfiniBand. Figure 2 provides a simple price comparison between these three contemporary fabrics used in data center and HPC applications. As shown, PCIe provides a 25% performance increase over InfiniBand and 68 percent over 10 Gbit/s Ethernet. Similarly, PCIe is over 60 percent less expensive than either InfiniBand or 10 Gbit/s Ethernet. With its industry standardization, high performance and low costs, PCIe over cable is well suited for within-therack networking applications. In addition, PCIe over cable offers low latency as a result of no protocol conversions, minimum switch layers, PCIe switch cut-through and memory to memory DMA transfers. In the SLAC blade center, throughput is 40 Gbit/s for any CPU to any other CPU with a total throughput = 320 x 40 Gbit/s = 12.8 Tbit/s. Also, the system is nonblocking, so all CPUs can communicate simultaneously at full speed.

The Hardware

Each 42U rack contains five 16-blade enclosures. Each enclosure contains sixteen CPU blades (Figure 3). Each CPU blade contains two CPU boards, each of which contains two 8-core Intel CPUs (Figure 4). Each board connects to a switch blade (Figure 5) and each switch

Connectivity for 8 users 40Gbit Infiniband


Includes switch, host adapters & cables 10Gbit Ethernet


Includes switch, host adapters & cables 40Gbit PCI Express


Includes switch, host adapters & cables

Figure 2 Price comparison of PCIe, InfiniBand and 10Gbit Ethernet.

Figure 3 Sixteen-blade enclosure from Clustered Systems.

blade connects to each other through a 40port stand-alone switch (Figure 6). Each CPU board also has access to a 1Gbit Ethernet port. Therefore, a virtual terminal can run over Ethernet to provide a human interface to each CPU board. An Ethernet switch in each switch blade reduces the number of ports to one port per switch. Two 10 Gbit/s Ethernet ports are located in one of the 40-port external switches. Each CPU blade can use the 10 Gbit/s Ethernet ports as if they were local ports. PCIe over cable as a high-speed networking solution requires switch-based hardware with non-transparent (NT) ports and a software product that provides drivers and support tools for various network configurations interconnected by PCIe over cable. In the case of the SLAC blade center, switches with NT ports are located on the two switch boards that connect the 32 CPU boards in each enclosure. The switch boards route the PCIe signals from the blades through switches to PCIe cable connectors. Non-transparent PCIe bridges are used to isolate and reconfigure the clock signal and provide memory mapping aliasing. The NT bridges allow cross-

Figure 4 Clustered Systems’ CPU blade with two CPU boards.

mapping of memory address segments through the bridge so that either CPU can read and write to/from certain segments of other CPU’s memory. In effect, a “virtual target” device is created by isolating a CPU behind a non-transparent bridge such that it looks like a PCIe endpoint to another host CPU. As explained further below, this concept can be extended to multiple elements by incorporating PCIe switches that allow one host CPU to connect to multiple PCIe endpoints. To implement a full network, the architecture is further extended in a multi-tiered fashion. Each rack contains two 40-port switches. Each switch has 40 PCIe x4 cable connectors, each cabling to the cable connectors on the switch blades. The following illustrations show the interconnection of the CPU blades, the switch blades and the 40-port external switch boxes. Sixteen CPU blades in each enclosure plug into each switch blade, located behind the CPU blades. Each switch board has eight PCIe x4 cable connectors. Each connector is cabled to an external 40-port switch. RTC MAGAZINE JUNE 2012


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The Software

Figure 5 One Stop Systems PCIe switchboard connects 16 motherboards to external; switches with 8 PCIe x4 cables plugging into cable connectors (top) and 16 blades plugging into 16 high-density PCIe connectors (bottom).

Figure 6 One Stop Systems 40-port switch.

Application Layer TCP Layer IP Layer


Software Implementation

ExpressNet Driver PCI Express Transaction Layer Data Link Layer Physical Layer Figure 7 ExpressNet OSI model.



Hardware Implementation

Initialization and fabric management software runs on two miniITX-style CPU boards located in each 40-port external switch. This software initializes the PCIe components, understands the full network topology, and communicates with other nodes and other hosts. It also continually monitors the network nodes to detect failures and hot-swap events and updates the topology when hot-swap events occur. Each CPU communicates via memory-tomemory DMA transfers. The 10Gbit Ethernet ports on the 40-port external switch can be used by each CPU blade. The ExpressNet Driver software runs on each CPU board in the CPU blades. It configures the NT bridges and allows the direct data transfer (DDT) between CPUs. This is a low latency, low overhead protocol to move data. The driver initializes the hardware, memory mapping, write combining and/or DMA and provides the optical programming interfaces (Figure 7). For direct data transfers (DDT), memory regions in each CPU are mapped to all other CPUs, and direct writes into the other computer’s memory are executed. That is, no data is stored and forwarded in DDT. Each application writes directly to other CPU’s memory. Address spaces are set up such that reads and writes to those addresses go directly to another CPU’s physical memory. There are separate allocated memory spaces for each possible pair of intercommunication nodes. Typically 1 Mbyte per pair is allocated (Figure 8). Software running on each CPU initializes memory windows into each other CPU’s memory. This creates a virtual mesh structure where any CPU can directly communicate with any other CPU. Combining a host CPU with a switch element hides the host CPU’s uniqueness allowing all other node CPUs to be homogeneous. All of the usable CPUs are virtual targets, thus they can all be identical. In the software virtual mesh architecture (Figure 9), each node has dedicated memory for each other node. A host CPU’s BIOS code searches each PCIe bus and identifies each PCIe endpoint. It then configures the endpoint devices and allocates memory and interrupt resources. Non-transparent bridges

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isolate PCIe bus segments. This stops normal CPU initialization programs (such as the BIOS) from seeing any devices on the far side of the NT bridge. The advantages of PCIe over cable versus other networking fabrics on the market today are greater performance and less cost. PCIe over cable is used in many networking applications today and has even expanded its breadth to the 320-CPU system described above. The SLAC blade center is designed and manufactured by a consortium of companies as an open architecture product. All electronic components, including the backplanes, are designed to be field replaceable. Each blade accommodates a single 12.8” motherboard or two half width (6.4”) server motherboards. Each chassis holds 16 blades and 4 switch (back) planes. The system can simply be populated with any mix of servers, GPUs, disk arrays, or even network line cards and switches. A user can thus mix and match components, possibly from different OEMs. Companies involved in the project are Clustered Systems, Intel, Emerson Network Power, Panduit, One Stop Systems and Inforce. Clustered Systems Santa Clara, CA. (408) 327-8100. [].

Address Space


App 1

App 2

Address Space

Memory PCIe over cable

Figure 8 Direct data transfers utilize allocated address spaces belonging to each CPU. Intel Santa Clara, CA. (408) 765-8080. [].

One Stop Systems Escondido, CA. (877) 438-2724. [].

Emerson Network Power Columbus, OH. (614) 888-0246. [].

Inforce Computing Fremont, CA. (510) 683-9999. [].

Panduit Tinley Park, IL. (800) 777-3300. [].

A lifetime of support


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User Interface Design for Small Systems

Unlocking the Potential of a MultiTouch Experience Creating an effective multi-touch user interface requires a combination of technology and art. The foundation must be reliable hardware with adequate graphics and processing performance. This must support a UI design that understands the user’s needs and behavior. by Mark Hamblin, Touch Revolution


oday’s smartphones and tablets have awakened the world to the capabilities and ease of use of multi-touch systems. Innovative OEMs, ODMs and systems integrators are designing multitouch capabilities into products as far ranging as retail point-of-sale systems, industrial control equipment, seatback entertainment systems and white goods. The research firm Display Search forecasts the total touch screen module market will grow to $9 billion annually by 2015, from $3.6 billion in 2008, a CAGR (compounded annual growth rate) of 14%.

Drivers of the Multi-Touch Experience

While traditional keyboards and mice will have a place in certain applications, multi-touch will continue to proliferate into a wider range of products, replacing lower-tech interfaces such as buttons, dials and knobs. Five key factors are driving the expanded use of multi-touch interfaces. A well-designed multi-touch interface simplifies the interaction with the device by providing features that are more intuitive. For example, any user of a smart device knows that if they spread their fingers apart on a screen, the image will



zoom in. Multi-touch provides for more accessible interfaces and also enables continuous inclusion of new functions into a device. Therefore multi-touch helps “future proof” a device since software can be continuously upgraded. A well-implemented multi-touch interface can be much simpler to use than a conventional mechanical or button-based interface. It can show the user only those controls that are relevant to a particular operation versus conventional controls that are always visible to the user. This characteristic also facilitates expanding the interface’s functionality since additional functions can remain hidden until they are needed (Figure 1). Designers can also implement multitouch interfaces to offer a sequential guide to help users through a series of control steps, similar to a “set up wizard” on a PC. These features improve the user experience by making the device easier to understand. For example, many of today’s kitchen appliances include a multi-touch interface that appears at first glance to have fewer features since the interface is clean and simple. In fact, these appliances offer many more features than the button and knob controlled products of just a few years ago.

Figure 1 Multi-touch graphic displays allow the design of user interfaces that are graphically intuitive to the user and show only those functions that are relevant for the particular stage of interaction. They also ease the addition of functionality and specialized applications that convey the appropriate user experience.

As seen on today’s smart devices, multi-touch interface gestures, defined as two-dimensional figure motions, can further simplify an interface and provide an intuitive user experience that transcends the typical “button replacement” configuration of most simple multi-touch


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Typical Touch Panel Construction Method Single glass sensor laminated to cover glass Cover Glass Decoration Ink Pattern OCA (Optically Clear Adhesive) Flex (Controller + Passives) Bonding Glue (ACF) Touch Sensor Transparent Conductive Circuit Pattern and Metal Trace Connection

Touch Sensor Glass Substrate

Figure 2 P-Cap technology allows touch displays to be mounted so they can sense behind a protective layer of glass and implement multi-touch user interfaces for handheld and mobile devices.

interfaces. Gestures allow a sense of control over interface elements that mirror physical elements, allowing for a concept known as â&#x20AC;&#x153;direct manipulation.â&#x20AC;? For example, swiping emulates the finger motion

involved in turning the pages of a book. Interactive multi-touch interfaces provide a significant benefit over conventional static interfaces since designers can configure them individually for each user,

languages can be changed as required, options can be simplified for beginning users, and pop-up help menus can appear automatically. The device can even automatically make these reconfigurations upon sensing information about the user. Accessibility will become increasingly important as multi-touch interfaces move into more devices and face an increasingly diverse user base. A reconfigurable multi-touch interface without hardware dependencies enables designers to modify and improve the interface over time, and even upgrade and change the functionality of the entire device. Designers can introduce new features to devices after the initial sale, fix bugs remotely by upgrading the software over a network connection, reconfigure the interface after actual field usage data is collected, and load new applications on the device through an online store or other provisioning system. As device manufacturers continue to add more complex features and interfaces, the ability to future proof will become increasingly important, as already realized


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in automotive and GPS applications. A multi-touch interface is really just a blank slate onto which the control of any application or function can be placed. This allows a multi-touch interface to be the common element through which various functions can converge into one device. In the past, the need for different physical interfaces such as buttons determined the need for products and applications to be separate. For example, in a business environment, a physical business card file or phone list on paper is often located beside a desktop phone. Neither of these two products provides an interface that a designer can merge with the other. If a gesture-based multi-touch interface were implemented on the desktop phone, integrating a GUI-based electronic contact direction, there is an obvious workflow improvement.

Typically, projected capacitive sensors are made up of three major components: the sensor glass, the cover glass and a flexible printed circuit (FPC) with controller. The sensor glass includes a series of electrodes that are configured into rows and columns. These electrodes are made of a transparent indium tin oxide (ITO) conductive coating. Each electrode is routed back with a metal trace to a connection point where the FPC can be

bonded. The FPC generally contains the controller for the touch sensor. The cover glass is optically bonded on top of the sensor glass, burying the electrodes within the stack of the lamination. The cover glass serves as a dielectric between the userâ&#x20AC;&#x2122;s touch and the electrodes of the sensor glass. It also doubles as a barrier layer, protecting the sensitive electrodes from the environment and any potential damage.

Deploying the Multi-Touch System

Critical to the successful deployment of a multi-touch system is selecting the optimal multi-touch technology, controller board, enclosure and HMI, such as OS, graphics and CPU power. These components are customizable to fit a wide range of conditions and user needs. Clearly, a multi-touch system used on a forklift in a distribution center, a system used to operate an MRI machine in a hospital, and a system integrated into an informational kiosk outside a convention center have enormously different requirements. There are several multi-touch technologies available, each with benefits and deficiencies. The flexibility of industrial design, optical clarity, accuracy, response speed, need (or lack thereof) for a stylus are among the factors that will guide the choice as to which multi-touch technology is best for a given deployment. Projected capacitive (P-cap) technology provides a high-quality, multi-touch experience and suits a wide range of applications, including both indoor and outdoor environments and ranging from retail POS to industrial settings. It stands up well to wide temperature swings and is highly reliable. P-cap provides high chemical resistance, high impact resistance, an infinite number of touches and features high-strength glass (Figure 2). Untitled-19 1


2/3/12 3:55:28 PM RTC MAGAZINE JUNE 2012

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The controller continually scans and monitors the capacitance of the electrodes. When a finger touches the surface of the cover glass it pulls a small charge from the electrodes, and using complex algorithms, the controller can determine the exact location of the touch. When selecting a CPU board, designers must think through how the system will be used both today and in the future. Specific features to focus on include responsiveness, speed, unambiguous and simultaneous touches, integration with the display and the calibration required. One significant advantage of P-cap technology is it does not require calibration. An advanced, complex multi-touch experience will require a more powerful CPU board to provide the performance the user will expect from the touch experience. And, a product with a simple multi-touch experience today where the designer plans to add more functionality in the future, may require a CPU board as or more complex than the advanced system described above, depending on anticipated functionality down the road. As with every other component of the multi-touch system, selecting the right enclosure is critical to maximize performance. Some enclosures must be made of materials that resist harsh chemicals, such as those used to sterilize hospital equipment. Others must be sealed to ensure they are waterproof. P-cap technology allows for a wide range of enclosure possibilities. Designers can flush mount the module, for example, avoiding the need for a bezel. This capability provides several advantages, such as preventing dirt, cleaning chemicals and bacteria from entering the modules. This is especially important in sterile environments, such as in medical facilities. Getting the human-machine interface (HMI) right starts with a powerful processor that enables smooth graphics and a user interface that is well conceived and written. A weak processor or poorly designed graphical user interface renders an otherwise well-designed multi-touch computer worthless. A few key elements to ensure a successful user interface include ensuring that the functions reflect the user’s knowledge and behavior and that choices are made clear for the user

through well-organized menus that are at most two to three levels deep. These second and third levels should closely resemble the first in order to make the experience easy to understand. In addition, there should also be understandable visual feedback, such as progress indicators, so users know where they “are” in a multistep process.

Multi-Touch Deployment Best Practices

OEMs, ODMs and integrators seeking the benefits of a multi-touch experience must then tackle how to do it. While today’s smart devices act as benchmarks for a multi-touch experience, those attempting to create a similarly intuitive, easy-to-use multi-touch interface quickly learn it is not as simple as buying a capacitive touch sensor and wiring it into an existing product. Incorporating multi-touch capabilities into a product involves hardware, software, integration, optimizations and testing. Understanding and applying ten best practices will help designers maximize the power (and ROI) of a multitouch experience. Think holistically: Rather than connect a multi-touch computer to an existing product, think about creating a new product that is designed to take maximum advantage of multi-touch capabilities. Factors to consider include end user demographics, the product’s industrial design, system hardware selection and supported features. Select the right multi-touch technology: The “right” technology will do more than meet requirements for today. The designer must understand how the product might be used in two to three years and build in functionality that will certainly make increased demands on the system. Utilize a touch-friendly operating system: Developing an attractive, intuitive, gesture-based multi-touch GUI is a difficult process. Utilizing an operating system, such as Google Android, Apple’s iOS and Windows 7, which (to varying degrees) are specifically designed for touch, makes the designer’s job significantly easier by pre-integrating many common multi-touch user interface elements, such as sliders, selection switches and gestures like “flick to scroll” and “swipe.”

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Don’t skimp on integration testing: Allowing sufficient time for integration testing is critical. Among the issues that are common and require attention include the effects of RF-EMI on the multi-touch sensor and software driver optimizations on the LCD and touch controller. Other factors include cable routing, application performance affecting touch responsiveness and unwanted optical interaction between the LCD and the touch sensor as well as ESD. Designers often underestimate the amount of effort required to integrate the hardware and software components into a cohesive, field-ready product. This results in deployment delays, budget overruns and even cancelled projects. Ensure adequate graphics and processing horsepower: A powerful multitouch interface can consume a significant amount of processor cycles. It is important to understand where processing takes place—in the multi-touch screen controller’s CPU, the host CPU or the host GPU? Without adequate processing horsepower in the right places to run an advanced user interface effectively and without latency, designing the system is pointless. Choose the best display: Selecting the optimal display to integrate into a multi-touch device can be especially difficult due to the numerous dependencies between the display and the touch sensor. Among the factors to consider are RF-EMI interference issues between the display and the touch sensor, matching the active area and viewing angles, minimizing optical losses and bonding/sealing the display and touch sensors properly. Correctly integrate the sensor: Most multi-touch sensors are made of glass, which has many benefits, but can also have drawbacks. The touch sensor must be integrated correctly to prevent breakage in the event of mechanical stresses. Slight deflections of the sensor could also interfere with the sensing baseline. Dust or other contamination must be kept from interfering with viewing quality, and ESD prevented from damaging the sensor or system. Focus on industrial as well as interface design: By definition, multi-touch devices are intended to be highly interactive with the user. High-quality ergonomics, usability and intuitiveness are critical. This is important for both the GUI design

as well as the physical design. For example, if the device is portable, designers must consider how the user will hold it and ensure there is either adequate room for the user to grip the device without touching the screen or build in grip suppression. Optimize the touch software: There are many software layers involved in translating the motion of a finger or fingers on the multi-touch screen into a responsive action on the LCD and in the application software. The firmware running on the multi-touch controller, the touch and display drivers running in the OS and the application software itself must all be tested and optimized for responsiveness. Any lags in this software stack will result in a sub-optimal user experience. Create a great GUI: That a multitouch interface should include a great GUI seems obvious, but many designers fail to devote adequate attention to this. The interface should be much more than just a series of virtual buttons. It should reflect how the designer anticipates the user will interact with the product and facilitate that interaction. To maximize the effectiveness of multi-touch systems, designers must clearly identify specific objectives and performance characteristics for the system. In a retail POS system, “effectiveness” might be measured as the incremental revenue and product volume uplift the system generates; while in an industrial environment, effectiveness is more likely focused on improving worker productivity and reducing inventory errors. Careful thought and planning to the interface will help ensure that designers maximize the investment in the system by providing a high-quality user experience. Being in touch with the user’s needs and the operator’s objectives for the user will help ensure an optimal multi-touch return on investment. Resources are available for designers building multi-touch into their products for the first time, as well as for those experienced with multi-touch, but eager to incorporate the newest designs and feature sets. Touch Revolution Redwood City, CA. (415) 655-4940. [].

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User Interface Design for Small Systems

Keeping up with Embedded Development—The New User Interface With the ubiquity of touch screens, user interfaces have become much more than just a control panel for an embedded device—they are a new way of interacting with technology, and even more, a defining element of a company’s brand experience. by Jason Clarke, Crank Software


rom medical devices to in-car infotainment touch screens, consumers now rely on and expect the ease and convenience of intelligent embedded systems. As a result, embedded designers must transform embedded technology by incorporating new, cutting-edge user interfaces to compete and win in the marketplace. The next wave of successnies providing now demands streamlined, inful solutions electronics ion into products, technologies and companies. Whether your goal is to research the latest tuitive and easy-to-operate user interfaces ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you that leverage the latest touch technology you require for whatever type of technology, Figure 1 hardware interfaces—without slowand productsand you are searching for. ing the development process or increasing Traditionally, a user interface was required only to be functional. Products that previously had only rudimentary user interfaces like this household thermostat costs of goods. now require screens similar to smartphones just to be accepted in the market. To develop appealing and functional interfaces that will get their products recognized quickly, organizations must shift the product, technology and brand. Sec- order to easily evaluate the interface and their current thinking and typical prac- ond, and perhaps most critical, companies make changes to it before the product is tices. First, embedded developers have to have to change their internal processes complete. This embedded design evolution understand and define the user interface and tools, integrating graphic designers that will appeal to their audience and al- into the product development process to highlights the need for a new approach low the user to experience the fullness of create and refine the user interface as em- that puts user interface development as a bedded software developers focus on the priority alongside system functionality. system. Lastly, graphic designers must be Engineers and graphic designers need Get Connected able to quickly deploy and test a user in- new tools to develop user interfaces for with companies mentioned in this article. terface during the development process in their embedded devices and ultimately

End of Article



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Tech In Systems

Figure 2 In a better solution, graphic designers would be part of the engineering process, able to seamlessly integrate design files into user interface development.

help organizations to understand the new user interface and to adapt teams and processes to be integrated and efficient. They must also be able to quickly prototype and test user interfaces that will steer an end product’s marketability.

Understanding the New User Interface

Consumer devices like Apple’s iPhone are driving customer expectations to new heights, and the demand for an intuitive, aesthetically pleasing, easy-to-use interface for embedded devices will only continue to increase as more consumers adopt devices like smartphones into their daily lives. In a report last February, Forrester predicted there would be 1 billion smartphones in the hands of consumers by 2016. Pervasive consumer smartphones lead to a strong desire for rich interactive displays, and the ever-decreasing price of LCD and touch screens allows this desire to become reality. Adding an LCD and new user interface to an embedded device is an effective technique to re-brand older product lines or differentiate a new product when it enters an existing market. A product’s user interface is more than just a set of assorted images on a screen. A product has an operational flow associated with it that is the sum of the



Figure 3 New technology now allows designers to prototype devices and deploy them onto common handheld embedded targets like smartphones to see how the interface actually looks and feels in the hands of a consumer.

graphical interface, the presentation of the data, and the methods by which the user interacts with the system. The heart of the user experience is not just the technology inside the embedded device, but the way it is graphically presented to the user (Figure 1). While it must be intuitive, the user interface is not a single piece of software that an engineer can easily write a specification for and implement. The user interface has a look, and more importantly a feel that creates the entire user experience. It takes time to be tested and iterated. Embedded device developers need a system that ties graphic designers directly into the tools that the engineers are using, so that graphic designers are no longer left out of the product development process.

Adapting Teams and Processes to Integrate the User Interface

Internal graphic design and engineering teams must be streamlined and efficient in order to get quality products to market quickly. Product development can slow as different groups face unique challenges with the user interface. For example, graphic designers may have concerns about usability, interface con-

sistency, graphics quality and overall user experience while the embedded developer’s concerns tend to focus on processor usage, memory footprint, code architecture, maintainability and reuse. Disparate teams and the lack of an integrated process thwart the development process and compromise the product’s ultimate appeal. Embedded system developers and user interface designers are often disconnected, working in parallel silos. With a traditional handoff process, graphic designers draw screens, hand them off to engineers, and don’t see the screens they designed until the final product is ready to be released. Often, the engineer encounters challenges and solves them by changing the user interface, compromising its look and feel. At this point, the user interface designer makes changes to remedy the problems. Though necessary for the product to ultimately succeed, the results are extremely costly and involve time-consuming, back-and-forth changes. In a process with an equally negative result, user interface designers use desktop solutions that the designers are familiar with to design their user interface, and try to force-fit the solution

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into a resource-constrained device. This approach offers an appealing workflow for the designers, but embedded device developers lose the user experience when the resource-intensive solution requires more power than what’s offered by the embedded target created by the embedded developer. The result is a slow, frustrating user interface for the consumer. Ideally, graphic designers could use the tools they are familiar with, such as Photoshop and Blender, and have a process that integrates easily into the embedded development cycle. Designers could create static content with familiar tools, easily add animations to tie content together, simulate the final product, and involve the embedded developers in the whole process. In this case, designers could use a set of tools that not only expose the changes of user interface-specific elements in a visual manner, but also integrate with the main collaboration hub of the embedded development life cycle, the source code repository (Figure 2). Using tools that can expose each change of the user interface at a level that is easily understandable to any stakeholder allows graphic designers and embedded developers to work in parallel. Stakeholders that fully collaborate achieve early discovery of issues in user interface behavior, shorten product development times and improve user experience in the final product. Constant communication with open platforms and full collaboration turns a traditionally long feedback cycle into an interactive and onthe-fly one, without slowing or hindering product development. Embedded developers and graphic designers must seek an approach where each can work in an environment that they find familiar, use the tools that they are comfortable with (like Photoshop or a model-view-controller paradigm) and make them most effective. Organizations should foster a collaborative development process so that graphic designers create the user interface in parallel with the embedded device. The ability to merge content, display changes and resolve conflicts is a key aspect of successful distributed software development teams.

Prototyping and Testing the User Interface

Quickly deploying and testing is at the core of a successful user interface. However, because of the traditionally fragmented processes described earlier, designers often wait until the embedded device is complete to begin working on and testing their interface, because earlier testing reveals incompatibilities as engineers modify and enhance the device during development. To get products to market quickly, graphic designers need a reasonable, quick way to test their user interfaces during the development process. They need to develop and test the prototype product before final hardware and OS have been created. To facilitate this process, designers need new functionality like the ability to prototype transitions between Photoshop screens and see how they would look on a deployed embedded target without waiting months for new code. Using common embedded targets, graphic designers can get an accurate idea of the look and feel of their user interface (Figure 3). They also can experience the amount of time it takes to load screens or have icons respond to touch. Designers often overlook these variants when interfaces are only deployed to desktop CPUs, with enough RAM that interfaces run deceptively smoothly during the testing phase, and then extremely slowly on the final embedded target. Issues such as incorrect image color depth or the use of extraneous alpha channels can have a significant performance effect on systems where computing resources are already being stretched. With the ability to prototype easily, graphic designers can troubleshoot almost all challenges immediately, even before the embedded device they’re working on is complete. Graphic designers and embedded developers must seek a system that will prototype easily. They need the ability to highlight design errors specific to the performance and operation of the user interface in the embedded environment early in the design cycle to adjust the design accordingly. In addition to generating warnings about performance-impacting design decisions, the system should allow rapid and scriptable deployment of a user

interface design to a particular embedded target configuration. Similar in nature to the compilation phase for source code, this will provide a platform-optimized (CPU, OS, render and display configuration) solution using the same input design elements.

Finding a System to Create Your New User Interface

By understanding the importance of the new user interface, aligning teams and communicating properly, and integrating accurate and useful user interface prototypes into the design process, embedded device developers can create industryleading user interfaces and still get their products to market first. Embedded developers and graphic designers must seek one platform for the entire user interface process—from prototype through development to deployment. Designers should be able to create a true user experience. They need to move quickly, by importing assets directly from Photoshop and creating complete application user interfaces without having to develop the code behind them, and prototype to common handheld devices to check for accuracy at any time. One of these tools, Crank Storyboard Suite, provides a user interface environment that empowers graphic designers to create innovative user interfaces and participate actively in product development. The software helps graphic designers align their involvement with the rest of a product’s software development team. Designers can use the software to easily prototype and deploy their interfaces to the Android platform, allowing them to immediately see the way their designs will look and feel to an end user, and quickly make adaptations, resulting in products that have a refined, effective, appealing user interface that enhances a product. Crank Software Ottawa, Ont. (613) 595-1999. [].



technology deployed Embedded Technologies for the Smart Grid

SoCs Driving Higher Levels of Integration in Smart Appliances Ubiquitous connectivity is being realized from handheld communication devices to smart appliances within our homes and working environments. IC manufacturers are driving advances in semiconductor processes and integration in the form of System-on-Chip (SoC) platforms. by Rufino Olay and Reghu Rajan, Microsemi


n recent years, SoCs have increased in complexity from purely analog or digital devices to mixed signal ICs that can be field upgraded to adjust to evolving communication protocols or regional deployment requirements. The next evolution of the SoC is to include an RF subsystem onto the mixed signal controller IC platform while ensuring shrinking power consumption budgets are met. Energy harvesting methods ensure that remote or self-powered devices are capable of increasing the duration of operation in low-power modes.

Designing for an Evolving Smart Grid

The term “smart” is increasingly used to describe an intelligent bi-directional communication between our community, environment and products. For example, an electric, water or natural gas smart meter is but one component of a smart grid system providing numerous functions such as: • Accurate real-time load data • Secure two-way communication to a host network or the Internet • Ability to connect/disconnect nonessential loads dependent on preset parameters or user feedback • Rugged, reliable, low-power operation



With the increased functionality and capability of smartphones, consumers are becoming more comfortable with monitoring and controlling greater aspects of their lives. The rise of smart appliances is a natural extension of the control that consumers are demanding to not only make their lives easier by allowing them to accomplish more with their precious time, but to also control their financial expenditures. Simple push-to-start or timer-based systems are evolving into sophisticated controller-based systems with high levels of connectivity. Energy consumption can be monitored and usage adjusted to align with more favorable time-varying pricing. As a result, appliance manufacturers will have to invest in telecommunications and software development utilizing platforms that allow them to quickly get to market while providing a flexible path for upgradability due to evolving communication protocols. With this in mind, companies must carefully approach the design of their smart appliances from an architectural level in order to take into account current and future requirements. Semiconductor advances in the form of smaller process geometries and packaging technologies coupled with mixed signal capabilities, higher reliability and decreased power

consumption are giving engineers more flexibility to realize their designs.

Putting the “Smarts” into Next Generation Appliances

Mixed signal SoCs are progressively becoming the platform of choice for complex system design and provide a single system development platform for both the software and hardware engineering teams. Figure 1 shows the major subsections of a non-volatile flash process based intelligent mixed signal SoC, which includes an embedded ARM Cortex-M3 microcontroller, programmable analog and FPGA logic fabric. The combination of a standard MCU and programmable logic with the FPGA provides the ability to tackle system-level algorithms such as power management, communication interfaces, encryption for data security and more. Numerous analyses can be performed on load monitoring data such as power factor and harmonic content. Algorithms such as Fast Fourier Transform (FFT) can be cycle intensive and therefore implementation within the FPGA fabric is recommended to free up the Cortex-M3 microcontroller for other high-level system tasks. In general, partitioning the computationally intensive algorithms into the FPGA fabric allows for parallel processing techniques that historically have been suitable for FPGA implementation, which reduces cycle times and power requirements.

Secure and Low Power Connectivity

In smart appliances, connectivity is an integral function. Unfortunately, no single communication protocol has yet been widely standardized, thus the ability to customize to regional and market needs is key. Multi-protocol support can be realized with different RF front ends or TCP/IP. To save space, protocol stacks can be stored in memory and loaded into the CortexM3 microprocessor during initial set-up or field upgraded in the field as necessary. Data integrity and security are of utmost importance in a two-way communication system. Of first consideration is the hardware. During initialization, the

Technology deployed

Supervisor PLL




32 KHz



+ 3V






ARM Cortex - M3


Microcontroller Subsystem Programmable Analog FPGA Fabric













AHB Bus Matrix UART_0




SCB Temp. Mon.

Volt Mon. (ABPS)

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10/100 EMAC

Analog Compute Engine ADC

Sample Sequencing Engine


Versa Tiles

SCB Temp. Mon.

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Post Processing Engine




Figure 1 Mixed Signal SoC Platform.

configuration data must be stored onchip to avoid unauthorized access to the boot-code. This makes it virtually impossible to steal the configuration data as compared to external memory bit stream interception. Secondly, an Advanced Encryption Standard (AES) of at least 128bit cryptographic keys provides another layer of protection. Short-range sensor networks are widely used today for wireless communication in factories, industrial complexes, commercial and residential buildings, agricultural settings and urban areas, where they improve manufacturing efficiency, safety, reliability, automation and security. They can be used in ambient/environmental monitoring, building automation and security, access control, structural health monitoring, tire pressure monitoring systems, tank level monitoring, wireless cold chain tracking for pharmaceutical shipments, and flexible smart cards for embedded autonomous sensors, to men-

tion a few. Until recently, almost all sensor networks have used costly wired data communications and power connections. Moving to wireless protocols eliminates the data communications wiring, but still requires power sources. Batteries provide an alternative, but replacing them when they wear out can be expensive, especially when sensors are installed behind walls or in other similarly unreachable locations. An important component to an ultralow-power Wireless Sensor Network (WSN) is efficient energy storage and management. Micro-power batteries, such as thin-film batteries, have greatly advanced in technology in recent years along with micro-power management solutions. Advances in ULP technology have replaced the need for AA or AAA batteries to much lower battery capacities and sizes. Hence small, flexible and â&#x20AC;&#x153;smartâ&#x20AC;? wireless sensors with long battery life are a reality. A new class of wireless sensors powered by harvested energy that does not

need battery replacement is the latest in WSN technology for sensing and monitoring hard-to-reach environments and applications where energy can be harvested. Wireless sensors working on harvested energy have a set of needs that are more stringent than regular wireless sensors, such as low peak power, ultra-low standby current etc., apart from general low power consumption. This is a relatively new field within WSN and has wide-spread applications including medical, M2M, military and other research areas. The technology and design considerations on the short-range radio transceiver play a key role in efficiency of such low power wireless sensors. The requirements on the transceiver to fit applications mentioned above can be categorized as shown in Figure 2. The power supply requirement of the transceiver is a key factor in the wireless sensor design and application. Since most ULP sensors run from tiny batteries and energy harvesting sources, sub 2V supply RTC MAGAZINE JUNE 2012


technology deployed

Peak & Average Current


Supply Voltage

Streaming Capability


Figure 2 Requirements for an ultra-low power radio transceiver.

Pressure gauge Temperature etc...

Microcontroller / DSP RF Tx / Rx



Bias Gen

Xtal Osc & Clk Gen








Switch, Motor, Valve, etc...



USB controller


Figure 3 Control & RF subsystem for smart appliances.


Application Link Layer

24.576 MHz




Antenna Impedance


Link Frequency

This constraint is even more important for wireless sensors that run from harvested energy sources. Often energy harvester transducers have higher output impedance than batteries. The micropower management layer between the transducer and the sensor converts the supply characteristics including source impedance. Therefore, the low peak current consumption in the radio transceiver reduces constraints on the power supply of the wireless sensor. For a radio transmitter, the power consumption of the PA can be very large. Many 802.15.4 or Bluetooth radios consume 25-40 mW for a 25-meter free-space range, wasting over 95 percent of it. The principal parameter from a transmitter PA point of view comes from the receiver. Its sensitivity defines, for a given range, how much power must be radiated. Most radios fall into the -85 dBm to -95 dBm sensitivity range, resulting in a factor 10 in PA power consumption. The three main factors impacting power consumption are receiver sensitivity, carrier frequency and output impedance. They are additive, and together can represent over two orders of magnitude in PA power consumption variation for an identical range. The choice of carrier frequency is also an important parameter for the transceiver. The two available options within industrial, scientific and medical (ISM) radio bands are 2.4 GHz or sub-GHz frequencies. Some of the factors to consider with this choice are: â&#x20AC;˘ Range â&#x20AC;˘ Power consumption


Network Protocol

Radios consume certain current when in transmit or receive operation. In real wireless networks radios seldom operate continuously, instead they operate in small time slots to save power and to not use up the radio spectrum. This is called duty-cycling and results in times when a radio consumes little or no power and other times when a radio is operating and consumes significant current. The absolute value of current when a radio is operating is the peak current and these instantaneous currents are often much higher than the reported average current of the system due to time-averaging. Radios that have high peak currents (even though average currents might be lower) can impose constraints on power management circuits, especially in applications that use harvested energy. Hence radios with low peak currents are desirable.


voltages are highly desired as most sensors run out of a single cell depending on battery chemistry. Radio transceivers that work down to 1.1V give additional flexibility to sensor design and reduce power management constraints. The supply voltage, power amplifier (PA) energy consumption (at comparable range) and link data rate are often ignored when comparing different solutions. However, all three have a substantial impact. A radio operating at 2.5V consumes twice as much power as a radio with the same current consumption but operating at 1.25V. Operating at higher voltage is only required when output power in excess of 5 dBm is needed. This is not the case for short-range applications, as output power is rarely over 0 dBm. Low supply voltage is an easy way to reduce power consumption at the system level, but it requires an RF IC designed for low voltage operation.

Technology deployed • Data rates • Antenna size • Interoperability (standards) • Worldwide deployment Wi-Fi, Bluetooth and ZigBee technologies are heavily marketed 2.4 GHz protocols used extensively in today’s markets. However, for low power and lower data rate applications, such as wireless sensors, wireless medical monitoring, home security/automation and smart appliances/ metering, sub-GHz wireless systems offer several advantages, including longer range for given power, reduced power consumption and lower deployment and operating costs. Therefore sub-GHz carrier frequencies have certain advantages over 2.4 GHz in terms of range and signal quality. As radio waves pass through walls and other obstacles, the signal weakens. Attenuation rates increase at higher frequencies, therefore the 2.4 GHz signal weakens faster than a sub-GHz signal. 2.4 GHz radio waves also fade more quickly than subGHz waves as they reflect off dense surfaces. In highly congested environments, the 2.4 GHz transmission can weaken rapidly, which adversely affects signal quality. Even though radio waves travel in a straight line, they do bend when they hit a solid edge like the corner of a building for example. As frequencies decrease the angle of diffraction increases, allowing sub-GHz signals to bend farther around an obstacle, reducing the blocking effect. The Friis Equation demonstrates the superior propagation characteristics of a sub-GHz radio, showing that path loss at 2.4 GHz is 8.5 dB higher than at 900 MHz. This translates into 2.67x longer range for a 900 MHz radio since range approximately doubles with every 6 dB increase in power. To match the range of a 900 MHz radio, a 2.4 GHz solution would need greater than 8.5 dB additional power. Besides the need for higher power for the same link budget, the 2.4 GHz band has higher chances of interference. The airways are crowded with colliding 2.4 GHz signals from various sources, such as home and office Wi-Fi hubs, Bluetoothenabled computer and cell phone peripherals and microwave ovens. This traffic jam of 2.4 GHz signals creates a lot of interference. Sub-GHz ISM bands are mostly used for proprietary low-duty-cycle links

and are not as likely to interfere with each other. The quieter spectrum means easier transmissions and fewer retries, which is more efficient and saves battery power. Figure 3 shows an example of an architecture used for a smart appliance based on a ULP wireless sensor for connectivity where power consumption is critical. Semiconductor advances are allowing designers to deploy increasing amounts of control and connectivity options. The trend toward further field up-

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gradable SoC platforms with integrated RF subsystems provides hardware and software architects a platform on which to co-develop system features and algorithms necessary to support the process of developing highly intelligent smart appliance and smart grid products. Microsemi Aliso Viejo, CA. (949) 380-6100. [].


6/7/12 3:54 PM RTC MAGAZINE JUNE 2012

technology deployed Embedded Technologies for the Smart Grid

Key Considerations for Designing Low Cost, Energy Efficient Smart Grid Devices by Srinath Balaraman, Mentor Graphics


ur society’s ever-demanding energy needs have not only led to an increased investment in alternative renewable sources, but have also forced us to look at ways to effectively manage our current energy consumption. One way to accomplish this is by upgrading the aging energy grid to become more efficient through the use of sophisticated technology. As more energy becomes available from alternative renewable sources and as the proliferation of technology makes devices on the grid inherently smarter and more efficient, the aging grid must be upgraded to accommodate these changes. To do so, the electricity distribution infrastructure must be able to manage congestion and offset peak load demands in a smart, efficient and effective way by soliciting consumer participation through the use of “smart” devices. Self-sufficiency in meeting new energy demands is a major motivation for governments throughout the world. This motivation compels agencies—NIST in the United States and CEN, CENELEC and ETSI in Europe—to drive standards that aim at turning their countries’ electrical grids into a “Smart Grid.” These new standards will eventually require compliance from all smart devices that attach to the Smart Grid, and in the process, introduce new challenges for device manufacturers to come up with innovative compli-



ant designs that have very little impact on cost to customers. In the past, due to a lack of widely adopted standards, the functional requirements for a so-called smart device on the grid were often quite simple. This lack of standardization led to both hardware and software designs that lacked sophistication. These devices traditionally focused on isolated functionalities like metering, monitoring, or reporting usage data without contributing to the grid’s intelligence. For example, power meters would collect usage data and the only action taken on that data was to calculate the power bill based on the number of units consumed. If instead, that data was used to trend the consumer’s usage pattern and subsequently the consumer automatically received recommended steps or actions that would help reduce usage, the meter would have contributed to the reduction in the consumption of energy and would have made the energy grid “smarter.”

The Smart Grid challenge

Devices on the grid today follow either very fragmented sets of standards or no standards at all. Standardization of functionality would enable these devices to add much needed value by adding more capacity and contributing to the overall goal of maximum grid efficiency (Figure 1). This is where the emerging Smart En-

ergy Profile (SEP) standards proposed by the ZigBee Alliance and the HomePlug Alliance come into play. The new SEP 2.0 Specification defines technology standards for devices that enable consumer participation and align with the utility company’s goal of effective smart energy management and distribution. The SEP standard defines a variety of “Function Sets” that specify the functionality expected from a SEP-compliant device—or a “Smart Grid” device. There are a collection of behaviors that comprise each function set. Every device must implement a common/base function set as described in the SEP 2.0 Application Protocol Specification in order to be classified as a Smart Grid device, and then depending on the device’s expected behavior, more of these function sets can be included on top of the common/base set. A SEP-compliant device should also be inherently power efficient, support high availability (always-ON and connected), provide real-time responsiveness (to achieve grid efficiency) and must include feature-rich networking support, including IPv6, TLS, HTTP, Wireless connectivity, etc. To meet networking requirements, SEP requires the use of TCP/IP as the underlying communication protocol and specifies the use of IPv6 to eliminate the problem of a limited address space while providing for interoperability and mobility. Due to its expected proliferation into a multitude of consumer devices, SEP requires support for commonly adopted application layer protocols like HyperText Transfer Protocol (HTTP) and REpresentational State Transfer (REST). To facilitate time synchronization for device management and logging, SEP specifies the use of the Network Time Protocol (NTP). In addition to all of these requirements, one of the most important—and the most worrisome—aspect that accompanies these requirements is the vast exposure of the energy grid to attacks via the Internet. Such attacks could have catastrophic repercussions. This vulnerability necessitates the need for securing all of the devices on the grid with capable se-

Technology deployed


USB Ethernet ZigBee





Smart Meter

Figure 1

Bluetooth Connection

Home Network

Energy Co.

In a typical Smart home, devices such as a washing machine, an in-home display and a power meter can all work together in tandemâ&#x20AC;&#x201D;to make the grid smarter.

curity and cryptographic algorithms. SEP specifies the use of IPSec, SSL or TLS depending on the function set and the layer at which security is desired. SEP is designed to work over any link layer technology. So, depending on the application, Ethernet, Wi-Fi, ZigBee, PPP, Bluetooth, etc. are all possible technologies (Figure 2). Besides wired and wireless connections for network communications, several service oriented tasks like firmware download/upgrades, security certificate updates, running diagnostics etc. require a direct connection. For this purpose, SEP also specifies the use of direct connection methods like USB and serial. This expansive set of requirements adds to the challenges device manufacturers will have to address. Foremost, device manufacturers must select a hardware design that supports achieving this level

of functionalityâ&#x20AC;&#x201D;with little to no cost increase to the end-user. Consumers will not be exposed to most of the underlying functionality, so paying more for their appliance so it can plug into the Smart Grid is hard to justify. After selecting the suitable hardware, a software architecture is also required that meets these requirements and supports execution in a low-cost hardware design. The following sections explore both the hardware and software sides of these challenges.

Choosing Low Cost Hardware

A device must comply with the SEP specifications and provide the required functionality to be classified as a Smart Grid device. Furthermore, all of this functionality needs to be supported in a low-cost hardware solution. Considering the device functionality, power require-

ments and the available silicon, 32-bit MCUs are the best suited hardware for such a device. Most 32-bit MCUs offer enough memory and processing power to deliver the performance necessary to meet the requirements outlined in the SEP specification. They can support all the peripherals necessary in a Smart Grid device like Graphical User Interfaces (GUIs), Ethernet, UARTs, USB, Bluetooth, ZigBee and Wi-Fi. Such MCUs also provide realtime clocks for time tracking, SPI and I2C buses for device communications, and support operating at different power levels. Furthermore, these system-on-chips (SoCs) contain up to 1 Mbyte of on-chip flash memory and a maximum of 192 Kbytes of on-chip SRAM. The following are some examples of the MCUs currently available in the market that are a good fit RTC MAGAZINE JUNE 2012


technology deployed

for various types of Smart Grid devices: â&#x20AC;˘ ARM-Cortex-M processor family: â&#x20AC;˘ Texas Instruments Stellaris Family â&#x20AC;˘ STMicroelectronics STM32 Family â&#x20AC;˘ Freescale Kinetis Family â&#x20AC;˘ MIPS 14K â&#x20AC;˘ Renesas SH-2 and SH-2A

WiFi I2C Bus ZigBee Bluetooth SPI USB RS 232 IPV6 Ready

S/W Solution


Selecting the Right Software USB Ethernet ZigBee



Bluetooth Hardware Board [~3 Inches] Figure 2

An example of a minimalistic hardware design that can support a wide range of peripherals, and at the same time includes a software solution that can offer all the services required by SEP.

After discussing both the hardware constraints and the functional requirements, it becomes apparent that the software architecture for these devices must be carefully considered. In addition to the SEP functional requirements, these Smart Grid devices should also support extremely fast booting as well as have the ability to easily switch to using battery sources in case of power outages. These requirements necessitate that these devices use less complex yet power-efficient software designs. Limited memory resources also mean that any software that powers these devices must have a small and highly optimized footprint. Three different software architectures that meet these requirements are worthy of evalua-

tion: bare-metal designs, general purpose OS designs and real-time OS designs. One choice is sticking with a proprietary bare-metal system and adding new functionality to the design to meet the SEP requirements. But that will very often turn out to be a huge undertaking of re-inventing the wheelâ&#x20AC;&#x201D;IP stack, security, etc. Besides, the fact is itâ&#x20AC;&#x2122;s extremely difficult to ensure that the underlying implementations are complete, comprehensive and meet all the required standards. In addition to these difficulties, extreme delays in getting the products to market could severely hurt the productâ&#x20AC;&#x2122;s prospect for success. Another option would be to port a freely available, general purpose operating system such as Linux onto the platform of choice and build SEP specification-based applications on top of it. The main problem here is that the platform of choice, as described above (a 32-bit MCU), is heavily constrained both in terms of processor speed and the available on-chip memory, and Linux has somewhat large requirements for both. Besides this key point,

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many of these devices do not require such a heavy weight operating system, making this option a poor choice for most Smart Grid designs. The last option is using a real-time operating system (RTOS), which can provide support for all the sophisticated functionality required by the SEP specification and yet offer a small footprint in addition to being fast, efficient and robust. An RTOS can provide for all of the “must have” capabilities such as: “instant ON” and “stay ON” all the time; real-time responsiveness; a wide range of peripheral support; TCP/IP networking; graphics (GUI) support; and network security, etc. The Nucleus RTOS provided by Mentor Graphics is a good example of one such solution (Figure 3). Nucleus is a widely deployed and scalable RTOS that meets all Smart Grid device requirements. It has both hard, real-time performance and integrated power management services. Such an RTOS can fit in a memory-constrained MCU, yet still provide the large set of functionality required for a Smart Grid device.

As the adoption of the new Smart Grid standards becomes a requirement, designing fully compliant devices that keep the bill of materials (BOM) minimized will become a major challenge for manufacturers. To create a device compliant with the SEP specification, a bare-metal software design is likely not an option due to the high number of functional requirements. On the other extreme, using a general purpose operating system will result in unacceptable cost increases because of the need for increased hardware resources. Device manufacturers need to find the right balance when choosing both the software design and hardware platform. The use of a scalable, power-efficient, real-time operating system with extensive networking support (wired and wireless) along with one of the 32-bit MCUs now available in the market is the closest to meeting all of these requirements. Following this design paradigm, designers will significantly reduce their time-tomarket and still realize all of their Smart Grid application goals.

Application Smart Energy Profile (SEP) API Real Time Kernel

Power Manager


(fully featured)


NUCLEUS Board Support Package Microcontroller (MCU) Figure 3 A diagram depicting how the software stack of a SEPcompliant Smart Grid device might look like on a low-cost microcontroller. Mentor Graphics Wilsonville, OR. (503) 685-7000. [].

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Safe and Secure Systems

Industrial Computers in SafetyCritical Applications: Out of the Ordinary In safety-critical environments, requirements go well beyond the usual demands. As safety increasingly becomes an issue in computing in more and more areas, costs don’t have to explode. There are COTS solutions for CompactPCI and VMEbus. by Susanne Bornschlegl, MEN Mikro Elektronik


herever you go these days, chances are you have to put your faith in some type of electronic system that is controlling all kinds of equipment and amenities in our lives, and the service provider is expected to take care of the necessary safety precautions. Systems like these are subject to many stringent, safetyrelated and market-specific standards, as found in the railway and avionics markets. The subconscious (or blind eye) trust that people put into these systems to operate reliably is quite large, especially when their safety depends on proper system operation. This is of course a bit unnerving, so the obvious question is: what types of computers do system integrators typically employ? Certainly not just “ordinary,” commercial offthe-shelf industrial computers, when safetycritical systems are involved. Manufacturers have been developing industrial SBCs on two tried and tested standard platforms, CompactPCI and VME, that are certifiably safe and yet COTS-based. Of course, these two platforms are far from ordinary (Figure 1).

Safety as the Standard

Any reasonable design for safety-



critical applications uses a set of common techniques to achieve the high reliability that is demanded. One of the key items is redundancy. A system component that, in the event of a failure, will stop the entire system from working is called a single point of failure (SPOF). In the worst case, such a failure could cause great damage and endanger human life. This is why critical components are always incorporated several times, increasing system redundancy. Being identical, these components can keep the system in an operational state, even if one fails, or put the system into a safe state. Systems that are “fail-operational” continue to operate when an error occurs, such as in the control system of an airplane. “Fail-safe” systems are turned off in case of a failure; they are immediately put into a safe state. For these scenarios, there are different types of redundancy setups, from “1-out-of-2” (1oo2) systems up to “2-outof-4” (2oo4) systems. A “voter” mechanism in the redundant structure compares and evaluates the output of each component. Depending on the redundancy type, the system then reacts in a defined way.

Redundant Architecture

In a 2-out-of-3 system with three identical CPU cards based on CompactPCI, for example, the voter compares the results and the majority of the circuits with a matching output to determine the outcome used to control the system. Building up this type of redundancy using COTS components in a standard bus system seems to be a cost-efficient way to do it, but only if the complex software requirements and specialized I/O necessary to synchronize the three systems and implement the voter are addressed (Figure 2). There are currently CompactPCI and VME CPU boards that come with onboard triple redundancy, called a lockstep architecture, where the identical components work synchronously and always do the same thing, making them virtually visible only once for the software. The same software can be used as for a single-CPU board, facilitating software integration, keeping overhead low and reducing development costs. In case of failures, simple code is sufficient to synchronize the three processors. And for upgrades of existing systems based

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The input ranges are 0-5V, Âą5V, 0-10V and Âą10 volts. The board will support up to 16 single-ended or 8 differential channels or various combinations of both. Eight independent, 12-bit D/A converters are also on the board. The output voltage ranges

are 0-5V, 0-10V, ¹5V, and ¹10V. The PCM-MIO-G has 48 lines of digital I/O programmable for input, output, or output with read-back. The lines are TTL-compatible and can sink 12 mA. The board will operate from -40° to +85°C. WinSystems, Inc. (817) 274-7553

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The power supplies have no minimum load requirement to bring the units into regulation. All the outputs have overvoltage and short circuit protection plus overcurrent protection as well. LED indicators display a visual status of each regulated output. Both versions will operate from -40° to +85°C with no fans or heat sinks and are well suited for applications including pipelines, transportation, communications, solar power, and military. WinSystems also offers the PPM-DC-ATX which is a PC/104-Plus DC/DC supply that generates 5 regulated voltages plus supports the software controlled shutdown and power monitoring for SBCs with advance CPU chipsets employing sleep modes and active power management. WinSystems, Inc. (817) 274-7553


components, as commonly used in aerospace, an FPGA protects the design from obsolescence and is a smart way to lower overall costs in the long run. This is particularly true where complex functions like Avionics Full Duplex Ethernet (AFDX) are needed. To harden the FPGA component, design tools can turn its internal memory structure triple redundant as well, making it virtually immune to cosmic radiation.

Safety Relies on Data Execution

Figure 1 Safety-critical applications can employ cost-effective COTS components that have met the certifications of relevant industry-specific standards.










Bumps on the Road to Redundancy

2oo3 Voter

Figure 2 A 2-out-of-3 voting arrangement uses a “majority-rule” voting approach to ensure continued operation in the event of an error from any one of these three redundant circuits.

on a single-CPU solution, it takes less effort to port existing, dedicated applications. A 2oo3 design also tolerates hardware faults and transients. A typical problem experienced in avionics applications is a single event or multiple event upset (SEU or MEU). These random events can be caused by a single bit being “flipped” through the effects of cosmic radiation. A single processor or memory bank is very susceptible to single event upsets. The triple-redundant dynamic memory found in 2oo3 systems automatically



Next to being fault-tolerant, safetycritical systems often require predictable execution times. The system must react to an external event within a defined time, and this reaction time must even be met under worst case conditions. Systems need to avoid interrupts and DMA to assure strictly deterministic operation because they could compromise the system reaction time. Additional diagnosis mechanisms within the system can help detect latent errors before they lead to a system error. They include extensive built-in test equipment (BITE) features such as ECC error correction or monitoring of all internal voltages, further increasing safety and availability.

corrects such upsets. Reading and writing is always performed on all memory banks and a “scrubbing” mechanism reads out one memory cell through the voter and writes back the voted data into all three memory banks. This happens for every refresh cycle and prevents accumulation of flipped bits over time. Critical functions such as the voter and memory management functions can be implemented in an onboard FPGA. Contrary to specially developed, expensive

Still, one obstacle seems to block the way when developing a redundant system for critical applications: Because redundant subsystems are identical, there is the possibility for multiplied, parallel failures. Applicable industry standards, such as DO-254 for avionics and EN 50129 for railways, demand that there must be dissimilarities inside the system architecture. Employing boards that incorporate a resource partitioning MMU is one effective means of mitigating this pitfall. Independently developed, dissimilar applications can run on two partitions, and different I/O hardware can be used. These two dissimilar hardware/ software paths have to lead to the same result for a specific action to take place. The last stepping stone in developing safety-critical systems is the operating system. Luckily, several platforms specifically target safety-critical applications. Sysgo’s PikeOS and various flavors of Wind River’s VxWorks are available. In addition to its general-purpose realtime operating system (RTOS), Wind


Figure 3 SBCs can come with triple redundancy built into one board to save integration costs and system space.

River also supplies VxWorks platforms that support safety certifications up to DAL-A as defined by RTCA DO-254 and RTCA DO-178B (avionics), and to SIL 4 defined by EN 50129 (railways). PikeOS or VxWorks support resource partitioning mentioned above. CPU cards with optimized booting characteristics will enable significant application startup times, so that applications can operate immediately after power on and provide a quick restart in case of power interruptions, a critical function in safety-critical environments. Two triple-redundant cards (Figure 3) can be combined to form a high-availability (HA) cluster to make a system even more failure-safe. In a constellation like this, each channel operates on its own, but only one channel is active. If the active channel fails, the system automatically switches over to the second channel.

Redundant SBCs for Safe Operation

Only a qualified SBC can be effectively employed in safety-critical applications, such as in aircraft communication, navigation or display control, infotainment, flight control, weather systems, collision avoidance or other management systems. On the ground, airport-related infrastructures also need safety: communications, security systems, traffic control or radar systems also play mission-critical parts in air traffic. Similarly, SBCs used in systems found on board a train or other vehicle as well as for wayside control in the various systems involved in railway

traffic, also need these exceptional levels of reliability and redundancy. Apart from the two classic areas of railways and avionics, there are many other interesting fields where industrial, and at the same time safe computers may be needed. In general, this includes markets where failures may lead to high costs: commerce, logistics, production, the medical industry and server or telecommunication infrastructure.

In a world of ever increasing dependence on computer infrastructure, failuresafe operation has become an important asset. The â&#x20AC;&#x153;ordinaryâ&#x20AC;? industrial computer may not be able to live up to the high demands emerging from this. MEN Micro Ambler, PA. (215) 542-9575. [].



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6/6/12 3:52 PM RTC MAGAZINE JUNE 2012

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TECHNOLOGY Master API Package for the Development of CANopen A solution for a quick and easy development of PC-based CANopen control test and service applications is now available and runs under Microsoft Windows. Along with the active CAN interfaces, CANopen Master API V6 from IXXAT Automation supports IXXAT’s low-priced passive interfaces. The new API can operate up to 12 CAN interfaces in parallel, and depending on the hardware used, up to 4 CAN channels per interface board. New functionality of CANopen Master API V6 includes support for the latest CiA specifications CiA 301 (CANopen application layer and communication profile) version 4.2 and CiA 305 (CANopen layer setting services (LSS) and protocols) version 2.2. An important feature of the most recent CiA 301 specification is the extended CANopen SYNC protocol, which enables the system integrator to avoid temporary message bursts during synchronous operation of large CANopen networks. CiA 305 includes an enhanced search and configuration protocol (LSS Fastscan) simplifying the dynamic allocation of node IDs for CANopen LSS slave devices. Currently, the CANopen Master API programming library is offered for 32 and 64 bit Windows 2000, XP, Vista and Windows 7 systems. In addition to the DLL and a detailed user manual, numerous sample applications for C, C++, C#, Delphi and are included with the delivery. Also included are examples enabling the easy integration of the CANopen Master API in LabVIEW from National Instruments.

AdvancedTCA Chassis Offers 50 Percent More Computing Density A new 6U AdvancedTCA (ATCA) SlotSaver Shelf gains 2 slots of payload card usage, along with AC power. The density, full redundancy and versatile power configuration is suited for telecom, military/aerospace and high-end networking/computing applications. The 6U ATCA SlotSaver PXS0600 chassis from Pixus Technologies features shelf managers that also employ dual redundant switch functionality. An AdvancedTCA horizontal chassis would typically have to dedicate 2 slots for redundant switch cards, thus offering only four payload slots. With the

IXXAT, New Bedford, NH. (603) 471-0800. [].

Energy Measurement Analog Front End Has Two 24-bit ADCs As the global energy-metering infrastructure is being upgraded and the power-monitoring market is growing, designers of energy measurement and other signal acquisition applications are looking for ways to increase performance while lowering costs. Microchip Technology is addressing these needs with accurate analog front ends (AFEs) that reduce power consumption with their low-power modes and reduce costs by decreasing the number of required power rails and external components. MCP3911 Block Diagram A next-generation energy measurement analog front end (AFE) features two 24-bit, delta-sigma ADCs that operate at 3V with industry-leading accuracy of 94.5 dB SINAD and 106.5 dB THD. The MCP3911 provides better energy meter and power monitoring performance by accurately measuring from start-up to maximum current, and enables faster calibration during production. Four different power modes offer the flexibility of enabling either extremely low-power designs, to 0.8 mA per channel, or designs for higher-speed signals and harmonic content. The extended temperature range allows operation from -40° to +125°C. The MCP3911 also features 2.7 to 3.6V analog and digital operation, which simplifies the interface by running off of the same power rail as the microcontroller. An internal, low-temperature-coefficient voltage reference, along with PGAs on each channel, further enables metering and monitoring designs. Pricing ranges from $1.40 to $1.43 each, in 5,000-unit quantities. Microchip also announced a tool that enables development with these new AFEs. The MCP3911 Evaluation Board for 16-bit MCUs ($79.99) is also available today. REFIN/OUT


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PXS0600, the combined switch/shelf manager functionality provides a full 6 payload slots for a 50 percent increase in the computing density. The PXS0600 also features a push-pull cooling configuration for thermal management. All of the field replaceable units (FRUs) are hot-swappable, including the cooling units, washable filters, power entry modules (PEMs), shelf managers and AC power supplies. With 3x AC power supplies in an N+1 configuration, the chassis offers both AC and DC options. In fact, the AC and DC power can be running at the same time for swapping modules in the field, such as a base of operations in military applications. A 5U chassis with DC-only power is also available. The 6-slot ATCA backplane offers a full mesh configuration. The shelf manager offers the integration of 10GbE and 1GbE layer two managed switch on the same module. With two shelf managers in the system there is a full redundancy and failover, both on the switch as well as on the shelf manager. Pricing for the PXS0600 starts under $9,800. depending on configuration. Pixus Technologies, Waterloo, Ontario. (519) 885-5775. [].


6U VXS/VME Sports Third Generation Intel Core Processors A new VXS/VME family of high-performance embedded single board computers features the third generation Intel Core processor from the Intel long life cycle embedded roadmap. The VX 91x/01x from Concurrent Technologies is a 6U VXS/VME single board computer fully compliant with the VITA 41.x standard. Users will benefit from the enhanced processing and graphics performance of the newly released quad-core Intel Core i7-3615QE processor or the quad-core Intel Core i7-3612QE processor. The board provides a feature-rich complement of front and rear I/O interfaces, and is designed to provide a plug and play upgrade path for users of earlier generations of Concurrent Technologies’ 6U VXS/VME products. Applications for the VX 91x/01x are expected in real-time systems and military embedded systems for data acquisition, instrumentation, control systems and signal processing. The 3rd generation Intel Core processors offer enhanced graphic and processing capabilities resulting in an increase of up to 15 percent in CPU performance and an increase of up to 50 percent in graphics performance when compared to previous architectures operating within the same power budget. With support for OpenCL and improved media acceleration, this SBC offers technology for high-end numerical and graphics applications. Supporting up to 16 Gbyte of ECC DDR3 SDRAM, the VX 91x/01x maintains compatibility with the previous generation product (VX 81x/09x) and offers an array of I/O functions: configurable PCI Express fabric interface supporting 1 x8, 2 x4, 1 x4 + 1 x4 at Gen 1 or Gen 2 data rates, dual Gigabit Ethernet, dual SATA600, dual PMC / XMC slots, dual serial RS-232/422/485 ports, 6 USB 2.0 ports, dual independent display ports, onboard CompactFlash and optional 2.5-inch hard drive. The VX 91x/01x is available in three temperature grades: 0° to +55°C (N-Series), -25° to +70°C (E-Series), -40° to +85°C (K-Series); and two ruggedized grades: Ruggedized Conduction-Cooled -40° to +85°C (RC) and Ruggedized Air-Cooled -40° to +75°C (RA). Get Connected with technology and Concurrent Technologies, Woburn, MA. (781) 933 5900. []. companies providing solutions now

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COM Express Type 6 Module with Quad Core, 3rd Generation Core Processors A new COM Express module combines the crucial innovations in the 3rd generation Intel Core processors. The TM77COM Express module from congatec is fitted with the new quad cores, 3rd generation Intel Core i73612QE (4 × 2.1 GHz, 6 Mbyte L2 cache memory, TDP 35W) and Intel Core i7-3615QE (4 × 2.3 GHz, 6 Mbyte L2 cache memory, TDP 45W) processors along with the Mobile Intel HM76 Express chipset, as well as native USB 3.0 support and the fast dual channel DDR3-1600 MHz memory, providing up to 16 Gbytes. The newly integrated Intel HD4000 graphics core is equipped with over 16 execution units, performs up to 50 percent better than its predecessors, and can control up to three displays independently of each other. It also provides Intel Flexible Display Interface (FDI), DirectX 11 OpenGL 3.1 OpenCL 1.1, as well as a high-performance MPEG-2 hardware decoding unit in order to decode multiple high resolution full HD videos in parallel. In addition to VGA and LVDS, it has three digital display interfaces, each of which can be configured for DisplayPort (DP), HDMI or DVI. This ensures a maximum of three independent displays for applications in the medical, automation and gaming industries. With the first native USB 3.0 support for the module, data transfer is considerably faster, energy consumption lower, and now even simultaneous sending and receiving of data is possible. Eight USB ports are provided, three of those are capable of USB 3.0 Superspeed operation. Seven PCI Express 2.0 lanes, PCI Express graphics 3.0 (PEG) × 16 lanes for high-performance external graphics cards, four SATA interfaces with up to 6 Gbyte/s and RAID support, an EIDE and a Gigabit Ethernet interface facilitate fast and flexible system expansions. Fan control, an LPC bus for simple connection of legacy I/O interfaces, and Intel high definition audio round out the comprehensive range of features. The congatec board controller provides an extensive embedded PC feature set. The independent x86 processor makes functions such as system monitoring or the I2C bus faster and more reliable, even if the system is in standby mode. The matching evaluation carrier board for COM Express type 6 is also available, so that all the new features can be tested with ease. Single unit pricing starts at less than $1,000. congatec, San Diego, CA. (858) 457-2600. [].

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Products Curtiss-Wright Controls Defense Solutions, Ashburn, VA. (613) 254-5112. [].

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Third Generation Intel Core i7 Processor Third across Product Line Extreme Engineering Solutions is supporting the 3rd generation Intel Core i7 processor across eight industry-standard form factors: COM Express, 3U VPX, 6U VPX, 3U CompactPCI, 6U CompactPCI, VME, air-cooled PrPMC/XMC and conduction-cooled PrPMC/ XMC. The XPedite7470 3U VPX Single Board Computer (SBC) and XCalibur4401 6U CompactPCI SBC are the first products available from X-ES to support the third generation Intel Core i7 processor. Third generation Intel Core i7 processors provide higher performance and lower power compared to 2nd generation Intel Core i7 processors. Third generation Intel Core i7 processors also include Intel HD Graphics with DirectX 11, supporting OpenGL 3.1 and OpenCL 1.1. Initially, X-ES products are available with these versions of the 3rd generation Intel Core i7 processor: Quad-core Intel Core i7-3615QE, 2.3GHz and Quad-core Intel Core i7-3612QE, 2.1GHz. When dual-core versions of 3rd generation Intel Core i7 processors become available, they will be supported on X-ES products. Because of the lower power consumption of the 3rd generation Intel Core i7 processors, quad-core third generation Intel Core i7 processors are more easily supported in conductioncooled applications. As with all Intel processors used in X-ES designs, the third generation Intel Core i7 processors are on Intel’s embedded roadmap, guaranteeing at least seven years of availability for customers. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

Opto-Isolated Digital I/O Signal Conditioning Boards for Small Form Factor Systems Two new optically isolated signal conditioning and termination boards for OEM computer system designers are targeted at applications requiring signal isolation between an embedded computer and monitoring points. From WinSystems, ISM-TRM-ISO-IN provides 24 lines of optically isolated and digitally debounced inputs to provide easy connections and signal conditioning from field wiring. The ISM-TRM-ISO-OUT provides 24 lines of optically isolated outputs. To interface with field wiring, the boards use a 3.5 mm pitch, industry-standard, pluggable connectors to ensure reliable connection with easy removal and insertion Each input pair of the ISM-TRM-ISO-IN has configuration flexibility to support either an active high or active low signal from 5 to 30 volts. Each input line is optically isolated from the others and from the computer interface circuits. The isolation voltage rating between the input and output of the photocoupler device exceeds 2500V. Then each input line is wired to a contact bounce eliminator. Its purpose is the elimination of extraneous level changes that result when interfacing with mechanical contacts such as switches or relays. This circuit removes bounce on both the “make” and “break” of a contact closure. Each output of the ISM-TRM-ISO-OUT has a NPN Darlington transistor pair with an integral clamp diode for switching inductive loads and transient suppression. The collector-emitter voltage can withstand up to 30 volts and each output is capable of sinking 500 mA of current required by most relays. Both boards measure 3.6 x 3.8 inches (90 x 96 mm) and have the same mounting hole pattern as PC/104 modules. Both boards can be placed on the top or bottom of a PC/104 stack, but it does not have the PC/104 connector and therefore does not pass through power, data, or control signals. These cards will easily work with other embedded computers of different sizes as standalone signal conditioning modules. Both signal conditioning modules are RoHS-compliant and can operate over an industrial temperature range of -40° to +85°C. Quantity one pricing for the ISM-TRM-ISO-IN is $209 and for the ISM-TRM-ISO-OUT is $149. WinSystems, Arlington, TX. (817) 274-7553. [].



6U CompactPCI Enhanced by Third Generation Intel Core Processors A single slot air-cooled 6U CompactPCI Single Board Computer (SBC) utilizes third generation Intel Core processors based on 22nm process technology, featuring improved power efficiency and processing performance compared to the previous generation of processors. The PP 93x/x1x from Concurrent Technologies provides complementary front

and rear I/O interfaces, and is designed to provide an upgrade path for users of earlier generations of Concurrent Technologies’ 6U CompactPCI products. The PP 93x/x1x supports the newly released quad-core 3rd generation Intel Core i73615QE processor or quad-core Intel Core i73612QE processor along with up to 16 Gbytes of ECC SDRAM. Users could experience an increase of up to 15 percent in CPU performance and an increase of up to 50 percent in graphics performance when compared to previous architectures operating within the same power budget over previous Intel Core processor-based 6U CompactPCI products. In addition, the third generation Intel Core processor extends itself to support compute-intensive applications by providing support for OpenCL. Supporting up to two 100 MHz PCI-X PMC or XMC x4/x8 PCI Express sites, the PP 93x/x1x maintains compatibility with previous generation products and offers an array of rear I/O functions: 1x RS-232, 2x Gigabit Ethernet, up to 3x USB 2.0 and up to 4x SATA interfaces. The front panel supports the following interfaces on industry standard connectors: up to 3x USB 2.0 interfaces, 2x Gigabit Ethernet, optional DVI-I graphics and optional RS-232 interface. For application and data storage there is an onboard site for a CompactFlash module and an onboard option for a SATA600 2.5-inch disk drive. The PP 93x/x1x is designed to scale from commercial temperature grade 0° to +55°C (N-Series) through to extended temperature grade -40° to +85°C (K-Series). Operating systems currently supported are Windows 7, Windows XP, Windows Embedded Standard 7, Linux and VxWorks. Concurrent Technologies, Woburn, MA. (781) 933 5900. [].


USB 2.0 Transceiver Series Compatible with Multi or Single Mode Optics A new series of USB 2.0 transceivers allows any USB 2.0 device to be transmitted through a fiber cable network and fulfill longer distance requirements. These distances will certify transmission of up to one (1) kilometer on a multimode fiber and up to ten (10) kilometers on a single mode fiber. The AFI USB 2.0 Series from American Fibertek provides installers with an easy to use solution for incorporating USB devices into a video surveillance system. The system is available in module format for field use or rack card for control rooms and is compatible with multimode or single mode optics. USB 2.0 specifications allow for faster transmission speeds. As PCs and peripheral devices have added more processing bandwidth, performance and features, the USB 2.0 standard was developed to offer a complementary high-speed transfer rate at 480 Mbit/s. Backward compatible with the full speed and low speed transfer rates of USB 1.1, USB 2.0 delivers a significant bandwidth increase while maintaining the value added features that motivated the original USB development. American Fibertek, Somerset, NJ. (877) 234-7200. [].

Quad Serial FPDP Modules for High-Speed Digital Data Links

Software Platform with Enhanced Tools for Optimal Multicore Performance

Two Quad Serial Front Panel Data Port (FPDP) modules with a Xilinx Virtex-6 FPGA provide four channels of serial communication with up to 1 Gbyte per second of aggregate data transfer capability. The Model 71611 XMC module and the Model 7811 native PCI Express card from Pentek provide very competitive alternatives to other sFPDP products in the market. The inclusion of a user-configurable Virtex-6 FPGA allows customers to extend the factory-installed sFPDP functions to perform custom signal processing for both inbound and outbound data streams. Many applications need to deliver highspeed data between systems or from sensors to a data acquisition system over extended distances. As a popular industry standard, sFPDP offers a fast, efficient, bi-directional point-to-point interconnect solution. Applications such as military radar, signal intelligence and medical imaging can take advantage of this high-throughput, minimum latency protocol. As an XMC module, the Model 71611 can be installed on any XMC carrier making this an attractive option for VPX, PCIe and CompactPCI platforms. The 71611 has 2 Gbytes of DDR3 SDRAM for FIFO memory buffering of DMA packets and an optional PMC P14 connector for custom I/O through 20 pairs of LVDS connections to the FPGA. The Model 7811 native PCI Express (PCIe) card can be installed on any motherboard with PCIe card slots. Both the 71611 and the 7811 support Gen2 PCIe and offer a range of Virtex-6 devices so developers can add additional FPGA IP to match custom processing requirements. The Virtex-6 is ideal for modulation/demodulation, encoding/decoding, encryption/decryption and channelization of signals for transmission and reception. The Models 71611 and 7811 are fully compatible with the VITA 17.1 Serial FPDP specification in all modes and operational features. Supporting 1.0625, 2.125 and 2.5 Gbaud link rates and options for multimode and single-mode optical interfaces, the modules can work in virtually any system. Programmable modes include flow control in both receive and transmit directions, CRC support and copy/loop modes. For applications that require specialized functions, users can install their own custom IP for data processing. Pentek GateFlow FPGA Design Kits include source code for factory-installed IP functions, so developers can easily add new functions by incorporating additional FPGA IP modules. Pentek’s ReadyFlow board support packages, with high-level C-callable library functions and device drivers, are available for Windows, Linux and VxWorks operating systems.

A multicore software platform consists of a bundle of productivity tools and a runtime communications engine that simplifies the process of migrating to and developing applications for multicore platforms. Version 2.0 of the Poly-Platform from PolyCore Software offers enhanced memory organization tools and added functionality to maximize multicore efficiency for the high-performance, concurrency needs of applications targeting telecom, datacom, military and aerospace, and process control. Fundamental to improvements in Poly-Platform Version 2.0 are changes to Poly-Mapper, a graphical configuration tool that maps the application functions to multicore architectures. The new memory management of Poly-Mapper significantly improves application functionality and configurability by assisting the developer with memory organization and structure, generating code from the model. Developers can graphically define memory usage across the system, finely controlling interprocessor communication to ensure consistent, documented and well-defined memory utilization for the application. In addition, memory organization models improve abstraction and portability. Additional new features include portable memory maps, improved resource configuration, management and monitoring, and message scheduling. These features precisely control resources, enabling developers to tune parallel processes for maximum performance. With the added control and clear separation between the application and underlying multicore platform, applications are easily ported and optimized for different architectures. Poly-Platform addresses the challenges that arise in multicore programming and facilitates the full use of multicore architectures. With the Poly-Templates GUI tool that rapidly jumpstarts the design cycle, Poly-Platform increases a company’s competitive advantage by handling the inter-process communications across cores, and thereby freeing time for developers to enhance applications. When implementing new multicore solutions, engineers can reuse and scale existing code from one to many cores, preserving software investments. Poly-Platform supports the Multicore Association’s Multicore Communications API (MCAPI), creating an efficient, standardized programming paradigm. Poly-Platform Programming Model Benefit

Topology Assumptions Create Memory Map Create Topology Map

Write Comms Software; Set up Transports


Poly-Platform Tools GUI and Wizards to:

Development Time


Encapsulate functions, if needed; Add Communication Primitives

Hand Coded

• Build Topology Model • Add Instant MCAPI • Structure Memory Usage • Manage Resources • Configure Transports • Generate Code • Initialize/Manage

Topology Definition

pm_n1.c, pm_n1.h

Compile Link Run/Test

Poly-Messenger/MCAPI Libraries

PolyCore Software, Burlingame, CA. (650) 504-0240. [].

Pentek, Upper Saddle River, NJ. (201) 818-5900. []. RTC MAGAZINE JUNE 2012



MEMS Variable Capacitive Accelerometers A high-precision accelerometer uses a simple four-wire snap-in removable connector and is designed to allow users the added ability to exchange, move, reposition and replace accelerometers within a given test setup for greater flexibility, convenience and cost savings. The model 2266 from Silicon Designs is expressly tailored for zero-to-medium frequency applications and offers integral amplification and high drive, low impedance buffering for precision measurements. The accelerometer produces two analog voltage outputs and supports both single-ended and differential modes. Signal outputs are fully differential about a 2.5V common mode voltage. Sensitivity is independent from the supply voltage of +8 to +32V. At zero acceleration, the output differential voltage is nominally 0 VDC; at full scale acceleration, the output differential voltage is ±4 VDC. The sensors feature onboard voltage regulation and an internal voltage reference, which eliminates precision power supply requirements. The low impedance outputs of the Silicon Designs model 2266 will drive more than 100 meters of cable, with an overall flexibility that allows them to be used within a wider variety of applications.

Mini-ITX Board Series Offers Low Power with Integrated High Performance Graphics A Series of new Mini-ITX embedded system boards provides an economical solution for applications that require powerful highquality graphics output with low power consumption. The new AMDY-7000/7001/7002 Series models from American Portwell are powered by AMD Fusion G, Turion II Neo and Athlon II Neo processors with powerful ATI HD 6320 and HD 4200 graphics engines. Depending upon the model, the low power consumption ranges from 12W to 25W. DDR3 SO-DIMM memory supports up to 8 Gbytes.

Silicon Designs, Kirkland, WA. (425) 391-8329. [].

COM Express Modules with Quad-Core Third Generation Core Processors Two families of COM Express modules are based on the third generation Intel Core processor family formerly codenamed “Ivy Bridge,” which utilizes Intel’s advanced 22nm process technology with three-dimensional transistors for higher performance at lower power. The two new COM Express module families from MSC Embedded support Type 2 (MSC CXB-6SI) and Type 6 (MSC C6B-7S) pin-outs. The first products of these module families are equipped with the quad-core Intel Core i7-3615QE processor with 45W thermal dissipation power (TDP) and the Intel Core i7-3612QE processor with 35W TDP. The quad-core processors include support for Intel 64 architecture, Intel Virtualization Technology, IntelAdvanced Vector Extensions and the Intel Advanced Encryption Standard (AES). The Intel HD 4000 Graphics controller on the processor die offers significantly better video and graphics acceleration than the second generation Intel Core processors. One major advantage is the support of three independent displays. In addition to accelerated full HD video encoding and decoding, DirectX 11 and OpenGL 3.1 are supported. The MSC CXB-6SI module family uses the improved Intel 7-series chipset. Fast dual-channel DDR3 SDRAM modules (two SO-DIMM sockets)—each with a maximum storage capacity of 8 Gbyte—also ensure high computing power and at the same time low power consumption. The COM Express module family offers six PCI Express x1 channels, a PCI Express Graphics (PEG) x16 interface, the classical 32-bit PCI bus, eight USB 2.0 ports, HD audio and Gbit Ethernet. DisplayPort and HDMI interfaces with a resolution of up to 2560 x 1600 pixels multiplexed on the PEG lanes are available for the connection of high resolution displays. Data can be stored via four SATA II channels with up to 300 Mbyte/s, an enhanced IDE port or on an optionally populated NAND flash SSD. An onboard connector for a speed-controlled fan on a special cooling solution allows low-noise systems for noise-critical environments. Designed with a Type 6 pin-out definition, the MSC C6B-7S additionally offers four USB3.0 interfaces and easy access to digital display interfaces such as DisplayPort, HDMI and DVI. The platforms run under the operating systems Windows 7, Windows XP (embedded) and Linux. The AMI UEFI BIOS has been implemented on the modules. The pricing for the high-end quad-core Intel Core i7-3615QE will be approximately $680 in volume quantities. MSC Embedded Computer Technology, San Bruno, CA. (650) 616-4068. [].



Dual display is achieved through VGA/ DVI/HDMI/LVDS and dual LVDS is available on model AMDY-7002. The series supports PCIe x1, PCIe x16 or half-size mini-PCIe depending on the model; dual GbE is based on a PCIe x1 high bandwidth I/O interface. In addition, the ATI HD 6320 and HD 4200 provide powerful graphics performance. The AMDY-7000 Series Mini-ITX embedded system board is available now for applications such as point-of-sale (POS), lottery, medical, gaming, high-resolution digital signage and surveillance security monitoring, and it supports a low power, high performance x86 fanless DC option for information kiosks. American Portwell, Fremont, CA. (877) 278-8899. [].


Server-Grade Motherboard with Dual Xeon E5-2600 Series A new server-grade motherboard is powered by Intel Xeon processor E5-2600 family technology, which comprises 64-bit multicore processors, PCI Express Gen 3 high-speed communications and DDR3 1600 registered high capacity memory. The ASMB-920IR from Advantech is designed for high-performance demands such as video processing and mission-critical multi-task applications. ASMB-920IR is Advantech’s first mainboard with flexible Powerful Modular Expansion (PME) design. The PME cards with various support options allow PCI, PCI-X and PCI Express slots to flexibly plug into the main platform. With diverse PME options, the ASMB-920IR keeps upgrade costs under control while fulfilling multiple slot requirements in field applications. This Extended ATX board also meets Server System Infrastructure (SSI) EEB form factor baseboard mounting location specs, so customers can easily build system solutions using Advantech’s or a third party’s server chassis. Unit pricing for the ASMB-920IR starts at $1,215. Advantech, Irvine, CA (949) 789-7178. [].

Ad Index

COM Express Module Marks Energy Efficient Entry Level into Multicore

AdvancedMC SBC Features Third Generation Intel Core Processors

A COM Express compact Computer-on-Module represents an energy efficient entry-level multicore module based on next-generation Intel Atom processors with 32 nm technology. The COMe-cCT6 from Kontron is available in three multicore performance levels up to 2x 1.86 GHz and offers an increased performance per watt ratio. The new Kontron COMe-cCT6 Computer-on-Module is equipped with 2x 1.6 GHz or 2x 1.86 GHz Intel Atom processors (N2600, N2800 and D2550), the Intel NM10 Express chipset, and up to 4 Gbyte of fast onboard DDR3 800/1600 system memory. The integrated Intel Graphics Media Accelerator 3600/3650 enables 1080p playback of MPEG4 Part 2, VC-1, WMV9 and H.264 videos with minimum processor load. Furthermore, the new module provides HDCP support via HDMI 1.3a and DisplayPort 1.1, enabling BluRay playback. Additionally, OEMs can connect monitors also via the common LVDS and VGA interfaces. Intel High Definition Audio complements the multimedia features. Furthermore, the Kontron COMe-cCT6 offers two SATA II 300MB/s interfaces, eight USB 2.0 ports, Gigabit Ethernet and three PCI Express x1 lanes for custom extensions. The platform’s enhanced power management features include Intel Deeper Sleep and Intel Rapid Start Technology, all of which further help to reduce power consumption and enable fast recovery from standby mode for intermittent usage models like those found in modern KIOSK systems. In combination with the Intel Smart Connect Technology, the COMe-cCT6 also enables connected usage scenarios where an instant Internet connection is available as soon as the application is (re)activated, and also allows for constant updates even while in standby. Therefore, the COMe-cCT6 is also an attractive building block for connected devices that are becoming more and more prevalent. The Kontron COM Express compact Computer-on-Module COMe-cCT6 supports a wide range of operating systems including Wind River VxWorks 6.8, Linux, Windows XP, XPe, WEC 7 and WES 7 where Windows 8 support is planned.

An AdvancedMC (AMC) Get high-performance board and feaConnectedprocessor with technology providing solutions tures the third generation Intel companies Core processors. Users of thenow AM 92x/ Get Connected is a new resource for further x1x from Concurrent Technologies could experience an increase of upexploration into products, andof companies. Whether to 15 percent in CPU performance andtechnologies an increase up to 50 per- your goal is to research the latest datasheet from a company, speak directly cent in graphics performance an Application Engineer, or jump to a company's technical page, the when compared towithprevigoal of Get Connected is to put you in touch with the right resource. ous architectures while Whichever level of service you require for whatever type of technology, operating within the Get Connected will help you connect with the companies and products same power budget you are searching for. as previous Intel Core processor-based AMC products. The highly integrated AM 92x/x1x single board computer features the newly released Core i7Get Connected with technology and companies prov 3615QE processor or quad-core Core i7-3612QE processor alongGet with up to 16is a new resource for further exploration into pro Connected datasheet from a company, speak directly with an Application Engine Gbytes of ECC SDRAM in single-width touch the right resource. Whichever level of service you requir form factor. By utilizing inthe 3rdwith generation InGeton Connected will help you connect with the companies and produc tel Core processors, based 22nm process ogy, the AM 92x/x1x is able to benefit from improved power efficiency and processing performance compared to the previous generation of processors. In addition, the third generation Intel Core processor extends itself to support compute-intensive applications by providing support for OpenCL. The AM 92x/x1x is designed in compliance to AMC.0, including full hot swap and IPMI capabilities, AMC.2 Type E2 (2x Gigabit Ethernet) and AMC.3 Type S2 (2x SATA ports). Additionally, the front panel provides connectivity to a Gigabit Ethernet port, DisplayPort interface, a USB port and RS-232 port. Bootable Flash memory can be supported via an optional onboard SATA Flash module. For ease of integration, many of today’s leading operating systems Get Connected with companies and are supported including Linux, Windows 7, Windows XP, Windows products featured in this section. Embedded Standard 7 and VxWorks.

Kontron, Poway, CA. (888) 294-4558. [].


Concurrent Technologies, Woburn, MA. (781) 933 5900. [].

Get Connected with companies and products featured in this section.



with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Company Page Website

Company Page Website

Advanced Micro Devices, Inc......................

Logic Supply, Inc........................................ 20................................

American Portwell................................... 27,


End of Article 2................................. ARM Modules Showcase............................ 10................................................................. Mathworks, Inc........................................... Products Axiomtek Co., Ltd....................................... 35...................................

MEN Micro, Inc.......................................... 34..................................

Get Connected with companies and Cogent Computer Systems, Inc................... 47................................... products featured in this section. Dolphin Interconnect Solutions.....................

Get Connected Microsemi Corporation............................... 51................................. with companies mentioned in this article. MSC Embedded, Inc...................................

Multicore Board Showcase......................... 37.................................................................

Elma Connected Electronic, Inc.................................... Get with companies and products featured in this section.

Get Connected with companies mentioned in this article. One Stop Systems, Inc...............................

Extreme Engineering Solutions, Inc............. 11......................................

Pentek, Inc..................................................

Inforce Computing, Inc...............................

Phoenix International.................................. 46....................................

Innovative Integration.................................. 33...........................

Phoenix Technologies, Ltd.......................... 31.....................................

Intel Corporation...................................... 28,

Sealevel Systems........................................

JK Microsystems, Inc.................................. 46......................................

Super Micro Computer, Inc.......................... 7.................................

Keil, An ARM Company............................... 16...........................................

WinSystems, Inc.........................................

Lauterbach................................................. 25.................................

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.



RTC magazine  

June 2012 Issue

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