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The magazine of record for the embedded computing industry

May 2012

Power Architecture Scores in Embedded Making the Most of Buses and I/O Speeding Data Acquisition in Small Systems

An RTC Group Publication


58 Freescale QorIQ P2041-Based PMC/XMC Module

61 PC/104 Module Combines Serial and Digital I/O


64 Wind River Announces Software Support for Xilinx Zynq-7000 EPP



Technology in Context


Power Architecture Stakes Its Claim

Android: Breaking Out of Phones and Tablets

Power Architecture Combines Rich 6Editorial 18 Once the Network Was the Computer. Features for Embedded Last A Ubiquitous Now the Network Is the World. Embedded OS? 38Android—At Insider TECHNOLOGY CONNECTED 8Industry Latest Developments in the Embedded Marketplace Networks, Buses and I/O Android Goes Beyond Google 44 Ensuring Rigorous Isolation in Small Form Factor Forum 24 Fieldbus Designs 12Wake Up, COM Fawzi Behmann,

Bill Weinberg, Olliance Group (A Black Duck company) and Art Lee, Viosoft


Products & Technology Newest Embedded Technology Used by Industry Leaders


Vincent Ching and Foo Chwan Jye, Avago Technologies


Challenges in Providing Optimal I/O Solutions for Small Systems Ram Rajan, Elma Electronic

Network Connectivity Affects Embedded

14The Fabric of the Cloud Tom Williams


Data Acquisition with Small Modules

Data Transport Challenges in Radar and Sensor Applications 48Solving Bottlenecks Using PCI 54Avoid Express-Based Embedded Systems Rafeh Hulays, Ph.D., AdvancedIO Systems

Jim Henderson, Innovative Integration

Digital Subscriptions Avaliable at RTC MAGAZINE MAY 2012


MAY 2012 Publisher PRESIDENT John Reardon,




Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR/ASSOCIATE PUBLISHER Sandra Sillion, COPY EDITOR Rochelle Cohn





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Tom Williams Editor-in-Chief

Once the Network Was the Computer. Now the Network Is the World.


t is sometimes amazing how things develop in ways we never expected. Let us consider the humble “app.” Now, the word “app” is nothing new. It has long been used as an abbreviation to signify an application. However, with the rise of tablets and smartphones—and especially with Apple reportedly copyrighting the phrase, “There’s an app for that,” the word has taken on a more specific meaning. Namely, it has come to mean an application or operation that can be started by touching one of the icons on a smart screen, usually on an Apple or Android-based smartphone or tablet. In the world of Android, at least, such apps are supposed to be written in Java and executed by the resident Dalvik JVM, which has been integrated into the Android operating system. It is from here that the app accesses any other hardware or software resources that may be available on that particular device. For example, that could be a graphics processor that was integrated with the particular version of the ARM architecture used in the device. For example, the Nvidia Tegra family consists of multicore ARM processors into which an Nvidia GPU has been integrated. Drivers targeted to access this peripheral have been included in the Android build for the device. But now we find that there are further possibilities and that they potentially relate to embedded devices. In a very interesting article in this issue from Viosoft, the author explains that since Android is based on an underlying version of Linux, programs written in C and C++ can be invoked from the Android user interface and run in the Linux environment. They can even take advantage of specific hardware resources that may not be accessible by the Java code but are made useful by means of Linux drivers that can be called by the compiled C programs. Now let’s go one step further. No one is claiming this yet, but suppose we have a device built on a multicore processor (Android has now been ported to the x86-based AMD G Series as well), and that one of those cores has been dedicated to running an RTOS. That RTOS has access to specific memory and hardware resources and can, when needed, run in a partition separately from the rest of the system, communicating over well-defined protocols with a Linux-based program, which in turn sends and receives user data to and from the Java app.



And here, Android doesn’t even have to be in mobile devices. It can offer a well-known and well-understood user experience for many deeply embedded local devices that can also be remotely connected via the same user interface. Yet connectivity is now everywhere and even more resources are available in the Cloud—resources that, when needed by an app, can be accessed by touching that same little icon on the screen wherever that screen may be. Since most tablets and (presumably) all phones have some form of wireless connectivity, apps have access to Cloud-based resources as well. These resources can make huge apps out of “small” ones. For example, almost any app that needs to use and present geographical data could utilize a cloud-based service like Google Earth. At some point, Google does charge for such utilization, but, really, would you prefer to write your own global satellite mapping program or pay Google? Thus, a utility company can have its meters deployed, get the readings and use the mapping program to get any location-related information. Cloud-based hardware resources are becoming available as well. As Cloud applications ramp up, more computing and processing resources become available online. These can be made available during off periods, such as during the night hours when the Wall Street crowd is not using them, and they can be used by apps or by contracting parties such as scientific institutions. But theoretically, even such resources could be accessed by the humble icon on the screen whose underlying app could tap those and diverse other resources and even other apps available and linked to the goals of the app that was invoked. Conversely, the vast amounts of data collected by even small but numerous and distributed embedded systems are available to higher level applications that may reside in business, scientific and IT settings, depending on what they do. And the really cool part is that the availability of such data and resources can easily trigger ideas about how they can be further combined, exploited, used and linked to other apps in ways that had not even been thought of when their collection was originally started. And all of it, all of it is conceivably available right there on that little screen.

ÂŽ Computing/HMI



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INSIDER MAY 2012 PAC on Board for Historic Piloted Return to Depths of the Mariana Trench Industrial controls manufacturer Opto 22 played a central role in the reliable operation of filmmaker and National Geographic Explorer-in-Residence James Cameron’s technologically advanced prototype submersible Deepsea Challenger. Cameron recently piloted the submersible in a successful descent of almost 7 miles (11 km) to the “Challenger Deep,” the deepest point in the world’s oceans. Cameron’s descent was part of the Deepsea Challenge expedition, a joint scientific expedition by James Cameron, National Geographic and Rolex to conduct deep-ocean research and exploration to learn more about the biology and geology of the deepest point on Earth. Aboard the Deepsea Challenger, Opto 22’s SNAP programmable automation control (PAC) System acts as a central controller that manages more than 180 interconnected onboard systems, including sensors, batteries, thrusters, life support, lighting and 3D cameras. The SNAP PAC System additionally records depth, temperature, pressure, battery status and other vital data from the submersible, periodically transmitting the information to a support vessel on the surface. Precise data was essential for control and telemetry, and Project Manager David Wotherspoon with submersible builder Acheron Project Pty. Ltd. thought the Opto 22 system met this requirement well. “I was supremely confident the data being processed and released through the Opto 22 SNAP PAC System was accurate,” Wotherspoon said, “and that it provided a stable control platform.” The SNAP PAC System’s core ability to communicate with all onboard subsystems eliminated the need for signal converters and extra hardware, reducing complexity and increasing reliability. Since most electronic systems and the submersible’s human pilot occupy a cramped 43-in. (109 cm) diameter pilot sphere, these communications capabilities—as well as the compact size of SNAP PAC System components—saved much-needed space. Cameron’s solo dive to the greatest depths of the ocean was backed by a team of engineers, scientists, educators and journalists. Opto 22 provided an on-site technical liaison, Application Engineer Benjamin Orchard, who worked with submersible builder Acheron Project Pty. Ltd. in Sydney, Australia—and later aboard the Mermaid Sapphire support vessel—to integrate the SNAP PAC System into the Deepsea Challenger. In addition, a team of programmers and electrical engineers at Opto 22 headquarters in Temecula, CA, helped with custom programming, system design and troubleshooting.

Hypervisor Vendor Promoted to Windows Embedded GOLD Partner

Real-Time Systems GmbH, a vendor of embedded Hypervisor technology for x86, has announced that they have been awarded with Gold Status in the Microsoft Windows Embedded Partner Program. The company’s flagship product is the RTS Real-Time Hypervisor, a software product that allows customers to partition an Intel x86 multicore platform into virtually independent computers running, for example, a Microsoft operating system as a user interface and separate real-time operating systems in parallel for real-time tasks on the same hardware. Consolidating hardware greatly reduces cost while increasing reliability and reducing power



consumption. The hypervisor solution is particularly useful for products in the industrial, medical or transportation markets where many customers rely on a Real-Time Operating System (RTOS) for time- or mission-critical functions while using a different operating system (OS) for other tasks, such as running a human machine interface (HMI). Because the RTS solution does not depend on a host OS, operating systems can start in any sequence, reboot independently and never harm each other. Real-Time Systems has been a long time member of the Windows Embedded Program as an Independent Software Vendor as well as a System Integrator. “After four years as a Silver Partner, we are very honored that Microsoft now

awarded our expertise and success in the market by promoting us to Gold Level” said Gerd Lammers, CEO and President of Real-Time Systems GmbH. “A large percentage of our customers worldwide use Microsoft Windows embedded operating systems and we firmly believe that only through our close relationship with Microsoft and other partners were we able to make our Real-Time Hypervisor as successful as it is.”

Pervasive Displays and Energy Micro Team to Create Low Power Electronic Paper Solutions

Pervasive Displays, a designer and manufacturer of electronic paper modules for com-

mercial and industrial display applications, has announced its alliance with Energy Micro, a global provider of energy friendly microcontrollers based on the ARM Cortex processor. Combining PDi’s low power electronic paper display modules with Energy Micro’s ability to create low power microcontrollers, this alliance enables Energy Micro solutions developers to quickly and cost-effectively develop and prototype a wide range of low energy electronic paper solutions to display dynamic content. The first release from the alliance is the EPD SK-2 daughter board for the EFM 32 Gecko developer kit. To enable easy, fast demonstrations of electronic paper solutions, Retronix created the EPD SK-2 for Energy Micro developers and bundled it with the EFM 32 Gecko developer kit. The 32-bit EFM 32 Gecko microcontroller family has ultra-low energy consumption, a modern and powerful ARM Cortex-M3 CPU and a vast array of tools like real time, accurate energy and power profiling. The alliance between PDi and Energy Micro enables developers to quickly integrate EPDs into products and applications, creating enhanced benefits and return-on-investment potential unique to PDi’s electronic paper solutions intended for applications where low energy consumption and showing dynamic content are critical. These require ultra-low power consumption for a dot-matrix digital display, capable of years of operation from a coin battery or energy harvesting-based technology. Paper-like dot-matrix displays offer a very high grade of readability and viewing angle, even in direct sunlight and high ambient light

Collaboration Yields Secure Platform for Sensitive Cloud Deployments

Three companies, LynuxWorks, TransLattice and Fritz Technologies, have announced a collaboration of their technologies and expertise to provide a new platform for building cloud deployments in sensitive environments. The resulting Secure, Enterprise, Cross-Domain, Unified, Resilient Environment (SE-

CURE) platform solution creates a suitable environment for situations requiring secure hosting of applications, geographic redundancy of applications and data, and secure cross-domain transfer of information. A first-generation secure server-based separation kernel (SepKer) solution was delivered by Fritz Technologies, working with the LynxSecure 4.0 separation kernel from LynuxWorks. Fritz Technologies successfully

demonstrated that SepKer technology can incorporate trusted boot via the Trusted Platform Module (TPM) and enhanced administrative tooling required to support the hosting of multiple domains and application missions whether in a data center, shipboard, airborne or terrestrial deployment. To add resiliency and efficiency to the already significant benefits provided by SepKer virtualization, LynuxWorks and

Fritz worked with TransLattice to incorporate their state-of-the-art “lattice� application and data distribution solution into the SepKer platform. The TransLattice technology, TransLattice Application Platform (TAP), fully distributes both the application and its data across multiple virtual machines (VMs) and system platforms within a secure domain, ensuring non-stop operations, even in the case of the loss of one or more components of the computing

651.08 (-4.80%) This data is as of May 99, 2012. To follow the RTEC10 Index in real time, visit COMPANY







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Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTC MAGAZINE MAY 2012



“lattice.” This means that mission-critical applications and data are fully distributed and the loss of an individual system (node) or multiple nodes does not endanger the continued efficient operation of the application.

Global M2M Subscriber Base Now Exceeds 100 Million

According to new a research report from the analyst firm Berg Insight, the global number of mobile network connections used for wireless machine-tomachine (M2M) communication increased by 37 percent in 2011 to reach 108.0 million. Asia-Pacific was the strongest regional market, recording a year-on-year growth rate of 64 percent and reached 34.5 million connections at the year-end. Europe and North America grew by around 27 percent each to 32.3 million and 29.3 million connections respectively. In the next five years, the global number of wireless M2M connections is forecasted to grow at a compound annual growth rate (CAGR) of 27.2 percent to reach 359.3 million in 2016. “2011 was the year when M2M communication really took off in China. The number of wireless M2M subscribers in the country nearly doubled and is now estimated to exceed 20 million,” said Tobias Ryberg, Senior Analyst, Berg Insight.” We believe that China Mobile became the world’s largest M2M connectivity provider at the end of 2011 with around 14 million subscribers. If the trend continues, the Chinese market will surpass the U.S. in absolute terms within two to three years.” Berg Insight expects that 2012 will be another positive year for the wireless M2M industry. A renewed interest in telematics technology from the global automotive industry has already had a positive effect on demand and promises to generate very significant additional volumes over the coming. Overall, the enterprise M2M market will benefit from increasingly advanced service enablement platforms that



facilitate the integration of enterprise applications and networked remote devices.

Kyocera Acquires LCD Manufacturer Optrex to Create Kyocera Display

Kyocera has acquired LCD manufacturer Optrex Corporation, to form Kyocera Display Corporation. The Kyocera Group includes over 200 companies worldwide that manufacture a wide range of products including industrial ceramic materials, semiconductor components, automotive components, communications equipment and liquid crystal displays (LCDs). With the acquisition of Optrex and formation of Kyocera Display Corporation, Kyocera will expand its LCD product offerings and manufacturing capabilities for automotive and industrial applications. Kyocera offers a wide range of active matrix TFT LCD panels in sizes from 3.5 to 12.1 inches diagonal and resolutions from QVGA to SVGA. Optrex, founded in 1976, has been focused on small and medium size LCDs in the automotive and industrial market sectors, offering a range of active matrix TFT and monochrome graphic and character LCDs. Kyocera’s Gen 3 TFT LCD fabrication facility produces state-of-the-art polysilicon and amorphous silicon panels. Kyocera Display Corporation will complement their high-volume front-end array production capability with Optrex’s back-end modularization capabilities. The acquisition of Optrex will also enable Kyocera to complement its range of resistive and capacitive type touch screen panels with Optrex’s touch screen bonding capabilities.

Zytronic and Omnivision Cooperate on Multi-Touch User Interface with PCT Sensing Mechanism

Public use touch sensor specialist Zytronic has taken steps to further the uptake of its

Projected Capacitive Technology (PCT) touch sensor portfolio, with news of its collaboration with software supplier Omnivision. As a result, the Omnitapps platform from Omnivision is now fully compatible with Zytronic’s dual touch capable range of PCT touch sensors. Working in conjunction with Microsoft’s Windows 7 operating system, Omnitapps is a customizable application software package that has the capacity to support multi-touch operation on large form factor displays. It consists of an array of different professional applications that, when combined with Zytronic’s robust touch sensors and high-performance ZXY100 touch controllers, make it highly suited to user interface implementations in a variety of different sectors. Zytronic’s PCT-based touch sensors employ a proprietary sensing technology that sets them apart from conventional touchscreen solutions. It consists of a matrix of micro-fine capacitive elements embedded within a laminated substrate, which can be located behind a protective overlay (more than 10 cm thick).Touchscreens based on this proven technology are resistant to the various forms of mechanical damage that can potentially shorten the lifespan of resistive or surface capacitive touch solutions—such as vibration, heavy impacts, scratches, build up of dirt, extreme temperatures, exposure to potent chemicals, high humidity levels, or liquid ingress. These sensors are highly optimized for a wide variety of heavy use applications in industrial and public environments, where they can expect to be constantly “in the firing line” from various forms of accidental and deliberate damage. Furthermore, unlike infrared (IR) and surface acoustic wave (SAW) touch sensor options, PCT can enable all glass, bezel-free designs resulting in smooth-fronted attractive user interfaces that are both stylish and practical to use.

Upcoming Industry Events June 3-6, 2012 IEEE Int’l Interconnect Technology Conference San Jose, CA

June 3-7, 2012 DAC / Design Automation Conference San Francisco, CA

June 6-7, 2012 Sensors Expo & Conference Rosemont, IL

June 21, 2012 Real-Time & Embedded Computing Conference Toronto, ON

July 31, 2012 Real-Time & Embedded Computing Conference Denver, CO

August 2, 2012 Real-Time & Embedded Computing Conference Salt Lake City, UT

August 6-9, 2012 AUVSI 2012 Unmanned Systems Las Vegas, NV


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Colin McCracken & Paul Rosenfeld

Wake Up, COM


ongratulations! You just received your Computer-on-Module (COM) starter kit and you can’t wait to make it hum. Thank your boss for having enough smarts (and budget) to let you buy a complete kit that actually does run out of the box. Simply plug it in and locate the power button; after all, the design is based upon Intel’s reference design for ATX power mode used in PCs worldwide. Pity the poor developers who only bought the processor module. Unwittingly, they are taking a much more precarious development path. After they design and build a prototype carrier board, they will plug into their COM Express or Qseven module only to find that it won’t boot. While interoperability continues to plague COM standards, the typical no-boot scenarios have nothing to do with reserved pins or optional versus required features. Root causes include BIOS initialization, power management, power sequencing, CMOS setting retention and AT/ATX power mode incompatibilities. Ironically, COM standards remain strangely silent (agnostic) with respect to these “gotchas.” BIOS firmware is responsible for initializing all core subsystems as well as I/O controllers. But the standard BIOS on the module doesn’t know about the legacy serial ports, FPGAs or other I/O on your carrier. In other words, plug and pray. Your COM vendor will likely require a minimum order quantity of 100-200 modules to customize the BIOS for you. Power sequencing is even more out of your control. Processor and LAN controller vendors created many optimized power rails to reduce power consumption in laptop or notebook systems. Coupled with main power (+5V or +12V), the main standby rail and the real-time clock (RTC) battery voltage, these must rise and fall in a precise way or the chipset is vulnerable to classic CMOS latch-up. Some COMs now use dedicated microcontrollers to perform most of the power sequencing, which works fairly well as long as your carrier board implementation takes care of the RTC voltage, main standby rail and main power rail. A few vendors have even eliminated the need to provide standby at all, generating it locally when absent. But you can never be sure your design avoids latch-up because the module vendor will not share the details of that part of their COM design.



CMOS settings are responsible for enabling/disabling some features of the hardware and forcing speed and timing selections of others. Once you get settings that work on the reference carrier board, you want to save those settings, unplug the module and install it on your custom carrier. However, those settings are retained by the CMOS coin battery, which resides on the carrier board. Unplugging the module from the carrier disconnects the voltage that retains your optimized settings, so the module reverts to the factory default settings. Catch 22 anyone? Power management is based on the ACPI Specification, which describes system states ranging from on (full power) to soft off (no power except for standby rails). The intermediate states save CPU state information to RAM, or copy RAM to disk (HDD or SSD). ACPI is intended for use with ATX power supplies, which provide +5V standby and handshaking lines such as PWROK/PWRGOOD (the power supply says that the power rails are up and ready) and PSON# (the chipset tells the power supply to turn on or off). Don’t forget to incorporate a “power” button, which tells the system to power on or wake up in the first place. Various systems may or may not wake up when power is initially applied. To wake your COM, you need a keyboard, touchscreen or mouse movement. Or simply press a power button. Wake on LAN requires support in the network controller hardware along with support in the Ethernet driver. And if you want to wake in response to activity on a USB device, good luck. You’re not using an ATX power supply? Join the ranks. “AT mode” refers to turning on and off a system and operating the system from a single voltage power supply. No standby rails. No power buttons. No handshaking lines. Luckily, many module manufacturers have already been forced to deal with this problem. You just need to know to order the right configuration. To design your custom carrier, simply copy your vendor’s reference schematics with minimal changes. Don’t even think about plugging in a competing vendor’s COM. Because whether powering on for the first time or resuming from the deepest of hibernation slumbers, waking up a module-based embedded system requires substantial knowledge of and carrier customization to the module’s implementation.





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Copyright © 2012 Mission Technology Group, Inc. dba Magma

RoHS Compliant

ISO9001:2008 Cer tified

Magma is a trademark of Mission Technology Group, Inc. PCI Express is a registered trademarks of PCI-SIG. Thunderbolt and the Thunderbolt logo are trademarks of Intel Corporation in the U.S. and/or other countries.

editor’s report Network Connectivity Affects Embedded

The Fabric of the Cloud Internet users and Internet-connected devices continue to place demands on the overall bandwidth and capacity of what has come to be called “The Cloud.” Advances in processing power, storage capacity and speed, along with local interconnect efficiency, are trying to keep up. by Tom Williams, Editor-in-Chief


ith the rapid growth of the Internet of Things, with the proliferation of machine-to-machine (M2M) systems and with the growing need for embedded devices to make vast amounts of data available for higher-level applications, the role of “The Cloud” is becoming pervasive. The Cloud is generally understood to be the Internet put to specific uses. But the growth of these uses puts even more demands on the host of data centers and server farms—and the vast numbers of server racks populating them—that constitute the physical presence of the Cloud. With storage roughly doubling every two years, service providers are straining to keep up. And one of the big issues is latency among the components within the data center. So when it takes time to get to the page of a search, the delay is not only due to bandwidth limitations between the node and the service provider. It is also a result of latencies between components and networks within the data center, such as the need to translate protocols between the CPU and the network interface card (NIC) within the individual server and the external network switch and then to the network. In addition, most servers use two NICs—one for an Ethernet switch to the Internet and to other servers and another switch for Fibre Channel access to disk storage. While the latencies keep piling up, there is hope on the horizon for both



increasing transfer speeds as well as simplification in the form of ever faster generations of PCI Express—currently with the arrival of Generation 3 at 8 Gtransfers/s and with Generation 4 at 16 Gtransfers/s about three years out.

A Transformation in Storage

Storage in the data center will be moving from hard disk drives (HDDs) to solid state drives (SSDs) as costs inevitably come down. The traditional data center accesses HDDs via a Fibre Channel network to which each server pizza box is connected via a Fibre Channel switch on top of the rack. This mostly requires a Fibre Channel NIC in each server in addition to the Ethernet NIC required for Internet access. This does not mean that HDD storage will go away, but terabyte-class SSD storage will be coming to supplement it and provide for faster access in a multitiered caching scheme that will no doubt make use of PCIe as well. According to Akber Kamzi, senior marketing director for PLX Technology, the need for higherspeed transfer between CPU and the rest of the system is being driven by the increasing number of cores in the CPU and the need to get the data out. The recently introduced Romley CPUs from Intel with eight and more cores have also integrated multiple PCIe Gen3 lanes into the chip so the interface to the system is via PCIe to the NIC. The distance limit on the board

Figure 1 The Violin 3000 series of solid state memory arrays can scale to more than 140 TB in a rack with performance of over two million IOPS.

is about 14 inches maximum without circuits such as retimers. The next logical step would be to continue with that same speed between CPU and storage—and indeed, between CPU, storage and the Internet—an Internet that will be pushing to 10G, at least for PCIe Gen3. “If you look at the amount of data that is being sorted,” Kamzi notes, “to get the data in and out of the CPU, you need the PCIe bus. Now you have to go to the next step to meet the demand of the data interfaces.” Another big difference is that the SSDs are more local to the server. If not within the box itself, they tend to be in or near the rack, making access with a PCIe over cable scheme practical and able to handle the higher data rates of which SSDs are capable. Previously the HDDs sit somewhere on the other side of the data center and communicate with the servers over Fibre Channel. According to Kamzi, the use of SSDs in a tiered caching role in conjunction with HDDs is becoming quite popular. And the availability of large solid state memory arrays such as the 3000 Series from Violin Memory can now offer scalable storage from 500 Gbytes to 140 Terabytes (Figure 1). The cost of NAND flash is currently hovering around $1 per gigabyte and will eventually match that of HDD storage. Of course, care must be taken with the life cycle of SSDs in that they should only go into applications with relatively low write frequencies. In that respect, their role in the data center will complement that of the HDDs in greatly reducing latency for access to data.

editor’s report

Spreading the Fabric

If you look at the present day data center, Kamzi points out, “You have a 1G or 10G NIC in the server. Each server has two cards and each card connects to a top-of-the-rack switch (Ethernet and Fibre Channel) and each server has to bear the cost of the two adapters—heat and power” (Figure 2). In addition, of course, there are latencies due to electrical and protocol transitions between PCIe to NIC, NIC to switch and switch to network. PLX is advocating a simplification by using PCIe in what it is calling a converged ExpressFabic. Since PCIe is now readily available in CPUs, Gen3 access to a PCIe NIC is now possible, and access to the top-of-the-rack switches and to other servers in the rack is handled by the Gen3 PCIe over cable technology developed by One Stop Systems. PLX has also developed a 48-lane fabric switch and is soon to introduce a 96-lane version. Such switches can be configured for x16 channels to interface with the Ethernet and Fibre Channel NICs and as x4 channels for access between servers in a rack using PCIe over cable. PLX has also announced that it is working with Avago on a low-cost optical connector that will enable 30- to 50-meter Gen3 access to other racks in the data center. In the near future there will be silicon that will do Ethernet on one side and PCIe on the other. The result could be a high-speed unified fabric such as the one in Figure 3. In addition to local and massive SSD storage, Kazmi foresees Gen3 and eventually Gen4 PCIe access to arrays of generalpurpose graphics processors (GPGPUs) for extremely intense floating point processing. Such arrays could act as cloud-based clusters for high-speed scientific processing. For example, installations such as a national laboratory like Lawrence Livermore could send jobs in the evening when traffic is down and pick up the results in the morning in situations where they happen to need more compute power than they have in house.

When Gen4?

Of course, now that PCIe Gen3 is starting to appear as actual products, ev-

FC Switch

Ethernet Switch



Ethernet LOM/NIC











Fibre Channel Figure 2 Today’s data center consists of rack-mounted servers with multiple network cards running different protocols to connect to the Ethernet (Internet), storage and other servers.

eryone is clamoring to know when they can expect Gen4. Gen3 is attracting attention because Intel recently introduced its “Romley” Sandy Bridge-based server series of CPUs, with their 8 to 16 cores and that also integrate multiple PCIe Gen3 lanes, hence making them practical to use in schemes such as those discussed here. We asked PLX’s Akber Kazmi, and his unofficial estimates for actual products on the market are approximately sometime in late 2014. The specifica-

tion is still being defined and experiments are underway, and a completed spec may be expected sometime mid to late next year. There had been a debate over whether to implement Gen4 in copper or as an optical interface. The decision was finally made to go with copper one more time, although this is probably the limit. The limit on a run for copper is maybe 10 to 12 inches on a board after which additional electronics such as retimers and repeaters are RTC MAGAZINE MAY 2012


editor’s report


or she might need with the 16 Gtransfers/s that will be available from PCIe Gen4. But that question appears to be limited to the local aspects of what are increasingly more global, cloud-oriented applications. If science and engineering can find ways to make things run faster, developers will definitely find ways to put that to use.

PCI Express Fabric Switch



PCI Express CPU/Host









PCI Express

PLX Technology Sunnyvale, CA. (408) 774-9060. [].

PCI Express Switch

Figure 3 A PCI Express-based server fabric will use Gen3 and, later, Gen4 PCIe fabric and switches throughout to minimize latency and access different parts of the data center including local solid state storage and GPGPU arrays.

necessary. Additionally, there will be market demand for cabling solutions, which will no doubt be optical as well. In addition, the prediction is that graph-


Untitled-2 1


ics processing will take a big advantage from the increased speed. So the embedded developer might be forgiven for asking what in the world he

One Stop Systems Escondido, CA. (877) 438-2724. []. Avago Technologies San Jose, CA. (408) 435-7400. []. Violin Memory Mountain View, CA. (650) 396-1500. [].

5/4/12 1:53:35 PM

Technology in


Power Architecture Stakes Its Claim

Power Architecture Combines Rich Features for Embedded Spanning applications from tiny, dedicated controllers to vast supercomputers, the Power Architecture offers advantages to the embedded space that include parallelism, multicore virtualization, power management and a rich selection of software tools. by Fawzi Behmann,


ower Architecture processing tech- for game consoles, Px series for micronology is the common thread for a controllers, PowerQUICC, QorIQ P & very broad range of devices, based T series for networking and communiploration on 32/64-bit Architecture. It is a ubiqui- cations. The list continues with Packet your goal tous architecture with more than a bil- Pro for WLAN and Storage, Axxia sek directly lion Power Architecture-based chips that ries for carrier grade and core networks, age, the source. have been built into electronics equipment 7xx & 9xx for mission-critical applicaology, tions and High Performance Computsince 1991. d products Power Architecture technology is the ing (HPC), POWERx for servers & basis for an extraordinary range of prod- workload optimization, Blue Gene suucts, from supercomputers with 213,000 percomputers and Watson, licensable processors to tiny automotive control- cores, full featured Virtex FPGAs from lers dissipating less than a watt of power. Xilinx and hybrid processing devices Power Architecture technology is used in (Figure 1). Every Power Architecture technoleveryday household electronics—printers, nies providing solutions now ogy-based chip is rooted in the Power InHDTVs, video recorders, game consoles— ion into products, technologies and companies. Whether your goal is to research the latest struction Set Architecture (ISA) and proas well as more exotic electronics, such as ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you cessing specifications spanning server satellites and the Mars Rover Lander. This you require for whatever type of technology, and embedded computing capabilities. it well for.suited for any advanced and productsmakes you are searching Power ISA is the only architecture in the electronic application offering the best market that has proven implementations performance per watt. from the smallest devices to the largest supercomputers while covering a diRich Set of Chip Families, verse set of markets. Power ISA features Diversity, Applications and are familiar to thousands of software, Market Share Power Architecture technology un- hardware and tool developers who have derlines many well-known chip fami- worked with PowerPC devices for many lies for 32-bit and 64-bit architecture, years. The most recent Power ISA 2.06 including the Cell Broadband Engine extends the edge Power ISA has in HPC and computation-intensive workloads; provides enhancements to the server Get Connected space such as memory management, prowith companies mentioned in this article. cessor version compatibility features and

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Get Connected with companies mentioned in this article.

cache management; and also introduces a number of capabilities for the embedded space such as embedded hypervisor, energy management, multicore and multithreading. According to IMS Research, Power Architecture is $4.4 billion of the total 32/64-bit microprocessor market spanning the eight major markets and expanding into 30 vertical market segments. Among ARM, MIPS, SPARC, X86 and others, Power Architecture microprocessor revenue was ranked as the number one worldwide market share leader in 32-bit MPU, and the number two worldwide market share leader in 64-bit CPU (Figure 2).

Power Architecture—Power ISA Key Differentiation

Scalability, reliability, flexibility and the open collaborative model of are some of the characteristics that differentiate the Power ISA from all others and influence the evolution of Power Architecture into a unique position. “Set-tops to Teraflops” is the tagline that uses to communicate the inherent scalability of the Power Architecture to the industry. Power Architecture covers the most diverse set of markets including consumer electronics, industrial control, telecommunications

technology in context

Power Architecture Silicon Roadmap The Heart of Ecosystem Applied Micro





32-bit Commercial Processors Historical



China Chip

GDA Tech.

32-bit Commercial Cores Historical

APM 86XXX APM 821XX APM 801XX Pro+ ket 460SX 450EX/GT Pac Pro 440 440S 440E 440G SLIM 405E 405EX QorlQ P40xx QorlQ P30xx QorlQ P20xx QorlQ P10xx 75x 7410 74XX 8641D PowerQUICC III – 85xx PowerQUICC II Pro– 83xx PowerQUICC II – 82xx PowerQUICC I – 8xx P51xx/52xx P5XX/ 55xx/ 56xx


Axxia Comm. Proc. 750GX 750CXe / CXr 750L


IPextreme Synopsys VeriSilicon Current

e200/e300/e500/e600 405/440




465 c500mc


476 476

480 460 40582 / 440T90

c200 405S / 440S 405S2 / 460S


64-bit Commercial Processors Historical



970FX 970MP / GX POWER1/2/3/4/5 POWER6 POWER7 P7 755QDR Power8 QorlQ P55xx/T4xxxAMP

64-bit Commercial Cores Historical



750GL 750CL

Hybrid or Accelerator Architectures

Dual 440 Blue Gene/L/ P




Next-gen (A2) Next-gen e5500/e65xx Future

Cell/PowerXcell/Blue Gene/L/P Blue Gene/Q/Blue Waters Watson Virtex-II Pro Virtex-4 FX Virtex-5 FXT

Figure 1 Power R&D roadmap delivering scale, scope and range.

and networking, high-performance computing, IT and commercial systems, aerospace and defense, high-end printers and imaging solutions. This is a testament to Power Architecture’s scalability in that it can address a vast array of applications while preserving the binary compatibility of software. The reliability of Power Architecture implementations is evidenced by

the many mission-critical applications in aerospace and defense, such as all the Mars Rover landings that used Power Architecture chips. Power Architecture maintains the leading share of safetycritical automotive embedded systems and has a proven track record of reliability in servers with the lowest soft error rates under a barrage of proton and neutron radiation.

Power ISA covers both 32-bit and 64-bit variants and provides facilities for expressing instruction level parallelism (ILP), data level parallelism, and thread level parallelism that give the programmer the flexibility to extract the particular combination of parallelism that is optimal. The ability of Power Architecture to provide instruction, data and thread level parallelism has enabled a variety of parRTC MAGAZINE MAY 2012


technology in context

Figure 2 Power Architecture is $4.8 billion of total 32/64-bit microprocessor market spanning eight major (embedded and compute) markets.

allel systems, including some notable supercomputers. Power ISA allows exposing and extraction of ILP primarily because of the RISC principles embodied in the ISA. The reduced set of fixed length instructions enables simple hardware implementation that can be efficiently pipelined, thus increasing concurrency. The larger register set provides several optimization opportunities for the compiler as well as the hardware. Processors implementing the Power ISA have been used to create several notable parallel computing systems, including the IBM RS/6000 SP, the Blue Gene family of computers, the Deep Blue chess playing machine, the PERCS system, the Sony PlayStation 3 game console and the Watson system that competed in the popular television show Jeopardy!

Multicore SoC and Virtualization

Power Architecture technology was an early participant in the world of multicore SoC. IBM Systems and Technology Group and Power Architecture embedded partners and customers have been implementing multicore designs since 2001. The ubiquitous PowerQUICC



processors from Freescale, which were launched in the mid ’90s, have always been heterogeneous multicore devices. In 1995, Freescale introduced MPC860, which had two cores—one based on Power Architecture technology and the other was proprietary RISC architecture. In 2001, IBM’s POWER4 incorporated dual cores on a single die. It also was the first to implement a multichip module containing four POWER4 microprocessors in a single package. More recently, Freescale’s QorIQ families (P1, P2, P3, P4 and P5) implement from 1 to 8 Power Architecture cores, emphasizing hypervisor and virtualization. Additionally, the POWER7-based supercomputer, Blue Waters, was announced to support 200,000 processors, bringing multi-petaflops performance in 2010-2011. The challenge of how to efficiently program and automate software development for multicore devices has been addressed by via multiple ISA and technical initiatives. Power ISA 2.04 was finalized in June 2007 and includes changes regarding virtualization, hypervisor functionality, logical parti-

tioning and virtual page handling. Additional enhancements resulted in ISA 2.05 released in December 2007, which supports decimal arithmetic and server hypervisor improvements. Power ISA 2.06 was released in February 2009 and included extensions for the POWER7 processor and e500 multicore regarding hypervisor and virtualization on single and multicore implementations for the embedded market. Thus, Power ISA 2.06 enabled virtualization for embedded hypervisor and other virtualization technologies. In the embedded space, the hypervisor is a true hardware-supported operating mode that ensures protection of the virtual kernel from guest operating systems. Thus, the hypervisor allows different software systems to run on different cores at the same time with high integrity. This approach allows each software system and its associated private hardware resources to be protected. While different systems are insulated from direct interactions, software systems can establish communication mechanisms with other software systems in a controlled and reliable manner. This results in simplifying software development by creating an abstraction layer of capabilities for the underlying cores.

Energy Management

Power Architecture cores provide important capabilities for dynamic power management. Some of these are enabled internally in the core. For example, it is common for execution units in the processor pipeline to be power-gated when idle. Furthermore, Power Architecture cores offer software-selectable powersaving modes. These power-saving modes reduce function in other areas, with some modes limiting cache and bus-snooping operations, and some modes turning off all functional units except for interrupts. These techniques are an effective way to reduce power, because they reduce switching on the chip and give operating systems a means to exercise dynamic power management. But sometimes only the application software running on the processor has the knowledge required to decide when

technology in context

power can be managed without affecting performance. Recognizing this fact, Power Architecture Embedded Supervisor Architecture provides application software with a means for power-optimized solutions through the wait instruction (Power ISA 2.06). This instruction allows software to initiate power savings when it is known that there is no work to do until the next interrupt. With this instruction, power savings can now be achieved through user-mode code. This feature, for example, is well matched to the requirements of the LTE market segment, which requires that total SoC power be managed effectively. The combination of CPU power-savings modes, the wait instruction and the ability to wake on an interrupt has been demonstrated to achieve deep sleep power savings with wake up on external event— with no packet loss.

ment, enabling the highest performing processors and cores for the server and embedded space. Advancements in the Power Architecture technology continue to provide designers and developers with scalability, reliability and flexibility needed in their diverse markets. Moving forward, Power Architecture technology’s focus on energy management, multicore/virtualiza-

tion, SoC platforms and software development environments will enable Power Architecture technology to continue to be a ubiquitous architecture in the industry, helping to drive many new and exciting applications. [].

Software Development Environment

Power Architecture technology has the largest breadth and depth of development tools support in the industry. As expected, tools naturally congregate around the market segments where Power Architecture technology is popular: servers, storage, networking, communications, automotive and digital media. Power Architecture technology is supported by virtually all major operating system platforms and most minor ones as well. Full system simulation provides virtualization capabilities for the Power Architecture community and helps software developers debug at the system level instead of at the individual board level. Developers are able to run simulations of their full systems, sometimes containing hundreds of different boards with many different kinds of processors, SoCs, devices and communication buses. This simulation helps identify performance enhancements and improves time-to-market through early identification of system trouble spots. and its members further advanced Power Architecture technology, completing a number of vital initiatives including Power ISA standards, hypervisor, virtualization and energy manageUntitled-18 1


2:03:25 PM RTC MAGAZINE 5/2/12 MAY 2012












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Morning & Afternoon Sessions Plus Hands-On Lab

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connected Networks, Buses and I/O

Ensuring Rigorous Isolation in Fieldbus Designs Understanding Fieldbus interface isolation technologies and their associated tradeoffs is the first step in making sure your design is as tough as the environment it works in. by Vincent Ching and Foo Chwan Jye, Avago Technologies


ieldbus (or field bus) is a diverse collection of industrial computer network protocols and network standards used for real-time distributed control. Unified and harmonized under the IEC 61158 standard, Fieldbus provides designers with a well-stocked arsenal of technologies for connecting, controlling and managing automated equipment in manufacturing plants and other challenging environments. A complex automated industrial system, such as the manufacturing line shown in Figure 1, is often built on an organized hierarchy of controller systems. In this hierarchy there is usually a human machine interface (HMI) at the top, where an operator can monitor or operate the system. This is typically linked to a middle layer of programmable logic controllers (PLCs) by a non-time-critical communications system such as Ethernet. At the bottom of the control hierarchy is the Fieldbus that links the PLCs to the components that do the assembly line work, such as sensors, actuators, electric motors, console lights, switches, valves and contacts.

Common Fieldbus Types

The IEC 61158 Fieldbus standard defines eight different protocol sets, also known as “Types.” These Types are used as the foundation for a larger



Date Rate (Kbit/s) 125 250 500

Communication Distance (m) 500 250 100

TABLE 1 DeviceNet’s maximum data rate vs. distance.

number of application-specific Fieldbus standards and their associated physical, data link and application layer specifications. The most commonly used standards for industrial automation applications include Profibus, DeviceNet and CAN Bus, which are briefly described below. Profibus-DP (Decentralized Peripherals) has been adopted by over 200 suppliers that offer compatible devices. It is accepted and used globally for plant and process automation. It is an open standard (based on EN 50170) digital communications interface, or Fieldbus, designed specifically for use in industrial applications. It can be implemented using either copper-based (EIA/RS-485) or fiber-based transceivers; its optical variant supports data rates of up to 12 MBaud, making it the fastest Fieldbus available today. Profibus-DP can link plant supervisory systems, process automation systems

and peripheral devices such as feeders, mixers and pneumatic conveying systems. It supports communication distances in excess of 2000m. DeviceNet is a low-cost industrial network for connecting industrial devices such as limit switches, photoelectric cells, valve manifolds, motor starters, drives and operator displays to PLC processors and PCs. It implements the Common Industrial Protocol (CIP) over the CAN bus. This network technology delivers moderately high data rates and helps eliminate expensive hard-wiring while providing device-level diagnostics. DeviceNet’s data rates and communication distances are shown in Table 1. The Controller Area Network (CAN) bus is a rugged serial digital bus designed for harsh industrial environments. Its flexibility and robust characteristics have helped it gain widespread acceptance in many applications and markets including factory automation, building automation,

technology connected

aircraft and aerospace as well as in cars, trucks and buses. CAN’s physical layer is a differential serial bus based on the EIA/RS-485 standard with non-return to zero (NRZ) coding. When combined with CAN’s higher-layer error detection/correction and fault confinement techniques, it enables highly reliable transmission of commands and data. As with other electrical Fieldbus variants, its reach varies according to the data rate it is required to support, ranging from a maximum of 40m at 1 Mbit/s to a maximum of 6 Km at 10 Kbit/s. A summary of the capabilities and characteristics of the common Fieldbus technologies is presented in Table 2.

Three Big Challenges

The three primary challenges faced by anyone designing electrically based Fieldbus interfaces are noise (EMI/RFI) immunity, high voltage isolation and bus latency. As we shall see, all three issues are related in some way to the isolation components used in Fieldbus designs to ensure the bus controller and the electronics behind it are electrically protected against EMI/RFI-induced transients and high-voltage incursions. Due to the lower cost and simpler installation requirements of copperbased electrical interfaces, many Fieldbus networks employ them rather than the fiber-based alternatives available for CAN and some other Fieldbus standards. While usually slower and able to support shorter network spans than their optical counterparts, electrical transceivers offer lower wiring costs and direct compatibility with the large installed base of older, “legacy” systems already in use at many industrial facilities. Unfortunately, stray electromagnetic energies cause electromagnetic interference (EMI) and radio frequency interference (RFI) on the copper Fieldbus cabling. RFI is usually a narrow-band phenomenon and can





Isolation needed Figure 1 Fieldbus provides a robust, reliable electrical or optical communication backbone for modern automated industrial control systems. If the network uses a copper-based physical layer, isolation is required at each network node to guard against transients and EMI commonly found in harsh industrial environments.

originate from a wide range of sources such as mobile phones, power lines, transformers, medical equipment, electromechanical switches, some motors, and many other unintentional emitters found in the industrial environment. EMI wreaks havoc upon an unprotected network in two ways. Radiated EMI travels through the air and conducted EMI travels along a conductive path. Both flavors of EMI can interfere with the proper operation of the equipment, contaminate the bus signal beyond recognition and, in some cases, physically damage electronic components. The discipline of EMI/RFI mitigation is usually achieved by a combination of removing or reducing any sources of interference and good design practices, which include selecting devices that are less susceptible to EMI, optimizing the layout to minimize coupling effects, and using proper shielding practices.

In addition, Fieldbus standards require the use of isolators at every network transceiver to prevent EMI, RFI, or stray voltages from working their way from the bus cabling to your equipment, or from escaping from your equipment onto the bus. All commercially available isolator solutions are based on CMOS or bipolar integrated circuits and use capacitive, inductive or optical isolation techniques. Optical isolators, or optocouplers, are the most commonly employed isolation technology in Fieldbus applications. They have provided electrical safety in industrial applications for decades and come in a variety of form factors, voltage ratings and speed grades to fit nearly any application (Figure 2).

The Shocking Truth

In addition to protecting against EMI/RFI effects, designers must consider equipment and component safety, RTC MAGAZINE MAY 2012


technology connected

especially when high voltages (above 48 VDC or 110 VAC) are involved. This requires protecting the equipment and anything connected to it against the unfortunate ability of Fieldbus’ copperbased UTP cabling to act as a conductor for the high voltages often found in industrial systems. The Fieldbus transceiver in an industrial automation system is usually surrounded by motor starters, servo drives, programmable logic controllers and power converters. And in many factories, instruments and automation control boxes are co-located with high-powered industrial systems that may contain power supplies and control elements that operate in the multi-kilovolt range. All these factors make it imperative that the isolators connected to a

copper Fieldbus protect against whatever potentially lethal AC or DC voltages might unexpectedly emerge from your, or someone else’s equipment during normal operation, an equipment malfunction or other disaster. Whatever technology they use, isolator components must have insulation characteristics that help to separate circuits that present a danger of electrocution from other circuits, as well as to separate certain parts of the equipment with which a user may come into contact or that connects to other equipment. Additionally, the circuit must be safe both during normal usage and under fault conditions. The IEC 60747-5-5 safety standard defines two levels of insulation with a clear distinction for safety. Basic insulation is by definition considered to

fail or become shorted under a single fault condition. In contrast, the “reinforced insulation” rating can only be approved and applied to “failsafe operation-qualified” components that deliver both basic protection from electric shock and also support “failsafe operation” designs that enable safe user access during an equipment failure. IEC 60747-5-5 was specifically written for optical isolators only, but devices using other isolation technologies, such as magnetic or capacitive isolation barriers, have obtained “basic insulation” certifications to this optocoupler safety standard. As noted, this basic insulation may not provide failsafe operation performance, so the non-optically isolated devices cannot be considered failsafe and therefore should not be accessible to





Max. Devices or Nodes

64 per master



Max. Baud rate

156 Kbit/s to 10 Mbit/s depending upon distance

500 kBd

127 nodes (124 slaves -4 seg, 3 rptrs) + 3 masters 12 MBd (9.6 kBd to 12 MBd are supported)

Max. Extension

1200 m (twisted pair), Master plus 10 repeaters= 13.2Km

100 m at 500 kBd, 500 m at 125 kBd, 6 km with repeaters

Network Topology

Trunk line, drop line with branching

Typical Applications

Commonly found in factory floor processes

Technology Developer

Mitsubishi Electric

Most commonly found in assembly, welding, automotive, semiconductor, and material handling machines. Layer 1, 2: Bosch AG, Layer 7: 1994 Rockwell Automation (AllenBradley)

TABLE 2 Properties and capabilities of common Fieldbus technologies.



1 MBd

100 m between segments 1 km at 10 kBd, at 12 MBd, 24 km (Fiber) 40 m at 1 MBd (baud rate and media dependent) Line, Star, or Ring Trunk line, drop line

Commonly found in Process control and large assembly, and material handling machines

Commonly found in Automotive and Motion control systems, assembly, welding, and material handling machines Siemens Profibus DP Layer 1, 2: Bosch (Decentral Periphery) AG, Layer 7: CAN In 1994 Profibus PA (Process Automation, Philips, 1995 Automation) 1995

Bus Controller

Bus Cable

Bus Transceiver

technology connected

Local Device

ACPL-072L Figure 2 An opto-isolator, such as one of Avago Technologiesâ&#x20AC;&#x2122; ACPL-07x series, provides protection for Fieldbus equipment against the EMI/RFI and stray voltages found in industrial environments.







Figure 3 Measuring distance through insulation (DTI) for wide body and standard packages.

Multicore Debugging: Mix & Match Untitled-6 1


5:17:55 PM RTC MAGAZINE 2/6/12 MAY 2012

technology connected

a user. Designers must also be aware of the isolator’s contribution to a Fieldbus network’s overall system propagation delay. System delay consists of the combined delays of the CAN transceiver, CAN controller and the optocoupler. It is critical that the sum of the component propagation delays not exceed the specified value to ensure the device is capable of working with the maximum cable distance at the corresponding bit rate. The CAN standard calls for a maximum delay time of 40 ns for the isolator. This indirectly translates to a speed of 25 MBd (1/40 ns).

parameters: high-voltage performance and insulation integrity. The high-voltage life test was a destructive test where high voltage was applied to magnetic isolator devices from a well-respected manufacturer and optocouplers from Avago. In accordance with the devices’ data sheets, 2.5 kV was applied constantly to the magnetic isolators and a group of comparable optocouplers were subjected to a higher voltage (3.75 kV). The magnetic isolators were destroyed between 8.5 hours to 10.5 hours of continuous test, while the optocouplers survived a minimum duration of 168 hours at the higher 3.75 kV voltage.

and performance issues in earlier generations created a market opportunity for other types of isolators based on magnetic and capacitive technology. As a result, several magnetically coupled isolator products have emerged on the market that claim to deliver better integration, size and speed. While the manufacturers can substantiate some of these claims, fundamental questions about their reliability and robustness have remained unanswered. And, as we shall see shortly, each isolation technology behaves differently in the presence of high voltages and strong electromagnetic fields. Some of the claims about magnetic isolators were recently evaluated in a series of tests that were designed to determine how long a particular isolation device can successfully insulate one side of its isolation barrier from high voltages on the other side. The test was structured to assess a device’s reliability in terms of two

Comparing Optical and Magnetic Isolation Technologies

Over the years, manufacturers have added new functionalities, increased insulation, higher isolation voltages and smaller packages to their optocoupler product portfolios. Nevertheless, the relatively high complexity of optocoupler structures

Distance Through Insulation (DTI)

Internal clearance, or distance through insulation (DTI), is another important metric for electrical protection. When applied to optocouplers DTI is defined as the direct distance between the




ACPL -072L/772L HCPL -7721/3 HCPL -0721/3





6 7


5V VCC 1 TxD

.01uF +


5 V+

3 CAN Transceiver


.01uF ACPL -072L/772L HCPL -7721/3 HCPL -0721/3






RXO .01uF






7 5

2 .01uF




4 CAN+ 3 Shield

RxD 8

Linear or Switching Regulator


2 CAN1 V-

5 4 D1 30V

C1 .01 uP 500V

Figure 4 A Fieldbus (DeviceNet, CAN, Profibus and RS-485) application circuit using Avago high-speed optocouplers.



R1 1 MΩ

technology connected

photo-emitter and photodetector inside the optocoupler’s cavity. Figure 3 illustrates how DTI is measured in the widebody and standard optocoupler packages. Some equipment standards require a minimum of 0.4 mm DTI for reinforced levels. Examples of such equipment standards are: IEC 60651 (Medical) and IEC 61010 (Measurement and Control). No exemption is given for these two equipment standards. Current suppliers of non-optical based isolators do not offer products that meet the minimum DTI specification of 0.4 mm. Their current product portfolios have typical DTI specifications of about 0.018 mm; this reason alone makes designers think twice about choosing a magnetic or capacitive isolator for a medical or a test and measurement application. While the optocoupler’s LED/photodiode combination is considered immune against EMI due to the optical coupling path, the magnetic isolators do have limitations with respect to EMI because of their microstructure and magnetic coupling. Magnetic coupler failure can occur at DC (0 Hz) as well as at various frequencies and different field strength levels. The results of these studies indicate that optical isolation provides superior EMI performance and can withstand much higher electromagnetic fields than other isolator technologies currently on the market. This supports the assertion that optocouplers are the best choice for demanding Fieldbus applications.

paying attention to four key issues. The first is to observe safety standards for isolation devices. Look for optocouplers that meet the IEC 60747-5-5 standard with “Reinforced Insulation” to ensure failsafe operation. Next, carefully consider the reliability of the isolator’s high voltage insulation to minimize the potential for component breakdown when the system is exposed to a high voltage surge. It is also essential to use design, shielding and isolation to mitigate the effects of EMI and RFI. And finally, one must ensure that the transceivers’ isolators meet or exceed the mandatory distance through insulation (DTI) requirement: A greater than 0.4 mm requirement for both medical and test and measurement equipment has excluded magnetic and capacitive isolators from use. Avago Technologies San Jose, CA. (408) 435-7400. [].

Optocouplers in Action – A Practical Example of a High Speed Fieldbus Design

Figure 4 illustrates how optoisolators are implemented in a typical Fieldbus transceiver circuit. As the multiple part numbers beside the opto-isolators indicate, there is a wide range of optocouplers available to meet any speed, signaling/operating voltage and level of protection required by the various Fieldbus standards. Designing a safe and robust Fieldbusbased industrial system can be challenging, but the process can be made easier by

Untitled-3 1



2/3/12 2:11:13 PM


connected Networks, Buses and I/O

Challenges in Providing Optimal I/O Solutions for Small Systems As systems get smaller yet more powerful and feature-rich, the challenge of bringing all the I/O out of the box increases. Various methods are available to bring that I/O out of the system despite SWaP challenges and reduction in number of slots, all while retaining the use of military-style connectors. by Ram Rajan, Elma Electronic


he most obvious challenge in bringing I/O out of electronic packaging is the lack of real estate. The same ploration powerful processors that are enabling your goal systems with smaller footprints are also k directly supporting greater numbers and types of age, the source. I/O from each card in the system. Thus, ology, density is being driven both by advanced d products silicon that can handle more inputs and by the smaller form factors that the more powerful processors are allowing. This is Figure 1 especially challenging in rugged defense environments, where large military-grade Example of a rigid I/O panel. connectors are still necessary to meet human factor requirements and to withstand • Special I/O slots that bring the necesnies providing now the solutions rough environment. There are multiple sary signals to a faceplate, much like ion into products, and companies. your goal is to researchother the latest plug-in cards. waystechnologies of addressing these Whether I/O challenges. ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you •  S idewall I/O panels that support mulAn overview of considerations for differyou require for whatever type of technology, tiple connectors and are connected to typesfor. is presented in the sidebar and productsent youcable are searching the main backplane with discrete wire titled, “Cable Type Considerations.” cables and or flat flex cables. Five general approaches are regularly used to bring I/O out of embedded • Rigid-Flex-Rigid (RFR) assemblies systems based on standard backplane that support multiple connectors at architectures: the enclosure sidewall on rigid printed • Hard-mounted I/O connectors incorcircuit boards. These are similar to the porated into the backplane itself that previous approach, but they are actually extensions of the backplane and support all types of discrete custom manufactured at the same time, with a cables as well as all the standard comflexible multilayer section that allows mercial cable connectors. the I/O panel to be positioned at a different angle than the backplane itself. Get Connected • Connectorized (Direct Plug Interconwith companies mentioned in this article. nect) risers and mezzanines that

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Get Connected with companies mentioned in this article.

port multiple connectors at the enclosure sidewall, as in the previous two approaches but are directly attached using board-to-board connectors to one of the edges of the backplane, or even on the rear of the backplane as a mezzanine.

Hard-Mounted I/O Connectors

In this method, individual bulkhead connectors are mounted to the wall of the enclosure and multiple discrete wires connect it to one or more cable connectors mounted directly on the backplane. This method includes cable connectors that are designed to plug directly into the backplane slot connectors from the rear. Such cable connectors exist for most standard backplane architectures such as VME, CompactPCI and even the ATCA architecture. The VPX architecture has a particularly dense backplane cable connector system that supports very high speed signals. Hard-mounted I/O connectors also include flexible coaxial cables, semi-rigid and rigid coaxial cable. Fiber optic cables are also included in this approach. The challenge with RF cables is that coaxial cables require a bend radius for the cable to reach the sidewall. Right angle connectors will help in some cases, but if there are too many connectors arranged in


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Cable Type Considerations There are several cabling methods to consider when faced with a challenging package design. Three different types of cables are most common in embedded systems: discrete, RF and fiber optic. See the summary in the accompanying Table 1.


Connector Types: Mil-Spec Style, D38999, Micro D-Sub, Standard D-Sub, General “Offthe-Shelf” style. Depending on the design of the system, there are several ways to approach discrete system I/O cabling. When space is not an issue, using a more traditional wiring approach is typical and most economical for prototype development. Where space is somewhat limited, a flex circuit might need to be considered, which then eliminates the need for discrete wires. Board-to-board design is the next alternative way to make the custom I/O connections. This is by far the most costly method and is not suitable for prototypes. Testing: Standard point-to-point testing is done for custom I/O cables using an Ohm Meter. The quantity of systems being built will determine if special test adaptors are required. Custom extender boards have been developed to test custom I/O cables that interface with backplanes, which will test the entire chassis from rear panel connectors through the cables and through the backplane.

RF Cables: Cable types: RG59, RG316, RG402, RG405, Rigid Connector Types: SMA, SMB, SSMC, TNC, BNC Testing: Special testing equipment is required for measuring insertion loss for RF cables. In the prototyping stage or for low volumes, this is not practical.

Fiber Optics: Cable Types: 50/125um, 62.5/125um, 85/125um, 100/140um, Armored Connector Types: FC, LC, SC, ST. Single Mode, Duplex Mode, Simplex Mode, and Multi-Mode Testing: Special testing equipment is required for Fiber Optic Cable assemblies.




Discrete Mil-Spec Style, D38999, Micro D-Sub, Standard D-Sub, General “Off-the-Shelf”

Teflon Insulation, Non-PVC, MultiConduction Shielded/Jacketed


RG59, RG316, RG402, RG405, Rigid

Discrete: Cable types: Teflon Insulation, Non-PVC, MultiConduction Shielded/Jacketed


Standard point-to-point testing is done for custom I/O cables using an Ohm Meter. Custom extender boards have been developed to test custom I/O cables that interface with backplanes, which will test the entire chassis system.

Coxial RF Special testing equipment is required for measuring insertion loss for RF cables In the prototyping stage or for low volumes, this is not practical.

Fiber Optic : FC, LC, SC, ST, MT, QSFP

50/125um, 62.5/125um, 85/125um, 100/140um, Armored, ribbon, MultiMode, Single Mode, Duplex Mode, Simplex Mode

Special testing equipment is required for Fiber Optic Cable assemblies.

TABLE 1 Connector I/O Solutions.

a small area, right angle connectors cannot be used. Insertion loss numbers need to be very low with RF cable, so this determines the type of cable selected. When using rigid or semi-rigid coaxial cables in a chassis, 3D modeling is required to determine the actual layout of all cables needed for a chassis. The cables need to be laid out in a manner that can be converted into a 2D drawing for each cable assembly. Tight tolerances are needed for this application, as are special manufacturing sequences when installing these types of cables into a chassis. This can, however, be an expensive solution, particularly in the prototyping stages. Optical cabling often needs special trays to support the cables within the enclosure. In the case of fiber ribbons, consideration must be given to providing additional fibers for future repair and replacement. One of the important considerations for fiber optic I/O cabling is the minimum allowable bend radius. Fiber optic signal integrity can be affected if the bend radius is too small. Although there are some new fiber cables on the market that allow much tighter bends, a good rule of thumb is the “soda can” rule, which suggests a bend radius of no less than 35 mm, equivalent to the curve of a typical soda can.

Hard-mounting connectors and cables is a very flexible approach that works well in low volume applications. There are probably at least one or two such cables in any enclosure system, even if another approach is the primary solution. This sort of approach, however, presents several serious issues. Having a large number of separate cable assemblies is labor-intensive to assemble, test and troubleshoot. Each assembly requires its own test fixture and documentation, and if tested with standard bench equipment, highly trained technicians are essential. In addition to the labor cost associated with assembly, testing and installation, discrete cable assemblies are a known point of failure because over time inevitable movement of the cable bundles can result in failure at the termination point. Enclosures filled with a maze of such cable assemblies can be a nightmare to debug because technicians can inadvertently damage cables while trying to reach other cables. There is a growing need for EMI filtering, which creates additional signal integrity challenges, and using cable mounted filters to route high-count I/O out of the chassis requires a considerable amount of space.

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Special I/O Slots for Cards with Faceplates

This is one of the most straightforward solutions. It involves dedicating one or more backplane slots for plug-in cards that are dedicated to bringing I/O to or from all the other cards in the system through the backplane. In typical enclosure systems designed for field or vehicle deployment there is almost never space behind a backplane for rear transition modules (RTMs). Special I/O slots for front removable I/O cards can serve the same purpose as RTMs and work in much the same way. As easy as such cards are to design, they have some serious limitations. First, in most such systems the front panels of cards are behind protective covers, which eliminates any possibility of bringing I/O off the faceplates. In addition, backplane slots are typically too valuable a commodity for any function that does not have to be removable. The primary drawback is related to the issue of front covers. The types of rugged circular connectors used for I/O in these systems are too large for typical front panels, and are designed for panel or bulkhead mounting and not for right angle faceplate applications. The lack of appropriate connectors for faceplate applications is almost certainly because the faceplate of plug-in cards is almost never the desired surface for I/O in deployed rugged systems.

Sidewall I/O Panels Cabled

These consist of three solutions that all support an integrated I/O panel for sidewall mounting. The only difference between the three approaches is how they are connected to the rest of the system. We will first address an I/O panel that is connected by removable cables to the primary backplane. There are a number of advantages to mounting all the I/O connectors on a rigid printed circuit board. This is why this feature is common to all three approaches. An example of a rigid I/O panel is shown in Figure 1. The first obvious advantage is that PCB-mounted I/O connector assemblies require much less labor to assemble than their direct cabled cousins. The I/O panel is easy to test and is quite reliable because the termination is rigid. For cabling to the main system, the

Figure 2 Example of a Rigid-Flex-Rigid interconnect assembly.

Figure 3 Rigid-Flex-Rigid assemblies inside an enclosure.

I/O signals can be organized as needed and brought to one or more cable connector. This can be a flat flexible cable such as a ribbon cable or a shielded flex-circuit. Alternatively, a discrete wire connector can be used, or finally, some combination of connectors. The advantage to this approach is that there are cable connectors available that can be mass terminated, which is less costly than individual cables to each sidewall connector. Also, cable assemblies with a large number of wires are more efficient to test and install than many separate cables. Finally, the cable assemblies can be tested separately from the printed circuit panel. The ease of assembling the I/O panel and the use of mass-terminated flat flex cables

reduce labor, and the compactness of flat cables uses less interior space than separate cables to each circular connector.

Rigid-Flex-Rigid Assemblies

As the name implies, there are three subelements to a rigid-flex-rigid (RFR) interconnect structure: the main board, the flex PCB and the I/O board. The main board is where all the signals are generated, such as in a backplane. The flex element is an impedance-controlled flexible circuit board that is integral to the two rigid boards. The I/O panel is a second rigid section mounted with I/O connectors. All three sections are fabricated at the same time. Figure 2 shows a typical RFR interconnect. RTC MAGAZINE MAY 2012


Copyright Š 2012 RTD Embedded Technologies, Inc. All rights reserved. All trademarks or registered trademarks are the property of their respective companies.


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Figure 4 Typical Direct-Plug Interconnect assembly.

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There are several advantages to using the RFR approach. The RFR interconnect structure provides a constant impedance from point A to point B on a given signal path. Because it is assembled as a single structure, with the lack of intervening connectors, reflection is minimized. All the signal planes are surrounded by ground or power planes, which minimizes crosstalk, and the structure behaves well under high vibration and shock environments. Finally, this approach is usually the most compact solution possible. The labor cost required for separate cable assemblies and their testing is eliminated. Rear access to the connector pins at each end of the circuit allows accessible test point locations for high speed signal measurement. Increasingly, systems are turning to rigid-flex cabling. The combination of a flex circuit for tight corners paired with a rigid PCB for the I/O connectors is ideal for space-constrained chassis or boxes. Figure 3 shows such a RFR assembly installed. There are however a few limitations to this approach. RFR design is typically very costly, and the assemblies are more expensive because of the specialized materials and processes used in their fabrication. Because design and tooling requirements make this solution more costly, it is best for applications with higher volumes, where NRE costs can be distributed across many units. When volumes are expected to be significant, this approach should always be considered.

Connectorized (DPI) Risers and Mezzanines

The direct plug interconnect (DPI) is implemented with a direct connec-

tion between the main board and the I/O panel by means of a board-to-board connector. When attached at a right angle to one of the edges of the backplane, any family of typical backplane connectors can be utilized. The I/O panel can be located at right angles to any one of the four edges of the backplane or even as a rear mezzanine by using stacking connectors. This flexibility together with the varied mounting options for the subrack within the enclosure allow the I/O panel to be placed on almost any desired face of the system enclosure. The compactness of DPI preserves one of the important advantages of the RFR approach. And like RFR, the costs associated with assembling and testing interconnecting cables are eliminated. The important advantage of DPI over RFR interconnect is cost. Figure 4 shows a typical DPI interconnect. This approach is typically more reliable than either of the cabled approaches and equivalent to the reliability of any of the card-to-backplane slot connections. The connectorized DPI approach is more expensive to implement than the cabled approach first mentioned but significantly less expensive to implement than the RFR approach. The DPI offers an excellent solution to intermediate volume programs. It offers a compact reliable solution that is easy to test and efficient to assemble. Silicon will always move ahead of the rest of the system components, and systems will struggle to keep up with new silicon capability. At the present time there are a number of efforts within VITA to define both higher-speed MIL 38999 connector implementations as well as to define interface strategies for a number of new small form factor standards. In time, new connectors will populate the backplane slots, I/O connectors will get new faster inserts, and the fiber content of I/O cables will increase. Despite such inevitable advances, the five basic approaches to backplane I/O will likely remain for the foreseeable future. Elma Electronic Fremont, CA. (510) 656-3400. [].

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Android: Breaking Out of Phones and Tablets

Android—At Last A Ubiquitous Embedded OS? The Android operating system has established itself in a vast number of mobile devices. Now developers are eyeing expanded application possibilities for this dynamic software. Here is a survey of some of those attractive, but uneven, possibilities. by Bill Weinberg, Olliance Group (A Black Duck company) and

This article is the third in a series written for RTC discussing the potential and reality for developing and deploying ploration embedded systems using Android. The your goal first, “Android Moves Beyond Mobile” k directly (RTC, September 2009), introduced the age, the source. then-outlandish idea of using the mobile ology, OS to build intelligent devices beyond d products its core domain of mobile handsets. The second, “Android—Google’s Mobile Platform and its Capabilities for Embedded” (RTC, July 2011), highlighted the expanding application space for Android but also examined the gaps in its capability set for many types of smart devices. nies providing now We solutions now continue the discussion, paying ion into products, technologies and companies. yourof goalthe is to research the latest specific attention to the Whether progress ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you Google mobile OS and to both actual you require for whatever type of technology, potential in specific markets and productsand you are searchinginroads for. and applications. These domains include those listed in Table 1.


Automotive systems break down roughly into two broad categories: critical systems control and in-vehicle infotainment (IVI). The first addresses core functions and safety-critical op-

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eration in engine/ignition control, antilock braking, steering, etc., and is the domain of RTOS-type platforms with small resource footprints. The second, IVI, encompasses smart dashboards, GPS devices and “head units” that integrate these and other functions in a single box. It is these applications that


Get Connected with companies mentioned in this article.

today garner attention in the press and in the boardrooms of automotive OEMs and the Tier I suppliers that serve them, because these IVI systems increasingly define and differentiate the vehicle occupant experience. A consortium of the leading OEMs and Tier I suppliers, Genivi, was launched

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in 2009 by BMW, Wind River, Intel, GM, PSA, Delphi, Magneti-Marelli and Visteon, to “foster a vibrant open-source IVI community” by delivering an open-source platform consisting of Linux-based core services, middleware and open application layer interfaces, and by engaging developers to deliver compliant applications. Originally building on MeeGo, Genivi today supplies an open specification with a range of compliant platforms from OSVs and community sources. To some degree Android is the “competition” for Genivi and also for GM OnStar systems (based on QNX), but to date this is primarily only in aftermarket applications such as GPS devices and media systems like the Clarion Mirage. One exception is the IVI system in Renault Clio and Zoë vehicles. So why isn’t Android coming to an OEM dashboard anytime soon? Basically, it’s “an impedance mismatch.” For one thing, Android releases come too often for the conservative automotive segment and its 5- to 10-year design cycles. The other issue is that despite efforts from both handset makers (Motorola Cliq/Blur, HTC SenseUI, etc.) and from OSVs with add-on UI products (FST FancyPants and Mentor Graphics Inflexion), automotive OEMs seek a truly differentiated user experience (UX). Therefore they have set their sights “lower” in the stack for a common platform, ensuring that each vendor/ vehicle platform will be unique and making cross-brand application interoperability unlikely. There is, however, another path to market for Android in IVI. OEMs and Tier 1 suppliers are looking at cutting costs through processor consolidation in their head-unit devices, in particular onto ARM and IA silicon. Enabling the integration of IVI, CAN and MOST stacks on a single CPU will likely be done with embedded virtualization technology (from OK Labs, Wind River and others). With Genivi, AUTOSAR and legacy RTOS stacks liv-

Automotive (IVI)

Consumer Electronics

Defense and Aerospace

EIT and Office Automation

CPU Support

ARM / IA (Intel Architecture including Atom)


IA / Power

Real-time Response



Cost Sensitivity


GUI Open App Platform Certification Needs

Industrial Control



IA / Power

























Security and Safety




TABLE 1 Key requirements compared across markets.

ing in virtual machines (as “guests”) on a single piece of silicon, adding Android to run apps from Android Play becomes a snap.

Consumer Electronics

Consumer electronics manufacturers, primarily in Asia, have embraced Android for next-generation digital TVs, set-top boxes, DVRs, media players and other CE devices. Many of these devices are built on the MIPS architecture, and MIPS Technologies and their partners have invested substantially in optimizing Dalvek to run well on MIPS—a 4 to 5x speed-up, according to MIPS marketing—and in creating reference implementations. With good support for ARM and MIPS and other relevant hardware, consumer electronics as a segment has enjoyed the most success with Android beyond mobile. A quick glance at the CE retail space reveals announcements of Android-based TVs, IPTV boxes, media players, controllers and other

products from LG, Motorola, Philips, Samsung, Sony and Vizio, as well as lesser-known brands.

Enterprise IT and Office Automation

Over the last decade, Linux has won countless designs in both enterprise networking (routers, access points, firewalls, etc.) and in office automation (printers, copies, MFPs). Most of these systems are closed devices—they support field upgrade (reflashing) but not unconstrained download of new applications and functions in the manner of Android-based smartphones and tablets. Android is finding its way as a general purpose embedded OS into this design domain, primarily by manufacturers wanting to leverage Android’s Java programming model and increasingly familiar GUI. But it is not being done to enable users to download and play Angry Birds (or even more useful apps) on routers and copying machines. Enterprise IT (EIT) is leveraging RTC MAGAZINE MAY 2012


Tech In Systems

Arguments For and Against Android Arguments For Android

Arguments Against Android

• Ubiquitous—Android is increasingly ubiquitous, and so is the expertise to develop systems with and apps for it. Furthermore, it leverages an even larger global community of developers already fluent in Java and other programming disciplines. • Open Source—with the release of Android 4.0, the OS is generally considered to be “open source” (again), giving OEMs the ability to customize and enhance for a range of new application domains. • OEM-Friendly Licensing—OEMs have in general made their peace with license compliance when deploying the GPLv2 Linux kernel. Far more forgiving (“liberal”) is the Apache 2.0 license that applies to the majority of Android code, letting OEMs modify and redistribute with minimal disclosure requirements. • Linux—As of Q1/2012, Android no longer forks Linux. Instead, changes unique to Android have been merged into the tree under a special architecture branch, assuring that the core of Android will track mainstream Linux evolution. • Paravirtualization—since the underlying Linux kernel and hardware-dependent parts of Android are supplied in source, the platform can be paravirtualized for execution on processors with hardware virtualization support. This capability offers developers and OEMs the option of addressing some Android shortcomings (security, performance) by running the OS as a guest of a hypervisor, alongside more secure and/or higher performance software (including vetted instances of Android itself).

• Size—Android is too large in both source and binary forms for many application types. Its massive source base is too large to certify and the derived binaries can outstrip the resources of smaller embedded designs. • Overkill—Android, between the kernel, application framework, and including “hygiene” apps, is far richer than many (most?) intelligent devices need. Strip out the apps and sections of the framework and it’s not “Android” anymore—not all apps will run, etc. • Application Architecture—the Android programming model is optimized for building mobile handsets (i.e., Activities, Services, Broadcast receivers and Content providers). While that model can be stretched and bent to fit other paradigms, Google’s OS is still at heart best suited for smartphones (and maybe for tablets). •P  erformance—while the Dalvik run-time engine has been optimized for most silicon architectures, Android is still fairly “heavy” and can overwhelm modest processors and lean memory systems, as evidenced by sluggish system response and sub-par application performance on low-end (single core) handsets. •R  eal-time—Android, like Linux, in its unadulterated form has somewhat limited real-time response capabilities. That being said, most embedded applications don’t really have particularly stringent latency requirements. When they do, there are many means to meet those requirements, including “ugly” shortcuts around standard system mechanisms (true for Android and true for many legacy RTOSs as well). One area of concern for latency-sensitive systems is Android power management, whose aggressive sleep states of course degrade responsiveness. It can be disabled, of course. •S  ecurity—Android native security combined with both vulnerable and outright malicious apps presents a grim picture for security conscious developers and deployers in general. However, it is probably no worse (and likely better) than many/most legacy RTOSs and other platforms it replaces. And, Android’s global developer community makes aggressive efforts to patch and update to address known exploits and other threats. • Reliability—Users report that Android phones crash a lot. One study reported that low consumer satisfaction drives Android device return rates as high as 40%. Reliability is paramount to intelligent device design: not all applications are mission-, safety- or life-critical, but even a failed toy or fun gadget can be business-critical to its manufacturer and distributors. • Forking—the flip side of liberal (Apache) licensing is that developers and deployers can customize Android beyond recognition. Forked Android implementations are fine for closed box systems, but a major selection criterion for the OS is its ample and growing portfolio of 400,000+ apps in Google Play (a.k.a. the Android Market). If open devices can’t run a significant number (or they run badly), then the whole ecosystem suffers.

Android as a platform for Enterprise Mobility—to deploy internal apps and enhance mobile worker productivity by giving them access to enterprise assets in company data centers and in private and secure public clouds. This BYOD (Bring Your Own Device) paradigm lets EIT staff add software to employee-owned Android devices to enable remote productivity and ensure the security of businesscritical data. Numerous vendors of Mobile Device Management (MDM) and mobile virtualization solutions offer Androidbased EIT mobility software, ranging



from application-level sandboxes to thin clients to virtual machine platforms to multi-function MDM suites that provision, manage, monitor and even wipe Android-based devices.

Defense and Aerospace

In theory, Android and Androidbased devices fit the increasing trend for acquisition of COTS solutions by military, government and civilian aerospace contractors and users. In practice, the development and deployment profile of Android in Aerospace and Defense (A&D) has encountered several key limitations

important to military and aerospace— security and certifiability. In terms of security, Android, at least in its mobile incarnation, is notoriously susceptible to exploits of all types: ranging from zero day attacks, processlevel denial of service, API and document-based exploits, to malicious apps in standard app stores, especially Google Market and Android Play. Moreover, the Android platform includes native encryption, and while security-minded integrators and OEMs could certainly deploy stronger measures, many apps and much third-party-ware blithely employ

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native encryption methods like secure sandbox apps. In addition, Android, starting with the underlying Linux kernel, bionics libraries and going right up through the rich Android m/w framework, is too large, complex and dynamic to pass current certification regimes such as Common Criteria EAL and FIPS 140-2. Such disciplines are optimized for code bases of 10-15K lines of code, although Linux-based systems have undergone EAL4+. However, the total Android stack size numbers are in the tens of millions of lines of C and Java coming to approximately 6 Gbyte of source code in total. As with EIT, use of Android for enterprise mobility, A&D (and government IT too) is looking to virtualization to facilitate development and deployment of Android devices and applications. Full hypervisors and less feature-rich separation kernels address both the above concerns by presenting a much smaller code base, streamlining certification and offering a diminished “attack surface” to malware as with the NSA’s High Assurance Platform “HAP.” The use of Android in so-called “superphones,” smart radios and other hardened communications devices, responds to the same requirements as EIT BYOD: let service personnel carry a secure single device with a friendly and familiar user experience for regular communications, and “military grade” security for mission-critical messaging, voice and data transport. This paradigm also serves to cut costs in line with COTS procurement policies. Re-flashing or special ordering COTS Android handsets and tablets with High Assurance firmware and middleware developed by integrators and government contractors is orders of magnitude less expensive than developing, deploying and maintaining traditional equipment.

the Linux kernel that lies underneath Android. The Java execution engine (Dalvik), while boasting excellent performance, is not particularly well suited to latencysensitive control and sensor applications, although it is more than sufficiently able to communicate with dedicated hardware modules to perform those functions. Where Android really comes into play is in creating the control panels and operator interfaces to program and run

control and instrumentation systems. Developers are drawn to using Android for both communications with dedicated control/instrumentation hardware and with “back office” resources. The attractive and familiar user interface, rich complement of services and middleware, and integrated networking make CTOS Android-based devices and custom interface devices ideal to support both control and instrumentation apps.

Industrial Control and Instrumentation

Industrial control and instrumentation systems seem the least likely of candidates to be powered by Android, and yet developers are seriously considering using Google’s mobile OS here as well. For nittygritty control applications, they are mostly building native applications and drivers on Untitled-19 1


3:55:28 PM RTC MAGAZINE 2/3/12 MAY 2012

Tech In Systems


Medical monitoring and treatment devices based on Android face comparable challenges to that of the Google mobile OS in A&D—certifiability and security (privacy). But the attraction of a platform that comes ready-to-use with hundreds of medical apps, touch screen support, networking and other must-have capabilities is overcoming those key limitations. Just as Linux did before it, Android is mak-

ing its way onto medical systems for diagnosis and monitoring—not life-critical, but those that confer convenience and a friendly user experience to clinicians and patients alike. Suggested medical device applications for Android include hospital room patient monitors, remote monitors and surgical displays, portable medical records input/display devices, pharmaceutical dispensers and scanners—anything where

user interaction is paramount. Another area that has faced certification issues is out-patient monitoring equipment. To some extent, suppliers have side-stepped the issue by creating apps and mobilephone add-ons for COTS Android phones, letting patients automatically report their vitals and long-term test data over 3G and 4G mobile networks. In the higher-stakes area of therapeutic and imaging devices, medical OEMs are following the same path as their peers in industrial automation—use Android devices with built-in displays as front-ends to certified proprietary devices requiring certification from the FDA and other regulatory bodies. And in scenarios where even separate displays face certification, OEMs obtain it for a single common design destined for reuse across a range of life-critical systems.

Is Android the Right Choice?

Despite its expansion across the segments described above, Android is still probably not for everyone. Whether Android fits your particular intelligent device application will depend upon the unique combination of considerations endemic to your business and your particular project. See Table 1, which calls out arguments for and against the use of Android with rationale teased from across application segments and the particulars of the platform. Also, see the sidebar titled, “Arguments For and Against Android.” The sheer number and scope of arguments against using Android beyond mobile might in the future doom the little green robot to dwelling in smartphones and tablets. However, the smaller set of for arguments is quite compelling, and our verdant friend is marching across the field of device applications with no signs of pause or retreat. Like I used to say for embedded Linux, the Google Android OS is finding broad deployment not so much because of its attributes, but in spite of them. Olliance Group []. Linux Pundit [].


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Android: Breaking Out of Phones and Tablets

Android Goes Beyond Google Android is finding uses in more than just the mobile market. The coming expansion further into these markets will involve opportunities and risks and require resources beyond the intentions of Google. by Art Lee, Viosoft


s of Ice Cream Sandwich (ICS), Android as delivered by Google is a software platform largely targeted at the mobile handset and tablet market. The Google Android software development environment and programming interfaces (APIs) are geared

toward enabling applications written for this market. For the non-mobile market, the challenges and opportunities begin with the breakaway intent to repurpose the Android platform for any consumer product that requires a touch-oriented user interface, high-performance mul-

timedia recording and playback, and/or application portability. We will look at some of the challenges associated with these product scenarios as well as examine a case study of an approach developed by Viosoft to assist OEMs in this task.






Voice Dial





Media Player Photo Album






Window Manager

Content Providers

View System

Notification Manager

Package Manager

Telephony Manager

Resource Manager

Location Manager


LIBRARIES Surface Manager OpenGL|ES

Media Framework Audio Manager





Core Libraries




Da | vik Virtual Machine






Radio (RIL)



LINUX KERNEL Display Driver

Camera Driver

Bluetooth Driver

Shared Memory Driver

Binder (IPC) Driver

USB Driver

Keypad Driver

WiFi Driver

Audio Drivers

Power Management

Figure 1 Android Architecture diagram.



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Android Application Android Application Android Application DALVIK VM Viosoft “Container” DALVIK VM Control Remote “Container” Android DALVIKApplication VM Native Process “Container” DALVIK VM Native Process “Container” Native Process Native Process

Native Linux Shared Libraries


Bionic Libraries Word Processor

Applications written for traditional embedded devices are specific to the underlying hardware architecture and OS that host the platforms. In many cases, embedded applications need to be rewritten, or ported to a specific platform. This process, referred to as “re-targeting,” can significantly add to the costs of the development and testing of embedded software. This is where the appeal of the Android platform’s application portability comes in. The concept of “write once, run many” suggests that the same application binaries, written for and tested on one Android platform of a given architecture, shall run identically on another Android platform of a different architecture. This is not a new concept but rather one that existed when James Gosling of (now defunct) Sun Microsystems gave birth to the Java programming language more than a decade ago. The generally interpretive nature of the language means that Java applications tend to run slower than those for compiled languages (C/C++). Android leverages Java, but not entirely. To better understand this, let’s look more carefully at the Android Software stack (Figure 1). Android applications (in blue) are written in Java, but they rely on the application framework, associated libraries and runtime consisting of over fifteen million lines of some Java and mostly C/C++ code. The partition between Java and C/C++ language in the Android design is premised on performance, with “slower” code on the Java side, and “faster” code on the C/C++ side. Under this framework, the developer is presented with the option to 1) write a pure Java application that relies exclusively on the pre-established C/C++ “sandbox” for acceleration and achieve 100% portability, or 2) write a self-containing C/C++ application wrapped in Java that is specific to a given architecture. Given the current state of near homogeneity of Android around the ARM architecture, and the success of vendors like Rovio (Angry Bird) who have taken the latter approach, the Android developer market has spoken in favor of performance. Recent releases of Android have added a Hardware Abstraction Layer (HAL) to address the needs of high-performance native applications. The Android HAL wraps the Linux kernel drivers to create a


Portability versus Performance

Full Featured Media Center

Open Office Suite

Native Process

Native Process

Media Framework

SMP Linux static kernel (Android Enabled) Linux static device driver

Linux static device driver

Linux static device driver

x86 core

Linux static device driver

x86 core

AMD Linux loadable FireGL module Device Driver


G-Series APU Figure 2 Integration Framework for Android.

layer of abstraction for native applications to access location (GPS), Wi-Fi, 2D/3D graphics, audio/video and other hardware specific to a mobile use profile. While the Android HAL has helped to simplify hardware integration for OEMs and device manufacturers, it’s not clear how the HAL delineates from the abstraction of the Linux kernel itself, or how it will evolve to incorporate non-mobile use cases.

Android, in Embedded and beyond Google

In advocating the adoption of “Android beyond Google,” we envisage Android being ported for and integrated into products that do not meet the mobile use profile of smartphones or tablets, or necessarily use a CPU powered by the ARM architecture. Yet, these products still require and benefit from the touch GUI, application portability and multimedia capabilities and resources that Android provides. Printers, digital camcorders, set-top boxes and smart TVs are just a few examples of how Android can potentially be used outside of mobile. One of the primary challenges in repurposing Android is the ability for applications to (inter) operate in and out of the Android runtime sandbox. Just as with Linux appli-

cations, native (C/C++) Android code often needs to access runtime libraries for string or math operations. On standard Linux desktops, these operations are provided as part of the GNU runtime environment (i.e., glibc and libm). For performance and footprint reasons, these are supplanted by the Bionic libraries in the Android runtime environment. While both Bionic and the GNU libraries are largely semantically and syntactically equivalent, they are not runtime compatible. This means that Linux application binaries cannot run in the Android sandbox, and vice versa. A second challenge adds to this incompatibility divide: most, if not all Linux applications have a graphical interface that relies on X11, whereas Android applications rely on the Android framework and HAL to render graphics. OEMs and developers must develop approaches to reconcile between Bionic and GNU libraries, and between X11 and the Android frame-buffer, as part of the strategy to benefit from embedding Android.

Integration Framework for Android

One such approach to reconcile between Android and legacy Linux applications is Viosoft’s Integration Framework for AnRTC MAGAZINE MAY 2012


Tech In Systems

droid. Under this framework, applications are deployed under two separate containers— one hosting Android and the other X11-based Linux applications. Applications in the Linux container can be launched and controlled by the Android desktop, while maintaining full

compatibility with existing legacy libraries and drivers. Figure 2 shows a high-level architectural diagram of the framework. To verify the viability of this approach, we’ve implemented a full media center for Android on the AMD G-Series STB refer-

Figure 3 Android 4.0 desktop with native application icons (circled in red).


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ence board. Before diving into the implementation details, let’s have a look at the hardware. The G-Series family combines two 64-bit x86 processors with a Graphics Processing Unit (GPU) that consists of 80 floating point engines. The STB reference platform that we used is clocked at 1.6 GHz, equipped with full HDMI /Component out, wireless and 10/100 Ethernet, 2 Gbyte of memory and a 320 Gbyte SATA drive. Utilizing the Integration Framework for Android, we were able to deploy a full port of Android 4.0 ICS, running simultaneously with other legacy Linux applications such as XBMC (Xbox Media Center) and the Open Office Suite. Porting Android to the G-Seriesbased STB was straightforward. Most of the code pulled from the Android for x86 projects ( org/) built and ran out of the box, albeit at VESA resolution. Nonetheless, this baseline enables us to leverage all of the applicable resources of Android. Our next step was to fine tune a variety of kernel drivers to take full advantage of the hardware capabilities of the STB, including full 1080p streaming/playback and network-

5/2/12 1:41:12 PM

tech in systems

ing support for both wired and wireless interfaces. Once this work was completed, we examined the X11 requirement by XBMC and Open Office and ensured that both the X11 server and Android graphics subsystem could share audio and video resources while executing out of two separate runtime containers. The Integration Framework for Android fundamentally acts as a bridge between the Android Application Framework and native Linux applications. As shown in Figure 3, icons are displayed in the Android Desktop for both XBMC and Open Office (circled in red). These icons are used to launch the respective applications, putting the Android desktop in the background. The launched application then has direct and full access to the underlying resources necessary to render graphics and audio/video contents. At the same time, other Android services will continue to respond to stimuli in the background, and if necessary, relinquish control of the display to solicit input from the user. For example, an incoming Skype call would interrupt an XMBC movie playback, giving the user the option to pick up the call. The end result is a surprisingly fluid and functional media experience, hosted by the modern look and feel of the Android frontend, while at the same time being fully capable of tapping into the large body of stable and functionally rich desktop Linux applications. The same environment can readily power a variety of real-world applications such as touch-based medical equipment products and user consoles for industrial control. An exciting aspect of this work is in the potential to repurpose Android toward different use profiles that have needs for Android and native Linux application interoperability. The ability to reuse existing code while benefiting from some of Androidâ&#x20AC;&#x2122;s modern capabilities can result in significant costs and time savings to OEMs. An essential challenge often presented to developers by multi-faceted environments like the Integration Framework is the lack of debug visibility for application logic that straddles runtime or language boundaries. When a function call crosses over from Java into C/C++, developers are often at a loss in their ability to follow through the flow in the process of tracking down a program defectâ&#x20AC;&#x201D;making a multi-lingual debug environment an indispensable tool for such

needs. Arriba for Android is the only tool of its kind to fully integrate mixed language, multicore and multidomain debugging for Android and Linux applications into a single environment. Arribaâ&#x20AC;&#x2122;s â&#x20AC;&#x153;run modeâ&#x20AC;? debug feature yields complete transparency to all layers of the Android-based platform, making it practical for the developer to visualize the flow of the system in its entirety. With this level of visibility and control, Arriba can dramatically reduce development

time and costs associated with product development. Bundled with the Integration Framework for Android, Arriba offers the OEM a complete environment to rapidly develop and deploy Android-enabled products with higher reliability and significantly lower costs. Viosoft San Jose, CA. (508) 881-4254. [].


XMC . +!





Technology For: Communication Industrial Instrumentation Medical Military Scientific Transportation



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10:05:38 AM RTC MAGAZINE 4/9/12 MAY 2012

technology deployed Data Acquisition with Small Modules

Solving Data Transport Challenges in Radar and Sensor Applications FPGAs have been shown as the ultimate guarantors of real-time performance for high-speed inter-processor and I/O communication in defense applications. It is important to select the appropriate architecture to meet performance metrics, and the appropriate development tools to meet time-to-market. by Rafeh Hulays, Ph.D, AdvancedIO Systems


he military and various national security agencies use high-power radio monitors, remote surveillance, satellite imagery and radar systems to monitor and detect hostile and illegal activities be-

fore and while they unfold. Systems are deployed remotely and sensor data are backhauled to central monitoring and coordination sites for processing. Figure 1 depicts a net-centric COMINT or ELINT wideband

UDP broadcast ADC






(optional) Delay Buffer

analysis application with real-time record and playback capability. Data are being collected and backhauled to a central location from multiple sensors for analysis. Today’s high-performance signals intelligence (SIGINT) systems require massive processing power to detect, identify and classify an enormous number of highly complex signals. SIGINT systems typically consist of a variety of functional elements such as signal processors—themselves often consisting of multiple processing elements—snapshot memory buffers, high-speed data recorders and bulk storage. All these may reside in multiple physical units, connected through highspeed data pipes. In many application dataflows, the processing elements within and between the distinct units need to be interconnected using switched fabrics. Real-time Command, Control, Communications, Intelligence Surveillance and Reconnaissance (C4ISR) applications such as these have a requirement to send raw sensor data in parallel to storage and multiple processing streams—a challenge that 10 Gigabit Ethernet addresses handily. 10 Gigabit Ethernet’s (10GbE) ubiquity, performance, portability and future roadmap make it an attractive highspeed interconnect for such real-time high-bandwidth situational awareness

SAN Wideband Spectrum Analysis Control and Tuning Narrowband Demodulators/ Signature Match


Figure 1 A typical high-level architecture for a network-centric signal intelligence system showing the major different elements interconnected by 10GbE networks.



Technology deployed

User Applications

Software Libraries

PCI Express


PCI Express

systems. This has led some to propose the use of commercial Ethernet cards or chipsets for defense applications. Unfortunately, such systems are unable to meet the stringent requirements demanded by such applications and this results in suboptimal performance. A robust and efficient connectivity solution to a networked signal intelligence architecture operating in real time must support high-speed point-to-point data pipes to transfer data between distinct units or chassis and high-speed networking of multiple units that need to share data with an extended duration line-rate burst. There is a requirement for a time stamping and synchronization interface to deterministically and precisely stamp packets entering or exiting. It is necessary to provide the ability to drop in a solution out of the box or tailor the transport layer protocol offload to the application, bus interface and host processor along with the ability to alleviate CPU burden by offloading intensive application processing operations or inspecting and dropping packets that are uninteresting before they ever get to the CPU. It must also be possible to modify the standard transport protocol behavior to tag but not drop the packets received with checksum errors. The system should be available in multiple form factors to accommodate different deployment scenarios. The choice of the User Datagram Protocol (UDP) instead of the TCP protocol was driven by the need for a low latency solution in a controlled network where packet loss is negligible. In such a network, it would be difficult to justify the higher latency resulting from the sliding window protocol used in TCP communication. In addition, retransmitting data at a 10 Gbit/s rate requires very large memory buffers on both the transmitting and receiving ends, which is both impractical and unnecessary in radar applications. In addition, memory buffers are best utilized to handle bursts of incoming data. It is therefore more efficient to use the UDP protocol, tag the packets having checksum error and allow the system architect to decide whether to drop or use them.

Interface Wrapper

Interface Wrapper



Figure 2 A complete system-level FPGA development framework solution includes optimized low-latency Linux drivers and APIs as well as the optimized controllers shown in Figure 3.

FPGA Technology as a Solution

AdvancedIO was the first company to introduce to the market 10GbE FPGA cards to solve the challenges encountered in data transport for sensor and radar applications. We argued that FPGAs have proven themselves in ruggedized systems and are deployed extensively in the military in some of the harshest environments. No other technology is able to match FPGA performance in processing large

amount of data in real time, an essential part of radar design. It is therefore the obvious choice to underpin a robust realtime data transport solution. The militaryâ&#x20AC;&#x2122;s need for high-quality and high-performance COTS solutions made it necessary that standard implementations be made available to perform high-efficiency UDP offload on various form factors such as XMC and PCIe. For applications demanding customization, RTC MAGAZINE MAY 2012


technology deployed

Remote Upgrade Controller

Clock Logic

UART Controller

PCI Express

10GbE Controller

SRAM Controller

SDRAM Controller

Peripheral Controller

Packet Bus

Packet Bus

Memory Bus

Memory Bus

Peripheral Bus


Packet Processing

Memory Tester

Memory Tester

Register File

Sandbox Figure 3 A high level view of the expressXG FPGA development framework from AdvancedIO. The top row components (in blue) are the controllers integrated into the hardware. The bottom row components are provided as an infrastructure for development.

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5/2/12 2:20:50 PM

Technology deployed

AdvancedIO pioneered the use of FPGA development frameworks, which eases and accelerates the process of developing and customizing applications. A development framework abstracts the details of Ethernet protocols and inter-

faces, memory controllers and host fabric interfaces, thereby reducing the development effort and schedule for designers to customize the transport protocol, to analyze, manipulate and route the data (Figures 2 and 3). A development framework must


V1121 Ethernet card Channel 1

Sensor ADC

Channel 0

Transmit Port 0




10 GbE

Management Port Channel 1 Transmit Port 1








Streaming Front End




Receiveit Port 1


Sensor ADC








Signal and Packet Processong Algorithms


Receive Port 0

Sensor ADC

at minimum abstract underlying hardware interfaces and Ethernet communications protocol functions. This allows developers to focus 100 percent of their time on application development and integration rather than spending time on getting all the exter-

10 GbE

UDP Offload Engine (UOE)

Figure 4 The architecture of the Streamed Front End (SFE) implementation over XAUI. The sensorâ&#x20AC;&#x2122;s data undergoes signal processing before being sent to the Ethernet module over XAUI.

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2:05:04 PM RTC MAGAZINE 5/2/12 MAY 2012

technology deployed

nal interfaces working on the FPGA card. A proper development framework must ensure application portability among FPGA device families and within the same family of cards. This significantly reduces the costs of future migration or upgrade cycles. The expressXG FPGA Development Framework developed by AdvancedIO consists of an interface wrapper and a user sandbox. The wrapper, a hardware abstraction layer, provides a robust user interface to all high-performance interfaces required for an FPGA Ethernet card to fully function. The sandbox region, where designers play, features easy-to-follow examples that will jump-start user application development and debugging. This is made available to engineers to add their own customizations and perform additional signal processing before the data is packetized and sent out to the Ethernet network. All features are intended to function out of the box and to promote the rapid coding and integration of high-performance applications with FPGA technology. The expressXG FPGA development framework enabled the development of a highly effi-

cient UDP/IP protocol offload engine that abstracts 10GbE communication. This enables engineers to focus on implementing their solutions without the need to worry about the nuances of 10GbE protocols. A carrier card (or the sensor card itself) is equipped with an FPGA that communicates with a 10GbE XMC module over XAUI as per the VITA 42.6 standard. A Streaming Front End (SFE), which is a small IP core that resides on the carrier’s FPGA, provides a user interface to the 10GbE module and replaces the software device driver typically used in PCI Express implementations (Figure 4). The 10GbE module has a built-in Ethernet protocol accelerator, which performs all of the functions required for UDP/IP communication over standard 10GbE networks. It also supports multicast and broadcast, which make it suitable for communication with several processing elements. For socket setup and diagnostics, the 10GbE module supports the Internet Control Messaging Protocol (ICMP) and the Address Resolution Protocol (ARP). The SFE has a simplified interface so that an engineer with standard socket pro-

gramming skills can be confident about integrating it within his or her application. It is lightweight so that it occupies minimal resources on the carrier board’s FPGA. This leaves plenty of room to implement complex signal processing algorithms without it having any measurable effect on system performance or cost. Here we have presented the overall requirements for net-centric COMMINT and ELINT systems and the technologies that can help an engineer implement a robust and scalable solution. UDP on 10 Gigabit Ethernet and powered by FPGAs helps meet the challenges of today’s modern systems. There is also a method to implement efficient data streaming that substantially improves performance. In addition, a development framework is available that enables the rapid customization of the transport protocol and helps implement algorithms to exercise the sensors’ data. AdvancedIO Systems Burnaby, BC. (604) 331-1600. [].


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technology deployed Data Acquisition with Small Modules

Avoid Bottlenecks Using PCI ExpressBased Embedded Systems Implementing efficient data movement is a critical element in high-performance embedded systems, and the advent of PCI Express has presented us with some very effective approaches to optimize data flow. by Jim Henderson, Innovative Integration


good friend will help you move, but a trusted friend will help you move the bodies.” Fortunately, I haven’t any direct experience to substantiate this old quip, but I chuckle at the premise. Embedded system architects occasionally need help moving as well, and for this we turn to our trusted friends DMA, bus-mastering, shared memory and coprocessing. Embedded systems are ubiquitous, used within communications installations, automobiles, cell phones and even table saws. Most systems interact with their environment through transducers connected to analog-to-digital converters (ADCs/ DACs), communications ports such as USB and Ethernet, and myriad other specialized devices. It is commonplace for such devices to generate or consume gigabytes per second, well beyond the capacity of a typical embedded processor to manipulate directly. Usually, this problem is addressed by including some form of coprocessing or direct memory access (DMA) within the embedded system. For example, consider the narrowband receiver inside a software radio depicted in Figure 1. A wideband IF signal



is digitized at 250 MHz, with 16-bit resolution, down-converting to produce 12.5 MHz of narrowband data. This operation might be implemented using a COTS device such as the TI GC6016 DDC or using custom VHDL firmware within an FPGA, such as a Xilinx Virtex 6. Regardless, the output data rate is substantially reduced— the complex, 16-bit output data samples are produced at 12.5 MHz, equivalent to just 50 Mbyte/s. However, even this mitigated rate may represent a substantial burden to an embedded processor. It might be necessary to implement a decoder to bring the signal to baseband, reducing the data rate by another order of magnitude before that rate is suitable for the embedded controller. In this scenario, the efficiency of data flow is improved by delegating the per-sample manipulations to the coprocessor, reducing the bandwidth from 500 to just 5 Mbyte/s. The bandwidth of the embedded computer’s bus is preserved by reducing its load. But in some situations, coprocessing is not feasible or desirable. Implementing the necessary coprocessing functionality might exceed available FPGA resources. Or, such computations may be deferred or

implemented on another system in nonreal-time. For example, it is commonplace to capture wideband recordings of signals to disk, subsequently analyzing the waveforms in environments such as Matlab. Multipath, Doppler fading and other impairments on a cellular transmission might be captured by a portable 250 MHz IF recorder mounted in the trunk of a car driving throughout a city. These realworld signals could subsequently be used to stimulate prototype receiver equipment in a lab. What architecture is required to implement such a system at these rates? Direct Memory Access (DMA) is a feature of many embedded systems that allows I/O subsystems to access memorymapped peripherals independently from the embedded CPU, microcontroller or digital signal processor. Once initialized, a DMA controller autonomously reads from source memory addresses and writes to destination addresses. Typically, DMA controllers initiate data movement when signaled by an external stimulus signal, such as an FIFO level signal indicating that data can be read or written to a device. Many modern DMA controllers provide substantial addressing flexibility, allowing transactions to/from fixed addresses (memory mapped FIFOs), address ranges (shared memory) and even noncontiguous ranges (image buffers). Since DMA responds to the stimulus signal independently from the CPU and is granted higher priority than the CPU in accessing the bus, DMA transactions are a mainstay for reliable, deterministic data flow in real-time applications. Nearly all desktop PCs and many embedded systems now incorporate PCI Express (PCIe) as the communications bus between I/O cards and host system memory. PCIe is a standard, point-to-point serial implementation that has displaced the earlier (parallel) PCI standard that was a dominant expansion card interface used until circa 2005. PCIe gained market acceptance very rapidly, primarily due to the signal routing density intrinsic to its serial implementation and its correspondingly scalable performance. PCIe traffic flows in lanes, each implemented as a matched

Technology deployed

Bypass SPECT INV Fs=250MHz

16 16 I/Q

Bypass CIC CIC /5






16 I/Q Fddc=12.5MHz

DDS DC125MHz Power meter Figure 1 Digital Down Converter implementation.

pair of differential signals implementing a bidirectional data path. Data flow is 8/10B encoded at a bit rate of 2.5 Gbit/s in the PCIe v1 standard, providing a rated 200 Mbyte/s for each lane. PCIe v2-compliant hardware doubles that bit rate to 5.0 Gbit/s, doubling throughput. To support high bandwidth devices, lanes may be bonded to improve throughput. For example, graphics adapters in desktop PCs often bond sixteen v2compliant lanes to establish an effective 6400 Mbyte/s bidirectional link between system memory and the GPU (graphics processor unit). Use of PCIe is not restricted to the desktop form factor. VITA Standard 42 combines the popular PCI Mezzanine Card (PMC) format with the PCIe serial fabric technology to support standardized PCIe peripheral cards in embedded applications, known as XMC modules (Figure 2). Likewise, VITA Standard 46 supports use of PCIe within VPX platforms, the popular rugged successor to VME (Figure 3). To effect a transfer, a PCIe device first arbitrates with the host processor(s) for memory bus ownership. Once granted, the master writes or reads small packets of 32- or 64-bit words to another memory-mapped peripheral, the slave. Packet sizes are governed by cache memories within the PCIe chipset. These are typically less than 2K words in size, although

they are frequently much smaller on the chipsets found in embedded systems. The slave device accepts or rejects the packet by emitting an acknowledgement or negative acknowledgement, respectively. This protocol allows for flow control if data is being sourced too rapidly for the slave by the master. PCIe cards typically implement embedded data movement engines that implement bus masteringâ&#x20AC;&#x201D;a specialized form of DMA transfer. Bus mastering offers several advantages compared to using a legacy DMA controller. While both DMA and bus mastering arbitrate with the host processor for access to the host memory bus (exhibiting similar transaction latency), each DMA transaction involves

both a bus read and write. However, a bus mastering peripheral can access onboard I/O devices via a local bus, so a transfer to system memory or another memorymapped PCIe peripheral requires only a bus write operation, effectively doubling the efficiency of DMA. Bus mastering transfers occur between a PCIe device and another memory-mapped peripheral. But the latter need not be memory, per se. For instance, one PCIe device may transfer directly to another, bypassing host system memory. PCIe systems can incorporate switch devices that allow multiple attached devices to communicate locally, mitigating traffic on the primary system bus. Traffic between such devices behaves as if

Figure 2 XMC Module with FPGA and Analog I/O. RTC MAGAZINE MAY 2012


technology deployed

Figure 3 Embedded VPX System.

interconnected directly. Switch devices are typically configured either statically from flash ROM during system initialization or dynamically by the host processor during OS initialization. Once configured, even persistent PCIe traffic between local devices will consume no system bus bandwidth. The high-speed cellular data storage application referenced earlier seems a suitable candidate to exploit inter-device PCIe communications. One would assume that a high-speed PCIe digitizer could bus master directly to a RAID disk controller to implement wideband recording, without loading the host system bus or processor. While local, inter-board communications is exploited frequently in VPX platforms to share data between two FPGA cards, it is rarely feasible when mixing PCIe devices from multiple vendors. Most RAID controllers, for instance, are closed designs provided with drivers only for popular operating systems such as Windows or Linux. These drivers perform all low-level access to the array and are the exclusive vehicle for interacting with the array. The manufacturers do not document or support use of the RAID controller as a slave device. The zero work solution is to accept the implicit inefficiency of a single bus mastering transfer from the source PCIe device to host system memory. If acquiring at a relatively modest rate like 250 MHz from 16-bit ADC devices, this represents a load of only 1000 Mbyte/s on the system bus (500 Mbyte/s for the BM from the acquisition device to system memory, and another 500 Mbyte/s when the RAID controller BMs from system memory to the RAID array), which is well within the available bandwidth of modern motherboards and RAID subsystems.


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But if the data rate escalates, this approach becomes increasingly unattractive. A typical i7-based embedded system will provide approximately 6-8 Gbyte/s of aggregate system memory bandwidth. If the acquisition card samples at 2 Gsamples/s at 12-bit resolution with no packing, the system bus utilization becomes an unmanageable 8000 Mbyte/s for the realtime storage to the array. Interestingly, CPU utilization is nearly zero—the CPU is involved only occasionally to initiate a write of data to the array when the acquisition device completes each bus mastering transfer. But the miniscule CPU usage is irrelevant in this application; We’re bus-bound. To address this problem, it is necessary to redesign the interface on the acquisition device. Instead of using a bus mastering interface in which the module autonomously delivers data into host system memory—consuming host memory bus bandwidth—available memory on the acquisition card must be mapped as shared memory. Acquired samples from the ADC on the card are stored into consecutive memory locations in onboard memory, similar to a FIFO. But these memory locations are also mapped into the memory space of the host, and appear as a memory bank addressable by the host CPU and the RAID controller. The key advantage of this approach is that during acquisition, samples will appear in the memory space of the read-only memory, without requiring a memory bus arbitration or write cycles. Effectively, the data transfer is free. Of course, when the RAID controller reads from this memory area, the bus will be utilized normally and a fraction of the available bus bandwidth will be consumed. However, the utilization is halved, compared to the bus-master scenario described earlier. On modern acquisition cards that employ reprogrammable FPGAs, this sort of repurposing is relatively easy to implement. What a difference compared to the cut and jumper world in which we used to live! Innovative Integration Simi Valley, CA. (805) 578-4260. [].

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An air-cooled PrPMC/XMC module based on Freescale Semiconductor’s quad-core QorIQ P2041 processor is an optimal solution for industrial and communications applications that require a high-performance PowerPC processor on an industry standard mezzanine module. For designs utilizing a PrPMC/ XMC processor mezzanine installed on a carrier baseboard, the XPedite5600 from Extreme Engineering Solutions offers an easy upgrade path to a higher-performance processor mezzanine subsystem. The XPedite5600 features include a Freescale P2040 or P2041 processor with four PowerPC e500mc cores running at up to 1.5 GHz and implemented on an air-cooled PrPMC/ XMC form factor. The module supports up to 8 Gbyte of DDR3-1333 ECC SDRAM along with two rear I/O SATA 3.0 Gbit/s ports. It includes a x4 PCI Express Gen2 XMC interface or 32-bit PCI PMC interface plus one front panel and one rear I/O USB 2.0 port. There are three rear I/O Gigabit Ethernet ports plus one on the front panel and two I/O RS-232/422/485 serial ports each on the front and rear panels. The XPedite5600 supports Linux, Wind River VxWorks and Green Hills Integrity BSPs. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

SBC Boasts Intel Gen2 Core i7/i5, Celeron 1.6 GHz to 2.5 GHz

A new single board computer features 2nd generation Intel Core i5-2510E (DC), i7-2710QE (Quad) and Celeron B810 processors, which integrate Intel’s HD Graphics 3000 engine and the memory controller functions of a traditional GMCH. The QM67 Platform Controller Hub (PCH) provides PCI Express 2.0 I/O bandwidth at twice the speed (5 Gbit/s) of previous Intel Core or Core 2 Duo platforms. The ADLQM67HDS from ADL Embedded Solutions also supports a broad set of features. The ADLQM67HDS has a discrete 8-bit digital I/O port as well as separate DVI-I and HDMI interfaces. The onboard DVI-I connector provides signaling for analog VGA, and can be configured as an HDMI output with audio. The internal HDMI port can be configured to DVI-D through cabling options. The ADLQM67HDS also has 4x RS-232 COM ports, 4x SATA with RAID 0, 1, 5 and 10 support. Two of the ports support up to SATA 6G while the other two support SATA 3G. 10x USB2.0 with 4x onboard connectors, two bootable Gigabit Ethernet LAN, HDA 7.1. Expansion capacity is provided through a custom 2x40-pin PCIE connector that is configurable as one x4 PCIe lane or four x1 PCIe lanes with backplane accessories provided for plugging standard PCIe peripheral cards. The 2nd generation Intel Core processors with 256-bit ring bus architecture, AVX instruction set and integrated HD 3000 graphics engine provide extremely powerful floating point and vector processing performance. Early interest in our Intel Sandy Bridge product lines is in applications such as military communications, military and industrial minirouters, military command and control, scientific image processing, and all manner of DSP and heavy computing applications. This allows reduction in overall system size, weight and cost by removing the need for peripheral graphics and DSP boards, which are often used to offload this work. ADL Embedded Solutions, San Diego, CA. (858) 490-0597. [].



Intelligent Vehicle Displays: Upgrade Opportunity for Harsh Environments

Two rugged intelligent vehicle displays are designed for deployment in harsh environments such as tanks and other ground combat vehicles for applications including embedded training, 360° situational awareness, terrain visualization and Force XXI Battle Command Brigade and Below (FBCB2) as well as commander and gunner display consoles. Both integrate advanced processing capabilities to deliver a complete, self-contained, COTS display solution with a high Technology Readiness Level (TRL) that enables prime contractors and OEMs to shorten time-to-market, minimize program risk and more easily add value to create competitive advantage. The IVD2010 and IVD2015 from GE Intelligent Platforms also include the advanced thermal management capabilities necessary for deployment in confined spaces. The 10.4” screen IVD2010 and 15” screen IVD2015 XGA (1,024 x 768) resolution smart displays both incorporate not only an Intel Core2 Duo processor operating at 2.26 GHz but also a 96-core NVIDIA GT 240 GPU. Together with 4 Gbytes of SDRAM3 memory and four simultaneous video inputs, this equips them to handle the most demanding, sophisticated graphics applications such as picture-inpicture and symbology overlay, stitching multiple videos into a single panorama and allows high-performance GPGPU applications to be deployed directly on the display unit. Both the IVD2010 and IVD2015 also include display features designed to deliver optimum screen visibility and usability, thereby maximizing personnel effectiveness. These features include LED illumination for sunlight readability and MIL-STD-3009 NVIS (Night Vision Imaging System) compatibility; a multitouch resistive touchscreen; and a high quality optical stack-up with toughened glass. GE Intelligent Platforms, Huntsville, AL. (780) 401-7700. [].


Industrial-Grade 16 Gbyte MicroSDHC Memory Card for Extreme Environments

An industrial-grade MicroSDHC memory card targets high reliability and longevity even in extreme environments for mission-critical applications. The shock-resistant industrial-grade MicroSDHC memory card from Apacer comes in capacities of 4 Gbyte, 8 Gbyte and 16 Gbyte. One of the highlights is its firmware and major components that can be fixed right after customer’s recognition and validation. This reduces the risk of out-of-stock and compatibility issues by providing customers stable supply and high reliability. The industrial-grade MicroSDHC memory card is compliant with the SD 3.0 Specification and supports Class 10 high-speed transmissions with sequential read/write speeds reaching up to 20 and 14 Mbyte/s respectively while fulfilling the requirements for high-capacity and high-speed data storage. Since Apacer particularly stresses “stability” as the primary concern for industrial devices, the greatest difference with consumer memory cards lies in the firmware version and major components that can be fixed. Furthermore, clients can benefit from the stable, long-term supply commitment to warrant for a stable supply chain and prevent out-of-stock risks. This in turn significantly reduces compatibility issues caused by frequent product component changes. Time and money spent on product verification can also be saved. To ensure that data stays correct in the transmission, the card supports ECC functionality. The Global Wear leveling also helps deliver a phenomenally prolonged lifespan, as well as safer data storage. Apacer, Milpitas, CA. (408) 518-8699. [].

Architecture Visualization Scales to Millions of Lines of Code

A next-generation software architecture visualization system incorporates a new graphical interface for viewing the relationships between software program elements. The system is integrated with CodeSonar, the static-analysis tool for detecting defects from GrammaTech. CodeSonar is a static-analysis tool that performs a whole-program, interprocedural analysis on C/C++ code, and identifies complex programming bugs that can result in system crashes, memory corruption, concurrency errors and other serious problems. The growing complexity of large software systems makes it more difficult for developers to test and analyze the interrelationships between elements of source code. CodeSonar visualization is designed to optimize visual inspection and analysis of software. It offers real-time, fluid transitions for developers to visualize massive data sets to work at different levels of abstraction. The software makes extensive use of the graphics processing unit (GPU), is very high performance, and can handle very large code bases of about 10M+ lines of code. CodeSonar visualization displays the program’s call graph organized according to the module structure of the program. Graphic layouts can be changed in real time and present data in tree, map, circuit, cluster, flow, radial and other layouts. Data is featured in a layered way that provides a high-level view with drill-down capability; users can explore the program from the bottom up as well. CodeSonar visualization also includes other program understanding and navigation features, and supports annotations and sharing of diagrams between team members. With CodeSonar visualization, users can start at individual functions to gain insight from a bottom-up perspective, annotate nodes and edges with additional information, and overlay the visualization with information on defects and source-code metrics such as complexity. Other features include the ability for users to search the graph for functions of interest, view the graph in a variety of different layouts, and navigate to and from the source code of the program. In addition, the architecture is extensible, so users can generate graphs from other sources, feed them in an XML format to the tool and see them in the same user interface. CodeSonar visualization runs through a standard web client such as Microsoft Internet Explorer, Firefox or Chrome browsers. An early release version is available to customers today. GrammaTech, Ithaca, NY. (607) 273-7340. [].

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Second Generation Core i7-Based 6U cPCI Blade with Remote Management

Get Connected with technology and A 6U CompactPCI processor blade isproviding based on solutions the latestnow quad- and companies dual-core second generation Intel i7 and InCore processors withexploration GetCore Connected is a newi5 resource for further up to 16 Gbyte DDR3-1600into memory support. The cPCI-6210 Series products, technologies and companies. Whether your goal from Adlink Technology is a performance computing solution with enis to research the latest datasheet from a company, speak directly an Application Engineer, or jump to a company's technical hanced managementwith features such as PICMG 2.9-compliant IPMI, re- page, the goal ofon GetIntel Connected is to put you in touch with the right resource. mote management based vPro technology and optional Trusted Whichever level of service you require for whatever type of technology, Platform Module (TPM) for security management. Get Connected will help you connect with the companies and products The cPCI-6210youSeries offersfor.enhanced are searching processing and graphics performance. Dual independent display functionality is provided via dual-mode DisplayPort and DVI-I graphics interfaces. The DisplayPort interface supports single-link DVI or HDMI with a passive adapter cable and analog VGA output via an active adapter cable. When coupled a Adlink with technology and companies prov Get with Connected XMC-G460 graphics module installed in the Get Connected is a new resource for further exploration into pro XMC site or an Adlink cPCI-R6700 Rear Transition theancPCIdatasheet from a company, speakModule, directly with Application Engine 6210 Series supports up to four independent displays. in touch with the right resource. Whichever level of service you requir Connected willcPCI-6210 help you connect withinclude the companies Storage interfacesGet supported by the Series one and produc SATA 6 Gb/s direct connector for a 2.5” HDD/SSD, one 7-pin SATA port for external storage, an optional CompactFlash socket, a built-in CFast socket and three SATA ports routed to the RTM with RAID 0/1/5/10 support. Up to eight SAS/SATA interfaces with hardware RAID are supported by the cPCI-R6200 RTM. The cPCI-6210 Series can operate in a system slot as a master or in a peripheral slot as a standalone blade for high density computing applications. In addition, the series is compliant with the PICMG 2.9 specification and supports system management functions based on the Intelligent Platform Management Interface (IPMI) as well as hardware monitoring of physical characteristics such as CPU and system temperature, DC voltages and power status. TPM 1.2 is also supported on Get Connected companies and selected models to provide with efficient hardware-based data protection. products component featured in thisselection, section. Through careful it optionally supports an tended operating temperature range of -40° to +70°C. Supported operating systems include Microsoft Windows XP, Windows 7, Red Hat Enterprise Linux 6 and VxWorks.


ADLINK Technology, San Jose, CA. (408) 360-0200. []. Get Connected with companies and products featured in this section.




COMe Module Allows for Application-Specific Customization

Based on the industry standard Computer-on-Module (COM) Express Compact form factor measuring 95 mm x 95 mm, the VIA COMe-8X92 module from Via technologies pairs a 1.2 GHz VIA Nano X2 E-Series dual core processor and the VIA VX900H MSP, which features the VIA ChromotionHD 2.0 video engine, boasting hardware acceleration of the most demanding video formats, including MPEG4, H.264, MPEG-2, VC-1, WMV and Blu-ray support, for incredibly smooth playback of multimedia titles at resolutions up to 1080p. The VIA COMe-8X92 module offers support for the latest connectivity standards including 18/24-bit single-channel LVDS, VGA, Display Port and HDMI. Onboard I/O includes two SATA II ports, one GigaLAN port, one USB client port (shared with one of four USB 2.0 ports), four USB 2.0 ports, SDIO, expansion buses for one PCIe X4 and one PCIe x1 and the VIA Labs VL800 USB 3.0 host controller, which offers support for four USB 3.0 ports. System memory support includes one slot for up to 4 Gbyte of SODIMM DDR3 RAM. VIA Technologies, Fremont, CA. (510) 683-3300. [].

Services Streamline FAA/EASA Certification at a Fixed Price

A comprehensive and fully compliant FAA/EASA certification solution brings together a team of certification industry experts who are fully accredited across all aviation disciplines along with certification-readiness tools tailored for the needs of the avionics industry. LDRA Certification Services (LCS), a division of LDRA, provides comprehensive support to oversee and guide certification applicants through a wide range of aviation standards including: • Aircraft & Systems Development (ARP-4754A) • Safety Assessment (ARP-4761) • Integrated Modular Avionics (DO-297) • Flight Electronic Hardware (DO-254) • Flight Software (DO-178B/C) • Ground Systems (DO-278/A) LCS addresses critical project requirements that relate to certification, including the management, planning, staff training, development, verification and production. While analyzing certification and safety needs from a total aircraft system perspective, LCS ensures that the individual and exacting aviation standards can be met at a fixed price. LCS provides comprehensive support to avionics companies across the entire development and production lifecycle. With development and verification tools qualified for avionics standard objectives, the LCS team successfully applies these tools across the product lifecycle. To address the new initiatives for model-based development, LDRA offers out-of-the-box integration of the LDRA tool suite and industry-leading modeling tool MathWork’s Simulink. Using this integration, avionics applicants gain model and target-execution coverage. The assured consistency of the same tool performing code coverage on the host and target systems reduces the costs and risks associated with the avionics industry’s best practice of back-to-back testing. From requirements definition and traceability to MC/DC code coverage analysis, unit testing and validation, the LDRA tool suite delivers a broad range of qualifiable verification capabilities that support FAA/ESEA certification objectives at all levels. The LDRA tool suite manages and tracks all artifacts to achieve complete bidirectional traceability through all aspects of development, down to object code and on-target testing. A DO-178-specific template streamlines avionics regulatory processes, outlining necessary certification methodology and requirements. Modules within the LDRA tool suite manage and graphically depict the complex relationships between objectives, requirements, code and tests, automatically documenting all aspects of analysis, code correction and validation. LDRA, San Bruno, CA. (650) 583-8880. [].



Microchip Simplifies C Compiler Line, Optimizes Execution Speed and Code Size

Microchip Technology has simplified its line of C compilers that provide the best execution speed and code size for all ~900 PIC microcontrollers (MCUs) and dsPIC Digital Signal Controllers (DSCs). The MPLAB XC line of compilers offers reduced complexity for 8, 16 and 32-bit designers, with three MPLAB XC Compilers cost-effecMPLAB XC8 MPLAB XC16 MPLAB XC32 8-bit Architecture 16-bit Architecture 32-bit Architecture tive optimiMPLAB XC Suite All PIC MCUs and dsPIC DSCs zation levels—Free, Standard and Pro; the Pro editions can be evaluated for free for 60 days. Additionally, MPLAB XC provides support for the Linux, Mac OS and Windows operating systems, enabling designers to use their platform of choice for embedded development. Another important consideration for today’s designers is the ability to re-use their code and easily migrate to the level of microcontroller performance and features that best suits the needs of each project. These have always been strengths for Microchip, and MPLAB XC continues that tradition by making it easy to move code from any of Microchip’s existing compilers. Additionally, MPLAB XC completes Microchip’s tool chain of compatible compilers and debugger/ programmers that operate seamlessly within the universal, cross-platform and open-source MPLAB X integrated development environment, reducing both learning curves and tool investments. MPLAB XC compilers are also compatible with the legacy MPLAB IDE. Many designers need a free C compiler. The 8, 16 and 32-bit Free editions of Microchip’s MPLAB XC compilers offer many optimizations, are fully functional and have no license restrictions for commercial use. For those who want to test their code with the Pro optimization levels, which are approximately 50% better than the Free editions, Microchip also offers evaluation editions with Pro optimization levels that last for 60 days, after which they convert to the Free compilers. Like the Free editions, the evaluation editions are fully functional and have no license restrictions for commercial usage. Prices for this new XC line have been reduced up to 60%, and the Pro editions are $995. To download the Free editions, or evaluate the paid options with increased code and speed optimizations, visit Microchip Technology, Chandler, AZ. (888) 624-7435. [].


PC/104 Module Combines Serial and Digital I/O

A PC/104-compliant module with four asynchronous serial ports and forty-eight lines of digital I/O eliminates one board in a stack without sacrificing any features or benefits at a lower cost. The PCM-SDIO from WinSystems is based upon an FPGA with both 16C554 UART and WS16C48 digital I/O-compatible cores. The digital portion is further enhanced since its I/O can interface with up to 30 volt signals. The PCM-SDIO will operate from -40° to +85°C without forced air cooling. All four serial channels support RS-232, RS-422 and RS-485 signal levels. The RS-422/485 configuration provides user configurable terminations for balanced transmit and receive signal pairs for longer distance serial communications. Each channel supports 5-, 6-, 7- or 8-bit characters with even, odd or no parity generation and checking. Independent on-chip software programmable baud rate generators support each channel with data rates through 115,200 bits per second. The PCM-SDIO also supports 48 lines of digital I/O. A major feature of this card is its ability to monitor 24 of the 48 lines for both rising and falling digital edge transitions, latch them and then interrupt the host processor notifying that a change-of-input status has occurred. This is an efficient way of signaling the CPU of real-time events without the burden of polling each of the digital I/O points. Each output channel is latched and has an open collector driver (with a pull-up resistor) capable of sinking 12 mA of current. This allows direct control of up to 48 opto-isolated signal conditioners with a single card for high-density I/O support. There is an isolation MOSFET in a High Side configuration on each digital I/O line that can support from 5 to 30 volts. The PCM-SDIO is a replacement and is pin compatible for WinSystems’ PCM-UIO48A and PCM-COM4A serial and parallel PC/104-compatible I/O boards. The PCM-SDIO has free driver software support for Linux, Windows and C on their website. The PCM-SDIO only +5 Get Connected withrequires technology and companies providing solutions now volts and typically draws 250 mA. Quantity one pricing starts at $249.

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WinSystems, Arlington, TX. (817) 274-7553. [].

Quad-Port PoE Frame Grabber Features MultiCamera Synch

A quad-port GigE Vision frame grabber features Power over Ethernet (PoE), IEEE 1588 Precision Time Protocol and a smart PoE application programming interface. The GIE64+ from Adlink Technology supports PCI Express x4 lane, four independent Gigabit Ethernet ports with data transfer rates up to 1 Gbit/s, and GigE Vision camera compliance. With multi-channel synchronization, PoE interface, IEEE 1588 PTP technology and Smart PoE support, the GIE64+ cuts cabling requirements by as much as 60%, significantly reducing maintenance burdens and boosting ease of use. The GIE64+ is suitable for manufacturing environments utilizing multi-camera acquisition. The GIE64+ supports IEEE 1588, providing a software trigger mode for multi-camera synchronized captures. Combining IEEE 1588 and PoE function, the module utilizes a lone Ethernet cable for power supply, data transfer and synchronization. In a typical 4-channel image system, the GIE64+ requires only four cables rather than the conventional twelve, representing a clear reduction in total cost of ownership (TCO). In addition, the GIE64+ further supports a smart PoE application programming interface, enabling easy power status programming and auto detection of compatibility with both PoE and non-PoE devices. Operational simplicity and energy efficiency are enhanced exponentially. The GIE64+ provides link aggregation, increasing double-speed networking by merging two Gigabit Ethernet pathways into a single connection. An easy-to-read I/O-mounted LED display comprehensively communicates PoE status for worry-free power monitoring. Full driver support is provided for Windows 7/XP. ADLINK Technology, San Jose, CA. (408) 360-0200. [].

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly Q7 SBC Uses Dual/Quad-Core ARM CPU for Multiple with an Application Engineer, or jump to a company's technical page, the HD Displays goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, A high-performance quad core-based Q7 connect system-on-module incorGet Connected will help you with the companies and products porates Freescale’s i.MX6x 1 GHz ARM you are searching for. Cortex A9 Dual/Quad core pro-

cessor, which is optimized for high-speed and multimedia applications. The module is Q7 R1.20 standard compliant and targets the Industrial, Automotive and Medical verticals. Incorporating both onboard eMMC flash and expandable DDR3 memory, the i.MX6x Q7 module from iWave also features the latest high-perforGet Connected with technology and companies provi mance interfaces includingGet PCIe Gen2, Connected is a new resource for further exploration into pro Gigabit Ethernet, SATA datasheet 3.0, HDMI from a company, speak directly with an Application Engine 1.4, SDXC and MIPI CSI/DSI. in touch with the right resource. Whichever level of service you require Get Connected Designed with a rich feature set, will help you connect with the companies and produc the module focuses on the high-demand automotive infotainment (IVI) and Telematics market. The combination of performance and power also makes it suitable for applications such as Advanced HMI, Video and Navigation, Portable Medical devices, Digital signage and Single Board SOC Computing. Key features include the ARM Cortex A9 at 1 GHz Dual/Quad core with up to 4 Gbyte DDR3-1066 support along with OpenGL ES 2.0 3D and OpenVG 1.1 graphics accelerators. The i.MX6x Q7 offers 1080p hardware that can encode and decode for four simultaneous display ports and supports the latest HDMI 1.4, SDXC, MIPI CSI/DSI interfaces. Software support includes Linux, Android 4.0 and Windows with companies and EmbeddedGet 7. InConnected addition, iWave has also developed the i.MX6x Develfeatured in this section. for engineers wishing to use the opment Kitproducts to speed time-to-market new processor for their system development.


iWave Systems Technologies, Bangalore, India. +91-80-26683700. [].

Get Connected with companies and products featured in this section.




PCIe/104 SBC Includes Dual Core Atom D2700 at 2.13GHz

A new single board computer in the PCIe/104 form factor features the Intel Atom D2700 with integrated graphics and memory controller functions. The ADLD2700PC from ADL Embedded Solutions has an Intel-rated thermal design power (TDP) maximum of 10 watts, yet has increased clock speed and enhanced graphics including dual-channel video capability at full 1080P with full HD-Decode (MPEG2, VC1, AVC, H.264) and Blu-ray 2.0 support. The processor interfaces to the ICH9M-E to provide PCIe/104 I/O bandwidth (2.5 GT/s) necessary to enable performance-based rugged, portable and thermally constrained applications. In addition to the wide range of rugged, extended temperature or harsh environment applications in which the ADLD2700PC can excel, it also supports a healthy set of features including a discrete 16-bit digital I/O port as well as individual VGA, LVDS, DisplayPort and HDMI/DVI ports. The module also has two RS-232 COM ports, 2x SATA with RAID support, and 9x USB2.0 are also supported onboard, with an additional two SATA 3G and two USB 2.0 ports available on the down-stacking Type 2 PCIe/104 connector. The ADLD2700PC can be optionally expanded by adding the PCIe mini-card Socket, which can be used for Wi-Fi, DDC-1553, bootable flash, Ethernet or other functions. ADL Embedded Solutions, San Diego, CA. (858) 490-0597. [www.adl-usa].

Cost-Effective Analog and Digital Integration Come to 8-bit Microcontrollers

An enhanced mid-range core microcontroller (MCU) family includes advanced analog and integrated communication peripherals, such as on-chip 12-bit analog-to-digital converters (ADCs), 8-bit digital-to-analog converters (DACs), operational amplifiers and high-speed comparators, along with EUSART (including LIN), I2C and SPI interface peripherals. The MCUs from Microchip Technology also feature an advanced level of PWM control and accuracy via their new programmable switch-mode controllers (PSMCs). This combination of features enables higher efficiency and performance, along with cost and space reductions in applications such as closed-loop control in power supplies, and lighting. The “LF” versions of the MCUs feature eXtreme Low Power Technology, for active and sleep currents of just 32 µA/MHz and 50 nA, respectively, helping to extend battery life and reduce standby current consumption. Low power consumption and advanced analog and digital integration make the general-purpose PIC16F(LF)178X MCUs ideal for LED lighting, battery management, digital power supply, motor control and other applications. Environmental concerns and “green” initiatives have led to the rise of new energy-consumption legislation around the world. The PIC16F(LF)178X MCUs enable designers to create products that consume less power. Microchip’s enhanced mid-range 8-bit core brings more performance, with 32 MHz operation, automatic context save for faster interrupt handling, more efficiency in the instruction set with better code density, plus faster and more direct-port control capabilities. Available in 28- and 40-pin packages, the MCU’s advanced analog integration includes an on-chip 12-bit ADC for very small voltage measurements as well as enabling mTouch capacitive sensing, and an 8-bit DAC for high-resolution voltage references. Also included on chip are fast analog comparators with 50 nS response time, capture compare peripherals and I2C, SPI and EUSART interfaces for communications. Additionally, the MCUs feature a 32 MHz internal oscillator, 2 - 8K Words (3.5 – 14 Kbytes) of flash, 128 - 512 Bytes of RAM and 256 Bytes of data EEPROM. The PSMC peripherals are 16-bit pulse-width modulators (PWMs) with 64 MHz operation and advanced control capabilities. The PIC16F(LF)1782/3/4/6/7 MCUs are available in 28-pin SOIC, SPDIP, 6 x 6 mm QFN and 4 x 4 mm UQFN; as well as 40-pin PDIP, TQFP, 8 x 8 mm QFN and 5 x 5 mm UQFN packages. Pricing starts at $1.18 each in 10,000-unit quantities. Program Memory Up to 14 KB (8K Instructions)

Reliable Low Power EWDT, RTC, BOR, POR, nanoWatt XLP

Self Read & Write Capabilities

CPU 14-bit Instruction 49 Total Instructions (2) 16-bit File Select Registers Interrupt Context Save

16-Level Stack & Program Counter Reset Capabilities

(2) 8-bit Timer (1) 16-bit Timer

Op-Amp Up to (3)

PSMC Up to (3)

8-bit DAC


Fast Comparators Up to (4)

Fast 12-bit/10-bit ADC Up to 14 channels Low Voltage Temp Voltage Reference Indicator Detection

Internal Oscillator 32 MHz/32 kHz Data EEPROM 256B

Data Memory Up to 1 KB Linear Addressing

Communications MI2C/SPI, EUSART

Capture Compare PWM Up to (3)

Featured Peripherals

Microchip Technology, Chandler, AZ. (888) 624-7435. [].



Atom SBC Integrates PCI Express with PC/104 to Smooth Legacy Transitions

A single board computer (SBC) powered by an Intel 1.66 GHz Atom processor adds the Stackable Unified Modular Interconnect Technology (SUMIT) I/O expansion connector onto a PC/104 expandable SBC. This combination provides designers easy I/O expansion for the thousands of standard and custom designed PC/104 modules currently available worldwide plus enhanced performance and throughput of stackable PCI Express (PCIe) and USB. The PXM-C388-S processors from WinSystems enable designs that need multiple video input data streams and high-speed A/D, which opens up applications for security, automated inspection of production lines, data acquisition and machine-to-machine communications in a small, rugged form factor. The PXM-C388 is a full-featured SBC with a rich array of onboard peripherals plus I/O expansion options. It is based on Intel’s single core 1.66 GHz Atom N455 and the ICH8M System Controller Hub with up to 2 Gbyte of DDR3 systems memory. The I/O interface on board features a Gigabit Ethernet port; simultaneous CRT and LVDS flat panel video support, eight USB 2.0 ports, four serial COM ports, SATA controller, PATA controller for the CompactFlash socket, twenty-four lines of digital I/O, and HD audio. It will operate from -40° to + 85°C. The PCM-C388 has both PC/104 (ISA) and SUMIT AB expansion connectors to allow self stacking I/O modules to be added for even more I/O flexibility. The PXM-C388-S requires only +5 volts and typically draws 2.5A. It supports power savings modes, which will reduce the standby current to 270 mA (S3 power state). The board is RoHS-compliant and can operate over an industrial temperature range of -40° to +85°C. The module supports Linux, Windows and other x86-compatible real-time operating systems. Free drivers are available from the WinSystems’ website. Quantity one pricing for the PXM-C388-S1-0-0 is $499. WinSystems, Arlington, TX. (817) 274-7553. [].


DIN Rail Programmable Automation Controller Based on ARM9

A Linux-ready ARM9 industrial PC is housed in a robust metal casing with a DIN-Rail mounting attached to its back side. The PAC-4070 from Artila is an ARM9 Linux-based programmable automation controller. The PAC-4070 is powered by 400 MHz AT91SAM9G20 ARM9 Processor with memory management unit, and equipped with 64 Mbyte SDRAM, 128 Mbyte NAND Flash and 2 Mbyte DATAFlash. It is also equipped with 4 x 16-bit isolated A/D channels, 4 x 2500Vrms opto-isolated digital inputs and 4 x high-drive isolated digital outputs. In addition, the PAC-4070 integrates two 10/100Mbit/s Ethernet, two RS-232 serial ports, two RS-232 or isolated RS-485 ports, two USB hosts and one MicroSD socket into a compact metal box. The DIN-Rail also makes its on-site installation flexible. The unit comes with Linux 2.6.29 OS and busybox utility collection pre-installed. The UBI file system is employed to provide improved performance and longer lifetime for NAND Flash compared to JFFS2. Moreover, the DataFlash includes a backup Linux file system that will automatically boot up PAC-4070 in case the primary NAND Flash fails. The failure-proof and redundant booting design makes PAC-4070 an ideal platform for many mission-critical applications. In terms of package management system, PAC-4070 uses ipkg, a lightweight system that resembles Debian’s dpkg. This allows users to easily install, upgrade and remove the software package. Artila continuously increases and updates the software package to its ftp site for the users to download for free to install the software package they need from the Internet. Useful software utilities are also provided for easy management and development of PAC-4070, including webmin, and the GNU tool chain, which includes a C/C++ cross compiler and Glibc.

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Artila, Taipei, Taiwan. +886 2 86 67 23 40. [].

A Motion Control Solution Packed on 21 x 54 mm of PCB Space

A new intelligent servo drive offers high power density (up to 360W of peak power) on a very compact board (only 21 x 54 mm of PCB space). Specifically developed to be PCB embedded, iPOS3604 VX from Technosoft can be mounted vertically or horizontally onto a motherboard. A complete motion control solution, iPOS3604 VX combines controller, drive and PLC functionality into a single compact unit. The drive is able to control brushless DC, brushless AC (vector control), DC brushed and step motors of up to 144W (36V, 4A) continuous power. Equipped with a CAN interface, iPOS3604 has the flexibility to operate in CANopen and TMLCAN protocols. The EtherCAT interface is available using an additional EtherCAT module. Typical feedback devices include incremental encoders, digital and linear Hall signals. SSI, BiSS, EnDAT encoders and resolver interfaces are available through additional extensions. The iPOS3604 VX performs position, speed or torque control and works in single-axis, multi-axis or stand-alone configurations. Complex motion profiles (PVT, S-curves, electronic camming and gearing) can be executed directly on the drive using its built-in motion controller and the high-level Technosoft Motion Language (TML) instruction set. The drive commissioning and the motion programming are straightforward with Technosoft’s integrated development environment, EasyMotion Studio. The software provides a simple, graphical way of creating motion programs written in TML. It automatically generates all the TML instructions. Features of the machine can be split between the host and the iPOS drive by embedding complex motion sequences in TML functions and then executing them from the host with simple commands. Programming is simplified by enabling the host to focus only on the global functionality of the machine, the interaction between machine and user, the management of the application and so on. The drive is suited for all industrial applications that need high-precision control and limited space integration. Technosoft, Bevaixm Switzerland. +41 (0)32 732 55 01. [].

Get Connected with technology and companies providing solutions now

IEC 62304-Compliant RTOS for Medical Devices Get Connected is a new resource for further exploration

A new version of the QNX Neutrinotechnologies RTOS hasand been developed to your goal into products, companies. Whether is to researchreduce the latest datasheet a company, speak directly help medical device manufacturers the effort from of building infuan Application Engineer, or jump to a company's technical sion pumps, patientwith monitoring devices, blood analysis systems, MRI page, the goal of Get Connected is to put you in touch with the right machines, robotically assisted surgery systems, and other safety-criticalresource. Whichever level of service you require for whatever type of technology, products that must pass regulatory approval. The expanded offering will Get Connected will help you connect with the companies and products include the new QNX Neutrino RTOS you are searching for. for medical devices to comply with the IEC medical device standard for software life cycle processes. The company is also offering on-site audits, proven-in-use data, training courses on designing dependable systems and assistance to meet compliancy requirements. Medical device developers Get Connected with technology and companies prov must deal with increasedGet regulaConnected is a new resource for further exploration into pro tory pressure, increaseddatasheet systemfrom a company, speak directly with an Application Engine complexity and increased connecin touch with the right resource. Whichever level of service you requir tivity—and yet, they Get mustConnected create will help you connect with the companies and produc systems that remain simple and intuitive to use. Leveraging deep perience in embedded systems for medical devices and other safetycritical applications has enabled QNX to create a suite of products and services, from training to consulting, to facilitate development efforts and to help customers meet compliancy requirements, such as those for the FDA 510k. The QNX Neutrino RTOS for medical devices is based on the QNX Neutrino RTOS, which has a proven history in medical systems for angiography, blood apheresis, laser eye surgery, hemodynamic monitoring, electrocardiography and anesthesia monitoring. In addition to the expanded product and services offering, medical device manufacturers can also take advantage of the QNX Momentics Connected with companies and Tool Suite,Get an Eclipse-based development environment with profiling products in this section. insight into software behavior. tools designed forfeatured gaining maximum They can also leverage the wide range of processors, protocols, tools and package solutions available through the extensive QNX partner ecosystem. Operating system – QNX Neutrino RTOS Advanced runtime technologies Adaptive partitioning

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QNX Neutrino RTOS microkernel QNX board support packages Processor architectures x86 SH-4





QNX,Ottowa, Ontario. (613) 591-0931. []. Get Connected with companies and products featured in this section.




Wind River Announces Software Support for Xilinx Zynq-7000 EPP

Wind River has announced support for the Xilinx Zynq-7000 extensible processing platform (EPP) on its VxWorks operating system platform and Wind River Workbench. The Xilinx Zynq-7000 EPP combines the performance and power benefits of an ARM Cortex-A9 processor-based system-on-chip (SoC) with the flexibility and scalability of an FPGA. VxWorks real-time operating system (RTOS) and Wind River Workbench development tools support for the Zynq-7000 EPP is available now. Wind River is also currently working with Xilinx on Linux efforts. Wind River’s global support and services are also available to customers on this platform. Well suited for systems that require real-time performance, the Zynq-7000 EPP combines the powerful ARM dual-core Cortex-A9 MPCore processing system with the flexibility and scalability of Xilinx’s programmable logic in a cost-effective platform that encourages wide adoption across multiple markets. Wind River’s extended hardware support for the Zynq-7000 EPP is particularly significant to customers in the aerospace and defense, industrial, medical and networking market segments, for a variety of applications including software defined radios and other military communications technologies, consolidation of high-performance network equipment and high-speed processing in industrial control systems.

Noise Reduction Leads to Quiet Industrial Computers

A Quiet Industrial Computer line from Advantech features a full range of selections with acoustic and thermal optimization. The smart fan, for example, adjusts rotation speed while addressing both cooling and noise issues. Complying with the ISO 7779 standard, noise level is controlled down to as low as 35 dBA. Advantech Quiet Industrial Computers support the Intel 2nd generation Core i7 processors and DDR3 memory modules. They also feature two form factors—a 4U rackmount enclosure and a compact size wallmount enclosure. Both form factors support Advantech industrial-grade ATX and MicroATX motherboards, the AIMB-781, AIMB767 and AIMB-581 series.

Wind River, Alameda, CA. (510) 748-4100. [].

Mentor Embedded Simplifies Linux and Open Source Development with Support of the Yocto Project

Mentor Graphics is releasing its next generation Mentor Embedded Linux platform, which includes support for the Yocto Project, an open source collaborative project established by The Linux Foundation. By leveraging the Yocto Project, the Mentor Embedded Linux platform helps developers easily build Linux-based embedded systems, independent of hardware architecture. With the new Mentor Embedded Linux platform, developers also gain the ability to easily select the best Linux kernel for their needs, whether that kernel was developed by Mentor Graphics, by a semiconductor company, or by any third party. Linux usage has experienced significant growth beyond traditional networking applications. The Yocto Project was created to provide open source, standardized tools and resources to support embedded development. As an advisory board member of the Yocto Project, Mentor Graphics is a key driver of this open source technology. Building on its previous acquisitions of CodeSourcery and Embedded Alley, Mentor Graphics continues its contribution to open source by participating in the Yocto Project. The Mentor Embedded Linux platform supporting the Yocto Project is integrated with the Mentor Sourcery CodeBench and Sourcery System Analyzer tools. Mentor’s Sourcery CodeBench professional-quality GNU toolchain is a complete development environment for embedded C/C++ development on the leading hardware architectures. The Sourcery System Analyzer tool is a comprehensive system and application performance analysis tool that speeds performance analysis on multicore systems with visualization of multiple data sources in synchronized timeline views. The Mentor Embedded Linux platform includes reference board support packages (BSPs) for leading hardware platforms, including those from Broadcom, Freescale, Intel and Texas Instruments. The Mentor Embedded Linux platform also supports QEMU, allowing users to develop Linux systems in simulation without using actual hardware. For more information on the Mentor Embedded Linux platform and to download the free PandaBoard and BeagleBoard Linux Kits, visit Mentor Graphics, Wilsonville, OR. (503) 685-7000. [].



In the past, industrial computers were placed in manufacturing sites or in outdoor environments fairly tolerant of noise. However, as industrial computer applications have become more and more diverse, these computers are also being used in indoor placements, in environments more sensitive to noise, such as in network communications, POS, medical systems, or systems that are placed in offices, including measuring instruments, flight safety consoles, etc. Accordingly, Advantech is introducing its Intelligent IPCs, Quiet Industrial Computers. ISO 7779 is the test specification Advantech is currently using, and the system idle noise level is controlled down to as low as 35 dBA. For the noise reduction design, a team of fully engaged field professionals integrated Advantech technology such as stability and flexible customization, and created a quiet, stable, high-performance system. Starting in 2012, Advantech plans to gradually incorporate noise reduction into all its industrial systems, and provide clients with a full range of Quiet Industrial Computers. Advantech, Irvine, CA. (949) 789-7178. [].





with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




ACCES I/O Products, Advanced Micro Devices, Inc.............................................................................................68................................................................................................................. American Portwell.............................................................................................................67............................................................................................................

Cogent Computer Systems, Inc..........................................................................................50.......................................................................................................... End of Article Products Design Automation Get Connected with companies and Get Connected Elma Bustronic...................................................................................................................2.............................................................................................................. products featured in this section. with companies mentioned in this article. Extreme Engineering Solutions, Inc....................................................................................11.............................................................................................................. Innovative Integration.........................................................................................................41................................................................................................... Intel Corporation............................................................................................................ 22, JK Microsystems, Inc..........................................................................................................4.............................................................................................................. Get Connected with companies mentioned in this article. Keil, An ARM Company......................................................................................................16.................................................................................................................... Get Connected with companies and products featured in this section. Lauterbach........................................................................................................................27........................................................................................................ Logic Devices, Logic Supply, MSC Embedded, One Stop Systems, Phoenix International..........................................................................................................4............................................................................................................ Real-Time & Embedded Computing Conference..................................................................65................................................................................................................ RTD Embedded Technologies, Inc.................................................................................. 34, Saelig Company, Inc..........................................................................................................51................................................................................................................ Sealevel Systems...............................................................................................................7............................................................................................................. Solid State Drives and Industrial Box PC Showcase.............................................................57........................................................................................................................................ Super Micro Computer, Inc.................................................................................................5........................................................................................................ Trenton Systems................................................................................................................31................................................................................................. VIT WinSystems,


A seasoned embedded technology professional? Experienced in the industrial and military procurement process? Ever thinking about writing as a career?


RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Ride along enclosed.



Fueling Innovation for Tomorrow’s Technology……Today AMD is ushering in a new era of embedded computing. The AMD Embedded G-Series processor is the world’s first integrated circuit to combine a low-power CPU and discrete-level GPU into a single embedded Accelerated Processing Unit (APU).

AMD is also proud to offer extended availability of the AMD Geode™ LX processor family until 2015.

Learn more about new levels of performance in a compact BGA package at: © 2011 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, ATI, the ATI logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names are for informational purposes only and may be trademarks of their respective owners. Features, performance and specifications may vary by operating environment and are subject to change without notice. Products may not be exactly as shown. PID# 50599C

RTC magazine  

May 2012 Issue

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