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The magazine of record for the embedded computing industry

January 2012


Power Management— Making Every Electron Count Systems Combine Vision with Motion ARM Moves onto COM Modules An RTC Group Publication

ASICs and SoCs— Finding the New Sweet Spot(s)

50 I/O Extension Module Adds Analog and Digital I/O to FPGA Boards

53 Rugged, Liquid Cooled ATR Chassis Accepts 6U VPX Boards


54 VPX Board Set with High-End DSP for Aero and SIGINT



6Editorial Large Operating Systems Have Embraced Embedded. Did Anyone

Technology in Context


The Changing Role of the ASIC and SoC

Power Management: Making Every Electron Count

16 The Changing Nature of the ASIC Alan A. Varghese and Michael B. Doerr, Coherent Logix


20 Insider 8Industry Latest Developments in the Embedded Marketplace 12 & Technology Newest Embedded Technology Used 50Products by Industry Leaders Small Form Factor Forum Occupy Consortia

Changing Demands Are Changing the Role and Applicability of SoCs and ASICs Brian Calder, IntervalZero

TECHNOLOGY CONNECTED Developments in Small Form Factors


The Benefits of COM-Based Single Board Computers Jonathan Miller, Diamond Systems


on COM Modules: Meeting the Needs of Mobile Devices 14ARM Tom Williams

the SoC for Energy 32Re-focusing Optimization Rasmus Christian Larsen, Energy Micro

Considerations to 36Software Manage and Optimize System Power Adam Kaiser and Arvind Raghuraman, Mentor Graphics

TECHNOLOGY DEPLOYED Combining Vision with Motion

Considerations for a Successful Vision-Guided Motion 40Three System Priya Ramachandran, National Instruments

Vision Interfaces Deliver 46GigE Higher Performance for Machine Vision Systems John Phillips, Pleora Technologies

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JANUARY 2012 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Sandra Sillion, COPY EDITOR Rochelle Cohn

Art/Production ART DIRECTOR Kirsten Wyatt, LEAD WEB DEVELOPER Hari Nayar,


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Large Operating Systems Have Embraced Embedded. Did Anyone Notice?


ere’s a riddle: What do Windows CE, Linux and Java all have in common? Answer: They were all originally designed with no thought to their use in embedded and real-time systems. Windows CE was developed some time in the late 1990s for use in what were to be palm-sized or pocket PCs—little laptop-like machines such as the HP-300LX, which had a touch-sensitive gray (four shades) screen and about 4 Mbyte of RAM. Those machines never made it in the market at that time. Linux was developed to be an open source operating system similar to Unix, which was owned and controlled by AT&T. Java was intended to enable “write once run anywhere” capability for networked systems. Today we see later versions of all three operating systems across all manners of embedded systems with many fulfilling demanding timing requirements, which in the context of their applications constitute real-time performance. Since there is no exact definition of “real time” short of a dissertation on relativity, what has been called realtime performance has always been qualified by the circumstances of its context. It has to meet the timing and determinism constraints of its application. Getting to such a point for a large portion—not all— of embedded applications has come as the result of hard work and dedication by both software and hardware engineers. When I first started covering Java as an embedded systems editor, for example, I listened while several colleagues patiently recited litanies of reasons why it would never be used in real time. The same was true for Linux. They did not figure on the dogged determination of software engineers who saw such value in these technologies that they were determined to adapt them to their needs. They went to work on the Linux kernel to make it more real time. They found ways to deal with the issues of Java’s garbage collection and many other details and forged versions of these OSs that could be used in a large class of embedded applications. Likewise, Microsoft saw the value of giving users of small and embedded systems a familiar user interface with which to work, and later versions of Windows CE were targeted at small embedded and handheld devices that needed a user interface of some form. So why not offer users one that they were already comfortable with?



Tom Williams Editor-in-Chief

However, such heroic efforts could not have come to success were it not for the staggering advances in the performance of microprocessors. The increase in raw speed from hundreds of megahertz to multiple gigahertz has simply blown away a large portion of timing concerns for many an application. This is not to say that critical systems can simply be assumed to perform within all timing constraints—not by any means. But the amount of testing, tweaking and hair pulling has been greatly reduced. Nor is this to say that such operating systems adapted from the IT and/or PC space can replace the selection of robust and advanced RTOSs that are available. It does mean that a vast and expanded number of devices can be reliably fitted with operating systems that provide rich and integrated networking, file systems and user interfaces along with the desired performance. This is further enhanced by the spread of multicore processors with facilities such as hypervisors. Now any timing issues associated with the adapted OS can be safely confined to one processor core while an RTOS on another core or cores deals with all the real-time issues as needed, and again giving the system the functions already offered by the other OS. While this may not exactly be breaking news, its implications are still emerging. One of them, of course, is that we seem to be moving toward an integrated world of IT, personal computing and embedded systems, where all of them will be able to seamlessly communicate and interact by means of straightforward interfaces and protocols. A Linux or Windows-based factory controller, which may or may not have an actual RTOS running on it as well, can be accessed by the floor manager or the executive suite. The Internet of Things is accessible from the home or from the IT department and in a familiar form thanks to built-in graphics capabilities. The next question, of course, is what happens to the ever more popular Android OS? The word on the street seems to be that Google is not the least bit interested in discussing its use in embedded systems. But if the determination of the software community turns its eyes seriously toward Android, who is to say how long that will last? Stay tuned.


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INSIDER JANUARY 2012 Congatec Cooperates with Freescale to Expand Product Line with ARM Modules Congatec has announced that it is collaborating with Freescale Semiconductor to expand its product portfolio with the addition of ARM technology. This will allow the company to offer products with extremely low power requirements in the future. As a first step in that direction, congatec is expanding its Qseven product family with i.MX processors from Freescale. Until now, congatec has focused exclusively on x86-based COMs (Computer-on-Modules), which in the past only allowed a choice between Intel and AMD. As part of its new product strategy, the company now plans to extend its offerings to include Freescale and its ARM-based i.MX portfolio of products. The COM concept integrates all generally available interfaces onto the computer module itself while any special interfaces are implemented on individually tailored carrier boards. In complete contrast, the majority of existing ARM processors come with specialized interfaces designed to suit dedicated applications. These cannot be used by COMs in a standard format and are therefore neither interchangeable nor scalable. However, the new generation of ARM processors focuses on standard PC interfaces such as USB and PCI Express and will therefore be ideally suited to COMs. The Qseven standard was designed from the very beginning around modern interfaces. Its specification was updated in September 2010 (Revision 1.20) to enable the development of 100% compatible ARM-based modules. The features offered by modern ARM processors and the interface definitions of Qseven are a perfect match and require no additional I/Os. This allows the development of price/performance-optimized modules and also makes the modules suitable for a range of completely new applications—many of them related to mobile operation and deployment. The first products resulting from the Freescale collaboration are expected to be available by the middle of 2012.

Fujitsu Semiconductor Standardizes on Mentor Graphics HyperLynx Signal Integrity Technology

Mentor Graphics has announced that Fujitsu Semiconductor has standardized on the Mentor Graphics HyperLynx Signal Integrity technology as the company’s LSI-IC Packaging (PKG)-Printed Circuit Board (PCB) co-design tool for fast and accurate highspeed simulation and analysis. For today’s highly functional end-products, bus speeds are increasingly getting faster and the demand for noise timing-aware LSI-PKG-PCB co-design is increasing. Fujitsu Semiconductor adopted the HyperLynx product suite to address problems caused by high-speed signals throughout the design cycle, from early architectural stages through post-layout verification. As memory bus speeds get faster, timing margins become more severe, impacting simultaneous switching noise and timing design. For good quality control



and optimized performance, this affects the ICs, the packaging, and the printed boards. This includes traditional challenges such as signal crosstalk, over-shooting and under-shooting. Since the HyperLynx product is easy-to-use and provides an intuitive user interface, all members of the product development team (hardware engineers, PCB designers and signal integrity specialists) can use it, from prelayout analysis and simulation to post-layout verification.

Complete P25 SDR Waveform Ported to Android Helps Migration of SDRs

Objective Interface Systems has announced that Communications Research Centre Canada (CRC) ported a complete APCO P25 waveform and Software Communications Architecture (SCA) radio system to a small form factor Android device in just one day with zero source code modifications using the ORBexpress com-

munications software. This port by CRC of the P25 waveform to an Android device realizes the Joint Tactical Radio System (JTRS) program initiative to facilitate the migration of software-defined radios (SDRs) to smaller, commercial form factors to enable faster time to market and substantially lower development costs. The Association of PublicSafety Communications Officials (APCO) Project 25 (P25) is a complex, public-safety waveform that federal, state/province and local public-safety agencies use in North America to enable communication with other agencies and mutual aid response teams in emergencies. The P25 waveform was designed to improve interoperability among civilian publicsafety agencies. This port by CRC proves that public-safety radios can now easily adapt to new operating parameters—the real strength of SDR in a public-safety communications system. In addition, the success of this port makes it easier

for military radios to communicate easily and seamlessly with public-safety radios during homeland security and other emergency situations. CRC’s port of the entire radio system, including a full core framework and a P25 waveform application, ran seamlessly while achieving long battery life on a dual-core ARM processor.

Advantech Partners with Silicom; Adds six Network Mezzanine Cards

Advantech has announced a partnership that will enable Advantech to integrate Silicom’s range of multi-port networking bypass adapters into their network appliance platforms. Initially, Advantech will offer six Intel NIC-based PCIe Network Mezzanine Cards (NMCs) with support for 1GbE fiber or copper bypass ports and 10GbE fiber bypass ports. “More than ever, time to market, re-usability of software across platforms and total cost of ownership are key factors for success of our OEM customers. Network Equipment Manufacturers now can seamlessly combine the benefits of our modular and field replaceable network interfaces based on NMCs and Silicom’s unique and powerful bypass implementation,” stated Peter Marek, Director x86 Solutions for Advantech’s Networks and Communications Group. “Especially, customers using Silicom NICs on other platforms can now move to Advantech’s leading edge appliances without having to invest in, spend time on, or maintain software to accommodate different bypass schemes.”

Renesas Receives USB-IF Certification for USB 3.0SATA3 Bridge System-on-Chip

Renesas has announced that its SuperSpeed USB (USB 3.0) SATA3 bridge system-on-chip (SoC), part number, µPD720230, has passed the certification test-

ing by the USB Implementers Forum (USB-IF). Renesas also announced that AMD has tested and verified chipset compatibility with Renesas’ performanceenhancing UASP software for external storage devices. USB 3.0 achieves data transfer speeds that are up to 10 times faster than the previous version of the standard, enabling more rapid and efficient transfers of data to and from external storage devices. Renesas has led the industry by in-

troducing the world’s first USB 3.0 host controller in May 2009, and the company’s lineup of USB 3.0 host controllers has been broadly adopted by customers worldwide with total shipments already exceeding 450 million units. A newly defined mass-storage class protocol, USB Attached SCSI Protocol (UASP) allows mass-storage devices to operate more efficiently, and therefore take advantage of the increased bandwidth available SuperSpeed

Universal Serial Bus (USB 3.0) interface. In December 2009, Renesas released a UASP driver, followed by the launch of a USB 3.0SATA3 bridge SoC (µPD720230) in August 2011, which was the world’s first USB 3.0-to-SATA3 bridge SoC that supports UASP. Renesas is currently working with leading chipset manufacturers to ensure that its UASP software is compatible with their chipsets. The UASP driver runs not only on the Renesas

µPD720200 USB 3.0 host controller and its follow-on products (µPD720200A, µPD720201 and µPD720202), but also on A70M and A75 AMD Fusion Controller Hubs and its future products.

Test Event for IPv6 at the Customer Edge and Beyond

The University of New Hampshire InterOperability Laboratory (UNH-IOL), an independent provider of broad-based testing and standards conformance

585.88 (7.61%) This data is as of January 17, 2012. To follow the RTEC10 Index in real time, visit COMPANY






Adlink Technology












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Interphase Corporation

















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Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTC MAGAZINE JANUARY 2012



services for the networking industry, has announced it has seen an increase in the number of customer edge (CE) routers that are capable of being deployed in IPv6 networks, as evidenced by results of the lab’s recent IPv6 CE Router Interoperability Test Event. In addition to hosting IPv6 interoperability test events, the UNH-IOL helps member companies cost effectively speed IPv6 broadband deployments through a variety of educational materials, including a recently released IPv6 CE whitepaper and a newly launched YouTube video series. The UNH-IOL’s third IPv6 CE Router Interoperability Test Event, which took place last month, brought together a total of eight operators and CE Router vendors to prepare for the delivery of reliable, uninterrupted Internet service to new and existing customers using IPv6, and to enable end-user connectivity by ensuring IPv6 readiness in home or small office networking environments.


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Participants included Actiontec, Broadcom, Cisco, D-Link, Lantiq, Motorola Mobility and Time Warner. In addition to verifying that CE routers are ready to be deployed in IPv6 networks, the test event proved support of transition mechanisms, such as 6rd, in some CE Routers, which is needed to maintain connectivity for subscribers when networks are not dual-stack (both IPv4 and IPv6). When making recommendations or purchasing decisions, operators and consumers alike may refer to the CE Router Tested List, which will be updated as vendors continue to test IPv6 CE devices at the UNH-IOL, to find out which routers will work in homes and small offices using IPv6.

Microsemi Unveils SmartFusion cSoC and FPGA Private Label Program

Microsemi has unveiled a private labeling program for its SmartFusion customizable sys-

tem-on-chip (cSoC) and its broad portfolio of flash and antifusebased FPGA solutions. Key program features include: • Custom Marking: Devices are marked with the customer’s logo and part number. • Factory Programming: Microsemi programs all devices, alleviating the need for customers to build in-house programming capabilities and infrastructure. • Licensing: Microsemi’s SmartFusion cSoCs include a licensed, hard ARM CortexM3 processor, eliminating the need to obtain a separate ARM license. • Fabless Model: Private labeling eliminates the time and costs associated with establishing and managing a chip manufacturing infrastructure. • No Tooling Charges: No costly non-recurring engineering charges associated with Microsemi’s off-the-shelf SmartFusion cSoCs and FPGAs.

More than a dozen companies are already leveraging Microsemi’s flash-based, highly flexible architectures to quickly deliver tailored solutions to customers, quickly and cost-effectively. Microsemi’s SmartFusion cSoCs are devices that integrate an FPGA, a complete microcontroller built around a hard ARM Cortex-M3 processor and programmable analog, enabling full customization and IP protection. Based on Microsemi’s proprietary flash process, SmartFusion devices are intended for hardware and embedded designers who need a highly integrated SoC that provides more flexibility than traditional fixed-function microcontrollers, and significantly reduces the cost of soft processor cores on traditional FPGAs.

1/9/12 9:25:03 AM



Colin McCracken & Paul Rosenfeld

Occupy Consortia


cross the world, disgruntled citizens have gathered in encampments to protest joblessness resulting from rampant corporate greed and the bloated government that continues to fuel it with quid pro quo. The movement began with “Occupy Wall Street” and quickly spread to other cities. Bailouts for bankers with ballooning bonuses (the ultra-wealthy 1% of the population) are essentially paid for by the other 99 percent—the taxpayers. Meanwhile, our embedded community has its own “golden rule”—those with the gold make the rules. In this stretched economy, most suppliers and system OEMs alike are starved for resources, barely getting by on the backs of employees who wear three hats to make ends meet. The direction of small form factor (SFF) boards rests on the shoulders of those few vendors who are willing to invest their time and resources in the future of the industry. Once rich with diverse membership and widespread participation, trade groups have been recently dominated by member self-interest and individual egos. Rather than commissions and bonuses, the rewards are originator fame and unfair product head starts in the market. Many of the market-savvy old guard members who understand from where the industry came and the importance of legacy interfaces and embedded market firmware have long since moved on. Now most of the big name consortia are driven by just a handful of chipset-oriented engineers. These Lehman Brothers- and Bear Stearns-style engineers are developing standards that cater to the highest-performance 1 percent of applications. Embedded ecosystems are being forgone in favor of proprietary self-interest. The other 99 percent of embedded apps no longer have a voice in the standardization process. As a user of embedded technology, you are not required to consume passively whatever these groups dish out. Luckily there is still time to make changes for the better and restore the feedback loop—surveys, market research and customer involvement— that once regulated these consortia. Just as banking deregulation has taken decades to evolve into the current mess, the embedded market is only partway into the latest technology iteration. Embedded technology standards go through multiple stages between the formation of a new working group to wide market acceptance



of the technology. Many new board-level standards from various consortia are still in their infancy. Still others, developed outside of any formal trade group and without any multi-vendor review, might never result in products from any company other than the originator. COM Modules first lost touch with the broad application base when ETX transitioned to COM Express. Low-power +5V modules with legacy support gave way to multi-core, legacy-free PCI Express modules with enough +12V pins to support 188W of power consumption. The thermal solutions are an exercise for the user, of course. Ironically, nearly every module ships with a BIOS that initializes one of the many legacy super I/O chips that customers almost always add to the carrier board. Better pick the right one! Some of the power pins have been “reclaimed” in the Revision 2.0 specification, which means in lay terms that the power consumption has been traded for the latest chipset features including three digital displays and more PCIe lanes for the “one percent-ers” while foisting an incompatible pinout type upon everyone else. The other 99% of real-world apps are stuck with the carrier board re-design bill without any net feature gain. Not to be outdone, the governance in charge of stackables also appears to be obsessed with power-hungry dual-core and quad-core processors and I/O, trying to compete against expensive VME/ VPX systems rather than keeping the affordable 386/486/Pentium level of performance for simple control apps and ecosystem compatibility. If you’d rather upgrade your military and transportation systems to dual-core Atom at 15W than to quad-core Core i7 at 45W, you might want to tell someone now. Legacy system upgrades carry a lot of clout with vendors and can be used to bargain for desired features with some attention to developing a simple focused message (sound familiar?). But it has to start with the recognition of the problem and willingness to get involved to nip vendor ambivalence in the bud. There is no magic antidote. It will take a lot of hard work and involvement by many system OEMs. The voices of “we the people” need to be heard in the form of our own embedded “occupy” movement. “No specification without representation!” Need guidance about how to get involved? E-mail us at sf3@

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Marvell Armada510 System On a Module The CSB1730-88AP510, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, low-power, ARMADA 510 based System on a Module (SOM). The CSB1730 provides a small, powerful and flexible engine for Embedded Linux based Multimedia, Networking, Digital Signage and Storage applications. y y y y y y y y y y y y y y y


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editor’s report A New Wave of COMs—ARM-Based

ARM on COM Modules: Meeting the Needs of Mobile Devices A new design of very small modules is in the works that will support ARM processors with a standard connector. This is driven by the ever-growing need for high performance with minimum power consumption. by Tom Williams, Editor-in-Chief


here is change on the way in the embedded systems arena and we are just beginning to see the outlines of what it might look like. It looks like ARM. At least two companies whose entire offerings of embedded small form factor modules have been x86 are adding support for the ARM architecture. Led by Kontron, which has been joined by Adlink and is working with several other yet unnamed companies, a new module standard is taking shape that will be based on the low-power, high-performance ARM processor and in the future is planned to be able to accommodate custom SoC designs. For the present, however, the two companies are aiming at rolling out modules supporting one or two ARM implementations. If this effort is successful, of course, more will follow. One of the big issues faced in trying to adapt the ARM processors to a standard module, of course, is that ARM CPUs come in a wide variety of implementations, with a wide variety of pin-outs. On the one hand, this would mean having to select devices with a widely applicable set of external interfaces—even if they have different pin-outs and adapting them to a module board with a standard connector. And the assignment of all the external connector pins must remain absolutely constant across all modules. On the other hand, the ARM



approach puts a huge amount of functionality onto the same die, making the addition of support and peripheral chips much less of an issue and greatly reducing the board space and the power needed for a module. That is definitely reflected in the size of the proposed modules, the first of which will measure only 82 mm x 50 mm (3.23” x 1.97”). For future designs, a “full size” module is envisioned that will measure 82 mm x 80 mm (3.23” x 3.15”). Both modules will use the same 314-pin MXM 3.0 connector, which will be able to support traditional features such as 24-bit RGB, but also be future proof with the ability to support later standards such as HDMI, LVDS and Display Port. The total system power consumption of such designs is targeted to be on the order of 3 watts (Figure 1). The first question, of course, is why would such established x86 houses now be branching into support for ARM? Both companies emphasize that this is not a break from x86, but an expansion into new markets. It is also made possible by timely developments. Kontron’s VP of marketing, Norbert Hauser, notes that, “For the first time now you find the complete infrastructure in terms of operating systems, tools around ARM that make it very convenient—not the least with Android and Linux to work in this area.”

The overriding consideration, however, is power consumption. According to Hauser, more and more customers are asking for power consumption below 5 watts. We have seen how ARM has taken the lion’s share of designs in the smartphone and tablet arena and embedded vendors are now seeing similar demands for low power and mobility in the industrial sector for such things as ruggedized tablets, mobile equipment, test and measurement, etc. The main driving point is battery operation and low power consumption. A parallel development that is making this possible is the rapidly growing market for ARM devices. Hauser notes that while the PC market is growing at about 3 percent, the ARM industry is growing at over 50 percent. The volume of the consumer market for mobile devices, tablets and smartphones is driving down the costs of the components associated with them. It is a parallel phenomenon to what has driven the embedded industry from the PC arena. The x86 itself, as well as technologies such as the ISA bus (ubiquitous in PC/104), PCI and USB, all came from the PC world into use by the embedded industry partly thanks to their wide acceptance and high volume (lower cost) production for the PC. Now, according to Henk van Bremen, Adlink’s product director for Embedded, “It is happening today with the breakthrough of ARM and RISC in the intelligent mobile phone and tablet market that is taking the traditionally x86 dominated netbook market by storm. For the first time, embedded customers will have the same wide choice of operating systems on ARM as on x86, enabling efficient implementations of new and complementary embedded applications based on ultralow-power devices that were not possible with x86 based platforms. Adlink will be able to offer a wide range of OS support, including Linux, Android, Windows CE, Windows 8, VxWorks and QNX.” Both Kontron and Adlink emphasize that they are not aiming at the low end consumer devices, but at industrial applications and multimedia. At the time of this writing neither company is disclosing details about the specification nor announcing any products based on it. Both have, however, mentioned plans to offer modules based on Texas Instruments

editor’s report

implementations of the ARM architecture based on its support of long life cycle management and extended temperature ranges, which are particularly important to industrial customers. Kontron has additionally indicated that it will be working with Nvidia because that company’s CPU family is very well suited to multimedia and high-end processing applications. While Kontron has made no further indications of its plans with Nvidia, it is known that Nvidia’s Tegra2 series uses a dual-core ARM Cortex-A9 CPU. This implementation does not include ARM’s advance SIMD implementation named NEON but does integrate Nvidia’s own GPGU (different versions in different family members). In addition to advanced video and graphics processing, the Nvidia GPGU is capable of high-end number crunching and DSP operations. It also included an ARM7 processor to handle tasks with lower performance requirements and thus additional power savings (Figure 2). While no details about actual pin assignments are currently available, the new form factor will support the most common I/O functions, including SATA, PCI Express, USB 2.0, a number of different camera interfaces and others. It will not include as many USB channels as, say, COM Express, which supports six. There appear to be some as yet unanswered questions as to how the new form factor will go forward. It is being presented as a “slim and low-profile solution for ARM/ RISC and SoC ultra low power processors.” That would imply that it may one day also support architectures other than ARM and even custom SoC implementations. Obviously all the pins available on the modules have not been assigned and it would seem reasonable to assume that they will be assigned as more implementations offering additional or unique I/O are adopted. To date, however, no actual standards body has been established but both companies are aware that as customer acceptance grows and the need to support additional devices increases, there will have to be an organization that oversees the standard. Then there is the matter of software support. The world of ARM is definitely different from that of the x86 where you have a BIOS and a board support package, which may include a selected operating system. At

Figure 1 The basic form factors of what Kontron is calling the “Low Power Embedded Architecture Platform.”

that point one can quickly start application development. With ARM, there is first of all no BIOS and so a hardware adaption layer (HAL) along with drivers and other matters must be solved. It requires more engineering and Kontron has established a Global Software Center to offer software services for a fee to get designers up and running and working on their applications. Adlink’s CTO Stephen Huang indicated that there would be support for various operating systems including Android, Linux, VxWorks, QNX, Windows CE and Windows 8. If the vendor offers that level of off-the-shelf support, developers should be able to select their own tools and get started quickly. In fact, the availability of ARM and other RISC processors on a small, lowpowered module coupled with hardware and I/O level software support will no doubt go a long way toward moving this architecture into a growing number of embedded applications that do not achieve the volume that has normally been needed to justify the development costs. That volume, which is growing in the consumer arena, is making possible the adaptation of such technology in the lower-volume embedded space. The ability to offer an architecture such as ARM in a more ready-to-go package with software and support will speed its adoption into a growing number of designs whose hunger for performance and low power will only continue.

Figure 2 The Nvidia Tegra series is an example of an ARM architecture with custom additional processing elements. (Source: Nvidia) ARM Cambridge, UK. +44 (1223) 400 400. []. ADLINK San Jose, CA. (408) 360-0200. []. Kontron Poway, CA. (888) 294-4558. []. NVIDIA Santa Clara, CA. (408) 486-2000. [].



Technology in


The Changing Role of the ASIC and SoC

The Changing Nature of the ASIC As designs become more compact and power consumption becomes an ever more important issue, the need to address these demands with single-chip ASICs grows. To meet these demands, however, the nature of the ASIC needs to change. by Alan A. Varghese and Michael B. Doerr, Coherent Logix

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s the ASIC dead? Not if you consider the latest generation of semiconductor that ASICs comprised a $20 billion technology can run into tens of milGet Connected with technology and market in 2010. And industry analyst companies lions of providing The mask now set and wacompany Semico Research projects that Getfers are a small portion this cost; the Connected is a new resource of for further exploration total ASIC design starts will grow at ainto products, major technologies portion comes from Whether architecture and companies. your goal is to research the latest datasheet from verification, a company, speak directly healthy CAGR of 7.6 percent from 2010definition, design, and with an Application Engineer, or jump to a company's technical page, the 2014. Regardless, the question is valid for layout. To get a return on such a large goal of Get Connected is to put you in touch with the right resource. many reasons. market volumes to be Whichever level investment, of service you require for whatever type ofneed technology, The cost of ASIC development in very high. Get Connected will help you connect with the companies and products

As shown in Figure 1, the development costs to spin an ASIC in the 45 nm node can amount to more than $40 million. If we consider research and development costs to be 20 percent of revenue, then revenue target needs to be in the range of $200 million. And at a device ASP of say, $20, that would mean a volume requirement in excess of 10 million you are searching for. units to justify the cost of investment. If there is a mistake in the ASIC specification or design, these costs will have to be revisited. And industry surveys show that only about one-third of ASIC designs are bug-free at first silicon. Thus today, OEMs are cost-chalGet Connected with technology and companies providing solutions now lenged and hesitant to spin their own Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research th Instead, an technical IDM or semiconducdatasheet from a company, speak directly with an Application Engineer,ASIC. or jump to a company's page, the goal of Get Connecte in touch with the right resource. Whichever level of service you require for type ofcollects technology,requirements from torwhatever company Get Connected will help you connect with the companies and productsvarious you are searching for. and customers, and then markets designs an ASIC based on a “sweet spot” of requirements. This generates high end volumes that will justify the costs of chip development. The problem with this kind of approach is that the OEM’s time-tomarket is dependent on the IDM’s product strategy and timeline. To make matters worse, the competition may have access to the chip at the same time, and it may be Development Costs Revenues Unit hard to differentiate in the marketplace.






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Figure 1

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A comparison of the development costs versus unit volume and revenues needed to justify an ASIC design.



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technology in context

Another challenge with ASIC design is that it can take as long as 12-18 months from design concept to engineering samples. Unfortunately, market windows for new products, especially in consumer electronics, could be just a few months, and failing to have a product at the start may result in significantly reduced revenues. With fast changing market requirements and industry standards, it is challenging to predict all of the functions and features that are required at time of product launch. For example, the mobile wireless industry is currently transitioning from third generation technologies to what is termed as 4G. But 4G comprises a sequence of standards such as Release 8.0, 8.4, 8.6, 9.0 and so on. When designing an ASIC that will be out in only 12 months, which release features should the ASIC include? The mistake of leaving out a product feature in the ASIC can result in missed customer opportunities. In addition, ASIC design requires specialized skills such as programming in Register Transfer Level (RTL), which is again a challenge. Though signal processing has infiltrated many areas of engineering and product design, not many people know how to program in low-level code such as RTL.

Are FPGAs or General-Purpose Signal Processors the Solution?

FPGAs and general-purpose signal processors do mitigate some of the negatives of ASICs. But as systems become handheld and more mobile, power consumption is a critical constraint, and both of these architectures typically consume high power. In addition, the per-unit costs for FPGAs and general purpose processors are too high for high-volume markets. Some FPGA vendors offer the ability to “harden” their solution eventually into an ASIC. Though this option offers some advantages, it still results in

Product Specification

Specification Changes and CRs

Product Enhancements





Market Introduction

Volume Production

Start with Specifications Program in high-level language Real-time execution on reconfigurable processor

Ship product with standard parts for fast TTM

Differentiate product through software

Incorporate CRs from field-trials and deployments Differentiate product through software

Figure 2 Design flow for a low-volume emerging market using reconfigurable hardware.

a device that is larger and more powerhungry than a custom designed ASIC, due to the underlying FPGA fabric in the design. And it does not eliminate the need to program in hardware design language. The bulk of engineering effort in ASIC/FPGA design is in placeand-route and meeting timing convergence, which can consume months of engineering effort. More recent products available in the marketplace such as structured ASICs allow customization through programmable metal layers. These compare favorably to FPGAs in terms of unit costs, but do not have the capacity, performance and power consumption metrics of a custom ASIC solution.

The Holy Grail in Terms of a Signal Processing Platform?

The Holy Grail would be a reconfigurable platform on which to quickly test out product concepts, ideas and algorithms. The processor should be programmable in a high-level language. Such a platform would give the software team actual hardware to test on, instead of simulation (usu-

ally too slow) or hardware-emulation. The design would be tested on actual production hardware at-speed. Reconfigurability would allow for changing market and customer requirements; making changes that would be prohibitive in an ASIC. And it would be relatively easy on the reconfigurable processor. The risk of an engineering change request (CR) impacting time-to-market (TTM) is considerably reduced. Also required is high-performance. Signal processing requirements continue to increase in step with Moore’s Law, so it is good to have multi- or many-core type of processor performance. And if additional signal processing power is required in the future, the platform should allow seamless extension of the underlying architecture and programming model. The most important requirement is to be able to go to market on the same development platform. And if end-market demand and volumes take off, there needs to be an ability to convert the reconfigurable design to a custom ASIC to reduce cost and get the highest performance and RTC MAGAZINE JANUARY 2012


technology in context

Product Specification

Specification Changes and CRs

Product Enhancements





Market Introduction

Volume Production

Ship product with standard parts for fast TTM

Automatic conversion of programmable fabric to custom ASIC for best cost & power

Start with Specifications Program in high-level language Real-time execution on reconfigurable processor

Incorporate CRs from field-trials and deployments Differentiate product through software

Differentiate product through software

Figure 3 Design flow for a high-volume and mature market using reconfigurable hardware and eventual conversion to a full ASIC.

lowest power consumption. This conversion should be relatively easy and not require writing any RTL code, due to reasons previously mentioned. Since it’s hard to predict how markets will ramp, this type of approach defers any high costs of chip development and production until end-demand is clearly known.

Software First, Hardware Last Design Methodology

The traditional industry approach was to choose specific hardware, and then develop software on that platform. But what we need is a new methodology by which software and applications are first developed independent of hardware implementation, and independent of software/hardware co-design issues. Functional correctness needs to be the initial objective; cost, power-consumption and other implementation details are relegated to a subsequent step. The software is written in a high-level and well-known language such as C. This allows considerable productivity increases in comparison to RTL coding since there is no need for logic synthesis, place and route, and the timing closure required in ASIC/FPGA design. The software is the “golden” reference code as well as the final product, and



thus the software investment is preserved from prototype to production. Compare this with the typical methodology of first implementing a C or Matlab model of the algorithms, then manually converting that to RTL code, and finally having to make sure the RTL is bit-exact with the golden reference model. Execution is performed in real-time and the debug cycle is fast, in the order of minutes rather than weeks and months. All this translates to fast time-to-market and time-to-revenue. The other advantage is that software written in high-level language is much more portable. Thus the OEM is not tied to any chip supplier, but can have a multi-source strategy right from project inception. The most important advantage of this methodology is that since hardware comes last, hardware is matched perfectly to the different stages of the product life-cycle; and performance, power-consumption and cost are designed exactly to market and customer requirements.

What Would the Design Flow Look Like?

The design flows would differ depending on the type of market being addressed. Figure 2 shows the design flow and the different stages for a low-volume emerging market.

At the prototype stage, the engineer starts from the product specifications or market requirements and writes software in high-level language. This software can be immediately compiled and run on the reconfigurable processor. When market conditions are right, the product can be shipped exactly as-is for customer trials and initial deployments. There is no new silicon involved, and the product is “right enough” for the application. Specification changes, software bugs and CRs derived from the field-trials can be addressed and incorporated. Finally in the volume production stage, software can be added that enhances product functions and feature-set and competitive differentiation. Figure 3 shows the design flow stages for a high-volume and mature market. The major difference here is that in the volume production stage, the reconfigurable chip can be converted to a custom ASIC/ SoC (system-on-chip) for best form-fit, cost and power consumption. During this stage, unused communications links in the chip architecture are removed, and critical links are hardwired for best performance. Memory size and organization are matched to the exact application and market profile. The I/O is optimized to reduce pincount and package size, and the drivers are matched for exact loading. The processor core is synthesized and hard-wired for ideal performance. Also, additional IP cores may be integrated such as microcontrollers, embedded DRAM, and analog functions. This process results in a custom floor-plan or metal layer programmable ASIC. It is important to note that, a portion of the processor can be preserved to stay programmable; thus with this method all the advantages of an ASIC are retained, with the added benefit of re-configurability. A technology from Coherent Logix called HyperX comes very close to the Holy Grail definition of signal processing platforms. The architecture combines value added characteristics such as reconfigurability, performance, programming ease and time-to-market into a single software and hardware platform ca-

technology in context

Figure 4 Design methodology used with HyperX.

pable of spanning commercial, industrial and defense applications. In addition, the technology offers the following benefits: • Balanced communication and computation capabilities • High cost efficiency • System of systems on a single chip • Power-aware management resulting in 10-fold improvement over current state-of-the-art reconfigurable processors • High productivity algorithm-to-hardware development environment • Lifetime field upgrades • Scalable to address performance versus cost in the marketplace • Clear path to custom ASIC solution The software first, hardware last design methodology employing Coherent Logix’s HyperX technology is shown pictorially in Figure 4. Are there any negatives with the kind of design approach we have outlined here? If an OEM has many man-years of code developed in RTL, then it may be difficult to discard that legacy code-base and start from scratch in a high-level language. And in certain mature markets where industry requirements are static and end-

volumes are well-known and significant, it may make sense to go directly to ASIC development. But for the majority of markets in signal processing, the existing industry paradigm needs to change. What we need is a model in which innovative ideas can be rapidly implemented on a flexible, programmable platform and taken to market. And if the market and end-demand are high, the option exists to convert the design into the most cost-effective, power-optimum, and custom solution. A reconfigurable general-purpose processor that can also morph into a reconfigurable ASIC will enable a new breed of innovation in signal processing. Coherent Logix Austin, TX. (512) 382-8940. [].



Technology in


The Changing Role of the ASIC and SoC

Changing Demands Are Changing the Role and Applicability of SoCs and ASICs Multicore architectures and raw silicon speed are closing the performance gap between general purpose processors, SoCs and ASICs. This makes it possible to do in software all of the functions on a GPP that would have previously required an ASIC. by Brian Calder, IntervalZero



als, and a programmable fabric—all on a single device. An April 2011 article in RTC magazine noted that “because they combine logic programming with software programming, these new devices offer design teams the maximum flexibility, enabling users to rapidly develop unique functionality for whatever application they are targeting.” Still, why limit the ASPs to SoCs and ASICs? The definition can be expanded to include a promising—and revolutionary—all-software approach that runs on GPPs like x86 or ARM, and an off-theshelf OS with real-time capabilities. Any successful, long-term ASP must be able to deliver successive generations of product in shorter product cycles—not longer— and do so while reducing costs. While the question remains as to what the next dominant platform will ultimately look like, there are some key features required from the ASP to deliver the needed cost, time and risk-mitigation breakthroughs. Context is important to understand why an ASP is important and how a breakthrough is possible. What are the market drivers and technology advances that make a breakthrough in time-to-mar-

Multicore: The Platform of the Future Latency, Power (Watts) & Cost


ompanies building embedded systems that depend on SoCs and ASICs have reached a tipping point. They cannot continue to meet their customers’ increasingly aggressive product-feature demands and at the same time accommodate equally aggressive product-refresh rate expectations. In fact, SoC and ASIC platform limitations are forcing longer product cycles—not to mention more expensive and higher-risk investments—in order to deliver the required product features. This emerging dilemma is creating opportunities for companies that can harness the power of x86 and ARM general purpose processors (GPPs) for the applications that traditionally relied on SoCs and ASICs. Indeed more and more SoC manufacturers are integrating GPPs such as ARM and Atom into their solutions. Over the past two years, RTC magazine has referred to innovative approaches that address the critical issues of cost, time and risk as application services platforms or ASPs, a name coined by RTC Editor-in-Chief Tom Williams. To date, ASPs have been defined as a new class of integrated circuits that combine a CPU, a standard set of configurable peripher-




ult ico AR re M Mu lt




Historical Time

The Present

Figure 1 Over recent years, the latency and performance gap between general purpose multicore processors such as x8 and ARM has been closing to the point that many of the functions that required the specialized hardware properties of DSPs and FPGAs can now be done in software in the GPP.

ket possible and what are the key features of the ASP itself?

Market Drivers

There will always be a market for ASICs or SoCs, but today’s economic reali-

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technology in context

Integrated Platform Addresses Hard Real-Time System Requirements Customer Application Platform Non Real-Time Components (eg: GUI, File System)

Real-Time Applications

SMP Real-Time Applications

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Real-Time RTX I/O

Real-Time Drivers

Real-Time 3rd Party Apps

Win32 API

IntervalZero RTX Real-Time API

Microsoft Windows Kernel

IntervalZero RTX SMP-Enabled Windows Real-Time Kernel Extension

Core 1

Core N

Core N+1

Core M

Multicore Multiprocessor Hardware Platform ARM (Future)


x64 (2012)

Figure 2 A hard real-time platform such as RTX integrates an operating system like Windows with symmetrical multiple processing (SMP) over a number of cores on a GPP so that functions that required specialized hardware components can now be done in software.

ties reduce the number of suitable projects. For example, consumer electronics have a shorter time-to-market, high product volume, and lower cost per unit than corporate electronics. More costly designs that also have less time-in-market for a given product limit the ability for companies to earn a return on new products. Of course, as opportunity for the time-in-market shrinks, so does the feasibility of using an ASIC. Aberdeen’s “Best in Class” study and Design Trends reports, which track ASIC pre-silicon architectural trends, confirm the growing complexity of ASIC chips at all levels of design metrics. Contrast this complexity with the continued decrease in ASIC project starts, and the conclusion is that ASICs may be getting larger in size, but less numerous in unique projects. Besides the increase in design time and cost for SoC and ASIC, there are other profound technology advances in other parts of the chip industry that threaten the domain of the SoC: multicore GPPsnamely x86 and ARM (Figure 1). With Intel’s relentless drive to double performance every 18 months and with the



inclusion of technology like AVX to handle Signal Processing needs, x86-based solutions can now feasibly—actually very favorably—compete with SoC solutions. Clearly, x86 is not a solution for a camcorder, but for any powered system like X-Ray or shop floor control it is already being used today. As multicore processor power consumption and prices come down by 50 percent every 18 months, it will not be long until SoCs feel even more pressure. ARM has had profound impact on the SoC and ASIC vendors. By providing a low-power GPP that was openly licensable, ARM started a technology adoption rate that has rarely been seen. With the help of standardized platforms supporting the ARM platform, such as Android, iOS, Linux, etc., ARM has become the de facto standard for all handheld devices. The ASP is actually recognition by the ASIC and SoC vendors that the GPP can handle more and more of the processing. Still, in order to gain the most benefit, an all-software solution running on a GPP best meets the requirements to shorten the

time–to-market. The concept is called Hard Real-Time Platform.

Hard Real-Time Platform Enabled by Multicore GPP

A Hard Real-Time Platform is simply any development platform that allows the customer to build a standardized real-time system with standardized hardware. The vision is that the product can be designed entirely in software without respect to the target hardware and then deployed to the appropriately sized target PC hardware, depending on the target application. For example, a mixing board for the music industry might have 4, 16 or 96 channels. Traditionally, a mixing board would require a specific hardware design and software application to target each product. Today, world-class organizations in the music industry are designing a single, scalable mix engine that can be deployed to a two-core PC for the 4-channel product, a four-core PC for a 16-channel board, and a 24-core PC for the 96-channel mix surface. This approach is available today and has supplanted an SoC. Similar solutions are in other markets, too. In today’s hyper-competitive and wired global economy, standard pre-integrated application development, softwareonly platforms are increasingly in demand because they allow companies to focus solely on delivering value-added applications. The Android and iPhone platforms are excellent examples. With the supporting infrastructure already in place, smartphone and PDA application developers are using those platforms to build and deploy applications with confidence. No development resources or time are spent building custom DSP or FPGA hardware or operating systems. The platforms provide all the necessary computing resources, integrate the components and ensure both interoperability and stability. This frees application developers to concentrate on capturing their intellectual property in the application. Using SoCs to lower the bill of material costs has been the traditional way for manufacturers to increase profits. However, by moving to multicore GPPs, manufacturers are able to fully leverage standardized software to deliver much richer, more desirable products than either SoC

technology in context

or ASICs can, with only a slightly higher BOM. The GPP-powered smartphones can command a higher average selling price and generate significantly more profit. A win-win: market demands met, profitability increased. The primary GPP in deployment today is the x86, but it is exciting to think about the possibilities of Windows 8 on ARM if Microsoft creates a standard multicore ARM environment for the Hard Real-Time Platform. An ASP based on an SoC model will have a difficult time matching the relentless reduction in cost for an ARM-based platform that runs only software.

Best Practices

We are witnessing a trend in which devices that were once conceived as ASICs or SoCs are able to run standardized software on GPPs using a Hard RealTime Platform, a sample architecture of which is shown in Figure 2. In researching alternative approaches, it is advisable to consider five key features that will decrease the time-to-market and reduce overall design cost. Leveraging a single integrated development environment will maximize productivity. Additionally, the use of system-wide debugging directly improves quality and an immersive user interface drives product differentiation. Proprietary hardware limits continuous performance gains. Taking advantage of COTS multicore PC boards will drive down computing costs by 25 to 50 percent, and by staying on multicore x86, it is possible to double application performance every 18 months. It is clear that scalability is vital for expanding product offerings and opening new markets. With a parameter-driven real-time “engine,” system builders can move from a 2-core system to a 24-core system without redesign, quickly scaling with x86 to create their next-generation products. Hardware independence will also increase the ability to create new products and revenue by re-hosting from Atom to x86, to x64 to ARM. And finally the use of pre-tested components, drivers and applications will cut development time and allow engineering teams to focus on adding Intellectual Property.

These five differentiating components comprise a Hard Real-Time Platform, which can be used for developing complex hard real-time systems that run on COTS hardware. An example of this would be IntervalZero’s Hard Real-Time Platform, which is based on its SMP-enabled RTX software. RTX extends the Windows operating system to deliver hard real-time and runs on multicore x86. The Hard Real-Time Platform approach will likely be very interesting to companies that have traditionally relied on SoCs and DSPs to satisfy their hard real-time requirements for systems with a sophisticated user experience. Today these companies are facing significant challenges: the relentless pressure to get to market faster at a lower cost; increased competition from smaller-form-factor systems with higher quality; and the need to open new markets to continue to grow. It is hardly surprising that CEOs, CFOs and product management are increasingly recognizing the value of replacing their proprietary real-time hardware with standardized software components that can run in real-time as a component of an off-the-shelf PC. Unlike traditional architectures that rely on two development environments and two subsystems to deliver both the hard real-time and the sophisticated user interface, a Real-Time Platform such as IntervalZero’s supports the creation of a single, integrated system that executes a Windows-based HMI/GUI and the realtime system in parallel with SMP architecture on a single PC. At the outset of this article, we talked about the need for the SoC and ASIC systems builders to be mindful of the gap that is growing between design cycle time (and costs) and the shortening product life cycles. The more the industry can evolve its ASP approach the better off it will be. The winning companies will be those that think big, start small and scale fast. Standardized software on a Hard Real-Time Platform that runs on multicore x86 cores offers tremendous advantages.

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connected Developments in Small Form Factors

The Benefits of COM-Based Single Board Computers Recent discussions have debated the advantages of COMs, such as COM Express, versus stackable SBCs, such as PC/104. Here’s how to get the benefits of both at the same time. by Jonathan Miller, Diamond Systems


he benefits of the single board computer (SBC) are well established. An SBC provides a complete solution off-the-shelf. No electronic design or manufacturing are needed, making access to the technology available to customers ranging from giant multinational corporations to one person working in their garage. Getting the board running is usually a relatively painless activity. While integrating the SBC into the final product may require some mechanical design activity, such as enclosure design, cable design and the establishment of assembly and test procedures, an SBC is a tremendous shortcut for anyone wanting to provide computer control of their product. In addition, most SBCs today offer some sort of I/O expansion possibility, whether through the vendor’s proprietary system or through an industry standard. The most common industry standard forms of I/O expansion are slot cards, such as ISA / PCI / PCI Express; sockets, such as PCI MiniCard and PCI Express MiniCard; and stackable systems, such as PC/104 and SUMIT. The availability of these expansion systems means that a customer can usually buy whatever I/O is needed for the application from a supplier, again eliminating the need for any circuit design and manufacturing (Figure 1). SBCs do have their limitations however. Since SBC vendors want to fit as many applications as possible, their designs usually follow industry-standard,



general-purpose physical formats. In some cases a standard format may not fit the customer’s application. In addition, some rugged applications may call for the elimination of cables or the use of special I/O connectors. In these cases, a typical off-the-shelf SBC may be difficult to use. Furthermore, even though most vendors follow industry standards, those standards only specify the mechanical outline of the board, not the types of I/O or the locations of the I/O connectors. Therefore, no two SBCs are exactly alike. If a customer wants an increase in processing power, or the currently designed-in product becomes obsolete, significant changes may be required in the customer’s physical design to accommodate the different configuration of a replacement product. Regarding cost, although the ability to mix and match I/O from multiple vendors is attractive, a multi-board design usually is not cost-effective for high volume applications, and it also may increase the size of the system beyond the packaging limits of many applications. A few other important but often overlooked drawbacks exist for SBCs. First, when new processors are introduced, the first products in which they appear are typically computer-on-module products not SBCs, which means that SBC users must wait longer for the opportunity to incorporate them into their products. Secondly,

Figure 1 The AURORA is a typical offthe-shelf embedded small form factor SBC. This board offers an Atom Z530 1.6 GHz processor, rugged SODIMM memory, gigabit Ethernet, USB, SATA, multiprotocol serial, LVDS and SDVO features in the PC/104 form factor. It has both PC/104 and SUMIT expansion capabilities for adding I/O modules. This off-theshelf board provides an instant solution for small to medium volume applications.

most SBCs use heat sinks on the top side of the board for processor cooling. These heat sinks are inefficient since they conduct heat to the surrounding air. If the SBC is in a sealed box, the cooling problem becomes even worse, limiting the upper temperature at which the SBC can operate reliably.

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Layers of a COM-based SBC

Stackable Expansion Baseboard COM Express module Heat spreader Heat Dissipation

Figure 2 A COM-based SBC utilizes layers to condense the electronics and thermal solution into a smaller outline than a typical COM baseboard.

Because of their many advantages, SBCs are used in a wide variety of applications in all industries. SBCs find use in applications in which customers do not want to or are not able to design their own electronics. In addition, they are used when the product’s physical design can accommodate their shape, and their method of I/O expansion, without significant compromise. Due to the aforementioned disadvantages, SBC applications are usually limited to lower volume applications (less than 1,000 per year), although there are certainly many exceptions to this upper limit.

COM: Optimizing for High Volume and Custom Designs

The Computer-on-Module (COM) concept is, in many ways, the reverse of the SBC concept. Where the SBC is an offthe-shelf complete solution, a COM is essentially a large component, requiring the customer to design a baseboard to provide power to the COM and bring out the I/O. Where each SBC offers its own set of I/O features and connectors, most COMs adhere to a standard set of connectors and features. A system using a COM can usually swap out that COM for another one relatively easily, making performance upgrades vastly easier and improving the ability to protect the product from obsolescence. The easy interchangeability of COMs results in important benefits of performance scalability and design reusability. A designer can use different COMs in the same base product to achieve multiple price and performance levels, serving more customers with just one product design. Another advantage of a COM-based


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design is that the design exists in two “layers”: The COM layer provides the processor circuit, and the baseboard layer provides everything else. Stacking these two layers together provides a compact solution whose physical outline can be smaller than a single board computer where everything is on the same layer. Customers who use COMs in their designs are, by definition, customers who have the ability to design and manufacture their own baseboard. Since such a design effort is usually only justified for a high volume application, COMs tend to be used in large quantities and are therefore extremely cost-competitive. The large-volume business model for COMs has a flip side however: It often presents difficult hurdles for small volume customers who may not be able to meet the vendor’s minimum order requirements, wait for the build-to-order production lead time or obtain satisfactory design-in support. Also, the effort to design and build a custom baseboard is often more than many customers are able or willing to accept. In today’s competitive business world, companies want to focus their resources on their competitive and unique abilities to maximize their payback on research and development. A medical instrument company would prefer to hire a scientist with expertise in their particular discipline over a circuit board designer.

Combining COM + SBC: The Best of Both Worlds

What if a customer could obtain the benefits of both SBCs and COMs with-

technology connected

SBC Advantages


• Complete off-the-shelf solution—no electronics design and manufacturing required

• Form factor may not fit many enclosure designs, especially when adding I/O boards

• Standard form factor and expansion sockets makes it easy to add I/O and other off-the-shelf features

• Lack of standard feature sets and I/O connectors increases difficulty to change to a new board • Lack of performance scalability—limited to the processor on the board • Cost is generally higher than COMs for large volume applications • Traditional heat sink cooling is inefficient and may interfere with expansion modules

COM Advantages


• Standard set of features and connectors makes it much easier to swap out modules

• Requires design and manufacturing of a custom baseboard

• High degree of performance scalability

• Business model may present difficulties for small volume customers

• Increased protection from obsolescence • “Layer” approach may result in smaller overall outline than a single-layer SBC • More cost-effective for high volume applications • Works well with efficient conduction cooling techniques

COM-based SBCs Advantages


• Off-the-shelf solution / faster time-to-market and lower development costs

• Cost may be slightly higher compared to an SBC with equivalent processor performance—but total combination of benefits offsets any increase

• High degree of performance scalability • Increased protection from obsolescence • “Layer” approach may result in smaller overall outline than a single-layer SBC • Works well with efficient conduction cooling techniques • Uses standard off-the-shelf expansion modules

TABLE 1 Summary table of SBC and COM advantages and disadvantages.

out suffering the disadvantages of either? To summarize: What if a customer could achieve the smallest possible outline for the computer board, achieve scalability in performance and protection from obsolescence, take advantage of off-the-shelf expansion I/O boards, and avoid having to do any custom design? This is the objective of the COM-based SBC. In the COM-based SBC, the processor is in the form of a COM, and all the other circuitry is on the baseboard, just like a traditional COM-based solution. The main difference, however, is that the COM-based SBC takes the form of a fa-

miliar industry standard format so that it can serve a broad range of customers. In addition, the COM-based SBC provides sockets for adding industry-standard expansion modules, allowing easy tailoring to each customer’s application (Figure 2). From the customer’s perspective, a COM-based SBC is exactly like a traditional SBC, except for the important and valuable distinction that the customer is not tied to a particular processor. The benefits of performance scalability and protection from obsolescence, so important to any company, are instantly achieved by using a COM-based SBC.

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12/5/11 10:11:05 AM

technology connected

Conduction Cooling Example

Heat Sink Cooling Example Heat rise of processor is 33˚ above ambient. I/O module cannot be installed over heat sink.

Heat rise of processor is 10˚ above ambient. I/O module installs easilly above SBC.

Both examples at 72˚C ambient

CPU junction temperature (Tj) is significantly lower with conduction cooling (right) than with heat sink cooling (left). The CPU temperature can be reduced by 20˚ or more.

Figure 3 Conduction cooling vs. heat sink.

Note that these benefits are also available to the SBC vendor: One baseboard turns into many products, while the vendor can also get to market sooner and more economically by avoiding the complex and risky processor circuit design. At first you might think that a COMbased SBC is taller or bulkier than a single board computer, where everything is on the same plane, or PCB. However, virtually all SBCs use heat sinks, and the height of the heat sink is almost always significantly higher than the height of an installed COM module. In a large number

of embedded applications, a COM module uses conduction cooling to dissipate its heat directly to a wall of the system enclosure, and this conduction cooling “heat spreader” is thin as well. So in many cases a two-layer COM-based SBC is actually thinner than an SBC. Conduction cooling presents an opportunity for two more valuable advantages of COM-based SBCs. First, in a traditional SBC, the heat sink and the expansion are on the same side (top) of the board. Often this results in physical interference or undesirable compromises, such

as making the SBC larger or installing an I/O board over the heat sink. But by putting the cooling system (heat spreader) on the opposite side from the expansion site, a COM-based SBC avoids interference problems and can be smaller. Second, since the heat in a conduction-cooled design is transmitted directly to the system enclosure without passing through the air inside, the entire inside of the enclosure is kept cooler than with a heat sink cooling approach. This leads to higher upper operating temperature capability plus reduced rates of heat-induced failure (Figure 3). The COM-based SBC takes advantage of all the benefits of a traditional off-the-shelf SBC plus all of the benefits of a COM-based solution, while avoiding the pitfalls of both. Furthermore, when designed properly, the COM-based SBC eliminates many problems that plague embedded designs.

Example—COM-based SBC

Diamond Systems offers a COM-based SBC named Magellan. This product consists of a 3-layer “sandwich”: The “application layer”, or baseboard, on top; the COM layer (in this case a COM Express module) in the middle; and a conduction-cooling heat spreader on the bottom (Figure 4). In addition to the standard set of I/O included with COM Express (gigabit Ethernet, USB, SATA, VGA, LCD, Au-

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dio), Magellan provides a second gigabit Ethernet, four multi-protocol serial ports, and a wide-range input power supply. The heat spreader on the bottom allows for the most efficient dissipation of heat from the processor while leaving the entire top side free for “triple play” expansion sockets for PCI-104, SUMIT, and FeaturePak I/O modules plus a board-mounted USB mass storage device. In this case the entire product takes the outline of the COM Express module. By using a COM for the processor and adopting a two-layer design, Magellan offers the highest level of features available in a small 125 x 95 mm package. Providing the same features in a single board would require the outline to be twice the size. When Magellan was first introduced, it was offered with the choice of Atom Z510 1.1 GHz and Core 2 Duo LV 1.6 GHz processors. Now, because of the COMbased design, it can be offered with the additional options of Atom Z530 1.6 GHz, Atom N455, and Atom dual core C525 processors, without any additional design effort. This gives Magellan customers

Figure 4 The Magellan SBC from Diamond Systems utilizes a COM Express processor module to reduce size and provide performance scalability. The customer can choose from among five different processors while retaining the exact same footprint, features and connectors.

more flexibility than they would obtain with a traditional SBC, while providing greater protection from obsolescence.

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Power Management: Making Every Electron Count

Re-focusing the SoC for Energy Optimization Minimizing power consumption in SoCs involves more than just sleep modes. Often, hardware-assisted techniques can save CPU cycles and reduce power consumption. by Rasmus Christian Larsen, Energy Micro


ower consumption has become a duce active power consumption—the primajor concern to users of system- mary concern when that design was inion-chip (SoC) devices. Although tiated—but that will do little to conserve they offer excellent cost-performance fea- energy when the block is idle. ploration tures thanks to the use of high-integration Although designers of low-power your goal processes, energy usage has not followed SoCs will favor semiconductor processes k directly such an advantageous curve. The key that do not exhibit large amounts of subage, the source. problem is that many SoC designs have strate leakage, any core that is powered ology, not taken full advantage of the improve- up for a long period of time will waste d products ments in energy efficiency that have been a comparatively large amount of energy. made possible by the use of finer geom- The best way to reduce that leakage enetry processes. ergy is to power down the core whenever The prevalent SoC methodology in possible – this optimization lies at the use was developed primarily for IC design heart of many low-energy SoCs and miproductivity. SoCs are rarely designed crocontrollers. This has led to the retrofitfrom scratch but are assembled from pre- ting of power-gating circuitry to the cores nies providing solutions now existing intellectual property (IP) cores. employed in low-power SoCs (Figure 1). ion into products, technologies companies. your goaluse is to research the latest This form of and design reuseWhether allows the ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you of tried and tested circuitry that can be A Holistic View of Power you require for whatever type of technology, almostfor. as easily as placing comSimply powering-down cores when and productsapplied you are searching ponents on a virtual printed circuit board they are not needed does not necessarily (PCB). provide the most energy-efficient archiAlthough an SoC designer has the re- tecture. What is important is the way in assurance that a reused block has passed which functional blocks are combined a series of stringent tests, each block will and controlled. have been designed under a set of engiLow-power engineering is an exercise neering assumptions that may not apply so in thinking out of the box; it is not best readily to a new process technology. For implemented by treating an SoC design example, a block design first implemented simply as a collection of hardware comten years ago may use clock gating to re- ponents combined with software. Lowenergy design demands a combination of software, hardware and application unGet Connected derstanding in which tradeoffs are made with companies mentioned in this article. between flexible software-based

End of Article



Get Connected with companies mentioned in this article.

ing and hardware. Even subtle changes to hardware implementation can make large differences to overall energy consumption. For the holistic approach to work, design reuse moves to the architectural level. Optimized implementations are then generated from this architecture based on the requirements of the target applications and the available processes. This rethinking of design reuse, which makes it possible to migrate functionality between the hardware and software domains, results in drastic improvement in energy efficiency. Take, for example, the implementation of support for typical sensing applications on Energy Micro’s EFM32 Gecko series of microcontrollers. Since the introduction of the Apple iPhone, consumer device makers have recognized the advantages of incorporating capacitive touch into their products to provide more responsive and intuitive user interfaces. However, these sensors generally demand a large amount of processing to be carried out in software running on a general-purpose processor. This can be difficult to optimize for power without considering the problem at the system level first. In a typical capacitive-sensor implementation, the sensor circuit includes a free-running RC oscillator. This generates a changing excitation voltage at a more or less constant frequency. When the user’s

tech in systems

finger approaches the sensor, the overall frequency of the circuit will change because the capacitance within the sensor element increases. Usually, software detects this change in frequency using a counter. If the counter value after a fixed period of time drops significantly from the nominal value, the algorithm will register that as a touch event. The problem with this implementation is that the processor core needs to be active during the sensor reading process. It will normally set a timer to count down to zero and during that time count how many positive swings the touch-sensor oscillator has generated. In a user-interface application, the sensing subsystem has no idea when the next contact will be made by the user. The host microcontroller can sleep periodically with the expectation that, in the context of a processor core running at several megahertz, a comparatively large number of clock cycles will complete between touch events. However, longer sleep periods will negatively affect responsiveness. Some touches may not be registered correctly until the system has fully woken up and put itself into a state that allows it to take accurate measurements. It would be more energy efficient to perform these operations in hardware and only wake the processor core once a touch event has been registered. A processor spends most of its energy supplying instructions and data to the execution units rather than performing the computations themselves. Researchers working on the Stanford University ELM low-power processor project concluded that instruction supply alone was responsible for 42 per cent of total processor power consumption. Dedicated hardware does not incur such a large amount of overhead. In the case of a capacitive-sensing subsystem, it is possible to build a circuit that periodically excites the oscillator, sets a timer and then counts the number of pulses before the timer expires. At the end of the process, if the counter value is below a set minimum, it can raise an interrupt that wakes the processor. In this implementation, there is no need for the processor to wake up periodically unless

Original MCU

Upgraded MCU











New Cortex








Figure 1 Simply adding new blocks to a microcontroller cannot remedy all power issues. The peripherals and gating structure must also be changed to achieve energy efficiency as a whole.

LESENSE â&#x20AC;&#x201D; Low Energy Sensor Interface Analog events Capacitive, inductive or resistive sensors Generic MCU Wake-up periodically to detect the events Gecko MCU Wake-up only on the events Gecko MCU Conditional wake-up (e.g. on every 2nd event)

Figure 2 LESENSE block for autonomous operation and monitoring of up to 16 inductive, resistive and capacitive sensors. LESENSE makes it possible to create highly efficient and long lasting sensor applications, only using the CPU when necessary.

there are other management functions to handle. The processor and its software will only be active when they have work to do, which reduces power consumption to the minimum level possible based on user activity.

Hardware Assist to Save Power

Including support for other sensing applications can inform the design of a more general-purpose hardware-assist unit for the main processor. For example, lowcost inductive sensors present a problem similar to capacitive touch panels in terms of power consumption. Inductive sensors are used as proximity switches giving a simple on-off output indicating whether a conductive target is present or not. Inductive proximity sensors detect magnetic loss due to induced current generated on a conductive surface or target by

an external magnetic field. When an AC current is applied to a coil, it generates an AC magnetic field. If a conductive target approaches the sensor, it generates currents, also known as eddy currents, on the sensed object due to the alternating magnetic field. Every time energy is transferred between the two circuit elements, losses occur that will decay the oscillations. This damping process happens more quickly, however, if a metallic object is near the coil. By detecting this change in decay, a sensing algorithm can determine whether an object is within range of the sensor. This is normally performed by reading the change in voltage at regular intervals and comparing it to a reference voltage. If the input voltage falls below this reference, the algorithm can trigger a proximity event. RTC MAGAZINE JANUARY 2012


Tech In Systems

Figure 3 Coupled with an Advanced Energy Monitoring (AEM) enabled development kit, the free energyAware Profiler will correlate instant peaks in power with the C code that caused the problem.

As is the case for capacitive sensing, a software implementation requires that the processor be awake to generate the excitation signal and process the ADC inputs. In the case of a flow metering for water or gas utilities, it can be hard to determine how often the processor needs to wake up to be sure of registering all turns of the impeller. The supply may not be used for long periods, which will mean the processor core is waking up to find there is no useful input to process. Moving the sensing circuitry into hardware can greatly reduce the energy consumption of the system;however, the hardware components needed to perform inductive sensing are subtly different from those needed for capacitive sensing. Many of the same features, such as DAC, are present to provide an excitation signal and timers and counters to define the measurement periods, but the inductive sensor calls for an additional ADC and requires that the individual components be wired in a different way. The commonality between the two types of sensor interfaces can be exploited by careful design of a hardware subsystem; the key is recognizing that the primary changes lie in how the individual hardware components such as ADCs, DACs,



counters and timers are connected to each other and the way in which the software sensing algorithms are usually composed. The algorithms are primarily state based and move between states based on certain properties being true, such as the count value being less than a certain value after timer expiration or the ADC input being below a certain threshold before the timer expires. These conditions can be monitored and controlled by a state machine. A problem with many programmable state machines is that they can only act on and trigger a fixed set of outputs when they move from state to state. In LESENSE, a Low Energy Sensor Interface, system states and the conditions used to select them are programmed through descriptors that can be chained together to form relatively complex operations where needed. It is possible to build quite complex logic before intervention need be sought from the processor core (Figure 2). For example, a metering application that may, using a software-intensive implementation, operate with a duty cycle in which the processor is awake for 2 percent of the time. If the processor runs at 10MHz and is rated at 200µA/MHz with a deep-sleep consumption of 2µA, it will

be able to run for close to seven years on a pair of AA cells. If the use of hardware support cuts that cycle to 1 percent, battery life can be extended to almost 13 years. By looking at the combination of hardware and software that can be implemented in a processor-based system as a whole—and by moving functions between them—it is possible to ensure that the full flexibility of software is only called upon when necessary. The overall behavior of the application at the system level remains the same—allowing reuse of the overall framework—but differences in the implementation architecture make it possible to optimize the solution on a given target for minimum power (Figure 3). Architectural reuse coupled with implementation optimization is enabled through the use of software tools. Active feedback on energy consumption is a major feature of the Simplicity Studio that is realized in the energyAware Profiler. This tool takes the embedded development suite beyond its conventional use as a code-writing and debugging environment. In energy-sensitive applications, you can conceivably remove all the bugs from a design and still have a system that does not meet its most crucial target: its energy budget. The Profiler makes it possible to analyze the code in a system not just for its functionality but its energy consumption— providing engineers with a tool to help determine which functions are consuming the most power and guide whether some functions should be devolved to hardware, either for implementation in a peripheral, such as LESENSE, or restructured to allow the processor core to sleep for longer periods of time. By rethinking the way in which the blocks employed within SoCs are designed and realized, the experience at Energy Micro has shown it is possible to achieve major savings in power consumption. Further savings will come from greater insight into applications and how they are organized at the system level. Energy Micro Oslo, Norway. +47 23 00 98 00. [].

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Power Management: Making Every Electron Count

Software Considerations to Manage and Optimize System Power Modern CPUs have rich facilities for power management. The combination of a power-aware RTOS with application-level strategies can enable designers to greatly optimize system-level power consumption. by Adam Kaiser and Arvind Raghuraman, Mentor Graphics


pervasive trend in the embedded space today is the constant and unrelenting demand for end-device functionality. The advent of 32-bit microploration your goal controllers (MCUs) such as those based k directly on ARM Cortex M series, MIPS MIPS32 age, the 4K-class cores, etc., have drastically insource. creased the processing power and funcology, products tionality available to MCU-based system designs. In addition, today’s MCUs offer a rich set of peripherals that enable enhanced features such as network connectivity and advanced human-machine interfaces (HMI). These developments have enabled system designers to create new and exciting applications with increased nies providing solutions now functionality and improved end-user exon into products, technologies and companies. Whether your goal is to research the latest tion Engineer,perience. or jump to a company's technical page, the goal of Get Connected is to put you Figure 1 Whiletype allofof this is good news, develyou require for whatever technology, and productsopers you arestill searching for. face challenges when it comes Illustration of power savings achieved by system power state control. to managing system-wide power consumption and optimizing designs for power efficiency. Heat dissipation constraints and understanding of the power management cant power savings. Innovative IC design battery life requirements impose tight capabilities of the underlying MCU and techniques provide various architectural power budgets on portable device designs. the facilities available to them in order to facilities that enable a system designer to In addition, “green thinking” and the en- effectively manage and optimize device effectively manage/optimize MCU power vironmental impact of a device’s power power consumption. consumption. Modern day MCUs, such as consumption have become important conSilicon vendors have made signifi- the Texas Instruments Stellaris family of siderations across the industry. It’s imper- cant improvements in semiconductor de- micro-controllers, provide distinct power ative that system developers have a good sign and fabrication processes to reduce domains within the MCU to enable lowMCU power consumption. Component power operating modes. miniaturization (i.e., shrinking a design) The availability of multiple power Get Connected with companies mentioned in this article. and lowering of the internal operating modes allows developers to switch the voltage levels have resulted in signifi- system to lower power during periods of

End of Article


JANUARY 2012 RTC MAGAZINE Get Connected with companies mentioned in this article.

tech in systems

inactivity. Some architectures even integrate hibernate blocks with a voltage domain that is completely independent from the rest of the microcontroller. These hibernate blocks enable very low power consumption by including only the minimum number of gates required to keep the system “breathing” on a back-up battery. These include a low frequency oscillator, a real-time clock, a small amount of RAM to save state, and a wake-up mechanism to exit from hibernate mode. In order to realize further power savings, MCU designs provide the infrastructure required for software control of power and clock to system peripherals and memory. This allows system designers to make run-time decisions to shut down sections of the MCU and memory when they are not required. In addition, MCUs also allow for software control of operating frequency and sometimes voltage. This enables developers to leverage dynamic frequency and voltage scaling techniques (DVFS) to realize power savings. With the increased CPU performance, and enhanced network connectivity and HMI features offered by MCUs today, even simple applications have become multi-threaded systems. To coordinate operation, as well as maximize use of

an MCU’s low-power architectural capabilities, systems need a power-aware, realtime operating system.

The Power-Aware RTOS

An RTOS-based system design provides two key advantages for developing power-efficient applications. First, the multi-threaded application model provides an enabling framework to switch the system to low-power operating modes during system idle time. System idle time is defined as periods of inactivity when there are no tasks/threads ready to run. Second, a power-aware RTOS equips developers with proven, well abstracted, ready-to-use APIs that enable applicationlevel control of peripheral power states, system power states and operating voltage and frequency. Real-time operating systems, such as the Nucleus RTOS from Mentor Graphics, provide built-in power management facilities that automatically utilize the discovered hardware power management capabilities while enabling developers to effectively manage system power consumption from the application level. Using these facilities, a system developer can effectively optimize an application’s static and dynamic power consumption.

Static power consumption in a system can be directly attributed to the number of peripheral blocks that are active—clocked and powered ON—at a given point in time. Substantial power savings can be achieved by powering OFF peripherals that are not being used. Although this sounds fairly simple, the implementation details of safely switching between peripheral power states during run-time in a multi-threaded environment can become rather complicated. Power-aware RTOSs abstract the implementation details and enable developers to make high-level decisions on peripheral power states. For example, Nucleus provides the concept of system power states to optimize the static power consumed by a device. A system power state is a user-defined set of CPU and peripheral power states. Depending on the device usage model, the developer can define various system power states and make application level decisions to transition between them at run-time. Figure 1 shows static power measurements at various system power states (SS0— Standby, SS1—playback, SS2—User idle, and SS3—User active) for an MP3 player implementation.

Go lower only if


Additional energy to switch to low power mode

+ Additional energy to switch from low power mode




Energy savings

Figure 2





a) Power savings achieved by transitioning to low-power states during CPU idle time and b) Heuristic to determine the threshold value to switch to low-power mode.



Tech In Systems

Optimizing Dynamic Power Consumption

An applicationâ&#x20AC;&#x2122;s dynamic power consumption can be directly attributed to system activity. Many embedded applications spend most of their operating time waiting for an external event to occur, for example, waiting for a user key pad press event, waiting for idle timed-delay to expire, waiting


Untitled-12 1


for receipt of a data packet, etc. During such periods of low or no system activity, the low-power modes provided by the underlying MCU can be effectively utilized by the operating system to achieve run-time power savings. In addition to switching the MCU to lowpower mode, other power hungry blocks present in the system can also be transitioned to low-power operating states to

1/11/12 9:50:36 AM

maximize power savings. For example, SDRAM modules can be transitioned to self-refresh mode during long periods of inactivity. Figure 2a illustrates the power savings achieved by placing CPU in idle mode and SDRAM in selfrefresh mode during system idle-time. Transitioning to a low-power mode has associated costs in terms of power and time to enter and exit the desired lowpower mode. An OS scheduler can make intelligent decisions on the most optimal low-power mode transition based on the expected system idle time, and power cost of switching in and out of the lowpower mode as compared to the expected power savings. For example, when an expected idle-time is detected in the RTOS, the scheduler invokes platformspecific CPU idle functionality, which determines if the expected idle time is greater than an empirically determined threshold. The value of this threshold is experimentally determined by performing measurements of the cost and benefits and only making the decision to go to the lower power mode if there are expected overall system power savings. Figure 2b illustrates the principle behind this determination. For longer periods of system inactivity such as when a device is in hibernation, real-time operating systems should effectively use any hibernate facilities provided by hardware to save and restore system state. Advanced techniques, such as OS tick suppression can be used to prolong the duration of CPU idle-time, thereby multiplying the idle-time power savings that can be achieved. Typical real-time kernels use a periodic OS tick timer interrupt to evaluate the internal state and to make scheduling decisions. Tick suppression enables the kernel to dynamically change the time period of the OS tick timer interrupt based on the expected idle time. This enables the system to stay in low-power modes for longer periods of system inactivity. It is to be noted that the calculated power savings may not be fully realized if the CPU is frequently interrupted by asynchronous breaks during idle time. Figure 3 illustrates OS tick profiles with and without tick suppression enabled.

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CompactPCI® Goes Serial

Figure 3 A 50x reduction in OS tick frequency during periods of system inactivity with tick suppression enabled.

Most applications require the peak processing capability of the underlying CPU for only a small percentage of its operational time. Considerable power savings can be obtained using dynamic frequency and voltage scaling (DVFS) techniques. That means scaling down the CPUs operating voltage and frequency at the cost of performance. The system developer can make application-level decisions to pick an optimal operating point, i.e., a frequency and voltage setting, depending on the device functionality required. A switch from one operating point to another requires doing the following: notify all concerned peripherals of the operating point change request, stop peripheral activity, change CPU clock, bus clocks and peripheral clocks for the new operating point, and resume CPU and peripheral activity. A power- aware RTOS should abstract these details and enable the user to make applicationlevel DVFS decisions. Silicon vendors are constantly developing and integrating innovative new mechanisms to optimize device power consumption. Increasing complexity and

functionality of end applications, aggressive low power budgets, quality of service and performance requirements, and aggressive time-to-market pressures have made a power-aware RTOS-based design a table stake requirement for feature-rich MCU applications. Mentor Graphics Wilsonville, OR. (800) 547-3000. [].

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8/5/11 12:38:15 PM

technology deployed Combining Vision with Motion

Three Considerations for a Successful Vision-Guided Motion System

Types of Vision Guidance

The types of vision guidance vary from basic to advanced in terms of the level of integration or amount of interaction between the motion and the vision subsystems. A basic vision-guided motion sequence starts with the vision subsystem capturing the image of an object, for example, an unassembled part. The vision subsystem then processes the image to determine the coordinates of the part in pixels and then converts the pixel coordinates to real-world coordinates. The real world coordinates are then provided as guidance A well-implemented vision-guided motion system enables to the motion subsystem. The motion submanufacturers to improve product quality, enhance system uses the coordinates to determine xploration the trajectory for a coordinated multi-axis r your goal process control, and increase efficiency while lowering ak directly move, such as a move to pick and place the cost of ownership. Three considerations for finding a page, the part (Figure 1). resource. successful solution have proven to help yield a high ROI In a basic vision-guided motion system hnology, the vision subsystem provides guidance to nd products within a year of commissioning. the motion system only at the beginning of a move. There is no feedback during or afby Priya Ramachandran, National Instruments ter the move to verify that the move was correctly executed. This lack of feedback makes the move prone to errors in the pixelision-guided motion systems can automate tasks at accu- to-distance conversion and the accuracy of the move is entirely dependent on the motion subsystem. This drawback becomes racies and panies providing solutions now speeds that provide next-generation machines with faster throughput, higher quality and lower cost. To- prominent in high accuracy applications that have moves in the ation into products, technologies and companies. Whether your goal is to research the latest day,or the community is under to millimeter and sub-millimeter range. Such applications need a cation Engineer, jumpmanufacturing to a company's technical page, the goal of Get tremendous Connected isstrain to put you edge in the global market by offering high quality highly accurate and expensive robotic system. In some cases such ce you requiremaintain for whateveran type of technology, es and products you are searching for. products at competitive prices. To stay competitive, manufactur- a system may be cost prohibitive. ers are seeking solutions to improve productivity, lower manufacThe drawbacks of basic vision guided motion can be elimituring costs and increase customer satisfaction with zero defects Vision Guided Motion System and recalls. Vision-guided motion solutions offer manufacturers the means to achieve these goals. A vision-guided motion system consists of a motion subPosition system and a vision subsystem, which provides guidance to the Setpoint Position Trajectory Actuator motion subsystem in the form of the position or the orientation Loop Generator of an object. The motion subsystem then uses this guidance to move the object as required by the application. The self-guidance Partâ&#x20AC;&#x2122;s capability of a vision guided motion system eliminates the need Position Feedback Position for hard tooling, fixtures and positioning equipment. Parts can be presented in random positions or orientations and the robotic Get Connected companies mentioned in this through article. system iswith able to locate the part vision guidance. The Image Coordinate Camera benefits of vision guidance are provided in Table 1. Processing Transform


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Figure 1 Basic vision-guided motion system.

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Vendor Comparison Position Feedback

Equipment Cost

Integrated Solution

Single Vendor

Vendors in Partnership Multiple Vendors

Integration Time

Figure 2 Vendor comparison.

nated if the vision subsystem provides continual feedback to the motion subsystem during the move. This advanced type of vision guidance is called visual servo control. In visual servo control, the vision system provides feedback in the form of the position setpoints for the position loop (dynamic look and move) or the actual position feedback (direct servo). The dynamic look and move approach is becoming increasingly popular in industrial applications. Visual servo control reduces the impact of errors from pixel-to-distance conversions and increases the accuracy of existing automation. Visual servo control solutions are enabled by FPGA technologies that provide the processing optimizations required to generate position setpoints or feedback at the rate of tens of milliseconds to sub-milliseconds.

First Consideration: Vendor Offering and Support

The market now has several motion and vision vendors providing high quality components at competitive prices. When selecting components, two often overlooked but major factors to consider are the degree of interoperability between the various components, and the quality of support services from the vendor(s). These factors significantly affect the integration time and hence the total integration cost. The compatibility of components and the level of support can make or break an integration project. The first option is to consider a fully integrated vision guided motion system. These integrated solutions, offered by a limited number of vendors, provide turnkey solutions at a lower cost. They are also standardized and are usually not optimized for the requirements of the system. However, these solutions result in a shorter integration time and faster deployment. So, if a standard integrated solution meets the requirements at a reasonable cost, it is the best option to pursue. The second option is to consider a vendor who offers both the motion and the vision components, or at minimum, the core programmable motion and vision components. With this option there is guaranteed compatibility between the components, a single programming environment and one source for technical support. These factors contribute to a significantly shorter inte-



Figure 3 Project with integrated vision and motion subsystems.

gration time. When compared to the standard integrated solution, this option has the potential to provide higher performance and flexibility as shown in Figure 2. If the requirements of your design cannot be met with a single vendor, consider vendors that have a close partnership. In this case, software functions are usually available to communicate between the motion and vision systems. The workarounds for interoperability issues are typically documented, but these workarounds are often complex and time consuming. In many cases, interoperability is not fully tested for all features, so there is a risk of incompatibility. This option is comparable to the single vendor solution for performance and flexibility, but the integration time is significantly longer because of multiple programming environments, complicated workarounds and potentially insufficient technical support. Performance or equipment costs can force you to consider two or more vendors that do not have exiting partnership(s). Although this option has the potential to provide the most performance and flexibility, it definitely has the longest integration time. The path of integrating a set of untested components is littered with incompatibility and support land mines. The quality of support provided by vendors must also be factored in when selecting components. Component selection, set-up and configuration of a motion and a vision system are challenging tasks. A good support structure is crucial for the success of the project. Available technical support should include quality user documentation, a support website featuring knowledge base entries, example programs, training modules and individual support from applications engineers.

Technology deployed

Figure 4 Deterministic Real-Time Code from a Visual Servo Application.

Second Consideration: Software Platform

While higher software performance is enabling the adoption of vision guided motion solutions, software integration challenges are still the main barrier for integrators and manufacturers. Typically, there are two different programming environments for the motion and vision components. Learning the distinct environments often requires a huge investment of time. Even after getting acquainted with the environments, transferring and translating commands and information between them is cumbersome. Integration of HMI and I/O adds an additional burden and increases integration time. Hardware integration across various buses such as GigE, Camerlink, and EtherCAT further complicate the issue. It is important to select components with a common programming environment that is intuitive and easy-to-learn and can seamlessly integrate motion, vision, HMI, and I/O across various hardware platforms and buses. Figure 3 shows an example where an embedded vision system with a GigE camera is configured as an EtherCAT master and connected to an EtherCAT servo motor drive. Vision and motion programming modules provide the tools required to implement the high-level functions to process the images captured from the camera and control the axis through the servo drive. Additional high-level APIs provide simple integration of the HMI and I/O. Advanced vision-guided motion applications need high performance, determinism, tight synchronization, and custom event management. Today, CPUs and FPGAs provide previously unimaginable processing powers. Processors running fast real-time systems can meet the timing and processing needs of advanced systems, while FPGAs enable hardware acceleration for timecritical vision processing tasks and provide the response rates needed to close control loops in motion tasks. Customization is needed in new and unique applications in


Flexible automation with no fixturing requirements. Automation can easily adapt to product and process changeovers. Asset utilization can be increased by running multiple parts and products down the same production line.

Lower Costs

Lower capital costs with the elimination of hard tooling and fixturing. Lower maintenance costs from adaptability to new products or process changes. Vision helps avoid collision of tools, crushing of parts, or damage to the machine. This results in less waste, lower maintenance costs, and fewer instances of machine downtime.

Higher Efficiency

Higher efficiency from increased automation possibilities. Processes that were previously impossible to automate can now be automated. The elimination of clamping and positioning steps results in faster material handling and higher throughput.

Improved Quality

Improved product quality through visual inspection. Process quality can also be improved by logging defect data and analyzing the data to identify defective process components.

TABLE 1 Benefits of vision guidance.

which the standard features of off-the-shelf products do not make the cut. Customization is often required in high-speed visionguided motion systems, in visual servo systems, or in highly specialized applications, such as those found in the biomedical and life sciences industries. Typically, any customization added by the vendor is available at a premium price, and the price increases exponentially with each customized feature. User customization, if available, is often in the form of register-level or firmware-level programming, requiring very high domain knowledge and familiarity with vendor hardware. For this reason, customization has always meant high integration costs. RTC MAGAZINE JANUARY 2012


technology deployed

Figure 5 A Calibration Training Interface.

A customizable real-time and FPGA programming platform is required to solve current and next generation advanced vision guided motion applications. Figure 4 shows an example of deterministic code running on a real-time target from a visual servo application. First, images from a GigE camera are processed to generate the pixel position. Then, the pixel position is converted to an actual position setpoint. The position setpoint is sent to a user-written custom proportional integral (PI) loop to generate the velocity setpoint, which is then sent to the FPGA running the velocity loop for the motor drive. This modular architecture, on a real-time and FPGA platform, allows customization of each part of the application, from the processing of captured images to the position and current loops that control the motor drive.

Third Consideration: Calibration Tools

Spatial calibration is the process of correlating the pixels in an acquired image to real-world units while accounting for the errors in the imaging setup. Spatial calibration produces a mapping for each pixel in the acquired image to a real-world location. In a vision-guided motion system, the motion subsystem uses the position data generated from this mapping. Hence, accurate spatial calibration is required for the system to perform as expected. Spatial calibration must account for variables such as perspective projection, lens distortion, lens defects, tangential distortion, irregular image surfaces and, in some cases, atmospheric conditions. Not accounting for any of these will result in inaccurate calibration mappings. In a vision-guided motion system, the calibration must also account for any non-linearity in the motion system. Once the mechanical pieces of the system are in place, it is necessary to perform several sequences of moves and generate a mapping of pixels to motion units such as encoder counts. For maximum accuracy, the sequence of moves must provide quality coverage of all the axes in the coordinate system. It is almost impossible to manually calibrate the setup for the accuracies required by vision-guided motion applications.



The process of manual calibration is long, tedious, inefficient and produces unsatisfactory results. Many of the calibration variables change with time, so the system requires recalibration. Manual recalibration can significantly increase the maintenance costs of the system. Software calibration tools, on the other hand, can generate highly accurate calibration mappings within a fraction of the time required by manual calibration. They also provide the capability to easily recalibrate the system at regular intervals. Software calibration tools that make it possible for users to programmatically correct for lens and tangential distortion, perspective projections and non-linearity in the mechanical system must be used. Calibration can be implemented as part of the initialization routine of the application so that the system can be recalibrated at any time. A calibration training interface can help significantly reduce the time required to learn the full calibration model of the system. A calibration training interface is a graphical wizard that can be used to generate the calibration template for the system (Figure 5). Often, the interface will also provide the capability to visualize the accuracy of the calibration template by reviewing the mean error, standard deviation and other factors. Quality calibration tools generate the highly accurate calibration models required in vision-guided motion applications with very little time investment and risk to the project. They also provide the flexibility to programmatically recalibrate and improve the accuracy of the system after deployment. As such, they are crucial to the success of a vision-guided motion application. To successfully implement such a system, integrators must carefully consider motion and vision vendors with a focus on interoperability and quality of support services. Equally important and related to the choice of vendor is the software platform used to create the application. Integrators must focus on selecting a single programming environment that enables seamless hardware integration. When solving highly customized and advanced applications, integrators should select a software platform that makes customization and easy real-time and FPGA programming possible. Finally, integrators need to opt for software calibration tools that perform quick and accurate initial calibration and programmatic recalibration of the system after deployment. National Instruments Austin, TX. (888) 280-7645. [].

technology deployed

inspection rate, reduced operating costs, shorter time from production to market, less waste, and fewer manpower requirements. With such attractive benefits, it’s no surprise that manufacturers are keen to further capitalize and enhance the performance of their quality inspection systems. External market conditions are also influencing this desire for ever-growing performance levels. Recent and emerging regulatory requirements, particularly in the food and pharmaceutical sectors, are resulting in a need for more elements to inspect as well as deeper levels of inspection. To avoid escalating inspection costs, nextgeneration machine vision systems will employ higher resolution cameras and will not only need to process data faster, but The increasing performance and density of today’s also process data for a single object from vision systems are placing demands on bandwidth and multiple data sources. For example, a pill preprocessing. Higher speed 10 GigE Ethernet interface could be inspected from multiple camera angles using multispectral imaging as well devices and FPGAs for preprocessing vision data can as through the use of visible light imaging. increase the ease and reduce the cost of upgrades. High-performance, Ethernet-based video interfaces and in-line FPGA image by John Phillips, Pleora Technologies processing are two of the tools available to today’s vision system designer that allow him/her to enhance the flexibility and performance of quality inspection systems. When s price pressures increase due to global competitiveness these are used in combination, designers can optimize the use and economic retraction, productivity remains an everof overall system resources by bringing basic image processing green focus for the manufacturing industry. Machine viroutines closer to the point of image capture, and by efficiently sion, with its ability to emulate and even supersede the human distributing or consolidating the remaining processing tasks useye in a manufacturing process, has long been considered a ing a high-performance video network. means for achieving greater productivity. In the early 1990s, efforts to integrate machine vision were, however, largely disappointing since they were plagued by complex High-Performance Video Networks programming requirements, difficult installations, mediocre funcReal-time functionality in quality inspection systems is oftionality, vendor-specific interfaces and low reliability. The promise ten achieved using a direct link. This, however, limits the topolof enhanced quality and productivity, however, kept the desire for ogy to point-to-point connections between a vision sensor and an machine vision alive, particularly in the semiconductor and elec- image capture board or frame grabber in a PC (Figure 1). There tronics manufacturing sectors. In time, products matured, function- are often advantages to being able to view images on more than ality increased and the cost and complexity of machine vision sys- one display or process them on more than one PC. However, this tems came down. Today, virtually all sectors of manufacturing have requires the configuration of additional point-to-point connecadopted machine vision systems—from food processing and paper tions on extra PCs, display controllers and other pieces of speinspection to metal fabrication and pharmaceuticals. cialized hardware. Machine vision offers important advantages over human viConsequently, point-to-point connections—used in machine sion in terms of cost, speed, precision and physical demands. A vision-centric interfaces such as Camera Link and CoaXPress— machine vision system can verify if an object meets a quality can be costly to install, difficult to manage and expensive to scale. standard using a variety of activities: Moreover, as sensors continue to evolve to higher resolutions and • Determining location, orientation and position; faster frame rates, the high bandwidth needed for real-time im• Measuring dimensions within thousandths-of-an-inch accuracy; age transfer becomes a limiting factor. • Counting items such as pills in a bottle; or Ethernet, on the other hand, offers exceptional networking • Inspecting and identifying flaws. flexibility, supporting almost every conceivable connectivity configuration, including point-to-point, star (point-to-multipoint), The sophistication of quality inspection systems has grown and mesh (multipoint-to-multipoint). As the primary standard to such a degree that they can offer manufacturers 100 percent deployed in most of the world’s networks, including those for

Combining Vision with Motion

GigE Vision Interfaces Deliver Higher Performance for Machine Vision Systems




Technology deployed

demanding military and industrial applications, Ethernet is supported by a well-understood infrastructure based on cost-effective and non-proprietary chip sets, switches and cabling. Gigabit Ethernet, the widely deployed third generation of the standard, delivers 1 Gbit per second, while the fourth generation, 10 GigE, delivers ten times that speed. Additionally, different traffic rates between 10 Mbit/s up to 10 Gbit/s can be handled by the same switch, ensuring backward compatibility and permitting system upgrades without sacrificing legacy cameras already in place. The cost savings that come with using standard, off-theshelf Ethernet components are an attractive add-on benefit to Ethernet’s greater design flexibility, which allows more—and simpler—configuration and distribution options.

The GigE Vision Standard

Initially, interest from the machine vision sector centered on Ethernet’s ability to offer longer cable reach than the common interfaces of the day. Ethernet allows spans of up to 100 meters between network nodes over standard, low-cost Cat 5/6 copper cabling, and much greater distances with switches or fiber. More recently, the ability to build high-performance video networks has been recognized as a dominant advantage, offering the flexibility to combine various image acquisition and processing elements, connected through a variety of network topologies. The potential benefits of Ethernet for industrial vision applications led to the 2006 introduction of GigE Vision, a global open standard governing the distribution of video and control data over Ethernet networks. It establishes a standardized environment for the delivery of networked video applications based on switched client/server Ethernet architectures. Figure 2 shows an example of a GigE Vision enabled quality inspection system. The standard defines four main areas that are specific to machine vision networked systems (Figure 3). Importantly, GigE Vi-

Star Network

Point to Point Network



Mesh Network











Figure 1 Common network topologies; mesh networks offer the greatest flexibility.

sion leverages about 25 existing industry standards rather than introducing proprietary schemes. These include IEEE 802.3 (Ethernet), IEEE 1588 (time synchronization), IETF RFC2026 (jumbo frames) and EMVA GenICam (XML device description file). The recent inclusion of 40 GigE and 100 GigE in the IEEE 802.3 standard is a significant indicator of the expected long-term investment in Ethernet networks. Market studies show that the number of 1G, 10G, 40G and 100G network ports shipped on service provider and enterprise equipment in 2010 jumped 43 percent. Also of significance is that the Ethernet access device market is forecast to grow at an 18 percent compound annual growth rate from 2010 to 2015 as a direct reflection of growing Ethernet connections. This is a strong endorsement of the future of Ethernet networked technology. While the deployment of other non-networked technologies appears to be flat or in decline, Ethernet’s healthy outlook bodes well for the next generation of networked vision applications. With the release of the latest update to the standard, GigE Vision 2.0, formal support for mixed GigE and 10 GigE networks is provided. This provides two major advantages to system designers that leverage the GigE Vision standard: modular expansion of existing systems to accommodate higher-resolution and/

GigE Vision-Compliant Stamping Device

GigE Switch Optical Sensor

Up to 100 meters cable length

Rack-Mounted PCs

Encoder Control wiring Video or networking wiring

Master Controller and Database

Figure 2 GigE Vision Machine Vision System.



technology deployed

Device Discovery

Defines how compliant devices obtain IP addresses and are identified on the network

GigE Vision Control Protocol (GVCP)

Defines how to specify stream channels and control and configure compliant devices

GigE Vision Stream Protocol (GVSP)

Defines how images are packetized and the mechanisms by which images can be transferred

XML Device Provides computer-readable device datasheet permitting Description File access to controls and image stream GenICam Compliant

Figure 3 The four main elements of the GigE Vision standard.

or faster frame rates, with little to no rework of existing processing software. Using switches from a variety of big-name manufacturers (Cisco, Juniper, D-Link and others), a mix of GigE and 10 GigE equipment can be reliably used in the same system. Devices that convert legacy camera interfaces—such as Camera Link—into GigE Vision are also widely available, providing additional flexibility where needed. During an upgrade, an Ethernet system using GigE software and drivers can be largely, if not entirely, migrated up to 10 GigE. The elimination of software redevelopment or purchase dramatically brings down the cost, as well as reduces the complexity of migrating to a higher performing system. In addition to re-using software and drivers, GigE cameras can also be easily re-employed and 10 GigE interfaces brought on-line on an as-needed basis. Last but not least, FPGA architectures also remain largely unaffected during an upgrade, with clear migration paths from one FPGA family to another. With an Ethernetbased quality inspection system, one can avoid the “forklift” upgrades common to interfaces which are backwards-compatible in name only. Owners of quality inspection systems who are seeking higher performance levels can use the benefits provided by Gigabit Ethernet to increase the performance of new and existing machine vision systems. However, it is inevitable that performance requirements will continue to grow, rather than retract, and Ethernet-based systems (both 1 GigE and 10 GigE) are ideal for future-proofing, with simple migration possible on the hardware, software and system component level. As they continue to evolve, video networks incorporating the GigE Vision standard will serve as important technology platforms for machine vision applications, enabling real-time display, processing and storage. Their broad range of attributes appeals to many manufacturers due to the advantages of versatile system design, universal adoption, and cost-effective infrastructure. Further, the GigE Vision interface offers excellent interoperability and international standardization.

In-Line Image Processing and Control using FPGAs

In comparison to traditional machine vision systems, a GigE Vision-based system requires no PC-based frame grabber. While this means that no image capture hardware is required on the (PC) receive side, real-time system-level requirements remain. To meet these requirements, highly-tuned software and drivers can help on the PC side, while FPGAs can help on the camera side.



In fact, there are two often-overlooked areas in which FPGAs can play a vital role. The first is in pre-processing at the camera level. Five years ago, the amount of bandwidth needed to stream data in real time from a high-performance image sensor seldom exceeded 1 Gigabit per second. Since then, improvements in semiconductor processes and circuit design have yielded steady increases in sensor densities and frame rates. In many cases, it is not necessary—or even desirable—to have all of this data sent across the Ethernet link to the PC. For this reason, many camera manufacturers are choosing to add pre-processing capabilities into their cameras. These capabilities include laser triangulation and edge detection. Due to the high throughput and determinism requirements of most quality inspection systems, these tasks are not well-suited to a microcontroller or a DSP. With pre-processing taking place at the camera-level, the PC is relieved of these tasks and can then concentrate on analyzing the object’s quality. The second area in which FPGAs can play a critical role in optimizing a system’s performance is the triggering aspect. Newer line scan cameras operate at 100 KHz (100,000 lines per second). Triggering, which ensures that all cameras looking at an object capture imagery at precisely the same time, must be done with sub-millisecond accuracy. Certainly a PC cannot achieve this, and while this was typically done by an FPGA on the frame grabber, this aspect of control is now the domain of the camera. IEEE 1588 and GigE Vision protocols are implemented in the FPGA to achieve this level of precision timing and accuracy. With pre-processing and triggering, we can see that FPGAs are increasingly doing more at the camera level. At the same time, cameras are getting smaller and are required to use power-over cable technologies, such as Power over Ethernet (PoE), which has a maximum of 13W. However, this maximum might be restated to 7W or less in order to keep the camera size as small as possible. To overcome these challenges while still optimizing performance, low power FPGAs, such as Altera’s Cyclone family, can be integrated into the system’s cameras. The vision system designer of today is tasked to constantly increase performance while lowering cost. While this same designer might have a box full of tools, it can often be difficult to determine which tool or combination of tools will prove most effective for achieving these goals—especially over the long-term. The selection of high-performance, Ethernet-based video interfaces and IP, as well as in-line FPGA image processing, are a practical place to start. When used in combination with a long life cycle FPGA like Cyclone V FPGAs, designers can optimize the use of overall system resources by bringing basic image processing routines closer to the point of image-capture, and by efficiently distributing or consolidating the remaining processing tasks using a high-performance video network, as illustrated by Figure 2. Furthermore, with the use of FPGA, Ethernet-based systems can scale with increasing video bandwidth and pre-processing performance and can be seamlessly migrated from 1 GigE to 10 GigE, which significantly extends the lifespan of a system. Pleora Technologies Katana, ON, Canada. (613) 270 0625. [].




products &

TECHNOLOGY I/O Extension Module Adds Analog and Digital I/O to FPGA Boards

A multi-function I/O extension module adds A/D, D/A and digital I/O signal processing functions to a FPGA processor board. The AXM-A75extension I/O module from Acromag plugs directly onto the company’s PMC and XMC reconfigurable FPGA cards equipped with an AXM mezzanine connector. Engineers can interface a number of high-level analog voltage signals to and from the FPGA. TTL-level digital I/O channels can monitor and control discrete devices. A 68-pin VHDCI receptacle provides easy field I/O connections. The operating range is -40° to 85°C. Typical uses include hardware simulation, in-circuit diagnostics, machine control, signal intelligence and image processing. List price is $1,700. AXM extension modules like the AXM-A75 provide a convenient method to interface real-world signals to and from the FPGA for high-speed measurement and control operations. There are 16 differential analog input channels on the AXMA75. Each input has its own high-speed, 16-bit 250 kHz A/D converter, offering the ability to simultaneously sample all channels. A low-pass filter removes unwanted EMI. The input range is ±10 volts with programmable gain of 1x, 2x, 4x or 8x. Serial FLASH memory stores the factory calibration constants. Two quad DAC devices drive eight analog output channels with a range of ±10V. Each channel has its own high-speed 16-bit D/A converter, which allows updating of individual channels or all outputs simultaneously. The D/A settling time is 10µS. Sixteen bi-directional digital I/O channels provide the ability to read or write 5V logic levels on TTL devices. Each I/O channel is individually configurable as an input or output for great flexibility to match your requirements. The open drain outputs are pulled high via a pull-up resistor. Acromag, Wixom, MI. (248)624-1541. [].

64-bit Dual-Core Processor, HD Video, HDMI Connectivity in a PalmSized Chassis

One of the smallest full featured DIY PC kits available today, squeezes a range of features that include a 1.0GHz dual core Via EdenX2processor, HD video support, HDMI and VGA display connectivity, Gigabit networking, Wi-Fi Support and five USB ports into a palm-sized PC chassis. The Via ARTiGO A1150 from Via Technologies is suitable for a variety of applications in the home or office, including home server, media streaming and surveillance applications, or as a regular desktop PC, using only a fraction of the physical real estate. The small 5.7” x 3.9” x 2” (14.6 cm x 9.9 cm x 5.2 cm)Via ARTiGO A1150 offers a high performance native 64-bit computing experience while remaining within a low-power thermal envelope. The Eden X2 processor is joined by the Via VX900H media system processor, a fully integrated all-in-one chipset that brings exceptional multimedia experience to small form factor devices, including hardware acceleration for the latest HD video codecs including H.264, VC-1, and MPEG-2/4 at screen resolutions of up to 1080p. Front and back panel I/O includes HDMI and VGA ports, a Gigabit Ethernet port, five USB ports, including one USB device port, three audio jacks with optional wireless IEEE 802.11 b/g/n and SD card reader modules. VIA Technologies, Fremont, CA. (510) 683-3300. [].



COM Express Type 6 Module Extreme Rugged Solution for Mobile Environments

A COM Express Type 6 module based on the quad/dual-core second generation Intel Core i7 processor and Mobile Intel QM67 Express Chipset is targeted at mobile applications running in harsh environments. The ExpressHRR from Adlink Technology follows Adlink’s “Rugged by Design” methodology for use in environments prone to severe shock, vibration, humidity and extended temperature ranges.

The Ampro by Adlink Express-HRR is a modular, power-efficient solution for mobile applications running in space constrained, extreme rugged environments. The ExpressHRR is compatible with the COM Express COM.0 Revision 2.0 Type 6 pinout, which is based on the popular Type 2 pinout, but with legacy functions replaced by digital display interfaces (DDI), additional PCI Express lanes, and reserved pins for future technologies. The new Type 6 pinout also supports the SPI Interface, which was unavailable in COM.0 Rev. 1.0. The Ampro by Adlink Express-HRR offers up to 16 GB ECC 1333 MHz DDR3 memory in two SODIMM sockets; three DDIs for DisplayPort/HDMI/DVI/SDVO; eight PCIe x1 and one PCIe x16 (Gen2) for graphics (or general purpose x8/4/1); as well as two SATA 6 Gb/s, two SATA 3 Gb/s, Gigabit Ethernet, and eight USB 2.0 interfaces. The Express-HRR is validated for reliable performance in extended temperatures ranging from -40°C to 85°C and features a 50 percent thicker printed circuit board (PCB) for high vibration tolerance. ADLINK Technology, San Jose, CA. (408) 360-0200. [].


Desktop Platform with AMD G-Series Offers Fanless, Low-Power Operation

A desktop platform is designed for networking applications where low-power and fanless operation is desirable. Powered by the AMD T24L 1.0 GHz low-voltage G-Series processor and A55E chipset, the PL-80400 from Win Enterprises maintains a typical appliance-level power budget of under 25 watts, while supporting a 1.0 GHz AMD Embedded G-series T24L processor (5W) with advanced P-States operation for more efficient power use. The unit supports fanless operation with CF, SATA Disk-On-Module or 2.5” SSD storage with optional 2.5” disk mounting hardware. In addition, a single SO-DIMM slot supports up to 4GB DDR3 1066 MHz SDRAM. Available are a maximum of six GbE Realtek 8111DL Copper ports via PCI-e x1 and available 2 Port LAN Bypass option. Robust I/O includes USB 2.0, SATA, CF socket, MiniCard slot with PCIe and USB support, and Console port. There are 15 front panel LEDs for system status, link and activity monitoring. The unit is built with long-life AMD Embedded components and is RoHS compliant. Typical system power draws under 25W using HDD storage & cooling fans

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WIN Enterprises, North Andover, MA. (978) 688-2000. [].

Four-Channel, 1.25 GHz D/A Module for Beamforming and Multichannel Waveform Generation

A high-performing D/A converter module for RF and IF waveform playback delivers four independent analog outputs, each through its own digital upconverter. It also offers 16-bit D/A with sampling rates to 1.25 GHz. The Cobalt Model 71670 includes an on-board Xilinx Virtex-6 FPGA that contains factory-installed IP to provide turnkey waveform playback functionality for output signal bandwidths up to 250 MHz. Users can also customize the module’s operation by implementing their own IP in the FPGA. Channel independence in the Model 71670 is achieved with two new DAC3484 D/A converters from Texas Instruments (TI), each providing two digital upconverters (DUC) and 16-bit D/A channels with up to 16x interpolation that can translate a quadrature (I+Q) signal to a user-selectable IF center frequency. The Model 71670’s internal clock generator supports a wide range of timing modes and operates from an on-board programmable VCXO or an external clock. A front-panel connector accepts a 5 or 10 MHz reference clock to phase lock the internal programmable VCXO. The module also accepts a direct D/A sample clock input that can be as high as 1.25 GHz. The Model 71670 complies with the VITA 42.0 XMC interface specification, providing two gigabit serial connectors. The primary XMC connector supports x4 or x8 PCIe Gen 2 with multiple DMA controllers for efficient transfers to and from the module. The secondary connector supports two 4x or one 8x link with bit rates up to 3.125 GHz to support user-installed gigabit serial protocols such as Aurora, SRIO or a secondary PCIe interface. An additional I/O option provides 20 LVDS differential pairs to the FPGA through the PMC P14 connector. The Model 71670 is available in several form factors, including XMC, VPX, cPCI and PCIe, and with a variety of FPGA sizes and speed grades. Pricing with 2GB of memory starts at $12,795 and delivery is 8 to 10 weeks ARO. Pentek, Upper Saddle River, NJ. (201) 818-5900. [].

Get Connected with technology and Touch Screen HMI Displays Speed Development companies providing solutions now

A series of touch screen HMIs offers built-in communicaGet Connected is a Ethernet new resource for further exploration tions, advanced alarming/recipe/data logging capabilities and liveWhether video your goal into products, technologies and companies. to allowing research thedirect latest resetting datasheet from a company, speak directly input/display capabilities. isBy of faults, the NS with an Application Engineer, jump and to a company's technical page, the Series HMIs from Omega Engineering saveortime effort in troublegoalreturn of Get your Connected put you in touch right resource. shooting and quickly lines tois to production. Thewith NStheSeries Whichever level of service you require for whatever type of technology, achieves flexible data access to a variety of devices. It enables operators Get Connected will help you connect with the companies and products to reach the devicesyou onare thesearching network, for. including special I/O units, intelligent devices and PLCs. Screen project design time is cut from days to a few hours by preprogramming function blocks that easily drag-and-drop into a program. All you do is specify values for key parameters. The built-in Smart Active Parts library lets you establish communications and parameters for a wide range of products. Just select with technology and companies prov Get Connected the product and drag its icon into your projGet Connected is a new resource for further exploration into pro ect and it automatically sets the from a company, speak directly with an Application Engine datasheet correct protocols. in touch with the right resource. Whichever level of service you requir GetfuncConnected will help you connect with the companies and produc A device monitor tion that enables monitoring the PLC I/O data required for device maintenance and debugging is included as a standard feature of the NS12. Ladder monitor lets you monitor PLC program status, search for addresses or instructions, monitor multiple I/O points, and much more. It only takes about five seconds to switch from a user screen to the ladder program monitoring screen. The integrated simulation function simulates ladder programs and screen data simultaneously, even without the actual hardware. Operation is also simple; just click the icons and that’s it. No extra software Get withthe companies needed. Two of Connected the models are NS5 at and 7.68 x 5.59 x 2.13 inches and products featured this section. a screen resolution of 320 xin 240; and the NS12 at 12.4 x 9.49 x 1.9 inches and a resolution of 800 x 600.


Omega Engineering, Stamford, CT. (203) 359-1660. [].

Get Connected with companies and products featured in this section.




ARM Debugger Adds New Support and Features

An updated version of an ARM debugger includes many new features. SourcePoint from Arium includes support for a lineup of JTAG-based debuggers and trace port analyzers (TPA). This includes the basic LC-500S JTAG interface, the HS-1000 and Arium’s flagship LX-1000. With the LX-SER input adaptor, Arium’s LX-1000 can record six 6.25 GHz input streams for a total gross bandwidth of 37.5 Gbit/s. This bandwidth provides developers with a more complete trace capture, ensuring meaningful events will be captured. SourcePoint 6.9 adds support for several new CoreSight items, including A9, R5 and M0 cores. It also adds support for trace sources, including Program Trace Macrocell (PTM) and Instruction Trace Macrocell (ITM). SourcePoint continues to support one of the broadest offerings of ARM cores available today. Watch for future newsletters to see additional support for new ARM cores and CoreSight components. SourcePoint 6.9 contains performance improvements that speed up the entire debug experience. Additionally, two significant new features are the Graphical Calls chart and the GUI for funnel control. The new Graphical calls chart allows a developer to look at a graphical representation of huge amounts (gigabytes) of instruction trace, identify specific problem areas, and drill down to find the root cause of the problem. The funnel control tool includes automatic topology detection features.

MEMS Energy Harvester Suitable for Shock-Induced Energy Harvesting

A micromachined harvester for vibration energy boasts an output power of 489µW. Measurements and simulation show that the harvester developed by Imec is also suited for shock-induced energy harvesting in car tires, where it could power built-in sensors. In a tire, at 70km/h, the new device can deliver a constant 42µW, which is enough to power a simple wireless sensor node. These results, obtained within the research centre’s program for Micropower Generation and Storage, were presented at the 2011 IEEE International Electron Devices Meeting (IEDM) in Washington (Dec. 7-9).

Arium, Tustin, CA. (714) 731-1661. [].

Boards for RS-485-Based Applications Evaluate Circuit Protection

Two new evaluation boards for RS-485-based applications serve as a design resource that streamlines evaluating circuit protection on RS-485 serial device ports. To meet the required industry standards on RS-485 port interfaces, the new boards from Bourns provide two different evaluation approaches. The RS-485EVALBOARD1 includes two Bourns TBU High-Speed Protectors (HSPs), two Bourns fastacting GDTs and two Bourns TVS diodes. The RS485EVALBOARD2 uses Bourns TBU High-Speed Protectors (HSPs), MOVs and TVS products. Bourns designed the evaluation boards to help developers more quickly and easily determine the circuit protection required for their applications that use RS-485 serial device ports. Bourns’ RS485 evaluation boards are offered through the company’s distribution sales partners, with inventory available immediately at Digi-Key, Farnell and Mouser. As a pricing example, the Bourns RS-485EVALBOARD2 is priced at $20.00 in 10 piece quantities. Bourns, Riverside, CA. (951) 781-5500. [].



Imec’s harvester consists of a cantilever with a piezoelectric layer sandwiched between metallic electrodes, forming a capacitor. At the tip of the cantilever a mass is attached, which translates the macroscopic vibration into a vertical movement—putting strain on the piezoelectric layer and generating a voltage across the capacitor. As piezoelectric material, AlN (aluminum nitride) was chosen. The harvesters are packaged with a 6-inch wafer scale vacuum packaging process. The micromachining production process is compatible with low-cost mass-production fabrication. Imec, Leuven, Belgium, +32 16 28 12 11. [].


Qseven Mini Carrier Baseboard for Accelerated Design-In

A new mini carrier baseboard for space-critical applications is based on the Qseven standard. The conga-QMCB baseboard from congatec is suitable for fast prototype design and compact, mobile applications. Measuring 145x95 mm, the easy-to-integrate mini carrier board is packed with a wide range of state-of-the-art interfaces and is designed to accelerate the evaluation process in the designin phase, thereby facilitating faster time-to-market. DisplayPort, HDMI and LVDS 18/24 Bit graphics interfaces have been implemented, together with six USB interfaces and an Ethernet connection. The board also offers additional standard interfaces such as high definition audio and a mini PCI express socket, which can be used for WLAN. SD-Card, 2x SATA and CFast have also been integrated on the baseboard to enable the connection of mass storage devices. The conga-QMCB is powered by a single 5V DC supply. Battery management signalling is fully incorporated, enabling the use of the congatec Smart Battery Manager (conga-SBM2) and making the baseboard a simple solution for mobile systems. When using ACPI-compatible operating systems such as Linux or Windows, battery system communication is fully implemented; no special software or BIOS adjustment is required. The conga-QMCB is designed for use with the new conga-QAF computer module, which is based on AMD Fusion technology; and the conga-QA6, which is based on the current Intel Atom E600 series. congatec, San Diego, CA. (858) 457-2600. [].

Rugged, Liquid Cooled ATR Chassis Accepts 6U VPX Boards

A new rugged 1 ATR tall, short enclosure with independent dual liquid cooled side walls offers significantly better cooling than conduction only and air-flow designs. Targeted for highly dense embedded systems with exceptional heat dissipation requirements, the new platform holds 6U conduction cooled boards with a 1” pitch per VITA 48.2 (REDI) and VITA 65 (OpenVPX). The new liquid cooled chassis is available with a 6U OpenVPX backplane on a 1” pitch per VITA 65 Backplane Profile BKP6-CEN0711.2.3-n. The backplane provides seven slots, each cooled up to 100 W; one slot for storage, one for switch and five payload slots. Additional backplanes are available, including VME, VME64x, VXS, cPCI or custom backplanes. Different front I/O configurations are also possible, such as MIL-STD wiring and connectors, to meet specific application requirements. The all-aluminum chassis has electron beam welded fluid channels in the side walls that can use a variety of cooling fluids, including dielectric fluids (PAO), inhibited glycol/water solutions (PGW, EGW), kerosene, de-ionized water and salt water. The unit offers users the choice of a fixed-mount 400 W or 500 W 6U plug-in power supply. Dimensions of the new chassis are 10.625” H x 10.12” W x 12.52” L. This new enclosure is designed to meet shock and vibration standards per MIL-STD-810G, as well as MIL-STD-810F, MIL-STD-901D and MIL-STD-461F (CE102, CS101, CS116, RE102, RS103). It can operate at altitudes of up to 75,000 feet. Operating temperature is -55°C to 70°C and storage temperature is -62°C to 95°C. Pricing starts at $30,000, including the backplane and power supply.

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A 48-point remote isolated field input card designed for fast realinto products, technologies and companies. Whether your goal time PC-based control systems. The from Mesa Electronics comis to research 7I70 the latest datasheet from a company, speak directly municates with the with hostanwith a robust isolated RS-422 link. Standard Application Engineer, or jump to a company's technical page, the CAT5 cables are used convenience. The is supported byresource. goalfor of wiring Get Connected is to put you7I70 in touch with the right Whichever level of service you require for whatever type of technology, Mesa’s low cost FPGA cards, Get Connected will help you connect with the companies and products which present a simple paryou are searching for. allel register interface to the host, with all protocol details handled by the smart interface. One FPGA card can support up to 32 external devices and up to 3,072 control points while still maintaining a 10 Get Connected with technology and companies prov kHz service rate for all points. Get The 7I70 has 48 DC volt-Connected is a new resource for further exploration into pro datasheet from a company, speak directly with an Application Engine age sensing inputs. Thein7I70 touch with the right resource. Whichever level of service you requir inputs are smart with variable Get Connected will help you connect with the companies and produc threshold sensing. Default put threshold is 50 percent of field power voltage with 20 percent hysteresis, but input thresholds are individually programmable from 0 VDC to 36 VDC. All inputs have LED status indicators and removable screw terminal field wiring. The 7I70 is suited for high performance industrial automation and machine tool applications. Price of the 7I70 in quantity100 is $57.


MESA Electronics, Richmond, CA. (510) 223-9272. [].

Get Connected with companies and products featured in this section.

Elma Electronic, Fremont, CA. (510) 656-3400. [].

Get Connected with companies and products featured in this section.




VPX Board Set with High-End DSP for Aero and SIGINT

Two modules, both designed to meet demanding SIGINT, COMINT and radar processing applications, together with FPGA engines and FMC I/O modules from Curtiss-Wright Controls Embedded Computing, deliver comprehensive and high performance single board computer (SBC) and GPGPU solutions for demanding high performance embedded computing applications. The Champ-AV8, CWCEC’s first rugged, high performance OpenVPX DSP engine, is based on the new quad-core Intel Core i7-2715QE processor and accelerates SIGINT algorithms with its 256-bit AVX floating point instruction set. The VPX6-490 GPGPU compute engine features dual NVIDIA GPUs based on the NVIDIA Fermi architecture, and the massive compute capability of a pair of 240-core GPU devices. Together these two 6U OpenVPX processor engines comprise the heart of very high performance rugged deployable signal processor systems for aerospace and defense applications. The Champ-AV8 multi-processing board brings the floating-point performance of the quad-core Intel Core i7-2715QE processor to the OpenVPX form factor standard. The Champ-AV8’s dual processors deliver performance rated at up to 269 GFLOPs. With a 21GB/s (peak) DDR3 memory subsystem connected directly to the processor, the Intel Core i7-2715QE is able to maximize the throughput of its Intel AVX vector processing units and process larger vectors at peak rates significantly greater than was possible with previous AltiVec-based systems. Supporting the DSP engine’s floating-point performance is a 21GB/s (peak) DDR3 memory sub-system that provides ample bandwidth to simultaneously serve CPU access and streaming I/O from its sRIO and PCIe interfaces. The Champ-AV8 incorporates the enhancements of the OpenVPX (VITA 65) standard with a complete suite of data plane, expansion plane, and control plane interfaces. Supporting Gen2 SRIO and Gen2 PCIe interfaces, the Champ-AV8 offers triple the bandwidth of first generation VPX products with up to 32 GB/s of fabric performance, thus ensuring that application performance can scale commensurately with the much higher CPU performance. The VPX6-490 GPU Application Accelerator is a general purpose graphics processing unit (GPGPU)- multi-core engine. The VPX6-490 features dual Nvidia GPUs based on the Nvidia Fermi architecture, each with 240 CUDA cores. Integrated into a High Performance Embedded Computing (HPEC) subsystem, VPX6-490 functions as a co-processor attached to a host Intel-processor board and takes advantage of the new PCIe Expansion Plane definitions in the VITA 65 OpenVPX standard to provide off the shelf backplane support for high-speed interconnection between pairs of SBC/GPU. Curtiss-Wright Controls Embedded Computing, Ashburn, VA. (613) 254-5112. [].

Low-g Range Accelerometer Series

A dedicated product family of low-g range accelerometer chips and modules is designed to support a variety of zero-to-medium frequency aerospace, automotive, defense, energy, industrial and general test & measurement requirements. The LG Series from Silicon Designs provides high-drive, low-impedance buffering for high-reliability performance in temperatures up to 125°C within a rugged, anodized aluminum housing. The LG Series accelerometer modules produce two analog voltage outputs which

vary with acceleration and feature a four-wire connection in support of both single-ended and differential modes. The sensitive axis is perpendicular to the bottom of the package, with positive acceleration defined as applied force to the bottom of the package. Signal outputs are fully differential about a common mode voltage of approximately 2.5V and may be powered with a 9V battery. Sensitivity is independent from the +8 to +32V supply voltage. At zero acceleration, output differential voltage is nominally 0 VDC and ±4 VDC at full-scale acceleration. On-board voltage regulation and an internal voltage reference eliminate precision power supply requirements. The LG Series is also relatively insensitive to temperature changes with quick, easy self-calibration. Silicon Designs, Issaquah, WA. (425) 391-8329. [].

Free LabView Link for Data Translation USB and PCI

A library of Virtual Instruments (VIs) enables National Instruments LabVIEW programmers to access the data acquisition features of DT-Open Layers-compliant USB and PCI devices from Data Translation. LV-Link 3.0 provides the ability to quickly and easily measure and control analog I/O, digital I/O, quadrature decoders, and counter/timer signals, and stream data at full-speed. Version 3.0 features complete support for 32- and 64-bit LabView along with updated help to speed development time. It also includes new and updated example programs to aid application development. Data Translation is a designer and manufacturer of high performance USB and Ethernet (LXI) data acquisition (DAQ) modules for temperature, voltage and vibration measurement and analysis, with accompanying software solutions for the test and measurement market. The software is provided free and can be downloaded directly from: Data Translation, Marlboro, MA. (508) 481-3700. [].




Tiny 1.5W Isolated Low Noise DC/DC µModule Converters Include Transformer

Two 1.5W output DC/DC µModule converters with 725VDC galvanic isolation are each packaged in a 9 mm x 11.25 mm x 4.92 mm BGA (ball grid array) package. All components, including the transformer, control circuitry and power switches are housed in a small enclosed BGA package for superior interconnect reliability in high vibration applications. These compact products from Linear Technology break ground loops in applications such as industrial, avionics and instrumentation equipment. Both devices operate from an input voltage of 3.1V to 32V, delivering a regulated output voltage on the secondary side, adjustable from 2.5V to 12V (LTM8047) and 1.2V to 12V (LTM8048). The LTM8048 includes a low noise linear post regulator that reduces the output ripple noise to 20µVrms at 300mA. The LTM8048’s isolated post regulator delivers an output voltage accuracy of 2.5 percent. The low noise performance of the LDO delivers a clean supply rail, improving the performance of high accuracy mixed signal converters. Additional features available on both products include overcurrent protection and adjustable soft start. The LTM8047 and LTM8048 are available in three temperature grades, E and I from -40°C to 125°C; and MP for the -55°C to 125°C operating junction temperature range. Pricing starts at $8.25 and $8.75 respectively for 1,000-piece quantities.

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Linear Technology, Milpitas, CA. (408) 432-1900. [].

Touch Screen HMI Displays Speed Development

A series of touch screen HMIs offers built-in Ethernet communications, advanced alarming/recipe/data logging capabilities and live video input/display capabilities. By allowing direct resetting of faults, the NS Series HMIs from Omega Engineering save time and effort in troubleshooting and quickly return your lines to production. The NS Series achieves flexible data access to a variety of devices. It enables operators to reach the devices on the network including special I/O units, intelligent devices, and PLCs. Screen project design time is cut from days to a few hours by preprogramming function blocks that easily drag-and-drop into a program. All you do is specify values for key parameters. The built-in Smart Active Parts library lets you establish communications and parameters for a wide range of products. Just select the product and drag its icon into your project and it automatically sets the correct protocols. A device monitor function that enables monitoring the PLC I/O data required for device maintenance and debugging is included as a standard feature of the NS12. Ladder monitor lets you monitor PLC program status, search for addresses or instructions, monitor multiple I/O points, and much more. It only takes about 5 seconds to switch from a user screen to the ladder program monitoring screen. The integrated simulation function simulates ladder programs and screen data simultaneously even without the actual hardware. Operation is also simple just click the icons, that’s it. No extra software needed. Two of the models are the NS5 at 7.68 x 5.59 x 2.13 inches and a screen resolution of 320 x 240; and the NS12 at 12.4 x 9.49 x 1.9 inches and a resolutions of 800 x 600.

Get Connected with technology and

Graphics-Capable HMI companies for Mobile Machinery providing solutions now

Get Connected newlarge resource forDisplay further exploration A new graphics-capable HMI comes with isa a4.3” TFT into products, technologies and companies. Whether and has been designed especially for vehicles and mobile machines that your goal is to research the latest fromcomplies a company,with speak directly are used in harsh environments. The BTM 012datasheet from Jetter an Application Engineer, or jump to a company's technical page, the the applicable safetywith requirements as to ambient temperatures, shock, goal of Get Connected is to put you in touch with the right resource. vibration, electromagnetic tightness (IP65 front Whichever compatibility level of service youand require for whatever type of technology, panel). The night design serves for Get Connected will help you connect with the companies and products safely operating theyou device at night. are searching for. The display brightness and key ing can be adjusted in the application program according to the ambient brightness. With the help of a digital potentiometer, the user can quickly and easily navigate to the respective applications. Get Connected with technology and companies prov A MicroSD card slot allows data Get Connected is a new resource for further exploration into pro from a company, speak directly with an Application Engine exchange or data storage.datasheet There are in touch with the right resource. Whichever level of service you requir two independently functioning CAN Get Connected willremote help youperipherals. connect with the companies and produc busses available for communication with CANopen and SAE J1939 are offered as standard protocols. For data exchange, the BTM 012 has been equipped with an Ethernet interface, a USB port and four video inputs (multiplexed).

Jetter AG Ludwigsburg, Germany. +49 7141 2550 - 466. [].

Products Get Connected with companies and products featured in this section.

Omega Engineering, Stamford, CT. (203) 359-1660. []. Get Connected with companies and products featured in this section.




Flexible FPGA and I/O Complement SBCs in VITA 57 offering

COM Express Type 6 Module Boasts Quad-Core Processor

Kontron, Poway, CA. (888) 294-4558. [].

congatec, San Diego, CA. (858) 457-2600. [].

With VITA 57 FPGA Mezzanine Card (FMC)-based designs, OEMs can minimize latency for high data throughput in their COTS designs and still maintain flexible I/O configuration. The FMC optimizes the handling and formatting of data and is approximately half the size of a PMC. This makes the VITA 57 products from Kontron an attractive fit for applications where size, weight, and power (SWaP) are critical. Thanks to the modular approach of VITA 57-based designs, OEMs benefit from reduced development costs by integrating multiple functions into a single PCI Express-enabled FPGA. The Kontron FPGA Mezzanine Card FMC-SER0 is a multi-channel interface card for buffering up to 16 IEA-232 or 8 EIA-422 serial lines. With a standard air cooled build, it provides up to 24 General Purpose I/Os at the front via 50 pin Tyco front connector for direct connection of peripherals. The rugged conduction cooled build complies to VITA 47-Class CC4 and is suitable for the extended temperature range -40 °C to 85 °C. With power consumption as low as 27W, which is typical with Freescale MPC8640 1.00 GHz, the Kontron 6U VME SBC VM6250 reaches a new performance level while staying within a tight power envelope. The Kontron VM6250 combines high processing power with exceptional memory bandwidth with a choice of Freescale MPC8640 1.00 or 1.25GHz single- or dual-core processors; or Freescale MPC8641 1.33GHz single- or dual-core processors. Prepared to host a customerspecific FPGA, it also offers a mezzanine extension slot for FMCs. The Kontron 6U VME SBC VM6050, with an Intel Core i7 processor, combines extremely high x86 computing and graphics performance with flexible and modular expansion possibilities in four different ruggedization levels. OEMs can tailor the Kontron VM6050 to the individual requirements of new and existing applications and benefit from a reduced time-to-market. Featuring a FPGA site, it can be expanded via two mezzanine sockets for up to two XMC/PMC or one FMC (VITA 57 FPGA I/O) cards. With the Kontron 3U VPX FMC carrier board VX3830, OEMs can easily expand the I/O flexibility of their dedicated VPX systems. The Kontron 3U FMC carrier board VX3830 is based on a Xilinx Virtex-5 FPGA and offers enhanced I/O capabilities with high integrated performance logic. A Virtex-6 version is also under development. Kontron is currently implementing key customers’ demands to the feature set, such as an external high speed memory.



A new high-performance COM Express module for future designs features the Type 6 pin-out and digital display interfaces to ensure improved display options and increase bandwidth with additional PCI Express Lanes available. The conga-TM67 module from congatec features the second generation of Intel Core processors – such as the quad-core Intel Core i7-2710QE processor (2.1 GHz, 45W, PGA) and the dual-core Intel Core i5-2510E processor (2.5 GHz, 35W, PGA) with up to 8 GByte high-speed dual-channel DDR3 memory (1333 MHz). Type 6 pin-out is the ideal solution for the implemented Intel QM67 Express chipset series and its following generations. In addition to VGA and LVDS, it offers three digital display interfaces, each of which can be configured for DisplayPort (DP), HDMI or DVI. Unlike Type 2 modules, these are no longer multiplexed. Type 6 also provides a PEG (PCI Express Graphics) port enabling connection to other highperformance graphics components and thereby offering maximum display support for gaming and medical applications. The main highlight of the COM Express Basic (95x125 mm) module is its graphics capacity. 3D performance has again been significantly increased by comparison with previous Intel generations. The Intel HD graphics supports Intel Clear Video Technology and DirectX Video Acceleration (DXVA) for faster video processing. Thanks to the increase in computing power offered by the second generation of the Intel Core processor family, the conga-TM67 is the ideal graphics solution for gaming, medical technology, automation and digital signage applications. The integrated video coding function enables realtime processing of incoming video streams. Seven PCI Express Lanes, PCI Express Graphics (PEG) x16 Lanes for high-performance external graphics cards, eight USB 2.0 ports, four SATA interfaces with RAID support, one EIDE and a 1GB Ethernet interface make for fast and flexible system updating. Fan control, an LPC bus for the easy connection of Legacy I/O interfaces and Intel® High Definition Audio round off the range of functions on offer. All conga-TM67 modules are fitted with the new UEFI embedded firmware solution. The congatec board controller comes with an extensive embedded PC feature set. The independence from the x86 processor means functions such as system monitoring and the I²C bus work faster and more reliably – even when the system is in standby mode. A COM Express Type 6-compatible evaluation carrier board is also available.


Wide Temperature Box PC with Second Generation Sandy Bridge

A high-performance fanless embedded controller integrates 2nd Gen Intel Core i7, i5, i3, and Celeron Sandy Bridge mobile series processors and is equipped with a maximum 5 GbE LANs, DVI-D/HDMI and VGA dual display, CFast, SUMIT A, B, and two 2.5” SATA 6Gp/s HDD/ SSDs, and 2 eSATA ports. The EC-5500 Series from Vecow uses a fanless thermal and housing structure enables systems to operate from -20ºC to +70ºC. This scalable architecture can be optimized for individual embedded applications and provides performance, I/O, thermal conductivity and power use enhancements. 2nd Gen integrates QM67 graphics subsystem and with EC-5500 dual video out ports (DVI-D/HDMI and VGA), when the task is graphics intensive, EC-5500 series can provide winged fast performance and HD-quality output. A number of Intel technologies supports speedy platform control, high resolution multi-display graphic, and advanced security possibility. The EC-5500 series supports dual channel SO-DIMM DDR3 1333/1066MHz up to 16GB for boosting system performance. To designate a wide range of applications, EC-5500 series feature with variety I/O and interfaces. Including 6 USB, maximum 5 RJ-45 Gigabit Ethernet ports, CFast , 2 eSATA, 2 mini-PCIe, DC-Jack Connector, 3 RS-232 and 1 RS-232/485/422, 8 in/out GPIO, and 2 SATA III (6Gb/s) 2.5” HDD/SSD connectors. The EC-5500 series is constructed with wide DC input range from 6 to 36 voltages and are equipped with 2 front-panel access SATA III (6Gb/s) 2.5” removable HDD/SSD trays with key lock. For different application, Vecow also provide Isolated DIO and SUMIT A, B enable better power supply protection and various I/O adoptions to select.

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Vecow, Taipei, Taiwan. +8862 2268 5658. [].

Rugged IP67 Ethernet Switch for Cost-Sensitive Networking Requiring High Reliability

A rugged low-cost IP67 Ethernet switch targets homeland defense applications. The DuraNET 10-10 from Parvus is a lower-cost alternative geared towards civilian defense and mobile tactical / critical infrastructure applications. Without sacrificing reliability or performance, the product boasts a dust- and water-proof design with IP67 environmental protection that will appeal to more cost-sensitive commercial user applications that may not require MIL-STD compliance. Featuring a robust mechanical design and extended temperature operation from -40ºC to +85ºC (-40ºF to +185ºF), the DuraNET 10-10 network switch provides five 10/100 plug-and-play Ethernet ports over rugged field deployable RJ45 or M12 connectors in a sealed and fanless metal chassis designed for mounting to any machine or flat surface. With provisions for exposure to wide thermal ranges, shock, vibration, dust particles, and liquid immersion, the rugged DuraNET 10-10 combines a PC104 Ethernet switch and vehicle-grade power supply components in a rugged package designed for maximum reliability under extreme conditions, including provisions for hazardous locations and potentially explosive atmospheres. The DuraNET 10-10 is designed to provide local area network (LAN) connectivity to IP-enabled equipment, such as onboard computers, cameras, sensors, monitoring devices, and command-and-control gear for situation awareness and information sharing. Any of its five transceiver ports are flexibly designed to serve as an uplink. Support for auto-crossover, auto-polarity, auto-negotiation, and bridge loop prevention are all integrated. A non-blocking switching fabric provides excellent data transmission performance at wire speed. Parvus, Salt Lake City, UT. (801) 483-1533. [].

Get Connected is a new resource for further exploration Remote CNC Pendant into Control Card Supports 32 products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly Devices

with an Applicationwith Engineer, or jump to a company's technical page, the A remote pendant controller keypad input, LCD controller, goal of Get Connected is to put you in touch with the right resource. encoder, digital and analog inputs and digital outputs is designed for fast Whichever level of service you require for whatever type of technology, real time PC basedGet control systems.willThe from with Mesa Connected help 7I73 you connect theElectronics companies and products communicates with you theare host via a robust searching for. RS-422 link with 100 ft maximum link distance. Standard CAT5 cables are used for wiring convenience. The 7I73 is supported by Mesa’s low-cost FPGA cards which present a simple parallel register interface to the host, with all protocol details handled by the Get Connected with technology and companies prov smart interface. Get Connected is a new resource for further exploration into pro One FPGA card candatasheet supportfrom upa company, speak directly with an Application Engine in touch with the right resource. Whichever level of service you requir to 32 external devices and up to 3072 Get Connectedawill help you connect with the companies and produc control points while still maintaining 10 KHz service rate for all points. This high service rate allows much better control feel than USB, wireless, or other non-real time pendants. The keypad input can support up to 64 keys. Up to 4 quadrature encoder inputs are provided for MPG use. 8 analog inputs, 16 digital inputs and 10 digital outputs are available as well as a support for 2/4 line 20/40 character LCD. The 7I73 is suited for high performance industrial automation and machine tool applications. Price of the 7I73 in quantity 100 is $35.


MESA Electronics, Richmond, CA. (510) 223-9272. []. Get Connected with companies and products featured in this section.

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with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

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Advanced Micro Devices, Inc.............................................................................. Arrow Electronics, Inc......................................................................................... 5.................................................................................................. Axiomtek Co., Ltd.............................................................................................. 26.End of Article Products Cogent Computer Systems, Inc.......................................................................... Elma Inc............................................................................................ 2................................................................................................... GetElectronic, Connected with companies and Get Connected products featured in this section.

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Embedded World 2012...................................................................................... 41................................................................................... Extreme Engineering Solutions, Inc...................................................................... Intel Corporation................................................................................................ 30................................................................................................... Get Connected with companies mentioned in this article. LogicConnected Devices, Inc.............................................................................................. 27....................................................................................... Get with companies and products featured in this section.

Logic Supply, Inc............................................................................................... 10......................................................................................... Measurement Computing Corporation................................................................

MEN Micro, Inc.................................................................................................. Mentor Graphics Corporation............................................................................. 45............................................................................................... MicroTCA Showcase.......................................................................................... 28......................................................................................................................... MSC Embedded, Inc.......................................................................................... Nallatech, Inc.................................................................................................... 38............................................................................................ One Stop Systems, Inc....................................................................................... Phoenix International.......................................................................................... Prism Computer Solutions.................................................................................. RTECC.............................................................................................................. Super Micro Computer, Inc................................................................................. WDL Systems.................................................................................................... 21........................................................................................

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.



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Visit Us For More Information ©Super Micro Computer, Inc. Specifications subject to change without notice. Intel®, the Intel® logo, Xeon®, and Xeon inside®, are trademarks or registered trademarks of Intel Corporation in the US and other countries. All other brands and names are the property of their respective owners.

Versatile, Whisper Quiet and Highly Configurable SuperServer® 5037C-i/T

Fueling Innovation for Tomorrow’s Technology……Today AMD is ushering in a new era of embedded computing. The AMD Embedded G-Series processor is the world’s first integrated circuit to combine a low-power CPU and discrete-level GPU into a single embedded Accelerated Processing Unit (APU).

AMD is also proud to offer extended availability of the AMD Geode™ LX processor family until 2015.

Learn more about new levels of performance in a compact BGA package at: © 2011 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, ATI, the ATI logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names are for informational purposes only and may be trademarks of their respective owners. Features, performance and specifications may vary by operating environment and are subject to change without notice. Products may not be exactly as shown. PID# 50599C

RTC magazine  

January 2012

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