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The magazine of record for the embedded computing industry

October 2011




Memories Advance in Speed and Nonvolatility Energy Systems Gain Intelligence, Shed Waste Safety-Critical Systems: More than Reliability An RTC Group Publication

THREE AIRCRAFT, A SINGLE MODEL, AND 80% COMMON CODE. THAT’S MODEL-BASED DESIGN. To develop the unprecedented three-version F-35, engineers at Lockheed Martin created a common system model to simulate the avionics, propulsion, and other systems, and to automatically generate final flight code. The result: reusable designs, rapid implementation, and global teamwork. To learn more, visit

©2011 The MathWorks, Inc.


50 Sandy Bridge in PC/104 Form Factor—i7, 2.2 GHz PCIe/104 SBC

52 Multifunction USB Modules for Low-Cost Data Acquisition


55 4-Port and 2-Port USB 3.0 Host Controllers Broaden Choices



Technology in Context


Nonvolatile Memory

Designing Safety-Critical Systems

in Nonvolatile Memory 6Editorial 18 Advances Steve Jobs Interfaces Keep Pace with the Data Volume Industry Insider 8Latest Developments in the Embedded Marketplace Terry Grunzke, Micron Technology


Small Form Factor Forum When DId Legacy Become a 4-Letter Word?

& Technology 50Products Newest Embedded Technology Used by Industry Leaders

EDITOR’S REPORT Advances in Memory

the Performance Gap: Making Memory Faster with 14Closing Algorithms and Logic Tom Williams

the Cost of Developing 36Reducing Safe, Secure and Resilient Industrial Control Systems Jim McElroy, Green Hills Software


Industry watch

Network Processing

Wireless Networking

What You Pay For: Optimizing the 4G Phenomenon: PCIe Accelerator Card Designs Part 2 40Demystifying 24 Getting the Future of MultiTECHNOLOGY IN SYSTEMS Gigabit Wireless Communications 46Defining Matthew Dharm, JumpGen Systems

Todd Mersch, RadiSys

Technologies for Energy Intelligence

Ali S. Sadri,

Smart Grid Built on Smart 28 The Objects Will Challenge Developers

Bill Weinberg, Linux Pundit and The Olliance Group

Smart Grid Tipping Point for Electric Vehicles: Closer than You 32 The Think Jim Zyren, Qualcomm Atheros

Digital Subscriptions Avaliable at RTC MAGAZINE OCTOBER 2011



OCTOBER 2011 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Sandra Sillion, COPY EDITOR Rochelle Cohn



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The magazine of record for the embedded computing industry



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The magazine of record for the embedded computing industry

Free Online Spotlighting the Trends and Breakthroughs in the Design, Development and Technology of Embedded Computers. Search Archived Editions along with the Latest News in the Embedded Community. An RTC Group Publication



To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2, Scotts Valley, CA 95066 Phone: (831) 335-1509

Published by The RTC Group Copyright 2010, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

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Steve Jobs


he first time I actually met Steve Jobs was back around 1978 or 1979 at a Regis McKenna reception. Regis McKenna was the premier Silicon Valley advertising and PR agency of the day. Their major client at the time was Intel. I had talked to Jobs on the phone a couple of times previously but never met him in person until then. So we’re all standing around at this fancy reception in our three-piece suits and cocktail dresses eating canapés and being the consummate sophisticated yuppies of the day, when this dude comes walking through the crowd in cut-offs, with his shirt untucked, with unkempt long hair and a scraggly beard. That was Steve Jobs. Regis McKenna, for reasons and insights known only to him, had taken on Apple as a client. Regis soon got after Steve about how he had to dress to be credible in business. Regis had enough pull to get the high-end San Francisco haberdasher, Wilkes Bashford, to close his store long enough to cater to Steve. He sent his account manager up with Steve and they got him an entire wardrobe. The next time I met him, he was dressed like the rest of us, but I still remember how completely comfortable he seemed with himself in those cut-offs. How do we know what things and what people we encounter in life are going to profoundly influence us through the years? I arrived in Silicon Valley in 1977, the year the Apple II was released, and shortly thereafter was working as editor of a publication called Dr. Dobb’s Journal, which in those days was fully named Dr. Dobb’s Journal of Computer Calisthenics and Orthodontia—Running Light without Overbyte. That was the burgeoning beginning of the personal computer era, a time overflowing with creative activity and whimsy like the title of that magazine. It fostered many now-forgotten names introducing machines. They were differentiated by different processors, different operating systems (using that term loosely), different floppy disk formats, etc. The two that stood out were the Apple II and the IBM PC, which was introduced in 1981. Both were based on a bus into which you could plug selected peripheral cards. In short, they still appealed to geeks and techies but they also wakened the longings of ordinary users. Then, in 1984 Steve Jobs surprised the world with the introduction of the Macintosh. The geeks and techies were dumbfounded. It was a closed box. There was no bus. You couldn’t get into it and tinker with it. And it worked flawlessly right out of the box! And regular people could do real work with it without being intimidated by the technology—very sophisticated technology—



Tom Williams Editor-in-Chief that was hidden within that box. I was at that introduction in 1984, and none of us realized at the time that this day represented the turning point for how Steve Jobs and Apple would bring technology into the wide world for all to use. For years, when people have asked me what embedded systems are, my answer has been, “Basically, it’s hiding the computer behind its own usefulness.” That is exactly what Steve Jobs did with the introduction of the Macintosh. And that is how he approached every Apple product after that. He was the supreme master of hiding the computer behind its own usefulness. I am no more supposed to be aware that there is a computer running my iPhone than I am that there is one inside the gas pump I am using. Steve Jobs’ seemingly relaxed, often irascible, nature had buried within it an energy and a quest for perfection every bit as intense as the computing power he put inside every Apple product. Where others might pay lip service with a cliché like “user friendly,” Jobs insisted that every Apple product be not only intuitive to use, but also styled to fit smoothly into the user’s lifestyle. At the same time, the products like the iPod, the iPhone and now the iPad helped actually shape the lifestyle of their users. That lifestyle change has created a demand for products that has resulted in a proliferation of similar products such as the world of Android-based smartphones and tablets—all trying to leverage off of the creative genius of Steve Jobs. Recently, Samsung flew a little too close to the flame, at least in the view of the German courts, and its latest tablet has been banned in that country for being too close to the iPad. The embedded industry has been heavily influenced by Jobs, even though we may not be aware of it. Things with 32-bit CPUs, RTOSs, sensors and actuators are supposed to function within the world understood by the user, be he/she a factory shop foreman, a pilot, a transit worker or a medical doctor. The latter doesn’t want to know how to get the needed readings from a patient. He or she just wants the medical data in a form that can be used. And now, we see a bit of a convergence starting to happen with iPhones running apps that can communicate with industrial controllers and medical instruments to name a few. All they need is the data from and a link to that embedded, dreaded, computer and they can process it into the natural, intuitive environment of the user and in the same environment they use for the other things in their lives. This is a trend I predict will grow and for that we have Steve Jobs to thank. He showed us so much with his short life.

X-ES 2nd Generation Intel® Core™ i7 Processor Solutions: Delivering Innovation In 2010, Extreme Engineering Solutions, Inc. (X-ES) developed more Intel® Core™ i7 processor products based on VPX, CompactPCI, VME, CompactPCI Express, and XMC form factors than anyone in the industry. This year, X-ES has added solutions based on the 2nd generation Intel Core i7 processor. Providing products customers want, when they want them – that truly is innovation that performs. X-ES offers an extensive product portfolio that includes commercial and ruggedized single board computers, high-performance processor modules, multipurpose I/O modules, storage, backplanes, enclosures, and fully integrated systems. 2nd generation Intel Core i7 processor solutions available in a variety of form factors. Call or visit our website today.


INSIDER OCTOBER 2011 ZigBee Alliance Passes 300 ZigBee Certified Products Milestone The ZigBee Alliance has announced it has approved 341 ZigBee Certified products. This growth is more than 80 percent over last year’s 187 ZigBee Certified products. ZigBee standards have been adopted by more than 350 global manufacturers with representing annual revenues exceeding $1 trillion, according to a 2010 report from ONWorld. The ZigBee Certified products are used by millions of consumers and businesses worldwide. The growing list of ZigBee standards, now at 10, appeals to manufacturers wanting to offer their customers smart, green and easy-touse products on an interactive wireless sensor and control network. The ZigBee Certified program tests the functionality and interoperability of products using ZigBee standards and specifications. The certification of products is a critical part of the ZigBee Alliance’s standards development process. Unlike most other standards groups, the testing and certification of products is required before any ZigBee standard or specification is released for use. The ZigBee Certified process allows manufacturers to deliver a variety of products to customers of all types who can benefit from the simplicity of ZigBee control.

VIA Sues Apple for Patent Infringement

In what may appear to be a turnabout, VIA Technologies has announced it has taken legal action against Apple Inc., filing a complaint with the United States International Trade Commission (ITC) and the U.S. District Court of Delaware for patent infringement by Apple’s iPhone, iPad, iPod, Apple TV product lines and associated software. “VIA has built up an extensive IP portfolio consisting of over 5,000 patents as a result of significant investments in world class technology research and development,” commented Wenchi Chen, CEO, VIA Technologies, Inc. “We are determined to protect our interests and the interests of our stockholders when our patents are infringed upon.” The patents at issue cover microprocessor functionality featured in Apple iPhone, iPad, iPod and Apple TV devices, namely:



•U  .S. Patent No. 6253312 – Method and apparatus for double operand load. • U.S. Patent Nos. 6253311 & 6754810 – Instruction set for bi-directional conversion and transfer of integer and floating point data. Apple has been in aggressive actions against competitors for alleged infringement on its iPhone and iPad designs, so the attack coming from the other direction is at least entertaining.

BIOS Rootkit Infects China

Malware, such as viruses and worms, typically infect systems in user space, where applications run. A few dig deeper, infecting the system’s kernel; these are called rootkits. A new piece of malware digs even deeper, infecting systems before the operating system even loads. Dubbed “BMW virus” by Chinese antivirus vendor Qihoo 360, a new rootkit successfully

infects key areas of a computer system: the BIOS, the Master Boot Record (MBR) and key Windows files. Symptoms of infection include the phrase “Find it OK” on the screen at start up, an antivirus virus warning of a “Hard Drive Boot Sector Virus” and a browser home page redirect to htm (which does not point to an active web site). Infection vectors include a compromised game download with a system restart required. BMW appears to be limited to China. The BIOS or Basic Input/ Output System is stored on a ROM and is responsible loading and checking the hardware for the system in advance of loading the operating system. Failure to “boot” the system from the BIOS generally means failure of the system. While infection at this time may seem novel, there have been other BIOS malware. In the 1990s CIH/Chernobyl required the motherboard of infected systems to be replaced. More recently, in 2007, the ICELord BIOS rootkit affected only Award BIOS systems. ICELord may have been the basis for the new BMW rootkit.

3,000 GPS Shoe Devices Shipped for Tracking Dementia Patients

GTX Corporation has announced the FCC certification of the GPS Shoe and the delivery of the first 3,000 units to shoe partner Aetrex Worldwide. As millions of boomers are approaching 65, and in recognition of World Alzheimer’s Day on September 21, 2011, GTX announced the release of its first GPS tracking technology to be imbedded into comfort and wellness shoes for individuals

afflicted with Alzheimer’s disease and related dementia. “The GPS Shoe has the potential to be life saving, as well as life changing technology for those afflicted and their caregivers,” says Andrew Carle, who has been internationally recognized for coining the term “Nana” Technologies for describing technology for older adults. Carle has served as an advisor to GTX Corp for the past three years and is additionally director of the program in Senior Housing Administration at George Mason University in Fairfax, VA. “The shoes also hold the potential to save governments hundreds of millions of dollars in search and rescue operations, as well as in healthcare costs for those otherwise injured.” The World Alzheimer Report 2010 provides the clearest, most comprehensive global picture yet of the economic impact of Alzheimer’s disease and dementia. Over five million Americans suffer from Alzheimer’s, and without a cure, those numbers are expected to quadruple to more than 20 million in the U.S. and 106 million worldwide. Statistics show 60% of those afflicted will wander and become lost, and up to half of those lost who are not found within 24 hours may die, from dehydration, exposure, or injury. Because paranoia is a manifestation of the disease, many will remove objects placed upon them with which they are unfamiliar. However, habitual memory, which includes getting dressed, is the last type of memory retained in individuals with Alzheimer’s. The placement of the miniaturized 2-way GPS technology in comfort and wellness shoes is an efficient and useful monitoring solution for the estimated 15 million family and caregivers of people suffering from the disease.

Oracle Buys GoAhead

Oracle has announced that it has entered into an agreement to acquire GoAhead Software and add its standards-based service availability software to its communications industry portfolio. GoAhead has been a pioneer in the development and delivery of COTS service availability software for the communications and aerospace and defense industries. Network equipment providers (NEPs) and Systems Integra-

tors are moving to a standardized software and hardware platform that can deliver and manage highly available services. Oracle, with the combination of GoAhead technology, plans to deliver a comprehensive, standardsbased solution that supports the delivery of new services. NEPs and Systems Integrators should find it easier to deploy and maintain services for their customers and help them significantly reduce the cost and risk associ-

ated with bringing new services to market. GoAhead was the first software company in the industry to deliver a commercially available product based on Service Availability Forum (SAF) specificationsâ&#x20AC;&#x201D;the most widely adopted standard for service availability software. Oracle has been an active member of the Service Availability Forum and OpenSAF communities and plans to continue to participate and support

these initiatives after the acquisition closes.

Linear Technology Teams with AEi Systems to Offer WCCA and SPICE Modeling

Linear Technology has signed and implemented a multiyear cooperation agreement and program with AEi Systems, a leader in worst case circuit analysis (WCCA) and SPICE

640.79 (2.27%) This data is as of October 13, 2011. To follow the RTEC10 Index in real time, visit COMPANY






Adlink Technology












Concurrent Computer

















Interphase Corporation

















Performance Technologies






PLX Technology






RadiSys Corporation






Elma Electronic

Mercury Computer Systems

RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities. RTEC10 is sponsored by VDC research

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTC MAGAZINE OCTOBER 2011



modeling. Under the agreement, AEi Systems and Linear Technology offer customers and partner organizations (including M.S. Kennedy and Aeroflex) design and analysis assistance for circuit design and use of Linearâ&#x20AC;&#x2122;s radiation-hardened (RH) products in space and other radiationhardened applications. AEi Systems is developing and maintaining a database of SPICE models and performance data necessary to perform worst case analysis of Linear Technologyâ&#x20AC;&#x2122;s rad-hard products, as well as ICs and hybrids from M.S. Kennedy and Aeroflex, such as the popular MSK58xx series or the VRGxxxx series of linear regulators. AEi Systems also provides Linear customers and partners with nominal SPICE

models of Linearâ&#x20AC;&#x2122;s RH products at no charge. In addition, using AEi Systemsâ&#x20AC;&#x2122; extensive knowledge base, AEi Systems performs WCCA and provides design support for integration of Linear Technology ICs into new and upgraded customer designs.

RTI Selected to Sponsor Interoperable Open Architecture 2011

Real-Time Innovations (RTI) has announced that it has been selected as lead sponsor for the upcoming Interoperable Open Architecture 2011. This event brings together global leaders in defense procurement strategy from the U.K. Ministry of Defence (MOD), U.S. Department of Defense (DoD),

French Direction GĂŠnĂŠrale de lâ&#x20AC;&#x2122;Armement (DGA), Canadian Department of National Defence (DND), the European Defence Agency (EDA), NATO, and other defense organizations. The purpose is to share ideas on how to create a more efficient procurement process for defense systems. The Interoperable Open Architecture conference, presented by the International Quality and Productivity Center (IQPC) and promoted by Defence iQ, offers delegates the opportunity to explore the recent shift in the way defense procurement is taking place. Increasingly, procurement agencies such as the U.S. DoD and U.K. MOD are mandating the use of data-centric integration

strategies in open architecture to achieve systems-level interoperability, thereby creating a more open and competitive procurement environment. By specifying a common architecture across a multitude of similar platforms, defense agencies are greatly reducing throughlife maintenance and modification costs while increasing opportunities for innovation. The intent is to provide systems to the military that are more rapidly adaptable to changing warfighter conditions. As lead sponsor and host, RTI will be presenting a paper on proven open-architecture strategies for systems integration and participating in a panel discussion exploring the future of defense procurement strategy.

Marvell Armada300 System On a Module The CSB1724, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, low-power, ARMADA 300 (Sheeva ARMv5TE) based System on a Module (SOM). The CSB1724 provides a small, powerful and flexible engine for Embedded Linux based Gigabit networking and storage applications. y y y y y y y y y

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Colin McCracken & Paul Rosenfeld

When Did Legacy Become a 4-Letter Word?


nce upon a time, embedded systems engineers would anxiously scan data sheets for new embedded components and boards looking for those magical words “Backward Compatible” or “Upward Compatible” to provide some level of assurance that the customized hardware and software they had developed over the years would continue to work with the new thing they were considering. Embedded manufacturers, anxious to keep existing customers, realized that product upgrades represented the fastest time to revenue of all potential OEM opportunities, thereby mandating compatibility with prior solutions. At that time, the quickest way to kill a new product was to force the OEM to start development from scratch. The compatibility king, if you will, was Intel. All the x86 processors developed over the last 30 years continue to run code originally developed for the 64K memory space of the 8008 processor in 1973 (now affectionately known as “real mode”). For all you young'uns out there, that is really a K, as in kryptonite. As the few remaining engineers who may have been forced to sit through a computer architecture class might know, it was possible in those days to construct a complete embedded application in that space by carefully selecting each individual machine instruction. Can anybody under the age of 50 write assembler code today? But we digress. Sometime in the last ten to fifteen years we got lost. What Intel giveth, Intel taketh away. While real mode lives, the ISA bus that interconnected the processor with virtually all the I/O in original PC systems sadly does not. This first little chink in the compatibility armor sparked two simultaneous and ongoing sets of events. The first event was an industry-wide effort to find some possible way to replicate the bus external to the processor / chipset. This led to a number of bus bridge products that recreate much but not all of the original ISA bus. The second event was a massive engineering effort to start redesigning existing I/O (both hardware and drivers) to utilize new bus technologies. That sort of opened the floodgates. If Intel could kill off ISA, imagine what else we could dump. We have USB—who needs RS-232 serial ports? PS/2 keyboard and mouse—who needs ̓em?



The PCI bus just wastes a lot of pins. Who needs it? And the parallel printer port—well maybe that one was OK to kill. In the last ten years, we’ve moved from burying incompatibilities in spec sheets in the hope that no one would notice to shouting from the rooftops—Legacy Free. It’s tantamount to putting a big, bold, boxed warning sticker at the very top of the spec sheet: Guaranteed not to work with anything you’ve previously developed—hardware or software What’s next? Now that we have USB 3.0—do we really need to support the previous versions? And PCI Express Gen 2, let alone Gen 3. How quickly can we dump the previous versions and move on to the next generation? The really clever folks don’t bother to deal with revisions or gens at all—just create a new “type.” As each new type arrives, compatibility with existing types seems not to be a consideration at all. COM Express type 74 is just around the corner! The good news is that there are signs of resistance. Have you noticed the new PC/104 cards with the Atom processor and the ISA bus? Huh? The Atom chipsets don’t even support ISA. And where’s PCI Express? It doesn’t come off the board. Maybe it’s not required by the many OEMs who just want a new CPU to replace one that is EOL? Blasphemy. It’s time for suppliers to recognize that there is a lot more demand in the embedded space for “backward compatibility” than for the latest new whizzy bus or interface. I/O vendors reluctantly start new designs for the new bus architectures, looking for a CPU to plug into. CPU vendors look at the paucity of I/O cards that support the new bus architectures and wonder how an OEM can build a system. We got ourselves into this mess and we need to get ourselves out of it. It’s time for system OEMs to teach suppliers that legacy free means customer free. OEMs can and should adopt new technologies as the benefits from those technologies expand capabilities in their products, but they should insist on doing so only with products that incorporate a smooth, backward compatible migration path from the key technologies of yesterday.



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editor’s report Advances in Memory

Closing the Performance Gap: Making Memory Faster with Algorithms and Logic By taking memory access to a higher level of abstraction, a new interface approach is able to greatly enhance read/ write access speed without new process technology or higher clock speeds. by Tom Williams, Editor-in-Chief


t is an eternal truth of system design creasing power consumption, heat disthat something always winds up be- sipation and cost. Such an alternative ing the bottleneck. In the case of approach—based on creative archiASIC/SoC design, and presumably gen- tecture and IP—is now being brought eral system design as well, that bottle- to the memory performance issue by neck is becoming the performance gap a new company named Memoir Sysbetween thenow processor and its memory. tems. Memoir’s approach is based on nies providing solutions Part of this is due to raw processor surrounding existing memory technolion into products, technologies and companies. Whether your goal is to research the latest speed, a big part of it results ogy in terms of process/geometry and ation Engineer, or jump but to a company's technical page, the goalfrom of Get Connected is to put you you require for type of technology, thewhatever requirements of networks and multi- memory type (DRAM, SRAM, DDR2, and productscore you are searching for. The question that must DDR3, etc.) with a layer of IP logic that processors. now be addressed is how to close this takes memory access to a higher level of soon-to-be-yawning performance gap abstraction via creative algorithms for encoding, compression, virtualization (Figure 1). In fact, it was the advent of the mul- and management. The idea is to add more external acticore processor that proved there must cess points to the surrounding IP that be another approach to enhancing perwill create an interface that will be able formance beyond simply flogging the to do multiple accesses to the memory silicon with higher clock speeds. The array in a single clock cycle, while acmulticore approach yielded significantly cessing data at the level of single adhigher throughput without hugely indresses. For example, a given singleport memory process technology with a Get Connected with companies mentioned in this article. clock speed of 500 MHz could be able to perform four memory operations

End of Article


OCTOBER 2011 RTC MAGAZINE Get Connected with companies mentioned in this article.

(MOPS) at an effective external clock speed of 2 GHz. So at the system level, that memory would effectively be running at 2 GHz. The memory appears as a standard multiport memory (Figure 2). This is accomplished through the addition of external IP logic and in no way involves a redesign of the memory itself. According to Sundar Iyer, CTO of Memoir, the memory consists of a number of banks and different banks can be accessed in parallel. Each bank has its own physical address and data bus. Thus, four external accesses that addressed four different banks could take place in parallel in a single clock cycle. The matter gets more complex when all four addresses are within a single memory bank. In such a case, one of the writes would be posted to its address and the remaining three would be cached or buffered either in locations within other banks of the memory or in the surrounding Memoir IP. These actual addresses are a form of virtual address that is kept track of in scratchpad memory so that they are correlated with the intended address. Since successive reads and writes can come in fast and furiously and in all kinds of combinations, the logic in the Memoir IP has to be able to manage all the patterns of hot spots and multiple accesses to the same bank and cache them intelligently. When there is time, the IP can move them and rearrange them. “Of course,” Iyer notes, “you could also have a worst case for life, so we have to intelligently rearrange things so that the operations continue to be posted.” If the process of writing seems complex, the read process gets even hairier. In the case of a two-read access, for example, if the application wants data from the same memory bank, they cannot be accessed in parallel and trying to access them sequentially would cost performance. Therefore, all the data that is stored in the physical memory is encoded using a variety of schemes such as algorithms

editorâ&#x20AC;&#x2122;s report

an embedded ASIC or SoC design. The technology is also at least theoretically applicable to memory chips, but the initial implementation is targeted for memory integrated into embedded devices.

Memoir also has developed an analysis tool that lets the developer select a combination of characteristics for the desired memory. Using this synthesis platform (Figure 3), the developer

Processor-Memory Performance Gap 20 18 16 Normalized Growth Rate

for encoding, lossless compression, virtualization, etc., into coded metadata that is stored in a scratchpad area. Storing this metadata requires an overhead in terms of memory capacity of about 1.5 percent for a 2x performance increase. While not explicitly stated, that would appear to imply that a 4x performance increase would require a correspondingly larger amount of memory overhead. Memoir states that they are capable of achieving up to a 10x increase in performance. In the example of a two-address access from the same bank, the first data word could be retrieved directly, but the second cannot and would require decoding. This means that all stored data undergoes this metadata encoding. Three locations participate in the encoding of the metadata: the actual data, and the data in two other locations in two different memory banks. Then in order to retrieve the data from the second target address, the system takes the data in the two other locations (which it can access in parallel with the first target address) and uses the metadata in the scratchpad memory to recreate the data stored at the second target address. These schemes required extensive simulation and analysis to be able to manage all possible patterns and contingencies, and involve a large number of techniques that must all work together for all instances. According to Iyer, â&#x20AC;&#x153;You have to do it in a way that is deterministic so that every location is covered so that if you need to recreate it, you can always recreate it using the right combination of other locations. And the IP knows when you are doing a straight read from a given location.â&#x20AC;? The Memoir IP that connects to memory arrays is written at register transfer level (RTL) and is agnostic in terms of semiconductor process or geometry and fits into any standard design flow. In addition, it can connect to any memory architecture that accepts addresses and data. That gives developers a wide range of choices when selecting the memory and the technology they want to use for

Processor-Memory Gap becoming worse with time

14 12 10 8 6 4 2 0 2000




*Graph derived from approximating aggregate processing, memory performance data from ASIC data. Includes future projections.

Figure 1 Due to advances in processor architectures, particularly the advent of multicore processors, there is a huge impending gap between processor and memory performance.

Physical Memory 500 MHz Memory ...

Memoir Algorithmic Memory 500 MHz Memory ... Memoir IP

500 MOPS

Allows 500M I/O Operations

Allows 2000M I/O Operations

Scales Up to 10x Memory Operations Per Second (MOPS) Figure 2 A given memory technology consisting of numerous banks can be connected to innovative IP logic to parallelize faster external accesses and keep track of simultaneous reads and writes to and from the array without changing the underlying memory technology.



editorâ&#x20AC;&#x2122;s report



Memoir Memory Synthesis Platform



4X # Read

Real-time Ports

Synthesized Memory

# Write Reduced

... Feedback


Standard Power

Push Button Analysis Optimization


Figure 3 The Memoir synthesis platform can analyze different configurations of memory type, desired acceleration, number of ports and other parameters and give information about the resulting density, speed, power consumption and die size within seconds.

Performance (MOPS)

Physical Memory

Higher performance algorithmic memories

Memoir Higher Performance Memory Memoir Area Efficient Memory Memoir Power Efficient Memory


Higher density algorithmic memories


Power efficient algorithmic memories

Memory Density (Mb/mm2)


Power Efficiency (Mb/mW) Figure 4 Choices for interfacing to physical memory fall along three axes: performance, density and power efficiency. The Memoir IP and analysis tools allow the developer to evaluate a wide range of options.

can select a memory type in terms of DRAM, eDRAM, etc., and also by process geometry, such as 22nm. Then by selecting the number for read and write ports and the acceleration (2x, 4x, etc.), can almost instantly analyze the amount of power consumed and the die area for



that configuration and get a picture of the available tradeoffs for the desired design goals. In fact, the tool can be set up to provide an analysis for multiple instances of memory on the same die (all would, of course, use the same process geom-

etry). In many SoCs, such as network devices, there are numerous memory blocks that fill different roles and thus have different numbers of ports, different capacities and even different types. Such an analysis can provide a selection of options for the desired mix of characteristics for the target device die size and power requirements (Figure 4). Thus for a given physical memory type, there may be a number of combinations in terms of the number of ports, the memory density and the power efficiency. These could all be characterized for each given candidate geometry or only for the one that has been preselected. Memory performance thus becomes a programmable characteristic with its own set of tradeoffs for the system developer. And this performance enhancement and flexibility comes as a result of additional logicâ&#x20AC;&#x201D;not different, smaller or faster logic. Memoir Systems Santa Clara, CA. (408) 550-2382. [].

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Technology in

context Nonvolatile Memory

Advances in Nonvolatile Memory Interfaces Keep Pace with the Data Volume As the capacity of NAND flash devices increases, so does the amount of data that must be transferred on every read and write. In order to avoid degradation of performance, the speed of the interface must increase accordingly. by Terry Grunzke, Micron Technology



ith the ever-increasing demand for larger nonvolatile memory capacities, NAND flash technol120 ogy is widely used in a variety of appli100 cations today. It is an aggressively scaled technology, with 20nm-class lithography 80 devices currently in production. As the technology scales, page sizes typically in60 crease, which drives the sizes of the data Xfer Time transfers to become larger. To improve 40 Array Time performance and maintain latencies, the nies providing solutions now interface speeds must increase along with ion into products, and companies. Whether 1). your If goalthe is to research the latest 20 the technologies data transfer size (Figure ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you page widths or number of planes on the 0 you require for whatever type of technology, devicefor.double, the correspond8K page 16K page 8K page 16K page and productsNAND you are searching 200 MTIs 200 MTIs 400 MTIs 400 MTIs ing interface speed should also double to maintain similar data transfer times per ONFI 2.x ONFI 3.0 array access. This is especially imporFigure 1 tant in high-performance SSDs, USB 3.0, Transfer Time: As NAND technology advances, page widths and data transfer or other high-performance applications sizes become larger. The transfer time across the NAND interface must where bandwidth can improve greatly due become faster so the bus transfer is not a performance limiter. to the high density and the number of devices per data channel (Figure 2). sibility of data channel reduction in SSDs. the Open NAND Flash Interface (ONFI) Another consideration for increasing The same bandwidth from the NAND de- Workgroup released the ONFI 3.0 specithe NAND interface bandwidth is the pos- vices can be supplied to the SSD control- fication. This specification includes the ler with a faster interface and fewer data newly defined NV-DDR2 interface that channels. This can mean fewer pins on enables up to 400 MT/s NAND interface Get Connected the controller, resulting in smaller form speeds, doubling the frequency of the prewith companies mentioned in this article. factors and lower costs. In March 2011, vious standard.

End of Article



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technology in context

Cache Program 8KB page 200 MT/s


Cache Read 8KB page 200 MT/s

350 300


250 200 150 100 50 0 1




Number of LUNs per Channel

Cache Program 16KB page 400 MT/s Cache Read 16KB page 400 MT/s






0 1




Number of LUNs per Channel Figure 2 The ONFI 3.0 NV-DDR2 interface (lower chart) enables 400 Mbyte/s per data channel vs. the previous 200 Mbyte/s interface speed (upper chart) supported by ONFI 2.1 NV-DDR interface. LUNs refers to logical units, or dies, per channel.

To achieve a reliable 400 MT/s interface, improved signaling between the controller and the NAND device is required. Since NAND flash is used in a variety of applications, the system topology is an important consideration in determining the features required to improve the interface signaling. Due to the importance of achieving faster speeds for high-computing applications, the ONFI Workgroup decided that a widely used SSD topology should be used for evaluation in determin-



ing the features (Figure 3). The SSD tree topology used to evaluate 400 MT/s NAND interface speeds includes a host controller connected to two NAND packages with four NAND flash devices per package, for a total load of eight NAND devices. SSD form factors determine the distance from host to NAND devices.

Interface Features

To allow the NAND interface to attain 400 MT/s, several features were added to the ONFI 3.0 specification. User commands provide the system designer flexibility through optional enablement of these features (Table 1). This provides adaptability for optimal power and complexity versus performance tradeoffs. The features added to the ONFI 3.0 specification are discussed in more detail in a recent Webinar titled, “ONFI 3.0: Enabling 400 MT/s” ( Differential signaling is a method of transmitting information by means of two complementary signals that are 180° out of phase from the original signals. Previous NAND interfaces used a simpler technique called single-ended signaling. Differential signaling offers twice the noise immunity of single-ended signaling, reduced sensitivity to simultaneous switching output (SSO) noise, and mitigated radiated electromagnetic interference (EMI). For the ONFI 3.0 NV-DDR2 interface, differential signaling can be enabled for the read enable (RE) input and bi-directional strobe (DQS) signals. The flexibility of enabling or not enabling each of the complementary signals saves system pins and associated costs when differential signaling is not required. An external voltage reference input provides the high-speed differential input buffers with a common voltage reference. It is used by the single-ended, high-speed signals that require fast switching and do not have a complementary signal enabled. The use of the reference voltage also achieves additional system noise immunity. This allows tighter setups and holds during data input to the NAND device, providing more system timing margin. At higher interface speeds VCCQ = 3.3V can no longer be supported due to slew rate and timing budget requirements. Thus, the NV-DDR2 interface only supports VCCQ = 1.8V with reduced signaling. The popular JEDEC SSTL_18 logic switching range provides the reduced signaling and allows use of existing PHY designs for easier NV-DDR2 enablement. Improving NAND output drive strength tolerances to improve impedance matching with connected traces is an important consideration for signal integrity

technology in context

at increased transfer rates. To address this, the ONFI 3.0 NV-DDR2 interface requires tighter tolerances across process, voltage and temperature than the previous specification. Selectable drive strength settings of 18 ohms, 25 ohms, 35 ohms and 50 ohms are available on the NAND device. Warm-up cycles during data input or data output provide a configurable number of dummy cycles with no incremental data transfer. Signal integrity of the system is improved by reducing the effects of intersymbol interference (ISI).

Bus 2

NAND Package 2 Bus 1



On-Die Termination Techniques

Termination improves noise margins, reduces signal reflections, affects slew rates, and improves the interface signal integrity overall. Figure 4 illustrates the signal integrity improvements with termination enabled. It can easily be observed that the aperture of the data window and the slew rate improve drastically—making it a picture that is worth a thousand words. When on-die termination (ODT) is enabled, the device or host can dynamically select when to switch on the termination circuitry to avoid unwanted power consumption. The termination circuitry on the die consists of a pull-up resistive element and a pull-down resistive element where RTTPU = RTTPD = 2 x RTT. RTT is the equivalent termination value selected for the device. For each individual die, the ONFI 3.0 specification can provide RTT values of 30 ohms (optional), 50 ohms, 75 ohms, 100 ohms and 150 ohms. While termination improves the signal integrity of the system, it comes at the possible cost of additional power consumption. For example, if a termination scheme requires RTT = 50 ohm, a single I/O could have 9 mA or more current consumption. For a single data channel on an SSD that may consist of 9 to 11 signals with ODT enabled, this could consume 160 to 180 mW. Because of these costs, it’s important that system designers use the minimum amount of termination to achieve the desired I/O performance. ONFI 3.0 provides flexibility to make intelligent termination tradeoffs dynamically and attain the best desired performance at the minimal amount of power consumption.

Bus 2

NAND Package 1 Bus 1

Figure 3 Single-channel SSD topology for signal integrity study: The SSD tree topology used to evaluate 400 MT/s NAND interface speeds includes a host controller connected to two NAND packages with four NAND Flash devices per package, for a total load of eight NAND devices or dies (LUNs) on the channel. SSD form factors determine the distance from host to NAND devices.

Data Interface Feature SDR







200 MT/s

400 MT/s

CE_n Pin reduction support




Volume addressing support




On-die termination support




Differential signaling



Yes, optional for DQS and/or RE_n

3.3V or 1.8V

3.3V or 1.8V


External VPP suport




External VREFQ support





Source Synchronous


Protocol Maximum speed

VCCQ support

Previous name in older ONFI specifications

TABLE 1 Interfaces and features supported by ONFI 3.0: The newly developed NV-DDR2 interface is backward compatible with the previous SDR and NV-DDR interfaces.



technology in context

Chip in termination mode ODT IPU To other circuitry such as RCV...








Figure 4 Benefits of Termination: Interface signal integrity improves greatly when termination is provided on the die. Shown above are data traces and corresponding data eyes without ODT enabled (left) and with ODT enabled (right).

Applications and workload determine if the power required to enable termination should be of concern to the system designer. Achieving performance for consumer applications and client-class SSDs does not typically require high NAND bus utilization, so the overall energy per byte in comparing termination with no termination is small. Higher performance is required for enterprise-class SSDs and, consequently, NAND bus utilization is much greater. For these applications, system designers must consider the tradeoffs of performance versus energy consumption because implementing termination can potentially consume 10% to 20% of the total energy. To address the issue of possible additional energy consumption, the ONFI 3.0 NV-DDR2 interface introduces the matrix termination method, which provides the system designer with a diverse selection of termination schemes. This enables



optimal performance at the lowest system power cost. At initialization, the host controller assigns a unique volume address to each individual target in a system. A target can consist of several individual die or logical units (LUNs) contained in the same package. The host then assigns a termination matrix for each individual LUN in the system. Depending on the values defined in the matrix, the LUN enables termination based on the selected volumeâ&#x20AC;&#x2122;s operation. Target termination occurs when a LUN is configured to terminate for the volume to which it belongs. Non-target termination occurs when a LUN is configured to terminate for any other volume. Matrix termination provides the ability for target or non-target termination and allows configuration of possible different RTT values for each LUN. In addition, a LUN can terminate for writes to or reads from the NAND device. This pro-

vides many permutations of termination schemes and flexibility to design the optimal power versus performance solution. For examples of enabling an ODT matrix in the ONFI specification, refer to www. Implementing ODT on the NAND device requires termination circuitry that can increase NAND die capacitance. Unfortunately, the additional bus loading increases the need for termination. The ONFI 3.0 NV-DDR2 interface specification maintains the same input pin capacitance values as the previous specification while adding the ODT functionality. This is challenging for NAND vendors, but itâ&#x20AC;&#x2122;s also a requirement to achieve 400 MT/s. To reduce the die capacitance cost of adding ODT, NAND designers can choose to use existing output driver circuitry of pull-up and pull-down transistors to provide the termination. The downside of this technique is that the transistors are

technology in context

NC ENi_0 Volume A CEO_n


Data Channel

ENi_1 Volume B ENo_1 ENi_2 Volume C ENo_2

lowing the second package to accept volume assignment. This sequence will continue until all packages that share the same CE_n pin have unique volume addresses. At that point, the host controller has the ability to address packages, whereas with prior architectures, a separate CE_n was required (Figure 5). The ONFI 3.0 NV-DDR2 interface provides the features required to achieve 400 MT/s on the NAND interface. While

Toggle Mode 2.0 can serve as a compatible alternative, the ONFI NV-DDR2 interface offers additional features that add flexibility and cost reduction. Work is ongoing in an ONFI-JEDEC Joint Task Group to achieve a common 400 MT/s interface. Micron Technology Boise, ID. (208) 368-4000. [].

ENi_3 Volume D ENo_3 NC

Figure 5 Implementing CE_n reduction: A single CE_n signal is shared across several NAND packages. The ENi and ENo signals are connected in daisy chain, allowing only one package at a time to be appointed a unique volume address at initialization.

in saturation when providing termination at the AC signal switching voltages and consume more power than a more linear resistive terminator.

Reducing Pin Count

Lowering controller pin counts and reducing layout space on the PCB reduces cost and enables smaller form factors. Adding complementary signals for differential signaling to enable 400 MT/s is not desirable for overall pin reduction. To offset the additional pins, the ONFI 3.0 specification added a chip enable (CE_n) pin reduction scheme. Several CE_n pins can be reduced to a single shared CE_n pin. Enabling CE_n reduction requires the volume address appointment at initialization, which was discussed earlier with regard to matrix termination. Two new NAND device-only pins are added to each NAND package. One pin is an input (En_In) and the other an output only (En_Out). These pins are connected to configure the NAND packages in a daisy chain. At initialization, only the first package in the daisy chain will accept a volume address assignment. After the first package has an assigned volume address, the En_Out pin will be pulled HIGH, alUntitled-13 1


10/6/11 12:22:04 PM RTC MAGAZINE OCTOBER 2011


connected Network Processing

Getting What You Pay For: Optimizing PCIe Accelerator Card Designs PCIe accelerator cards can improve system performance significantly. But, are you getting the most out of your investment? Careful design and implementation are necessary to guarantee that the accelerator produces the maximum benefit possible. by Matthew Dharm, JumpGen Systems


ccording to an old story that periodically makes its way around the industry, a system consisting of a rack of 1U servers was being used in a small room to process data. As the processing requirements grew, more servers were added but the total performance of the system did not improve. What the designers didn’t account for was that as the number of servers increased, the temperature of the room increased. Each server then went into “thermal throttle back,” reducing power consumption to compensate for the higher temperatures. Thus, while there were more servers, each unit was running slower, and the total processing power of the room was (effectively) a constant. Most people take the moral of the story as “not every problem can be solved with more units.” But, perhaps the moral should be “make certain you get all the performance you are paying for.” One common way to expand system capabilities is the addition of one or more “accelerator” cards. Such cards usually contain multiple network interfaces, some number of general-purpose CPU cores, and some number of hard-accelerator cores for specific tasks such as pattern matching, cryptography, compression, or even stor-



age-related mathematical operations. Often, a system-on-chip (SoC) Network Processor (NPU) or other similar part contains much of this capability. The host CPU and the accelerator card are connected (generally) via a multi-lane PCIe link (Figure 1). While accelerator cards can offer significant increases in system performance, the task of the software designer now includes the added responsibility of making certain that all subsystem components are being utilized to their maximum capability. Also, software must maximize throughput and minimize latency in the data path between the general-purpose CPU and accelerator card. Let’s take a look at some of the key design considerations of this sort of system. The most obvious area of focus for developers interested in optimizing system performance is, perhaps, transporting data between an accelerator and host processor. Regardless of the type of accelerator in use, at some point data must flow from the host to the accelerator, or vice versa. Classically, there are three particular areas that are of critical importance to moving data across a PCIe bus: the use of Direct Memory Access (DMA) transfers rather than Programmed I/O (PIO), the use of writes instead of reads,

and the efficient use of interrupt requests (IRQs). As with many things in the software world, there are many ways to accomplish this, and most of them are poor choices.


Many designers view the use of DMA as an opportunity to reduce the number of processing cycles devoted to moving data from one location to another. While that is one benefit, when dealing with multiple processing complexes (such as in a system with a host processor and an accelerator card), the real benefit is in maximizing the utilization of the interconnecting PCIe bus. DMA involves the use of a dedicated “engine” specifically designed to copy data from one location to another. A processor sends commands to the engine, and the DMA engine often has a variety of transfer modes suitable for packets, multi-dimensional arrays, storage blocks, or other common data types. Some even support descriptor-based operation, allowing multiple jobs to be queued up and processed automatically. What is, perhaps, less obvious about DMA engines is that their base unit of operation is usually quite large. For example, a processor may be able to operate on 64bit values (8 bytes) in a single bus transac-

technology connected

tion, while a DMA engine may easily be able to operate on 256-bit values (32 bytes) or more in a single bus access. Of course, DMA engines commonly operate on much larger data units. But, since the base access is large, it takes fewer bus transactions to complete a transfer. This reduces transaction overhead and increases throughput. The difference between DMA and PIO, then, is transaction overhead on the PCIe bus. When using PIO to transfer data, each 8-byte chunk of data gets hit with the overhead of initiating and ending a transaction. When using DMA, that overhead penalty is at least 4 times less, possibly even 8 or 16 (or more) times less, than when using PIO.

PCIe Writes, Not Reads

When transferring data between two entities, many designers will arbitrarily choose to read the data from one side rather than write the data from the other. To many designers, the choice is arbitrary and one of convenience. However, this choice has serious performance implications. The issue at hand is fundamental to the operation of PCI-like buses, including PCIe. When writing data on such a bus, all intermediate bridge devices between the initiator and target are allowed to buffer the data being written. Since the bridges are buffering data, multiple writes can be happening through any given bridge simultaneously. Several rules apply to this buffering, including mandatory flushing of buffers under certain conditions to give the appearance of coherency. However, reads performed on such buses are entirely different. In the case of a read, all intermediate bridge devices between an initiator and target must interlock simultaneously, providing a clear and continuous path for the two entities to exchange data until one decides to stop (or the expiration of the latency timer). The overhead to set up the read interlock down the entire chain is significant, and no other reads through the intermediate bridges can happen during this time.

Figure 1 Example of a PCIe accelerator card, the JumpGen R7E-100 uses an 8-core Netlogic processor and can provide up to 10 Gbit/s of bulk encryption.

It is worth mentioning that many system bugs are caused by developers not properly understanding the rules for buffering PCI writes, or not properly applying these rules to their system design. This often leads developers to switch to the lowerperformance “read” configurations. Familiarity with these rules, known as PCI Write Posting Rules, is recommended for anyone implementing a PCIe-based system.

IRQ Management

While most people are familiar with interrupts signaled from an accelerator card to a host CPU, it is also common for a host CPU to signal an interrupt to an accelerator card. These interrupts can be used to indicate any one of a number of meanings, but most commonly they signal that data is either ready for processing, or processing on a block of data has completed. Interrupts can be implemented any number of ways, from physical interrupt request lines, to PCIe in-band interrupt messages, to message signaled interrupts or to mailbox interrupts. Receiving an interrupt, however, is generally the same regardless of how or where it is generated. Also, receiving an interrupt is a costly process in terms of computational resources. Receiving and processing an interrupt generally requires a processor to switch contexts, handle the interrupt (at least minimally, often defer-

ring most of the work until a later time), and then restore context to what it was before the interrupt happened. These operations involve a large amount of overhead and therefore high rates of interrupts can cripple a system. This phenomenon is the reason many systems have difficulty processing even a low-bandwidth data stream that is composed of extremely short packets (voice and video data have these characteristics); each packet causes an interrupt, and the overhead of the interrupts overwhelms the processing capacity of the system, even at a relatively low total bandwidth. There are many ways to mitigate this issue. One such way is “interrupt coalescing,” where multiple interrupts that happen close together in time are issued as a single interrupt (this is usually done with some sort of hold-off or delay logic). Another technique to reduce interrupt frequency is to reduce how interrupts are used, changing, for example, from an interrupt for every packet to an interrupt for every 1000 packets or for every flow setup/teardown. Regardless of the method used to manage interrupts, managing the amount of processing power consumed by interrupts can be an important part of system performance. It is important to note, however, that reducing the total number of interrupts is not the only concern. The PCI Write Posting rules also mention that PCI bridge write RTC MAGAZINE OCTOBER 2011


technology connected

buffers must be flushed when an interrupt is passed through the bridge. Thus, if an accelerator transfers data to the host, an interrupt can be used to flush buffers and guarantee that the host sees all the data.

Dividing Up the Workload

While it is important for system designers to be mindful of how data is moved between a host processor and an accelerator card, is it also important to consider where

and how the data is manipulated. Specifically, it may be a performance gain to preor post-process data on an accelerator card, even if that accelerator card has a different primary function. Also, when transferring

Network Processor General Purpose Processor Cores

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Figure 2 A typical accelerator architecture on a PCIe card. Note how data can be processed by multiple blocks on the accelerator before/after being sent to/from the host.

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data between a host processor and accelerator card, choosing a sensible format for the processor architectures involved can significantly improve performance. Many designers using an accelerator-based architecture initially target the accelerator for very specific parts of the processing workload. For example, many accelerators have dedicated hardware to support compression or certain types of cryptography (Figure 2). These dedicated acceleration blocks are faster than either the host CPU or the processor on the accelerator card. While this does lead to improved system performance, the processor on the accelerator is often extremely underutilized, leaving a large opportunity to further improve performance. When allocating what workload will be done on the host or on the accelerator, the total capabilities of the accelerator, including any general-purpose processing capabilities, should be considered. Moving a task as simple as a packet checksum calculation to an accelerator that is already handling that packet can free up valuable host processor resources and provide a significant performance boost.

mation from the packet, and then transfer an additional data block to the host CPU, which provides a summary of that information in an easy to access format. Accelerator cards can offer significant performance gains in a variety of tasks on many platforms. The availability of such accelerator cards in multiple standardsbased form factors makes them an attractive option to boost system performance, especially in systems where the increase

in performance is viewed as a valuedadded addition or option to the system. However, accelerators are not a â&#x20AC;&#x153;silver bulletâ&#x20AC;? that can be implemented without regard for the overall system design or the interface to the host CPU. JumpGen Systems Carlsbad, CA. (760) 931-7800. [].

Formatting Data between Subsystems

While efficiently moving data between subsystems is important, moving that data in the best possible format is equally important. Different CPUs have different strong and weak aspects of their architecture, and using the accelerator to change the format of the data to be more suitable for host CPU processing can yield performance improvements. For example, many CPUs are more efficient when data is aligned on a 64-bit boundary, but Ethernet packets have many fields that are not aligned on any reasonable boundaries. Misaligned memory accesses can be a significant source of performance problems and are almost invisible to most debugging and profiling tools. However, if an accelerator card segmented the packet into multiple buffers such that fields of interest were aligned for the convenience of the host CPU, then the host CPU could process the data more efficiently at the relatively minor cost of a few bytes of memory. Alternatively, an accelerator card could extract the desired inforUntitled-7 1


7/6/11 6:12:18 PM RTC MAGAZINE OCTOBER 2011

technology in


Technologies for Energy Intelligence

The Smart Grid Built on Smart Objects Will Challenge Developers The notion of a “Smart Grid” to imbue generation, transmission and consumption with intelligence presents daunting challenges of grand scope. The Smart Grid will consist of many elements and they all need to be smart and connected. Java, Linux and Android will contribute greatly to the effort. by Bill Weinberg, Linux Pundit and The Olliance Group


or the last 50 years, developed countries have enjoyed “all you can eat” electrical energy. But no more. Today, multiple factors are leading to climbing energy costs, power quality degradation, brownouts and blackouts. Unpredictable energy supply and demand complicates the lives of individuals and operations of businesses, from manufacturing to services industries. To address this next energy crisis, governments, power companies and entrepreneurs must address myriad factors.

Among these are the declining fossil fuel supplies, increasing pollution and looming climate change from use of still plentiful non-renewable energy sources, especially coal, combined with the current system of geriatric energy distribution networks— the “dumb” grid. In the face of this is the increasing demand for energy from regional growth and from anticipated demand for electric vehicle charging. There are regulatory and cost barriers to increasing generating ca-

pacity, especially for nuclear power along with “not in my back yard” (NIMBY) objections to construction of new nuclear, solar and wind projects. At present there is only limited, emerging ability to monitor and respond to changing energy demand in real time, and always in the background are security threats to the distribution grid and to consumer privacy. Many of these issues come to a head at the “last mile”— the last 10 yards, actually—of the emerging Smart Grid.

Demand Response







Smart Meter




Figure 1 The Smart Grid, end-to-end involves intelligent devices and different levels of networking throughout.



tech in systems

Energy Awareness

Embedded system developers need to start integrating energy efficiency and management into the hardware and software of their designs—home appliances, entertainment systems, office equipment and environmental controls. Energy monitoring and control are embodied in systems and software that measure actual energy usage by communicating with the universe of devices in the home and workplace. To enable efficient operation, communication, monitoring and control, developers need to rethink embedded systems beyond their stand-alone roles. Rethinking entails designing and building application platforms, systems and software that respond to changing local conditions and can be upgraded to respond to changing energy economics. The last mile (or last ten yards) of the Smart Grid includes nodes that use electricity, monitor consumption, and reside in or near homes, offices and other premises. Among these are data aggregation devices—smart meter readers/concentrators/ routers and microgrid controllers, most often located atop power poles as well as smart meters installed on premises. It also involves premises-based Home Energy Gateways (HEGs) and In-Home Displays (IHDs) as well as passive (monitored) and smart (remote policy-driven) appliances and other energy-aware equipment. Energy goes in and data comes out (and sometimes in, too), ideally in a loop to support Demand Response. Demand Response is the ability of the Smart Grid to react to widespread high demand by automatically adjusting premises devices such as thermostats across many locations by small amounts to keep overall consumption under control (Figure 1).

Premises Devices

Device types sort themselves out into four basic categories: device concentrators, smart meters, IHD/HEGs and smart appliances. Data concentrators are head-


Local Display


Mobile Apps



Java Android, iPhone


Swing/LWUIT Android UI GTK+, QT, etc.


Java Applications

Middleware & Enablers

Java or Dalvik Run-time

Native Applications

Linux or RTOS


C/C+ Runtime TCP/IP

System S/W

Mobile Gateway

CGI, Webapp

HAN Protocols

Device Drivers LCD,Touchscreen, etc.

LAN Drivers WiFi, Ethernet

Scripts and “Glue” HTTP

OSGi Storage/FS HAN Drivers Zigbee, Z-Ware, etc.

Figure 2 Key elements of a Smart Energy software stack.

less (pole-top) systems and primarily act as routers and access points that let smart meters “phone home” periodically with usage data, and support commands for provisioning and service disconnect. Building these systems on embedded Java, Linux or Android, augmented with storage/db capabilities, gives them options for local caching and analysis of client smart meter data, especially for maintenance and troubleshooting purposes. A scalable platform is required to extend the lifetime of these systems, allowing for provisioning and management of a large number of smart meter client devices that can grow over time. These systems need to communicate with smart meters over a number of channels, and due to their strategic role in provisioning and relaying customer energy usage data, also benefit from robust security. Utilities and premises owners also deploy these types of systems as controllers for autonomous microgrids that generate local power and act as backups against grid-wide outages.

Smart meters today represent a large and growing revenue opportunity for energy sector OEMs. Currently, smart meter rollout parameters constrain the functionality of these devices to monitoring and reporting energy usage. In the future, they present interesting opportunities for accelerating demand response and participating in home area network (HAN) monitoring and control activities (across the premises demarcation). As such, they need protocols and intelligence for upstream and downstream communications—to poll-top systems, to HEG/IHDs, and to selected high-load HAN nodes, especially HVAC, pool pumps and hybrid/ electric car chargers. The evolving role of the smart meter also benefits from Java’s programmable platform functionality: smart meters that are relatively “dumb” at rollout can easily be re-provisioned for more comprehensive capabilities as legal and regulatory environments change. In-home displays and home energy gateways hold the greatest opportunities RTC MAGAZINE OCTOBER 2011


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for Java deployment in the Smart Grid. The IHD/HEG needs to manage and control a multi-faceted and always changing environment. Today, penetration of energy-aware appliances is quite low. In the next several years, mandates for energy-efficient white goods in the U.S. and abroad will boost the presence of smart appliances in the market and on premises. Over the next decade, homeowners will upgrade aging appliances and add new ones to their homes. The broader vision of IHD and HEGtype devices places them at the center of the energy-efficient home. Java is the most appropriate platform to support this central, user-interactive role. It is also an excellent application platform to accommodate appliance-specific applications and widgets and third-party apps that extend the pre-load functionality of IHD and HEG hardware with aftermarket postload plug-ins. IHD/HEG systems will leverage the most functionality from the underlying software stacks and will need to support multiple communications and HAN protocols. They will offer users interfaces locally and via the Cloud, support downloaded and over-the-air software upgrades, and will do so with topnotch data and operational security. Many appliances and devices in the prototypical HAN exhibit constrained functionality and BOM/market price points—light switches, power strips, electric heaters, smoke detectors and myriad other devices with simple operational states, limited or no user interface, and liberal or non-existent latency/response requirements. These devices are probably best served by microcontrollers with no real software platforms or low-cost multifunctional units running minimalist RTOS, µCLinux or Java Card. Examples include Internet-connected HVAC systems and other environmental controls as well as smart refrigerator/ freezer units, with capabilities to track contents/expiration and deliver information such as recipes and nutritional data through embedded displays. These will also include high-wattage Internet-connected audio-visual equipment such as flat screen TVs, DVRs, STBs, etc., which are already fairly smart. Higher-end “white goods” and other household systems

greatly benefit from inclusion of greater intelligence conferred by full-blown embedded Linux, Java or Android. The home area network that will tie together these premises devices and link them to the external network is actually the sum of several networks, encompassing existing LANs (Ethernet and Wi-Fi) and networks specifically designed for premises automation and monitoring: • WiFi—standard 802.11b/g/n wireless networking, connecting the HEG with local computers and tablets, and sometimes acting as a data backhaul • Ethernet—standard wire line connection to LAN and Internet backhaul • Bluetooth—peripherals and mobile devices, both as interfaces to HEG and for energy management and control • Zigbee—IEEE 802.15.4-2003 wireless mesh for industrial and home networking with profiles for energy monitoring and control • Z -Wave—a proprietary wireless networking protocol for home automation • HomePlug—a power-line communications (PLC) protocol for home/ SOHO • X10—legacy power line and wireless home automation network

The Software Stack

The premises devices described above require a relatively generic software stack, with multiple options for OS, middleware and display paradigm (Figure 2). Smart energy is a domain closely associated with Java—a large swath of projects, commercial software and hardware and applicable standards are implemented in or for Java, with Oracle investing strongly in all parts of the emerging Smart Grid. Using embedded Java enables rich base functionality and modest impact on bill of materials. At a minimum, smart appliances need Java ME, HAN protocol stacks, and application-specific device drivers to run relays, sense temperature, etc. Internet-enabled appliances would also require TCP/IP, and higher-end devices code to support a device user interface. Using embedded Linux and Java together constitutes an optimal Smart Grid combination. The broad horizontal support for devices, protocols, middleware and

tech in systems

other development languages gives developers the widest possible design palette. In addition, Android for Smart Grid devices offers most or all of the virtues of Java—well-understood programming model, rich toolbox of existing Smart Grid resources, and synergy with Java applications in the “back office” (billing, monitoring, etc.). Android has the additional benefit of presenting developers and users with an application platform and a vibrant application marketplace. HAN devices built on Android could offer users numerous options for add-on software and stimulate a Smart Grid software aftermarket. While there are devices that benefit from smaller footprint and deterministic responsiveness, and many target appliances and other devices already deploy on RTOSs, few Smart Grid projects moving forward are selecting RTOS platforms. Even when combined with Java, RTOSs lack the broad device, protocol and middleware support offered by Linux (underlying Android or Java). It is certainly possible to build HEGs and other systems on an RTOS, but in a market where timeto-market and field upgradability are key requirements, RTOSs are often too minimalist to make the cut. Microsoft, like Oracle with Java, offers a gamut of resources for Smart Grid. Building a premises device with an embedded version of Windows offers synergy with the dominant enterprise application platform and avails developers of the rich toolkits offered to support Microsoft platforms. However, most existing Smart Grid project code and products are not optimized to run on versions of Windows, necessitating additional porting and integration work. Building on modern, standards-based system platforms confers multiple options for a user interface paradigm on Smart Grid devices. An “In-Home Display” (IHD), by definition, includes a display, from small, simple numerical LCDs output to fullfeatured color LCD and touchscreen input/ output. With Java, Swing and the Light Weight UI Toolkit (LWUIT) simplify prototyping and building user-friendly interfaces for Java applications. With Linux, developers have myriad UI framework options, from familiar GTK+ and Qt to e17 to FancyPants and other proprietary graphics and multimedia frameworks. Android also

offers its own rich native UI framework, the tablet version of which appears to be well suited to premises form factors. And Microsoft and top-tier RTOS vendors have invested in supporting platform-native and third-party graphics toolkits. To reduce BOM cost for HEG devices, and to provide UIs for other Smart Grid nodes (appliances, smart meters, pole-top systems, etc.), a headless smart energy device can easily present a webbased user interface for display on PCs, notebooks, tablets and other client devices over a network. Java and Linux both provide a rich set of resources for building embedded web servers (e.g., httpserver), and Java can also form the basis of the client-side UI with Applets. Increasingly ubiquitous smartphones and the need to control Smart Grid devices remotely predicate building mobile applications for secondary (or primary) smart energy control and monitoring. A mobile app can just encapsulate a browser UI in an application wrapper or can have a “life of its own,” with capabilities unique to mobile host platforms (input methods, location info, etc.). Note that unless an app is designed strictly for LAN-based monitoring and control (usually via Wi-Fi), the mobile app architecture will likely include access to the smart energy device through some kind of gateway, especially to avoid installation and configuration issues. Devices deployed across the Smart Grid must be manageable without handson intervention. Many nodes are physically remote, inside power plants, on pylons, or embedded inside of other systems, appliances and construction. Also, many or most Smart Energy device types are headless, without displays or user input. Smart energy requires smarter devices—intelligent control systems easily provisioned, maintained and upgraded with both inherent functionality and aftermarket applications. There is no one right path (let alone an entirely straight one) to building Smart Grid premises devices, but there is no dearth of options and available resources, either.


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technology in


Technologies for Energy Intelligence

The Smart Grid Tipping Point for Electric Vehicles: Closer than You Think With gas prices once again creeping toward $4/gallon in the United States, the industry is overcoming obstacles that have impeded widespread adoption of plug-in electric vehicles. This technology will become an integral part of the Smart Grid. by Jim Zyren, Qualcomm Atheros






Dollars per gallon

ill your next car be a plug-in electric vehicle (PEV)? For many American consumers, this is becoming a distinct possibility. At some point, the world will emerge from the global recession. When this occurs, many experts predict that gasoline prices will eclipse the $5/gallon threshold, a price that will catalyze tremendous interest in PEVs. With price levels driven down by the possibility of a double-dip recession and a slow summer driving season, oil consumption actually hit an all-time high in, reaching 87.4 million barrels per day in 2010, according to the Worldwatch Institute. When the current recession ends (and it will), those aforementioned $5 per gallon gasoline prices in the U.S. will create a lot of electric vehicle enthusiasts (Figure 1). Of course, many early adopters purchasing PEVs today, such as the Nissan Leaf, Tesla Roadster or Chevy Volt, are doing so for philosophical rather than economic reasons. These consumers are mainly interested in reducing their carbon footprint or reducing our national dependence on imported oil. However, even with todayâ&#x20AC;&#x2122;s lower than expected gas prices, PEV owners are already sav-



$2.00 $1.50 3/2/2009

Figure 1






Source: Energy Information Administration

The steady rise of gasoline prices, despite temporary fluctuations, is expected to continue. The point of five dollars per gallon is considered to be both an economic and psychological tipping point.

ing money through government incentives and by inexpensively charging their vehicles at home rather than spending money at the pump. Depending on the model of car being replaced by a PEV, consumers can save anywhere from $36/fill-up for a vehicle

currently averaging 30 MPG to $45/fillup for a model averaging 15 MPG. (These numbers were calculated for California.) The savings from replacing that gas-guzzling SUV adds up quickly. As utilities modernize their infrastructures and with the build-out of the Smart

tech in systems

Preliminary 15. ? B A POWER



10.8 5.6


Tax Incentives Help PEVs Compete

Consumers tend to focus on up-front costs and often lose sight of longer-term recurring benefits when deciding on new vehicle purchases. Ask any behavioral economist, and they’ll tell you that consumers aren’t good at factoring in long-term consequences. Instead, the sticker price and variables such as horsepower, style and interior legroom get more attention when consumers step into showrooms. Today, PEVs need incentives—typically in the form of tax credits from state and/or federal government—to be competitive at the time of purchase. In the U.S., California incentivized the first wave of early adopters. California consumers could defray the cost of a new PEV by adding a $5,000 state tax credit to a $7,500 tax credit from Uncle Sam. $12,500 in tax credits goes a long way toward making PEV purchase prices more competitive. Unfortunately, California no longer offers its PEV tax credit, but as electric vehicles ship in greater volume, the sticker price is expected to fall significantly. As of July 2011, Nissan sold 4,134 Nissan Leafs, while General Motors sold 2,745 Chevy Volts (which is technically a PEV, since the gas assist doesn’t kick in unless the vehicle is driven beyond its initial 35-mile EV range). Those numbers are nowhere

(33.45) TBD


Grid, time-of-day pricing programs will become available to PEV owners. Demand on the energy grid varies dramatically over the course of a day. Nationally, the average price for electricity is about 10 cents per kilowatt-hour. Time-of-day pricing will allow utilities to vary the price of electricity over the course of a day. This will create an economic incentive to shift existing demand from peak hours. It will also spur new demand (such as PEV charging) at off-peak hours (between midnight and 5:00 AM, for example). PEV owners stand to save a lot of money when they charge their vehicles during off-peak hours.








TBD 28.00 SEC. A-A

Figure 2 The SAE J1772 connector specification is expected to become standard for pluggable electric vehicles. It can handle charging from both AC and DC charging stations as well as the network signals for such things as billing and time-of-day pricing.

near the volumes needed to compete with gas vehicles, but manufacturers are aggressively ramping up production. Nissan is investing about $1.7 billion in an electric-car battery factory and other upgrades to its Smyrna, Tenn. complex. The company intends to start building batteries and PEVs in Smyrna by the end of 2012. Meanwhile, other automakers, including GM, Mitsubishi, Ford, Toyota and Honda, have either announced new PEV models or plans to scale up PEV manufacturing.

Standards Pave the Way toward Even Broader Adoption

For PEV adoption to spread quickly, standardization is a must. It is one thing

if you need an adapter to charge your cell phone overseas, it is quite another if you can’t recharge your vehicle after you’ve crossed state lines. Fortunately, automotive standards bodies such as the Society of Automotive Engineers (SAE) in North America, ISO/IEC in Europe and the Japanese Society of Automotive Engineers, are making progress on developing uniform global standards for connectors and signaling over charging cables. The recently adopted SAE J1772 standard specifies a five-pin, conductive-coupling connector for AC charging (Figure 2). Having a standardized connector is essential with PEVs, since roaming isn’t possible without them. SAE J1772-compliant connecRTC MAGAZINE OCTOBER 2011


Tech In Systems

Smart Grid/HAN Customer Premises

Smart Grid/WAN Utility Backhaul

Light Switches EV Charging Station

Authentication Server WAN Controlled Port




Security Cameras

HAN Clients

Utility Network


Home Control Devices (not on HAN)

Figure 3 The home area network (HAN) will partly act as an extension of the wide area network (WAN) portion of the Smart Grid. In addition to smart metering, it will allow intelligent interaction with major appliances as well as electric vehicles.

tors support both AC and DC charging, meaning that plugs that work with slowercharging home AC stations will still maintain compatibility with fast-charging public DC stations. The J1772 connector also includes a safety interlock that immobilizes the vehicle while plugged in. Roaming in PEVs is far different than roaming in a traditional vehicle. Finding a charging station is just the first obstacle. Once found, how will you be billed for power usage? How will providers connect your vehicle to an existing home electric utility account? How will they handle roaming as you drive beyond your home utility’s coverage area? If those questions sound like we’re talking about mobile phone coverage rather than vehicle charging issues, it may be because many of the roaming obstacles facing PEV manufacturers mirror those that telecom carriers struggled with twenty years ago. In the industry parlance, charging pedestals are referred to as Electric Vehicle Supply Equipment, or EVSE. Communications between PEVs and EVSEs are being worked out in parallel by the SAE J2931 committee in North America, ISO-IEC 15-118 in Europe and JSAE in Japan. It’s worth repeating that all of these groups have agreed to work together to create a single global standard for PEV/EVSE digital communications over the J1772 charging interface.



As a result of such efforts, the power delivery infrastructure that enables vehicles to charge at home, at work and in public locations such as restaurants and entertainment complexes is starting to be built out. By 2017, Pike Research, a market-research firm that studies clean-tech trends, forecasts that more than 1.5 million locations to charge vehicles will be available in the United States, with a total of 7.7 million locations worldwide. With standards and infrastructure in place, the appeal of PEVs will spread beyond the consumer market to the business market. Another recent report from Pike Research predicts that between 2010 and 2015 more than 1.3 million PEVs will be purchased for use in fleet operations, with nearly 400,000 vehicles being sold annually by the end of the forecast period. Helped along by fleet purchases, Pike predicts that worldwide PEV sales will reach 5.2 million by 2017, up from 114,000 vehicles in 2011.

The $5/Gallon Tipping Point

As noted earlier, consumers often ignore long-term benefits (the price of gas, insurance rates, resale value, etc.) in favor of short-term, tangible factors, such as initial sticker price, horsepower and vehicle styling. When gas exceeds $5/ gallon, which could happen sooner rather than later, the price of filling up the gas

tank shifts from a long-term to a shortterm consideration—because it’s really gonna hurt. At $5/gallon, the cost of a typical 40mile roundtrip commute in a car averaging 20 MPG hits $50 per work week, each and every week. That’s more than $200 per month—and that’s without factoring in various side trips, such as dropping the kids off at soccer practice or driving to the grocery store. At $5/gallon, each and every fill-up for a typical 14-gallon tank will cost at least $70. Other economic factors will also tip the scales in the favor of PEVs. Utilities scale their generating capacity to meet peak demand, which occurs at about 3 p.m. on a typical workday. During postpeak hours, much capacity sits idle. Expect utilities to roll out preferred pricing plans for off-peak PEV charging. The economics behind producing a kilowatt-hour (kW-hr) of electricity on the North American grid have a major influence on the overall case for electric vehicles. Power plants represent huge investments of capital for utilities. They are extremely efficient when run at full capacity. However, when demand is minimal between the hours of midnight and 5 a.m., large scale natural gas or coal fired plants are grossly underutilized. The average price for a KW-hr in the United States is about 10 cents. However, at periods

tech in systems

of minimal demand, utilities could sell power profitably for as little as 3 cents per KW-hr. One of the main features of the emerging Smart Grid will be “time-ofday” pricing programs. Utilities will be able to charge different rates based on the time of day. The idea is to incentivize consumers to shift existing demand from 3 p.m. to 3 a.m. wherever possible to realize the lowest possible energy cost. Utilities are also interested in creating new demand that can exploit unused capacity at off-peak periods. Consumers with EVSEs installed at home will be able to qualify for timeof-day pricing incentives. EVSEs will be able to recognize and respond to pricing signals sent by utilities and automatically commence charging when the price is right. By charging between midnight and 5 a.m. for example, PEV owners will be able to recharge those high capacity batteries for as little as 3 cents per KW-hr. It’s been estimated that charging a PEV at 3 cents/KW-hr is roughly equivalent to buying unleaded gasoline at 75 cents per gallon. When compared to filling up for $4 or $5 per gallon, charging a PEV at 3 a.m. for a few pennies per KW-hr starts to look pretty attractive (Figure 3). Most utilities are also under pressure to expand use of renewable energy. In California, former governor Arnold Schwarzenegger launched an ambitious plan requiring that utilities generate 20 percent of their electricity from renewable energy sources. Current governor Jerry Brown has increased that target to 33 percent. Renewable energy incentives and mandates will apply further downward pressure on the cost of a mile driven in PEVs. As renewable energy replaces energy sources such as oil, nuclear and coal, the problem of matching output and demand becomes an even larger concern. With conventional sources of energy, output is completely controlled by the utility. This is obviously not the case with power generated by wind-turbines. Peak generation from windmills and peak demand are completely uncorrelated. One of the main drawbacks of renewable energy from wind-turbines or solar arrays is that they

are use-it-or-lose-it resources. You can’t get back yesterday’s wind or sun. This means that either expensive electricity storage must be added to the grid, or utilities need to figure out ways to align peak output with peak demand. Once again, innovative approaches to pricing can help by aligning demand with capacity. Time-of-day pricing is straightforward. You’re charged more during peak demand, and less in off-peak hours. What’s needed to get the most out of renewable energy is an additional pricing variable: opportunistic pricing. In other words, if the Santa Ana winds create a surplus of electricity, California utilities should have a way to artificially inflate demand through things like price-drop alerts, power sharing with other states, and even free PEV charging offered as means of matching supply and demand. A case in point is Germany, a country that has aggressively built out wind farms. Wind power currently accounts for approximately 7 percent of Germany’s total electrical power (compared to 2.3 percent

in the U.S.). Germany has plans to build more wind farms and other forms of renewable energy, and has a goal of attaining a 100 percent renewable energy supply by 2050. In a country like Germany, where renewable energy has strong public support, PEV owners will almost certainly benefit from ultra-low-cost or possibly even free charging when wind-generated capacity exceeds demand. As wind farms get built out, those “free” charging times will be more and more frequent. Who wouldn’t trade a $70 fill-up with a traditional gasoline-powered vehicle for a $10 charging session, with the occasional freebie thrown in? Qualcomm Atheros San Jose, CA. (408) 773-5200. []. Pike Research Boulder, CO. (303) 997-7609. [].

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7/25/11 10:48:03 AM RTC MAGAZINE OCTOBER 2011

technology deployed Designing Safety-Critical Systems

Reducing the Cost of Developing Safe, Secure and Resilient Industrial Control Systems

Requirements and Cost Factors of Industrial Control Systems

Todayâ&#x20AC;&#x2122;s industrial control market is changing rapidly as the companies deploying these systems are demanding their suppliers provide flexible, upgradeable, IEC 61508-certified devices to mitigate risk. Of course, this may also provide them some legal protection in the event their system fails. In some locations the government may demand that industrial control systems be certified, putting further pressure on the OEMs to deliver and use certified devices. Driven by the IEC 61508 standard, the risks associated with the ICS are analyzed and safety functions are put in place to reduce the identified risks to acceptable Safety InTodayâ&#x20AC;&#x2122;s development techniques, including a separation tegrity Levels (SILs). ICSs are certified to kernel teamed with the methodologies of IEC 61508, can a particular SIL with SIL 3 being the highest level of risk reduction without hardware reduce the development cost while providing a foundation redundancy. In essence, SIL 3 is used to for developing industrial control systems that are safe, protect high-risk systems, such as critical infrastructure components. secure and resilient. The construction and certification of industrial control systems is an expensive by Jim McElroy, Green Hills Software endeavor, in terms of hardware and software acquisition and development costs, as well as certification costs. More complex he cost of developing and certifying control systems that ICSs may consist of a collection of sensors, actuators, single core are safe, secure and resilient continues to escalate due to in- and multicore processors, network devices, and potentially mulcreasing complexity, demands for increased assurance and tiple network connectivity technologies. From the development reliability, and the need for these systems to operate in ever more perspective, IEC 61508 demands a rigorous safety lifecycle, and hostile environments. To meet these demanding requirements, as such, involves more work, products and activities, lengthening developers of industrial control systems are turning to the IEC the development schedule and raising the overall development 61508 standard as well as COTS hardware and software develop- cost. The certification process alone can cost hundreds of thoument solutions to mitigate project risk and provide high assur- sands of dollars and typically months and months of schedule. ance of functional safety and reliability. Certification of industrial control systems is labor intensive and Industrial control systems (ICSs) that monitor and control consequently takes substantial time and money; multi-year develwater, oil, gas, electricity generation and distribution, chemical opment schedules are common, and budgets for system certificaprocessing, manufacturing and transportation systems are in- tion easily require multi-million-dollar investments. creasingly coming into the spotlight of media and the general Historically, ICSs have been constructed around rigid onepublic; unfortunately, not for their successes. System failures time ASIC designs. However, these systems are simply no longer with great social and environmental impact and deliberate cyber flexible enough given the ever-changing technical requirements attacks on these systems have increased their visibility and raised and demands of the market. For performance reasons, this may the awareness regarding the vital role these devices and systems have been a good decision in the past but that has changed. Future play within the critical infrastructure. Failure of supervisory con- system expansion and upgradeability require that more and more trol and data acquisition (SCADA) systems, distributed control functionality be put in software, which includes both the applisystems and other special purpose controls can have catastrophic cation software as well as safety functions developed under IEC physical effects on the population and equally dramatic effects 61508. Looking ahead, it will be the software that not only difon the economy. Therefore, their construction and maintenance ferentiates these industrial control solutions, making them more should be based on rigorous and proven methodologies such as secure and resilient, but it will also be the software that deterIEC 61508 to mitigate any potential safety risks. mines the vast majority of the cost of these systems. Application




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technology deployed

Protected Partition

Protected Partition

Protected Partition

Safety relevant application

Non safety-relevant application

Safety critical application

C Library

C++ Library

C Library

Kernel API

Kernel API

Kernel API

Kernel Space

Integrity - 61508 ASP

Safety BSP


Global Table

C Library


Peripheral Hardware

SIL 3: pre-certified Certified and integrated with System Safety Architecture and Requirements

Figure 1 An example of an industrial control system leveraging the separation kernel architecture.

software, board support packages, drivers, middleware, communications infrastructures, user interfaces, persistent storage applications and device controllers will all contribute as the primary drivers of effort, schedule and cost. Therefore, a more effective means of delivering safe and reliable software is paramount to the successful future deployment of industrial control solutions.

Developing Software under IEC 61508

IEC 61508 provides the framework to both avoid the introduction of faults into industrial control systems as well as to respond appropriately to failures when they do occur. In reality, failures and deliberate attacks on these vital systems will occur and these ICSs must be built to address this reality. While the IEC 61508 standard does not target system security requirements specifically, it does recognize that knowledge or discovery of security threats during the development cycle cannot be left unaddressed. In part 1 of IEC 61508-2010 section, the standard states, â&#x20AC;&#x153;If a hazard analysis identifies malevolent or unauthorized action, constituting a security threat as being reasonably foreseeable, then a security threats analysis should be carried out.â&#x20AC;? For developers of software within industrial control systems, IEC 61508 part 3 provides a rigorous development framework and standard to help enable the construction, deployment and maintenance of functional safety systems. This occurs when the software system can detect potential faults and then take corrective or preventative action based on that determination. However, ICSs and their functional safety systems continue to increase in complexity as they take on more functionality to address the business and safety demands in the industrial market. These sys-



tems are becoming increasingly distributed and require more communication of vital data and control information. Of course, this means that the cost of developing such systems is driven by the different communications strategies and technologies, both hardware and software redundancies, user interface designs, network topology, and level of safety and security required, to name just a few of the key factors. Fortunately for suppliers of industrial control systems, there are methods and techniques that can be employed to reduce cost, schedule and risk while addressing these requirements. Building systems from previously certified components is one such possibility. By using a certified operating system technology with potentially pre-certified software components, significant development and validation time can be saved. Furthermore, depending on the certification, these components may offer increased levels of security, reliability and safety. However, before deploying just any off-the-shelf software, suppliers need to make smart decisions regarding the authentication and technical pedigree of the offering and how that will play in the overall system of components. An example consideration for safety and security may be the decision to leverage a single processor with an operating system based on a separation kernel architecture. IEC 61508 informs software developers of techniques for achieving non-interference between software elements, i.e., independence of execution on a single processor. One way to realize execution independence among software components on a single processor is by utilizing operating system technology that provides spatial and temporal separation through the use of virtual address spaces and memory protection on the processor. Green Hills Softwareâ&#x20AC;&#x2122;s Integrity operating system is an example of such a technology, providing a separation kernel architecture built from the ground up to address safety, security and reliability in single-processor, distributed and multicore processing environments. Such an operating system should provide an industry-proven and SIL 3-certified separation kernel architecture that enables modular construction of safe software, not only simplifying initial development of certified systems, but also greatly reducing cost of re-certification along the lifecycle, which inevitably occurs when making modifications to individual components. The separation kernel is able to safely and securely partition off software components that manage different aspects of the industrial control solution into virtual address spaces while guaranteeing resource availability. This protects each individual software component from other components potentially operating under duress in other partitions. For example, in one partition, the designer may choose to place the communications stack, while another partition may handle the control of a pump or actuator, while yet another may handle the user interface, should such an interface exist (Figure 1). By using this separation kernel architecture, it is possible to build safety and resiliency into the industrial control solution. Flexibility and scalability are paramount for the success of future industrial control solutions. For example, with a wide array of protocols now in play within the industrial sector, future ICSs must be flexible and expandable without giving up safety.

Technology deployed

Now suppliers are backing various protocols and flavors of protocols such as CAN, CANopen, EtherCAT, Profibus, Profinet, etc. There is a clear need in the market to acquire pre-certfied software components that offer these protocols and simply add them into existing architectures and platforms to ensure device interoperability. Many industrial control solutions require multiple operating systems, for example, those with user interfaces running under Linux or Windows, in addition to the control applications. A separation kernel foundation can provide the basis for supporting virtualization, safely partitioning off these insecure and potentially unsafe components from the safety-critical components of the overall control solution. The separation kernel architecture enables expansion and flexibility without giving up on the safety and security requirements of the system while maintaining safety and integrity under IEC 61508. A separation kernel architecture can also simplify the overall design and lower the bill of material and development cost. With the separation kernel, developers of industrial control solutions can put more functionality into fewer processing components, potentially supporting multiple levels of safety on a single or multicore processor, consolidating and reducing the bill of material and development cost of the overall solution. In addition, with this partitioning approach, certification can be simplified as components with different certification requirements can be placed in their own partitions. As a result, now the certification process can be paired down to only those partitions that require it. Industrial control solutions that do not leverage such an architecture will be more com-

Untitled-13 1

plex, require more development and certification time and effort, and will likely be less safe due to their complexity. The advantages of using the pre-certified kernel as described so far are important, but the complete value of using a separation kernel operating system for safety systems requires more features and services from the PS vendor. Safety systems require fault detection and responses. The hardware on which the software executes may have either systematic or random failures, which may in turn prevent the software from running safely and reliably. Therefore, it is up to the system architect to decide whether detection and correction happens in the hardware, or if the software must perform periodical checks to verify the hardware is still fully functional. This is an activity that typically happens at the driver level and through functionality such as PBIT and CBIT (power on and continuous built-in test). Because of the dependency on a system-level safety architecture, building a safety BSP is not a generic activity, which can be conducted independently of the program as long as the hardware is given. The operating system vendor should be expected to deliver a turnkey safety platform comprised of a pre-certified separation kernel and safety BSP engineering services with a certification deliverable in the program using the platform. Green Hills Software Santa Barbara, CA. (805) 965-6044. [].


3/31/11 4:26:15 PM RTC MAGAZINE OCTOBER 2011



Wireless Networking




Part 2

Demystifying the 4G Phenomenon Ad Index

While the extensive use of 4G has made it into an enduring marketing term, there are still issues as to what truly constitutes 4G and Long Term Evolution (LTE) in the wireless world. In addition, thereandare a variety of Get Connected with technology companies providing solutions now different paths forward. Get Connected is a new resource for further exploration by Todd Mersch, RadiSys


into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

key consideration in any mobile to LTE or WiMAX. This phenomena is voice (i.e., the circuit switched (CS) network upgrade is cost, and by far, playing out today in the U.S. and Japa- work) and one for data (i.e., the packet the big ticket item remains spec- nese markets where Verizon and KDDI switched (PS) network). This means operators will, essentially, be extending trum, which is followed by equipment have rapidly moved to LTE. the life of their legacy CS infrastructure, If this is the case, why would any CAPEX. Second to cost, is spectrum which is expensive to enhance and operoperator not choose to move to HSPA+ availability. You cannot roll out a new It also means first? network without the appropriate specGet Connected with technology and companies providing now that operators deploying HSPA+ will able toWhether take advantage First off, do not be fooled by the trum allocation. This is where Evolved Get Connected is a new resource for further exploration into products, technologiesnot andbe companies. your goal is to research th datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get of the service innovation possibilities of Connect HSPA+ diehards who claim it is a softHigh Speed Packet Access (HSPA+) in touch with the right resource. Whichever level of service you require for whatever type of technology, a converged IP core network like in the ware only upgrade. If you are to achieve steps in. Get Connected will help you connect with the companies and products you are searching for. The advantage of HSPA+ is that it the performance gains promised, you LTE and WiMAX solutions. Finally, there is significant global is an upgrade to existing deployed 3G need to leverage the multiple antenna momentum behind a rapid move to LTE techniques of diversity and MIMO, which HSPA networks. Existing base station networks. If this momentum continues, means software and hardware upgrades at sites, spectrum and core network equipthe operator who moves to HSPA+ may be all the base station sites. ment all can be reused to deliver the the minority. The result would be reduced Second, while it does not require a increased performance of HSPA+ sereconomies of scale both on the equipment massive functional change in the core vice. Additionally, HSPA+ has a roadnetwork, it will require an upgrade. and, more importantly, the UE and subsemap through 3GPP Release 10 that has Minimally the software needs to be quently increased costs. it pushing to the performance levels of Most operators who have deployed LTE. Finally, not all operators are com- enhanced, but also the capacity will need to be grown to deal with the inalong the GSM family of standards that ing at 4G from a GSM heritage. Operators who chose the code division multiple creased speeds being provided on the Get Connected with companies and Get Connected access third generation (CDMA2000 or air interface. products featured in this section. with companies mentioned in this article. Another drawback is that the core CDMA2K) path of standards cannot verage HSPA+ and need to leap directly network remains as two silos: one for


End of Article



Get Connected with companies mentioned in this





Microcell/ Picocell

Greater Femto


Figure 1


Small Cells.

are choosing HSPA+ see this as a stepping stone to LTE. These operators will use HSPA+ to extend the life and competitiveness of their existing 3G HSPA assets, and to intersect the LTE roadmap likely at LTE-Advanced.

WiMAX 1 and WiMAX 2

The 802.16 family of standards and related technology enjoyed a distinct advantage over LTE and HSPA+â&#x20AC;&#x201D;it was available first. WiMAX standards and technology development were fueled by titans of the industry and driven to completion very quickly with the support of the WiMAX Forum. From a technical perspective, WiMAX delivers similar performance characteristics to LTEâ&#x20AC;&#x201D;spectrum flexibility and an all-IP core network to deliver converged services. WiMAX also has some early success with significant operators including Sprint / Clearwire in North America. So why has WiMAX not rapidly become the 4G standard of choice? The biggest early challenge for WiMAX was a distinct focus on time di-



vision duplex (TDD), or unpaired, spectrum. At the time of WiMAX development, this was the generally accepted form of spectrum that would be used, and therefore much of the investment in profile generation and interoperability testing focused on TDD. However, it has become clear that 4G will be deployed in both frequency division duplex (FDD) and TDD spectrum, and from an LTE perspective, around two thirds is projected to be FDD and one third on TDD. This gap allows LTE to catch up by way of standards development and network equipment availability. Additionally, WiMAX is a greenfield technology. It does not build on an established technology and a standards base like LTE does with the GSM family. There are more than 2.8 billion GSM subscribers, and operators have largely aligned around an eventual move to LTE with more than 140 operators making public announcements of their LTE intentions. This has severely impacted WiMAX momentum as there are now fears that the economies of

scale, UE innovation and roaming partners will not be on par with LTE and LTE-A. This is not to say all is lost for WiMAX. It has been extensively deployed both in major markets and is enjoying success in emerging markets for commercial services. It also is being leveraged extensively in non-telecommunications applications like health care, industrial and military scenarios. However, in the end, we see that operators are choosing the GSM standards track not really for technology reasons, but primarily due to the global alignment behind the LTE and LTE-A network technologies.


LTE, and eventually LTE-A, seems to be the clear winner in the 4G space. As mentioned above, more than 140 operators have aligned behind LTE and there are rollouts taking place in major markets including Denmark, Sweden, Norway, U.S. and Japan. Verizon in the U.S. launched nationwide service


42 Mbps R8 Multicarrier Single Carrier

21 Mbps

(same number of users per carrier) 7.8 Mbps

User data rate experienced during a burst 3.8 Mbps

Peak Rate

Median Users

3 Mbps

1.5 Mbps

Cell Edge Users

Figure 2 Cell performance as a function of proximity. (Source: Qualcomm)

in the fourth quarter of 2010 and has embarked on an aggressive advertising campaign. LTE has truly arrived, but why? The fastest movers to date have been those on the CDMA2000 track, as the rapid alignment behind LTE left them without an upgrade path of their own. To remain competitive and, in many cases, to get an advantage in their markets, a rapid move to LTE was necessary. From a technical perspective, LTE promises a significant boost in performance over today’s 3G HSPA and CDMA2000 evolution-data optimized (EV-DO) networks. In addition, it delivers a flat Radio Access Network (RAN) architecture that reduces RAN costs, and an all-IP core network that reduces capital and operating expense costs as well as supports service innovation. It provides a rapid path away from the existing silos of CS voice and PS data networks, moving away from costly CS equipment and maintenance. Also, with a solid upgrade path to LTE-A, operators can deploy base sta-

tions today that are software upgradeable to LTE-A, managing their longterm network evolution costs. Finally, the global economies of scale expected cannot be ignored and are driving operators to follow suit and choose the LTE path. In the end, LTE offers the lowest cost/bit next-generation mobile technology. The biggest question facing the LTE market is whether or not operators from the GSM lineage will decide to move to HSPA+ first and then migrate to LTE-A, or if they will make the jump directly to LTE in the near term. Much of this will be decided by competitive situations in each market. For example, Verizon’s push into LTE has accelerated AT&T’s LTE plans, whereas early on, AT&T had been a major proponent of HSPA+.

Deployment Strategies

The final question involves what deployment strategies and supporting technologies are available to ensure 4G operators’ competitive edge and managed costs moving forward. The two key

elements identified here are the cell splitting technology of small cells and the intelligent traffic management capabilities powered by Deep Packet Inspection (DPI). Small cells and DPI are critical elements, regardless of whether the operator plans to deploy HSPA+, LTE or WiMAX. The term “small cells” refers to delivering service over a myriad of different sized base stations as illustrated in Figure 1. Small cells deliver a massive increase in performance—even more so than just moving to a next-generation air interface. Mobile data services are delivered over a shared channel, which means the more users operating in parallel, the less throughput allocated per user. If you shrink the cell you effectively reduce the number of users served and immediately deliver greater performance. Additionally, signal to interference plus noise ratio (SINR) reduces as you get further away from the cell, and therefore, the realized performance reduces. Figure 2 illustrates this phenomenon from an HSPA+ perspective. RTC MAGAZINE OCTOBER 2011



Video Conference Operator VoIP Gaming Video on Demand Email Business Class VPN Browsing P2P

Tiered SLAs

Maximum Network Monetization

App-based QoS

Figure 3 Deep packet inspection approach for traffic shaping and management.

By delivering service using small cells, the operator is ensuring that the user is closer to the transmitter and enjoying the best possible performance. Finally, small cells are the most costeffective base station. When deployed in a residential area or home use situation, the operator no longer bears the cost of site acquisition, power or backhaul. Operators who leverage small cells could even consider an “inside out” deployment model, where 4G services are deployed to the home and in hotspots where capacity and performance are needed most, and macro area coverage is provided by existing 3G networks. Intelligent or mobile aware traffic shaping and management, in the near term, really is a tool for the operator deploying HSPA+ on top of existing core network infrastructure, and will become a useful solution for LTE or WiMAX operators as subscriber adoption continues. In the HSPA+ scenario, it was

Offloaded data traffic to PDN CRF



Internet Gi Ga Gx

lub Node B



lu RNC


IOG Signaling



Non-offloaded data traffic

Offloaded data traffic

Offloading • Bump-in-wire device • DPI application/protocol Figure 4 A 3G Internet offload gateway.



• Minimize traffic to CN • Reduce CN OPEX/CAPEX


highlighted that increased capacity will quickly need to be added to the existing core networks that HSPA+ will be tacked onto. The huge throughput gains at the air interface will impact already capacity-crunched core networks. Operators have the choice of simply adding more core network equipment or leveraging a DPI-based traffic shaping and management solution to extend the life of their existing infrastructure. Figure 3 illustrates at a high level the benefits of DPI solutions. In addition to managing the traffic flow more efficiently on their networks, operators may leverage a different DPI-driven application to offload the traffic from their core network. An Internet offload gateway (IOG) may be deployed at the edge of the network and, based on operator-defined policies, divert Internet traffic from the network early on, providing savings both in core network and transport infrastructure. Figure 4 illustrates a 3G IOG architecture. By intelligently managing and, in some cases, offloading traffic, HSPA+ operators have an opportunity to manage the costs of their network rollouts and leverage the less expensive base station upgrade to HSPA+. For those operators that choose to move to LTE or WiMAX, these solutions will be necessary as subscriber adoption increases, and will provide similar benefits in extending the life of their packet core equipment while allowing operators to focus CAPEX on coverage and capacity in the RAN. The marketing term 4G is here to stay, and everything from HSPA+ to LTE-Advanced is going to be called 4G. Operators are choosing their network evolution path not just on technical merit, but also with a view toward their competitive environment, spectrum availability and global economies of scale. So far, it seems LTE is the clear winner in the 4G race, but in mobile telecommunications, the race is a marathon not a sprint. Accordingly, it will be interesting to see how WiMAX and HSPA+ proponents combat the LTE momentum. In the end, operators cannot just leverage a new air

interface to provide true 4G performance to their subscribers. They will need tools like small cells and DPI applications to meet the needs of the data hungry, onthe-move Internet generation, which, frankly, is ready for 5G. LTE-Mega Advanced anyone?

Untitled-3 1

RadiSys Hillsboro, OR. (503) 615-1100. [].


10/12/11 10:03:26 AM RTC MAGAZINE OCTOBER 2011



Wireless Networking

Defining the Future of Multi-Gigabit Wireless Communications The WiGig specification utilizes the unlicensed 60 GHz band worldwide to provide data rates up to 7 Gbit/s. Based on the 802.11 standard, it includes native support for Wi-Fi over 60 GHz. Products with tri-band radios will be able to transparently switch among 2.4 GHz, 5 GHz and 60 GHz networks. by Ali S. Sadri,


he widespread availability and use of digital multimedia content has created a need for faster wireless connectivity that current commercial standards cannot support. This has driven demand for a single standard that can support advanced applications such as wireless display and docking, as well as more established usages such as network access. The Wireless Gigabit (WiGig) Alliance was formed to meet this need by establishing a unified specification for wireless communication at multi-gigabit speeds. This specification is designed to drive a global ecosystem of interoperable products. The WiGig MAC and PHY Specification enables data rates up to 7 Gbit/s, more than 10 times the speed of the fastest Wi-Fi networks based on IEEE 802.11n. It operates in the unlicensed 60 GHz frequency band, which has much more spectrum available than the 2.4 GHz and 5 GHz bands used by existing Wi-Fi products. This allows wider channels that support faster transmission speeds. The WiGig specification is based on the existing IEEE 802.11 standard, which is at the core of hundreds of millions of Wi-Fi products deployed worldwide. The specification includes native support for



Common Upper MAC (Management) Multi-band operation (WiGig/.11ad)

2.4 GHz

BB & Lower MAC

BB & Lower MAC



5 GHz

60 GHz

Figure 1 WiGig architecture enables tri-band communications.

Wi-Fi over 60 GHz; new devices with triband radios will be able to seamlessly integrate into existing 2.4 GHz and 5 GHz Wi-Fi networks (Figure 1). IEEE 802.11ad

is an amendment to the 802.11 standard that enables multi-gigabit wireless communications in the 60 GHz band. The WiGig specification was submitted to the


IEEE 802.11ad standardization process, and was confirmed in May 2010 as the basis for the 802.11ad draft standard. The specification enables a broad range of advanced uses, including wireless docking and connection to displays, as well as virtually instantaneous wireless backups, synchronization and file transfers between computers and handheld devices. For the first time, consumers will be able to create a complete computing and consumer electronics experience without wires.


DisplayPort HDMI




Specification Overview

The WiGig specification includes key features to maximize performance, minimize implementation complexity and cost, enable compatibility with existing Wi-Fi and provide advanced security. Key features include: • Support for data transmission rates up to 7 Gbit/s; all devices based on the WiGig specification will be capable of gigabit data transfer rates • Designed from the ground up to support low-power handheld devices such as cell phones, as well as high-performance devices such as computers; includes advanced power management • Based on IEEE 802.11; provides native Wi-Fi support and enables devices to transparently switch between 802.11 networks operating in any frequency band including 2.4 GHz, 5 GHz and 60 GHz • Support for beamforming, maximizing signal strength and enabling robust communication at distances beyond 10 meters • Advanced security using the Galois/ Counter Mode of the AES encryption algorithm • Support for high-performance wireless implementations of HDMI, DisplayPort, USB and PCIe The WiGig specification defines Physical (PHY) and Medium Access Control (MAC) layers and is based on IEEE 802.11. This enables native support for IP

Enhanced 802.11 MAC New 60 GHz PHY

Figure 2 WiGig Protocol Adaptation Layers (PALs).

networking over 60 GHz. It also makes it simpler and less expensive to produce devices that can communicate over both WiGig and existing Wi-Fi using tri-band radios (2.4 GHz, 5 GHz and 60 GHz). The WiGig Alliance is also defining Protocol Adaptation Layers (PALs) that

support specific data and display standards over 60 GHz. PALs allow wireless implementations of these standard interfaces that run directly on the WiGig MAC and PHY, as shown in Figure 2, and can be implemented in hardware. The initial PALs are audio-visual (A/V), which de-

WiGig Beamforming Use of the 60 GHz band allows extremely fast communication, but also presents the challenge that propagation loss is higher than in the 2.4 GHz and 5 GHz bands. The WiGig specification addresses this challenge using adaptive beamforming, a technique that enables robust multi-gigabit communications at distances greater than 10 meters. Beamforming employs directional antennas to reduce interference and focus the signal between two devices into a concentrated “beam.” This allows faster data transmission over longer distances. Support for beamforming is defined within the PHY and MAC layers of the WiGig specification. During the beamforming process, two devices establish communication and then fine-tune their antenna settings to improve the quality of directional communication until there is enough capacity for the desired data transmission. Another key benefit is that if an obstacle blocks the line of sight between two devices—if someone walks between them, for example—the devices can quickly establish a new communications pathway using, for example, beams that reflect off walls.




CHANNEL BOUNDARIES (GHz) 57.24-59.4 59.4-61.56

fication includes new features that support advanced usage models, facilitate integration with Wi-Fi networks, reduce power consumption and provide strong security.

61.56-63.72 63.72-65.88

Network Architecture


Canada Korea EU China Japan












SPECTRUM ALLOCATION (GHz) Figure 3 Worldwide spectrum availability in the 60 GHz band used by WiGig.

fines support for HDMI and DisplayPort, and input-output (I/O), which defines support for USB and PCIe.

Physical Layer (PHY)

Like the 2.4 GHz and 5 GHz bands used by Wi-Fi, the 60 GHz band used by WiGig is unlicensed and available worldwide. Within the 60 GHz band there is variation in the spectrum available in different countries, as shown in Figure 3. Worldwide, the 60 GHz band has much more spectrum available than the 2.4 GHz and 5 GHz bands —typically 7 GHz of spectrum, compared with 83.5 MHz in the 2.4 GHz band. This spectrum is divided into multiple channels, as in the 2.4 GHz and 5 GHz bands. Because the 60 GHz band has much more spectrum available, the channels are much wider, enabling multigigabit data rates. The WiGig specification defines four channels, each 2.16 GHz wide—50 times wider than the channels available in 802.11n. These wide channels enable WiGig to support applications that require ex-



tremely fast communication, such as uncompressed video transmission.

Modulation & Coding Scheme (MCS)

The specification supports two types of modulation and coding schemes, which provide different benefits: • Orthogonal frequency-division multiplexing (OFDM) supports communication over longer distances with greater delay spreads, providing more flexibility in handling obstacles and reflected signals. Furthermore, OFDM allows the greatest transmission speeds of up to 7 Gbit/s. • Single carrier (SC) typically results in lower power consumption, so it is often a better fit for small, low-power handheld devices. SC supports transmission speeds up to 4.6 Gbit/s. The two types of schemes share common elements such as preamble and channel coding. This reduces implementation complexity for manufacturers of WiGig devices. The MAC layer of the WiGig speci-

The specification defines a new network architecture that enables two devices to communicate directly with each other, allowing new uses such as rapidly synchronizing two devices and transmitting audio-visual data to a projector or TV. In addition, the specification also supports existing 802.11 network architectures, including the use of a shared access point as in today’s Wi-Fi networks. A communication session can be rapidly and seamlessly transferred between a 60 GHz channel and any lower-frequency Wi-Fi channel, including channels in the 2.4 GHz or 5 GHz band. This innovation enables seamless fallback to 2.4 GHz or 5 GHz Wi-Fi if 60 GHz WiGig connectivity is not available. Multi-band operation provides a greatly improved user experience. Users with multi-band devices will be able to continue accessing the network, without interruption, if their device switches from a 60 GHz to a lower-frequency WiFi channel. They will always experience performance that is at least as good as today’s Wi-Fi products, and will be able to automatically take advantage of the additional speed of 60 GHz WiGig whenever it is available. WiGig devices can take advantage of a new scheduled access mode to reduce power consumption. Two devices communicating with each other via a directional link may schedule the periods during which they communicate; in between those periods they can sleep to save power. This advanced capability allows devices to more precisely tailor their power management to their actual traffic workload, and is especially important for cell phones and other handheld batterypowered devices. The WiGig specification builds on the strong security mechanisms used in IEEE 802.11. WiGig uses Galois/ Counter Mode, a highly efficient mode of operation that is designed to support communication speeds of 10 Gbit/s and above, provides strong encryption based on the



Kiosk Sync & Data Exchange

Instant Wireless Sync - IP-based P2P applications - Using I/O PAL

Wireless Display

Wireless Display

- HD streams over HDMI or DP using A/V ..PAL -CE, PE and HH usages

Distributed Peripherals

Cordless Computing

- Combination of Wireless display using ..A/V PAL, sync and I/O using I/O PAL


Internet Access

- Using native Wi-Fi, 802.11ad support

Figure 4 Usage models.

Advanced Encryption Standard (AES), is government-recommended, and can be implemented in hardware for performance and efficiency.

Protocol Adoption Layers (PALs)

PALs allow wireless implementations of key computer and consumer electronics interfaces over 60 GHz WiGig networks. PALs make it easier for implementers to produce devices with built-in support for specific uses such as wireless connections to displays. PALs enable highly efficient implementations because they are defined directly on the WiGig MAC and PHY, rather than layered on other protocols, and can be implemented in hardware. This maximizes performance and reduces power consumption. PALs defined to date are the Audio-Visual (A/V) and the Input-Output (I/O) APALs. The A/V PAL allows wireless transmission of audioÂŹ-visual data. An example might be transmitting movies from a computer or digital camera to a TV set or projector. This PAL supports wireless

implementations of HDMI and DisplayPort interfaces, as well as the High-bandwidth Digital Content Protection (HDCP) scheme used to protect digital content transmitted over those interfaces. It scales to allow transmission of both compressed and uncompressed video. The I/O PAL defines high-performance wireless implementations of widely used computer interfaces over 60 GHz. Definitions exist for USB and for PCIe. USB is typically used to connect external peripherals and other devices to a host; the USB PAL enables multi-gigabit wireless connectivity between USB devices, and facilitates the development of products such as USB docking stations. PCIe is typically used within computers to connect the CPU and memory to I/O controllers that support storage, network cards and other interfaces. It is also used to connect to media and visual processors to enhance picture quality or offload processing from the CPU. Implementation of the PAL enables multi-gigabit wireless synchronization between devices and con-

nection to storage and other high-speed peripherals. The WiGig specification and PALs enable multi-gigabit wireless implementations of a broad range of new and existing usage models, as shown in Figure 4. The publication of the specification enables manufacturers to create a global ecosystem of interoperable WiGig products. WiGig Alliance and Wi-Fi Alliance established a cooperation agreement in May 2010 to share technology specifications for the development of a next-generation Wi-Fi Alliance certification program. This agreement further encourages the development of products supporting 60 GHz technology to expand existing Wi-Fi capabilities. The specification is available to members of the WiGig Alliance who are able to develop next-generation wireless products under royalty-free terms. For more information, including how to become a member, visit WiGig Alliance [].



products &

TECHNOLOGY Sandy Bridge in PC/104 Form Factor—i7, 2.2 GHz PCIe/104 SBC

A PC/104 form factor features the 2nd generation Intel Core i7 processor that incorporates Intel’s latest embedded twochip platform. This 2nd generation i7 processor integrates Intel’s HD Graphics 3000 engine with AVX (Advanced Vector Extensions) as well as the memory controller functions of a traditional GMCH. The QM67 Platform Controller Hub (PCH) provides PCI Express I/O bandwidth at twice the speed (5 Gbit/s) of previous i7 or Core 2 Duo platforms. The ADLQM67PC from Advanced Digital Logic is suitable for rugged applications where high processor performance is critical. It brings unparalleled performance to applications such as radar and sonar processing, image signal processing, tactical command and control, surveillance and reconnaissance, transportation and railway. In addition to the wide range of rugged and harsh environment applications in which the ADLQM67PC can perform, it also supports a healthy set of features. The ADLQM67PC has a discrete 16-bit digital I/O port as well as separate VGA, LVDS, HDMI and Display Port interfaces. The ADLQM67PC also has 2x RS-232 COM ports, 2x SATA 6 Gbit/s with RAID support, 8x USB 2.0, two bootable Gigabit Ethernet LAN, HDA 7.1, and type 1 bottom-stacking PCI Express V2.0 supporting Gen2 throughput of 5 GT/s are just a few of the available features. Two key features that will make the ADLQM67PC a popular high-performance computing platform is the ability to offload general purpose computing onto the GPU, and the added flexibility and 5 Gbit/s bandwidth of the second generation PCI Express bus, which make possible tantalizing high-performance peripherals such as 10G Ethernet in the near future. Advanced Digital Logic San Diego, CA. (858) 490-0597. [].

Fanless Box Computer with VIA Nano/Eden CPU

A fanless box computer for embedded applications is powered by Via Nano/Eden processors. Housed in a compact, robust enclosure, the PL-80320 from Win Enterprises can be applied to a range of applications such as industrial automation, kiosk, POS and digital signage. The unit offers a range of processor performance that includes 500 MHz, 1.0 GHz and 1.3 GHz. Excellent connectivity is provided with eight COM ports, dual GbE LAN and four USB 2.0 ports. In addition to fanless operation, the PL-80320 features a compact size of 217 mm (W) x 141 mm (D) x 69 mm (H) or 8.6”W x 5.6”D x 2.7”H. The onboard processors available are the 500 MHz VIA Eden, the 1.0 GHz VIA Eden and the 1.3 GHz Via Nano. I/O includes dual GbE, four USB 2.0 ports and eight COM ports plus a high-definition audio interface. One mini PCIe and a single CompactFlash interface are supported. WIN Enterprises, North Andover, MA. (978) 688-2000. [].



RISC SBC with ARM-Based Cortex-A8 Series Processor

A new RISC-based Single Board Computer uses the latest Texas Instruments OMAP35 Series Processor. The PCM-C3500 from Advantech has a CortexA8-based TI OMAP35 600 MHz high-performance/application processor with mobile DDR. It supports OpenGL ES 1.1 & 2.0, OpenVG 1.0 and Direct 3D. The PCM-C3500 video also supports D1 resolution directly. Advantech PCM-C3500 series units are designed for low power consumption around 2W (3W maximum). These heatsink-free designs are suitable for various low-power applications in industrial control, HMI/kiosk, medical and portable applications. In addition to supporting Windows Embedded CE 6.0, Embedded Linux 2.6 and Android (on a project-by-project basis), the PCM-C3500 Series supports Advantech’s SUSIAccess, a set of software APIs that reduce project development effort, enhance hardware platform reliability, and shorten timeto-market. SUSIAccess also provides an easy upgrade path as functions are continuously added and improved. The off-the-shelf evaluation kit provides a complete design environment with full technical documentation. In addition to the OSready platform, Advantech provides an application-oriented support package, complete with testing and evaluation capabilities, which minimizes development effort. The evaluation kit includes: the OS-ready, RISC-based COM/ SBC; the LCD kit (with LCD, touchscreen, etc.); test cables; power adaptor and accessory package; and a CD-ROM (with system upgrade/maintenance utilities, SDK, system test utility, user manual and COM design guide). Advantech, Irvine, CA. (949) 789-7178. [].


Boundary Scan Platform Extends Integration of Bus Interface Tests

The new member to the Scanflex module series from Goepel Electronic provides five ports for the universal test of industrial interfaces, which can be completely electrically isolated with relays. With the SFX-9305/R, users are now able to combine functional test procedures for bus interfaces such as LAN, USB, CAN or LIN with vector-less working test methods on a unique platform. In addition to increased fault coverage, the new integration opportunities result in reduced test costs by saving separate process steps. The SFX-9305/R module provides five independent, freely configurable bus ports. The target is physically accessed by a selection of bus access cables (BAC). The current configuration is automatically identified, whereby BAC type and quantity are freely definable. By parallel operation of several SFX-9305/R modules, the number of available bus ports is nearly unlimited. Supported interfaces are LAN (10/100/1000), USB 2.0 (Host/Slave), Bluetooth, CAN (high-speed/low-speed), LIN, RS-232 and RS-422/458. Additional interfaces are being developed. The available interface functions contain the step-wise handling of protocol layers including bi-directional data transfer. Hence, users can completely control the bus target without additional driver software and clearly identify faults. SFX-9305 can be combined with all Scanflex controllers on the basis of PCI, PCI Express, PXI, PXI Express, FireWire, USB and LAN. It is fully supported in the industrially leading JTAG/Boundary Scan software System Cascon from version 4.5.x on. Module programming and handling of test program data are based on user-friendly Caslan instructions. Caslan is currently the most powerful Boundary Scan programming language with several hundred commands supporting IEEE1149.1, IEEE1149.4, IEEE1149.6, IEEE1532 andGet JESD71 as well as with mixed signal operaConnected technology and tions and VarioTAP for emulation test as well as control of chip embedded instruments. companies providing solutions now Get Connected is a new resource for further exploration GOEPEL electronic, Jena, Germany. +49 3641 6896 739. [].

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into products, technologies and companies. Whether your goal

Integration Testing Tool Comes with Enhanced Support of ASAP2

The latest version of Tessy, a tool to automate unit / integration testing of embedded software and distributed by Hitex Development Tools, now offers enhanced support of the ASAP2 standard. Tessy can use the standard’s conversion rules to change a (physical) test input value into a binary value, which then can be used for the test. Conversely, Tessy can convert binary test results into physical formats the test engineer is used to. This allows him to work in a familiar way when generating test cases and checking test results. Tessy has already supported the ASAP2 standard for more than ten years. The new release now also enables the initialization of characteristic curves with physical values. All kinds of definition for axises and data from ASAP V1.5.1 are supported by Tessy. Furthermore, all values that are entered in Tessy using the integrated editor or that are imported into Tessy from files are converted to the nearest valid physical value according to the ASAP conversion rule in question. ASAP2’s full name is ASAM MCD-2 MC. ASAM stands for the organization (Association for the Standardisation of Automation and Measuring Systems) and MCD for Measurement, Calibration and Diagnosis. It is a standard for the conversion of physical values in their ususal representation (e.g., temperature in °C) and the internal (binary) representation of the value in the memory of a computer. This conversion may not be trivial, i.e., a binary zero does not need to represent 0°C in any case, but the binary zero may represent for instance -40°C (and the binary one may represent -39.5°C). The standard is mostly used in the automotive field, where values from the memory of an electronic control unit (ECU) need to be converted for input and display using external tools, e.g., calibrating tools. Hitex Development Tools, Irvine, CA. (949) 863-0320. [].

is to research the latest datasheet from a company, speak directly Software Platform for Medical Devices Comes with with an Application Engineer, or jump to a company's technical page, the Compliance Documentation goal of Get Connected is to put you in touch with the right resource.

of service you require for whatever type of technology, A new softwareWhichever suite forlevel mediGet Connected will help you connect with the companies and products cal devices is part of a comprehenyou are searching for. sive software portfolio designed for medical device development, including those devices requiring premarket notification, U.S. Food and Drug Administration’s (FDA) 510(k), or the more stringent premarket approval. The Platform GetWind Connected with technology and companies prov for Medical Devices from Get Connected is a new resource for further exploration into pro River is a commercial off-the-shelf datasheet from a company, speak directly with an Application Engine (COTS) development and run-time platform enabling safety and secuin touch with the right resource. Whichever level of service you requir rity for medical devices.Get The Platform iswillbuilt River’s Connected helpon youWind connect with theVxWorks companies and produc real-time operating system (RTOS), which has a proven track record for use in regulated medical devices that demand the highest levels of safety, reliability and performance. It also includes Wind River Workbench, a collection of embedded software development tools, as well as critical networking and middleware run-time technologies, such as IPsec, SSL, IPv6 and USB. Having VxWorks serve as the core of Wind River Platform for Medical Devices enables the medical device developers to focus on differentiation, while leveraging the core foundational elements of small footprint, determinism, scalability and high performance. An essential component of the Platform is a comprehensive vendor qualification summary (VQS), which includes documented descriptions of the controls processeswith Wind River uses Getand Connected companies and to design and develop its platform components. Thein VQS is prepared in accordance with FDA products featured this section. quality system regulation 21CFR820.50 Purchasing Controls, which require manufacturers to evaluate suppliers for their ability to meet specified requirements, including quality requirements.


Wind River, Alameda, CA. (510) 748-4100. []. Get Connected with companies and products featured in this section.




PLX Technology Expands PCI Express Gen3 Switch Family

Three new high-performance, feature-packed devices compliant with the PCI Express Gen3 r1.0 Specification are aimed at enabling new, more powerful designs in servers, storage and communications platforms. The new ExpressLane PEX8749 (48-lanes, 18 ports), PEX8733 (32 lanes, 18-ports) and PEX8725 (24 lanes, 10 ports) PCIe Gen3 switches from PLX Technology blend innovation and high port counts. With the debut of these three new switches, PLX is expanding its PCIe Gen3 portfolio to 11 highly flexible devices ranging from 12 to 48 lanes, and three to 18 ports. Integrated into each new PLX PCIe Gen3 multi-root switch device are performancePAK features, including two non-transparency (NT) ports, four direct memory access (DMA) engines, two virtual channels (VCs), and up to 12 ports for spread spectrum clock (SSC) isolation. The NT feature enables host failover and redundancy and has been widely used by tier-one OEMs since it was developed in early PCI technology. The on-chip DMA engines enable designers to increase the performance of systems by moving data among endpoints or between memory and endpoints without sacrificing CPU bandwidth. Support for two VCs enable users to prioritize traffic to support desired quality of service (QoS). The SSC clock isolation for each x4 port of the device allows designers to create large systems with each subsystem running its own SSC clock. In addition to x16 and x8 ports, these switches offer native x2 and x4 ports that enable development of large arrays of SSD-based systems with fewer switches. Also included is the support for PCIe specification engineering change notices (ECNs) such as multicast, access control service (ACS), alternative routing-ID interpretation (ARI), atomic operations, and optimized buffer flush/fill (OBFF). PLX PCIe Gen3 devices are fully backward compatible with Gen2/Gen1 devices and recommended for all new designs. The PLX Gen3 devices can be used to create Gen3 slots using their bridging capability in a Gen2 platform. The new switches are supported by PLX’s visionPAK system debug tools, such as Performance Monitoring, Error Injection, Packet Generator, and the ability to measure both width and height of a SerDes eye using PLX’s free software development kit (SDK). The on-chip hardware debug features, complemented by the SDK software, offer instant logic analyzer support, high-speed scope view, pattern generation and error injection—capabilities that shed the cost of spending hundreds of thousands of dollars on test equipment. Volume pricing is $35.00 to $70.00. PLX Technology, Sunnyvale, CA. (408) 774-9060. [].

6U PXI Switch Matrices Target High-Density Needs

Two new high-density 6U PXI matrices provide the highest density single slot solutions available in the 6U PXI format. The 45-541 and 45-542 matrices from Pickering Interfaces are suitable for those users who have selected the increased board area that 6U offers over 3U PXI, when compared to their previous generation VXI/VME modular platforms. Providing a solution based on the faster operating speed of reed relays and of the higher capacity EMRs gives users a choice of pin compatible switching solutions. The 45-541 is a reed relay matrix occupying one slot of a 6U PXI chassis, which provides a 132x8 matrix that supports 0.5A switching and up to 10W hot switch capacity. User connections are provided through easy to use 50 way D Type connectors. The module includes BIRST (Built-In-Relay-Self-Test) capability that allows functional checks on all the reed relays to be conducted without the use of supporting test equipment. The 45-542 is an electro-mechanical relay (EMR)-based matrix occupying just one slot of a 6U PXI chassis supporting a 132x8 matrix with 1A, 60W switching capacity. It is user pin compatible with the 45-541. Pickering Interfaces, Clacton on Sea, UK. +44 (0) 1255 687900. [].



Multifunction USB Modules for Low-Cost Data Acquisition

Equipped with built-in signal conditioning, a family of USB-powered Plug and Play USB DAQ modules delivers easy connection and accurate results for both portable measurement and machine automation applications. Featuring built-in signal conditioning, the USB-1900 Series and USB-2401 USB DAQ modules from Adlink enable direct measurement of most frequently applied signal sources, which reduces manpower requirements and associated development costs while increasing overall accuracy. All of Adlink’s USB DAQ modules feature USB power and removable screw-down terminals for simplified device connectivity, and a multifunctional stand for fast and easy desktop, rail, or wall mounting. Additionally, a lockable USB cable secures connectivity. The USB DAQ modules also provide device ID setting by a rotary control for convenient identification of the active module in multiple-connection configurations. Adlink’s USB DAQ collection offers the USB-1900 series, consisting of USB-1901 and USB-1902 models of 16-bit 250kS/s DAQ modules. Also in the series is the USB-1903, with additional built-in precision current-tovoltage resistors allowing direct measurement of current signals from 0 to 20 mA. Rounding out the USB DAQ category is the USB-2401, a 24-bit four-channel simultaneous-sampling universal DAQ module supporting sampling rates up to 1.6 kS/s and a more flexible signal conditioning circuit such as voltage, current, strain, load cell, thermocouple and RTD measurement. The USB DAQ line is ideally suited for easily accomplished deployment and superior accuracy when measuring temperature, stress, strain and other factors in diverse applications. The USB DAQ modules include Adlink’s free U-Test utility, allowing direct operation and testing of all functions with no requirement for coding or programming. Driver support is provided for Windows 7/Vista/XP, in both 32-bit and 64-bit versions, and third-party software support accommodates LabVIEW & MATLAB. ADLINK, San Jose, CA. (408) 360-0200. [].


Digital I/O Module on PXI Basis for Signal-Critical Applications

Two JTAG Digital I/O Modules on PXI bus basis support structural JTAG/Boundary Scan tests as well as dynamic I/O operations up to 100 MHz for functional test executions. The PXI5396DT/x modules from Goepel Electronic feature an impedance controlled VPC interface for direct coupling to signal-critical load boards or other verification environments. Consequently, users are now able to utilize only one piece of test hardware for both laboratory verification and in the production line with fixture-based systems, which results in a significantly higher flexibility. The PXI 5396-DT/x modules are based on a two-component solution, consisting of a PXI supported interface module (IFM) and an offset desktop module. The modules can be separated as far as 2 meters without loss of performance. The desktop module is equipped with a front connector developed by Virginia Panel Corporation, which allows the module to be connected directly to the test environment. Due to this, an optimum reliability of the I/O signals is achieved by fully controllable line impedance. Two variants are available, which differ in the onboard memory depth of 72 Mbyte with the PXI 5396-DT and 144 Mbyte with the PXI 5396DT/XM. Both variants provide 96 single-ended channels, configurable as input, output and tri-state, which allow simultaneous driving and measuring, as well as real-time comparison. While the signals are processed synchronously to the test bus operations in the JTAG mode, the dynamic I/O mode allows functional testing with freely programmable clock rates within the range of 500 Hz to 100 MHz. Hence, structural boundary scan tests with succeeding functional tests can be executed with the same instrument. The included VarioCore technology adds extra flexibility to the module by enabling the use of custom IP embedded in the module hardware. Both PXI 5396/FXT-x are fully software-supported by the integrated JTAG/Boundary Scan development environment System Cascon from version Get Connected with technology and now scan. 4.5 on. This includes the automatic generation of wiring diagrams, as well as the automatic test programcompanies generationproviding (ATPG) solutions for boundary After the test is finished, a failure diagnosis on pin and net level is executed, with the fault location being visualized in theislayout. Get Connected a new resource for further exploration into products, technologies companies. Whether your goal The execution of functional dynamic tests and the subsequent failure diagnosis are based on the support of the standardand IEEE 1445 Digital to research the latest datasheet from a company, speak directly Test Interchange Format (DTIF), which is now integrated in System Cascon. Additional to the importisprocessors, an interactive waveform editor is with an Application Engineer, or jump to a company's technical page, the also available. goal of Get Connected is to put you in touch with the right resource.

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GOEPEL Electronic, Jena, Germany. +49-3641-6896-739 [].

Storage XMC Features High Speed Operation and Front Removability

Developed to address rugged storage applications, a new singlewidth storage XMC uses the latest mezzanine form factor and flash drive technologies, including the new CFast flash storage technology. The next generation 9289 XMCStor solid-state CompactFlash drives from Elma Electronic are based on a SATA interface and offer much higher data rates compared to drives with a parallel connection. The XMCStor provides one front removable drive and one internal drive for maximum operational flexibility. Drives may be addressed as combined or separate volumes depending on their usage and application requirements. The front removable drive capability combined with hot swap allows fast and easy equipment upgrade and data transportability. With board level data transfer rates up to 130 Mbyte/s (write) and 140 Mbyte/s (read), the 9289 XMCStor is suitable for applications demanding high data rates. Current storage capacities equal 64 Gbyte across two drives, with higher capacities supported as new drives are introduced. The XMCStor is capable of meeting a wide range of operating conditions. It is available in standard (0° to +55°C) through extended temperature (-40° to +85°C) versions and can withstand operating shock up to 40 Gs at 11 Msec. For added reliability, the unit can be conformally coated. Elma provides XMCStor software support and drivers for Linux, VxWorks and Windows with specific versions and host cards available upon request. Pricing starts at $800 in low quantities, configuration dependent. Elma Electronic, Fremont, CA. (510) 656-3400. [].

Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Mini Datalogger Stores One Billion Measurements

A miniature datalogger now boasts capability for storing over one billion readings from a number of parameters simultaneously with 12-bit resolution. The MSR145 mini datalogger from Saelig, previously limited to only two million measurements, is now available with a slot for a removable microSD card (≥ 4 Gbyte). Connected This increases the storageGet of the logger to 1 with technology and companies prov billion measurements. TheGet MSR145’s SD is a new resource for further exploration into pro Connected datasheet card can be easily changed duringfrom on-a company, speak directly with an Application Engine in touch with athe right resource. Whichever level of service you requir going experiments, representing Connected will help you connect with the companies and produc significant benefit whenGet undertaking extremely long-term measurements. This allows users to evaluate the saved data at any time, whenever it may be necessary. Whether for monitoring the transportation of sensitive goods, climate monitoring in building services engineering, taking vibration and temperature measurements, or for documenting process workflows in industrial applications—the range of possible applications for which battery-powered MSR145 dataloggers can be used is virtually unlimited. MSR loggers are available with up to five different sensors— temperature, humidity, pressure, light, 3-axis acceleration, and can be expanded significantly with additional analog inputs. Featuring selectwith this companies andusers to connect individual able 12-bit Get inputConnected configurations, allows products featured in this section. external sensors for a diverse range of measurement applications. ing starts at $500.


Saelig Company, Pittsford, NY. (585) 385-1750. [].

Get Connected with companies and products featured in this section.




Validation Tools for New Intel Microarchitecture Codenamed Haswell

When circuit board designs for desktop and mobile applications roll out with Intel Core processors based on the new Intel microarchitecture codenamed Haswell, a new platform for embedded instrumentation will be able to access Intel’s embedded instruments and perform advanced validation on all of a board’s high-speed buses. The tool from Asset InterTech called ScanWorks High-Speed I/O (HSIO) for Intel Architecture (IA) is based on the Intel Core processor family and capitalizes on Intel’s embedded instruments intellectual property (IP). Asset is leveraging the success that ScanWorks has achieved in the Intel server marketplace by enhancing its capabilities and migrating it to the desktop and mobile markets. The new tools provide advanced diagnostics, bit-error-rate (BER) testing and margining for the Direct Media Interface (DMI), PCI Express Graphics (PEG) and DDR3 I/O buses. Asset is a key third-party vendor (TPV) to Intel. According to Intel, microprocessors based on the Haswell microarchitecture and accompanying chipsets will be a key step toward achieving the company’s Ultrabook vision of ultra thin, light, responsive and secure laptops and other types of designs. Inevitably, this microarchitecture with a projected power consumption 30% lower than current Core processors will migrate to embedded applications as well. Crucial to achieving this vision will be the performance of the high-speed serial input/output (I/O) buses that connect processors and chipsets to other devices on a circuit board. When bus speeds exceed approximately 5 Gbit/s, as they will on Intel’s future designs, they become supersensitive to capacitive coupling effects. This means that legacy testers like oscilloscopes and logic analyzers must compensate for the effects that result from placing a probe on a high-speed bus to verify its performance. In many cases, the capacitive effects of probing can invalidate test results. Some external testers have attempted to overcome these difficulties by resorting to simulation or higher-order mathematics, but these techniques only generate a projection of the actual signaling on the bus. Over the last seven years, Asset has collaborated with Intel to overcome these shortcomings and to empower design and test engineers with advanced validation and test tools. Because ScanWorks is a non-intrusive, software-based tools platform, it can use the instruments embedded in Intel’s chips to perform validation and test. The reports ScanWorks provides engineers are a more accurate reading of the signal integrity on an I/O bus than are the results from external, intrusive testers. ScanWorks High-Speed I/O (HSIO) will be available in 2012. Pricing for a one-year subscription is $10,000. Asset InterTech, Richardson, TX. (972) 437-2800. [].

3U CompactPCI PlusIO Compatible Blade with IPMI and TPM support

A new 3U CompactPCI PlusIO compatible processor blade supports high-speed serial point-to-point connections. The cPCI-3970 Series from Adlink is equipped with the latest quad and dual core 2nd Generation Intel Core i7/i5 processor, also known as Sandy Bridge, with ECC memory support, and the Intel QM67 Platform Controller Hub (PCH). It is a high-performance solution for applications in industrial control and automation, transportation and medical segments that require enhanced graphics capabilities, ECC memory and high-speed I/O interconnects. The cPCI-3970 Series includes two blade types based on the same electrical and mechanical design: the cPCI-3970, which is equipped with HM connectors, and the fully PICMG 2.30-compliant cPCI-3971, which features an Ultra Hard Metric (UHM) J2 connector with a data transfer speed of 5 Gbit/s. Both products are compatible with the CompacPCI PlusIO pin assignment and support PCI Express Gen2 x4, three SATA ports, three USB 2.0 ports and two Gigabit Ethernet ports at the J2 connector. The cPCI-3970 Series is a 3U CompactPCI blade with rich features for different applications. For high density computing applications, it can operate in a system slot as a master or in a peripheral slot as a standalone blade. In addition, the cPCI-3970 Series is compliant with the PICMG 2.9 specification and supports system management functions based on the Intelligent Platform Management Interface (IPMI) as well as hardware monitoring of physical characteristics such as CPU and system temperature, DC voltages and power status. With different riser cards installed and the addition of a Rear Transition Module (RTM), the cPCI-3970 Series provides versatile I/O interfaces up to two DisplayPort/DVI/HDMI, four serial ports, four SATA ports, five USB 2.0 ports, four GbE ports, PS/2 KB/MS, audio ports, and one PMC/XMC site for expansion flexibility. Trusted Platform Module (TPM 1.2) is also supported to provide efficient hardware-based data protection. The DisplayPort supports single link DVI or HDMI by passive adapter cable and analog VGA interface by active adapter cable. With the Adlink XMC-G460 graphics module installed in the XMC site, the cPCI-3970 Series supports up to four independent displays. Storage interfaces supported by the cPCI-3970 Series include one SATA 6 Gbit/s direct connector for a 2.5” HDD/SSD, CompactFlash socket, CFast socket and three SATA ports on RTM with RAID 0/1/5/10 support. The Adlink cPCI-3970 Series supports the following operating systems: Microsoft Windows XP, Microsoft Windows 7, RedHat Enterprise Linux 6 and VxWorks. ADLINK, San Jose, CA. (408) 360-0200. [].




User Interface for Graphical JTAG/Boundary Scan Project Development

Intuitive system controls guide first-time users safely through the project development flow and improve their productivity with a new JTAG/Boundary scan graphical user interface from Goepel Electronic. Cascon Mission Assist enables completely graphical project development based on predefined mission targets, while automating the contextsensitive adaptation of all system tools and process controls. The open and flexible design of Cascon Mission Assist provides support for various access technologies, such as Boundary Scan, processor emulation test, chip-embedded instruments, in-system programming and core-assisted programming based on a consistent software platform. This multidimensional instrumentation offers the benefit of optimized test coverage and throughput provided by a definition of mixed test and programming strategies. The new Mission Assist visualizes the entire project development workflow based on a selected mission target. This includes automated process scripting and complete management of centralized project data. In principle, type and scope of a mission are not limited; the library of missions integrated in System Cascon is subject to continuous extension with the introduction of new features and technologies. System Cascon, a professional JTAG/Boundary Scan development environment developed by Goepel Electronic, currently includes 45 completely integrated tools for in-system programming (ISP), test, debugging and design validation. Get4.6, Connected The new graphical project development based on Mission Assist is available with System Cascon version which will with start technology shipping atand the companies providing solutions now end of November 2011 and will be available as a free update for users with a valid software maintenance agreement.

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Goepel Electronic, Jena, Germany. +49 3641-6896-739. [].

1U Networking Appliance with Xeon E3-1200 Series

A new 1U rackmount appliance is powered by Intel E3-1200 series processors. The E3-1200 series represent the 2nd generation Core processors from Intel that deliver greater performance and efficiency than their Nehalem predecessors. PL-80310 from Win Enterprises provides a choice of Intel Xeon E3-1200 series 32nm dual- or quad-core processors with Intel Advanced Vector Extensions and Turbo Boost Technology. The PL-80310 is a high-performance platform that supports applications such as firewall, packet inspection, SPAM filtering, VPN, UTM, financial and Internet services. It supports Intel 32-nm Xeon, Corei3 LGA 1155 with a maximum of 32 Gbyte dualchannel DDR3 1066/1333 MHz system memory along with up to 5 GbE Copper ports via PCI-e x4/x1. The PL-80310 supports four unbuffered ECC or non-ECC DDR3 1066/1333 MHz DIMM sockets with memory up to 32 Gbyte. Storage interfaces include one 3.5â&#x20AC;&#x2122;â&#x20AC;&#x2122; SATA 3.0 and CompactFlash. The device supports an optional onboard Cavium Nitrox PX cn16xx to provide hardware-level cryptographic acceleration. The Cavium security coprocessor enables greater main computing power for higher-layer packet processing. An optional IPMI web-based user interface module for remote management provides powerful functionality with KVM over IP, SoL, Virtual Storage Redirection, remote power control and hardware monitor support. The platform comes standard with 7 GbE LAN ports, optionally expandable to a maximum of 15 GbE ports via PCI-E. PL-80310 supports two segments of LAN bypass function through WDT and GPIO pin definitions. The front panel features dual USB 2.0 ports, one RJ-45 console port, and four LED indicators. WIN Enterprises, North Andover, MA. (978) 688-2000. [].

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with anUSB Application or jump to a company's technical page, the 4-Port and 2-Port 3.0Engineer, Host Controllers Broaden goal of Get Connected is to put you in touch with the right resource. Choices Whichever level of service you require for whatever type of technology, Get Connected willcontrollers help you connect the companies and products Two new SuperSpeed USB Host havewith achieved Superyou areby searching for. Implementers Forum (USB-IF). Speed USB certification the USB

The certification Via Labs VL800 4-port and the VL801 2-port SuperSpeed USB host controllers provides the assurance that these products will interoperate with the bilGet Connected with technology and companies prov lions of USB-enabled devices Get available on the market while Connected is a new resource for further exploration into pro datasheet from a company, speak directly with an Application Engine delivering the speed, power in touch with the right resource. Whichever level of service you requir efficiency and power delivery Get Connected will help you connect with the companies and produc specified by the USB 3.0 standard. In addition to the VL800 and VL801 Host Controllers, Via Labs currently offers USB 3.0 SATA Bridge and USB 3.0 to NAND Flash Controllers, which have also achieved the USB-IF certification. The Via VL800 and VL801 are single chip USB 3.0 Host controllers, which enable a PCI Express equipped platform to interface with USB SuperSpeed (5 Gbit/s), High-Speed (480 Mbit/s), Full-Speed (12 Mbit/s) and Low-Speed (1.5 Mbit/s) devices. The VL800 root hub consists of four downstream facing ports, enabling the simultaneous operation of multiple peripheral devices. The VL801 has two downstream ports, and is pin-to-pin compatible. The Via Labs VL800 and VL801 USB 3.0 Host controllers are currently shipping.


VIA Labs, Taipei, Taiwan. +886-2-2218 8924.and []. Get Connected with companies products featured in this section.

Get Connected with companies and products featured in this section.




Two-in-One Development Platform for Xilinx Spartan 6 FPGA on SBC

A turnkey single board computer development environment for the Xilinx Spartan 6 FPGA is aimed at accelerating development of FPGA-based applications for low-power embedded systems. The DK-FPGA1651 from Micro/sys provides designers the option to develop and debug their FPGA firmware for porting to their own user-designed hardware or to keep the firmware on the validated COTS platform for their final application. With all the basic building blocks in one package, designers can work smarter and leverage prevalidated hardware and software including FPGA firmware (VHDL and Verilog) examples to improve productivity, reduce R&D costs and speed time-to-market. The DK-FPGA1651 enables designers who intend to use the SBC as their target’s hardware to use the Spartan 6 in various modes depending on the complexity of their application. For instance, FPGA users can begin by implementing “simple” onboard I/O such as UARTs, DIO, and/or CAN in the FPGA. This added I/O can interface to the outside world through 64 bidirectional signals mapped directly from the FPGA to headers. Additionally, there are four RS-232/RS485 transceivers and five differential LVDS signals to ease I/O expansion. For more advanced system designs, the integration between the onboard Freescale i.MX515 ARM Cortex-A8 processor and the FPGA enables developers to expand upon the SBC’s feature set by adding IP cores in the FPGA, which bring features such as DSP, Gigabit Ethernet, SATA, or dual video to the SBC with firmware. Additionally, users can choose to implement yet another processor on board such as the Xilinx Spartan 6 MicroBlaze for dedicated control independent of the SBC’s CPU. With all the necessary components to immediately start development with the Spartan 6, the DK-FPGA1651 two-in-one turn-key kit allows designers to focus on building differentiating features into their end application. To ease I/O hardware pinouts, the DKFPGA1651 comes with multiple connectivity examples including 64 lines of bi-directional GPIO signals, four pre-validated transceivers for RS-232/RS-485, and five differential LVDS signals for user-defined configuration. These added features enable easy addressing and decoding for customized protocols by providing designers a 32-bit data bus as well as 32-bits of addressing lines for data-in, data-out of various IP cores for functions such as real-time video, motion control and industrial Ethernet. Designers profit from the easy-touse Xilinx ISE Design Suite including the Embedded Development Kit and selection of validated IP cores as well as Micro/sys’s embedded system expertise to shorten design time and gain smarter methodologies for creating FPGA-based solutions. The DK-FPGA1651 starts at $1695. The kit includes the Micro/sys SBC1651 (Linuxor WinCE-Ready), Xilinx ISE and EDK design software and Micro/sys interface software, multiple reference designs and demos, and all the necessary cables and adaptors. Micro/sys also offers custom FPGA programming services. Micro/sys. Montrose, CA. (818) 244-4600. [].

JTAG/Boundary-Scan Tool for Debug & Repair

A new “no-netlist-required” JTAG/ boundary-scan test and debug tool uses a “seek and discover” feature to scan completely a compliant design and then perform comparative tests using JTAG/boundary-scan. AutoBuzz from JTAG Technologies needs only JTAG scan-chain information plus BSDL models of the JTAG/IEEE std 1149.1 compliant parts (available from manufacturers’ web sites), to enable users to connect to their designs via a number of compatible JTAG interface options. AutoBuzz can then be set to gather a complete “connectivity map” of any board’s boundary-scan to boundary-scan pin connections (where these can be direct or via “transparent” devices such as series resistors).

AutoBuzz supports just two simple operating modes: Learn and Compare. With AutoBuzz in Learn mode a “known good” sample PCB is initially scanned to establish a reference connectivity map. Suspected faulty boards can then be scanned by AutoBuzz in Compare mode, and a comparison is automatically made of their connectivity maps. Differences between the two maps are highlighted to indicate possible faults such as interconnect short-circuits, open-circuits or “stuck-at” faults. For added reliability and reproducibility a constraints section allows critical pins to be set at fixed drive values as “guards.” Since the user requires no boundary-scan technical knowledge and with only a basic scan chain input needed, AutoBuzz is expected to find favor in repair and service centers as well as other debug arenas. Supported interfaces currently include Altera’s USB Blaster, Xilinx’s parallel III/IV and USB interfaces, JTAG Technologies’ JT 3705 / USB controller, JTAGLive dedicated USB controller and some FTDI-based modules. About JTAG Technologies, Easton, MD. (410) 770-4415. [].




Secure RFID Keys Feature 13.56MHz Interface for Access Control, e-Cash and ID Cards

A new line of RFID keys and cards is designed for the two-billion-units-per-year automatic identification, access control and electronic cash (e-cash) markets. This new contactless RFID product family, the MAX66000/020/040/100/120/140 from Maxim Integrated Products, leverages the expertise utilized in the company’s 1-Wire secure authentication ICs, which protect intellectual property in embedded systems. With a 13.56 MHz interface, these secure keys are positioned to gain market share because 13.56 MHz is becoming the worldwide standard for access control and e-payment applications. Some regions of the world have already begun deploying this RFID technology for passport and national ID cards. Maxim’s new RF devices are packaged in a laminated plastic key fob or ISO thin card format and are available in either the ISO 14443B or ISO 15693 HF protocol. Each protocol family offers three products: 64-bit ROM ID only, ROM ID plus 1K-bit EEPROM, or ROM ID plus 1K-bit EEPROM and SHA-1 authentication. Custom form factors are also available. The MAX66040 and MAX66140 employ the secure hash algorithm (SHA-1), a proven technology designed by the NSA for protecting a system’s critical data without using expensive encryption techniques or an untested, proprietary protocol. SHA-1 is an ISO standard that is publicly available and has been thoroughly tested in the marketplace. It is designed to maintain the integrity of the stored data so that one can verify the authenticity of any credential. Maxim’s RF keys and cards are custom programmable to match the requirements of new and existing tag populations. They work with most 13.56 MHz readers on the market, thus providing an alternative tag source for existing systems.

Trust a world-wide expert for your embedded critical network applications.


More than 3O models... VME, cPCI, VPX

ComEth 4410a

• Data/control Planes 3U VPX switch • Six 4-lanes ports (PCIe x4 Gen 1 & 2) • Up to ten Giga Ethernet Ports


Maxim Integrated Products, +49 89 85 799-561. [].

Intel® & Freescale® processors

Mini-ITX Board Offers Improved HD Audio and Video Performance

MPC8636E processing unit


A next-generation Mini-ITX board features the VIA VX900 MSP and is an upgrade from the VIA EPIA-LN. The VIA EPIA-M720 delivers DDR3 and SATA II support for greater performance, richer digital media and extended connectivity for embedded devices. Combining a VIA 1.0GHz C7 processor with the VIA VX900 unified all-in-one media system processor, the VIA EPIA-M720 delivers a highly optimized platform that boasts comprehensive HD video performance, HD audio and HDMI support in a compact, power-efficient package to meet the broader scope of needs for today’s advanced digital signage, POS, Kiosk, ATM, home automation, healthcare and media client system design applications. Measuring just 17 cm x 17 cm, the VIA EPIA-M720 features the 1.0 GHz VIA C7 processor for fanless configurations with ultra low power requirements. The VIA C7 processor is combined with the VIA VX900 MSP, supporting up to 4 Gbyte of DDR3 1066 DIMM system memory and featuring the VIA ChromotionHD 2.0 video processor. The VIA EPIA-M720 also adds support for Windows 7 and Windows Embedded 7 operating systems. Rear panel I/O includes two PS/2 ports (KB/MS), one HDMI port, one VGA port, one COM port, one Gigabit LAN port, two USB 2.0 ports and three audio jacks. An onboard PCI slot is accompanied with two SATA II connectors, an additional COM port, a further three USB 2.0 pin headers for 6 USB ports (including two optional ports), SPDIF out, one pin header for LPT and an SMBus header.

• 1GB DDR2 • 512KB nvRAM • 128MB Mirror Flash • 4GB SSD • USB2, SATA, RS232, I2C, GPIOs

Communication Platforms

Synch/Async serial ports / LAN


• MPC8536 E • 8 sync/async serial ports • 3 Ethernet ports • One embedded L2/L3 switch with 8 SFP modules

VIA Technologies, Fremont, CA. (510) 683-3300. [].

+33 +33 (0)2 (0)2 98 98 573 573 030 030

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Advanced Micro Devices, Inc...................... 60.......................................... Apacer Memory America, Inc......................

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Cogent Computer Systems, Inc................... 10................................... End of Article Products COM Express & Wireless Network Showcase... 17.................................................................

Elma Electronic, Inc....................................

Get Connected with companies and Extreme Engineering Solutions, Inc.............. 7........................................... products featured in this section. Innovative Integration.................................. 27........................... Interface Concept....................................... LiPPERT Embedded Computers, Inc............ LogicConnected Supply, Inc........................................ 39................................ Get with companies and products featured in section. Measurement Computing Corporation......... MEN Micro, Inc.......................................... 30............................................. MSC Embedded, Inc................................... One Stop Systems, Inc............................... Phoenix International................................... 4..................................... Portwell, Inc............................................... Prism Computer Solutions.......................... 26..................................... RTECC....................................................... 13......................................... Sealevel Systems, Inc.................................. Tech Design Forum..................................... 37...................... The MathWorks, Inc.................................... 2.................................

Sandra Sillion Managing Editor

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Learn more about new levels of performance in a compact BGP package at: © 2011 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, combinations thereof are trademarks of Advanced Micro Devices, Inc. Other names are for informational purposes only and may be trademarks of their respective owners. PID#50599-A.

RTC magazine  

October 2011

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