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The magazine of record for the embedded computing industry

August 2011



Making DSP Work in Real Time Bridging PCIe and Serial RapidIO Making the Most of Multicore An RTC Group Publication

THREE AIRCRAFT, A SINGLE MODEL, AND 80% COMMON CODE. THAT’S MODEL-BASED DESIGN. To develop the unprecedented three-version F-35, engineers at Lockheed Martin created a common system model to simulate the avionics, propulsion, and other systems, and to automatically generate final flight code. The result: reusable designs, rapid implementation, and global teamwork. To learn more, visit

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54 Ethernet Board Enables High-Speed Long Distance Transfer

56 7400 MHz SMT Frequency Synthesizer Featuring Low Phase Noise


59 AdvancedMC Processor Module with Freescale QorIQ P2020



Technology in Context


Embedded Memory System Options

Real-Time DSP

Modules Ease An Integrated Real-Time Platform 6Editorial 18 Downloadable 36 Things in the Cloud Memory Constraints in Small Can Deliver Improved DSP Embedded Systems Performance at Lower Costs Industry Insider 8Latest Developments in the Embedded The Things I Hear: The Engineering Marketplace TECHNOLOGY DEPLOYED 26 to Purchasing Gap in Embedded Memory Selection Small Form Factor Forum Making the Most of Multicore 12The Bad, the Good and the Ugly A Static Analysis Approach 42 to Identifying Defects in Products & Technology TECHNOLOGY CONNECTED Multithreaded, Multicore Designs 54Newest Embedded Technology Used by Industry Leaders PCI Express Meets Serial RapidIO RapidIO Reaches a Building Scalable Network 32 Serial 46 Crossroads with PCIe in IntelProcessing Platforms with EDITOR’S REPORT Based DSP Designs Multicore Processors John A. Carbone, Express Logic

Andy The, IntervalZero

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Embedded Systems in Solar Power


Growth of Solar Power Rides on Embedded Intelligence

Ian Stalker, Curtiss-Wright Controls Embedded Computing, and Devashish Paul, IDT

Tom Williams

Paul Stevens, Advantech

Industry watch Advances in Wireless Connectivity

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Tom Williams Editor-in-Chief

Things in the Cloud


loud computing is one of those things that is becoming “popular” these days. Now when things become popular in the world of technology—as opposed to the world of “pop” culture for instance—there is usually also a technical and economic reason. In addition, as with most popular things, the exact definition of what constitutes cloud computing could best be described as “nebulous.” In this case, however, that means that cloud computing can take many forms depending on the type of application or service, or how it is provided. Basically, however, cloud computing is modeled on the idea that there is a remote server or servers that provide the service of hosting a client’s data and/or applications so the client can avoid the upfront investment in servers. This can help many start-up ventures get off the ground because as the amount of storage and usage grows, the cloud service provider adds more server resources and charges accordingly. Of course, there are many issues with such a model, such as security, availability (will the service provider always be online?), volume of Internet usage as data is sent back and forth to the remote servers, and privacy to mention a few. Cloud services are often hosted on large server farms that are shared by a large number of clients with widely differing needs and applications. In many instances their data is hosted along with their, often proprietary, applications on the cloud servers. Of course, this makes it convenient for remote and mobile users to take advantage of the service wherever they are, but it also brings up problems with security and other matters. So there are quite a few decisions a potential user must make when contracting for a cloud computing service—which brings us to the Internet of Things. With the ever-growing number of devices that are connected to the Internet, the issues of managing them are growing as well, as is the question of the role of cloud computing involving large numbers of often relatively simple devices. Remote management of embedded systems has long been attractive because of the potential savings in terms of service calls and the ability to do things like large scale updates from a remote site. Often the management strategy will depend on the number and complexity of the systems involved.



For example, if you are managing 100 remote pumping installations, it might make sense to have each one with an embedded web page that could be individually called up for monitoring, diagnostics and upgrades and that could also autonomously send data and alerts as needed. Managing such a small number of sites in a cloud computing model might not be the most attractive scenario. However, when the picture changes to managing 10,000 relatively simple devices like vending machines, things can look entirely different. In such a scenario, each machine still has a connection to the Internet, but we have a large number of devices dealing with relatively small amounts of data each. There is still a need for two-way communication but it must now be via a large database on a server rather than directly with actual users or service personnel. To be sure, service personnel are still involved but seldom interact with the individual devices. An application can be used to sweep up all the data and present it in any way desired for things like routing delivery and service vehicles or ordering more product to fill the machines. The application can be hosted on the cloud server or on machines at the user’s site. The advantage of reducing the investment in server hardware remains. There is also a rather intriguing possible advantage in terms of security. Something as simple as a vending machine or a remote sensor may only send data infrequently and then perhaps only a packet or two at a time. If such data needs to be confidential, the actual meaning of the data in the packet can be secured by the application. The bit fields in the packet are not identified in the packet. They are simply written to by the device and read by the application. Thus the actual fields representing things like device ID, time, amount deposit, number of Jolt Colas, Mountain Dews, etc., are only known at the end of the network, not within the cloud. This, of course, depends on the application not being hosted in the cloud as well. As intelligent devices connected to the Internet and to private networks proliferate, the data they generate will grow at many times that rate and require huge amounts of storage and connectivity to manage. The emergence of the cloud model to accommodate such growth will become more attractive as ideas that begin as relatively small applications grow to very large ones.




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INSIDER AUGUST 2011 Intel to Acquire Fulcrum Microsystems Intel Corporation has announced it signed a definitive agreement to acquire Fulcrum Microsystems, a privately held fabless semiconductor company that designs Ethernet switch silicon for data center network providers. 10 Gigabit Ethernet (10GbE) networks are one of the fastestgrowing market segments in the data center today. As demand for data continues to increase, there is a growing need for high-performance, lowlatency network switches to support evolving cloud architectures and the growth of converged networks in the enterprise. Fulcrum Microsystems designs integrated, standards-based 10GbE and 40 Gigabit Ethernet (40GbE) switch silicon that have low latency and workload balancing capabilities while helping provide superior network speeds. Cloud computing is driving the convergence of server, storage and network technologies and solutions based around Intel Xeon processor solutions. IP Data Center customers need faster and more flexible networking solutions. The acquisition will fulfill an important component in Intel’s strategy to deliver comprehensive data center building blocks, from server processors and technologies to storage and networking. Founded in 1999, Fulcrum Microsystems is based in Calabasas, California. Additional terms of the transaction were not disclosed. The agreement is subject to the approval of Fulcrum Microsystems shareholders, regulatory approval and satisfaction of customary closing conditions. It is expected to close in the third quarter of 2011.

Maxim Acquires SensorDynamics, Developer of Sensor and MEMS Solutions

Maxim Integrated Products has announced it has acquired SensorDynamics, a privately held semiconductor company that develops proprietary sensor and microelectromechanical (MEMS) solutions. SensorDynamics is based in Lebring, near Graz, Austria. SensorDynamics holds numerous original patents for MEMS sensor technology. It has devoted over 800 man-years of research and development to the high-growth fields of MEMS sensors and associated low power interface and wireless connectivity solutions. Consequently, this acquisition enables Maxim to accelerate expansion in markets where it already has a strong presence including automotive and



high-end consumer. In the near term, this acquisition enables SensorDynamics to focus on its strength in engineering for sensors and MEMS, while utilizing Maxim’s considerable manufacturing, distribution and sales infrastructure. This will quickly make the combined company a leading competitor in the inertial sensor, wireless connectivity and sensor interface markets.

Consortium of Companies to Offer Turnkey Imaging Solutions

A new alliance named Technology United, dedicated to advancing the state of the art in enterprise print/imaging technology, including IT security, automation and supply chain management, has been initiated by a small group of cofounding companies.

The founding members of the alliance include Intel, Green Hills Software, MWA Intelligence, Genius Bytes, NewField IT, RIM, US Fleet Tracking, Spline Network, ESP, Compass Sales Solutions and Barrister. Technology United’s best-of-breed solutions are intended to leverage the power of technology to offer a superior level of efficiency and quality. The imaging channel around the world is in need of a seamless and fully integrated enterprise capable of dramatic improvement in supply chain operation. This new alliance is designed to recognize and deliver the solutions for supply chain automation; intelligent procurement of machines, parts and hardware; implement a world-class level of security; leading-edge field service mobility; scheduling optimization; service call avoidance; and a long list of advanced document management tools. Technology United is a powerful force dedicated to delivering what the worldwide market is demanding for growth in the MPS and e-commerce marketplaces. “Modern imaging systems are increasingly sophisticated, controlled by powerful computers and connected to the IT infrastructure, yet the security impact within the enterprise has been largely ignored,” said Gordon Jones, vice president and general manager of Green Hills Software’s Integrity Secure Virtualization business unit.

CAN in Automation Seeks to Develop Framework Based on IEC 61499

The nonprofit CAN in Automation (CiA) group has established the CANopen Special Interest Group (SIG) “IEC 61499.” The group’s scope is the development of a framework specifica-

tion for CANopen-based systems using an IEC 61499-compliant programming environment. During the inaugural meeting the experts from Epis, Isagraph, NXP Control and Weidmüller agreed to provide a very first proposal at the SPS/IPC/Drives exhibition in November. It is intended to support a migration path from IEC 61131-based decentralized control systems to distributed control systems using IEC 61499 function blocks. A function block in the IEC 61499 standard is the basic building block from which entire applications may be built. There are two types of function blocks: basic function blocks and composite function blocks. A composite function block contains other composite function blocks and/or basic function blocks. A basic function block contains algorithms and an execution control chart (ECC). Each function block has event inputs and outputs as well as data inputs and outputs. In a basic function block the execution of an algorithm is triggered by the occurrence of an input event. The executed algorithm then from the input data produces new output data. When the algorithm has finished executing an output event is generated. This output event might then be the input event to another function block. CANopen comprises the application layer protocol (EN 50325-4) and profile specifications defining a list of parameters (process and configuration data as well as diagnostic information). CANopen is based on the CAN (Controller Area Network) protocol, internationally standardized in the ISO 11898 series. CAN and CANopen are designed for distributed control systems.

NetLogic and EZchip Collaborate on Packet Processing for Terabit Class Systems

NetLogic Microsystems and EZchip Semiconductor have announced that they are collaborating to deliver high-performance, merchant, packet-processing solutions for IPv6-ready Terabit class systems. By optimizing and implementing exclusive operational modes in both EZchip’s NP-4 100

Gbit/s network processor (NPU) and NetLogic Microsystems’ NL11k knowledge-based processor, the companies are enabling customers to achieve enhanced performance and functionality when using both the processors together when compared to alternative solutions. The companies have achieved broad design success across leading Tier One OEMs adopting the 100G NP-4 NPU and the industry-leading NL11k knowledge-based proces-

sor. In addition, the companies are collaborating to further enhance the performance optimizations and tight coupling between EZchip’s next-generation NP-5 200 Gbit/s NPU and NetLogic Microsystems’ next-generation of knowledge-based processors at the 28 nm node. The ever-increasing demand for network bandwidth and for smarter networks is continuously driving OEMs to look for solutions that offer faster and more

extensive packet processing. Additionally, the depletion of IPv4 addresses is further stressing the Internet and is forcing the migration to IPv6 Internet addresses, which require 5x the processing capability compared to IPv4 packets. Moreover, the growing requirement for deep-packet inspection throughout the network is driving an unprecedented need for knowledge-based processors with significantly higher performance and database capacity.

734.64 (-2.21%) This data is as of August 9, 2011. To follow the RTEC10 Index in real time, visit COMPANY






Adlink Technology












Concurrent Computer

















Interphase Corporation

















Elma Electronic

Mercury Computer Systems -

Performance Technologies






PLX Technology






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Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTC MAGAZINE AUGUST 2011



New Study Finds Strong NAND Threat to PC DRAM Growth

The DRAM industry faces NAND as a serious threat in its largest market. That’s the conclusion of a study just released by Objective Analysis after reviewing a series of nearly 300 PC benchmarks. “We looked at the performance of industry-standard benchmarks in PCs with a range of DRAM and NAND configurations, and were rather surprised to find that even today a dollar’s worth of NAND improves PC performance more than does a dollar’s worth of DRAM,” commented Jim Handy, the author of the study. “Over time the price/ performance gap between these two technologies will widen, driving NAND to become the memory of choice in the PC. Once OEMs and end users discover this fact, PC DRAM capacities will stop growing.” This will lead to continuing declines in DRAM revenues, faster DRAM market consolidation, and the eventual rise of a fabless DRAM market. The study bolsters findings by several university researchers and data center managers that NAND is more likely to displace a computer’s DRAM than its HDDs. “An appropriate balance of NAND, DRAM, and an HDD yields superior performance per dollar to a simple DRAM/HDD system,” commented Handy. “A well-designed NAND/DRAM combination brings SSD-like performance to a system at little or no price increase over a standard system based on the conventional DRAM-plus-HDD platform.” The study: “How PC NAND Will Undermine DRAM” includes 50 figures to graphically depict the nature of the NAND/DRAM trade-off and forecasts based on this information illustrating its impact upon both the DRAM and NAND markets. This study can be ordered on-line on the Objective Analysis website at www. Objective-Analysis .com.



Smart Meter Penetration in Europe Predicted to Reach 52 Percent by 2016

According to a new research report from the analyst firm Berg Insight, the installed base of smart electricity meters in Europe will grow at a compound annual growth rate of 19.4 percent between 2010 and 2016 to reach 130.5 million at the end of the period. Annual investments in smart metering technology are forecasted to exceed €3 billion by the mid-2010s. Smart meters help consumers better manage their energy usage and create financial incentives for energy savings. Moreover, they constitute the core building blocks in future smart grids that will support electric vehicle charging, renewable micro-generation and advanced energy conservation. Following major rollouts in Italy and the Nordic region, smart meters are now being introduced on a massive scale in Spain, France and the UK. “Endesa has commenced with a rollout to 12.9 million customers in Spain, and the second largest electricity network operator Iberdrola will follow,” said Tobias Ryberg, senior analyst, Berg Insight. “ERDF is awaiting formal approval from the government for a nationwide rollout to 33 million customers in France, and in the UK the leading energy suppliers British Gas and E.ON have committed to the deployment of several million smart meters prior to the start of a mass rollout in 2014. By that time there will also be massive installations in additional countries such as the Netherlands, Ireland and Norway.”

EVENT CALENDAR August 25, 2011

Real-Time & Embedded Computing Conference San Diego, CA

August 25, 2011

MEDS-Medical Electronic Device Solutions Conference San Diego, CA

September 13, 2011

Real-Time & Embedded Computing Conference Ottawa, ON

September 13, 2011

TI Technology Days Boston, MA

September 15, 2011

Real-Time & Embedded Computing Conference Montreal, QC

September 13-15, 2011

Intel Developers Forum San Francisco, CA

September 26-29, 2011

Embedded Systems Conference Boston, MA

October 11, 2011

Real-Time & Embedded Computing Conference Portland, OR

October 13, 2011

Real-Time & Embedded Computing Conference Seattle, WA

October 16-19, 2011

GEOINT 2011 Symposium San Antonio, TX

October 28, 2011

Real-Time & Embedded Computing Conference Toronto, ON Canada

October 31, 2011

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X-ES 2nd Generation Intel® Core™ i7 Processor Solutions: Delivering Innovation In 2010, Extreme Engineering Solutions, Inc. (X-ES) developed more Intel® Core™ i7 processor products based on VPX, CompactPCI, VME, CompactPCI Express, and XMC form factors than anyone in the industry. This year, X-ES has added solutions based on the 2nd generation Intel Core i7 processor. Providing products customers want, when they want them – that truly is innovation that performs. X-ES offers an extensive product portfolio that includes commercial and ruggedized single board computers, high-performance processor modules, multipurpose I/O modules, storage, backplanes, enclosures, and fully integrated systems. 2nd generation Intel Core i7 processor solutions available in a variety of form factors. Call or visit our website today.



Colin McCracken & Paul Rosenfeld

The Bad, the Good and the Ugly


e’ve written before to complain, if you will, about how difficult it is to gather investment capital to address the SFF board market. A lack of inventive start-ups to address this market is only part of the problem. Large companies serving commercial (consumer) markets are still not investing in innovative product solutions designed specifically for the SFF industrial market. SFF board and system designers still must utilize hand-me-down components designed for other market segments in embedded systems applications. With the SFF boards and subsystems market passing the 1 million unit per year shipment level during the last several years, and the dollar volume approaching the $1 billion level, this market deserves more attention. What’s wrong? TTM, which in this case means time-to-money, is the culprit. From the time of first availability of a new SFF board product, a supplier is faced with a long lead time to reach volume shipments. Once an OEM has made a board selection for an embedded system application, the OEM must complete their own development process, including software, enclosures, system integration, testing and documentation—a cycle that can take 12 to 18 months or longer. If certification is required, such as FDA or FAA, the timing can stretch even longer, to three years or more. Not long ago, a medical systems company bought a number of design kits, and placed a large production order seven years later—about a year after the product they had designed in went EOL and component availability dried up. The only way to satisfy their needs was to scour the globe for all remaining components that were available to make these boards. Once the OEM has introduced their product to the market, that product itself has its own ramp rate to full production volumes. So the bad news from a TTM standpoint is that a total cycle for a new SFF product to reach volume production can easily take three years or more. Not to mention the system OEM who, in the midst of the design process, decides that the proposed product is not competitive, or fails to meet market requirements, and simply drops the whole thing or redesigns with another, newer SFF solution.



The good news is that once in full production, SFF products can stay in volume production for many years. There are SFF products in volume production today that were first shipped in the early 1990s—almost 20 years earlier. This “annuity,” if you will, constitutes the vast bulk of the profits in the SFF board community. If you are a component supplier to SFF board companies, TTM truly gets ugly. Another development cycle, that of the SFF board company itself, gets tacked on. So component suppliers (processors, peripheral components, memory modules, etc.) get a “design win” from an SFF board company, wait 9-12 months for the board design to complete, ship 25 to 50 units for a first production run, wait for a system OEM to make a design commitment, wait another 12 to 18 months (best case) for the system OEM to complete their product design, sell a few additional units for an initial production run, and then and only then see volume finally start to ramp as the OEM system begins to sell. For a sure-fire winner, SFF component suppliers might wait three years. It might take five or more years for it to become clear that the product missed the boat. It takes an investor and company management with patience and confidence in their decisions to wait it out and reap the benefits. In our short-term, results-oriented financial environment, there are precious few investors and companies willing to place a bet with a payback that long. Intel, one of the leading component suppliers to this market, hasn’t invested in a new product designed specifically for the SFF board market in almost 20 years (remember the 386SX). Processors designed for tablets and cell phones, with many of the same requirements, continue to be adapted by SFF designers to their specific application requirements. It’s time for big component suppliers who seek a piece of the SFF pie to stop paying lip service to this segment. Get over the short-term performance mentality and establish internal organizations that operate by a different set of financial rules with the freedom to invest for the long term in SFF products. Those who do will reap the benefits 5, 10 or even 15 years down the road.

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editor’s report Embedded Systems in Solar Power

Growth of Solar Power Rides on Embedded Intelligence Counter to many predictions, the outlook for solar energy growth in the U.S. is fairly bright. Much of the optimism comes from the progress toward getting costs in line with other sources of power. And a good deal of it comes from the use of embedded systems to make installation, configuration and control of such systems straightforward. by Tom Williams, Editor-in-Chief


There has been a simmering debate he growth of the solar photovoltaic in the solar energy industry about whether renewable energy industry in the it is better to concentrate on building vast United States is looking to have arrays of solar panels in places like the positive news for the spread of embedded Mojave desert or rather to concentrate on systems. This may seem counterintuitive widely distributed systems of panels on given the somber news of budget woes individual rooftops that can connect to and the cutback of government support the grid and take off power and put it back for development of renewable energies. However, a recent Intersolar conference on the grid as needed. While a number nies providing solutions now had a definitely upbeat of large plants have been built and other in San Francisco ion into products, technologies and companies. Whether your goal is to research the latestprojects are underway, there atmosphere with a number of companies ambitious ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you has been a surge in the popularity of panfrom Europe (primarily from Germany) you require for whatever type of technology, els being installed on the roofs of private plans and productsannouncing you are searching for. to set up shop in the homes, small businesses and civic buildU.S., and numerous U.S. companies movings such as San Francisco’s Moscone ing aggressively into the residence and convention center. small business markets. This development In fact, the city of San Francisco has bodes well for the proliferation of invertjust announced a program called Solar@ ers, micro inverters, maximizers, gateways Work that will offer solar energy systems and monitoring systems and software—all to businesses in the Bay Area via a group of which are designed and built around purchase model. The program aims to microprocessors and embedded computer intelligence. make it possible for small and mid-sized businesses to pay less for solar energy than they pay for electricity from the grid without local rebates. Estimates are that interGet Connected ested participants will be able to purchase with companies mentioned in this article. more than two megawatts of solar power

End of Article



Get Connected with companies mentioned in this article.

over about six months. The city’s stated goal is to be able to meet its electricity needs with 100% renewable energy. This is partially made feasible by the fact that, according to European Sales VP Bernd Kohlstruck of Enecsys, solar energy is beginning to approach parity with electricity from other sources. In addition, Joe Cunningham, director of operations for CentroSolar, was asked the question of how the industry can be looking so optimistic in the face of apparent disappointing government support. He replied that people are now generally becoming aware that solar power may be more economic. Also, a number of companies are coming up with creative financing/leasing schemes that let people set up solar installations on their homes for no money up front and with terms that let them pay for equipment at rates that come out significantly lower than their monthly energy bill, and at the end let them own the equipment free and clear. The most basic solar installation is made up of the solar panels, which collect the solar energy and convert it into DC current, and an inverter, which converts the DC to AC and connects to the grid. There must be intelligence to interface to the grid so that the meter can be run forward and in reverse. But for the new systems now being offered to residential users and small to medium businesses, there are a lot more refinements coming into play that involve safety, monitoring, maintenance, ease of installation and use, and efficiency. For example, the simplest way to set up a solar array has been to connect a string of panels in series, which deliver the cumulative DC current at a constant voltage to the inverter, which then converts it to AC and connects to the grid. The problem with this is that one weakened panel in the string or one blocked by shade or some obstruction like a stray Frisbee can limit output of the entire string. One approach to this has been to use DC-to-Dc converters or “power optimizers” connected to each module to reduce losses due to differences between the modules’ outputs. The output of each module is combined

editor’s report

with that of the other modules and the final output sent to the inverter. This keeps one bad module from excessively bringing down the output of the whole string. Another approach to this is via a patented method from Tigo Energy, which uses units called “maximizers” along with an intelligent Energy Management Maximizer Unit (MMU) to sense the input parameters of each module and with its central processor to calculate the I-V properties of each module. It can then use circuitry consisting of an FET and a capacitor in each maximizer to adjust a nonresistive impedance to match the internal impedance of the preceding module such that a virtual “current tunnel” is created to let each module contribute its maximum output. This method also reduces the heat generated by an underperforming module, which could damage the system (Figure 1). The intelligence of each maximizer unit is also used to read the performance of each panel in the array on the Tigo monitoring system software. Another method of minimizing the effects of a shaded or malfunctioning panel is the growing use of microinverters. Microinverters attach to each solar panel producing an output of 120V or 240V AC at 50 Hz and are then are connected in parallel to the grid. Thus a low output from one panel simply contributes that low output to the total but does not impair the output of other panels in the array (Figure 2). One supplier of microinverters, Enecsys, has also built in safety features as well as the ability to monitor the installation. The Enecsys microinverters have two shutdown modes—one thermal in case of overheating and the other that shuts down if the grid is disconnected. This latter mode is important for things like protecting firefighters. If the microinverters were to continue to operate, their AC output would be present on all the lines between the inverters and the disconnect switch with the attendant hazards to firefighters. With shutdown, the only voltage present is the DC voltage between the panels and the inverters. The Enecsys modules also commu-

Tigo Energy Module Maximizer at each PV Module

Tigo Energy MaxiManager Software Suite for Monitoring & Advanced Managment Internet


Tigo Energy Maximizer Management Unit


Figure 1 The Tigo Energy Maximizer system senses the input parameters in each module and collectgs voltage, current and temperature for each module. It uses this information to select the proper impedance for the optimal current flow between modules.

120/240V ac 50/60 hz

Solar pv modules connected in series

Electricity String or central grid inverter

Solar pv modules connected in parallel

Enecsys micro-inverters

120/240V ac 50/60 hz Electricity grid

Figure 2 Using panels with microinverters connected in parallel, it is possible to avoid the “domino effect” of one underperforming panel in a series connection negatively impacting the outputs of the other panels.

nicate via a ZigBee wireless connection with a gateway that can connect in the home to the Internet and an in-home monitor (Figure 3). This makes data available to the user in terms of things like carbon footprint, rate savings, etc., and also can be accessed by service personnel for diagnostics and trouble shooting. While photovoltaic systems probably first came into widespread use by people who wanted to live entirely off the grid, the expected large commercial use will definitely be in grid-tied systems. Still, there are some who will want grid-interactive systems that also supply battery backup. Here again, intelligent embedded systems will be able to support battery backup as

well. In systems such as those supplied by Outback Power, the grid-interactive system supplies power while taking extra needed off the grid and selling excess back onto the grid. At the same time, however, it is also maintaining a charge on a bank of batteries that can be brought online and used to produce AC when the grid goes down (Figure 4). Such a system can also incorporate a generator that can be automatically started under preprogrammed conditions. Outback Power supplies an intelligent system display and controller, the MATE3, that can connect both to the Internet and to a local PC. The MATE3 supports up to one year of data logging and supports sysRTC MAGAZINE AUGUST 2011


editor’s report


Figure 3 User interfaces such as this one from Enecsys allow the homeowner as well as online support personnel to log and monitor system operation and performance and to carry out maintenance and troubleshooting operations.

Main Power Panel


Main Loads


• Grid Initially Charges Batteries • Grid and PV Power Loads During Day • Excess PV Power Sold to Grid • Batteries Power B/U Loads When Grid Fails







CentroSolar Scottsdale, AZ. (480) 348-2555. [].

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Figure 4 The grid-interactive systems from Outback power allow the incorporation of battery and generator backup to a solar PV system tied to the grid. Should the grid go down, batteries and/or the generator can be used to continue power to selected circuits.

tem configuration through a configuration wizard. For instance, the system can be set to work with time-of-day power rates and to program inverter and charger operations such as limiting the generator to running at specific times of day. The Internet connection also permits remote monitoring and allows online support personnel to run diagnostics. With the Outback system it is also possible to separate selected circuits for backup and save power by not running less critical circuits. Of course, such things as monitor



In fact, we are beginning to see some companies, such as miniJoule, a subsidiary of the German company GP Joule, that are about to enter the U.S. market with what can be called a do-it-yourself solar power kit. The kit comes in a box with solar panel, micro inverter, roof mounting bracket and cables. The user simply unpacks the parts, mounts them on the roof and connects the cables—up to the part where they connect to the grid. At that point, a licensed electrician and a permit and inspection from the utility are required. A 185-watt kit will sell for about $1,000 and they can of course be set up in multiples of up to 16 panels per string. Such kits combined with financial packages that lower effective monthly rates, municipal initiatives like Solar@ Work, and other incentives will soon replace things like tax rebates. But above all, the role of embedded systems will continue to drive this market. There are opportunities aplenty for semiconductor companies, software developers and system integrators to expand and exploit this trend.

gateways depend on data flowing throughout the entire photovoltaic systems from panels to the Internet. Thus all the components require some level of intelligence and connectivity, often wireless, such as ZigBee. The system monitoring, control and diagnostic systems are becoming ever more sophisticated. One of the virtues of embedded control is that it tends to hide very complex matters behind a relatively simple and straightforward user interface. And it is this ability that makes such systems accessible to a broader range of us-

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Embedded Memory System Options

Downloadable Modules Ease Memory Constraints in Small Embedded Systems Concern over physical size, power consumption and battery life place constraints on memory in deeply embedded systems. These constraints can be eased by using techniques commonly found in large systems but not often seen in small RTOSs. by John A. Carbone, Express Logic


mbedded systems have always found themselves between a rock and a hard place with regard to the amount Application Program of memory available for their software and data. More is always desirable, based on the benefits to functionality, capacity API and redundancy, yet at the same time undesirable because of the impact to size, power, heat and cost. Over time, various RTOS Services compromises and advances in technology have changed the picture somewhat, Threads, Queues, Semaphores, Mutexes, nies providing now but solutions there has constantly been this tension Timers, Memory Mangement, Scheduler, ion into products, andalways companies. your goal is to research the latest that technologies will likely beWhether a limiting facInterrupts, Device Drivers, Initialization, ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you tor. After all, Parkinson’s Law tells us that Instrumentation you require for whatever type of technology, demand and productsmemory you are searching for. will expand to exhaust available capacity. More memory leads to more demand; hence, we’ll always want to stuff more into a system, no matter what the memory limit might be. Figure 1 Back in the early 1970s, I worked on the Airborne Warning and Control SysMost small RTOSs operate as functions linked with application code into a tem (AWACS) communications subsyssingle executable file. tem, an early embedded system based on an IBM 4-pi/ CP-2 processor that used a team’s programming was done in assem- limit, there were severe constraints on resounding 8 Kbyte of memory! All our bly language, cross assembled on a DEC how the system was designed, what funcPDP-8i, then downloaded into the CP-2’s tionality was included, and how it was core memory via a monstrosity called programmed. We squeezed every inGet Connected a field operating unit (FOU). Since the struction out of our code, spending days with companies mentioned in this article. system had to operate within the 8 Kbyte to trim a few bytes—because we had to.

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technology in context





Operating System

Figure 2 A large RTOS, like a desktop OS, is structured as a stand-alone kernel and independent application executables that access it through a trap interface.

Application • Load parameters • Load code for function • Trap to the kernel Trap

R e t u r n


Call Handler Service Operating System

Figure 3 A trap mechanism can be used to enable code outside the kernel to communicate with it.

We’d have been delirious with even another 8 Kbyte! As memory constraints have diminished, I often imagine how we would have reacted to the availability of a megabyte. Today, by contrast, we have megabytes in many embedded systems, although some still struggle with less. While today’s systems are not quite as limited as 8 Kbyte to be sure, some applications that are particularly sensitive to the same constraints



that existed in the 1970s—cost, space and power—may only have perhaps 64 Kbyte to 256 Kbyte. Regardless of the improved memory resources, embedded systems never have enough memory, whether it’s due to available technology or size/cost/ power constraints. To meet system functionality requirements, while remaining within the limits of memory availability, embedded developers from time to time borrow big

system features to better handle certain situations. Again glancing back to the mainframe days of the 1970s, available memory could be used more efficiently if it were “time shared” among various pieces of independent code. These code sections were called “overlays,” and they were loaded into memory on demand from mass storage, overlaying previously resident code. Of course, this introduced significant overhead, but it was a very effective approach for mainframe systems where such overhead was relatively harmless. With this method, you could introduce virtually unlimited functionality, structured as a set of overlays, without expanding physical memory at all. A modern technique for functional expansion has worked its way into everyday life through the “app.” An app, or application, is structured in a manner that allows it to be loaded onto a running system. When a system must be updated without removal from service, an app can be downloaded into the system, adding to the memory-resident code that can be run at any time. Both the overlay and app can be leveraged to give embedded systems a boost in meeting the constraints of a memory system that’s just not as big as developers want. In fact, they can be blended in a manner that suits embedded systems quite well, and provides some measure of relief from memory constraints.

Modern Embedded Systems Are Still Memory Constrained

Many of today’s embedded systems used in consumer, medical and industrial applications face memory constraints similar to that early AWACS system and many embedded systems since then. These systems run with a real-time operating system (RTOS), and often with relatively small amounts of memory. RTOSs come in all sizes and flavors, from the large (256 Kbyte - 1 Mbyte), like Wind River’s VxWorks, to the supercompact (under 10 Kbyte), like Express Logic’s ThreadX. Large RTOSs offer many features adapted from desktop systems that are typically not available in the super-small RTOSs because such features require a larger amount of code, and result in a slower real-time response. The small

technology in context

RTOS generally operates as a library of services, linked with the application into a single executable file (Figure 1). The application references the services it needs through an API. A small RTOS can provide these services with low overhead and in a small memory footprint, often less than 20 Kbyte. This single executable file is efficient in both time and space since all of the code is statically linked. But it lacks flexibility since any changes to the application or RTOS require rebuilding, relinking, and a redownload/flash of the new image in its entirety. In contrast, desktop operating systems such as Windows and Linux, and large RTOSs, such as VxWorks, have two-piece “OS/Application” architectures (Figure 2) where target memory is allocated for the OS, and additional memory is allocated for each application that is to be run with the OS, usually as needed. In this architecture there is a resident kernel containing all the OS services available to applications, all linked into a distinct, memory-resident executable. This kernel executable boots the system and runs continuously, providing a foundation for applications that are loaded and run in dynamically allocated memory. Often in these systems, a virtual memory architecture provides demand paging to and from mass storage on desktop systems or multi-user separation in embedded systems. Virtual memory also can enable use of non-contiguous memory fragments that otherwise might grow over time and reduce or exhaust available memory. Applications that are not linked with the RTOS must use a different means of accessing RTOS services from the one used by functions within a statically linked executable. This alternate access is necessary because the application is developed independently of a particular hardware environment, and simply cannot predict the memory address of the OS service routine they wish to use. In most cases, these applications access the required OS service routines via a “trap” mechanism that does not require the calling program to be linked with the service it calls (Figure 3). A trap is a software interrupt that can be used to catch errors before they propagate or to stop the system if it is impos-

Application Thread 1 Application Thread 2 Application Thread 3

.. . Application Thread “n”

Module Manager Interface

Figure 4 Downloadable application modules are executable files containing one to many application threads, with an interface mechanism for accessing kernel services.

Module 1

Module 2

Module n

Application Thread 1

Application Thread 1

Application Thread 1

Application Thread 2

Application Thread 2

Application Thread 2

Application Thread 3

Application Thread 3

Application Thread 3

Application Thread......

Application Thread......

Application Thread......

Application Thread “n”

Application Thread “n”

Application Thread “n”




Interface Application Code

Module Manager

ThreadX Kernel Kernel Executable Figure 5 Critical applications can be linked with the kernel while others reside in separate modules.



technology in context

sible to perform a requested operation. A divide by zero or the loading of unaligned data illustrate possible illegal operations that might create a trap and activate a trap handler. Similarly, an intentional trap can be generated through an instruction such as a software interrupt or “swi” instruction, and used to communicate between non-linked program elements. The trap process requires interrupt servicing, processing, a function call, and then the same in reverse. For a desktop or large RTOS, this overhead is insignificant given the relatively lengthy response time expected of such systems. But for a small RTOS used in hard real-time, deeply embedded applications, low overhead response is essential.

Bringing Dynamic Memory Use to the Small Footprint RTOS

To provide the ability to add functionality dynamically, an “application module” structure can be used (Figure 4). An application module is a collection of one or more application threads, not linked with the kernel, but instead built as a separate

executable that can be loaded into target memory when needed, and overwritten when no longer needed—just like an overlay. This approach produces a time shared memory capability that enables system functionality to exceed physical memory. Such modules can be downloaded into memory via a wireless network or local mass storage, like an app. The modules use kernel services via an interface with a module manager, an agent within the kernel image that loads and initializes a module as well as fielding all module requests for RTOS services. The module manager is responsible for allocating memory for a module, loading it via a communications or storage interface, and keeping track of its location in memory. The module manager also informs the module of the addresses of the RTOS routines the module’s application threads need to access, avoiding the need for a trap mechanism, and providing a very efficient calling interface. The module manager also can overwrite one module with another, if vacant memory is not sufficient to hold the new module—much like the

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overlays of old. Threads within modules make RTOS service calls exactly as they would make calls if the service function were directly linked with the application. In the module, however, these calls are handled by an interface component that communicates with the module manager. The trap mechanism is avoided, enabling a low overhead service call interface (Figure 5). Application threads still can be linked with the kernel and reside with the kernel in target memory as part of the RTOS’s executable image. This option enables the system designer to balance the need for minimum overhead with memory conservation, using the more efficient, but more memory hungry approach only where absolutely necessary.

Securing Application Modules

Modules also provide a convenient means for memory to be protected against inadvertent, unintended access. They also enable developers to distinguish between

Module-1 Access Range

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technology in context

more trusted and less trusted modules, applying the appropriate level of protection as demanded by each module. Once a module’s code has been proven to be trusted, for example, it can be given access to the entire system, including hardware control registers, other threads, and the RTOS, without risk. This trust requires extensive testing and perhaps certification as well. For less critical code, a more practical approach might be to allow that code

to access only the memory within its own module and nothing outside. Despite testing, there is risk of accidental stack or memory corruption due to an erroneously calculated pointer, array limit or stack overflow. These faults can be catastrophic and difficult to find, especially if only one portion of the development team is familiar with the offending module. The extreme difficulty in tracing to the source of such errors makes it all

the more important to avoid them. This protects the rest of memory, including other threads and the RTOS, from faults within the un-trusted module code. While all code is tested, a 100% assurance of correctness is expensive and time-consuming. It may be more cost-effective, depending on the code’s function in the system, to simply isolate it from other code just in case it misbehaves. Using the system’s MMU or MPU, memory boundary registers can be set to constrain an un-trusted module’s code to accesses within a given memory region (Figure 6). With boundary register settings, any attempt to access memory locations outside the specified range will result in a trap. In that event, the trap handler can take appropriate action. It can terminate the offending thread, restart it, alert the system, or halt the system, all depending on the criticality of the offending code. The trap also provides excellent debugging information, as it identifies the code making the errant access, allowing it to be fixed. Downloadable application modules enable the RTOS to dynamically load and run additional application threads beyond those linked with the kernel. Applications gain increased functionality without the cost of an increased footprint or additional memory, and while retaining an efficient service call interface. This technique also provides on-demand reconfiguration and updates for deployed systems. Downloadable application module technology ideally suits situations where application code size exceeds available memory, when new modules need to be added after a product is deployed or when partial firmware updates are required. Another advantage of downloading separate application modules is that each module can be more readily developed by its own team or individual programmer. Each team can then focus on one aspect of a product’s functionality, without having to be concerned with other details. Express Logic San Diego, CA. (858) 613-6640.].


Untitled-7 1


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Embedded Memory System Options

The Things I Hear: The Engineering to Purchasing Gap in Embedded Memory Selection Look beyond reference designs and marketing materials. Some time spent studying data sheets and exploring less well-known manufacturers and then communicating this information to your purchasing department can go a long way toward cost savings and longer life for your design project. by Nicholas Urbano, Memphis Electronic


s the lead engineer on your latest problem, plug the hole or bridge the gap. Me? I’m on the receiving end of the project, you’ve chosen your memofrantic calls—listening to each request, ry, finished your design, and sent it identifying the parameters of the specific on to the next phase of development. Then application, and working to understand one Friday afternoon, the phone rings. the concerns of each engineer. I typically It’s someone in a purchasing department, advise on embedded solutions covering a either half a continent away or just down wide range of applications—medical, inthe hall. The problem? The memory you frastructure, aerospace, networking, autodesigned, be it 2 months or 2 years ago, is EOL. You scramble to find replacements, motive, civilian, military and everything only to discover that the pin out has been in between. My job is to work with the nies providing solutions nowthere is no recommended engineer to identify the best solutions, but discontinued, ion into products, technologies and companies. Whether your goal is to research latest to provide confidence replacement from the original manufac- moretheimportantly, ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in the sustainability of a design. turer, and despite your consumption of you require for whatever type of technology, So this is about the things I hear and productsten you thousand are searchingunits for. per month (or more!), each week. After more than a decade in there is nothing you can do but re-spin the this industry, I have gained a considerable board … immediately. amount of insight from the engineers I There goes your weekend. work with on a daily basis. Because each This scenario plays itself out someproject is so unique, I often can’t generalwhere on the globe every week. It costs your company valuable resources and ize the nature of questions from projectcosts our industry hundreds of millions to-project. These are some of the most of dollars each month. Of course, it also common inquiries and situations I’ve brings stress, frustration and internal com- been presented with, especially in the last pany strife while everyone tries to solve a year. And most importantly, these are the things I have to understand to ensure that I can provide you confidence in your deGet Connected sign. with companies mentioned in this article.

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Get Connected with companies mentioned in this article.

Should I Commit to DDR2 or DDR3?

The most common question I have received from engineers in the past year is whether to commit to DDR2 or DDR3 for long-term projects. With the influx of processors supporting DDR2 and/or DDR3 interfaces, the answer isn’t cut and dried and requires a bit of background knowledge. First, it is important to understand that memory is a commodity in the electronics industry. Many manufacturers make their version of the same product. However, each manufacturer has its advantages and specialties. If you know the niche that each manufacturer occupies, you can leverage this knowledge for your benefit. Secondly, consider the history of DRAM. Over the past fifteen years, we’ve gone from Asynchronous to Fast Page and EDO to SDRAM, and DDR through DDR2 to DDR3. While FPM and EDO DRAM have become all but extinct (there are still some suppliers that support both!), SDR still remains in heavy usage in applications all over the world. The key to its success has been that engineers working

technology in context

that in designing with DDR3 now, your embedded applications will not be in full consumption for several quarters. DDR3 will continue to be dominated by consumer applications. Stick with the most common densities, but don’t limit yourself to specialty CL callouts and configurations. 2 Gbit and 4 Gbit DDR3 in x8s and x16s will be safe to design with for the long term.

It’s Not in the Reference Design!

Figure 1 Data sheets may be many and unexciting, but they contain important details, which, when carefully compared to the requirements of your design, can result in significant savings. These details must be clearly communicated to purchasing.

on applications utilizing SDR allowed for increased densities. In fact, only now are we starting to see concerns about the continued support of lower-density 64 Mbit SDR in the long term. Fast forward to 2011; the industry has moved from DDR2 to DDR3 as the primary DRAM device in PCs, with the bulk of consumer applications soon to follow. However, we all know too well that embedded designs don’t always follow at the pace of the consumer. So what to do and what can we learn from SDR? Positively, most major memory categories introduced since SDR in the last decade are still active and in production in common configurations and densities, and that trend will continue. As long as you choose a common configuration and are flexible with your choice of manufacturer, both DDR2 and DDR3 are safe for long-term embedded designs. That leaves density as the most important variable in your selection. At this point, DDR2 has identified its “sweet spot”—1 Gbit IC production will remain the largest and most common density of DDR2. 2 Gbit Monolithic DDR2 ICs are offered as somewhat of a niche product (but are readily available!), while 4 Gbit DDR2 is available only as stacked die in a single package (DDP). On the low end of the spectrum, if you’re work-



ing with a processor that recommends 256 Mbit, forget it. Unless your processor cannot read more than a 512 Mbit DDR2 IC, it’s best to work with the 1 Gbit. The highest cost savings and safest long-term sustainability come with the largest segment of production, which is the 1 Gbit DDR2. Even if you do want to go up in density with a 2 Gbit or 4 Gbit, the pin out is the same as the 1 Gbit (or the 512 Mbit for that matter). While there might be a bit of a cost savings in a 512 Mbit DDR IC, the price does not directly correlate to density; half the density (512 Mbit vs. 1 Gbit) is not half the cost. The most commonly produced density and configuration remains 1 Gbit DDR2 in x8 and x16. So where does that leave DDR3? If space constraints, processor selection, or application demands push you over the limits of what DDR2 1 Gbit ICs can easily do for your application, then use DDR3. Presently, 2 Gbit DDR3 production is the “sweet spot.” By the end of 2011, most major manufacturers will have brought out a 4 Gbit Monolithic (some already offer a DDP 4 Gbit), and still others have even announced 8 Gbit DDR3 ICs. So long as your configurations match, then the best solution is to work with the “sweet spot” as much as possible and plan and allow for increased densities in the future. It is also important to understand

Manufacturers devote a great amount of attention to sample production and sales support in an effort to get their memory ICs included in reference designs. As we all know, these reference designs drive purchasing patterns for a very long time. However, engineers will often see only the major manufacturers for each new design that is debuted. Here’s a real-world example. I had a client call for support on a 1 Gbit DDR2 IC in a x16 configuration, CAS Latency (CL) 5 at 2.5ns. The 64Mx16 configuration in DDR2 is incredibly common in embedded memory applications. For some manufacturers, a CL5 at 2.5ns carries a specific part number add-on, and with it, a price premium. When my client wanted to match the original spec completely, I asked if it was really necessary to have CL5 at 2.5ns. After some deliberation and discussion with engineering, it turned out that the application did not specify nor require CL5 at 2.5ns. In fact, many of our customers’ feedback involved running 200 MHz at 5ns clock cycle times. The reality therefore is that nearly all DDR2 components can operate at CL5, CL4, or CL3 when clocking at such low speeds as 5ns. However, since the component specification was originally on the reference design and added to the Approved Vendor List (AVL; sometimes also called a BOM or AML), purchasing was forced to unnecessarily seek out a costly IC. In this case (as in many others), specific nomenclature is included in the part number that adds premium to your supply chain requirements. By thoroughly studying the simple differences on a datasheet, you can provide your purchasing department with multiple support options for future buys instead of just one. Additionally, you can

technology in context

prevent price bloat with add-ons that aren’t actually necessary for your specific application. Without review, cost savings and supply chain easing options might never make it to your AVL (Figure 1). Ask your suppliers and reps which speeds are most commonly manufactured. We’ve seen lots of EOLs on major brands for SDRAM this year. The most common speed previously was 133 MHz. However, most new manufacturers are only producing at 143 MHz. Some clients have balked at the speed increase, when in reality it rarely makes a difference in your application when you put it to test. Additionally, it is imperative to look for other manufacturers that make your chosen memory IC. Some of the major memory manufacturers continue to market SDR, DDR1 and DDR2 products in industrial and commercial temperature ranges. There are also several mid-tier manufacturers and fabless memory companies that offer competing products as legacy vendors. Their business models and long-term outlook are solid and can often provide deep cost savings. When dealing with mid-tier fabless companies, the key is to find local distribution or representation for those manufacturers. Once you have the support of a representative or distributor, then you have a direct channel to the lesser known manufacturers that may not have the marketing budget to comprehensively support reference designs. These representatives and distributors can then support your applications with sampling, technical support, cost saving and long-term design sustainability. As for the real-world example, we remedied the situation by qualifying three part numbers from the existing manufacturer, and added options from two additional manufacturers as well, one of them from a smaller brand. This has bridged the client through several revision changes by having the overlapping qualifications already done without seeing gaps in their supply.

is mostly consumer driven, and revisions will change based upon varying consumer demand and opportunities for the manufacturers to drive down costs with die shrinks and more efficient manufacturing processes. Typically, NAND flash devices have been limited to the big three memory manufacturers: Samsung, Hynix and Micron. However, other NAND manufacturers are beginning to come onto the scene

for smaller densities. For embedded applications, your choices are two-fold: either onboard flash memory ICs or peripheral flash devices. Peripheral flash devices include such products as disk on modules (DOM), compact flash cards (CF), or secure digital card (SD & SDHC). You can start by standardizing your flash controller if it’s not already built into your processor. Most problems I see with

What About Flash?

Many applications these days are now using some form of NAND flash memory devices. It is helpful to think of the category in a similar manner to DRAM. It Untitled-3 1


8/9/11 9:52:44 AM RTC MAGAZINE AUGUST 2011

technology in context

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qualification are not the memory chips, but the flash controllers themselves. If the reference design calls for a specific manufacturer, then actively test other NAND flash devices with your controller to ensure it works consistently. Lastly, remember that for rugged and high-vibration applications, onboard flash is the best choice. If you do choose to design with NAND flash ICs on the board, then keep in mind that the bulk of production on NAND ICs is presently in TSOP and at 3.3V. We have seen an increasing number of requirements for 1.8V BGA NAND ICs. But as production output is not as high as 3.3V TSOP, you may run into supply problems with BGA 1.8V NAND product. If your goal is to allow flexible densities for a product in an application, it is easiest to qualify a peripheral flash device. However this can be tricky in embedded design due to the wealth of manufacturers presently offering flash products in the market. The biggest problem customers create with peripheral flash devices is that engineers limit themselves to one manufacturer. Try to qualify several manufacturers who are willing to support with samples, sell industrial grade products and offer fixed BOMs. Once you qualify an industrial flash device, be sure to specify the differences between standard products and industrial grade products on the AVL. A simple note of “Industrial Temperature/Grade Only” in the AVL or in the part description can make a difference, and will prevent supply chain confusion with retail or consumer grade products. It is also important to be mindful that flash controllers across different manufacturers change. Once you find a flash device that works well with your application, make sure you’re on a fixed BOM with the flash device itself and stick with it. Without a fixed BOM, flash controllers will change rapidly, often times with negative results for embedded applications. Lastly, be open to solutions for different flash devices. Understand that revisions change frequently in NAND flash. In a peripheral flash device, a chip revision or a flash controller change will affect your complete device. Be open to suggestions if there are problems that arise due to these changes.

I have one last crucial and simple tip on design. Since you’re going to be looking at more than one manufacturer to include on your AVL after reading this article, try to find the manufacturer with the oddest and biggest package to design around. I have seen multiple applications where real estate on the board is at a huge premium because the original design used the smallest package available at the time. Packages, pin outs and FBGA layouts are standardized, but package sizes are not. I have had multiple clients reject alternative manufacturers because their package size was off by a millimeter or less in one direction or another. If you plan your pad space around the largest available package, you will prevent a world of headaches down the line. This is especially true for large companies that use a central library of internal reference designs and qualifications to share between projects. I have had so many conversations with engineers and purchasing personnel through the years and I wish I could cover everything. My best overall advice in embedded memory selection is simply to have an open mind to new and different manufacturers, expect comprehensive and knowledgeable support from your representation, and don’t get too creative on the configurations. Try to find out what is happening in the memory market. We are all part of a truly global business, and events half a world away affect our business daily. Consumer trends affect us in the embedded sector more than we sometimes want to admit. Accept that roadmaps will change despite our best planning and problems will arise. All we can do is try our best to be prepared. And one last personal request…when that next EOL notice does come down the pipe, try not to kill the messenger. We really are here to help! Memphis Electronic Houston, TX. (713) 600-6080. [].


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connected PCI Express Meets Serial RapidIO

Serial RapidIO Reaches a Crossroads with PCIe in Intel-Based DSP Designs Bringing the advantages to DSP recently achieved in Intel’s x86 architecture into systems previously dominated by the Power Architecture requires an efficient means of bridging between the PCIe world of Intel to the SRIO scheme implemented in most board designs. by Ian Stalker, Curtiss-Wright Controls Embedded Computing and Devashish Paul, IDT


SP systems designed for use in today’s signal processing applications require optimal bandwidth and reliability in rugged environments. To deliver the near real-time processing of analog sensor data required to locate the signals of interest, these systems require the optimal combination of data throughput and low latency. For these applications, Serial RapidIO (SRIO) is the preferred interconnect because of its high throughput, low latency, and the ease of architecting SRIO peer-to-peer processing clusters on modules, across backplanes and between chassis. Bridging PCI Express (PCIe) to SRIO changes the embedded military DSP landscape by providing a practical, cost-effective approach for using, for the first time, Intel x86 architecture microprocessors in system designs long dominated by Freescale’s (and formerly, Motorola’s) Power Architecture. Historically, the embedded DSP market has evolved toward using general purpose microprocessors, and away from dedicated DSP processors, such as Analog Devices’ SHARC and Texas Instruments’ 320C40 and 320C6701k. The PowerPC/Power Architecture, with its



AltiVec math processor for floating point calculations suitable for DSP algorithm processing, emerged as the clear favorite of DSP board and system designers. Demanding DSP systems typically comprise a mix of CPUs and FPGAs. A consequence of Power Architecture’s prevalence in embedded military DSP system designs was the establishment of SRIO as the favored serial communications fabric for interconnecting these types of devices, since PowerPC processors featured SRIO support built in. The stature of SRIO in the embedded market is reflected in the OpenVPX (VITA 65) standard, VITA’s open standard for building embedded military systems using VPX backplanes, which defines SRIO support for designers integrating highperformance radar, sonar, image processing and signal intelligence applications. Meanwhile, Intel microprocessors have become increasingly attractive to military embedded system designers. Helping to make Intel CPUs attractive for DSP applications is the recent debut, along with Intel’s “Sandy Bridge” architecture second generation Core i7 processors, of the new Advanced Vector Extensions (AVX)

math library. The AVX math library is an alternative to AltiVec that delivers double the performance of the venerable Power Architecture 128-bit floating point math tool by boosting the size to 256-bit wide floating-point instructions. Until recently, the major remaining hurdle for using Intel CPUs in multiprocessor embedded DSP designs was the fact that Intel historically provided no support for SRIO. Now, that hurdle has been surmounted with the recent introduction of the new Tsi721 bridge chip from Integrated Device Technology (IDT), a new PCI Express Gen2 to Serial RapidIO Gen2 protocol conversion bridge for x86 processors (Figure 1). This bridge chip supports 5 Gbaud PCI Express Gen2 and Serial RapidIO Gen2 interfaces. For the designer of embedded DSP systems, the combination of Intel’s new AVX-based Core i7 CPUs and IDT’s new bridge chip creates a true technology milestone after which Intel-based DSP systems are able to deliver unmatched embedded DSP performance and advantages.

The Serial RapidIO Advantage

The bridge chip addresses and solves

technology connected

limitations faced by earlier attempts to handle PCIe to SRIO protocol conversion in FPGAs, an approach that was both expensive and lacked support for the SRIO messaging required for control loops in signal processing applications. The use of an efficient bridge chip that features eight direct memory access (DMA) and eight messaging engines/channels, each capable of transferring large amounts of data and operating at the wire speed of 16 Gbit/s overcomes these limitations. While Power Architecture offers built-in SRIO support, options for Intel architecture-based distributed systems are more limited. One option is InfiniBand, a fabric popular in the enterprise computing world, but not often used in military system designs. Another choice is Gigabit Ethernet (GbE), but SRIO, especially the latest Gen2 SRIO, offers significant advantages for DSP designs over GbE. SRIO was designed for processor-to-processor communications within a system (be it chip to chip, board to board or chassis to chassis) and features guaranteed data packet delivery without risk that the packet might be dropped anywhere in the network. Ethernet, designed for very large networks connecting over great distances, doesn’t guarantee packet delivery. With Ethernet, packet delivery requires a packet verification protocol that adds significant overhead and burdens the processor as it checks every packet. The new generation of Gen2 S-RIO switches operate at 20 Gbit/s signaling, at more than 2x the bandwidth of 10 GbE (after header information is removed, the actual payload data is compared). Compared to 10GbE, Gen2 SRIO offers significantly higher performance, lower and predictable end-to-end latency and saves valuable board slots. 10 GbE performance drops when packet sizes are small, which is the preferred approach in embedded systems for better real-time performance. For 256-byte packets, 10 GbE delivers only 8 Gbit/s throughput. A bridge chip that features eight DMA and eight mes-

saging transmit and receive queues is able to support the full 16 Gbit/s line rate for 64-byte and larger packets, making it possible to transfer large amounts of data in a DSP system with low latency at 16 Gbit/s. Even better, SRIO supports distributed switch architectures, and SRIO switches are small, low-power devices (starting at 21 x 21 mm, ~3W typical). Their size and functionality make it common for board designers to provide SRIO switching on board DSP engine cards to locally aggregate multiple computing nodes. Compared to SRIO, Ethernet switches are significantly larger (typically 30 x 30 mm to 40 x 40 mm) making them impractical to deploy on 3U or 6U VPX multiprocessor DSP cards. Also, Ethernet switches have no small lane count options while SRIO Gen2 switches are available in 16 and 32 lane options. Where Ethernet switches are used in DSP applications today, they require a separate card, taking up valuable slot space and adding weight (a typical rugged card weighs 1.0 - 1.2 Kg) in size, weight and power (SWaP)-constrained military platforms. For systems that require a high level of fault tolerance, designers must add a second redundant Ethernet switch, consuming an additional slot and adding even more weight. Additional performance and overall system power penalties associated with Ethernet switches are end-to-end packet termination latency that can be in the order of milliseconds, and the need for processor intervention to terminate the protocol stack When it comes to OpenVPX system topologies, SRIO also comes out on top. Most embedded DSP systems deployed today have fewer than eight slots. One of the common topologies used on these distributed processing systems is a full mesh architecture in which each card is connected to every other card. This approach is attractive because it delivers very high card-to-card bandwidth and does not exhibit a single point of failure. OpenVPX

Figure 1 The Tsi721 from Integrated Device Technology offers efficient bridging between PCI Express and Serial RapidIO that uses minimal overhead and small package size, weight and power

defines four ports on the data plane. A system designer can use these four ports to build five-card distributed systems in which each card has a connection to the other four. While the five-card full-mesh is the ultimate in card-to-card bandwidth, larger systems can also be constructed using distributed switching where packets pass through the switches of intermediate cards. The high bandwidth of Serial RapidIO makes this practical for systems up to 16 slots in size.

The Importance of Slot Count

In comparison, a typical Intel-based DSP system using 10 GbE requires at least six slots, with one for a dedicated Ethernet switch card. A similar SRIO system requires only five slots since each DSP card can have multiple bridges per processor, mapped into a small SRIO switch and then have 4x4 SRIO links to the backplane. In addition to benefits for SWaP, minimizing board count also improves system Mean Time Between Failure (MTBF). Distributed switch systems (one example is the VITA 65 BPK6-CEN05-11.2.5-n backplane profile) make use of the local SRIO switch and thus avoid the need for RTC MAGAZINE AUGUST 2011


technology connected

Computing (CWCEC) implements the new IDT bridge on its dual Second Generation Core i7-based CHAMP-AV8 DSP OpenVPX engine (Figure 2). Each board employs four of the PCIe to SRIO bridge chips, providing two interfaces to each CPU, with each interface significantly faster than the bandwidth available from a 10 GbE interface. The bridges support 32 Gbit/s data rate for each Core i7. Overall, the CHAMP-AV8’s processors deliver up to 269 GFLOPS. With IDT’s Tsi721 bridge chip, the card delivers triple the bandwidth of first-generation VPX products—up to 160 Gbit/s fabric performance. Figure 2 The new CHAMP-AV8 for Curtiss-Wright uses four of the Tsi721 chips along with the second-generation Intel Core i7 processors for bandwidth beyond that of 10 Gbit/s Ethernet.

a separate switch card and save valuable, costly slot(s). For example, if the system were using a ½ ATR Short enclosure (four 1-inch slots), this capability would save 25 percent of the space and a consider-


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able amount of power. For large systems, centralized switch architectures are often preferred, and SRIO is equally adept at this approach. Curtiss-Wright Controls Embedded

Curtiss-Wright Controls Embedded Computing Ashburn, VA. (703) 779-7800. []. Integrated Device Technology San Jose, CA. (613) 592-0714. [].

3/31/11 4:26:15 PM

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systems Real-Time DSP

An Integrated Real-Time Platform Can Deliver Improved DSP Performance at Lower Costs Compared with systems based on DSP coprocessors, an approach that integrates processing cores on a single real-time platform yields economic and operational benefits that are catalysts for the increasing migration from DSPs. by Andy The, IntervalZero


igital Signal Processors (DSPs) Windows OS have specialized architectures that are optimized for heavy math comHuman UNUSED Real-Time Real-Time Real-Time Machine putations and they have dominated the Processing Processing Processing Interface real-time digital signal processing market (HMI) as a cost-effective solution for many complex designs. Although DSPs remain a viable Processor Processor DSP DSP DSP 0 1 1 2 3 choice for many systems, developers are finding that proprietary DSPs are no lonDuo Core System DSP/FPGA Subsystem ger required to perform real-time digital nies providing solutions now Instead, developers are signal processing. Figure 1 ion into products, technologies companies. Whether your goal is to research the latest migrating to and software-centered Realation Engineer, or jump to a company's technical page, the goal of Get Connected is to subsystem put you A DSP on a separate device connected to a Windows-based time Platforms, which comprise multicore you require for whatever type of technology, system involves a variety of development tools and issues with the interface general processors (GPPs), and productsx86 you are searchingpurpose for. and latencies. the Windows operating system and an SMP-enabled real-time software extension to Windows. They are leveraging this GPPs are used for human machine inter- Figure 2 illustrates a multicore x86 device innovative architecture to outperform face (HMI) and general purpose functions with cores dedicated for Windows and DSPs, to significantly reduce costs, and to such as input and output (Figure 1). Ad- cores dedicated to Windows real-time ditionally, it should be noted that DSPs extension for real-time signal processing streamline development cycles. DSPs rely on specialized architec- require separate memory devices for each functions. Unlike the design with a deditures designed for heavy math compu- device and separate buses, such as PCIe cated DSP, memory is shared using the tations, but not for general processing. or serial, are needed for all inter-processor same high-speed bus, allowing for data sharing and inter-processor communicaBecause of DSPs’ computational focus, communications. The Real-time Platform takes a dif- tions. Table 1 shows a comparison of the ferent approach, with the multiple cores two architectures, and in the sections that Get Connected divided up for dedicated real-time pro- follow, this paper will discuss the merits with companies mentioned in this article. cessing and general purpose processing. of the architectures in detail.

End of Article



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Tech In Systems

Real-Time Platform

World Class User Interface

Real-Time Application

Windows Kernel

Windows Real-Time Kernel Extension

Core 0

Core x

Core x+1

Core x+1


Core x+31

x86 Single or Multicore x64 Multicore Hardware Options

Figure 2 Real-Time Platform

Windows OS Processor 0

Windows Real-Time Extension Processor 1

Processor 2

Processor 3

Quad Core System Figure 3 An SMP-enabled Scheduler

Hardware Design

The x86/x64 multicore advances from Intel and AMD are changing the way system developers meet real-time signal processing needs. New GPPs not only have multiple cores with extremely high clock speeds, but also perform complex math efficiently. They deliver several times the performance of standard DSPs, as can be seen from the benchmarks in the comparison chart. Additionally, multicore x86 devices are delivered with commercial offthe-shelf (COTS) hardware, which is not usually an option for DSP users. COTS hardware rather than custom hardware translates into reduced costs, shorter timeto-market and less risk. When replacing DSPs with x86 multicore, attention should be focused on the



number of cores needed, as well as which x86 processor family best fits the system requirements. As a rough guideline, there can be a 1:1 relationship between DSPs and x86 cores. Because of the extremely high clock speeds with the x86 cores, the design will likely require fewer cores, but the 1:1 ratio is a conservative start, with room for optimization. Both Intel and AMD have different processor families based on cost and power. For example, Intel’s Atom and AMD’s Fusion devices are focused on embedded systems requiring low power and cost minimization. In DSP-based systems, engineers spend a great deal of time selecting the right processor so that the board can be designed and built in time for the soft-

ware. Having to make hardware commitments early in the design often creates challenges, and any miscalculation can lead to a hardware redesign, which will have a negative impact on the delivery schedule. When using the real-time platform there are no strict deadlines for choosing and designing the hardware. Because the real-time software extension for Windows is x86 based, standard COTS hardware is available for both development and production. With no custom boards or drivers required for development, the final hardware selection is performed later in the design cycle. This reduces risk and greatly improves the chances for releasing products on time. Also, because the real-time software is based on an x86 Windows architecture, engineers can use PCs as both development and target machines. No separate target system with specialized in-circuit emulators is needed to develop and debug code. As the comparison chart shows, the Real-time Platform’s use of COTS hardware reduces both engineering costs and risks. DSP-based systems rely on custom hardware and software interfaces when communicating between devices. Serial lines and sometimes PCI buses are used for inter-processor communications. These custom interfaces are troublesome to design on custom hardware and can be difficult to upgrade as requirements change. The Real-time Platform uses shared memory and formalized APIs to communicate between the processes. Because everything is running on a single device, it is easy to share data and messages between threads running on different cores. This communication architecture makes programming easy and scalable. While DSPs require separate memory devices, with the Real-time Platform memory is consolidated into a single memory device. Also, the x86-based platform can use standard off-the-shelf memory modules, such as 4 Gbyte SDRAM DIMM, and memory modules can be easily changed as system requirements dictate. DSPs require onboard memory chips because of strict timing and routing requirements. Switching out memory chips

tech in systems

is difficult and requires board changes to add or remove memory. The DSP-based approach is more costly, complex and less flexible than the Real-time Platform.


DSP Platform

Real-time Platform

RT Platform Benefit

Hardware Design

• Custom board design • Long development cycle • Difficult to modify hardware • Requires in Circuit Emulators (ICE)

• (COTS) • Short development cycle • Easy to change hardware • Local Debug – no ICE needed

• Reduced Cost • Reduced Risk • Faster Time To Market


• Custom Drivers-device specific

• Standard Drivers

• Cost • Productivity

System Communication

• Custom protocol • Custom buses

• Shared memory • Standard APIs

• Ease of use • Future proof


• Chip Down – hard to change • Limited selection • Limited memory reach (1GB) • No MMU

• P nP/COTS Modules – easy to change • Large selection • L arge memory reach (>4GB) • MMU – virtual memory

•R  educed system size, cost and complexity


• Proprietary

• winAPI

• Familiar API

Development Environment

• Proprietary Tools • Manufacture specific • Proprietary Compliers

• Standard x86 Tools • Microsoft Visual Studio • Intel and Microsoft Compliers

•C  ommon tool chain throughout the product

Code Base

• Assembly and C • Architecture specific

• C,C++, C# • Universal/Portable

• Uses other higher level languages for non real-time

DSP Libraries

• Processing libraries from OEM

• Intel supplied IPP library • Other 3rd party libraries

• No requirement to use OEM proprietary libraries.


• 1.25 GHz – Max core speed • 20 GFLOPS/Device Max

• 3.0 GHz – Max core speed • >50 GFLOPS/Device Max

• Faster • Higher performing

Software Design

Software advances have also had significant impact on DSP-based systems. The demand for standardized tooling in lieu of the proprietary tool sets is a recent change for many DSP developers. Programming DSPs requires proprietary tools and lower-level languages such as C and Assembly. Many engineering teams find that proprietary DSP tools and lowlevel languages require specialized expertise, which is often very difficult to find and expensive to acquire. The use of standardized development tools and higherlevel languages, such as Visual Studio and C++, not only increases productivity but also greatly reduces engineering costs. The demand for complex graphical user interfaces (GUIs) has also impacted DSP-based systems. Customers are increasingly seeking elaborate touch-andgesture-based user interfaces on top of a real-time subsystem. DSPs have never had the GUI and I/O support to satisfy most complex system requirements. That is why GPPs running general purpose operating systems are typically found next to DSPs to handle all of the I/O and the complex user interfaces. As a result of the strong demand for powerful GUIs, Windows is becoming the preferred operating system because of its abundant tools support and its standardization. The use of standardized tools like Visual Studio and the large support structure of Microsoft’s Developers Network make transitioning from DSPs to the Real-time Platform very straightforward. DSPs use proprietary RTOSs from device manufacturers such as DSP/BIOS from Texas Instruments (TI) or VDK from Analog Devices (ADI). These DSPbased RTOSs are quite capable but have significant limitations because of the lack of communication among the different DSP cores. Each DSP runs its own application and very little inter-processor communication is used. The Real-time Platform implements a single symmetric multiprocessing scheduler, such as IntervalZero’s SMP-enabled

TABLE 1 DSP vs. Real-time Platform

RTX, across all of the cores in the realtime subsystem (Figure 3). Instead of a separate RTOS and application running on each real-time core, the real-time platform uses a single real-time scheduler to schedule threads across a number of different cores. The flexible SMP scheduling model makes synchronization and communication among the different cores/ threads simple and easy to implement. Load balancing can be easily implemented from the APIs provided by the real-time subsystem. The subsystem’s APIs enable threads to be moved between processors during runtime. This scalability translates well when moving the application to systems with different core configurations. When cores are either added or removed from a system, the user can easily use logic within their application to load balance threads as needed. DSP manufactures provide proprietary tools such as Code Composer Studio from TI and VisualDSP++ from ADI. While these tools are very useful for de-

veloping DSP-based applications, market demand and cost pressures are providing impetus for more standardized tooling. Additionally, DSPs’ low-level tooling and proprietary coding practices do not promote code reuse and portability. This translates into longer development times and higher risks. Many developers are finding that working with proprietary DSP tools is not only challenging, but also costly to maintain. The real-time Windows extension uses Microsoft’s Visual Studio, which is the industry standard tool for x86/x64based programming. Finding engineering talent for Microsoft tools is easier and more cost-effective than is the case with DSPs. Leveraging the support and robustness of Visual Studio and the Microsoft Developers Network (MSDN) makes for increased productivity and reduced costs. Most engineering teams prefer the use of standardized tools for their robustness and their support. Migrating code base to a Real-time RTC MAGAZINE AUGUST 2011


Tech In Systems

CompactPCI® Goes Serial



Intel Multicore

1.25 GHz - Max core speed 20 GFLOPS / Core

3.0 GHz - Max core speed 32 GFLOPS / Core

TABLE 2 The comparison is between aC66xx multi-core DSP from Texas Instruments and an Intel i7 Sandy Bridge device.

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8/5/11 12:38:15 PM

Platform such as IntervalZero’s RTX Platform is straightforward. When considering a port, the developer needs to be aware that there are two parts to the application. First, there is the general purpose, or nonreal-time processing, and then there is the DSP/real-time processing. The non-realtime/general purpose code will directly port over using a standard Visual Studio project and will run on the Windows operating system. The DSP/real-time code will also be built using Visual Studio, but it will be running on the RTX controlled cores (real-time subsystem). DSPs are usually programmed in both C and Assembly. While the Assembly code is not portable and will need to be written in C or C++, the C code can be ported over using Visual Studio. The platform enables real-time users to code efficiently in C++ rather than having to start with C and Assembly programming. While DSPs do have some C++ support, object-oriented languages lose too much efficiency to be useful when compiled for DSP architectures. The RTX Platform’s strong support for C++ is a distinct advantage. Through the use of powerful x86 devices, programmers can use C++ to increase productivity. By keeping the code base in higher level languages like C/C++, portability and code reuse can be leveraged to reduce costs and risks. Texas Instruments and Analog Devices both provide optimized DSP libraries to help developers with performance and time-to-market. To take the place of these DSP libraries, Intel created the Integrated Performance Primitives (IPP). The IPP library is essentially a collection of optimized functions, such as DSP, imaging, video, etc., for the multicore x86 architectures. The IPP library helps to increase productivity and performance by providing optimized routines for the most common DSP-based functions. There are a number of ways to mea-

sure performance between processors. Because the focus is on DSPs, measuring the number of floating point operations per second (GFLOPS) is used in this comparison (Table 2). The TI C66xxx @ 1.25 GHz outputs 20 Single Precision GFLOPS per core. The Intel i7 Sandy Bridge processor outputs 32 Double Precision GFLOPS per core. Although the GFLOPS performance is very strong with the TI DSP, it does not match the raw performance and speed of the Intel processors. A real-time platform marries the powerful Windows 7 interface with the real-time signal processing capabilities of Intel’s and AMD’s multicore architectures. Using standardized COTS hardware and standardized tooling greatly simplifies the engineering effort and reduces cost. The SMP-enabled platform increases innovation, portability and scalability while also reducing costs. There will always be a need for digital signal processing, but because of the many hardware and software advances, dedicated DSPs are an option, not a requirement. For complex systems requiring powerful graphical user interfaces along with real-time signal processing, there are higher-performing, more scalable, less costly options. IntervalZero Waltham, MA. (781) 996-4481. [].



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technology deployed Making the Most of Multicore

A Static Analysis Approach to Identifying Defects in Multithreaded, Multicore Designs

leavings (Figure 1). The number of possible interleavings for a pair of threads with twelve instructions each exceeds two million. Real concurrent programs have astronomical numbers of legal interleavings, so testing every interleaving is completely infeasible. Static analysis tools such as GrammaTech’s CodeSonar can discover software defects without exhaustively exploring interleavings. They thus play an important role in multithreaded software verification: one that testing alone cannot fill. The consequences of interleaving stretch far beyond testing. Interleaved threads can actually affect each other’s behavior. Ideally these effects are intentional and correct, but in practice they sometimes involve race conditions—a class of problem that does not exist exploration in a single-threaded environment. The comr your goal The power of multithreaded code on multicore processors munity has devoted extensive effort toward eak directly developing techniques to eliminate these ill page, the has promise of huge gains in performance. At the same effects. Unfortunately, these techniques inresource. time these advances introduce levels of complexity that hnology, troduce problems of their own, including the nd products cannot be verified by any amount of testing. Static analysis potential for deadlock and starvation. A race condition arises when multiple tools can find many problems that testing cannot. threads of execution access a shared piece of data, at least one of them changing its value, without an explicit synchronization operaby Paul Anderson, GrammaTech tion to separate the accesses. Depending on the thread interleaving, the system can be left panies providing solutions now in an inconsistent state. Race conditions are ation into products, technologies and companies. Whether your goal is to research the latest especially insidious because they can lurk uncation Engineer, or jumpultithreading to a company's technical page, the goal Get Connected is to put you adds entirely newofclasses of potential bugs detected indefinitely and only show up in rare circumstances with ce you require for whatever type of technology, to those that must be considered by developers. At the mysterious symptoms that are difficult to diagnose and reproduce. es and products you are searching for. same time, the nondeterminism and sheer number of In particular, they are a common source of errors in (well-tested) possibilities introduced by thread interleaving make it signifi- deployed software. At best, the presence of race conditions means cantly more difficult to find bugs in multithreaded systems by increased development times; at worst the consequences can be devtesting and other traditional methods. We will have a look here astating. A race condition in a computerized energy management at some of the common concurrency pitfalls and explain how the system dramatically worsened the 2003 Northeast blackout by causcurrent generation of sophisticated static analysis tools can help ing delayed and misleading information to be communicated to the address both of these issues without the limitations experienced operators. Kevin Poulsen, writing in SecurityFocus, notes that “[t] by execution-based techniques. he bug had a window of opportunity measured in milliseconds.” When multiple operations can execute concurrently, everything The chances of a problem like this manifesting during testing are becomes more complicated. One of the most significant compli- infinitesimal. In another case, a race condition (now fixed) in iOS 4.0 cations is that instructions in multiple threads can be interleaved. through 4.1 meant that any person with physical access to an iPhone The number of possible interleavings increases enormously as the 3G or later could bypass its passcode lock under certain conditions. Connected number ofGet instructions grows—a phenomenon known as the combiA simple race condition example is shown in Figure 2. A manuwith companies mentioned in this article. natorial explosion. If thread A executes M instructions and thread facturing assembly line maintains a running count of items currently B executes N instructions, there are N+MCN possible interleavings of on the line. The count is incremented every time an item enters the the two threads. Even the smallest threads have many possible inter- line, and decremented every time an item reaches the end of the line. If an item enters the line at the same time that another item exits, the count should be incremented and then decremented (or vice versa) Get Connected with companies mentioned in this article. for a net change of zero. In a multithreaded system a race condition


End of Article



Technology deployed

can arise because the controllers read and write a shared piece of data: the count. Many interleavings correctly result in a count of 70, but some result in incorrect counts of 69 (as in Figure 2) or 71. Race conditions like this are difficult to eliminate for several reasons: Rare occurrence means little chance of even noticing that there is a problem. If the problem manifests infrequently, it may never show up during testing since, as noted above, testing can tractably cover only a tiny proportion of the possible interleavings in a program. Race condition diagnosis is difficult. Firstly, the symptoms can be perplexing. In the Figure 2 example, the running count will (probably) usually be correct, but sometimes too high and other times too low. Secondly, programmers unaccustomed to considering the particular pitfalls of multithreaded programming may spend a lot of time puzzling over the code before the possibility of a race condition occurs to them. The effects of race conditions often seem impossible when the symptomatic code is considered in isolation; this sometimes leads developers to discard race-related bug reports as unreproducible. Static analysis is especially helpful in this regard. It identifies race conditions by examining patterns of access to shared memory locations—that is, it focuses on the causes, not the symptoms. Eliminating race conditions can introduce new problems. Race conditions are typically avoided by using locks or other synchronization techniques to protect shared resources. However, these can introduce performance bottlenecks. They can also, in the worst case, introduce new kinds of problems: deadlock and starvation. In a deadlock, two or more threads prevent each other from making progress by each holding a lock needed by another. Figure 3 shows how a deadlock can arise with two locks used to pro-





Figure 1 There are six possible interleavings of two threads with two instructions each. With three instructions each, there are twenty possible interleavings.

When entry sensor trips, count++ 1) Read count:70 2) Compute 70+1=71

When exit sensor trips, count--





3) Update count to 71






1) Read count:70 2) Compute 70-1=69

WRITE 3) Update count to 69.

Figure 2 Race condition leads to incorrect count of items on an assembly line.

tect two shared variables. In this example, assembly lines share a count of the total number of items currently under assembly and a second bad_items value recording how many finished items have failed quality control. One thread acquires the lock on count, another acquires the lock on bad_items. Neither thread can now obtain the second lock it needs, so neither can carry out its operations: both threads are completely stuck. Deadlock can only arise if different threads try to acquire the same locks in different orders. This property is one that can be detected statically, meaning that the potential for deadlock in a program can be detected even if no deadlocks have emerged in testing. An even more aggressive approach is to forbid any thread from holding more than one lock at a time: a property that is also statically checkable. Even though either of these restrictions on locks is sufficient to eliminate deadlock, process starvation can still occur. A thread starves if it is waiting for a lock that is held by another thread for a very long time. The most common instances of this problem involve the lock-holding thread waiting for an event like a large disk read or the arrival of data from the network. Suppose our example manufacturing automation system includes a regular audit thread that examines all entry and exit records to ensure that the running count matches total items entering less total items exiting, as shown in Figure 4. The audit thread needs to hold locks on the count and on all sensors, so all updates must wait for the audit to finish. If the audit runs for a long time, updates can be significantly delayed. If it runs for too long, the next audit may manage to acquire all the locks and start running before the outstanding thread can make any progress. In the worst case, some or all of the updates may never have the opportunity to run. Static analysis can help find starvation errors by posing questions like “can the thread call a long-running function while holding a lock?” Various static tools have built-in checks of this form for calls to library functions such as sleep(). Some, such as CodeSonar, also allow users to extend this checking to other designated functions. It can be tricky to write code that uses synchronization techRTC RTCMAGAZINE MAGAZINE AUGUST MONTH 2011


technology deployed

niques effectively. Static analysis tools are generally well suited to identifying potentially risky patterns of synchronization function usage, such as a lock/unlock operation that refers to a lock that cannot be identified, or an unlock operation in some function that does not have a corresponding lock operation in the same function. Ensuring these patterns don’t occur can reduce the incidence of runtime problems as well as making code easier to read and maintain. In addition, users can add their own checks for risky usage patterns, perhaps based on local coding rules, or on the particular synchronization techniques used in a given project. The performance gains that come from increasing processor

Audit thread 1) Get lock on count 2) Get locks on all sensors 3) Start long-running audit ...

Thread 1

Thread 1....Thread N

1) Get lock on count Have to wait for audit thread 1) Get lock on count Have to wait for audit thread

...still running

...still waiting

...still waiting

Figure 4 When exit sensor on line 1 trips:

When exit sensor on line 2 trips:

1) Get lock on count

1) Get lock on bad_items

2) Get lock on bad_items Have to wait until other process releases bad_items lock


2) Get lock on count Have to wait until other process releases count lock

can’t progress

3) Decrement count 4) if item is faulty, increment bad_items 5) Release lock on bad_items 6) Release lock on count

3) Decrement count 4) if item is faulty, increment bad_items 5) Release lock on count 6) Release lock on bad_items

Figure 3

The audit thread holds the count lock during its long execution, starving all the other threads that need that lock to proceed.

core counts are significant, but so are the challenges of developing multithreaded programs and the effects of concurrency bugs. Static analysis provides important leverage in the multithreaded development lifecycle and is recommended as an adjunct to traditional testing and debugging activities. GrammaTech Ithaca, NY. (607) 273-7340. [].

Deadlock between two threads: neither can progress.

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Untitled-8 1




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technology deployed Making the Most of Multicore

Building Scalable Network Processing Platforms with Multicore Processors

challenges of the infrastructure that supports them. There is now estimated to be in excess of 500,000 apps available for the iPhone, iPad and Android platforms alone. Much of the demand is based around delivering new rich media and video. According to the Cisco VNI, an ongoing initiative to track and forecast the impact of visual networking applications, there are a number of both exciting and frightening trends that are fueling network growth and evolution. Here are just four numbers to consider 32, 26, 40 and 61: 32%—the compound annual growth rate (CAGR) that IP traffic will grow over the next five years; 26—the number of times mobile data traffic will increase between 2010 & 2015. The numbers 40 and 61 represent the percentWith the huge demand being placed on today’s networks, age of consumer Internet traffic that is video content, today and in 2015 respectively. No thanks in part to the surge in smart phones and tablets, longer can there be complaints about unused increased processing is needed in different roles in the capacity, and the challenge is how to corral the data traffic in the most efficient ways possible. network. To address this while keeping power, heat and Network technologies and applications such as cost under control, multicore processors are finding deep packet inspection (DPI), traffic-based filenthusiastic acceptance among developers. tering, encryption, packet and media processing are all needing to take on extra load. One of the fundamental attributes common to all new network application platforms is the need for “wire speed” processing as they by Paul Stevens, Advantech must interact with the traffic flows without impeding them in any way. As we can now see, the volumes are huge and the throughput and speed requirements will in turn require a serious amount of compute and processor capability. Simply throwing more s excited new users charge their latest mobile device for the processors, systems and racks full of equipment at the task just won’t first time, little thought is given to the challenges these new devices bring to the infrastructure that must support them. do as one begins to approach the logical limits of one’s resources Whether a smartphone, iPad or Android tablet, they are all adding to whether those are power, real estate or cash. the rapid growth in network traffic as new devices and applications, There are many similarities with the challenges that faced the proespecially those in the mobile space, place greater demands on the cessor developers as they fast approached the limits of physics with the infrastructure. Besides managing the overall traffic volume, which traditional performance enhancing technique of increasing clock freCisco’s Visual Networking Index (VNI) predicts will approach the quencies. These techniques dramatically increased power consumption zettabyte/yr threshold (1 zettabyte = 1 billion terabytes) by 2015 (Fig- and heat output, making it more challenging to build system platforms ure 1), increased burden is placed on all infrastructure support appli- with the necessary densities. The resulting solution was the developcations such as the security and traffic management platforms. At all ment of multicore processing technologies. Multicore architectures enlevels the evolving infrastructure needs platforms that can handle this able processors to be created that have two or more identical CPU cores load while still keeping both physical and power footprints in check. For (now as many as 32 or more) and typically share a common system all this, carriers must still watch the bottom line, so cost-optimized and memory. Each core can operate independently on different processing efficient solutions are a prerequisite. A range of multicore processors elements and dataflows and can also easily interact with other cores implemented across a variety of system platform architectures are being and processors. The processing, bandwidth, power, scalability and cost requireutilized both individually and in combination to meet these challenges. ments for platforms in next-generation mobile (4G/LTE) telecom It seems not that long ago since we experienced the telecom crash, infrastructure and enterprise networking are well matched with and the huge amount of excess capacity and dark fiber was crying out the capabilities of multicore technology. Many of the applications for the next “killer app.” Well, the tables have turned and one could say such as those related to DPI (security, filtering, content managethat a multitude of applications have contributed to the current growth




Technology deployed

40.2 EB

0 2010



Video Data Video Communications Online Gaming




File Sharing Web and Other Data Voice Communications * Cisco VNI June 2011

Figure 1 Network traffic will be 4x 2010 levels by 2015. Source: Cisco Systems

ment) can easily be split into logic chunks with the heavy lifting processes being highly repetitive making it suitable for scaling across many cores. Not all network applications have the same requirements; this has led to a “division of labor” approach to network equipment architecture: • Control Plane and Device Management functions—such as call setup, connection control, routing, signaling, device operation, administration and maintenance—were performed on General Purpose Processors (GPP). • Data Plane functions—such as packet processing, encryption/decryption, compression/decompression, traffic-based filtering, video transcoding and deep packet inspection—were performed on Network Processing Units (NPU). • Digital Signal Processing functions—such as audio and speech processing, digital image and video processing, sensor array and radar/ sonar signal processing—were performed on Digital Signal Processors (DSP). Early generation NPU and DSP products used ASICs to provide the required performance and functionality, sacrificing the flexibility provided by software programmability of GPP-based solutions. The current generations of NPU and DSP products use multicore technology to gain the benefits of programmability and scalability, typically using a less complex RISC processor for each core. Backed by a full SDK, the multicore NPU and DSP products are now as flexible (i.e. programmable) as general purpose processors. The boundaries between these different types of solutions are being blurred. GPP multicore processors have added hardware acceleration for certain packet processing and/or security functions, and some NPU and DSP processors have added general purpose CPU cores to

handle control plane and device management functions. As always, products are adapted to meet market needs and these “hybrid” architectures are a good example of that. There are numerous examples of multicore GPP, NPU and DSP processors that can fit the bill for telecom and enterprise networking applications. Although there is some crossover, each is suited to a certain set of applications. Intel Xeon Processors: The top end of the embedded Intel Xeon Processor 5000 Sequence Family, the E5645, is a 32 nm core microarchitecture designed for high-performance, data-demanding applications. Each of the six 2.4 GHz cores can support 12 threads, making it a great choice for use in networking platforms (Figure 2). For the 5000 family, there are specific low power options that provide greater performance per/watt, making them eminently suitable for matching with the power envelope constraints of embedded standard form factors. Intel targets this family of processors at a wide range of applications including storage area networks, network attached storage, routers, IP‐PBX, converged/unified communications platforms, sophisticated content firewalls, unified threat management systems, medical imaging equipment, military signal and image processing, and telecommunications (wireless and wireline) servers. Cavium Network’s Octeon II Internet Application Processor Family: A flexible multicore design using MIPS64 architecture, the Octeon family can support up to 32 cores and can be configured with up to 75 application acceleration engines. A state-of-the-art network processor, it is designed for the needs of next-generation networking 70 Mpps

60 Mpps

IP Forwarding Performance

80.5 EB

50 Mpps

40 Mpps 30 Mpps

20 Mpps

10 Mpps






Number of cores configured to run fast path

Figure 2 Performance for a 2.4 GHz Intel Xeon E5645 processor running 6WIND’s 6WINDGate packet processing software. The performance varies with the number of cores running the fast path protocols. RTC RTCMAGAZINE MAGAZINE AUGUST MONTH 2011


technology deployed

System Solution Density (# of channels)

Multimedia Application

DSPC-8661 PCIe card 4 x C6678 DSP

DSPA-8901E ATCA Blade 20 x C6678 DSP

Mobile Voice Applications AMR Encode + Decode, 12.2 Kbps H. 264 BP Encode + Decode, CIF, 30fps

5,500 120

27,500 600

Content Delivery Network H.264 BP Encode + Decode, SD, 30fps







HD Conferencing MCU, MRFP H.264 BP Encode + Decode, 1080p30 HD Broadcast AVCIntra-50, 10-bit, 4:2:0, 60fps

Figure 3 Specialized multicore processors such as digital signal processors from Texas Instruments can significantly optimize performance over GPP solutions. 20 TI C6678 multi-core DSPs using only a single slot can support up to 20 channels of HD broadcast video.

Figure 4 NCP-7560 Packetarium Platform with dual XAUI interconnects between each processor board to a 10 GbE switch on the mainboard. The system supports up to 256 cores in a 4U rackmount NEBS-ready server.

applications. Including specialized functions for security and packet processing acceleration with very low power consumption built directly into the hardware (with supporting software), these processors are designed to maximize throughput for a multitude of protocols all the way to layer 7. Key application uses for the Octeon family are routers, switches, HD video over IP, deep packet inspection (DPI), unified threat management (UTM) appliances, content‐aware switches, application‐ aware gateways, triple‐play gateways, WLAN and 3G/4G access and aggregation devices, storage arrays, storage networking equipment, servers and intelligent NICs. NetLogic Microsystems XLP Processor Family: The XLP832 processor supports 8 MIPS64cores and is designed for both control plane and data plane applications. Numerous autonomous acceleration en-



gines (AAEs) provide packet processing, security, compression/decompression, load balancing and storage acceleration functions. NetLogic’s low-latency Fast Messaging Network (FMN) allows for non-intrusive communication and control messaging among VirtuCores, acceleration engines and I/O, enabling inter-unit communication without the need for spin-locks or semaphores. NetLogic targets the XLP Processor at high-end communication systems, including wired and wireless security, networking, storage and data center acceleration. Texas Instruments Multicore DSPs: Texas Instruments offers a high-performance multimedia solution based on its TMS320C6678 digital signal processor (DSP). Designed for applications such as multimedia gateways, IMS media servers, video conferencing servers and video broadcast equipment, the C6678 is a highly dense media solution that is both power and cost efficient at the system level. Based on its newest DSP generation of devices, the TMS320C66x, TI’s C6678 features eight 1.25 GHz DSP cores with 320 GMACs and 160 GFLOPs of combined fixed- and floating-point performance on a single device, enabling users to consolidate multiple DSPs to save board space and cost, as well as reduce overall power requirements (Figure 3).

Multicore-Based Network Application Platforms

We have seen that multicore GPU, NPU and DSP platforms have healthy roles to play and equipment designers have a multitude of choices from which to select the best possible solution for their specific application needs. There may be a multitude of reasons why one development organization chooses one architecture over another. It may be specific technical features, existing software investments, power requirements or competitive economics. Examples of the two ends of that spectrum of choice are Advantech’s AdvancedTCA and Packetarium product lines. AdvancedTCA is a standards-based board and system platform architecture designed with telecommunication solutions in mind. Supported as part of the SCOPE Alliance’s profiles and carrier grade base platform definition, numerous network platforms have been built using AdvancedTCA. Advantech offers a number of multicore AdvancedTCA blades. For GPP requirements the MIC-5322 is a dual processor Intel Xeon 5500/5600-based blade. The MIC5322 supports one of the highest performing Intel Xeon processors in ATCA form factor with 12 cores and 24 threads of processing power, low DDR3 memory latency, fast PCI Express 2.0 and accelerated virtualization. Aimed at providing a large amount of video and media processing capability, the Advantech DSPA-8901 is designed with 20 TI TMS320TCI6608 DSPs. That totals 160 cores of processing power to reach the higher levels of performance density needed to build the highest capacity wireless media gateways. The DSPA-8901 significantly reduces overall system power dissipation and system cost, and frees up valuable slots in gateway elements for additional subscriber capacity and throughput. The DSPA-8901 includes a highperformance Freescale QorIQ P2020 processor and a Broadcom BCM56321 switch, which terminates the 10 Gigabit Ethernet fabric connections and distributes traffic to the twenty DSPs. Although they have an impressive array of carrier grade features, AdvancedTCA platforms can be size, power and price prohibitive for some applications, especially those that are heavily dedicated to network processing. This was one of the key reasons behind Advantech’s cost-optimized Packetarium range. The goal was to

Technology deployed

pack as much network processing performance as possible into the smallest package while keeping power consumption and cost efficiency optimized for the targeted applications. The NCP-5260 represents a new generation of hybrid system designs with Intel architecture processing on the control plane, and Packetarium network processing boards featuring NetLogic NPUs for the data plane. It integrates up to two powerful, multicore Packetarium network processing boards for wire speed packet processing and accommodates up to 16 x 10 GbE external interfaces. The main carrier board provides the high-speed switched interconnects between Packetarium boards (Figure 4). At the high-performance end of Advantechâ&#x20AC;&#x2122;s Packetarium product line, the NCP-7560 integrates up to eight powerful, NCPB-2320 multicore Packetarium Network Processing Boards. Utilizing Cavium Networkâ&#x20AC;&#x2122;s CN6880 Octeon II processor, a fully configured NCP-7560 packs 256 cores into the 4U server space to handle 80 Gbit/s of network traffic from multiple 10 Gigabit Ethernet ports. Applications that reap the performance benefits of the new Octeon II processor family include high-capacity radio network controllers, network acceleration platforms, as well as data center and LTE gateways. None of us have crystal balls but we can all be certain that the future of global networks will be one requiring a huge increase in capacity and capability. As the various models of cloud computing go from strength to strength, and networkcapable mobile devices become even more pervasive, the requirement for ever more powerful network systems platforms

Untitled-6 1

will increase. Whichever high level architectures are chosen by solution developers, the advantages of multicore silicon linked with flexible and cost-optimized system platforms will provide a major implementation advantage. Advantech Irvine, CA. (949) 789-7178. []. Cavium Networks San Jose, CA. (650) 623-7000. []. Intel Santa Clara, CA. (408) 765-8080. []. NetLogic Microsystems Santa Clara, CA. (408) 454-3000. []. Texas Instruments Dallas, TX. [].


6/9/11 2:29:49 PM


ploration your goal k directly age, the source. ology, d products



Advances in Wireless Connectivity

Demystifying the 4G Phenomenon: Part 1 Mixes of technologies and marketing messages have led to some confusion as to what actually constitutes 4G and Long Term Evolution (LTE) in the wireless world. Sorting out the differences within an overarching terminology can help developers make better choices. by Todd Mersch, RadiSys


End of Article



Get Connected with companies mentioned in this article.



Base Station Base Station

Base Station

No Diversity very time I flip on the television, I come to learn yet another mobile operator is providing “4G” service. Strangely, though, the International TelePropagation Channel communications Union (ITU) recently acknowledged only two technologies that fit their IMT-Advanced (i.e., 4G) framework: Transmit Diversity (TxD) • Mobile WiMAX 2, or IEEE 802.16m • 3GPP LTE Advanced – LTE Release 10, Propagation supporting both paired Frequency DiviChannel nies providing solutions now sion Duplex (FDD) and unpaired Time ion into products, technologies and companies. Whether your goal is to research the latest Division Duplex (TDD) spectrum ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you Unfortunately, they slapped an asyou require for whatever type of technology, TxD and Receive Diversity (RxD) this ruling stating that both the and productsterisk you areon searching for. forerunners of these technologies (i.e., LTE Rel-8 / Rel-9 and WiMAX 1.0) as well as Propagation enhancements to existing 3G networks that Channel provide “substantial level of improvement in performance and capabilities” can be called 4G as well. Figure 1 Translation: all network upgrades are being marketed as 4G. Diversity can protect against fading by choosing the best antenna. However, never fear. It is still possible to help organize the nebulous 4G cloud into discrete technology blocks. That way the The Problem with Marketing next time an executive says, “We should This section title itself could be the have a 4G strategy” you can respond on topic of a whole separate article, but that’s Get Connected the quick. not why we are here. The problem with with companies mentioned in this article. “4G” marketing is that once one operator


MIMO Stream1 MIMO Stream2

Carrier #1

MIMO Stream1 MIMO Stream2

Carrier #2

Aggregated Spectrum


Base Station

Figure 2 Downlink MIMO

claims they have moved from 3G to 4G, everyone else needs a position as well. This is truly what opened the door to a broader technical designation from the ITU and, ultimately, the current confusion. Table 1 outlines the various wireless networks technologies with 4G claims. From the summary in Table 1, a few initial items should jump out at you. First, each of these technologies leverages similar techniques at the air interface, including Multiple Input Multiple Output (MIMO) antenna systems, advanced modulation schemes and—except High Speed Packet Access+ (HSPA+)—Orthogonal Division Multiplexing (OFDM).

Frequency TDMA


Time 1G










User #1



User #2

User #3




Secondly, there are two primary standards bodies driving the definitions: the Third Generation Partnership Program (3GPP) and the Institute of Electrical and Electronics Engineers (IEEE). In this case the 3GPP is the incumbent body driving standards for mobile networks in the licensed spectrum, and the IEEE became the new player, primarily with WiMAX (802.16 series) growing out of the previously unlicensed spectrum world of Wi-Fi (802.11 series). To date, the majority of operators have embraced LTE, and, in the future, LTE-Advanced (LTE-A) as their path to 4G, but WiMAX remains a significant technology and the foundation of the Sprint/Clearwire network in the U.S. Finally, one operator’s 4G may end up slower than the others! An operator takes a big risk claiming HSPA+ as “4G” if their competitors are deploying LTE, LTE-A, or WiMAX 2. However, time-to-market may be the most valuable parameter for that operator. Unlike the others, HSPA+ builds on top of the existing deployed 3G HSPA network, operating in the same spectrum and Core Network.

(e.g., 64 QAM vs. 128QAM, etc.). Diversity and MIMO Diversity and MIMO are both based on leveraging multiple antennas at the base station and user equipment (UE) to increase signal to interference-plus-noise ration (SINR) and provide carrier aggregation, respectively. Diversity refers to using multiple transmit and receive antennas at the base station and UE respectively. It allows for protection against fading by essentially choosing which antenna to transmit or receive on based upon which has the best signal strength. There are two primary configurations. The first is called Transmit Diversity (TxD) in which there are at least two Tx (Tx = transmit) antennas at the base station. The second is termed TxD and Receive Diversity (RxD), where there are at least two Tx at the base station and two Rx at the UE. Using both TxD and RxD results in the greatest protection from fading as well as an option to co-phase beams to maximize SINR. Figure 1 illustrates TxD and RxD. All of the 4G technologies exploit both transmit and receive diversity to deliver better performance and capacity. MIMO takes this a step further by exploiting multiple downlink (DL) and uplink (UL) antennas to enable the aggregation of multiple carriers both on the DL and UL to multiply the throughput

Cell 1

4G Building Blocks User #4

Figure 3 Radio Access Air Interfaces (Source: WiMAX Forum, 12/2010)

As was pointed out above, the essential techniques leveraged to increase radio interface throughput to 4G speeds are shared across the different approaches. The key technical aspects covered here include MIMO, OFDM and coding schemes

Cell 2

Cell 3

Figure 4 Coordinated Multi-Point (CoMP)




Key Characteristics






Max Downlink* (DL)

28/42/84Mbps (R7, R8, R9)

100 Mbps

1 Gbps

63 / 128 Mbps

1 Gbps

Max Uplink* (UL)

11 / 23 Mbps (R7, R8)

50 Mbps

500 Mbps

28 / 56 Mbps

500 Mbps

Max Latency (roundtrip)






Standards Body






Initial Standards

Release 7

Release 8

Release 10



Approx Year of Availability

2008 / 2009

2010 / 2011




Radio Access Methodology






Other Techniques

64QAM, 2x4 MIMO

64QAM, 4x4 MIMO

128QAM, 8x8 MIMO

64QAM, 4x4 MIMO

128QAM. 8x8 MIMO

US Operators

T-Mobile, AT&T

Verizon, AT&T (planned)


Sprint / Clearwire


*Note: data rates are best case and reduce as a function of distance from the cell site and overall radio environment

TABLE 1 General Aspects of 4G Network Candidates.

achieved within the same spectrum allocation. Each antenna transmits on its own carrier and is aggregated at the destination to provide the overall effective increase in throughput. Figure 2 shows a DL MIMO example. The more antennas employed the greater the multiplier. As is shown in Table 1, MIMO is a key component in candidate 4G networks with the most advanced networks, LTE-A and WiMAX 2, using up to eight DL and eight UL antennas. OFDM and OFDMA Orthogonal Frequency Division Multiplexing (OFDM) is not a brand new concept and, in fact, was first introduced in 802.11a to deliver 54 Mbit/s performance on Wi-Fi. At a high-level, OFDM allows for the transmission of modulated carriers (i.e., carriers with voice, data, etc. applied to them) close together but orthogonal to one another. By making the modulated carriers orthogonal, there is no longer a need to space them to avoid interference



and allow for filtering at the receive end. The net result of using OFDM is more data being transmitted over less spectrum— higher capacity with better spectral efficiency. Figure 3 illustrates how the radio interface has evolved from early mobile networks through 4G. All of the 4G technologies (barring HSPA+) use a form of OFDM. Orthogonal frequency division multiple access (OFDMA) is used by WiMAX 1 and 2 in both the DL and UL, while LTE and LTE-A use OFDMA in the DL and a modified form Single-Carrier FDMA. These are defined as follows: • Orthogonal Frequency Division Multiple Access (OFDMA) extends the concept of OFDM to support multiple users (i.e., multiple access). Multiple access is achieved by assigning subsets of subcarriers to individual users. • Single-Carrier FDMA is leveraged in the UL in LTE and LTE-Advanced as it provides a lower peak-to-average power ratio (PAPR) due to pre-processing of the

transmit symbols. The lowered PAPR on the UL allows for greater transmit power efficiency and lower terminal costs. This does not come without a cost, which is lower performance than OFDMA. All the 4G technologies utilize increasing levels of quadrature amplitude modulation (QAM). QAM is both an analog and digital modulation scheme. In its digital form, which is used in mobile broadband, it transmits multiple digital bit streams by changing (i.e., modulating) the amplitudes of multiple carriers at 90 degrees out of phase with each other. This can be visualized as a grid. The increasing level of QAM (i.e., 16, 64, 128, etc.) indicates a denser grid and, hence, a greater amount of data throughput. However, higher order schemes do result in a higher bit error rate, so 4G systems dynamically switch the coding scheme used based on the quality of the signal. If the signal is high quality then a higher order scheme is used and vice versa.

What Makes a Network Really 4G?

All 4G technologies use the same baseline techniques. However, LTE-Advanced and WiMAX 2 not only utilize OFDM, MIMO and higher order coding, but also stretch things further to deliver increased data rates and, most importantly, improved performance at the cell edge. The cell edge is where performance degrades to its lowest point due primarily to interference, but new techniques are being employed to deliver the best possible performance at the edge. The ITU IMT-Advanced standard, which governs the 4G designation, levies significant performance requirements on the network that can only be achieved through certain approaches. These include: carrier aggregation (both contiguous and non-contiguous), coordinated multi-point (CoMP) and intelligent relays. The first advance is carrier aggregation, which refers to combining multiple carriers (i.e., channels) to deliver greater throughput. The channels are combined at the physical layer, so they are transparent to the upper layers of the base station. However, the real advance in true 4G technologies is being able to aggregate non-contiguous carriers. The biggest chal-


lenge in delivering on the promise of ever increasing data rates in mobile networks remains the scarcity of spectrum. Carrier aggregation requires a lot of spectrum. By leveraging non-contiguous aggregation, operators can mass together previously disparate frequencies and use them to deliver a ubiquitous service throughout their coverage area. Secondly, and very important to performance at the cell edge, is CoMP. CoMP allows a UE to receive from and transmit to multiple base stations at the same time. This essentially turns the interference found at the cell edge into usable signal. Figure 4 illustrates the concept. Implementing CoMP requires significant coordination across the base stations and requires very fast and very detailed feedback on the channel properties. Finally, there are two modes of CoMP: • Joint simultaneous transmission of user data from multiple base stations to a single UE • Dynamic cell selection with data transmission from one eNB

Don’t miss Part 2 in the Ocotber issue of RTC magazine, which will more closely examine the candidates for true 4G and look at how they are poised to develop in the future. RadiSys Hillsboro, OR. (503) 615-1100. [].

The last tool used in LTE-A and WiMAX 2 is relay. The intelligent relays in these standards are, again, targeted at improving the performance at the cell edge. A relay receives, demodulates and decodes the data; applies any error correction; and then re-transmits a new signal. Essentially, it shows a base station interface toward the UE then re-transmits as a UE to another base station. This moves the “serving” base station, from a UE perspective, closer and allows for increased performance. These intelligent relays come in two primary flavors. Type 1 relays appear as a distinct base station to the UE. They control their own cell identity and transmission of their own synchronization channels and reference symbols. Type 2 relays appear as an extension of the primary base station. In this case the control information is sent directly from the primary base station while the relay processes and concentrates the user data. Type 2 relays will likely be deployed first as a method to increase the data capacity, while Type 1 will likely come later, increasing both the signaling and data capacity as the number of subscribers increases. Untitled-3 1


8/8/112011 9:26:12 AM RTC MAGAZINE AUGUST

products &

TECHNOLOGY Compact COM Express Module with Dual Core Atom and DDR3 Memory

A COM Express module in Compact form factor measures just 95 x 95 millimeters, and is fully compatible with the Type 2 pin-out of the PICMG COM Express specification. The Express-LPC from Adlink is positioned as an entry level, cost-effective module with a high performance-per-watt ratio (MIPS, FLOPS). It typically targets calculation-intensive applications such as robotics, test and measurement, entry level medical diagnostics and industrial automation. The ExpressLPC is an attractive replacement for existing Pentium Mbased designs, offering better performance at a lower price and much lower power envelope. The Express-LPC is based on the latest Intel Atom processors ranging from the dual core D525 at 1.8 GHz to the low voltage single core N455 at 1.66 GHz. The module supports up to 4 Gbyte of DDR3 memory on two SODIMM sockets. In addition to an increase in memory bandwidth compared with DDR2, the DDR3 memory support also brings a significant cost advantage and the certainty of reliable supplies well into the future. The module is equipped with integrated graphics support for analog VGA and LVDS. The module supports five PCI Express x1 lanes via the Intel I/O Controller Hub 8 Mobile chipset (ICH8M), one Gigabit Ethernet connection and three SATA channels. Legacy support is provided by a single Parallel ATA channel, 32-bit PCI bus and Low Pin Count bus (LPC). The Express-LPC is available with an onboard IDE-based Solid State Drive (SSD) up to 8 Gbyte, and comes standard with an integrated Trusted Platform Module (TPM 1.2) to provide secure storage of encryption keys for system and data protection. The module is equipped with AMIBIOS8, supporting embedded features such as Remote Console, CMOS backup, CPU and System Monitoring, Watchdog Timer and OEM Splash Screen. Optimized for portable and mobile applications, the BIOS supports ACPI-based Smart Battery functionality for single or dual battery subsystems. Single quantity pricing starts at $249. ADLINK, San Jose, CA. (408) 360-0200. [].

Rugged Miniature Automatic Video Tracker Integrates into SWaPConstrained Environments

A miniature rugged automatic video tracker is designed for the detection, surveillance and tracking of still or moving objects. The ADEPT3000 from GE Intelligent Platforms is designed as a low-cost solution for environments in which size, weight and power (SWaP) are highly constrained. These would typically include unmanned vehicles and man-portable devices, or integration directly into a gimbal. The ADEPT3000 is small (34 mm x 24 mm—approximately the size of a microprocessor), light weight (around six grams) and consumes little power (~1 watt). It is designed to complement the more powerful but less compact ADEPT5000 multi-target video tracker. Whether integrated in air-to-ground, ground-to-ground, ground-to-air or naval electro-optical systems, the improved algorithm at the heart of the ADEPT3000 provides effective detection and tracking of challenging objects in difficult environments. The ADEPT3000 supports standard definition analog video, and, once a target has been acquired, the resulting signal is passed to a sophisticated algorithm for track path analysis. GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [].



Ethernet Board Enables HighSpeed Long Distance Transfer

A rugged 3U CompactPCI Serial Ethernet Interface board accommodates four fiber optic Ethernet transceiver channels (1000Base-SX) for high-speed connections over extended distances up to 1,800 feet (550 m). Connected to the backplane via a PCI Express x4 link and managed by a single IEEE 802.3x-compliant Ethernet controller, the G211F from Men Micro offers four channels to provide data transfers of up to 1,000 Mbit/s when used simultaneously. To enable highly flexible configuration, the board accommodates a wide range of small form factor package (SFP) transceivers that are quickly and easily inserted into the card cage, which hosts the optical adapter. Each interface features LEDs to indicate link status and activity. The G211F supports both full and half duplex operation depending on the choice of transceiver, such as an LC-duplex available from Men Micro, covering a broad range of rugged, embedded applications requiring high-bandwidth capacities as found in transportation, avionics and mobile medical equipment. As an alternative to the four channels, the board can be configured with two redundant channel pairs for safety-critical applications. The G211F peripheral board can be used in both pure CompactPCI Serial systems as well as in hybrid systems that utilize CompactPCI PlusIO boards. The single-slot G211F extends the number of Ethernet interfaces on the system slot CPU. Screened operating temperature is -40° to +85°C excluding the transceivers. With a heat sink, the board weighs less than a half pound. It can withstand shock up to 50 m/s2(30 ms) and vibration up to 1.9 m/s2(5 Hz to 150 Hz) during operation in a maximum of 95% non-condensing humidity. At 40°C, MTBF is 311,742 hours according to IEC/TR 62380 (RDF 2000). Pricing starts at $644. MEN Micro, Ambler, PA. (215) 542-9575. [].


High Speed, Isolated, USB Data Acquisition Module with two Simultaneous A/D Channels at 10 MHz

A high-speed simultaneous USB data acquisition module features isolated, high-speed USB data acquisition at throughput rates up to 10 MHz. With the DT9862 from Data Translation, when two A/D channels are sampled simultaneously, both channels can acquire data at 10 MHz using burst sampling or at 5 MHz continuously. The only limit on throughput is the USB 2.0 bus speed, which has been optimized for the DT9862 to over 25 Mbyte/s. Each analog input channel has its own separate A/D converter eliminating phase shift between each channel—a problem with multiplexed architectures where all inputs share one common A/D converter. As a result, the DT9862 series can correlate measurements instantly. This overall throughput improvement represents a 5x increase in speed for the industry. The previous fastest isolated USB data acquisition module is the DT9832A at 2 MHz. Key design features of the DT9862 include 10 MHz sampling per a single channel, 10 MHz for burst sampling for both channels, or 5 MHz for two channels continuously, synchronous operation of all subsystems and two true 16-bit analog inputs for measuring multiple channels simultaneously. There are two optional 16-bit deglitched D/A channels for a simultaneous output rate of up to 2 MSamples/s with an output range of ± 2.5 V. The high-speed digital I/O lines are for time stamping, pattern recognition and synchronizing external events, and there are two 32-bit counter/timers along with flexible clock and trigger modes. Three 32-bit quadrature decoders allow for X/Y positioning and rotation and the unit comes with software and drivers compatible with Windows XP/Vista/7. Data Translation, Marlboro, MA. (508) 481-3700. [].

Gigabit Switch Supports Complex, Data-Heavy Industrial Networking Applications

A new Gigabit-only switch offers 16 combo ports for copper and/or fiber ports and optional Layer 3 switching software. With its advanced bandwidth capacity, the Magnum 12KX Gigabit Managed Switch from GarrettCom is a backbone switch with applications in areas such as power utilities, surveillance and security, transportation, and heavy industry. With Layer 3 switching capability, based on high-performance routing using Layer 3 addressing information, the 12KX will more rapidly route large amounts of data in applications using complex networking techniques such as VLANs or multicast routing strategies. The Magnum 12KX is substation hardened, able to withstand industrial environments with high EMI, extended temperature range and significant atmospheric contamination. It has a non-blocking switching fabric to provide wire-speed performance on all ports, has an option to configure four ports for Power over Ethernet (PoE), uses sealed-box convection cooling, and has optional single or dual internal power supplies. The 12KX switch can be synchronized via SNTP or IEEE 1588 v2 precision timing, the latter of which ensures accuracy within 30 ns on all ports. It addresses a variety of applications with environmental certifications including IEC 61850 and RoHS compliancy, and has low voltage DC as well as worldwide AC/DC voltage power input options. The GarrettCom Magnum 12KX Gigabit Managed Switch provides 16 combo ports with built-in small form factor pluggable (SFP) ports—allowing a choice of fixed 10/100/1000 BASE-TX connectivity or fiber SFPs, and has a temperature rating of -40° to +85°C. GarrettCom, Fremont, CA. (510) 438-9071. [].

Mini-ITX Board with Dual Core VIA Nano X2 E-Series

A Mini-ITX board features a Via Nano X2 E-Series dual core processor, which combines a high-performance 1.6 GHz 64-bit Via Nano X2 E-Series processor with the Via VX900 unified allin-one media system processor. The Via EPIA-M900 delivers a highly optimized platform that boasts comprehensive HD video performance, HD audio and HDMI support in a compact, power-efficient package. Measuring 17 cm x 17 cm, the Via EPIA-M900 Mini-ITX board features the 1.6 GHz dual core Via Nano X2 E-Series processor. The Via Nano X2 E-Series is combined with the Via VX900 MSP, supporting up to 8 Gbyte of DDR3 system memory and featuring the Via ChromotionHD 2.0 video processor. 64-bit Via Nano X2 E-Series dual core processors include Via VT virtualization, a technology that allows legacy software and applications to be used in virtual scenarios without impacting performance. The unique Via AES Security Engine offers hardware-based data encryption on the fly, an essential tool in content protection and system security. The Via ChromotionHD 2.0 video engine boasts hardware acceleration for the latest VC1, H.264, MPEG-2 and WMV9 HD formats at screen resolutions of up to 1080p without affecting CPU load. The Via EPIA-M900 also features the Via Vinyl VT2021 HD audio codec, which supports Blu-ray and HD DVD Audio Content Protection. Rear panel I/O includes a Gigabit LAN port, HDMI port, VGA port, four USB 2.0 ports, one COM port and three audio jacks. An onboard PCIe x16 slot (with effective speed up to PCIe x8) and one PCI slot is accompanied with pin headers providing one dual channel 24-bit LVDS support (including backlight control), an additional three COM ports, a further four USB 2.0 ports and one USB device port, LPC support, 2 Digital I/O, SPDIF out and an SMBus header. VIA Technologies, Fremont, CA. (510) 683-3300. [].




Low Cost, High Flexibility WiFi Client, Access Point, or 3G Router

A secure embedded wireless LAN module easily connects embedded devices to 802.11b/g Wireless LAN, 10/100BaseT wired LAN and cellular WAN. The Nano WiReach SMT from Connect One includes the iChip CO2144 IP Communication Controller chip and Marvell 88W8686 WiFi chipset. It is packaged in a 37 x 20 mm RoHS-compliant ultra-slim low-profile 44-pin SMT module form factor with an onboard or external antenna. Nano WiReach SMT simplifies adding Internet connectivity to embedded devices. It does not require any kind of WiFi driver development on the host CPU, and its multiple interfaces (UART, SPI, RMII and USB 1.1) minimize the need to redesign the host device hardware. Nano WiReach SMT supports several modes of operation. As an embedded router it provides routing facilities between a wired LAN subnet, a WiFi subnet and a cellular WAN connection. It includes a DHCP server, NAT and port forwarding. As a LAN to WiFi Bridge it allows transparent bridging of LAN over WiFi, using direct RMII connection to existing MAC hardware. This allows any microcontroller with a built-in Ethernet MAC to be connected to WiFi, with zero development effort. It can also act as a serial to WiFi ridge allowing transparent bridging of serial over WiFi, using the module’s 3 Mbit/s fast UART. PPP emulation mode allows existing (e.g., cellular modem) designs currently using PPP to interface to the cellular modem to connect transparently over WiFi with no changes to application or drivers. The Nano WiReach SMT also supports a full Internet controller mode, which allows a simple MCU to use its rich protocol and application capabilities to perform complex Internet operations such as E-mail, FTP, SSL, embedded web server and others. Internet controller mode can be used with any hardware interface. Nano WiReach SMT includes RMII, USB, SPI and fast UART interfaces for easy integration into existing or new designs. It offers a highly advanced level of Internet security, including the latest WiFi encryption algorithms (WPA/WPA2, in both PSK and Enterprise modes) and Internet SSL encryption algorithms. In addition, it serves as an inherent firewall, protecting the embedded application from attacks originating from the Internet. Connect One Semiconductors, San Jose, CA. (408) 572-5675. [].

7400 MHz SMT Frequency Synthesizer Featuring Low Phase Noise

The UPN-7400 from EM Research is a surfacemount frequency synthesizer featuring exceptionally low phase noise (-102 dBc/Hz @ 10 KHz), utilizing a 100 MHz external frequency reference, offering +6 dBm output power from a +5 VDC supply drawing 200 mA current. The unit is available in a cost-effective, miniature surface-mount package of 0.90” x 0.90” x 0.15” (22.9 mm x 22.9 mm x 3.8 mm), which makes it suitable for SATCOM, radar and electronic warfare applications. The UPN Series can be custom-designed to offer fixed or serially programmable frequencies up to 10 GHz with extended temperature ranges, high vibration tolerance, up to +13 dBm output power and internal or external references. EM Research Reno, NV. (775) 345-2411. [].



IP65-Rated Panel PC Family for Demanding Industrial Applications

Four new industrial-grade Panel PCs are available with 12-, 15-, 17- or 19-inch diagonal displays and touch screens. The PPC65 family of Panel PCs from WinSystems is powered by a fully integrated 1.6 GHz Intel Atom-based single board computer (SBC), which offers a wide variety of I/O connectivity options. The front bezels on these Panel PCs are environmentally sealed to comply with NEMA 4/IP65 specifications to prevent damaging moisture, dust and dirt from getting into it. WinSystems’ PPC65 family of Panel PCs has design features that allow each unit to meet and exceed industry standards for RF emissions, conducted susceptibility and shock/vibration. The PPC65s have been tested for electrical and electromagnetically induced or radiated interference that could possibly degrade their performance when electronic and electrical systems are in close proximity and confined spaces. They comply with IEC 61000 electrical fast transient, surge, drop in power, conducted susceptibility and conducted immunity tests. Also the PPC65 product family of products is tested and compliant with FCC Part 15 B and CE EMC Directive 2004/108/ EC. They can also withstand 1.0G vibration and 15Gs of shock. The PPC65 products support operating systems such as Linux, Windows XPe, CE 6.0, WES7, and Windows 7. The SBC includes 2 Gbyte of system memory with either or both an optional customer-installed SATA drive and CompactFlash SSD. I/O support includes a Gigabit Ethernet port, four USB 2.0, and two RS-232 serial channels. The system requires +12V dc but a version that accepts +24V to +48V dc is also available. The PPC65-1210S2G-0 is a unit with a silver bezel and 12.1-inch screen with a list price of $1,395. WinSystems, Arlington, TX. (817) 274-7553. [].


High Performance ADC/DAC Module—Compact, Flexible and Cost-Effective

Designed to act as a powerful link between the analog world of sensors and the digital world of computing, a new XMC module can be deployed in demanding radar, signals intelligence, communications and test and measurement applications. The ICS-1572A ADC/DAC from GE Intelligent Platforms features 16-bit data acquisition at up to 250 MHz and the latest Xilinx Virtex-6 FPGA processor to deliver unprecedented performance in a cost-effective, compact, lightweight form factor. Not only does the XMC form factor allow for more compact solutions—it also allows for higher throughput to the host memory, which translates into the ability to send higher bandwidth signals for downstream processing. The higher sampling rates allow for higher instantaneous bandwidth to be captured, therefore meeting the challenging frequency coverage requirements of surveillance systems. The use of high-speed DDR3 memory allows for deep waveform storage and tolerates the interrupt latency associated with non-real-time operating systems. The ICS-1572A provides two 16-bit ADCs sampling synchronously at frequencies up to 250 MHz and two 16-bit DACs at up to 500 MHz. The ADC input pass band is 4.5 to 800 MHz (3 dB) to allow for under-sampling applications. A Xilinx Virtex-6 LX240T FPGA is provided for user-defined signal processing functions, giving greater capacity than previous generations; other Virtex-6 devices are available as options. The Virtex-6 device also provides a PCI Express interface to the host system. Other protocols, such as Serial RapidIO, can be provided upon request. The FPGA provides a powerful signal processing capability that can be loaded with standard functions such as wideband DDC, FFT and time stamping, or programmed by the user for any required function. Get Connected with technology and GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. []. companies providing solutions now

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Advanced Development Kit for High-Quality Digital Audio

A 32-bit microcontroller (MCU)based development kit for the creation of high-quality, 24-bit audio applications features an 80 MIPS PIC32 MCU, a 24-bit Wolfson audio codec, a two-inch color LCD Display, a USB interface and an onboard microphone. Supported by free software libraries, the Audio Development Board for PIC32 MCUs from Microchip Technology provides a solution for the development of speech and audio recording and playback products. Target applications include docks for portable audio players, home-entertainment systems and automotive sound systems. The 80-MIPS PIC32MX795F512L MCU on the audio development board features 512 Kbyte flash and 128 Kbyte RAM, providing plenty of processing power and memory to decode, analyze and playback audio and speech. Libraries are available for speech recording and playback, as well as MP3 music decoding applications. Additionally, an audio Sample Rate Conversion (SRC) library for 33 kHz, 44.1 kHz and 48 kHz is also supported. This enables developers to reduce component costs for playback solutions. There are also libraries available for managing the USB interface and driving the onboard color LCD display, which features 16-bit color images. For those developers who are enrolled in the Apple Made For iPod (MFi) Licensing Program, the kit also interfaces to Microchip’s accessory development platform for iPod and iPhone. The Audio Development Board for PIC32 MCUs is available today for $149.99 Microchip Technology, Chandler, AZ. (480) 792-7200. [].

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal Industrial Embedded Card Takes Shock, is toSD research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the Vibration and Temperatures goal of Get Connected is to put you in touch with the right resource. A new industrial Whichever level of service you require for whatever type of technology, SD card from Apacer GetisConnected will help you connect with the companies and products you are searching for. designed for embedded systems in harsh storage environments. Features include high reliability, high storage and resistance to extended temperatures. These advantages enable the new card to be widely applied to industrial, military, communication, surveillance, medicaland devices Get Connected with technology companies prov and car navigation, thereby theisstorage need of demanding Getsatisfying Connected a new resource for further exploration into pro industrial enterprises. datasheet from a company, speak directly with an Application Engine touch with the right Whichever level of service you requir Compliant with Ver.in2.0 standard and resource. SDHC Class 10 high-speed Get Connected will help you connect with the companies and produc transmission standard as defined by the SD Association, the new SD card from also supports SD and SPI modes. By using the reliable SLC chip, it not only delivers the features of anti-shock, anti-vibration and low power consumption, but also boasts resistance to extended temperatures (-40° to 85°C). Available in capacities from 256 Mbyte to 8 Gbyte, the new SD card can substantially accelerate data transfer, due to its sequential read/write speed reaching up to 20/13 Mbyte per second. It is also worth noting that the card’s automatic standby and sleep modes help save power more effectively. For the just-launched SD card, Apacer also introduces MLC (Multi-Level Cell) flash memory offerings. Boasting the sequential read/write speed of as fast as 19/8 Mbyte per second, the product is available from 4 Gbyte to 32 Gbyte in capacities. To ensure that data Get companies and stay correct, theConnected industrial SDwith card supports 24-bit ECC function, which products featured in this section. minimizes potential errors led by frequent data access to strengthen the system reliability. Also complete with integrated Global Wear leveling and S.M.A.R.T technology, the SD card features a prolonged lifespan as well as safer data storage.


Apacer Technology, Taipei, Taiwan. []. Get Connected with companies and products featured in this section.




Next Generation Wireless Server Supports New Software Development Kit

A next-generation wireless server allows design engineers and original equipment manufacturers (OEMs) to easily add Wi-Fi and Ethernet networking to virtually any device. The PremierWave EN from Lantronix is a Linux-based device server that offers secure, high-quality wireless connectivity that enables companies across a variety of industries to securely transmit medical, financial, customer or other important data across corporate networks. Also available with this release is an embedded Linux development offering from Timesys, provider of easy-to-use and affordable embedded Linux development products and professional services. The software features valuable Lantronix applications including a tunneling application, a core Lantronix technology that offers a rich set of configuration options for making serial device data available over wired and wireless networks. There is also a secure tunneling application, which extends the standard tunneling technology via numerous standard and secure network connectivity options. In addition, a configuration manager offers an enterprise class command-line interface (CLI) for managing the device, and XML configuration facilitates the update of multiple units using a standard configuration. A rich set of system level and diagnostic utilities simplify field deployment and remote management, and Ethernet-to-wireless LAN Bridging provides seamless wireless connectivity for wired Ethernet devices with high data packet forwarding performances while Virtual IP (VIP) Access allows remote connectivity behind firewalls. The PremierWave EN also offers a subscription to LinuxLink, Timesys’ embedded Linux software development framework that eliminates the learning time, complexity and risk in building and maintaining embedded Linux products, and helps developers reduce time-to-market. LinuxLink for PremierWave EN offers the ability to quickly assemble and boot an initial embedded Linux image on a PremierWave EN development kit. It enables you to patch, configure, rebuild and update a custom Linux platform on a desktop with a properly installed and configured development environment. It also enables debugging and tuning the platform with common open source development tools and development libraries/utilities and provides access to Timesys professional services to meet tight time and budget targets Lantronix, Irvine, CA. (949) 453-3990. []. Timesys, Pittsburgh, PA. (412) 232-3250. [].

Rugged Solid-State HD Video Data Recorder with up to Three Hours on CompactFlash

In the latest addition to its family of rugged video recorders, Curtiss-Wright Controls Embedded Computing has introduced the Skyquest VRDV-5002 High Definition Video Recorder. The VRDV-5002 is a compact, lightweight, high-definition (HD) video recorder that features a solid-state low-cost CompactFlash-based storage system and supports video and/or audio capture and playback during the mission. The VRDV-5002 is designed for use in applications that require optimal performance in harsh environments, including extreme temperature, high shock and vibration conditions. It speeds and simplifies the integration of high-performance HD video recording into space, weight and power (SWaP)-constrained airborne and ground military, paramilitary, and search & rescue platforms. The VRDV-5002 delivers industry leading, broadcast quality MPEG2 recording onto one or two CompactFlash cards, to deliver up to >3 hours of full quality recording capability. The lightweight, compact VRDV-5002 is housed in a rugged all-aluminum chassis with simplified Dzus fasteners. Designed for SWaP-constrained applications, the VRDV-5002 measures 146 mm x 56 mm x 256 mm and weighs 1.5 kg. The unit supports a single channel HD-SDI input and output. Curtiss-Wright Controls Embedded Computing, Auburn, VA. Tel: (613) 254-5112. [].



iOS App for Automation and Control Systems

Opto 22 has introduced the Opto iPAC iOS App, which offers access to the company’s SNAP PAC System via popular mobile devices including the iPhone, iPod Touch and iPad. The app makes detailed, realtime, control system information quickly and easily accessible to authorized control engineers, maintenance personnel, instrumentation technicians, panel builders, developers and others through their mobile and tablet devices. Now these automation and control professionals can view, debug and fine-tune their wirelessly accessible control and I/O systems, saving time and money during installation, commissioning and ongoing maintenance. Using the Opto iPAC application, devices running iOS (Apple’s mobile operating system) can discover any wirelessly accessible SNAP PAC programmable automation controllers (PAC) and I/O systems on the control system network. Authorized Opto iPAC users with proper security credentials can inspect SNAP I/O points and PAC Control strategy variables, and execute control functions such as turning digital output points on or off, writing values to analog outputs, and changing control variables and table entries. Specific I/O points and tagnames can be retrieved, viewed and saved to a Watch List for quick future reference. Also, Opto iPAC users can start or stop any flowcharts running within their control strategies. The mobility enabled by Opto iPAC creates new opportunities for control system diagnostics, maintenance and troubleshooting. Engineers and technicians carrying their mobile device in the field or on the plant floor can inspect their SNAP PAC System controllers and I/O processors, view any control strategies running or saved on their controllers, check firmware, and perform other functions that could otherwise only be accomplished from a PC running Microsoft Windows-based PAC Project software. The Opto iPAC application is available for download now from the Apple iTunes Store at a cost of $4.99. Opto 22, Temecula, CA. (951) 695-3000. [].


Dual Core Mini-ITX Main Board Supports High-End Graphics

Coupling a 1.6 GHz VIA Nano X2 E-series processor with the VX900 media system processor, the new VB8004 Mini-ITX main board from Via Technologies provides a high-performance and highly scalable solution for advanced digital signage and gaming systems. In addition to providing native support for dual-displays, the VB8004 Mini-ITX main board can also be easily upgraded to support four displays using an additional VIA S3 5400E graphics module, providing developers the widest possible variety of multidisplay configurations, including HDMI, LVDS and DVI technologies. Powered by a choice of a 1.6 GHz VIA Nano X2 E-Series, or 1.6 GHz and 1.2 GHz VIA Nano processors, the VB8004 leverages the advanced multimedia capabilities of the VX900 system media processor to deliver awesome DX10.1 graphics and support for rich 1080p video resolutions. In addition to supporting up to 4 Gbyte DDR3, the board features rich I/O capabilities including an HDMI port, one DVI port, a one channel 24-bit LVDS, one GigaLAN port and six USB 2.0 ports. The VIA S3 5400E dedicated graphics module is a daughter card specially designed to provide advanced multimedia capabilities for next-generation embedded applications. With support of DX10.1, Shader Model 4.1, OpenGL 3.1 and OpenCL 1.0, the 5400E GPU provides a cost-effective solution for feature-rich graphics processing with high levels of video decoding and 3D rendering performance. Featuring the ChromotionHD 2.1 video engine, a programmable video architecture supporting the latest HD standards including Blu-ray Disk, H.264, VC-1, WMV-9 and MPEG-2/4, the S3 5400E module offers stunningly smooth HD playback at resolutions of up to 2560 x 1600 pixels. Onboard I/O includes one HDMI port and one DVI port.

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VIA Technologies, Fremont, CA. (510) 683-3300. [].

Virtex-5 AMC with FMC Module Slot

A standard single mid-size or full-size AMC module comes with the choice of a user-programmable LX50T, LX85T, or SX50T Virtex-5 FPGA. The TAMC640 from Tews Technologies provides a number of advantages including a customizable interface for unique applications and a FPGA-based design to extend product lifecycle. The integrated PCIe Endpoint Block of the Virtex 5 can be used to build an x1, x4 or x8 PCIe link via AMC Port 4-11. In addition, the implementation of other protocols like SRIO or XAUI is possible. AMC Ports 0 & 1, commonly used for Gigabit Ethernet, are also connected to the FPGA. The integrated Gigabit Ethernet MACs of the Virtex-5 allow fast and easy protocol implementation. To allow direct board-to-board communication, AMC Ports 12-17 are connected to Virtex-5 I/Os, allowing AC-coupled LVDS communication with a port speed up to 1.0 Gbit/sec. For flexible front I/O solutions, the TAMC640 provides a VITA 57.1 high pin count FMC Module slot, allowing active and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the flexibility of the Select I/O technology of the Virtex-5 FPGA. Additionally the FPGA is connected to two banks of DDR2 DRAM and 1 bank of QDR-II SRAM. Multiple clocks from the AMC-interface, the FMC and from onboard sources are supplied to the FPGA. Configured by a flash device, the FPGA is in-system programmable and able to store multiple code versions. For security, the TAMC640 supports encrypted FPGA bitstream usage. Encrypted FPGA bitstreams cannot be copied or reverse engineered. User applications can be developed using the design software ISE WebPACK from Xilinx. Tews Engineering Documentation TAMC640-ED for FPGA programming includes all information needed for customer-specific FPGA programming with additional Constraints Files. The FPGA Development kit TAMC640-FDK provides ucf-files and well documented VHDL example applications. For OS level support, Tews offers extensive software support for major operating systems such as Windows, LynxOS, Linux, Integrity, VxWorks and QNX. TEWS Technologies, Halstenbeck, Germany. +49 (0) 4101-4058-0. [].

Get Connected with technology and

AdvancedMC Processorcompanies Moduleproviding with Freescale solutions now Get Connected is a new resource for further exploration QorIQ P2020

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A new single-width Adis to research the latest datasheet from a company, speak directly vancedMC processor module, with an Application Engineer, or jump to a company's technical page, the the AM4120, is the first member goal of Get Connected is to put you in touch with the right resource. of a new Kontron AdvancedMC Whichever level of service you require for whatever type of technology, product family withGet theConnected Frees- calewill help you connect with the companies and products you are QorIQ processors. Thesearching new for. vancedMC family is targeted to costsensitive applications as well as powerful data plane and control plane applications. The Kontron AM4120 is equipped with the Freescale QorIQ P2020 Dual Core processor with up to 1.2 GHz and based on the Power Architecture e500. Application reliability feaConnected withU-Boot technology and companies prov tures include the redundantGet universal bootloader and persistent memory for cycle data storage. Furthermore, dedicated Module Get Connected is a anew resource for further Manexploration into pro datasheet a company, speak directly with an Application Engine agement Controller (MMC), whichfrom supports basic IPMI commands, is in touch with theoperators right resource. Whicheverthe level of service used for board management, enabling to monitor status of you requir Get Connected will help you connect with the companies and produc the module in the system, simplifying system management and ing availability. The Kontron AM4120 also offers increased longevity due to Freescaleâ&#x20AC;&#x2122;s processor availability until at least 2018, careful component selection, and a Micro SDHC card socket that is not impacted by regular flash discontinuation. For flexible data exchange, the Kontron AM4120 features 4x SERDES lines routed to AMC ports 4 - 7, which are configurable either as PCIe (root complex or end point) or SRIO ports (host or agent), for applications that require close programming to the chip without extensive overhead. This provides several different boot options for the OS including from an easily exchangeable Micro SDHC card to simplify updates, a NOR Flash, or the soldered NAND Flash for rugged applications. For further flexibility in inter- and intra-system communication, Get Connected with companies and which are routed to AMC the AM4120 supports up to 3x GbE channels, products featured in this section. port 0 plus 2x RJ45 interfaces at the front or routed to AMC ports 0 and 1 plus one port at the front. The Kontron AdvancedMC AM4120 supports Bootloader U-Boot, IPMI, VxWorks 6.9 and Linux LTIB.


Kontron, Poway, CA. (888) 294-4558. []. Get Connected with companies and products featured in this section.



3U CompactPCI & FPGA Showcase Featuring the latest in 3U CompactPCI & FPGA technologies Commercial & Rugged Altera Stratix® IV GX 3U VPX Board with Optional High-speed Data Conversion

BittWare Phone: (603) 226-0404 Fax: (603) 226-6667

High density Altera Stratix IV GX supported by BittWare ATLANTiS™ FrameWork for FPGAs BittWare FINe™ Host/Control Bridge provides control plane processing and interface Fully connected to VPX: GigE, 15 SerDes, 32 LVDS Additional I/O: 10/100 Ethernet, RS232, JTAG Several data conversion options E-mail: Web:

Dual Altera Stratix® IV FPGA AdvancedMC with Optional High-speed Data Conversion Dual FPGAs: Altera Stratix IV E and Stratix IV GX supported by BittWare’s ATLANTiS™ FrameWork BittWare’s FINe™ III Host/Control Bridge provides control plane processing and interface AMC I/O: 18 ports SerDes, 1 port GigE Additional I/O: 10/100 Ethernet, 16 GPIO, RS-232, and JTAG Several data conversion options

BittWare Phone: (603) 226-0404 Fax: (603) 226-6667

3U cPCI, cPCI Express, cPCI Serial, and cPCI PlusIO Backplanes

CPCI7203 3U Processor Board Intel® Core™ i7 dual-core integrated processor (up to 2.0 GHz) Up to 8GB ECC-protected DDR3800/1066 (soldered) Front panel I/O includes VGA, GbE, USB 2.0 (air cooled only) Rear I/O includes VGA, GbE, USB 2.0, SATA, UART, PCI Express Air and conduction cooled Extended temperature -40°C to +85°C Optional solid state hard drive on conduction cooled variants

3U EasyCable cPCI with power bugs on side for cabling ease 3U EasyPlug cPCI with 47-pin pluggable connectors 3U 32-bit cPCI versions 3U Low Profile cPCI with power studs between slots, saving space 3U cPCI Express, Serial, and PlusIO versions – contact us for details

Elma Bustronic Phone: (510) 490-7388 Fax: (510) 490-1853

ETI Phone: (888) 444-1644 Fax: (781) 963-7203

Emerson Network Power E-mail: Web:

Phone: (800) 759-1107 or E-mail: Web: (602) 438-5720

XTECH Aluminum Enclosures for Small Form Factors

F21P3U CompactPCI PlusIO (PICMG 2.30) SBC

Electronics are getting smaller and performance/uptime more critical - therefore you need a robust packaging solution which provides the protection you need in addition to the secure board and component mounting needed for challenging environments. XTECH’s offering of standard aluminum enclosures – which can be customized to meet your requirements - provide a robust and stable mechanical solution. Give us your PCB layout for a custom solution or pick from our standard options.

MEN Micro’s F21P, a 3U CompactPCI PlusIO SBC for embedded systems using legacy CompactPCI, high-speed CompactPCI Serial or a combination of both, is equipped with the latest 64-bit and quad-core Intel i7 processor running at 2.1 GHz for applications with demanding graphics requirements.

E-mail: Web:

MEN Micro Phone: (215) 542-9575 Fax: (215) 542-9577

Model 74640: 6U cPCI Board with 3.6 GHz 12-bit A/Ds and Virtex-6 FPGA

Pentek, Inc. Phone: (201) 818-5900 Fax: (201) 818-5904

E-mail: Web:

One-channel mode: two 3.6 GHz, 12-bit A/Ds Two-channel mode: four 1.8 GHz, 12-bit A/Ds Supports Xilinx Virtex-6 LXT and SXT FPGAs 2 GB DDR3 SDRAM Clock/sync bus for multiboard synchronization Also available in 3U cPCI format: Model 73640 E-mail: Web:

E-mail: Web:

PCI Brackets Quick Turn PCI Brackets from Purcell in 7-10 Days! Get your prototypes done now with engineering design assistance, laser etching, and silk screening — all at a competitive price. Use our database of standard products, add your cutouts, and you’ll get a quote in 1 business day and the products 7-10 days.

Purcell Technologies Phone: (888) PBI-8500 Fax: (925) 513-1370

E-mail: Web:


Smart Meter Interoperability Easy with DLMS User Association Certified Stack

A Device Language Message Specification (DLMS) protocol stack that is optimized for 16-bit PIC microcontrollers (MCUs) is the result of a partnership between Microchip Technology and Kalki Communication Technologies. The DLMS protocol has become the worldwide standard of choice among smart meter designers for interoperability among metering systems, including most energy types (electricity, gas, heat and water), multiple applications (residential, transmission and distribution), and numerous communication media (RS-232, RS-485, PSTN, GSM, GPRS, IPv4, PPP and PLC); as well as secure data access, via AES 128 encryption. This software stack has been tested and verified by the DLMS User Association, and is customized to operate on all of Microchip’s 16-bit PIC microcontrollers and dsPIC Digital Signal Controllers (DSCs), making the DLMS certification process faster and easier. Additionally, the stack has been developed to ensure seamless integration with Microchip’s communication protocol stacks, including TCP/IP, ZigBee and PLC, covering a broad spectrum of smart energy applications. Furthermore, this DLMS stack has been optimized to fit in a small memory footprint, enabling the use of the smallest, most costeffective MCUs possible. For European applications, the stack provides support for the required IEC 62056-21 Mode E implementation. Customers can use the Explorer 16 development board to design their DLMS solutions, based on Microchip’s wide portfolio of industry-leading 16bit MCUs and DSCs. The Explorer 16 is available today for $129.99 each. The new DLMS stack is available today, in the following four flavors: The DLMS Evaluation Library for 16-bit MCUs is a free evaluation version of the DLMS library. The DLMS-lite Stack for 16-bit MCUs starts at $3,900 for 5k units. The DLMS Stack for 16-bit MCUs starts at $4,800 for 5k units. Finally, the DLMS Explorer is a Windows-based DLMS/COSEM client application, and it is available for $2,800 each.

Ultra Low Latency, High Definition Encoder Card on PCI/104

A high-performance, ultra low latency H264 Encoder is available on a single PCI/104 form factor board. The H264-HD2000 from Advanced Micro Peripherals allows system builders to easily add high definition analog and digital video capture with H.264/MPEG-4 AVC (Part 10) encoding to their embedded PC equipment designs. The powerful encoding engine supports ultra low latency full frame rate encoding of two HD video sources at up to 1080p30. The H264HD2000 can also do a single channel encode at full 1080p60 and perform stream duplication of the Digital Video input to provide multiple encodings of the same input. This allows streams to be created at different resolution, compression settings dependent on requirements and available bandwidth. The H264-HD2000 accepts both analog and digital video input. Digital video is received from DVI/HDMI sources at a full range of resolutions from 480p60 up to 1080p60. High definition (HD) analog video data can be taken from YPbPR, RGsB (Sync on Green) or VGA (separate HSync, VSync). The H264-HD2000 is also available with extended temperature range options (-40° to +85°C) and a long-term availability. The card is supported on a range of Operating Systems including Windows, Linux and QNX. Other embedded operating systems may be supported upon request. Advanced Micro Peripherals New York, NY. (212) 951-7205. [].

Microchip Technology, Chandler, AZ. (480) 792-7200. [].

3U CompactPCI & FPGA Showcase Featuring the latest in 3U CompactPCI & FPGA technologies Device Server

Radicom Research, Inc. Phone: (408) 383-9006 Fax: (408) 383-9007

Serial-to-Ethernet Modules Available Serial TTL or RS232 interface 3.3V, 48V or Power-over-Ethernet (PoE) support IEEE802.3 compliant 10/100BaseT network interface, auto detect TCP/IP, UDP, Telnet, HTTP, IGMP and ARP support DHCP and static IP support LED pin for monitoring LAN and link activity DTE data speed up to 230k bps Hardware and software flow control RoHS compliant E-mail: Web:

Embedded Modem Modules, the Half-Inch Modems Serial TTL interface -40C to +85C operating temperature Compact size: 1” x 1” x 0.2” up to 56K bps data rate 14.4K bps fax, voice AT command DTMF, ring and Caller ID detection Transferable FCC68, CS03, CTR21 telecom certifications Global safety: c/UL, IEC60950-1, IEC60601-1 (Medical) approved CE marking

Radicom Research, Inc. Phone: (408) 383-9006 Fax: (408) 383-9007

E-mail: Web:

with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




3U CompactPCI & FPGA Showcase.......... 60, 61..............................................................

ADLINK Technology America, Inc.................





Logic Supply, Inc........................................ 34................................

Measurement Computing Corporation.........

End of Article

Advanced Micro Devices, Inc...................... 64..........................................

Men Micro, Inc........................................... 40.............................................

Get Connected with companies and Advantech 29................................. productsCorporation............................... featured in this section.

MILESTONE............................................... with companies mentioned in this article.

Avalue Technology...................................... 49................................


Cogent Computer Systems, Inc................... 44...................................

Get Connected with companies mentioned in this article. One Stop Systems. .....................................

Get Connected with companies and products featured in this section.

Get Connected Diamond Systems......................................

Pentek, Inc..................................................

Elma Electronic, Inc....................................

Phoenix International................................... 4.....................................

Extreme Engineering Solutions, Inc............. 11..........................................

RTECC....................................................... 45.........................................

Innovative Integration.................................. 24...........................

Sealevel Systems, Inc.................................

Interface Concept.......................................

Tech Design Forum..................................... 35......................

Jayco Panels.............................................. 41...............................

The Mathworks, Inc..................................... 2.................................

JumpGen Systems.....................................

VersaLogic Corporation..............................

LiPPERT Embedded Computers, Inc............


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When You’re At 30,000 Feet Quality Matters Our products and service are second to none Photo Credit: U.S. Air Force photo by Staff Sgt. Samuel Morse (Released)


t VersaLogic we know about building dependable, high reliability embedded mbedded b computers p for mission critical applications. Our products have been designed into some of o the most sophisticated and high prole military and aerospace equipment used today. Every board we make is run through exhaustive inspections and quality tests, ensuring that we deliver only the best. And with our world class service and ve year availability guarantee, we’ll always be there when you need us. Whether you need one of our standard products or a specially customized version, our skilled technical staff will work with you u to meet your exact specications. So before your program launches, choose se the company with the quality and service to take you where you need to go. o o. With more than 30 years experience delivering extraordinary support and d ontime delivery, VersaLogic has perfected the ne art of service: One customer m at a mer time. Contact us today to experience it for yourself. Recipient of the Platinum Vendor Award for 5 years running!

1-800-824-3163 | 1-541-485-8575 |

AMD is ushering in a new era of embedded computing. The AMD Embedded G-Series processor is the world’s first integrated circuit to combine a low-power CPU and a discrete-level GPU into a single embedded Accelerated Processing Unit (APU). Unprecedented level of graphics integration High performance multi-media content delivery Small form factor and power efficient platform Learn more about new levels of performance in a compact BGA package at : Stop by AMD’s booth (#801) at ESC Boston to learn first-hand about this new APU (accelerated processing unit) architecture and how it can be leveraged to help you deliver innovative low-power and value-oriented solutions for a variety of embedded applications. ©2011 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. DirectX is a registered trademark of Microsoft Corporation in the United States and other jurisdictions. Other names are for informational purposes and may be trademarks of their respective owners.

RTC magazine  

August 2011

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