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The magazine of record for the embedded computing industry

June 2011

Software Defined Radio to Aid First Responders PCI Express Links up with DSP Hybrid CPUs Challenge Supercomputers An RTC Group Publication


fully-assembled turnkey solutions Run, drive, or fly your Simulink design in real time, using Rapid Prototyping or Hardware-in the-Loop simulations on low-cost PC-based hardware. xPC Target provides a library of device drivers, a real-time kernel, and an interface for monitoring, parameter tuning, and data logging. It supports a full range of standard IO modules, protocols, and target computers.

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Find it at datasheet video example trial request


Simulink and xPC Target™


©2010 The MathWorks, Inc.



A New Technology Infrastructure

47 Gang Tester Improves Efficiency During Boundary Scan in Mass Production

48 14-Bit PCIe Digitizer Offers High Data Throughput and High Dynamic Performance


50 Managed OpenVPX 10 Gigabit Ethernet Switch for High Performance Applications



6Editorial The Smart Grid: A Huge Task with Huge Opportunities 8

Industry Insider Latest Developments in the Embedded Marketplace

Form Factor Forum 12Small Head Transplant & Technology 46Products Newest Embedded Technology Used by Industry Leaders

EDITOR’S REPORT The Promise of the Smart Grid

Smart Grid: The Advent of a 14The New Technology Infrastructure Tom Williams

Technology in Context


Platform Management with Customizable Microcontroller

Embedded Technologies for the Smart Grid

a Microcontroller for Embedded 18 Customizing 30Synchronized Hardware Platform Management Intelligence Enables the Smart Grid Mark Overgaard, Pigeon Point Systems and Hichem Belhadj, Microsemi

TECHNOLOGY CONNECTED New Roles for Wireless Connectivity

Defined Radio: The Key 22 Software to Public Safety Radios Rodger H. Hosking, Pentek

Andre Marais, Symmetricom

Grid Security: Less Bruce 34Smart Willis, More Ben Franklin Robert Vamosi, Mocana

and Improving the Smart 38Securing Grid Requires Military Grade Technology Jim McElroy, Green Hills Software

TECHNOLOGY IN SYSTEMS Hybrid and Multicore Processors

Performance on 26 Supercomputer a Chip Powers Next-Generation Embedded Image Processing Dr. Vijay Reddi, Advanced Micro Devices

Industry watch PCI Express Meets DSP

with PCI Express Interface Expand Embedded Connectivity 42DSPs Options Krishna Mallampati, PLX Technology

Digital Subscriptions Avaliable at RTC MAGAZINE JUNE 2011


JUNE 2011 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

Art/Production CREATIVE DIRECTOR Jason Van Dorn, ART DIRECTOR Kirsten Wyatt, GRAPHIC DESIGNER Christopher Saucier, GRAPHIC DESIGNER Maream Milik, LEAD WEB DEVELOPER Hari Nayar,

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The magazine of record for the embedded computing industry

The magazine of record for the embedded computing industry

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To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, Editorial Office Tom Williams, Editor-in-Chief 1669 Nelson Road, No. 2, Scotts Valley, CA 95066 Phone: (831) 335-1509

Published by The RTC Group Copyright 2010, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.







Tom Williams Editor-in-Chief

The Smart Grid: A Huge Task with Huge Opportunities


ould it be bigger than the Internet? That is now one of the credible predictions that are growing up around the build-out of the Smart Grid. Some time ago, Cisco was predicting a $100 billion market with some $20 billion annual opportunity over five years for the communications portion alone. Gradually but inexorably the overhaul of the nation’s energy distribution system is drawing the attention of major players such as Cisco and Intel as well as sparking the creativity of smaller entrepreneurs and start-ups. All this appears to be starting to happen without the massive government direction and subsidies that many had expected or feared. The opportunities for electronics vendors and embedded systems involvement are—as we have noted previously—enormous. And it is happening in the face of what has the reputation of being an industry most resistant to change, the electric power industry. The emergence of a basic infrastructure can be the catalyst for the growth of countless new ventures and technologies that can work in synergy with it. We have seen this in the case of the Windows operating system and, of course, with the Internet. Such a phenomenon appears to be shaping up for the Smart Grid as well. A recent report from IBISWorld has identified the ten fastest growing industries. First in line is VoIP providers such as Skype, which was recently acquired by Microsoft. In third place is wind power, and number ten on the list is solar power. According to IBISWorld Senior Analyst Casey Thormahlen, “Each industry on the list experienced growth as a result of one or more of four drivers: Internet growth, environmental issues, cost cutting and evolving technology.” I would suggest that the nascent growth of the Smart Grid is at least encouraging investment in wind and solar as well. Wind power, for example, had generated revenues of $12.5 billion in 2010 with revenue growth for the next five years projected at 17.4%. But wait. There’s more. One of the promises of the Smart Grid, in addition to an advanced metering infrastructure (AMI), increased robustness and the ability to monitor and conduct the distribution of electricity, is time-of-day pricing so that users can schedule things like run-



ning washers and dryers for times when the rates are lower. This will lead to the development of smart appliances that will connect to and monitor the grid to know when to turn on. Estimates are that the market for such smart appliances will grow from a little over $3 billion today to well over $15 billion in the next four years. All of them will incorporate embedded control and connectivity. Semiconductor vendors such as Microsemi are rolling out product lines aimed specifically at solar power conversion. There is no hard prediction as to what sources of power generation—renewable, fossil or nuclear—will dominate the future, but it will no doubt be a mix. The emerging electrical infrastructure will need to accommodate this predictable mixture as well as technologies that are still on the horizon, such as the advent of electric vehicles, their service network infrastructure, and the increased generating capacity they will require. If electric vehicles do become a major component of transportation in the future, they will require their own network infrastructure for things like tracking and billing for charging and battery exchange. Will the Smart Grid have extra network capacity for those things it might give birth to but which are now unforeseen? Will we need some sort of highway-oriented network for the future or expanded wireless connectivity? Advances raise so many more questions. And of course, there are still issues such as security, which is the topic of an article in this edition of RTC. The very smart meters that can be read without sending the truck around each month also allow access for things like firmware updates—and that invites hackers and cybercriminals. We currently know that control centers are targets for such attacks, but a whole country full of vulnerable meters, which are small, low-cost and do not even run an operating system, could be a major headache. What is clear is that the gigantic task of rebuilding our electrical infrastructure while it is running is now underway. It presents huge challenges and enormous opportunities for exactly the kind of embedded intelligence that our industry has developed for so many previous applications.


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INSIDER JUNE 2011 RadiSys to Acquire Continuous Computing RadiSys has announced that it has entered into a definitive agreement to acquire privately held Continuous Computing. Continuous Computing develops communications systems consisting of highly integrated ATCA platforms and Trillium protocol software coupled with SW Professional Services to complement their full solution offering. Their key customer applications include 3G and 4G Wireless infrastructure, Small Cell base stations, Traffic Management, Internet Offload and Network Security. Following the transaction, Continuous Computing will become a wholly owned subsidiary of RadiSys. RadiSys believes the acquisition of Continuous Computing has a number of compelling strategic benefits. The acquisition drives further expansion into the high-growth LTE, Femto / Small Cell Wireless and DPI markets with high-performance ATCA platforms and Trillium software. The acquisition also benefits both companies’ customers with a broader set of solutions that are developed and supported by a global team with greater scale and capability. With over 150 customers, Continuous Computing will provide access to a highly complementary set of customers and add further customer diversification to RadiSys. The acquisition also brings a strong leadership team and a talented group of employees to accelerate and expand the RadiSys portfolio of software products and services. Upon closing of the acquisition, Mike Dagenais, Continuous Computing president and CEO, will become RadiSys’ chief executive officer. Brian Bronson, current chief financial officer of RadiSys, will become RadiSys’ president and chief financial officer.

Wind River Accelerates OpenSAF-Based HighAvailability Systems Development

Wind River has extended its relationship with GoAhead Software and is now the preferred integration partner for GoAhead Software’s OpenSAFfire offering, and GoAhead Software is Wind River’s preferred partner for commercial OpenSAF solutions. Together, Wind River and GoAhead Software provide a COTS solution for an open source platform integrating industry standards-based highavailability and Linux. Additionally, Wind River has introduced Wind River OpenSAF Quickstart, a professional services and technical support package designed to help customers who



are using the OpenSAF open source project for quick prototyping or are struggling with developing their own OpenSAF applications. OpenSAFfire implements all major functions of the Service Availability Forum’s Application Interface Specification and also includes important enhancements to improve scalability as well as hardware and software management. OpenSAFfire includes a full implementation of the SA Forum Software Management Framework and Platform Layer Management services, which provide hardware abstraction to ease the management of supporting multiple hardware architectures and facilitates virtualization. For developers looking to create high-availability middleware solutions using code

directly from the OpenSAF project, they can install and configure OpenSAF in a matter of days with Wind River OpenSAF Quickstart. The Wind River OpenSAF Quickstart package is immediately available. Developers can also use Wind River’s professional services for help in migrating legacy applications to OpenSAF or to modify and extend OpenSAF functionality. Additionally, developers interested in the freely available OpenSAF code can visit the Wind River Developers Network and download a pre-validated layer package of OpenSAF for Wind River Linux at

Fleet Management Systems to Reach 6.1 Million Units in the Americas by 2015

According to a new research report from the analyst firm Berg Insight, the number of fleet management systems deployed in commercial vehicle fleets in North America was 2.1 million in Q4 2010. Growing at a compound annual growth rate (CAGR) of 12.6 percent, this number is expected to reach 3.8 million by 2015. In Latin America, the number of installed fleet management systems is expected to increase from 0.9 million in Q4 2010, growing at a CAGR of 20.6 percent to reach 2.3 million in 2015. The report cites customer awareness of the benefits of telematics as the main driver behind growth. “Today managers in North America generally know that fleet management technology can help their businesses reduce costs and improve efficiency. In Latin America, however, an educational process may be needed in order to increase the

awareness among prospective users about the benefits that fleet management solutions bring beyond mere security related features,” said Rickard Andersson, Telecom Analyst at Berg Insight. New regulations related to road transport activities also have a major impact on the market environment. The recently implemented CSA safety scoring system in the U.S. to identify high-risk motor carriers requiring interventions is one example. The hours-of-service regulations are further being revised and a mandate to use electronic onboard recorders to log working hours for truckers is likely to come in place starting in 2012 for new vehicles and to eventually include all commercial vehicles.

Tabula, MorethanIP and NetLogic collaborate on Sub-$500 100Gbit Ethernet solution

Tabula, MorethanIP and NetLogic Microsystems have announced a complete programmable 100Gbit Ethernet solution that can be deployed cost-effectively in production with price points below $500. The complete, ready-to-use solution from Tabula consists of Tabula’s I-100 100Gbit Ethernet-to-Interlaken bridging device embedding MorethanIP’s silicon-proven Interlaken and 100G Ethernet MAC and PCS IP cores, and NetLogic Microsystems’ NLP15142T 100GE PHY devices. The solution enables effective deployment of high-speed networking and storage equipment products with no additional IP costs and at a radically lower price than competing solutions. The NLP15142-T 100GE PHY solution from NetLogic Microsystems features an in-

novative architecture and advanced circuit technologies to provide high 100GE density, low jitter and lower power consumption. The NLP15142-T PHY solution connects seamlessly to the Tabula I-100 device, and supports the 100 Gbit/s transmissions over at least 40 km on single-mode fiber (SMF) cabling, at least 100m on OM3 multi-mode fiber (MMF), or at least 10m over a copper cable assembly.

LDRA Implements Homeland Security’s Secure Programming Guidelines

LDRA, a provider of automated software verification, source code analysis and test tools, has achieved Common Weakness Enumeration (CWE) compatibility for the LDRA tool suite. The CWE project aims to better understand flaws in software and to create automated tools that can be used to identify, fix and pre-

vent those flaws. CWE compatibility confirms that the LDRA tool suite can identify common programming errors contributing to software containing potentially exploitable vulnerabilities. The CWE project is an international community-developed formal list of common software weaknesses. CWE is a software assurance strategic initiative co-sponsored by the National Cyber Security Division of the U.S. Department of Homeland

Security. The CWE effort aims to help shape and mature the code security assessment industry and to dramatically accelerate the use and utility of software assurance capabilities for organizations in reviewing the software systems they acquire or develop. According to research directed by the National Institute of Security Technology, 64% of software vulnerabilities stem from programming errors. To help identify core weaknesses contrib-

827.68 (-1.45%) This data is as of June 9, 2011. To follow the RTEC10 Index in real time, visit COMPANY






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Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTC MAGAZINE JUNE 2011



uting to software vulnerabilities, MITRE Corporation, a public interest not-for-profit organization, created the CWE list. MITRE manages several federally funded research and development centers, including one for the Department of Homeland Security, which is mandated with developing the CWE project. CWE was created to address the concerns of organizations that want assurance that the software products they acquire and develop are free from known types of programming errors.

MIPS Adopts Myriad’s Dalvik Turbo VM Engine for its Android on MIPS Distribution

MIPS Technologies has announced that it has entered into a license agreement with Myriad Group, through which MIPS will make Myriad’s Dalvik Turbo Virtual Machine (VM) available to its licensees as part of its standard distribution of Android for the MIPS architecture.


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Myriad’s Dalvik Turbo is a high-performance full method-based VM that replaces the standard Android Dalvik engine, accelerating performance up to 5x on real-world Android applications. MIPS Technologies and Myriad announced last year that Dalvik Turbo had been optimized for the MIPS architecture. Through this strategic agreement, MIPS Technologies and Myriad Group plan to work together to support the Dalvik Turbo VM on current and future versions of the Android platform. The agreement also includes continued support for MIPS architectural features such as multithreading and multiprocessing. Myriad will provide optimized support for the MIPS architecture on its other products for Java and Android in the future. With Myriad’s Dalvik Turbo VM, MIPS licensees can create SoCs with faster, more complex applications and richer game

graphics optimized for Android smartphones and other high-performance consumer devices without requiring significant increases in device memory. The VM also provides substantial battery life improvements when running resource intensive tasks, all while retaining full compatibility with existing software.

Digi-Key and Nuventix Sign Global Distribution Agreement

Electronic components distributor Digi-Key Corporation, and Nuventix, maker of SynJet thermal management technology, have signed a global distribution agreement. “Digi-Key is proud to welcome Nuventix as a new supplier partner. Nuventix is an example of a company dedicated to providing exceptional products and services to its customers, and now, to Digi-Key’s global customer base

as well,” said Jeff Shafer, DigiKey’s vice president of global interconnect, passive and electromechanical product. “We believe Nuventix’s line of active thermal management solutions for electronics and LED cooling, will provide design engineers and purchasing professionals with the products essential to new designs.” “Nuventix is excited to partner with Digi-Key and bring its phenomenal customer service, global reach and express delivery to our customers,” said Thomas Dalton, senior vice president of sales and marketing for Nuventix. “Product designers are under constant pressure to solve increasingly tougher thermal problems, quickly. Digi-Key’s rapid fulfillment and global logistics will allow us to get our SynJet solutions to these designers overnight to help accelerate their product introductions.” Nuventix’s product line is available for purchase now on Digi-Key’s global websites.

6/9/11 2:29:49 PM



Colin McCracken & Paul Rosenfeld

Head Transplant


hose of us old enough to remember when the word “control” always followed the word “embedded,” remember a day when even computer controlled equipment was beset with electromechanical dials, gauges, lights and switches to provide input to, and display results from embedded systems. Keypads and seven segment displays were considered sophisticated “user I/O” in those days. With the advent of the PC, the opportunity to move to keyboard-based input and display-based output opened up many new applications. But even with early graphics displays, the absence of a graphical software package and enough memory space limited output for most applications to text only. So keyboard input and text output took off, supported by the then-ubiquitous DOS operating system. As we moved through the 90s, graphical displays began to emerge. But early graphical systems were low resolution and slow. More importantly, the display used substantial CPU cycles and expensive RAM and was pretty much out of the question when any level of real-time performance or determinism was required. To deal with these limitations, embedded control system architectures evolved into distributed computing networks, where one subsystem was dedicated to the human-machine interface (HMI) while other systems on the network did actual control, using DOS or an RTOS to control motors, sample analog inputs and pass information over a network to and from the dedicated display system. In many applications, both the control system and the HMI system were in the same box and in some cases the “network” was a simple RS-232 connection. As the Internet ramped, it became possible to run the network over large distances, with the HMI system remote from the control systems. One could control a headless microwave tower on a mountain top from an office desktop thousands of miles away. As the sophistication of applications grew into the first decade of the 21st century, the HMI demands on the graphics systems grew as well. Graphics controllers became a more and more important part of embedded systems. Touch screens and high-resolution displays dropped in price. And high-performance graphics interfaces, such as AGP and PCI Express x16, emerged to funnel data ever faster between the application processor and the graphics processor. But the biggest impact by far was the relentless march of Moore’s Law—doubling the transistor density of integrated circuits every 18 months. Millions of transistors became available



on processor chips, more than could be consumed by additional cores or cache alone. Processor chips began to integrate other CPU board functions into the processor chip—first the Northbridge (or memory controller hub), but by the early to mid-2000s, processor designers also began to include graphics controllers. Early integrated graphics controllers used smaller, older generation graphics technology. While the performance of these integrated graphics controllers was adequate for many embedded applications, those applications requiring high-resolution displays or HD quality video still required a separate, discrete graphics controller. However, for many applications, it was now cost-effective to combine both HMI and control capabilities in the same system. The pervasiveness of this strategy became clearer as processor companies first built relationships with graphics processing companies and then acquired them outright as demonstrated by VIA’s purchase of S3, AMD’s purchase of ATI Technologies, and Intel’s long-term technology licensing relationship with Nvidia. But many multimedia applications such as digital signage and gaming required more performance than these integrated graphics controllers could provide. Discrete graphics controllers continue to thrive. At the same time, the emphasis on small form factor systems and low power consumption drove many applications away from a discrete graphics controller if at all possible. This year, these two trends have collided with the introduction of AMD’s Fusion family of Accelerated Processing Units (APU) combining a multicore low-power Gigahertz-plus processor with a high-performance graphics processor in a single BGA package. More applications than ever before can combine the graphical HMI with the control application in a single small form factor system. In addition, graphics processors are now comprised of hundreds of parallel calculating cores. While optimized for calculating textures, shading and 3D virtual reality, these general purpose graphics processing units (GPGPUs) can be harnessed for a variety of next-gen embedded features ranging from data encryption to smaller, lighter UAVs to computed tomography. While this won’t help the mountain-top microwave repeater, it does provide for a strong combination of user interface and real-time control in the same system, further distancing modern embedded systems from those old days of keypads, dials, gauges and switches.

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editor’s report The Promise of the Smart Grid

The Smart Grid: The Advent of a New Technology Infrastructure The need for a renovation of our electrical power infrastructure is now imperative. But in doing so, we are also creating an environment for adding creative new products and services that will represent a host of new business opportunities for the embedded industry. by Tom Williams, Editor-in-Chief


he concept of the Smart Grid can an infrastructure that will enable a whole be described as a “many splendored range of innovative applications, products thing.” In other words, it may have and services, many of which have not yet a basic definition, but many other ideas been thought of. In much the same way, and assumptions arise from the notion of the advent of the Interstate Highway Sysan intelligent power grid. That is because tem spawned motels, shopping malls, the electrical grid is a basic infrastructure transportation companies and more; the element of modern society. The problem way Microsoft Windows led to the birth is that it is mostly an aging infrastruc- of countless applications and new companies providing turesolutions trying now to keep up with a continually nies; and of course, how the advent of the ion into products, technologies and companies. society. Whether your goalinis to research the latest Internet gave birth to a revolution in the advancing technological The ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you way we live along with countless business creasing demand for electricity and the you require for whatever type of technology, opportunities. The birth of the Smart Grid and productsrapid you aregrowth searching of for. the distribution system can be expected to leverage the developalong with generation facilities is reachment of a whole new age of innovation. ing a critical stage. It is reaching a point According to a Department of Enwhere only the application of computer ergy publication, the initial stages will be intelligence and automation will be able aimed at making today’s grid a “smarter” to maintain reliability and offer the efgrid, leading eventually to the Smart Grid. ficiency we need to make full use of the The initial steps involve greatly improvpower that can be generated. As it turns out, the efforts to improve ing reliability and giving it the ability to the grid to make it more reliable, secure, easily accommodate both renewable and efficient and flexible are poised to create traditional sources of energy. Among the basic infrastructure makeovers is the use of precisely timed synchrophasor data— Get Connected which carries the phase relationships bewith companies mentioned in this article. tween voltage and current—to

End of Article



Get Connected with companies mentioned in this article.

cally alert the system and its operators to potential problems or failures and provide the ability to preempt them before they can cause outages. Right from the start, that involves adding data and control networking to the grid. Once such a network infrastructure is in place, there are many other applications that can take advantage of it. Another early concept is to implement the automatic metering infrastructure (AMI), which involves the use of smart meters that can be read wirelessly. Since smart meters also provide wireless access for things like firmware updates, they also constitute nodes in a network with the attendant opportunities for access by other applications as well as security issues to prevent cyber attacks. Also, throughout the network, equipment is to be refitted with intelligent electronic devices (IEDs) that can send status data and receive control commands from supervisory control and data acquisition (SCADA) systems. Such systems can be under a combination of human control via HMI interfaces as well as automated systems that can react to predetermined conditions. The addition of networking to the grid infrastructure creates the possibility of interoperability between different systems and devices on the grid (Figure 1). That opens the possibilities of a huge number of applications. Even this broad-brushed characterization of the Smart Grid helps indicate the potential for improving its reliability and efficiency as well as its potential to accommodate innovative applications and services as well as to accept alternate and renewable sources of power generation. These primarily come in the form of wind generation and photovoltaic sources. Wind generation usually comes from concentrated wind farms, which are centralized facilities in much the same way as traditional fossil fuel and nuclear facilities in that power must be transported from the plant and distributed over the grid. The issue with wind is that it can be fairly constant, but does not necessarily fall off at night when demand is much lower. The challenge here is to be able to store wind energy that is generated at off-

editor’s report

peak hours so that it can be used when demand is higher. One possible approach being suggested is to take advantage of the predicted growing number of electric vehicles (EVs) that will mostly be charging at night. More about EVs below. The large scale use of photovoltaics, or solar panels, presents a different set of challenges and has triggered a debate about the merits of large-scale central solar power facilities versus widely distributed photovoltaic systems, for example, across the rooftops of a city or multiple cities. Since solar panels do not produce energy at night, there is the reverse situation to wind. Also, solar panels are subject to variations in cloud cover. That can lead to significant fluctuations in power coming from large central plants. Such fluctuations can overly stress assets such as switching equipment and capacitors. Widely distributed generation would be less vulnerable and would also have the advantage of being local to the consumer, avoiding long transmission distances. Technology advances are needed in the inverters that would be used in widely distributed photovolataic generation to allow them to interact properly with the Smart Grid. Such developments, however, would be a boon to the semiconductor and embedded computer vendors who would supply the technology. Another function that is foreseen for the Smart Grid and which also offers opportunities for second-tier vendors is demand response (DR) and its more advanced version, automated demand response (ADR). Current DR operations usually involve large consumers such as industrial facilities or college campuses where curtailing some percentage of consumption can free up power for use elsewhere during peak periods. Utilities often make such arrangements with large users involving agreements for them to limit predetermined points of power consumption in exchange for rate considerations. ADR would expand such strategies by making them programmable and automated. Thus the utility and its customers could agree on levels of demand response that would be triggered by certain condi-




Service Provider


Bulk Generation Transmissions


Figure 1 The network that connects homes and other facilities via the smart meter extends to a wide number of systems, devices and facilities that can operate with each other automatically and/or be monitored and controlled by human operators at control centers or via the Cloud. (Courtesy of the Smart Grid Interoperability Panel)

tions with data and commands sent over the grid’s network. This could then be expanded to include commercial buildings that already have intelligent building management systems for controlling HVAC systems, lighting and security. The utility’s ADR application would then communicate with the building management software and implement the ADR operations, thus bringing demand response to a finer granularity over a larger number of consumers. Eventually ADR can be expanded into the home to the point of being able to turn down a thermostat by a few degrees or turn down an air conditioner. Such small adjustments over a wide number of consumers can amount to very significant power savings with little adverse effect on individual users. Additionally, for the home market, setting up the parameters for ADR would be in the hands of the consumer. Home users will be able to manage their home networked smart appliance by way of a display on their PC, a dedicated panel, via a tablet or smartphone (Figure 2). An adjunct to this sort of demand response savings will be the advent of intelligent appliances that will connect to the grid network via the in-home wireless network (predominantly ZigBee) over the smart meter. Such appliances as washers, driers, dishwashers, etc., will be fitted with intelligent network-enabled modules to al-

low them to take advantage of time-of-day pricing and perhaps also ADR. Some appliance manufacturers will undoubtedly have digital design expertise in house, while others will be OEM customers of prebuilt modules. In any event, it is an opportunity both for the semiconductor as well as the modular board industry. In addition to the ADR access to managed facilities, there are opportunities for third-party vendors to supply Cloud services for the management of multiple, geographically separated buildings from a central command center, or anywhere on the Internet. Data is exchanged and managed on a server in the Cloud and accessed over secure links by the management personnel with rich graphical interfaces. Like renewable power generation, there will be other technologies that may be developing independently but will inevitably have to adapt to and be accommodated by the Smart Grid. Primary among these is the electric vehicle (EV). The development of EVs is gaining momentum and in various parts of the world their popularity is also rapidly growing. The advent of the Chevy Volt, the Nissan Leaf, the pluggable Prius and the move by Tesla Motors to develop an affordable sedan all point to the increased presence of EVs in significant if not universal numbers. This will have a big effect on the way the Smart Grid is designed and managed. RTC MAGAZINE JUNE 2011


editor’s report

Figure 2 Consumers get the best smart grid understanding when they combine smart appliances with a central reporting device. Users can see and adjust energy consumption data for each appliance—and understand how their household energy use burdens the grid. They can then make decisions about programming for such things as time-of-day pricing or ADR. (Courtesy of Altia)

One of the major issues is the buildout of a public charging infrastructure. It is not enough to simply install charging stations in public places. There must also be a networking scheme to identify EVs connected to chargers so that the owners can be billed for the energy usage. Until there is a sufficiently large public infrastructure, owners will experience “range anxiety,” the uncertainty about how far they can drive and still get home or to a public charger. Ideally, an EV should be able to connect to a charging station and have its ID read automatically so that the owner can be properly charged for charging his car. Although there is now a standard for connectors, there is as yet no standard network protocol for communication between the vehicle and the electric utility. Although there are a number of schemes out there, vendor-specific protocols will not work across utilities, so some sort of standardization effort is needed. The question arises as to who will build and maintain such a charging infrastructure. Will it be the utilities, municipalities or some thirdparty service company or companies? There are also plans to take advantage of EVs to help stabilize the grid given the nature of the growing renewable re-


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sources. Since most cars, while used for basic transportation, are parked during the day after having been driven a fairly modest distance to work, they can be used to supply power to the grid during peak demand hours and then fully charge when they are parked at home at night. Just how this will all be worked out in terms of options for vehicle owners in a way that can also be standardized has yet to be determined. Still, it is not difficult to envision the heavy use of embedded computer intelligence in EVs, their charging stations and the network infrastructure. In addition, whether or not that infrastructure is a part of the Smart Grid, it will certainly have to communicate with the grid’s intelligent networking as well. The advent of the Smart Grid has arisen out of necessity. We simply need to upgrade the national electrical power infrastructure. In doing so, however, we are creating a much richer environment. This environment will make possible even more creative ways to make the grid more flexible, safer, more robust and secure. However, it will also make possible the addition of ever more creative applications and services that will create new businesses and provide an even more connected world.

Technology in


Platform Management with Customizable Microcontroller

Customizing a Microcontroller for Hardware Platform Management I/O customization can substantially benefit the functionality and costeffectiveness of a hardware platform management controller, especially one that takes advantage of the flexibility inherent in an intelligent mixed signal FPGA. by Mark Overgaard, Pigeon Point Systems and Hichem Belhadj, Microsemi




AMC Module Sites IPMB-L Legs

AMC Control Other Control A2F200/500 Carrier IPMC

Power Control


Serial Console Interfaces


Extended Management Power Domain

Direct Ethernet Link

hen the subsystem CPU is a microcontroller and its job includes hardware platform management for a larger board or module, it is highly desirable for the controller to integrate management-friendly I/O facilities. One way to accomplish such integration is by using an intelligent mixed signal FPGA, such as Microsemi’s SmartFusion, which combines a microcontroller, a programmable analog subsystem and a field programmable logic array. The latter two subsystems allow the traditional I/O facilities of the microcontroller to be augmented for this application, effectively moving the line between CPU and I/O to integrate application-specific I/O with the CPU. The examples given here focus on hardware platform management in boards and modules targeting the PICMG xTCA (AdvancedTCA, AdvancedMC or MicroTCA) family of architectures, but the same ideas are applicable to other standardized and proprietary management architectures. The article titled, “Using Intelligent Mixed Signal FPGAs for Hardware Platform Management,” in the October 2010 issue of RTC, introduces this overall concept, shows its applicability to other platform architectures beyond xTCA, and describes an example management controller based on this approach and an intelligent mixed signal FPGA, the SmartFusion device.

Payload CPU(s)


IPMI Traffic with IPMC

Ethernet Traffic with Payload CPU(s) Ethernet

Figure 1 Extensive I/O requirements of an xTCA carrier IPM controller.

Customized I/O Benefits an xTCA Carrier IPM Controller

An xTCA Carrier IPM Controller (Carrier IPMC) handles hardware platform management for an AdvancedTCA (ATCA) board that implements slots for hot-swappable AdvancedMC (AMC) mezzanine modules.

A Carrier IPMC interfaces up to an ATCA Shelf Manager via a dual redundant I2C-based IPMB-0 and down via a set of local intelligent platform management buses (IPMBs) called IPMB-Ls to the management controllers on its AMC mezzanine modules. In xTCA, a Carrier IPMC can need up to nine IPMB-Ls; that plus IPMB-0 yields a total of up to eleven I2C ports, almost double the largest number of such ports we know of on a standard microcontroller, even one that is optimized for management applications. With a carrier IPMC based on an intelligent mixed signal FPGA, extra I2C ports can be added in the FPGA fabric, as needed. xTCA allows IPMB-L to be implemented on a multi-drop basis, where a single IPMB is shared across all the modules. However, that approach has at least two downsides. The first is that each of the IPMB-L legs must be isolated from the others, so that, for instance, an AMC that is being hot swapped in or out of the AMC carrier board doesn’t corrupt that shared bus. The isolation devices increase the size and cost of the carrier IPMC. Second and more importantly, a single misbehaving IPMB-L node can disrupt traffic for all the other nodes, affecting reliability, and only one of the nodes can be sending a message on the bus at any given time, affecting performance. Both of these limi-

technology in context

I/O Customization for MicroTCA Management Infrastructures

MicroTCA (µTCA) is a smaller, lowercost complement to ATCA that also includes a full-featured hardware platform management architecture as elaborated in “MicroTCA.0 Specification Adapts and Extends PICMG Hardware Platform Management Facilities” in RTC, November 2006). Figure 2 shows the key infrastructure portion of a potential MicroTCA carrier, which is designed to support up to twelve AdvancedMC (AMC) modules. Only four are shown in the figure; these are the same AMCs that can also be installed in ATCA carrier boards and managed by a Carrier IPMC. The infrastructure elements in-

Backplane Connections to AMC and Other Module Sites

AMC Control (including power)

IPMB-L Legs to Modules

Supplementary Infrastructure Fan and Other Control

Serial Console Interfaces


Payload CPU

Direct Ethernet Link

Ethernet Switch

IPMI Level Messaging

Main MicroTCA Carrier Infrastructure

Payload Power Control

Figure 2

IPMB-0 to EMMCEquipped Modules

A2F500 MCMC µCarrier Manager µshelf Manager

Extended Management Power Domain

tations are removed when each IPMB-L is logically separate. Figure 1 shows a full-function carrier IPMC application based on SmartFusion, including what are likely to be one or more payload CPUs (say, PowerPCs or Xeons) on the ATCA board and a fabric switch—assumed to be Ethernet in this case. In addition to the IPMB-L support, FPGA fabric-based I/O enhancements include a Low Pin Count (LPC) PCI bus subset link between the payload CPU(s) and the IPMC and additional UARTs for serial consoles. It additionally provides power rail control, which also leverages the microcontroller and the programmable analog subsystem. There is one final I/O extension to mention for the Carrier IPMC in Figure 1. The Ethernet interface in the SmartFusion device implements the Reduced Media Independent Interface (RMII). This is perfect for compliance with the Network Controller Sideband Interface (NC-SI), an open standard for connecting management controllers to NCs. See “LAN-attached TCA Management Controllers: How to Build and Use Them,” in the August 2009 issue of RTC and check for a copy of the NC-SI specification. In the above context, however, the management controller needs to connect into a switch and often RMII is not an option there. Fortunately, the RMII connection can be routed through the FPGA fabric and converted to some other Media Independent Interface (MII) variant that is switch-compatible.

Application and Higher Level Management Messaging

Ethernet Fabric Connections via Backplane

Front Panel Ethernet

Key infrastructure elements of a MicroTCA carrier.

clude several levels of hardware platform management, plus a central CPU and an Ethernet switch fabric for the carrier. One way to realize the infrastructure of a MicroTCA carrier is with distinct functional modules. The main infrastructure elements in Figure 2 would be implemented on a MicroTCA carrier hub (MCH) module, possibly with two of them for redundancy. The power supply for the carrier would be implemented in up to four MicroTCA-specified power modules, which may support redundancy as well. Carrier cooling could be handled by up to two MicroTCA-specified cooling units. Figure 3a shows how a passive backplane could provide module slots for the above infrastructure functions and four AMCs. Below each slot are communication link stubs representing the various types of infrastructure links implemented in the carrier. This modular infrastructure approach is the most flexible and has the most architectural headroom, but it isn’t necessarily cost-optimized. It takes

advantage of roughly the same FPGAbased I/O customization as for the Carrier IPMC, but more of it—up to 13 IPMB-L legs, for instance! Alternatively, the infrastructure of a MicroTCA carrier can be integrated as shown in Figure 3b. An active backplane or motherboard can directly implement the main infrastructure elements as well as the supplementary infrastructure elements, leaving just the AMC modules to be installed in distinct backplane slots. An integrated infrastructure likely offers the best opportunities to optimize a MicroTCA carrier for cost and/or size. This architecture also provides even more opportunities for I/O customization. Substantial new functional blocks can be added to an intelligent mixed signal FPGA-based MCMC to implement fan control, perhaps via an IP block that combines PWM and tachometer functions. In addition they can provide enhanced power management capabilities, including monitoring all the AMC power channels. RTC MAGAZINE JUNE 2011


technology in context

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CU PM x2 Example Passive Backplane for Modular Infrastructure

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Example “Motherboard” for Integrated Infrastructure

Figure 3 Modular (a) and integrated (b) MicroTCA infrastructure approaches.


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Analog Compute Engine

ACE Flags

Sequenced Enables

Power Outputs

Power Supplies

Power Enables

Fault Detection Logic


BMR-A2F-ATCA/AMCc Reference Design Subset

Over-Current Protection Circuitry Power Monitoring

Figure 4

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Programmable Analog

Hardware Connection SoftwareDriven Connection

CoreGPIO (latched)

F19P – 3U CompactPCI PlusIO SBC with Intel® CoreTM 2 Duo

Margining Controls

To Payload

Cortex-M3 BMR-A2F Firmware

3/4/10 11:47:12 AM

Power supply management integration in SmartFusion-based ATCA IPMC reference design.

I/O Customization Integrates Power Rail Management

Power rail sequencing during powerup or power-down of an xTCA board or module is another critical supervision function in xTCA platforms. It requires care and in-depth understanding of all the requirements associated with individual chips on the board as well as with the overall system reliability and safety considerations. The complexity of the task increases when the number of analog and digital supplies and/or the number of analog or digital point of load (POL) regulators increases, and can be further complicated by system safety requirements. To illustrate with a simple example, consider a scheme where a power rail is not enabled until several other power rails, in a defined sequence, are turned on and reach a

minimum threshold voltage. And if a power rail falls below a minimum voltage, a safe shutdown of the already enabled POL regulators must occur. In actual boards or modules, the fault detection and response requirements can be much more complicated, highlighting the need for complete understanding of all the system requirements. Moreover, analog and digital power supplies may require real-time monitoring, trimming and current limiting, adding to the required sophistication of the power management subsystem. Additionally, when down time is not allowed, power management architects usually implement redundancy schemes to minimize the impact of unavailability of one of the power management units. All the above constraints get translated for the development and integration teams

technology in context into a high demand for digital and analog I/Os, data acquisition resources, data transfer schemes and processing power. Fairly complex power management schemes can be integrated into an ATCA IPMC that is based on an intelligent mixed signal FPGA such as the SmartFusion device, as shown in Figure 4. ARM CortexM3 firmware can supervise the overall subsystem, using the results of data samples retrieved and assessed (e.g. threshold tested) by the programmable analog function. The Analog Compute Engine (ACE) sets flags that are directly available to FPGA logic. These flags can represent, for instance, over- or under-threshold conditions, as inputs to fault detection logic implemented in the FPGA fabric. That logic

can control the actual power enables, overriding, if necessary, the normal sequence of enables or disables determined by the firmware supervisor. The FPGA fabric can also include a Pulse Width Modulator (PWM) function that, under Cortex-M3 control, provides margining controls to the trim inputs of the power supplies. Extending the I/O interfaces of a microcontroller in the innovative and flexible ways sketched in the example above may allow board and module architects to forgo the use of dedicated power management chips, because the responsibilities of those chips are integrated into the hardware platform management controller. This can result in footprint and bill of materials savings and may enable more

sophisticated power management paradigms to be implemented. Furthermore, all the key resources that participate in the power management implementation—the Cortex-M3, analog subsystem and FPGA fabric—are programmable, so it is possible to test different approaches and select the best one based on experiments with the physical board or module. Pigeon Point Systems Scotts Valley, CA. (831) 438-1565. []. Microsemi Irvine, CA. (949) 221-7100. [].

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6/8/11 2:24:44 PM RTC MAGAZINE JUNE 2011


connected New Roles for Wireless Connectivity

Software Defined Radio: The Key to Public Safety Radios The need to coordinate operations between different agencies such as fire, police, state and federal has become more urgent than ever. The flexibility and communications power of software defined radio is being harnessed for this daunting task. by Rodger H. Hosking, Pentek


uring the decade bridging the one of the toughest logistical challenges, tragic events of 9/11 and the recent and communications is near the top of devastation in Japan, the world has the list. Communication systems used by experienced numerous disasters claiming the numerous organizations involved in thousands of lives and destroying masa crisis are often incompatible, as was sive amounts of property. Now more than widely publicized and acknowledged ever before, firefighters, police, emerin the 9/11 response. The selection and gency medical teams, rescue units and procurement of radio sets and the choice other first responders are expected to act of frequency bands tend to be done at immediately, correctly and effectively to the local level to meet the required tersave lives and minimize damage. Maritorial coverage and operational needs jor natural disasters such as hurricanes nies providing solutions now of the particular organization, and are can pull in additional state, federal and ion into products, technologies and companies. Whether your goal is to research the latest influenced by support for existing legmilitary resources. Concerns over crimiation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you nal or terrorist involvement add federal acy equipment, vendor allegiances and you require for whatever type of technology, intelligence organizations to budgetary constraints. and productscrime you are and searching for. A nationwide public safety network the mission. of radios that can be configured to do In nearly every case, these events exactly what each organization needs are sudden and totally unpredictable and yet provide the interoperability to in scope or nature. Assessing the many support successful cooperation among complex issues surrounding each event to quickly form a strategic plan of ac- these organizations is essential. Delivtion is incredibly difficult and subject to ering on these features with improved revision. However, even with the best of levels of security, reliability and inforplans, trying to coordinate local, state mational bandwidth requires regulatory and federal organizations still remains changes for frequency allocation, government mandates for adoption of radio standards, and new development in Get Connected technologies like software defined radio with companies mentioned in this article. (Figure 1).

ploration your goal k directly age, the source. ology, d products

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Get Connected with companies mentioned in this article.

Legislative Initiatives Harness SDR Technology

In October 1989, the Association of Public Safety Communications Officials International, along with other government organizations, launched the APCO Project 25 initiative to provide a standard for public safety radios. It uses parts of the VHF and UHF bands previously allocated for analog public safety radios, and maintains compatibility with those legacy radio sets. In addition, it supports digital FM modulation for both speech and data, plus several levels of digital encryption and digital access controls for secure communications. As a result, Project 25 (or P25) represented a milestone for licensed, widespread deployment of a major communications system based on software defined radio (SDR) technology. SDR takes advantage of digital signal processing (DSP) techniques to replace the analog processing tasks associated with radio, such as filtering, frequency conversion, modulation and demodulation. Of course, because the electromagnetic signals propagating through the air are analog, A/D and D/A converters are an essential interface for any software radio system. The hardware used in these radios

technology connected

can be ASICs, processors, FPGAs, or just about any kind of digital device that can be configured to perform a digital signal processing task dictated by the user and the operational mode of the radio. Perhaps the earliest example of a software radio function is the DDC (digital down-converter). It translates a specific signal frequency within a digitized radio band down to baseband (0 Hz) using a digital mixer and digital local oscillator, and then filters it to the required channel bandwidth using a digital low pass filter. This essential SDR element easily tunes to any of several hundred available channels with precise frequency accuracy and extremely fast switching. Using a complementary process, the DUC (digital up-converter) filters and translates a baseband channel signal up into specific channel frequency slot for transmission. To gain better use of the original 25 kHz analog FM channel spacing on the public safety band, Phase 1 of the P25 standard split this spacing in half to 12.5 kHz, doubling the number of channels. In Phase 2, the channel spacing halved again to 6.25 kHz (Figure 2). To handle the higher channel count, improved DDCs and DUCs became even more important. An additional important SDR function for P25 is the digital modulation scheme. In order to achieve the same information capacity across these narrower channels, a 4-level FM modulation scheme called C4FM was developed. It handles a 4800 baud signal with 2 bits per symbol, delivering 9600 bits/s for each 12.5 kHz channel. While the C4FM modulation scheme required for P25 Phase 1 is now in widespread use throughout the country, the new Phase 2 requirements mandate the same channel capacity within a 6.25 kHz bandwidth. To achieve this feat, a new compatible quadrature phase shift keying (CQPSK) modulation scheme uses advanced signal processing techniques to achieve the same 9600 bits/s channel rate.

Figure 1 Pentek’s Model 7151 256-Channel DDC PMC module uses an advanced Virtex-5 FPGA IP core to accommodate high channel density for applications like P25 radios and GSM.

Because P25 radios must still operate with the legacy radios, the Phase 2 sets must be capable of recognizing and adapting to legacy 25 kHz analog radios and Phase 1 sets. Scanning, classifying and adapting to this diverse traffic pattern by engaging different modulation and demodulation tasks in a single radio is a perfect match for the configurable radio architectures provided by SDR. Another exploitation of DSP technology for P25 radios is the speech vocoder. In order to improve transmission and reception of speech over relatively low bandwidth digital channels, vocoders extract key parameters from speech including pitch, formants (resonant frequencies in the vocal tract) and fricatives (like “t” and “s” sounds). These parameters

change relatively slowly compared to the bandwidth of speech itself, so the digital samples of these parameters along with error correction coding can fit well within the 9600 baud digital channel supported by P25. At the receiving end, these parameters control the frequency of a digital pitch generator, filter coefficients for the formants, and a fricative generator to reproduce the speech. The standard vocoder for P25 is the Improved Multiband Excitation (IMBE) model. This algorithm provides far superior intelligibility compared to an analog signal over the same channel bandwidth, especially in the presence of channel noise. One major benefit of vocoders is the inherent rejection of ambient audio noise, because it does not fit the parametric model of the vocal tract. With a dual microphone handset, background noise picked up by the microphone closest to the person speaking is often the same as the noise picked up in a second microphone aimed in a different direction. By subtracting the common background noise, the first microphone signal is made clearer. Consumers are now benefiting from this same digital signal processing technique in noise-cancelling hands-free phone systems in automobiles.

Cognitive Radios

Cognitive radio is an extension of SDR that opens up important new features for public safety. The cognitive radio set uses various sensors to ascertain its environment so it can adapt its mode of operation and communicate situational information. For example, a cognitive radio can authenticate the user through a retina scanning camera to validate pre-authorized privileges and access rights to certain channels or modes of operation. This allows radio sets to be exchanged in case of damage and still deliver correct access rights to the new user. It also provides security against unauthorized access in case the radio is lost or stolen. RTC MAGAZINE JUNE 2011


technology connected


25 kHz

25 kHz

Legacy 25 MHz Analog FM Channel

P25 Phase 1 - C4FM 12.5 kHz Channels

25 kHz

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P25 Phase 2 - CQPSK 6.25 kHz Channels

Figure 2 SDR techniques have allowed P25 public safety radios to split the legacy 25 MHz analog FM channel into two 12.5 kHz channels (C4FM) or four 6.25 kHz channels (CQPSK) while still preserving full information capacity on each channel.

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5/6/11 10:01:41 AM

Handheld cognitive radios use GPS to locate each radio and automatically share their position over the air. Locations of police, fire and EMT personnel are displayed on each handheld radio.

A GPS subsystem built into the radio can not only show the user his exact location, but it can also be used to transmit his location to the rest of the users. Some new P25 radios now display a graphical map of the area marked with the locations of nearby team members in one color and members of other organizations in other colors (Figure 3). One major objective of cognitive radios is to continuously monitor the radio frequency environment and classify the

spectral terrain. In this way it can automatically adapt to interference or poor signal quality to change communication channels, modulation type and power level, as required, for best reception. This process is often referred to as dynamic channel allocation. With a cognitive radio, the public safety communications administrator can upgrade software, change access privileges, add or delete authorized users, and even add new channels or modulation

technology connected

types in the field and entirely over the air, eliminating the expense and inconvenience of returning the radio sets to an upgrade facility.

LTE – The Future of Public Safety Radio

Today, there are still two significant shortcomings of public safety radio. The first is that public safety organizations have failed to take advantage of the many technical benefits of the P25 system to achieve interoperability. After over $7 billion of federal spending to improve public safety communications since 9/11, improvements in inter-organizational communications are spotty and disappointing. Much of this can be attributed to turf protection and politics. The second shortcoming is channel capacity. Even if multiple P25 channels are combined for extra bandwidth, transmission of photos and video and other high-speed digital traffic is either impossible or limited. In 2005, the FCC ordered the transition of broadcast television stations to digital broadcasting. This freed up over 100 MHz of bandwidth in the 700 MHz band, with 24 MHz reserved for public safety. Most of the remaining bandwidth was auctioned off by the FCC to commercial carriers by 2008, leaving just 10 MHz, known as the D Block. The reason for this was the controversial D Block had strings attached: the licensee must agree to relinquish use of the D Block if needed in a public safety emergency. The government’s rationale for this restriction was clear: let commercial carriers build up and develop this broadband infrastructure at their expense, and then let public safety have priority use of it, if necessary. It is estimated that the government could save up to $9 billion in infrastructure and build out costs if such a deal could be made. However, because of this restriction, the D Block failed to attract the minimum bid of $1.3 billion and negotiations are now underway to offer a better plan. Nevertheless, in January 2011, the FCC announced that regardless of the funding model, the next generation of public safety radios must transition to the 700 MHz band. A major part

of this band will use the Long Term Evolution (LTE) standard to provide a broadband infrastructure with plenty of bandwidth for voice, video, graphics, data bases, and access to virtually all Internet resources. These new, high-bandwidth public safety radios will rely even more heavily on software radio to enhance communications reliability, improve access security, streamline the delivery and sharing of information

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and media, and provide situational awareness for first responders so they can operate more effectively in the future. Pentek Upper Saddle River, NJ. (201) 818-5900. [].


9:23:49 AM RTC MAGAZINE 4/12/11 JUNE 2011


Hybrid and Multicore Processors

Supercomputer Performance on a Chip Powers Next-Generation Embedded Image Processing A new framework for the C language had been developed to move appropriate code to parallel graphics processors for fast execution in graphical and other numeric-intensive applications. A new generation of hybrid processors is emerging to take advantage of this capability. by Dr. Vijay Reddi, Advanced Micro Devices


urrent-generation imaging applica- ognition, built around smaller box PCs. tions have exhausted every method But the performance of such CPU-centric for squeezing out additional perfor- systems on these imaging applications mance. First, microprocessor vendors deep- leaves much to be desired. Conventional sequential microprocesened on-die caches, created SIMD (single sors and coding languages have run their instruction multiple data) instruction set courses and are ill-prepared for the faster extensions to process media streams, and real-time performance and smaller system then implemented multi-threading and size demands of next-generation medical clock frequency scaling. However, imaging imaging, video surveillance, homeland applications typically operate on data sets security and similar applications. A fresh that are an order of magnitude larger than nies providing solutions now new approach is needed for the embedcaches, which better serve traditional code ion into products, technologies and companies. Whether your goal is to research the latest ded market, and that can now be realized and static (re-used) data. Although the rest ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you thanks to the advances in graphics proof the performance-enhancing techniques you require for whatever type of technology, cessing units (GPUs) and an innovative image processing, we will demonand productshelp you are searching for. strate here a much more efficient and scal- programming language, OpenCL. The OpenCL programming language able way to attack the problem, drawing was developed to provide developers with a from a supercomputing pedigree. platform to create C-based applications that Large racks populated with CPU run on the CPU but can also offload parallel blades and loud fans have been deployed kernels to the GPU. GPUs are implemented in MRI and CT scanning equipment, often with ASICs and FPGAs as additional with dozens to hundreds of very powerful performance-boosting offload engines. math engines with fast local RAM. PCs Additional imaging applications have with dual/quad core desktop processors emerged, from surveillance to facial rec- and discrete PCI Express graphics cards can certainly deliver the performance required for the embedded market; however, Get Connected next-generation systems require smaller with companies mentioned in this article. size and lower power consumption.

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Get Connected with companies mentioned in this article.


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tech in systems

Big Performance in Small Packages

Figure 2 The SURF application identifies points of interest within an image.

Input Image Approximated Gaussian Filters Build Integral Image

Calculate Hessian Determinant

Filter Scale

Graphics processing has evolved in a relatively short period of time from specialized supercomputers to powerful Graphics Processing Unit (GPU) add-in cards. High-end GPUs pack Teraflops of floating-point compute horsepower onto a single PCI Express graphics card. At the same time, the massively parallel processing logic once dedicated to specific 3D graphics processing tasks has become more flexible and programmable. Enhancements to the GPUs have enabled these processors to address a wider range of applications. While not suitable to accelerating every application, those with similar characteristics to graphics workloads can achieve large improvements in performance and power efficiency by exploiting the GPU. The best suited applications are characterized by many, largely independent tasks ideally operating on large, regularly structured data sets. Smaller die geometries have enabled the first family of single die CPU+GPU solutions, known as heterogeneous multicore processors, which greatly reduce space and heat while increasing the data bandwidth between CPU cores and graphics cores. These Fusion processors or APUs (accelerated processing units) are positioned well to reduce the size and weight of imaging systems dramatically. The low-power APUs integrate GPUs capable of tens to hundreds of Gigaflops onto the same die as multiple conventional CPU cores. AMD’s new Fusion processors such as the AMD Embedded G-Series dual-core 1.6 GHz T56N CPU with integrated AMD Radeon HD 6310 GPU shown in Figure 1, are ushering in a new era of efficient supercomputing for embedded applications that are not well served by conventional CPUs. GPUs are optimized primarily for graphics tasks, and are best suited to certain types of parallel workloads. Because of their data-parallel execution logic, GPUs are effective at tackling problems that can be decomposed into a large number of independent parallel tasks. With hundreds of computing cores, modern GPUs are much more scalable than the handful of cores offered in a CPU-centric paradigm. The term “GPGPU” refers to

Resultant “Hessian Determinant” stack which are images filtered using different scaled Gaussian filters

Non-max Suppression

Detected Scale Vector <int>

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Vector <float> OrientationVector

Calculate and Normalize Descriptors

Vector <float[64]> Descriptor Vector

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Figure 3 The SURF application block diagram reveals the computational work items.

the use of a GPU for general-purpose parallel computations. GPUs are geared for processing many independent “work items” in parallel. When it comes to graphics rendering, the particular work items are operations on vertices and pixels, including texturing and shading calculations. In a generalpurpose GPU (GPGPU) program, a set of operations is typically executed in parallel on each item in a data set. Applications well suited for GPU execution such as image processing have large data sets, high parallelism and minimal dependency between data elements. A common form for a data set to take in a GPGPU application is a 2D grid because this fits naturally with the rendering model built into GPUs.

Many computations naturally map into grids: matrix algebra, image processing, physically based simulation and so on. OpenCL kernels can also take advantage of dedicated texture processing hardware in the GPU to perform various 2D filtering operations on certain memory reads. Originated by Apple and turned over to the Khronos Group for standardization, Open Computing Language (OpenCL) is a framework for writing programs that can exploit heterogeneous platforms consisting of CPUs, GPUs and other processors. OpenCL includes a language based on C99 for writing kernels—functions that execute on OpenCL devices—plus APIs that are used to define and then control the platforms. Each kernel is a main body of RTC MAGAZINE JUNE 2011


Tech In Systems

/* * Host code to set up execution */ // ‘numIpts’ is the number of interesting points found by SURF size_t indexSpaceSize[1] = {this->numIpts*64}; size_t workGroupSize[1] = {64}; // The descriptors and descriptor lengths are stored in OpenCL buffers // already present on the device. They are set as arguments corresponding // the indexes in the kernel signature. ‘norm_kernel’ is the OpenCL Kernel // and has been previously created by reading the kernel source in as a // string, and compiling it using the OpenCL API clSetKernelArg(norm_kernel, 0, sizeof(cl_mem), &(this->d_descriptors)); clSetKernelArg(norm_kernel, 1, sizeof(cl_mem), &(this->d_lengths)); // This command executes the normalization kernel. ‘queue’ is the OpenCL // command queue that is used to execute the kernel on a device clEnqueueNDRangeKernel(queue, norm_kernel, 1, NULL, indexSpaceSize, workGroupSize, 0, NULL, NULL); // Copy back the descriptors from the device (d_descriptors) to the host // (h_descriptors) clEnqueueReadBuffer(queue, this->d_descriptors, CL_TRUE, 0, (this->numIpts)*64*sizeof(float), this->h_descriptors, 0, NULL, NULL); __kernel void normalizeDescriptors(__global float* surfDescriptors, __global float* descLengths) { // Previous kernels have computed 64 descriptors (surfDescriptors) and // 16 lengths (descLengths) for each interesting point found by SURF. // This kernel will sum up all of the lengths for each interesting point // and take the square root. This value will then be used to scale the // descriptors associated with the interesting point. // Note that each work group contains 64 work items (one per descriptor). // This array is used to cache data that will be accessed multiple times. // Since it is declared __local, only one instance is created and shared // by the entire work group __local float ldescLengths[16]; // Get the offset for the descriptor that this work group will normalize int descOffset = get_group_id(0) * 64; // Get the offset for the descriptor lengths that this work group will // use to scale the descriptors int lenOffset = get_group_id(0) * 16; // Get this work item’s ID within the work group int tid = get_local_id(0); // Have the first 16 work items cache the lengths for this interesting // point in local memory if(tid < 16) { ldescLengths[tid] = descLengths[lenOffset + tid]; } barrier(CLK_LOCAL_MEM_FENCE); // Work items work together to perform a parallel reduction of the // descriptor lengths (result gets stored in ldescLength[0]) for(int i = 8; i > 0; i >>= 1) { if (tid < i) { ldescLengths[tid] += ldescLengths[tid + i]; } barrier(CLK_LOCAL_MEM_FENCE); } barrier(CLK_LOCAL_MEM_FENCE); // Calculate the normalized length of the descriptors float lengthOfDescriptor = 1.0f/sqrt(ldescLengths[0]);


// Scale each descriptor surfDescriptors[descOffset + tid] *= lengthOfDescriptor;

Figure 4 The CPU host calls the OpenCL runtime (top), and a portion of the SURF kernel (bottom) reveals OpenCL, constructs which tap GPU resources (top).



a loop or routine. The developer specifies the kernel, memory regions and data set to process using OpenCL constructs. OpenCL provides parallel computing using task-based and data-based parallelism, and presents the GPU resources in a very clean manner as having many instantiations of a single processor type, buffers and memory spaces. AMD provides an SDK for its Fusion series of APUs to allow embedded developers to get started with OpenCL.

OpenSURF: Community Development with a Vision

As an example of the use of OpenCL with a GPGPU, one group within the opensource community analyzed and profiled the components of the Speeded Up Robust Features (SURF) Computer Vision algorithm written in OpenCL. SURF analyzes an image like the one in Figure 2 and produces feature vectors for points of interest (“ipoints”). SURF features have been used to perform operations like object recognition, feature comparison and face recognition. A feature vector describes a set of ipoints, consisting of the location of the point in the image, the local orientation at the detected point, the scale at which the interest point was detected, and a descriptor vector (typically 64 values) that can be used to compare with the descriptors of other features. A diagram of the application is shown in Figure 3. To find points of interest, SURF applies a Fast-Hessian Detector that uses approximated Gaussian Filters at different scales to generate a stack of Hessian matrices. SURF utilizes an integral image, which allows scaling of the filter instead of the image. The location of the ipoint is calculated by finding the local maxima or minima in the image at different scales using the generated Hessian matrices. The local orientation at an ipoint maintains invariance to image rotation. Orientation (the 4th stage of the pipeline in Figure 3) is calculated using the wavelet response in the X and Y directions in the neighborhood of the detected ipoint. The dominant local orientation is selected by rotating a circle segment covering an angle of 60 degrees around the origin. At each position, the X and Y responses within the segment of the circle are summed and used to form a new vec-

tech in systems

tor. The orientation of the longest vector becomes the feature orientation. To demonstrate the power of familiar C-style structures in OpenCL with the data-parallel compute capability of GPGPUs, Figure 4 shows SURF code for calculating and normalizing descriptors. The calculation of the largest response is done using a local memory-based reduction. The 64-element descriptor is calculated by dividing the neighborhood of the ipoint into 16 regular subregions. Haar wavelets are calculated in each region and each region contributes 4 values to the descriptor. Thus, 16 * 4 values are used in applications based on SURF to compare descriptors. The goal of using OpenCL with GPGPUs is to extract as much parallelism out of the framework as possible. In SURF, execution performance is determined by the characteristics of the data set rather than the size of the data. This is because the number of ipoints detected in the non-max suppression stage of the algorithm helps to determine the workgroup dimensions for the orientation and descriptor kernels. Computer Vision frameworks like SURF also have a large number of tunable parameters— for example, a detection threshold, which changes the number of points detected in the suppression stage—that greatly impact the performance of an application.

nels are run. In many cases, data is transferred back to the CPU host, or integrated into CPU library functions. Analysis of program flow can pinpoint sections of the application where it would be beneficial to modify data management, leading to more efficient use of the overall system. GPGPUs can be programmed and optimized efficiently using OpenCL, a royaltyfree language based upon C, in order to unlock the full potential of standardized pro-

cessing hardware for the rapid development of next-generation imaging applications. Advanced Micro Devices Sunnyvale, CA. (408) 749-7000. []. Khronos Group Beaverton, OR. (415) 869-8627. [].


In heterogeneous computing, knowledge about the architecture of the targeted set of devices is critical to reap the full benefits of the hardware. For example, selected kernels in an application may be able to exploit vectorized operations available on the targeted device, and if some of the kernels can be optimized with vectorization in mind, the overall application may be sped up significantly. However, it is important to gauge the contributions of each kernel to the overall application runtime. Then informed optimizations can be applied to obtain the best performance. In a heterogeneous computing scenario, an application starts out executing on the CPU, and then the CPU launches kernels on a second device (e.g., a GPU). The data transferred between these devices must be managed efficiently to minimize the impact of communication. Data manipulated by multiple kernels should be kept on the same device where the kerUntitled-5 1


4:47:07 PM RTC MAGAZINE 2/17/09 JUNE 2011

technology deployed Embedded Technologies for the Smart Grid



Technology deployed

Synchronized Embedded Intelligence Enables the Smart Grid Getting maximum electric power from the industry’s limited capacity requires precisely synchronized and massively distributed intelligence embedded throughout the grid. by Andre Marais, Symmetricom


he electric power industry is moving to the Smart Grid because it needs as much power as possible from today’s power system. A grid is “smarter” to the extent that there is intelligence embedded within the devices that manage power, and also to the extent that these devices exchange data among themselves and grid-wide applications that improve the grid’s efficiency. To use their intelligence, however, these devices, including potential and current transformers, must sample and time order voltage and current measurements. Accurate sampling therefore requires that devices be precisely synchronized to a common substation clock. Without accurate and precisely timed information, the trip instructions these devices send to switches may be wrong, potentially causing “false tripping.” Additionally, the information they report upstream to time-sensitive applications will probably be wrong as well. Precise, highly distributed timing was not always a priority. With today’s faster processors, more memory and more robust algorithms, devices can take more variables into account per unit of time and respond in a more granular and more intelligent way to out-of-spec conditions. But to do that they must know exactly when a unit of time begins and ends. As more data is sampled, the margin for timing error shrinks. The increased capabilities of these devices multiplied by their sheer number has led utilities to innovate how intelligent devices communicate downward to switches and upward to management stations. Increasingly, Ethernet over fiber is replacing hard-to¬-maintain point-to-point copper cable. Utilities have also sought to streamline how they distribute timing. Efficiency dictates a centralized source, such as a GPS-synced grandmaster clock, that synchronizes devices over the same Ethernet network used for integrated control and protection. In the past, timing has typically been done over dedicated point-to-point copper wires, often with sepa-

rate GPS clocks serving different applications and equipment. The more centralized packet-based approach synchronizes all devices to the same clock and allows applications the opportunity to gain a single unified view of timing of all events and measurements. The updated timing topology fully leverages the grid’s intelligence to achieve multiple efficiencies. For example, accurate packet time stamping of parametric data helps avoid false tripping and enables faster, more meaningful cause-and-effect forensics. Phasor measurement and alignment of current and voltage waveforms to a prescribed offset in real time across a

Figure 1 A substation is the grid interconnect consisting of a switch yard (where voltage conversion, line switching and line protection occur) and a control building, lower right, that houses electronics for substation control and timing. RTC MAGAZINE JUNE 2011


technology deployed

Control Center HMI Station Controller


Intelligent Switchgear

Communication Bus IEEE C37.238 Timing

IEC 61850 / Station Bus

Bay Controller

Next Generation (CT/PT (VT)


Bay Controller

IEEE C37.238 Timing (IEEE 1588 Power Profile) Communication Bus


Substation Clock

IEC 61850 / Process Bus Switchgear Merging Unit


Figure 2 A smart substation with all control and timing elements interoperating over Ethernet.

transmission line also helps maintain optimum grid operation. These and other timing applications wouldn’t be possible if devices controlling the network weren’t smart enough to support them. On the other hand, without precise and centrally distributed timing, much of that intelligence—along with grid capacity—would be wasted.

A Massively Distributed Multiprocessor Solution

Today’s smart gird is essentially a geographically dispersed embedded real-time control application employing thousands of processors synced over a network. Like other such applications, this one has a purpose, a topology, a networking protocol (actually two, one for control, the other for timing) and, of course, processors. The purpose is what it has always been: to maintain a precise balance between supply and demand for power everywhere on the grid simultaneously. Absent sufficient grid “smarts,” a sudden surge in either supply or demand—say, because a circuit breaker inadvertently shuts off a town—could cause a widespread power outage like the one that blacked out most of the Northeast U.S. in August 2003. Maintaining this balance in recent years has become much more difficult—with much less room for error—due to increasing demand with no commensurate increase in supply. As a result, the grid now runs “closer to edge.” Thousands of substations exist across the grid and each must make almost instantaneous adjustments in supply for every local fluctuation in demand. The topology actually includes three networks. There are the actual copper wires and switches (or “switchgear”) that carry electricity. There is a control network, including distributed intelligent electronic devices (IEDs) such as circuit breaker controllers, voltage regulators and digital protection relays. These are connected to each other, to the switchgear and to supervisory management stations via fiber optic Ethernet. And thirdly, there is a timing network running over the same fiber optic Ethernet that connects all these other devices to a central clock. All this equipment is



located in geographically dispersed substations (Figure 1). Each of these is responsible for distributing power within an area such as a town. This involves three basic functions: 1) voltage conversion, 2) line switching and connectivity, and 3) line protection (relaying). Within the substation, the switchgear is located outdoors in a switchyard while the IEDs and clock are located in the relay room of a control building, where there are also typically two other rooms—a communications room and a battery room. The communications room houses systems for voice and data communications with other substations and with grid operations centers. That includes supervisory control and data acquisition (SCADA) metrics on how substation devices are performing. Local and remote operators view SCADA data at human machine interface (HMI) consoles. The network protocols connecting these devices run on the same Ethernet fiber optic cable—with one protocol for control (IEC 61850) and the other for timing (IEEE C37.238), as in Figure 2. IEC stands for the International Electro Technical Commission, the organization that prepares and publishes international standards for all electrical, electronic and related technologies. IEC 61850 replaces vendor-specific protocols such as LON, Profibus and Modbus for inter-device data exchange and control within power substations. IEEE C37.238 is a power industryspecific flavor of the Precision Time Protocol (PTP) described in IEEE 1588. PTP’s value is that it enables an inherently asynchronous medium (Ethernet packets) to deliver timing synchronized to 1µs. PTP thus has a major advantage over point-to-point timing protocols, such as the Inter-Range Instrumentation Group – Time Code Format B (IRIG-B), which is how substation devices have traditionally been synced. IRIG-B is a serial binary coded decimal encoding that transmits one data frame of time information (year, day of the year, hours, minutes and seconds) every second—with precision in the 1 ms range. Replacing IRIG-B with PTP (while also implementing IEC 61850) removes the need for hundreds of copper cables, each one connecting a different substation device to a timing source. Not only are all these cables expensive and difficult to install and maintain; in power substations they’re also an electrical hazard. Furthermore, a single timing network enables a unified timing architecture. That reduces the number of timing sources required. Compare that to the multiple clocks of a traditional substation—each one supporting different equipment or applications—with multiple GPS antennas all mounted outdoors on control building rooftops and exposed to the elements. Unified management offers a single view of the substation’s timing infrastructure and the ability to drill down into infrastructure performance parameters such as the variation in timing packet delay across the network. That in turn alerts operators to timing issues so they can be addressed prior to failure rather than only after a failure—as they likely would be with unmanaged multiple autonomous clocks.

Technology deployed

Where Timing Syncs Control at the IED

The “processor” at the heart of this distributed multiprocessor application is an intelligent electronic device (IED). An IED is a firmware-programmable microprocessor-based controller that can serve any one of multiple functions such as a circuit breaker controller, digital protection relay or voltage controller. In a smart substation, for example, when a circuit breaker trips, it’s because an IED monitoring conditions on a substation bay told that circuit breaker to trip. A state-of-the-art IED takes continuous “snapshots” of voltage and current, with a 4.6 µs sample timing accuracy. “Next-gen” IEDs replace a previous generation of substation control hardware comprised of analog electromechanical relays, circuit breakers, voltage regulators and IEDs with less robust capabilities. Current IED architectures offer three key advantages: more functions, better control and less cabling. The first advantage of having a single device that can be assigned multiple roles is that it reduces costs and simplifies operation and maintenance. Its increased intelligence also enables better control. With the previous generation, often the only “control” option was to shut off a circuit when an out-of-range threshold was reached. Devices and operators were limited in the types of information sampled, different ways to respond, or the level of response short of a complete power shut-off. Now both supervisory control and electric power can be applied much more fluidly. Power can be shifted to where it is needed (or away from where it is not) more dynamically with less stress on generators, substation equipment, transmission lines and other assets. Conditions requiring a millisecond response (or faster) may be handled automatically. And both operators and supervisory software have a much wider and deeper view of potential issues as they develop. IEDs that support IEC 61850 for control and IEEE C37.238 for timing enable a fiber optic Ethernet to replace hundreds of point-to-point copper cables between the substation control building and switchyard equipment. To preserve investments in older switchgear and other legacy equipment, most current IEDs still also support IRIG-B. Adaptor solutions—or “merging units”— serve a similar purpose. As previously noted, removing lots of copper in a high-voltage power substation makes the substation a much safer, easier to maintain and less costly environment.

Precise Timing Matters

These benefits are possible because control elements like IEDs and timing sources no longer operate autonomously. It’s that synchronized distributed intelligence, again, that enables the grid to accomplish its purpose: to precisely and dynamically match supply and demand anywhere and everywhere simultaneously—so that the grid can more reliably operate closer to the edge of its capacity. Three applications in particular illustrate the importance of precise synchronization. The first is the ability to take precisely timed and accurate sampled values. IEDs receive current and voltage in IEC 61850 packets either directly from “next-gen” switchyard equipment such as circuit breakers or

indirectly from legacy equipment via merging units that packetize those legacy outputs. In order for IEDs to process this information correctly the IEDs must know when samples were taken. If the IED receives badly timed samples without knowing it, the IED may shut off power to customers. An even more severe consequence happens when the IED cannot interpret the data—it will default to the safe state and trip the breaker, perhaps inadvertently. To properly order the packets and process the sample values, the sampled value applications demand that the timestamps be accurate to within 4.6 µs, with a clock source accuracy of 1 µs. The second application is the ability to quickly locate a fault. When a fault occurs somewhere on a power transmission line, the event sets off an energy wave that travels along the line back to the substation. This phenomenon is very useful for repair crews who otherwise would need to “ride the line” potentially over hundreds of miles of countryside looking for the fault. Instead, the affected IED can simply time the arrival of the wave and multiply by the speed of light to determine the distance to the fault. Again, this requires 1 µs precision. The third time-critical application is phasor measurement. One of the key ways grid operators recognize an issue and take corrective action before the issue gets worse is to measure the phase alignment between voltage and current—optimally 120 degrees. This application requires a time precision of 5 µs (for an optimal TVE), and a clock accuracy of 1 µs precision is needed to support the synchrophasor applications. Measurements like these occur thousands of times a second on each IED—of which there are potentially hundreds in a single substation—with each measurement potentially requiring action by this or other IEDs or by operations personnel sitting at central consoles. Unless everything happens to the beat of a single, UTCsynced, PTP-¬compliant, centrally managed 1 µs-timing source, there would be chaos. Power companies today meet this challenge by implementing comprehensive timing strategies that fully take into account the precision, networking, management and reliability requirements of their timing infrastructures. The old ad hoc approach— simply adding another box wherever and whenever an application needs GPS timing—defeats the purpose of today’s Smart Grid. Like any other distributed processing application, this one also requires unified synchronized intelligence. Symmetricom San Jose, CA. (408) 433-0910. [].



technology deployed Embedded Technologies for the Smart Grid

Smart Grid Security: Less Bruce Willis, More Ben Franklin

however, doesn’t mean the existing energy-grid SCADA networks are secure, and there appears to be wide consensus that the older parts of the infrastructure need additional protection. Security researchers, such as Luigi Auriemma, recently published 34 exploits for common SCADA systems sold by Siemens, Iconics, 7-Technologies and DATAC. Shortly after his work appeared on the Bugtraq mailing list, the U.S. Industrial Control Systems–Computer Emergency Response Team (ICS-CERT) The humble electrical meter—now that it has gotten rushed out advisories to the energy indussmart—has also become a potential avenue for attacks try. And while these particular vulnerthat could lead to great damage to the electrical grid. abilities have been mitigated (or at least, the community has been alerted to them), More attention must be paid to securing these and other the fact that Auriemma, who prior to this exploration r your goal devices that are attached to the coming Smart Grid. research had never before studied SCADA eak directly networks, was able to find so many flaws, page, the suggests others may find even more. resource. Indeed, speaking at Black Hat USA in hnology, nd products by Robert Vamosi, Mocana 2010, Jonathan Pellot of Red Tiger Security said “without the proper security precautions, the electrical grid is now more vulnerable than ever.” His company logged over 38,000 software vulnerabilities in a n the movies, it’s compelling. In a matter of seconds, a hostile common operating system used on SCADA systems within the nation-state sends a string of malicious code to a small-town energy sector. While most aren’t enough to cripple a SCADA SCADA and as a consequence the entire Eastern network on their own, such vulnerabilities provide yet another panies providing solutionsnetwork, now Coasttechnologies of the United States Whether is plunged into vector for an attack. ation into products, and companies. your goal is todarkness research theduring latest the height of toa asummer wave. handsome,isintrepid cation Engineer, or jump company'sheat technical page,Hours the goallater of Geta Connected to put you ce you require for whatever type ofinvestigator technology, digital forensic discovers a “digital cure,” pounces Smart Grid Security Standardization es and products you are searching for. on the foreign hackers in their lair, and in a big shootout (preferShortly after 9/11, the North America Electric Reliability ably with explosions), installs the patch with minutes to spare and Corporation (NERC) issued guidance requiring energy providers fixes everything. to provide authentication technology on their devices to enable The reality is considerably less dramatic. more secure upgrades, and to use AES encryption for all network To date, there haven’t been any publicly documented communication. The 2007 Energy Independence and Security SCADA failures in the energy sector resulting from mali- Act gave these providers until 2009, but Congressional testimony cious digital attacks. That’s not to say that there haven’t been in early 2009 showed “most of the industry had yet to comply.” digital attacks. There have been many. But so far, the power In January 2011, the GAO released a report, Electricity grid’s network of fail-safes and redundancies seems to have Grid Modernization: Progress Being Made on Cybersecurity saved us from the worst scenarios. The example that most Guidelines, but Key Challenges Remain to be Addressed, which fear-mongers like to put forward—namely, the claim by U.S. concluded that while both NIST and FERC made key regulagovernment officials that a two-day blackout in Espirito, Bra- tory improvements during 2010, the U.S. energy industry as a Connected zil, was Get the result of sabotage—has been discounted by Bra- whole continues to suffer. In particular, the GAO cited six areas with companies mentioned this article. zilian authorities. They sayindust from a prolonged drought of concern: and soot from a nearby wildfire affected critical transform1. T  he electricity industry does not have an effective mechaers and were the actual saboteurs. The lack of an example, nism for sharing information on cybersecurity. 2. T  he electricity industry does not have metrics for evaluating cybersecurity. Get Connected with companies mentioned in this article. 3. Utilities are focusing on regulatory compliance instead of comprehensive security.


End of Article



Technology deployed

Figure 1 Even given all the components and stages of the Smart Grid, the weakest link might be the smart meters in the home.

4. Aspects of the regulatory environment may make it difficult to ensure Smart Grid systems’ cybersecurity. 5. Consumers are not adequately informed about the benefits, costs and risks associated with Smart Grid systems. 6. T  here is a lack of security features being built into certain Smart Grid systems.

Trouble at Home

While the state of security within larger energy grid systems remains in question, special attention should nonetheless be focused on the new devices that comprise the Advanced Metering Infrastructure (AMI)—the millions of smart meters now being put into homes nationwide. In response to federal funds available for the rapid installation of these devices, local utilities have been rushing to install them, sometimes with less attention to security concerns than some would find adequate. Cybercriminals may not invest the considerable resources needed to attack energy facilities directly. Instead, they might be able to start an attack with a drive down a residential street. Smart meters, new devices that are being installed in millions of consumer homes, may prove to be lower-hanging fruit to a would-be attacker (Figure 1). Here, issues of authenticating updates and encrypting communications may not have been fully addressed prior to implementation, and provide an opportunity for even greater security today. In other words, we may be worrying about the wrong part of the energy network. The units now being placed inside customer houses lack a good mechanism for authentication of downloaded software and firmware updates. In 2010, Shawn Moyer and Nathan Keltner at FishNet Security demonstrated to audiences at Black Hat USA a proof-of concept smart meter attack using this vector. Using radio equipment and open-source software, they were able to identify nearby smart meters in a residential neighborhood. They were able to circumvent the encryption used and inject malicious

code into the smart meter in the form of a firmware update. Once updated, the code then propagated to other smart meters in the area, creating a Smart Grid worm similar to a PC worm such as ILOVEYOU, a particularly nasty case that spread worldwide in 5 hours. The consequences of such a device-based worm might be more dire than a PC worm. If the smart meter hack Moyer and Keltner proposed were ever loosed in the “wild,” electricity to thousands of homes could be shut off—and it’s not clear that service could be restored without manually re-installing the software on every meter, in person. Such an attack would be expensive to recover from. Furthermore, vulnerabilities within home-based smart meters might allow someone remote access to the rest of the SCADA system. It seems reasonable to state that if the device security of these mass-produced smart meters were held to a higher bar, the overall electrical grid would be better protected. But right now there are no regulatory (or even customary) requirements for third-party security testing or peer review of these devices.

Stopping Meter Malware & Protecting Meter Updates

To protect against the Moyer/Keltner worm, best practices recommend that you digitally sign all of your device firmware, and set up your devices in the field so that they won’t run any code that hasn’t been properly signed. Cryptographic digital signatures ensure that any firmware appearing on the device is from an authenticated source, and that it has not been infected or modified. A cryptographically based automated update allows you to securely distribute software updates to millions of devices in the field, over virtually any network connection—secure or unsecure (Figure 2). With cryptographically based updates, a signed message is placed at a well known URL, which is proRTC MAGAZINE JUNE 2011


technology deployed





Advanced Components • Superconductivity, fault tolerance, storage, power electronics, and diagnostics components

Phasor Demand Measurement Unit Response • WAMS (wide-area • Demand-side measurement management systems) to provide • Distribution real-time monitoring and monitoring control

Advanced Metering • AMR/AMI • Metering/Analysis software • Sensors

Substation Automation • Intelligent Electronic Devices (IED)

Power System Automation • Outage detection and restoration • Voltage stability monitoring and control

Smart Appliances • Load management • Remote load control • Intelligent building

Networks and Transports • WAN/MAN/LAN/ VAN • Wired (BPL, PLC, DSL) • Wireless (RF, WiFi, WiMax, GSM, ZigBee, satellite)

Figure 2 Ideally, security throughout the Smart Grid is needed, not just at the consumer level.


Untitled-13 1


grammed to check for updates. The signed message is then downloaded, authenticated, verified, de-capsulated, saved and/ or acted upon. Products like Mocana’s NanoUpdate enable devices to authenticate incoming software or firmware updates, so that you can distribute new features, patches and bug fixes for your meters and other Smart Grid devices… without rolling a single truck. Additionally, device-based antivirus solutions can actively shut down virus and malware attacks against smart meters and other grid infrastructure devices. But traditional antivirus scanners simply won’t fit into the tight memory and CPU constraints of most smart meters. A new generation of smaller, non-database-oriented anti-malware agents has emerged where every action an application takes is checked against a known “good behavior” model. Mocana’s NanoDefender, for example, continuously scans running processes and terminates non-authorized threads or applications with minimal system overhead and no false positives.

Authenticating Meters & Encrypting Communications

Extensible Authentication Protocol (EAP) is an authentication framework that can be used to protect wireless networks and Point-to-Point connections by providing common functions and negotiation of authentication methods. Solutions exist that can prevent unauthorized access to grid

3/31/11 4:26:15 PM

Technology deployed

devices in the first place. This allows utilities to manage multiple users of the same device who require different security configurations. To ensure that only the devices you designate as â&#x20AC;&#x153;authenticâ&#x20AC;? can participate in your Smart Grid network, issuing X.509 certificates for all of your devices is a long-recognized â&#x20AC;&#x153;best practice.â&#x20AC;? Additionally, there needs to be a way to automate certificate management in devices and applications without increasing resources. Mocanaâ&#x20AC;&#x2122;s NanoCert automates certificate management, and can scale to handle millions of meters. The client software requests certificates, renews them or pulls down revocation lists from most any certification authority (CA), and can issue and revoke certificates at scale. Itâ&#x20AC;&#x2122;s not enough, though, to merely authenticate all of the communicating nodes. You also need to protect data while itâ&#x20AC;&#x2122;s in transit, and while itâ&#x20AC;&#x2122;s at rest on the meter or back at the utility. Best practices, again, dictate that you use government-validated (FIPS 140-2) encryption solutions, but finding a government-certified cryptographic engine is challenging for resource-constrained embedded systems environments. Solutions like Mocanaâ&#x20AC;&#x2122;s NanoCrypto low host-CPU utilization extends battery life on remote sensors, and enables even inexpensive low-end processors to use robust cryptographic techniques to protect sensitive information and authenticate legitimate users, systems and data. â&#x20AC;&#x153;Saving the dayâ&#x20AC;? when it comes to securing the Smart Grid is less Bruce Willis and more Ben Franklin. Some pru-

dent planning and careful implementation can spare us all a lot of drama later. By hardening the weakest (and most populous) entry pointsâ&#x20AC;&#x201D;namely the home-based smart metersâ&#x20AC;&#x201D; the energy industry can continue to avoid the Hollywood disaster story. Mocana San Francisco, CA. (415) 617-1273. []. FishNet Security Kansas City, MO. (816) 421-6611. []. Red Tiger Security Houston, TX. (877) 387-7733. [].

Marvell Armada300 System On a Module The CSB1724, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, low-power, ARMADA 300 (Sheeva ARMv5TE) based System on a Module (SOM). The CSB1724 provides a small, powerful and flexible engine for Embedded Linux based Gigabit networking and storage applications. y y y y y y y y y

1.6Ghz 88F6282 Sheeva ARMv5TE Core 16KByte I/D Caches; 256KByte L2 Cache 512MByte DDR2-800 and 512MByte SLC NAND Two PCIe x1, Two SATA Gen2 and Two USB 2.0 Two 10/100/1000 Twisted Pair Copper Ports On-Chip Crypto and Security Engines with XOR Dual SATA Gen 2 and Dual 480Mbit USB 2.0 Ports 4-Bit SD/MMC, 2-wire TTL UART, I2C, SPI and I2S 3W typ., 4W Max, <10mw Power Down

Now available at The CSB1724 is manufactured in-house on our IPC-610 Certified, lead-free capable surface mount line. All products carry a 1-year warranty and are available in commercial and industrial temperature versions. Cogent offers standard and custom carrier boards, royalty free licensing options and more.

&2*(17 "ALWAYS COMPLETE" Untitled-8 1



11:15:23 AM RTC MAGAZINE 4/28/11 JUNE 2011

technology deployed Embedded Technologies for the Smart Grid

Securing and Improving the Smart Grid Requires Military Grade Technology

use to secure, protect and control vital assets in high-assurance applications. For suppliers of Smart Grid devices such as meters, concentrators, Supervisory Control and Data Acquisition (SCADA) systems, and the communications infrastructure connecting such components, these technologies can expedite the timeto-market for delivering a secure and reliable grid infrastructure. Although it is acknowledged that both physical and cyber security must work hand-in-hand to properly secure the grid, we will focus more here on the cyber world aspects and relate how some of the Smart Grid challenges have been solved in other markets The Smart Grid is vast and complex, uniting a power with military grade operating system distribution system with a data and control network. As technology, middleware, key manageexploration a result, its vulnerabilities are many and often subtle. ment and encryption technologies. r your goal The Smart Grid industry, and in pareak directly Securing this huge system will require military grade ticular the advanced metering infrastrucpage, the attention, tools, systems and attention to detail. ture (AMI), is expanding at a rapid pace resource. hnology, with device manufacturers rushing devices nd products to the market to capture market share while by Jim McElroy, Green Hills Software responding to the demands of utilities, consumers and the government. As a result of this expansion and without full consideration of system and component-level security, industry research estimates that there will eliability and resiliency of the Smart Grid must be the be over 250 million new hackable devices introduced into the primary focus for utilities and their suppliers as the panies providing solutions now Smart Grid in the next five years, dramatically increasing the Smart Grid is critical to both national security and the ation into products, technologies and companies. Whether your goal is to research the latest number of potential vulnerabilities and the overall security risks global economy. With these goals in mind, in-depth vulnerabilcation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ity analysis should be performed on critical infrastructure asce you require for whatever type of technology, sets on a regular basis to ensure cyber-secure device interoperaes and products you are searching for. tion that helps realize the benefits of more reliable and available energy at lower cost and with less impact on the environment. Guest OS Guest OS Eliminating vulnerabilities throughout the grid is important. However, further protection and response mechanisms are necessary to safely quarantine infected or degraded components so they do not adversely affect other subsystems within the grid. In reality, the Smart Grid is now under constant attack and will be hacked, so preparing for this eventuality needs to take place now, both at the business level as well as in the field of devices throughout the grid. Recognizing that the Smart Grid encomINTEGRITY Multivisor passes information technology and control systems assets, security and response mechanisms will need to bridge the gap beGet Connected tween traditional IT infrastructures and industrial operational Single/Multicore Hardware with companies mentioned in this article. control systems. Fortunately, Smart Grid device manufacturers can leverFigure 1 age military grade software and hardware already proven in Health Monitor

Critical Applications

Secure Networking


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A secure RTOS for smart energy creates secure partitions to keep critical applications separate from operating systems that connect to the outside world and enforce security.

2011 Bringing together the design community, IC foundries and design automation tool providers to collectively address the hottest issues, trends and products effecting the electronics industry.

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New Delhi, India


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Bangalore, India


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Shanghai, China

September 6

Beijing, China

September 8

Santa Clara, California

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Hsin-Chu, Taiwan

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Tokyo, Japan


technology deployed

Health Monitor

Critical Applications

INTEGRITY Multivisor

Secure Networking

Single/Multicore Hardware

Guest OS


Secure Communication Flows

INTEGRITY Transmission

Operations INTEGRITY Distribution

Guest OS


Electrical Flows

Figure 2 With the use of a secure RTOS and hypervisor on the Smart Grid, critical components and operations can be placed under the supervision of secure applications and a protected OS.

to the grid. For terrorists and hackers who want to cause harm or steal valuable information, this is great news. For consumers, utilities and the government, hoping to realize the benefits of smart energy, the accelerating number of nodes and resulting attack points lessens the probability of sustained successful secure and safe energy delivery. The threats to the grid are real. Successful exploits to grid vulnerabilities have already resulted in real physical harm. The latest notable example is the Stuxnet worm, which deliberately and successfully attacked a particular industrial control system. Every day advanced persistent attacks occur on the transmission and distribution networks, control and data centers, and field area networks. Attackers are getting smarter all the time and exploits have been observed to take place over seconds, hours, days, months and even years without being detected. Unfortunately, the vast majority of these systems are “secured” by inherently insecure operating systems such as Windows and Linux, deployed in network devices and firewalls. The reality is that most industrial control systems deployed are relying on these insecure operating systems and potentially, even worse, the ability of each individual utility and vendor to keep up with patches that attempt to fix the vulnerabilities. In most cases, these systems and devices are not patched effectively, exposing the grid to attacks and breakdowns. These operating systems simply were not designed for this level of security and resiliency, and it is impossible to introduce these capabilities retrospectively. The grid cannot be secured entirely in its current form. With a complex infrastructure of aging components, mixed with a tremendous influx of new components, offering expanded capabilities and connection strategies, the grid must be secured one large step at a time with an emphasis on securing the most critical and vital assets first. The “Guidelines for Smart Grid Cyber Security” (NISTR 7628) sets the path for securing the Smart Grid and outlines the vulnerability classes for the grid into four primary areas: 1. people, policies and procedures 2. platform software/firmware vulnerabilities 3. platform vulnerabilities 4. network



Focusing here on the platform and network for the Smart Grid, NISTR 7628 identifies a collection of vulnerabilities that may exist in the Smart Grid device platform (hardware, software, firmware and operating system). From the software and firmware perspective, many of these vulnerabilities result from poor code quality, such as buffer overflows, memory leaks and leftover debug code. In addition to poor code quality, poor software design can lead to ineffective error handling, logic errors, protocol errors and weak authentication and authorization practices, potentially exposing vital grid information to unauthorized observation or mutation. For platform software and firmware in critical grid operational assets such as SCADA systems, transmission and distribution controllers, synchrophasors and utility business applications protecting the confidentiality, integrity and availability of information is paramount. As a best practice, a rigorous security-focused life cycle should be in place for developers of critical Smart Grid assets to eliminate device and system vulnerabilities. The aerospace and defense embedded software market can serve as a good model for developing secure and safe embedded devices. A common practice in this environment is to implement a rigorous, traceable software development approach with best-ofbreed development tools. For applications requiring safety, security and reliability, the separation kernel operating system architecture provides significant benefits. This practice enables these software teams to develop devices and systems that isolate, protect and secure software applications and data. Furthermore, in these critical environments the right selection of operating system, tools and hardware can expedite the delivery and also reduce the bill-of-material cost for each secure device. Common high-priority grid vulnerabilities exist in authentication and authorization of devices, applications, firmware and people. It is vitally important to ensure that only the right people, the right devices configured with the right software, and operating on the right information participate in grid functional collaboration. This should start at the earliest stages, even during the hardware manufacturing process where devices must be constructed from trusted and authenticated components. The firmware, middleware and application software all need to be created with security in mind, authenticated and securely “injected” into the device. A trusted boot process should start things rolling when it comes to an authenticated and authorized device joining the grid infrastructure. Public Key Infrastructure (PKI) technology and encryption is now commonly utilized to enable authentication, protection of data, provisioning and authorization. Strong password control, management and even biometrics may also be deployed to properly authenticate actors and data within the system. Addressing the authentication vulnerability requires that only trusted devices with trusted information and trusted communication can interact throughout the grid. Securing and making the Smart Grid network itself more resilient and secure is a vast topic on its own, as there are

Technology deployed

numerous protocols such as Wi-Fi, ZigBee, TCP/IP, WiMAX, GPRS, BPL and PLC used throughout the grid. Furthermore, the SCADA systems often have their own set of protocols. For the entire grid, it is becoming increasingly important to check the validity and integrity of the data at each end of the communication line. Application “whitelisting” is developing into a common technique to protect and ensure secure communication channels and data integrity by only allowing specific applications to see and operate on specific data. Protecting data at rest and in transit throughout the grid is important, and today’s military grade applications leverage the latest in encryption technology to secure the data and the keys to the information. Protecting “key” information about the device, its content, its firmware and applications can prevent tampering, counterfeiting and stealing personal or business information. Firewalls and IPS/IDS systems, such as those fielded in the market today, can help in protecting the grid, however, the reality is that these systems too have only been designed, developed and certified to protect systems against casual or inadvertent attempts to breach system security. They also rely heavily on users properly configuring these devices, which often is not the case. In addition, many of these systems are certified at only Evaluation Assurance Level (EAL) 3 or 4+ at best. This is a topic for another discussion, but suffice it to say that this is not a sufficient level of protection to secure Smart Grid critical assets. At the core of these critical Smart Grid devices, military grade software development tools and operating system technology can and should be deployed to provide high-assurance security and safety in a similar fashion to their use in developing secure aircraft avionics, military equipment, industrial equipment, medical devices and defense systems. In these environments, suppliers of high-assurance technology start with a formal development process, optimized development and debugging tools, and a secure and resilient platform upon which they deploy safety and security- critical applications. An example of such a platform is the Green Hills Integrity real-time operating system. Green Hills Software, specializing in high-assurance platforms and solutions, has successfully taken specific versions of this technology through a number of certifications in varying critical software domains. The Integrity operating system technology has achieved an EAL6+ high robustness certification from the NSA, having passed formal analysis and rigorous NSA penetration testing, demonstrating that this operating system has been designed and constructed specifically for the task of protecting high-valued assets from well-funded attackers. It is this type of technology, with security designed in from the start, which should be deployed to protect the critical assets of the grid. Not all vulnerabilities of the grid can be covered in this article. However, looking at the overall platform of software, hardware and the network connecting the nodes throughout the grid, vulnerabilities primarily exist in weak architectural design. Examples include no defense in depth, inadequate malware protection, ineffective logging and alerting mechanisms, and a weak

and insecure operating system infrastructure. Security and resiliency must be built into the platform itself, from the ground up, and that means the hardware and the software operating system upon which all applications run. Many military grade applications now leverage separation kernel technology with an intrinsic hypervisor to enable time and space isolation for applications and data, potentially running under different operating systems, safely and securely. With this architecture in place, Smart Grid intelligent electronic devices can have security, safety and resiliency built in where no one application can adversely affect other applications running in their own partition. System monitors, device drivers, communication stacks can all safely run in their own virtual address spaces, safely and securely. This military grade platform architecture also enables the capture of forensic evidence throughout the lifecycle of the applications. Degraded components can be safely quarantined and log files can be managed safely and securely. Military grade software development methodologies, tools and platforms can provide the foundation for building a more resilient Smart Grid. Green Hills Software Santa Barbara, CA. (858) 965-6044. [].



ploration your goal k directly age, the source. ology, d products



PCI Express Meets DSP

DSPs with PCI Express Interface Expand Embedded Connectivity Options Lower cost broadens usage of DSPs in real-time, range of other markets.

by Krishna Mallampati, PLX Technology


hile PCI Express (PCIe) has become wildly successful throughout virtually all market segments, DSP a few were slower to adopt this powerful serial interconnect standard. Wireless x1 base stations, for example, have yet to take advantage of PCIeâ&#x20AC;&#x2122;s speeds (now 8 Gbit/s in PCIe Gen 3). In the case of the base PCIe Gen 2 stations, this is because the main procesx1 x1 Switch sor used is a DSP, which vendors had not nies providing solutionswith now PCIe. integrated ion into products, technologies and companies. Whether yourproprigoal is to research the latest Instead, they offered their own x1 ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you etary interfaces or Serial RapidIO (SRIO) you require for whatever type of technology, meaning real-time/embeddedVideo and productsinterface, you are searching for. FPGA ASIC Encoder systems designers had limited choices when looking to connect several different endpoints. This in turn meant those designers had to depend on expensive FPGAs or ASICs to develop endpoints; because the Figure 1 ecosystem surrounding the proprietary Digital video recorder/network video recorder. and/or SRIO interface was very limited, ASICs and FPGAs essentially became the only choices for the wireless base stations. Freescale and LSI, however, have started PCI Express Blankets Market DSP vendors such as Texas Instruments, to integrate PCIe natively into their prod- Segments uct offerings, enabling designers over the With the 700-plus members in the PCI past year to take advantage of the huge Special Interest Group having deployed Get Connected ecosystem behind PCIe. the standard into markets ranging from with companies mentioned in this article. consumer and small-office electronics to

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DSP x2

PCIe Gen 2 Switch



x1 Video Encoder



Figure 2 Digital video recorder/network video recorder, with x2 upstream connection.

enterprise and cloud-computing systems, the ecosystem for PCIe is both enormous and responsible for bringing down the cost of designs using the interconnect. That ecosystem has developed over the past decade because PCIe has successfully penetrated graphics, storage, servers, communications and embedded systems—helped immensely by the ubiquity of PCIe interfaces on everything from high-end CPUs from Intel; GPUs from Nvidia and AMD; embedded processors from Freescale, AMCC and Cavium; and consumer products from Atheros, Marvell, Broadcom, Infineon and Conexant. Wi-Fi modules, set-top boxes, cable modems and home gateways now feature PCIe, and both the volume and number of product types are growing by leaps and bounds. This “marriage” of PCIe and processors, and those devices’ use in x8




PCIe Gen 2 Switch

x2 DSP

x2 DSP


high-volume products, has helped to drive the presence of PCIe into so wide a range of market segments and more importantly lower the costs for end-users, making it a win-win for all involved. Now DSPs incorporate the PCIe interface, which offers designers more options for connectivity and at an even lower price. This is especially important given the penetration of PCIe into rapidly evolving DSP product categories, which include not only wireless base stations but other market segments such as video surveillance systems, video communications, medical and biological imaging, home A/V equipment, and digital video recorder/network video (DVR/NVR) boxes. This new development, blending the two distinct yet compatible technologies, benefits DSP makers, system designers and end-users alike. Designers have numerous options in PCIe interconnect and are now able to maximize both the performance and power efficiency of DSP designs. Additionally, that efficiency is achieved by taking advantage of PCIe switches’ flexible ports and lanes, small packages and unique ability to fan out to a number of endpoints.

DSP Providers Recognizing Importance of PCI Express Figure 3 A typical DSP Farm

DSP vendors have realized that the markets in which they’re active are demanding more connectivity options.

Designers need a standard interface that is both inexpensive and widely used by millions, with a solid ecosystem that guarantees multiple sources for any device. Additionally, DSP vendors no longer have to add multiple interfaces to satisfy their varied customer base; they can add one lane of PCIe 2.0 (Gen 2) at 5 Gbit/s and save significant space by removing several pins of any proprietary interface on their packages, enabling them to offer more cost- and function-optimized devices. Also, since PCIe has been around since early in this decade, the cost structures are now at a point where it makes economic sense to utilize the interface. Furthermore, with the ecosystem so huge, connecting to PCIe endpoints is extremely easy. Last but not least is the emergence of endpoints based on the latest complementary interconnect technologies such as USB 3.0, whose bandwidth requirements are supported by PCIe Gen 2. Since most DSPs with PCIe have only two lanes configured as one x2 PCIe port, switches optimized for DSPs ensure connectivity to the large number of endpoints. Let’s take a look at some of the usage models in applications using DSPs and low-lane-count PCIe switches.

DVR/NVR – Digital Video Recorder / Network Video Recorder

In the DVR/NVR usage model illustrated in Figure 1, the single x1 interface from the DSP is being fanned-out to connect to several endpoints, which are PCIe-native. If the PCIe interface did not exist on the DSP, then the designers would have to use proprietary interfaces to connect these endpoints, which would have been difficult to implement on the FPGA or ASIC, not to mention in the video encoder. For designers worried that the bandwidth between the processor and the PCIe switch could be a bottleneck, the PCIe switch offers a x2 configuration for the DSP that supports such a configuration, as shown in Figure 2. Since the connection between the DSP and the PCIe switch is now x2 wide, as shown in Figure 2, there isn’t any bottleneck in the system. In fact, the trend in the market is that most designers no longer need to do their own ASICs; most everyRTC RTC MAGAZINE MAGAZINEMONTH JUNE 2011



Fan-Out Connections Using PCIe, DSPs DSP




PCIe Gen 2 Switch



USB 3.0

Figure 4 Fan-out in a set-top box.

thing is moving toward an ASSP because the interface is now standardized on PCIe. Having a standard interface helps develop the ecosystem around DSPs. Because DSPs support only one x2 PCIe Gen 2 interface, a PCIe switch plays an even more significant role in the design: It not only provides fan-out but also helps balance the speeds and feeds in the system, due to its flexibility to operate at both Gen 1 (2.5 Gbit/s) and Gen 2 speeds on each lane or port independently. This is tricky, however, because the market segments using DSPs are varied. Some, as in enterprise systems, need the PCIe switch to provide a large number of lanes and ports for scalability (Figure 3), while others must satisfy the “Three Ps” essential in consumer designs such as set-top boxes: package, power and price. Since the boards and systems in some segments are size-limited, it is crucial for the PCIe switch to come in the smallest possible package. Power is of extreme importance in these designs, as many feature no heat sinks and/or airflow. It is essential that these designs require no unnecessary components, which would drive the total system cost up while adding to their power draw.



DSP Farm

In this usage model (Figure 3), several DSPs are connected to a central PCIe switch through which the processing power of the system is greatly enhanced. Such a usage model is extremely attractive for vendors who want to enhance the performance of their system without incurring a high expense for implementing it. The PCIe switch and PCIe interface on the DSPs enable these designers to use a technology that is widely available and is extremely cost-competitive compared to other technologies. Figure 3 shows a perfectly load-balanced usage model—the x8 upstream from the PCIe switch provides up to 40 Gbit/s, and the four x2 ports from the DSPs provide 40 Gbit/s as well, resulting in no bandwidth bottleneck in this system. The flexibility of PCIe switches is really critical for such applications. In Figure 3, the DSP farm has only four DSPs, but designers need the assurance that a PCIe switch will not be a limiting factor if they want to scale their designs. If the designer decides to scale up to 12 or 16 (or more) DSPs and wants a x16 upstream port, the PCIe switch vendor must support such configurations. Obviously, the higher the number of DSPs connected in a DSP farm, the greater the processing power and the more powerful such a system will be.

While not typically considered a realtime/embedded design, set-top boxes illustrate how designers working in several market segments can use DSPs to implement fan-out connections to a Wi-Fi radio and a USB 3.0 endpoint, as shown in Figure 4. In this usage model, the PCIe switch is providing pure fan-out connectivity to multiple endpoints. With USB 3.0 emerging as the successor to USB 2.0 (thanks to the 10x speed bump), the trend is pointing toward more and more devices incorporating this technology, thus driving up the need for PCIe connectivity. In Figure 4, again, there is no bandwidth bottleneck. The 1 x2 Gen 2 upstream port from the switch provides 10 Gbit/s and the 2 x1 Gen 2 downstream ports together provide 10 Gbit/s—perfectly load-balanced without any bottleneck! With PCIe technology having become as ubiquitous as it now is, along with DSP-based designs now adopting PCIe on a large scale, we can look forward to an even broader ecosystem in which DSPs and PCIe complement one another seamlessly. Still, DSPs likely will continue to be limited in the number of PCIe lanes and ports they can support, making versatile PCIe switches all the more important in DSP-based designs. To satisfy the requirement for DSPfriendly PCIe switches, vendors such as PLX Technology are bringing to market devices that are both power- and space-efficient while also flexible and high in performance. These switches presently are being designed into the full range usage models cited above. DSP and PCIe silicon vendors will continue to speed the evolution of the PCIe ecosystem, giving designers the necessary elements to further deploy the PCIe Gen 2 standard, along with the emerging PCIe Gen 3. PLX Technology Sunnyvale, CA. (408) 774-9060. [].

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There was a time when if an application had some special functions that needed to be executed very fast and often, one alternative was to use an FPGA as a special-purpose co-processor that could offload these operations from the CPU. The tables now seem to have turned a bit. BittWare has announced a floating point co-processor chip for use with Altera’s high-performance FPGAs. The Anemone chip, featuring the Epiphany architecture from Adapteva, is a scalable, true C-programmable, floating point engine that enables novel solutions for complex and evolving signal processing applications. Because it was specifically designed to be used alongside an FPGA as a co-processor, the Anemone simultaneously achieves superior power efficiency and processing performance. Each Anemone features 16 processors, providing 32 GFLOPS of floating point processing while consuming only 2 watts of total chip power. Multiple Anemones can be gluelessly connected, thereby scaling to create compute blocks of up to 4096 processors providing 8 TFLOPs of floating point performance. Delivering a standard processor software development environment that tightly integrates with an FPGA platform from Altera, the Anemone allows the best of two worlds to be combined—facilitating increased productivity and optimal solutions for complex signal processing applications. Anemone was designed specifically for complex signal processing rather than for I/O, protocol processing, memory interfacing, or special functions, thus creating an extremely efficient chip compared to traditional floating point DSPs that may use only 5% of the silicon area for processing. This has translated into the scalable 1 GHz multicore processor. Each eCore processor features a compact, general-purpose instruction set that requires no instruction level parallelism and provides high program efficiency. All floating point computations are performed as single-precision



IEEE 754; hardware looping is also supported. Anemone offers distributed and segmented memory, and large uniform register files. On-chip distributed shared memory is 4 Mbit (32 Kbyte per eCore) with 32 Gbyte/s of sustained memory bandwidth within each eCore. The cache-less shared memory architecture is extended off-chip, and between chips, via external I/O links. The Anemone features an internal high-throughput mesh network, with separate data paths for on-chip and off-chip communications. Each eCore processor has a multichannel DMA engine to support background data movement over the ‘eMesh’. Total on-chip, inter-core bandwidth is 128 Gbyte/s full duplex, with an additional 8 Gbyte/s of off-chip bandwidth. Each router node can simultaneously sustain full-duplex transfers on all ports, with automatic routing based on global addressing. The Anemone provides a flexible low-overhead external interconnect scheme that supports memory-mapped direct connection of multiple Anemones and is compatible with any LVDS-capable FPGA. This is achieved via four Links that are full-duplex 8-bit LVDS data ports at 500 MHz DDR, each simultaneously providing 1 Gbyte/s in each direction for a total off-chip bandwidth of 8 Gbyte/s. Its FPGA co-processor use model provides the ultimate flexibility: since all external I/O goes through an FPGA, system designers can customize the I/O to their application’s specific requirements. The Anemone reduces system development cost by enabling out-of-thebox execution of applications written in regular ANSI-C. It does not require any C-subset, language extensions, or SIMD. Standard GNU development tools are supported including an optimizing C complier, simulator, GDB debugger and Eclipse multi-core IDE. The Anemone will be available from BittWare on standard COTS boards, including FMC (VITA 57), AdvancedMC (AMC), VPX (VITA 46/48/65) and PCI Express (PCIe) slot cards starting in Q3. Development boards, software and systems will also be available. BittWare, Concord, NH. (603) 226-0404. [].


Gang Tester Improves Efficiency During Boundary Scan in Mass Production

A new gang tester enables users to test or program up to 16 boards in parallel, applying only one central controller. With the SFX-TAP16/G from Goepel Electronic, users are now able to implement highly compact and cost-efficient gang test applications. The system utilization also increases efficiency in the production at significantly reduced manufacturing costs. The new TAP transceiver’s concept is based on modularly configurable TAP Slot Cards (TSC) and Power Slot Cards (PSC). By this, the system can be freely adapted to nearly any kind of UUT interface and gang numbers. Investments are protected by the hardware’s exchangeability and upgradeability. The number of TAPs on the UUT may vary between eight (2 UUT) and one (16 UUT). The Power Slot Cards enable the individual power supply per UUT, monitoring the power consumption and feature isolating relays. In addition to solutions for TSC and PSC, Goepel Electronic provides engineering services to develop project-specific modules and turnkey gang testers. SFX-TAP16/G is also available as a pure kit without housing for integrations on customers’ sites. The SFX-TAP16/G can be open configured, supporting numerous modern test and program strategies such as Processor Emulation Test (PET), core assisted Flash programming, chip embedded instrumentation and protocol driven interface tests as well as Boundary Scan. It can also be freely combined with all Scanflex controllers supporting PCI, PCI Express, PXI, PXI Express USB, GBit LAN, FireWire or LXI, whereby the distance can be up to five meters. The new gang testers are fully supported in the industrially leading JTAG/Boundary Scan platform SYSTEM CASCON from version 4.5.4 on. Get Connected with technology and GOEPEL Electronic, Jena, Germany. +49 3641-6896-0. []. companies providing solutions now

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Low-Power USB 3.0 to SATA Bridge Controller

A new Low-Power USB 3.0 to SATA bridge controller features a fully integrated 5V switching regulator. The Via Labs VL701 LowPower USB 3.0 to SATA Bridge is a single-chip solution that achieves high power efficiency while offering users transfer rates up to 10 times that of USB 2.0. The VL701 is a highly integrated single-chip solution that allows users to connect any SATA hard disk drive (HDD), solid state drive (SSD), or optical disc drive (ODD) to their PC via USB 3.0. With data transfer rates of up to 5 Gbit/s, data stored on SATA devices can be transferred to a PC in a fraction of the time it would usually take compared to USB 2.0 or Firewire. The VL701 has been certified by the USB Implementers Forum (USB-IF) while adhering to strict power-consumption criteria for buspowered devices. The comprehensive suite of tests conducted as part of the USB-IF Compliance and Certification Program ensures that certified products are interoperable with existing USB devices while also offering all the speed and power enhancements of the USB 3.0 specification.

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly RISC-Based Touch Computer Extended with an Screen Application Engineer, or jump with to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Temperature Range Whichever level of service you require for whatever type of technology, A new RISC-based embedded will computer Get Connected help you connect with the companies and products with a bright 8.4” TFTyou LCD targetedfor. as a wideareissearching

temperature, ruggedized, flat panel computer able for a variety of HMI and control applications. Featuring new LED backlight technology, the SeaPAC R9-8.4 from Sealevel Systems offers an extended operating temperature range of -30° to +70°C with no heaters or cooling fans required. Powered by a 200 MIPS ARM9 micropro- with technology and companies prov Get Connected cessor, the SeaPAC R9-8.4 isGet available with upistoa new resource for further exploration into pro Connected 256 Mbyte RAM and 256 Mbyte Flash memory. datasheet from a company, speak directly with an Application Engine in touch with the right resource. of service you requir Standard I/O includes Ethernet, serial, USB, CAN Bus Whichever and digitallevel interfaces. Get Connected will help you connect touch with the companies For intuitive operator interface, the system includes a resistive screen that and produc is suitable for a wide range of industrial environments and uses. The SeaPAC R9-8.4 is intended for panel mount applications and provides an aluminum front bezel that maintains NEMA 4/IP65 protection from sprayed liquids. Local or remote I/O expansion is available using Sealevel SeaI/O modules. Choose from a variety of I/O configurations including optically isolated inputs, Reed and Form C relay outputs, TTL interfaces, A/D and D/A. The SeaPAC R9-8.4 connects to SeaI/O modules via the system’s RS-485 expansion port and communicates using Modbus RTU. The Windows CE 6.0 BSP binary and low-level drivers for system I/O are included. Additionally, the SeaPAC R9-8.4 software package is equipped with the Sealevel Talos I/O Framework, which offers a high-level object-oriented .NET Compact Framework (CF) device interface. This interface provides an I/O Get Connected with companies point abstraction layer with built-in support forand easily interfacing the system’s products featured in this section. I/O. Linux support is also available. Low quantity pricing starts at $1,599.


Sealevel Systems, Liberty, SC. (864) 843-4343. [].

VIA Labs, Taipei, Taiwan. 886-2-2218 8924. [].

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Fanless Industrial PC with Modular I/O for Hazardous Locations

Already ruggedized for dependable computing in sites subject to extreme temperatures, shock and vibration, a new server Industrial PC now has Underwriters Laboratory (UL) certification for Class I Division 2 Group A, B, C, D hazardous locations with volatile substances. This UL approval permits use of the I/O Server fanless embedded computer from Acromag and its plug-in I/O modules in environments with flammable liquids, gases, or vapors. UL’s Class I Div 2 certification is often required for electronics deployed in chemical, oil, gas, mining and other manufacturing facilities. With the higher safety rating, the I/O Server can be installed closer to sensors and actuators to reduce installation costs for monitoring and control of automated machinery. Additionally, the I/O Server has no internal cables and conduction cooling removes heat without open vents or fans for more reliable operation from -40° to 75°C. Two models offer a choice of an embedded Intel Atom N270 1.6 GHz or AMD Geode LX800 500 MHz CPU that runs on Windows Embedded Standard or Linux and has up to 1 Gbyte of DDR2 RAM. Standard interfaces include VGA graphics, two Ethernet ports, two serial ports, four USB ports, a CompactFlash slot and audio input/output jacks. An internal 2.5” PATA hard disk or solid-state drive is accommodated as a user-installed option. Acromag offers several programmer support tools. A Windows development package provides API development software and Win32 DLL drivers, plus examples for C, Visual Basic, .Net and LabVIEW environments. The Linux software includes a library of I/O function routines to speed code development. Both packages include demonstration programs with C source code to test and exercise the I/O module operation. Acromag Wixom, MI. (248) 295-0310. [].

14-Bit PCIe Digitizer Offers High Data Throughput and High Dynamic Performance

A PCI Express digitizer provides 200 MS/s sampling rate of 14 bits of data across one channel. The PCIe-9842 from Adlink Technology is designed for applications such as light detection and ranging (LIDAR) tests, optical fiber tests and radar signal acquisition. Its 100 MHz bandwidth analog input is designed to receive ±1V highspeed signals with 50Ω impedance. With this simplified front-end design and highly stable onboard reference, the PCIe-9842 provides not only high-accuracy measurement results but also delivers high-dynamic performance. For applications that require data to be acquired and transferred in real time, the PCIe9842 is designed on the PCI Express x4 bus interface to provide adequate bandwidth for realtime transfers. As the signal is converted from analog to digital, the data will be transferred directly and continuously at a sustained 400 Mbyte/s rate to the host system memory. Endusers will further benefit from a typical dynamic performance that includes a 11.3 effective number of bits (ENOBs) and a 70 dB signal-to-noise ratio (SNR) with an input frequency of a 10 MHz sine wave. Adlink not only provides legacy drivers for users to develop using Microsoft C++ and Visual Basic, but also a task-oriented driver (DAQPilot) to accelerate the development cycle. Express VIs and Polymorphic Vis for the PCIe-9842 also provide a quick and simple way to operate the digitizer in LabVIEW. Current one list price is $3,000. ADLINK, San Jose, CA. (408) 360-0200. [].



Modular Chassis Kit Speeds Slim, Compact Design for Embedded Applications

A specially designed chassis kit for Em-ITX form factor boards enables the rapid and easy assembly of a wide variety of robust fanless embedded system designs. Measuring 35.2 mm high and 231 mm wide, the AMOS-5001 from Via Technologies is slim enough to fit in most space-constrained environments. Systems built using the AMOS-5001 are also shock resistant and can withstand extreme temperatures. The AMOS-5001 chassis kit features a unique modular design comprised of only four mechanical parts, which ensures the easy integration of Via’s EITX-3001 series mainboards. An optional 2.5” HDD storage subsystem chassis is also available. The kit makes it easy to assemble robust x86 embedded systems that can withstand a wide temperature range of -20° to 55°C and are capable of sustaining a g-force of up to 50. AMOS-5001 chassis are easy to assemble and maintain, utilizing only four separate mechanical parts to form a slim, robust fanless system. The AMOS-5001 chassis combines with the unique integrated heatsink design found on Em-ITX boards. The discrete aluminum heatsink has direct contact with the processor and chipset on the reverse side of the board, forming a solid, robust base for chassis assembly. An optional storage compartment can also be added. VIA Technologies, Fremont, CA. (510) 683-3300. [].


Open-Source IDE Covers Entire Microchip Line with Support for Linux, Mac OS and Windows Users

A comprehensive open-source integrated development environment has been created for the entire portfolio of 8-, 16and 32-bit microcontrollers from Microchip Technology. The MPLAB X IDE—with cross-platform support for Linux, Mac OS and Windows operating systems—provides a host of high-performance features that have been added to the new IDE, including the ability to manage multiple projects and tools with simultaneous debugging, an advanced editor, visual call graphs and code completion. And, MPLAB X is unique in the industry with its support for all the devices made by the company—including all 800+ PIC microcontrollers, dsPIC digital signal controllers and memory devices. The designers of today’s leading-edge embedded applications are demanding an IDE that provides a solid foundation for high-performance, user-friendly and flexible development. They also want it to be compatible with a wide range of development tools for a broad and reliable microcontroller portfolio with easy migration to decrease the learning curve and protect their tool and code investments. MPLAB X provides a single, unified graphical interface for Microchip and third-party tools, including the MPLAB ICD 3, PICkit 3 and MPLAB REAL ICE debugger/programmers. MPLAB X is based on the Oracle Sponsored open-source NetBeans platform, which has an active user community that can contribute a wide range of enhancements and third-party plug-ins. In fact, Microchip customers can take advantage of a host of free NetBeans software components and plug-ins that exist today. Additionally, the NetBeans platform allows MPLAB X users to customize the IDE to suit their individual development needs. Additional features of the new MPLAB X IDE include an import utility for quick and easy migration of projects from old MPLAB IDE platform, code completion and context menus via advanced editor and a configurable watch window. The MPLAB X IDE includes support for compiler Get Connected withmultiple technology and versions simultaneously and provides team collaboration tools for bug tracking and source-code control. The MPLAB X IDE can be solutions explored today companies providing now via a free download from Get Connected is a new resource for further exploration

Ad Index

Microchip Technology, Chandler, AZ. (888) 624-7435. [www.].

EPIC SBC with Single or Dual Core 1.66 GHz ATOM for Industrial Applications

An EPIC-compatible, 1.66 GHz ATOM-based single board computer (SBC) uses either the Intel ATOM single core N450 or dual core D510 processor combined with the ICH8M I/O hub controller, both of which are supplied from Intel’s Embedded Architecture Division for long-term availability. The EPX-C380 from WinSystems is operational from -40° to +70°C and provides an open platform for processor- and I/O-intensive solutions for demanding applications such as medical, COTS/military, security, transportation, pipeline and machine control. The EPX-C380 measures 115 mm x 165 mm (4.5” x 6.5”) and is compatible with the Embedded Platform for Industrial Computing (EPIC) computer board standard. The EPX-C380 uses the integrated Intel Gen 3.5 graphics processor, which incorporates both VGA and LVDS display interfaces with resolutions of 1400 x 1050 and 1366 x 768 respectively. Memory support includes up to 2 Gbyte of DDR2 667 MHz SODIMM system memory as well as a CompactFlash socket and optional 2 Mbyte battery-backed SRAM. The EPX-C380 has two Gigabit Ethernet ports, two SATA channels and eight USB 2.0 ports plus four RS-232/422/485 asynchronous serial channels on board. Also a parallel port consisting of 48 lines of digital I/O, high definition audio (7.1 codec), LPT interface, real-time clock and a watchdog timer round out the onboard I/O. PC/104-Plus and MiniPCIe connectors are included for expansion with either standard or user-designed specialty I/O modules. It supports WES 7, Linux, Windows XP Embedded and a vast software development tool set including device drivers and libraries. It also supports other x86-compatible real-time operating systems such as QNX and VxWorks. The EPX-C380 requires only +5 volts and typically draws 1.9 amps (typical) with 1 Gigabyte of DDR SDRAM installed. The board is RoHS compliant. WinSystems, Arlington, TX. (817) 274-7553. [].

into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with thewith right resource. Line of High-Speed CMOS Synchronous DRAMs Whichever level of service you require for whatever type of technology, Densities up toGet 256 Mbit will help you connect with the companies and products Connected you are searching for. A full line of new, high-speed

CMOS synchronous DRAMs (SDR) with densities of 64 Mbit (AS4C4M16S), 128 Mbit (ASGet Connected with technology prov 4C8M16S)and andcompanies 256 Mbit (AS4C16M16S), is optimized for industrial, communications, Get Connected is a new resource for further exploration into pro datasheet requiring from a company, directlybandwidth. with an Application Engine medical and consumer products highspeak memory touch with the right resource. Whichever level of service The devices introducedinby Alliance Memory are particularly well you requir Get Connected will help you connect with the companies and produc suited to high-performance PC applications. The SDRs are internally configured as four banks of 1M, 2M, or 4M word x 16 bits with a synchronous interface, operate from a single +3.3-V (± 0.3V) power supply and are lead (Pb) and halogen free. Packaged in a 54-pin, 400-mil plastic TSOP II, the new SDRs offer a fast access time from clock down to 4.5 ns at a 5-ns clock cycle, and clock rates from 143 MHz to 200 MHz. Alliance Memory’s SDRs provide programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto pre-charge function provides a self-timed row precharge initiated at the end of the burst sequence. Easy-to-use refresh functions include auto- or self-refresh, while a programmable mode register allows the system to choose the most suitable modes Get Connected with companies and to maximize performance. Pricing for U.S. delivery ranges from products featured in this section. $0.90 to $1.80 in 1,000-piece quantities.


Alliance Memory, San Carlos, CA. (650) 610-6800. [].

Get Connected with companies and products featured in this section.




Express Logic Introduces Memory-Protected Application Modules for ThreadX RTOS

Express Logic has announced the introduction of ThreadX RTOS Memory Protection for downloadable application modules. Downloadable application modules, introduced earlier this year, enable ThreadXbased applications to execute functions dynamically loaded from local mass storage or a network. Memory protection for these modules adds a level of safety and security that enables developers to protect other modules and the ThreadX kernel itself against unintended damage from errant external access. Memory protection is achieved with minimal software or hardware overhead by using the processor’s memory protection unit (MPU) or memory management unit (MMU) and no virtual address space. Any code within a particular module that attempts to access memory outside that module is prevented from making that access, and a system fault is generated. The RTOS then transfers control to an error handler that the application sets up to deal with the error. The module might then be disabled while allowing the rest of the system to continue operation, send an error message to an operator, or halt the system to prevent further damage. As a result, applications gain increased reliability, security and functionality without the cost of increasing overhead or memory. ThreadX memory protection technology is suitable for situations where application code is developed by multiple team members, new application modules need to be added after the product is deployed, or partial firmware updates are required. Virtual memory, memory protection and a kernel-module architecture are commonly found in desktop operating systems, such as Windows and Linux, and in larger RTOSs, such as VxWorks and QNX. Such architecture and functionality is not commonly found in smallfootprint RTOSs like ThreadX, nor is the “big-system” method of implementation appropriate for such RTOSs, where even a small number of additional instructions can represent significant overhead. Such overhead can interfere with hard real-time response for which these systems are best suited. ThreadX is available in full source code form, royalty-free, with project license prices starting at $12,500.

Static Analysis for Multicore and Multi-Threaded Applications

Managed OpenVPX 10 Gigabit Ethernet Switch for High Performance Applications

Development teams are embracing multicore processors such as the new quad-core Intel Core i7 processor because they are the most promising avenue to better computing performance. This is because traditional performance-improvement approaches, such as increasing clock speed, decreasing memory access times and clever scheduling of instructions, are no longer yielding major improvements. Unfortunately, multicore systems are much less forgiving of programming errors and can be extremely difficult to debug with currently available tools, especially when bugs are intermittent and difficult to reproduce. The severity of the problem caught the attention of the Defense Advanced Research Projects Agency (DARPA), which awarded a $749k contract to GrammaTech to develop an innovative approach to eliminating serious defects that commonly plague multicore applications. This lead to a new program-analysis engine from GrammaTech that identifies data race conditions and other serious concurrency defects. The engine is being incorporated into the company’s popular CodeSonar staticanalysis tool. The resulting analysis pinpoints such problems without testing, slashing development cost and reducing the risk of defects slipping into production. The analysis can also be applied to multi-threaded applications running on a single processor. The technology is compatible with a wide range of compilers, including ARM RealView, CodeWarrior, GCC, G++, Green Hills, HITECH, IAR, Intel C/C++, Microsoft Visual Studio, Renesas, Sun C/C++, Texas Instruments, CodeComposer, Wind River and many others. For some run-time environments, it may be necessary to model synchronization primitives, but the system has been designed to make this easy.

GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [].

GrammaTech, Ithaca, NY. (607) 273-7340. [].

Express Logic, San Diego, CA. (858) 613-6640. [].

A rugged 6U OpenVPX data plane switch module is targeted at demanding high performance computing (HPC) and networking applications such as communications, ISR and radar. The GBX460 from GE Intelligent Platforms now offers customers a choice between the fully managed switch with the flexibility, versatility and functionality provided by the OpenWare suite of protocols and switch management software, or the alternative time-to-operation of the unmanaged version. The GBX460 with OpenWare supports high throughput interprocessor communication (IPC) between 10GigE-enabled processing nodes for deployed network-centric defense and aerospace applications. Its non-blocking 10GigE ports provide high performance throughput across the VPX backplane; the non-blocking feature means that the GBX460 can pass traffic across all 10GigE ports at wire speed without bottlenecks. The GBX460 can support multiple OpenVPX slots/module profiles for maximum flexibility and throughput. The standard build provides 20 x 10GigE data plane fat pipes and 16 x 1 GigE control plane ultra-thin pipes to support multi-board 6U VITA 65 (OpenVPX) system configurations. Multi-board systems can be configured by using the GBX460 together with GE processor cards such as the SBC622 Intel Core i7-based single board computer and IPN250 and NPN240 NVIDIA CUDA GPGPU processors to scale to extraordinary levels of performance for size, weight and power (SWaP)-constrained applications such as deployed image, radar, sonar and signal processing.




MIPS-Based, FPGA-Optimized Soft Core CPU Supported by VxWorks

Altera, MIPS Technologies and System Level Solutions (SLS) have introduced a MIPS-based, FPGA-optimized soft processor for use on Altera’s FPGA and ASIC devices. The MP32 processor is a MIPS-compatible application class processor that inherits a large ecosystem of software development tools and operating system support. The MP32 processor is the first FPGA-based soft processor supported by Wind River’s VxWorks RTOS and the MIPS Navigator ICS software development suite. When combined with Altera’s portfolio of embedded intellectual property (IP) cores, FPGA design tools and a comprehensive array of programmable logic devices, the MP32 processor is attractive for the development of flexible, single-chip solutions used in networking, video and digital signal processing applications. The MP32 processor is distributed and supported through Altera Embedded Alliance partner SLS. SLS brings an extensive portfolio of IP, systems knowledge and FPGA design experience to deliver fully validated, ready-to-deploy MP32 processor-based solutions. Software developers using the MP32 processor can leverage MIPS’ extensive ecosystem of software development tools and operating systems. The processor is supported by the MIPS Navigator ICS software development suite and System Navigator EJTAG debug probes. For debug and trace, the MP32 processor is supported by TRACE32, a best-in-class debug and off-chip trace probe from Lauterbach. Developers can now run VxWorks on an FPGA-based soft core processor. VxWorks delivers real-time performance capable of handling the most demanding time constraints. VxWorks enables developers to reuse software assets and utilize the Wind Workbench software developGetRiver Connected with technology and ment suite to help accelerate time-to-market with run-time integrated tools for configuring, debugging and companies profiling software onnow the MP32 providingrunning solutions processor. Wind River provides world-class support and a VxWorks board support package (BSP) for the MP32 a new resource for further exploration Get Connected into products, and companies. Whether your goal The MP32 processor is designed to be used with Altera’s Qsys system integration tool. System architects cantechnologies quickly and easily construct is to the latest datasheet from a company, speak directly complex, flexible and differentiated solutions by assembling the MP32 processor with a broad portfolio ofresearch embedded, networking, video and digital with an Application Engineer, or jump to a company's technical page, the signal processing IP from Altera and its global IP partners. goal of Get Connected is to put you in touch with the right resource. The MP32 processor is currently available from SLS, who sells and supports the MP32 Whichever processorlevel core. The MIPS Navigator ICS type software of service you require for whatever of technology, development suite and a VxWorks BSP for the MP32 processor are available from MIPS andGet Wind River respectively. The MP32 processor Connected will help you connect with the companies is and products you are searching for. royalty-free and is sold on an unlimited use basis when targeting Altera’s FPGA devices.

Ad Index Altera, San Jose, CA. (408) 544-7000. []. MIPS Technologies, Sunnyvale, CA. (408) 530-5000. []. System Level Solutions, San Martin, CA. (408) 856-2469. [].

Compact 60 Watt Convection-Cooled Power Supplies Feature Medical and IT Safety Approvals

Two new convection-cooled open-frame AC/DC power supplies are each capable of delivering 60W. Offered by Emerson Network Power, the new NPS62-M has a 5 VDC output and can deliver up to 11A, while the NPS65-M has a 24 VDC output and can deliver up to 2.5A. The output voltage of each power supply can be adjusted by plus or minus 20 percent. Both the NPS62-M and NPS65-M power supplies carry a comprehensive set of worldwide IT equipment (ITE) and non-patient contact and non-patient-critical medical safety approvals. They have a safety ground leakage current not exceeding 275 µA when operating from their maximum input voltage. Both models have a compact 2 x 4 inch (51 x 102 mm) footprint and a height of just 1 inch (26 mm), which makes them ideal for use in light industrial, instrumentation and process systems, as well as in low-power dental and laboratory equipment. An optional enclosure kit (LPX50) is available for maximum protection. NPS62-M and NPS65-M power supplies have a full load operating temperature range of zero to 50°C, and can be used at up to 80°C with suitable derating. They both provide tight regulation, maintaining the output voltage to within plus or minus 2 percent for all standard line and load conditions, and feature optional remote sense capabilities to compensate for a 0.5V drop in the output cables. The power supplies are comprehensively protected against fault conditions and have a high demonstrated mean time between failures (MTBF) of more than 550,000 hours. Emerson Network Power, Carlsbad, CA. (760) 930-4600. [].

System-on-Module Packs Performance into UltraSmall Form Factor

A new system-on-module (SoM) is Get Connected with technology and companies prov implemented in an ultra-small form fac-

Get Connected is a new resource for further exploration into pro tor of only 15 x 27 x 3.8 mm using the datasheet from a company, speak directly with an Application Engine Texas Instruments DaVincilevel DM3730 in touch with the right resource. Whichever of service you requir and Sitara AM3703 processors Get Connected will help you connect with the running companies and produc

at up to 1 MHz. The Torpedo SoM from

LogicPD can also enter a suspend state in which it consumes less than 5mW. The DM3730 Torpedo is available in several configurations, including TI’s Sitara AM3703 version of the ARM Cortex-A8 microprocessor. It is also footprint compatible with LogicPD’s existing OMAP35x SoM to extend the roadmaps of existing products. The Torpedo includes a programmable color LCD controller that supports XGA 1024 x 768 with 24-bit color along with 256 Mbyte of Mobile DDR and 536 of NAND Flash memory. Additional interfaces include a parallel camera interface, audio codec, one USB 2.0 port, serial I/O in the form of UARTs, SPI and I2C. There is also a 40-pin debug connector on top side, which supportsandJTAG and ETM. Software Getthe Connected with companies support includes boot in loader/monitor and board support packages products afeatured this section. for Android, Linux and Windows CE. In addition, the Zoom DM3730 Torpedo development kit includes all the needed accessories to begin development.


LogicPD, Minneapolis, MN. (612) 672-9495. []. Get Connected with companies and products featured in this section.




Large Panel Creates New Opportunities for Projected Capacitive Touch Displays

A large projected capacitive (PCAP) touch panel stands to bring the kind of engaging user interface made popular on smartphones to a much wider range of applications, including environmentally challenging embedded systems and applications made for multiple users to use simultaneously. The newest addition to Crystal Touch line of PCAP touch panels from Ocular LCD measures 15.6 inches diagonally and has an outline of 356 by 223 mm along its perimeter. Unlike some PCAP displays that only support one or two simultaneous user touches, the 15.6-in. Crystal Touch display supports a true multi-touch interface with as many as 16 simultaneous touches. True multi-touch capabilities are critical to a number of applications such as gaming, medical diagnostic equipment, industrial controls, food services, interactive maps and other systems that require simultaneous actions and involve collaboration among multiple people. Due to its glass construction, the Crystal Touch is resistant to scratching, harsh chemicals and other contaminants. It operates over an industrial temperature range from -30° to 70°C. The optical clarity of the projected capacitive panel is far superior to other types of touch panels, such as resistive touch. The very thin, 1.6 mm profile of the panel makes it ideal for lightweight mobile devices, like tablet PCs. The 15.6-in. Crystal Touch PCAP true multi-touch panel is currently available in sample quantities and will be available for volume shipments in June 2011. Minimum volume pricing starts at $109 per unit. Integrated solutions that combine an optically bonded TFT display with a Crystal Touch panel are also available. Ocular LCD, Dallas, TX. (972) 437-3888. [].

Conduction-Cooled Rugged Armored Portable UPS Chassis

Combining the latest uninterruptible power supply developments in UPS power and Lithium iron phosphate (Li-FePO4) battery technology, the DesertGecko UPS 1000 from PCI Systems delivers more than 650 watts of uninterrupted power for deployed and mobile systems—having a very small footprint available in a 1/2 ATR size and horizontal radio type mount. The DesertGecko UPS 1000 has a wide working temperature range from -20° to +70°C; extremely cold or hot weather will not affect its performance. High safety supervisory circuits guarantee that no fire or explosion occurs in overcharge tests at up to 40V, and in short-circuit tests the unit survives without damage. A long life cycle of more than 2000 charging times means high availability in environments where power supply problems are present. The unit offers full power conditioning in low-quality power environments and lightning protection in harsh weather. Additional features include the latest in lithium ion battery technology, embedded battery power management and charging circuitry. It offers a wide range of features, including full EMI shielding, thermostat-controlled fans (ATR chassis), replaceable dust filters, embedded shelf remote management and power fault signaling and over-voltage protection circuitry. The DesertGecko UPS 1000 meets the battlefield environmental specifications of MILSTD-810F. The solid core batteries reduce leakage risk, eliminating HAZMAT and environmental concerns and facilitating shipment by air or ground without restriction. PCI Systems, Silver Spring, MD. (301) 358-3621. [].



Military Grade SSD SelfDestructs with the Push of a Button

A new series of rugged Military-grade storage devices is engineered to withstand the severe conditions encountered in the line of duty while delivering comprehensive data protection. The new MIL-SPEC S5 Series SSD from Emphase is an SLC flash device available in a 2.5” footprint and SATA (3 Gbit/s) bus interface. The MIL-SPEC S5 SSD has one clear objective: secure data. This level of reliability hinges on endurance as well as overall performance. This vault-like device can process data with read speeds up to 170 Mbyte/s and write speeds up to 90 Mbyte/s and it is designed to meet the environmental requirements of MIL-STD-810F. The Emphase MIL-SPEC S5 SSD is loaded with options for handling data in breach of security scenarios including data write-protection, secure and quick erasure, and data destruction. With these defense-grade triggers, data can be eliminated in less than two seconds through an ATA command or with the push of a button. Should the drive lose power during a protect, erase, or destroy command, the device will resume the command as soon as power is restored. The MIL-SPEC S5 SSD is currently available in 16 Gbyte to 128 Gbyte capacities, and with 256 Gbyte and 512 Gbyte models in development, is ready for longterm exposure to extreme levels of humidity, wide temperature ranges, intense shock and vibration, and high altitude. All devices are available with conformal coating, tightly managed BOM and a 5-year warranty. Emphase is a GSA Schedule 70 Contract Holder and all products are available for acquisition under General Purpose Commercial Information Technology Equipment, Software and Services – SIN 132-8. Emphase, South Burlington, VT. (802) 735-1799. [].


Tool Suite Provides Requirements to Object-Code Traceability

In the safety-critical domain, devices required to meet the most critical levels of certification must verify software traceability from requirements through design to code at both source- and object-code levels. Now a tool suite from LDRA offers full requirements to object-code traceability, ensuring that verification problems found at the object-code level can be quickly and easily traced to the originating source code and requirements levels. Evidence that all lines of software have been fully tested at the source- and object-code levels is becoming more important for a number of industries. DO-178C, the new avionics software standard, will soon mandate this for the most critical software, and the medical and automotive industries are recognizing that this verification process is equally valuable in their environments. Discrepancies caused by compiler interpretation or program optimization can lead to code verification passing at the source level, but failing at the object-code level. Tracing the object codeâ&#x20AC;&#x201D;also referred to as assembler codeâ&#x20AC;&#x201D;back to the originating highlevel source code is a tedious, time-consuming challenge without requirements to object-code traceability. LDRA pioneered requirements to object-code traceability to reduce the time and risk for companies developing embedded software that must meet the highest levels of safety standards. In the past, many companies needing to meet stringent certification requirements verified their object code using in-house tools. However, with the adoption of more complex architectures, engineering teams no longer have in-house expertise on the modern architectures, nor can they afford to develop and maintain complex object-level verification tools for project-specific implementations. LDRA equips developers with the ability to review code instruction by instruction, while eliminating the cost of developing and maintaining tools in-house. â&#x20AC;&#x153;In the medical community where 510k filings take 18 months or longer to be processed for compliance with the Medical Devices Act, thereâ&#x20AC;&#x2122;s an understandable desire to develop, test and file for compliance as soon as possible,â&#x20AC;? commented Dr. Jerry Krasner, principal analyst of Embedded Market Forecasters. â&#x20AC;&#x153;Software verification tools, particularly those that automate requirements traceability to object code, provide an additional level of confidence that code has been thoroughly executed, tested against requirements and verified. Far too often, verification is a bottleneck for process completion.â&#x20AC;? LDRA, Wirral, UK. +44 0151 649 9300. [].

USB to RS-485 Serial Adapter for Extreme Environments

A new single-port USB to RS485 serial adapter incorporates a ruggedized, overmolded enclosure to offer fast, reliable serial communication for even the toughest environments, including factory floor, mobile and outdoor applications. The serial port appears as a standard COM port to the host computer enabling easy setup and providing compatibility with legacy software. The SeaLINK+485-DB9 from Sealevel Systems features programmable baud rate and data formats with 128-byte transmit and 384-byte receive buffers for fast, error-free communication. Each adapter includes a removable terminal block adapter (Item# TB34) that simplifies field wiring. Thumbscrews on the TB34 secure the terminal block adapter to the serial port and prevent accidental disconnection. SeaLINK+485-DB9 is compatible with all standard PC baud rates and supports high-speed communication to 921.6 Kbit/s. The adapter is powered by the USB port and status LEDs molded into the enclosure indicate serial data activity and connection to the host. All SeaLINK USB serial adapters ship with Sealevel Systems SeaCOM suite of Windows drivers and diagnostic utilities. WinSSD, a full-featured application providing powerful testing and diagnostic capabilities, is also included. Use WinSSD for Bit Error Rate Testing (BERT), throughput monitoring and transmitting test pattern messages. The SeaLINK+485-DB9 operates over an extended temperature range of -40° to +85°C. Single unit pricing is $89. Sealevel Systems, Liberty, SC. (864) 843-4343. [].

Conduction Cooled VME Solid State Disk Phoenix Internationalâ&#x20AC;&#x2122;s VC1-250-SSD Conduction Cooled Serial ATA (SATA) based Solid State Disk VME blade delivers high capacity, high performance data storage for military, and y, aerospace p industrial applications requiring rugged, extreme emee envi eenvironmental i ron ronmen me tal and secure mass data storage.

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with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




ACCES I/O Products...................................






MEN Micro, Inc.......................................... 20..................................

Microsemi (formely White Electronics & Actel)................17...............

End of Article

American Portwell Technology, Inc..............

Multicore Board Showcase......................... 21.................................................................

Get Connected with companies and Arbor Solutions........................................... products featured in this section.

One Stop Systems...................................... with companies mentioned in this article.

Avalue Technology...................................... 10................................

Pentek, Inc..................................................

Axiomtek.................................................... 16...................................

Get Connected with companies mentioned in this article. Phoenix International.................................. 53....................................

Get Connected with companies and products featured in this section.

Get Connected Cogent....................................................... 37...................................

Sealevel Systems.......................................

Extreme Engineering Solutions, Inc.............. 7.......................................

Tech Design Forum..................................... 39......................

Innovative Integration.................................. 25...........................

The MathWorks, Inc.................................... 2.................................

Logic Supply, Inc........................................ 36................................

WDL Systems.............................................

Measurement Computing............................

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ÂŽ Computing/HMI



Data Acquisition for Distributed I/O.


SeaI/Oâ&#x201E;˘ data acquisition modules provide powerful digital, analog, and serial expansion to any computer. Connect to the host via wireless, Ethernet, USB, RS-485, or RS-232 to add the functionality required for your particular application. Multiple units can be daisy chained using convenient pass-through connectors to create a versatile distributed control and monitoring network.

Monitor and control I/O from a mobile device. Find out how and view other helpful videos at

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Easily Control I/O from Mobile Devices via 802.11

SeaI/O modules are perfect for a wide variety of applications including process control, data acquisition, broadcast communications and remote environmental monitoring.

SeaI/O Digital and Analog I/O Modules Wireless






Powerful Mobile SCADA Application for iPad > > 864. 843. 4343

Learn more about SeaI/O Data Acquisition Modules at or scan this QR code with your smart phone.

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Proven Results for Your Application

RTC magazine  

June 2011 Issue

RTC magazine  

June 2011 Issue