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The magazine of record for the embedded computing industry

April 2011

Strategies Abound:

Developing with Programmable Logic

Microcontrollers Get Application Specific Small Controllers Run Advanced Energy Systems Software Targets Safety where Danger Could Lie An RTC Group Publication


fully-assembled turnkey solutions Run, drive, or fly your Simulink design in real time, using Rapid Prototyping or Hardware-in the-Loop simulations on low-cost PC-based hardware. xPC Target provides a library of device drivers, a real-time kernel, and an interface for monitoring, parameter tuning, and data logging. It supports a full range of standard IO modules, protocols, and target computers.

m ®

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Simulink and xPC Target™


©2010 The MathWorks, Inc.



Developing with Programmable Logic

50 AdvancedMC Card with Second Generation Core Microarchitecture

53 CompactPCI Serial SBC Brings Serial Interfaces to Rugged Computing


54 Transient Recorder Combines Channel Density with High-Precision Measurements



Technology in Context

and Reusable FPGA Frameworks Let Engineers Do 36Portable What They Do Best – Design

Microcontrollers Go after the Details HD and 3D Buried in the Chip: 6Editorial Right Sizing the Micro: Honing in Embedded Systems Go More Visual 16 on the Right MCU for the Job Industry Insider TECHNOLOGY DEPLOYED 7Latest Developments in the Embedded Marketplace Control for Advanced Energy Systems TECHNOLOGY CONNECTED Small Form Factor Forum Controls Enable 40Advanced 10When Is a Standard Not a Standard? Security for Networked Devices Airborne Wind Power Generation Extra Levels of Security for Editorial Connected Client Devices 12Guest 20 Adding Evolution – It’s a Good Thing! Industry watch Products & Technology Safety-Critical Software 50Newest Embedded Technology Used TECHNOLOGY IN SYSTEMS Software: Things to Consider by Industry Leaders Developing with Programmable Logic When Building Products That Can 46Safe Cause Injury Utilizing a Flexible Interconnect EDITOR’S REPORT Architecture for System Design 24 Advances in Embedded Processor Jeffry Milrod and Kristen Zaffini, BittWare

Keith Curtis, Microchip Technology

Brian MacCleery, National Instruments

Jonathan Miller, Diamond Systems

Robert Day, LynuxWorks

Ken Maxwell, Blue Water Embedded



New Embedded Generation Fuses x86 with Parallel Processing Engine Tom Williams

Aaron Ferrucci, Altera

ASP-Type Devices: New Approaches for a New 30 Programming Paradigm Greg Brown, Xilinx

Digital Subscriptions Avaliable at RTC MAGAZINE APRIL 2011


APRIL 2011 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

Art/Production CREATIVE DIRECTOR Jason Van Dorn, ART DIRECTOR Kirsten Wyatt, GRAPHIC DESIGNER Christopher Saucier, GRAPHIC DESIGNER Maream Milik, LEAD WEB DEVELOPER Hari Nayar,

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HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, Editorial Office Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214

Published by The RTC Group Copyright 2010, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


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To Contact RTC magazine:

10/16/09 11:43:57 AM


Tom Williams Editor-in-Chief

HD and 3D Buried in the Chip: Embedded Systems Go More Visual


think it may be the integrated graphics. Embedded systems have broken out of their preconceived roles as industrial controls, instruments, transportation systems, toaster and microwave controllers, automotive systems, sensor networks, robotics, small data acquisition and a million other applications into even wider territory. And if it seemed that embedded intelligence was permeating every aspect of daily life, it’s getting even bigger. When someone at a social gathering used to ask me what I did, the very next question was “What is an embedded system?” My standard answer was a short explanation summed up by the quip that it involved, “Hiding the computer behind its own usefulness.” In other words, the user of a device like a microwave oven or a gas pump was supposed to simply use it based on its functionality and not even be aware that an embedded processor was doing all the work behind the scenes. Such systems could be headless or have a user interface. Of course even most headless systems, such as an automotive controller, do have a user interface. But in the case of the car, that interface is the wheel, accelerator, brake and transmission that we are familiar with from the stick shift days. They just hook up to the processor buried beneath. In the case of embedded systems with user interfaces, they have until now been mostly buttons or a small touch screen. Now enter a new generation of embedded processors with high-quality 3D graphics integrated on-chip as exemplified by the Atom family from Intel and the recently announced G Series from AMD. These babies can give you full HD streaming audio and video over an HDMI interface or interactive 3D graphics rendering. Suddenly we’re not talking small touch screens anymore. We’re talking big touch screens, touch screens with compelling interactive graphics, graphics that can be buried in small devices but talk to big displays. This is no longer hiding the computer behind its own usefulness. This is putting that usefulness in your face. At the same time it is stretching the definition of what we once comfortably thought of as a distinction between consumer electronics and industrial electronics. Consumer electronics were what consumers consciously used for the inherent electronic



functionality of the products: TVs, cell phones, home audio equipment, set top boxes and PCs. Industrial electronics comprised all that stuff that was hidden or had application in stages of service or production that are “pre-consumer”—manufacturing, street lights, etc. The availability of high-end graphics and video on a small form factor module is bound to accelerate the effects of what is (not well) known as Williams’ Law of Technology Utilization, which clearly states that the originator of a technology does not have the vaguest idea of how it will ultimately be used. Turn this stuff loose into the world and see what happens. Previously unknown applications of embedded intelligence, such as digital signage (is that industrial or consumer?), which have just started to emerge, will get a tremendous boost from such capabilities. High quality imaging on all manner of medical equipment down to small handheld devices will be greatly enhanced. Things as seemingly mundane as POS systems where you can order from a display in the top of your restaurant table, casino gaming systems, kiosk systems and many more will grow from the capability of the technology unleashing the creativity of the developers. Then think about what may have been considered those stodgy old industrial systems. Wouldn’t it be nice to actually be able to see what a machine tool is doing, or to bring the model created by the CAD system right onto the factory floor? Humans are visual animals, so I predict that the ability to interact with all kinds of applications through the medium of a visual model will take these models from where they currently reside, namely the development space in things like visual mathematical models or physical models, and enable them to be used as the actual user interfaces for small embedded devices as well. At the same time our everyday lives will be increasingly touched by visual displays all around us coming from devices and systems that were once hidden but are increasingly in our awareness and beckoning us to interact with them. And a huge amount of this visual content will be available from anywhere by means of the web. These projections are, of course, only small attempts to see the potential. Be prepared to be amazed.


INSIDER APRIL 2011 SFF-SIG Standardizes Rugged Memory Expansion for Small Form Factor CPU Boards The Small Form Factor Special Interest Group has announced the public availability of the new RS-DIMM Rugged Memory Specification. The Specification defines a highly rugged, DDR3 mezzanine memory module with a pin-and-socket connector optimized for small form factor CPU boards in applications with exceptional shock and vibration requirements. Use of this standardized memory module provides significant flexibility in memory sizes compared to memory soldered to a CPU board. An RS-DIMM module provides a significantly higher level of resistance to shock and vibration than commercial grade memory expansion modules such as SO-DIMM. In addition, the specification provides for both RAM and a Flash memory SSD drive on the same module through a SATA-2 interface. The Specification was created by the Rugged Memory Working Group at SFF-SIG, consisting of connector, memory module and CPU board suppliers working together to achieve an optimal definition. Simultaneously with this announcement, two memory module suppliers, Swissbit and Virtium Technology are each introducing RSDIMM modules. The RS-DIMM Specification defines a small 67.5 mm x 38 mm module that stacks 7.36 mm above the CPU board. RS-DIMM uses DDR3 technology and is specified for both unbuffered and registered implementations. Memory sizes up to 4 Gbyte with optional ECC (error correction circuitry) are supported using either 9-chip or 18-chip designs. Ruggedness is achieved by using a 240-pin Samtec BTH/BSH connector pair on the memory module and CPU board, along with two mounting holes. By avoiding the socket “wings” that hold an SO-DIMM in place, RS-DIMM modules can fit on a number of small form factor CPU boards, such as Processor AMC modules, which cannot use SO-DIMM because of the overall width (72 mm). Finally, the pin definition for RS-DIMM closely aligns with the SO-DIMM pin definition, making it easy to adapt an existing SO-DIMM-based design to use a rugged RS-DIMM module. A prototype RS-DIMM module has been tested on a Lippert COM Express module being announced simultaneously, with the shock and vibration results exceeding the levels defined in the ANSI/VITA 47-2005 (R2007) specification. The RS-DIMM Specification is freely available on the SFF-SIG website and can be downloaded free of charge and without license or registration.

PICMG Ratifies CompactPCI Serial Specification

The PICMG standards organization has announced the successful completion and adoption of the CompactPCI Serial (CPCIS.0) specification. This specification adds greater support for serial point to point fabrics like PCI Express, SATA, Ethernet and USB in the classic CompactPCI form factor. The specification contains definitions for both system and peripheral slots in 3U and 6U board sizes. This new specification includes definitions for eight PCI Express links, eight SATA/ SAS serial buses, eight USB 2.0/3.0 buses and eight Ethernet interfaces at system slots.

This specification defines a modular computer system, consisting of a backplane, a system slot and up to 24 peripheral boards. CompactPCI Serial defines the support of PCI Express, SATA/SAS, USB and Ethernet, concurrently. PCI Express, SATA/SAS and USB are arranged as a simple star architecture. Ethernet is a full mesh. Switch boards are not required and therefore not described. To support the high-speed serial interfaces a connector is introduced that is compatible to IEEE1101. The mechanical design is fully backward compatible to CompactPCI and will interoperate with existing systems.

This specification allows the implementation of hybrid backplanes: CompactPCI Serial with CompactPCI, CompactPCI PlusIO and/or with CompactPCI Express. 3U and 6U boards are supported with the main focus being on 3U. For 3U a new conductive cooling mechanical concept is introduced, which allows it to use all boards in a conductive-cooled environment as well. CompactPCI is a wellestablished industrial specification for modular computers. The IEEE 1101-compliant mechanics are robust and proven in use. The electrical interface is based on the parallel PCI bus. This technology will suc-

cessively be replaced by serial, high-speed, point-to-point connections. CompactPCI Serial uses the mechanical concept of CompactPCI and uses serial interconnect technology. CompactPCI Serial does not need special infrastructure hardware. The migration from CompactPCI to CompactPCI Serial is made rather simple by using hybrid systems. Even for these, no dedicated switch or bridge boards are required because of specifications like PICMG 2.30. PICMG 2.30 brings a limited number of serial interconnects to the backplane so that modern peripheral cards can be inserted into legacy CompactPCI systems. All mechanics are compatible to IEEE 1101.

Wind River On-Board Program Helps Partners Develop Board-Specific Development Kits

Wind River has announced the expansion of the Wind River On-Board Program, which will provide participating commercial off-the-shelf (COTS) processor board vendors with software tools, documentation and training to develop, test and validate their own unique Embedded Development Kits for the first time. Embedded Development Kits provide customers with processor boards and optimized configurations of Wind River’s operating systems, development tools, embedded hypervisor and graphics software. Wind River will enable board vendors to create their own Embedded Development Kits using Wind River’s automated board support package (BSP) validation suite, technical support and training. This will provide customers access to a larger variety RTC MAGAZINE APRIL 2011


EVENT CALENDAR May 2-5, 2011 Embedded Systems Conference San Jose, CA

May 17, 2011 Real-Time & Embedded Computing Conference Washington DC/Reston

May 19, 2011 Real-Time & Embedded Computing Conference Long Island, NY

of Embedded Development Kits with assured tight integration with Wind River run-time and tools technologies. Leveraging pre-integrated off-the-shelf solutions helps reduce risk and support costs resulting in faster time-to-market. Embedded Development Kits from Adlink, Advantech, Emerson, Eurotech, Intel and Kontron are available today. Additional Embedded Development Kits from Curtiss-Wright, GE, RadiSys and other vendors are expected to be available later in 2011.

May 24, 2011 Real-Time & Embedded Computing Conference Boston, MA

May 24, 2011 MEDS 2011 Conference Boston, MA

June 5-10, 2011 Design Automation Conference San Diego, CA

June 21, 2011 MILESTONE Conference Military Electronics Design Baltimore, MD milestone2011

June 23, 2011 MILESTONE Conference Military Electronics Design Nashua, NH milestone2011

June 28-30, 2011 Mobile Computing Summit Burlingame, CA

If your company produces any type of industry event, you can get your event listed by contacting: This is a FREE industry-wide listing.



VXS Architecture Expected to Grow 3x by End of 2012

The research firm VDC Research released its report titled 2010 Embedded Hardware Market Intelligence Service: Embedded Boards Supply-side Analysis - Slot Single Board Computers, showing growth expectations of nearly 3x for VXS from 2009 to 2012. Independent polling of VXS Marketing Alliance, VITA members and customers also suggests a continued increase in the migration from VME/VME64x architectures to VXS. “VME has experienced a number of evolutions during its more than 25 years in existence. These have allowed the architecture to remain not only relevant, but prominent in many designs and production cycles. An important part of this evolution is the VXS standard, which has brought new performance capabilities, including high bandwidth serial fabrics to the VME architecture,” said Richard Dean, VDC’s Embedded Hardware & Systems research practice director. VXS brings high-speed serial IO capability and up to 30 Gigabits per second data rate performance, while maintaining the vast VME hardware and

software ecosystem. This provides a powerful combination of performance, wide selection and cost-savings. “The VXS architecture continues to evolve with higher performance options and new features,” said Justin Moll, Chair of the VXS Marketing Alliance. “With a combination of performance, backward-compatibility and a wide selection of established products in the marketplace, VXS continues to grow and thrive.”

3D Imaging Software Helps Researchers Understand 19th Century Painting Techniques

The Swiss Institute for Art Research (SIK-ISEA) is studying the studio practice of Swiss painters of the late 19th / early 20th century, the materials they used for their paintings, and the deterioration processes the paintings undergo as they age. Among other issues this study is looking at the paintings’ grounds, which are mixtures of binding media, fillers and pigments applied to a suitable support as a preparation for painting. In particular, it has set a focus on the possible connection between the porosity of grounds, their absorption characteristics, the overall appearance, and the stability of the paintings. In attempting to characterize the degree of porosity or the capability of a ground to incorporate moisture, the study addresses a pressing conservation question: The presence of an absorbing layer within the painting build-up has important consequences for the painting’s stability. Issues of water-accelerated reactivity and moisture gradient-assisted material mobility within complex paint systems have been recognized but never studied. The characterization of the structure of absorbent ground layers is a first step toward the study of the mobility of mate-

rials between layers. Recent research at the Art technology department of SIKISEA in collaboration with TOMCAT beamline at PSI Villigen has shown that X-ray tomography is a uniquely powerful method to study the internal structure in intact ground samples. The current research challenge is twofold and lies in (1) estimating precisely the distribution of voids and pores and the connectivity of the porosity network at a micrometer scale, and (2) visualizing the impregnation and transport of moisture through the ground. The 3D tomographic data sets are being studied using the Avizo software, which enables visualization and quantitative analysis of the data sets by providing appropriate filtering algorithms and advanced segmentation tools.

Curtiss-Wright Announces Program for Lead-Free Components in Rugged Military Products

Curtiss-Wright Controls Embedded Computing (CWCEC) has announced that it is offering lead-free assemblies on selected strategic product lines. These CWCEC products have been designed, tested and built using the company’s extensive lead-free knowledge base and have been implemented using advanced approaches to reduce lead-free risk and provide customers confidence in meeting their rugged reliability requirements. The introduction of leadfree components and assemblies into aerospace and defense systems poses a substantial reliability risk unless proper measures are taken. To meet this challenge, CWCEC has, over the last several years, worked diligently to develop an expansive leadfree knowledge base. This leadfree expertise includes connec-


tions to leading-edge lead-free research, standards and policy establishments (for example, the PERM (Pb-free Electronics Risk Management consortium). CWCEC has taken specific measures to optimize the use of lead-free components in rugged COTS products, including detailed analysis of the various reliability risks and the implementation of effective mitigations against these risks.

DiSTI, ALT Software and Green Hills Collaborate on New Visual Interface Bundle

ALT Software and Green Hills Software have joined with DiSTI in announcing a new comprehensive visual development software bundle for the embedded community, offering an “out of the box” solution for the rapid development and deployment of visual interfaces utilized in standard and safety-critical embedded systems. VIBE includes DiSTI’s next-generation 3D Human Machine Interface (HMI) design

tools, ALT’s advanced 2D and 3D graphics device drivers for embedded systems, and Green Hills’ safety and security certifications for embedded software. DiSTI’s latest version of GL Studio Embedded will supply developers with the ability to generate code through a consistent and reliable method, eliminating the need for hand coding. Already flying in multiple aircrafts, ALT’s embedded OpenGL graphics drivers are certifiable to DO-178B and EUROCAE ED-12B Design Assurance Level A. Green Hills Soft-

ware contributes the MULTI IDE development tool with sophisticated capabilities that will allow the developer to quickly generate, debug and optimize code. Certified in a range of industries, Green Hills’ Integrity Real-Time Operating System (RTOS) will set the standard for the safety, security and reliability of embedded systems.

777.54 (-0.64%) This data is as of April 11, 2011. To follow the RTEC10 Index in real time, visit COMPANY






Adlink Technology












Concurrent Computer -

Elma Electronic


Enea Interphase Corporation



























Mercury Computer Systems






Performance Technologies






PLX Technology






RadiSys Corporation






RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities. RTEC10 is sponsored by VDC research

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTC MAGAZINE APRIL 2011




Colin McCracken & Paul Rosenfeld

When Is a Standard Not a Standard?


s we start our fourth(!) year writing the SF3 column for RTC magazine, our frequent readers should have detected a couple of themes that have come up repeatedly in our columns. One revolves around the evolution of technology that has all but forced the abandonment of mainstream technologies in use for 20+ years that are more than adequate for hundreds of currently deployed embedded applications. The obsolescence of these older technologies, such as the ISA bus, has forced equipment companies to spend hundreds of thousands, if not millions of dollars to upgrade equipment with new CPU boards sporting a spanking new PCI Express bus interface that is virtually useless in these applications while embracing an obtuse and complex bridging procedure to continue to use proven ISA I/O devices. Technology evolution for the convenience of component suppliers continues to plague our industry. While there is not one shred of evidence that our beating on this issue has changed anyone’s product roadmap, we hope that we have provided at least some comfort to those of you who deal with this problem every day. You have lots of company. The second overriding theme for the past three years has been standards. Standards abound. They are everywhere. Every new proprietary SFF board seems to result in a specification being written and a feel-good promo club being formed. All it takes is a specification and a web site. The reasons are clear. A spate of component discontinuances over the past decade has resulted in the (premature) end of life of dozens of small form factor boards. This has driven frightened OEMs to seek only solutions with the perception of a long life, multiple vendors and a rich ecosystem— hence industry standards. Under traditional guidelines, industry standards resulted from ideas and concepts being discussed and presented at working groups under the auspices of independent standards organizations such as VITA, PICMG and PC/104. But bringing your idea to this type of organization engenders some risk. First, you are probably telling your competition what you are thinking about fairly early in the game. Secondly, the group may not like



your idea. Even worse, they may change it. Finally, as soon as the working group gets going, you lose control. So, in the standards “gold rush,” and in an even madder rush to maintain control, SFF suppliers have come up with a new way to create a “standard.” Build a unique new product. As it is finished, write a specification that describes it in generic terms. Register a clever domain name. Contact a few of your suppliers, or weaker competitors and cajole them to join in your standardization effort. Put their logo on your web page. (Note to self: Since you already have a product ready for production, they are not a really competitive threat.) Don’t ask for money—membership in your “club” has to be free. Crank up the marketing machine and bring the world its newest SFF industry standard. There are a couple of problems here. Remember those three goals? Long life: Could be. But the life cycle control is in the hands of the company that created the new “standard” (not a multi-member standards organization), and if it doesn’t take off, it’s history. Also it should be noted that they can change the spec any time they please—after all, it’s theirs. Multiple vendors: Well, maybe eventually. But a serious second source is going to think twice about joining and investing in a “standard” that is controlled hook, line and sinker by a single company. If other vendors do show up, it’s the low end of the totem pole. Rich ecosystem: Same deal. Investment from third parties in the ecosystem is a serious issue. If it is Intel creating the standard, then fine. We believe in Intel’s ability to promote and support for the long haul. But if it’s coming from your local garage, then you have to seriously ask who would make such an investment and take such a risk. These so-called logo clubs (because member contribution is pretty much limited to putting their logo on the web site) are easy to set up and may be hard to distinguish from the real thing. They have a web site, distinct from their founding company. They may even incorporate a non-profit corporation, which may not be traceable back to their founder. They may have pretty graphics and fancy names. So caveat emptor, as if you didn’t know already.

1GHz PC/104 SBC

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Fanless, low power 1GHz Vortex86DX processor PC/104 Bus compliant form factor (90 x 96 mm) 512MB of soldered-down onboard DRAM 1MB of battery-backed SRAM CompactFlash socket Optional 512MB onboard SSD flashdisk Full-featured I/O includes: • Two 10/100 Mbps Ethernet ports • Four USB 2.0 ports • Four serial RS-232/422/485 ports • ESD protection on LAN, USB, and serial ports • 16 lines of general purpose I/O • PATA, LPT, PS/2 KYBD and Mouse controller • Mini PCI and PC/104 expansion connectors • WDT, RTC, status LEDs, and beeper Extended temperature -40°C to +85°C operation Runs Linux, DOS, and other x86-compatible operating systems Downloadable drivers available Responsive and knowledgeable technical support Long-term product availability

The PCM-VDX-2 can be customized by depopulating certain features or adding soldered-down flash memory, CompactFlash card retention clip, and/or a Mini PCI video card. Understanding long-term product availability is a critical issue for our customers, the PCM-VDX-2 is offered beyond 2017. Contact us for additional product information and pricing. Our factory application engineers look forward to working with you.

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EDITORIAL Jonathan Miller, Diamond Systems

Evolution – It’s a Good Thing!


e all know that nature evolves to meet new challenges. Old life forms become extinct to make room for newer, better ones, and existing life forms evolve to become more efficient and better adapted to their environment. Why should it be any different in the small form factor computing industry? Let’s take a look at some of the recent evolutions in expansion buses and hypothesize what might come next. The PC/104 Consortium introduced PCIe/104 in an attempt to provide PCI Express as an expansion platform for small form factor stackable systems. Unfortunately, they made two key mistakes: (1) they abandoned the highly popular PC/104 ISA bus in favor of the far less important PCI-104 PCI bus, and (2) they focused the new connector exclusively on PCI Express (PCIe), dedicating twothirds of the connector to a x16 link, even though there is little or no requirement for PCIe x16 in small form factor systems. As a result, a small group splintered off to create a competing organization, the SFF-SIG, and its own standard, SUMIT. SUMIT retained the ISA bus instead of the PCI bus (good) and provided a variety of “low-speed” expansion options, including LPC (also good). Unfortunately, SUMIT also got it wrong, by adding every serial bus they could think of, even though some have little or no applicability to the small form factor market. This kitchen sink mentality resulted in the SUMIT connector being overloaded with features that no one wants, like ExpressCard and Microwire, while coming up short on the ones that people do want, like PCIe. Enter that all-correcting force: Evolution. The PC/104 Consortium recognized the shortcomings of PCIe/104 and created a new Type 2 specification. Type 2 adds LPC, USB and SATA to the connector, providing more options for I/O module designers. Type 2 is backward compatible with Type 1, so existing products will still work in new systems. The SUMIT group made a minor update to their specification too, assigning a function to a reserved pin. However, they declined to add a life-saving second PCIe link to connector A, which would have made the connector far more useful. Analysis of the two organizations’ websites indicates a far greater market acceptance of PCIe/104 than of SUMIT, based on the number of vendors and products listed. This lead is likely to expand as more vendors see the utility of the new PCIe/104 Type 2 pinout. But Evolution isn’t done yet. Both PCIe/104 and SUMIT are guilty of key sins in the small form factor market: excess size, excess cost, and (in the case of SUMIT) inferior connectivity. In small boards like PC/104, not only is every bit of PCB area precious, but the PCB edges are also critically important, since that’s where the I/O connectors go. The long connectors used in PC/104, PCI-104, PCIe/104 and SUMIT



each occupy almost an entire edge of the board. In a typical 2-connector configuration, up to half of the board’s “coastline” is consumed by bus connectors. This leads to undesirable consequences, like “wings,” which violate the form factor, or even worse, omitting valuable features. In addition, the cost of these connectors is an unwelcome burden. A PCIe/104 or SUMIT connector set costs as much as $20. Add just one I/O module, and that becomes $40. By the time it reaches the customer, that $40 easily becomes $80 or even $100. So much for the mantra “smaller, better, cheaper.” Finally, both PCIe/104 and SUMIT have only a few reserved pins available for future definition. We all (should have) learned a lesson from ETX. When SATA came out, there were no pins left on the ETX connectors, so ETX vendors had to put the SATA connector on the module, which took up space and required a cable. Unfortunately, both PCIe/104 and SUMIT retain only four reserved pins, leaving them exposed to potential obsolescence once the next bus is introduced. Many SBC vendors, having confronted the shortcomings of both PCIe/104 and SUMIT, appear to have thrown up their hands in despair and stayed away from both. For example, low-cost Asian manufacturers are almost completely absent from both standards. Customers suffer from the resulting limited choice and high prices. So an opportunity exists for Yet Another Small Form Factor Bus Connector, one that has the right combination of connectivity features that match processor chipsets and I/O chips yet has the smallest possible size while maintaining sufficient ruggedness with the lowest possible cost. At the same time it would minimize the consumption of PCB coastline and reserve sufficient pins for future functionality. The table below summarizes the features of SUMIT, PCIe/104 and a possible successor. Feature Pins PCIe x1


PCIe/104 Type 2






















Reserved pins




PCIe x4 / x8 / x16 USB2.0

PCB area

0.56 sq in

0.82 sq in

Under 0.4 sq in

Coastline consumed




Cost (1K units)



Under $10

Intel® Atom™ Processor N450/D510 and ICH8-M Chipset Up to 2GB DDR2 SDRAM PC/104-Plus Expansion Onboard 4GB SSD Single Channel 18-Bit LVDS and Analog VGA

CoreModule 745

Integrated graphics DirectX 9 controller at 200MHz

PCIe/104 and PCI-104

Xtreme/SBC PCI-104

Intel Atom, Freescale i.MX51, TI OMAP & NVIDIA Tegra On-board connectors for connection to: - SATA, USB, Ethernet - LVDS & VGA Video - RS-232 & RS-422/485

Xtreme/SBC PCIe-104

ATX Supply Input or +5V/+12V

DM&P SoC CPU Vortex86DX- 800MHz PC/104 standard compliant, PCI-104 & PCI/104+ (Optional) Watchdog Timer, software programmable (30.5 μsec. to 512 sec.) XGI Volari Z9s Chipset, onboard 32MB VGA Memory Integrated 10/100Mbps Ethernet


Up to 512MB DDR2 onboard

Intel® Core™ i7 Processor 8GB DDR3 ECC RAM maximum using rugged RSOMM modules Pictured with optional 8 independent, isolated serial ports Pictured with optional 8 port Ethernet Board Graphics, Audio, USB, SATA


The Embedded Products Source 1.800.548.2319

editor’s report Advances in Embedded Processor Architectures

New Embedded Generation Fuses x86 with Parallel Processing Engine The G Series Fusion architecture from AMD pushes the envelope for the processing power in a single device. The x86 instruction set is integrated with a parallel core that can deliver high-end graphics and video as well as general compute-intensive parallel processing. by Tom Williams, Editor-in-Chief


hat do embedded processor customers want? Customers want infinite performance, zero power consumption, all for the price of a penny or less. And semiconductor manufacturers are scrambling to accommodate them. We’re not there yet but the drive is unrelentingly in that direction. Perhaps paradoxically, embedded customers also want something else. They also want product lifetimes on the order of ten years, which means that once they have designed this close-to-ultimate processor into their products, they want to stay with it and its soon to be nolonger-ultimate performance/power/cost characteristics for a long time. The end-of-life conflict comes from the fact that the PC market, the main world market for processors, keeps moving up the performance curve every few months abandoning the older processors as it goes. So stretching out the end of life (EOL) requires a commitment to the embedded market on the part of the manufacturer that runs somewhat counter to the demands of the much larger PC market. Often this had consisted of stretching out the EOL of pro-



cessors made for the PC market but also popular for embedded applications. Advanced Micro Devices, which has been serving the embedded market as well as the PC and notebook market for a good many years, has recently come out with a new high-performance x86-based architecture that includes an advanced graphics processing unit (GPU) integrated into a single device. The integration enables the GPU to act together with the CPU as a single computing device as well as play the role of a graphics engine. This combination has been dubbed by AMD as the accelerated processing unit or APU (Figure 1). The AMD Embedded G Series platform is aimed at the embedded market and features a 413-pin ball grid array (BGA). A minimum of five years product life is guaranteed. AMD says that its manufacturing arrangements with foundries such as TSMC in Taiwan, make it possible to economically continue a product with what will eventually become a somewhat older processor for a longer time. AMD is calling its architecture the Fusion family of APUs because it consid-

ers the integration of CPU and GPU to constitute a truly heterogeneous processing device rather than a CPU with a tightly integrated peripheral. The APU consists of a multicore x86 architecture CPU coupled via a high-speed bus with a parallel GPU architecture that is not only capable of high-end graphics processing but also of high-speed parallel data processing. It consists of video and display elements along with parallel SIMD arrays. The way the GPU has been integrated has led to its description as a “discrete class GPU.” That means that rather than being an internal CPU element, it is connected via the high-speed bus like a discrete GPU, has direct access to memory like a discrete GPU, so it is both integrated and discrete, hence “discrete class.” This kind of integration also enables it to perform high-speed parallel processing tasks other than graphics such as array processing applications. It can also combine such parallel tasks with graphics and display tasks— with appropriate performance tradeoffs. In terms of the combination of parallel computing engines with an x86 processor, the AMD APU is reminiscent of the Compute Unified Device Architecture (CUDA) developed by Nvidia for graphics processing that has been combined on boards with x86 processors. In the case of AMD, of course, this idea had been carried to the integration of two such elements on a single die. This is important because the use of CUDA with x86 processors had given birth to a number of software solutions to exploit its potential. One of these is a framework called OpenCL that is designed to provide for writing programs that execute across heterogeneous platforms such as CPUs and GPUs. AMD supports OpenCL, which is managed by a non-profit consortium called the Khronos Group. OpenCL is included in the G Series development kit, which also includes OpenCL-compatible compilers. It should come as no surprise that the G Series is equipped with the latest integrated display interfaces on-chip. These include HDMI, dual-link or dual singlelink DVI, dual DisplayPort, LVDS and analog VGA. In addition, there is a x4 PCI Express port directly off the chip and an integrated DDR3 memory controller.

editor’s report

The GPU core architecture has direct access to memory via a ring bus memory controller and provides full support for DirectX 11 including full speed 32-bit floating point per component operations. Motion video acceleration is provided through dedicated hardware for H.264, VC-1 and MPEG2 decode. Additional I/O is provided by an I/O hub called the Hudson, which connects to the G Series processor via a unified media interface (UMI). The Hudson hub provides a SATA interface, LPC and SPI as well as high-definition audio, USB 2.0 and another four x1 PCIe lanes. AMD has at present no partners building specialized versions of the I/O hub for such vertical markets as automotive, nor is it clear if there is information available to configure FPGAs with specialized I/O to communicate over the UMI (Figure 2). AMD also offers a development board with either the T56N 1.6 GHz dual core or the T40N 1.0 GHz dual core processor and the A55E controller hub (Hudson). The board provides a variety of display interfaces. The availability of high-performance embedded processors with high-end 3D, high-resolution graphics is significantly extending the reach of what has traditionally been considered the realm of embedded systems. From industrial controls and headless devices of the past, we are witnessing the emergence of systems with compelling visual interfaces that are nonetheless dedicated in functions yet spreading more into what may be considered the “consumer” market. At the same time, what was once considered the consumer electronics market is no longer as well defined as it once was. There was a time when consumer electronics meant things like televisions, stereo and audio equipment for the home and even personal computers. Now we are seeing devices such as a restaurant or bar table whose top is an interactive touch-sensitive video display. One such system not only lets customers play games but presents the menu so that they can order food and drinks. If someone sets a glass down on the table, it senses that it is a glass. It is even able to determine if the glass is getting empty and can alert the customer to ask if he or she would like to order a refill. Designs like this in addition to the growing market for interactive digital signage, casino gaming machines

Multicore CPUs CPU General Program Task

General Program Task

Designed for: General-purpose tasks Most common applications Data processing serially


External GPU sub-systems

Serial Data Processing


Parallel Data Processing

• General-purpose, programmable scalar and vector processor cores, form heterogeneous capability • High-speed bus architecture • Shared, low-latency memory model




ATI Stream

Designed for: Specialized tasks (e.g. graphics, video) Most visual applications Data processing in parallel

• All on the same die

Figure 1 The accelerated processing unit (APU) is the result of the integration of a multicore x86 CPU with a parallel graphics processor that is also capable of single instruction multiple data (SIMD) parallel processing for general computing tasks. 2 DDR3 DIMMS

SIMD Engine

x86 processor High Performance Bus and Memory Controller

SIMD Engine Unified Video Decoder HDMI VGA dvi

x86 processor

Platform Interfaces



Figure 2




The integrated high-end video and graphics are available via interfaces directly from the processor die. Other I/O is carried by the I/O hub attached via the universal media interface.

of all sorts, point of sale and kiosk systems are all target applications of this enhanced class of embedded processor. Things that formerly were inanimate objects like bar tables are becoming intelligent interactive devices thanks to the computing and graphics power that is now being packed into this

generation of small, low-power and lowcost processing engines. Advanced Micro Devices Sunnyvale, CA. (408) 749-4000. [].



Technology in


Microcontrollers Go after the Details

Right Sizing the Micro: Honing in on the Right MCU for the Job Given the vast variety of microcontrollers in all bit widths, with almost infinite combinations of on-chip peripherals and features, a systematic approach can save many headaches when searching for the proper controller for a project. by Keith Curtis, Microchip Technology


hen starting an embedded control project, the first question that inevitably comes up is, “Which microcontroller should I use?” Should I go for a low-cost micro and migrate up, or start with a high-end micro and downsize? Do I need an 8-bit, 16-bit or 32-bit MCU? Unfortunately, the simple answer is, “It depends.” What level of control will the project need? What are the power limitations? Will it have to work in a harsh environment? What kind of processing power will be required? Does it interface with a human being, or other systems? How fast does it have to respond to changes? The list goes on and on, and if the engineer is not careful, a kind of paralysis can set in and hobble the project. The solution is to collect all the requirements together in one place and weigh the tradeoffs. Personally, I like to use a requirements document; basically, a one- to two-page document that clearly, and as completely as possible, outlines the basic requirements of the project. Typically, a good place to start is with the basic functionality of the project: 1. W  hat tasks will the system perform? 2. What are the system inputs and outputs? 3. How much data storage will be required? 4. How quickly must the system perform its tasks and respond to events?



Table 1 shows an example list for a simple thermostat control. Next, the document should include design constraints: 1. What are the materials and assembly cost targets? 2. What are the power requirements of the system? 3. What are the physical-size limitations of the system? 4. What is the target operating environment for the system? Table 2 shows an example list for the same simple thermostat control. When these requirements are clearly defined, we can start a preliminary list of resource requirements for the system: 1. Data memory; how much data ram is required? 165 bytes 2. Flash memory; how much program space is required? 2300 words 3. Peripherals; what on-chip peripherals are needed on the MCU, and what onchip peripherals would be nice to have? Must have a) LCD peripheral b) USART c) ADC



32-bit Software RTOS Multitasking Dynamic Power Calculation Advanced Machine

Hardware Real-Time Response Sleep Power Robust Electrical Signal Chain/Analog Real world

Figure 1 System Tradeoffs

Nice to Have a) Cap-touch peripheral b) Real-time clock peripheral 4. External circuitry; what other signalconditioning or control circuitry is required? a. Temperature sensor b. Watchdog timer c. Open collector drivers for heat/ cool d. Voltage regulator 5. Processing speed; how many MIPS are required to do the job? 500 KIPS to 1 MIPS Don’t worry about the absolute accuracy of these estimates at this point. This is an attempt to get a rough order of mag-

technology in context

Intelligent Home Thermostat Function list

Intelligent Home Thermostat Data storage

1. Heater control 2. AC control 3. Serial output to PC 4. Serial input from PC 5. LCD display driver 6. Capacitive-touch input 7. Temperature control 8. Command decoder 9. Real-time clock

System inputs/outputs

• 32 bytes: Serial transmit buffer • 32 bytes: Serial receive buffer • 20 bytes: Command parser • 10 bytes: Real-time clock • 20 bytes: LCD buffer • 6 bytes: Tone generator • 45 bytes: Temporary variables 165 bytes total


1. RS-232 serial input 2. Cap-touch sensor 4 3. Heat/cool switch 4. Temperature sensor 5. Heat/cool output drive 6. RS-232 output 7. Segmented LCD display 8. Piezo buzzer 9. Battery Voltage

• 2 kHz: Touch interface scan rate • 60 Hz: LCD update rate • 4 kHz: Tone generator • 5 Hz: Heat/cool drive • 1 Hz: Battery check • 1 kHz: Serial port character rate (6900 baud)

Cost Targets • Material cost <$4 • Mechanical cost <$2 • Assembly cost <10 System Power • Battery backup <20µA • Line power <5mA Physical Size • 3” x 4” x 1” Operating Environment • Temperature 0C to 30C operating -20C to 75C storage • Electrical noise 3V Common mode noise (no effect) 1 KV ESD (human body model) Cell phone 2’ proximity



Preliminary Project Requirements List

Project Design Constraints

nitude in order to have a numerical basis for the tradeoff analysis to follow. Figure 1 shows some of the tradeoff decisions that we will need to make in the design. Notice that Figure 1 shows a range of 8 through 32 bits. The idea is that each item listed is a continuum, ranging from one extreme to the other. It doesn’t mean that both extremes are not possible at either end; it just means that they are easier to implement. For example, real-time response is listed at the 8-bit end of the chart, while RTOS is listed at the 32-bit end. This doesn’t mean that there isn’t an RTOS solution available for 8-bit microcontrollers, just that RTOSs are more prevalent at the 16- and 32-bit end, and that their memory footprints are proportionally smaller in 16- and 32-bit microcontrollers.

Hardware versus Software

Let’s start with the first item on the list: hardware versus software. For the moment, let’s limit the question to digital peripherals; we will discuss analog peripherals below. The question is fairly far-

reaching in a design. Basically, will some or all of the needed functions be created in software, or will we use hardware? The tradeoff is processing power versus hardware complexity. For example, should a stepper motor controller be implemented in software, or with the use of a controller chip? The answer will affect processor speed requirements, program memory requirements, system cost, board size and possibly current consumption. There may also be hidden limitations. For example, it is certainly reasonable to build a USART function in software, as both transmit and receive functions can be emulated in software. The problem is, the receive function must continuously poll for the falling edge of the start bit, to accurately synchronize its receive timing. This can put a considerable drain on processing power. Even if an interrupt-on-change function is available, the latency time of the interrupt service routine may make accurate timing of the edge problematic. So be careful when trading hardware peripherals for their software-based alternatives, there may be lurk-

ing limitations. For now, just note the potential options and know the potential costs.

Real-Time Response versus RTOS

The next tradeoff concerns a similar decision for the software design of the project; real-time response or RTOS. Here, we have to make a decision about how we are going to multi-task in our design. Will we use a real-time operating system (RTOS), or will we build the system out of interleaved state machines? Both have advantages. The RTOS handles all of the switching between states and simplifies the software design, while a real-time response system requires a smaller memory footprint and makes real-time response control easier to implement. Both choices will have some impact on the data/programming memory requirements and, potentially, the processing power required for the system. Another potential complication may lurk in the type of RTOS to be used. RTOSs fall into two basic categories: preemptive and cooperative. Both allow switching between multiple tasks, but differ in the RTC MAGAZINE APRIL 2011


technology in context trigger for the switch. This results in differing requirements for variable storage and peripherals, which should be factored into the system requirements.

Sleep Power versus Dynamic Power Control

Another hardware decision concerns the system power requirements: sleep power or dynamic power control. Here the question is, will we go with a control that has all-or-nothing current consumption, or will we go with a more graduated system that selectively turns off sections of the design. Both have a place in designs, and the choice will be heavily affected by decisions made earlier in the hardware/software section. Basically, the question is, will some of the system be required to stay awake and drawing current in order to handle the system idle tasks, or will it be an automated hardware system that can handle simple tasks while the processor is asleep and drawing much less quiescent current?

Robust Electrical Design

A related question is the need for a robust electrical design. Now, while all designs

should be robust electrically, there can be a tradeoff concerning how that robustness is achieved. This question ties back to both the power and hardware/software questions. For example, let’s consider a power conversion function. One option is to select a more software-centric design, which uses a software function to generate the feedback control. The second option uses an opamp-based loop filter with a simpler analog feedback PWM. Both systems work, and both are currently in use in the industry. The differences are that the software-based system must remain active while the power converter is operating, which may require a higher operating current. And, in the event that the program counter in the microcontroller is corrupted, the hardware-based system is unaffected by the microcontroller recovery function, making it more electrically robust in a noisy environment.

Analog Signal Chain versus Calculation (DSP)

The fifth item gets back to the question of hardware versus software, but this time it has to do with using an analog signal chain versus calculation (i.e., a DSP). The tradeoff

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here concerns system controls. Will an analog signal chain be used to condition input signals and generate outputs, or will we use software? This question becomes more of a gray area than the aforementioned hardware versus software question. Here, the question has a much more profound effect on the microcontroller choice. To implement a proportional-integral-derivative (PID) function or a digital-filter design, the microcontroller really must have a couple of on-chip features. The first requirement is a hardware multiply function that is capable of keeping up with the system requirements for feedback and control. The second required feature is a high-speed, high-resolution analog-to-digital converter (ADC). Now, some simple feedback controls can be implemented using micros without these features, but they tend to be slow and they typically use up all of the available processing power to accomplish the task. The simpler option, in these cases, is to go with an analog system to accomplish the necessary functions, and relegate the microcontroller to a supervisory role. However, there are some functions that require greater speed, or are more difficult—even impossible—to implement in analog, such as non-linear feedback controls and infinite impulse response (IIR) filters. Here, the better (or only) option is to use a software solution, plus any necessary analog fault-detection circuitry.

Real World versus Advanced Machine

The final tradeoff is a question of usage. Is the system a small automated control system with only a limited user interface, or a more advanced system with networking and a more complex user interface? Clearly, we are not going to try to use a QVGA with a touch screen to implement a $9.99 home thermostat control. But, we might need such a user interface for a system that is networked into a large office building environmental control system. It is really a question of how much bandwidth is required for the user interface and whether any connectivity is required. There may also be requirements based upon the aesthetic “look and feel” trends in the marketplace, or even requirements for operation by a user wearing gloves. All of these requirements should be weighed to determine the appropriate complexity of the system.

[32,16] [32,16] [120,40] [40,10] [64,16] [48,12] [40,40] [20,5] [64,16] [48,12] [80,40] [80,40] [80,40] [20,5] [40,10] [40,10] [40,10] [32,16] [42,10] [32,16] [64,16]

XLP Yes Yes Yes XLP Yes

3 2

XLP Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes XLP

3 2 2 2 2 2 2 2 2 2 2 3 3

3 2 2

13 16 16 5 16 12 16 0 24 12 10 9 10 11 12 13 10 16 11 16 24

10 10 10 10 12 10 10

2 2 2 1 2 2 2

12 12 12 10 12 10 10 10 10 10 10 10 12

2 2 2 2 2 1 2 1 1 2 1 4 2

2 2 2 1 2 2 2 0 2 1 2 2 2 1 1 1 1 2 1 3 2

2 2 2 1 2 2 2 0 2 1 1 1 1 1 1 1 1 2 1 3 2


Yes Yes Yes Yes


Yes Yes

Yes Yes Yes Yes 10 B Yes Yes

5 5 5 4 11 5 6 1 11 4 7 7 7 3 4 4 4 5 5 5 11

5 5 4 2 10 5 5 0 10 2 4 4 4 3 2 2 2 5 5 18 10

5 5 4 2 10 5 5 0 10 2 4 4 4 3 2 2 2 5 5 9 10

PMP 0 PMP 0 GPIC 0 0 132 PMP 0 PMP 0 0 192 192 PMP 0 PMP 0 PMP 0 0 192 PSP 0 0 PMP 0 0 PMP 0 PSP 0


Supply Voltage

CPU Speed (MHz, MIPS)

8.00 8.00 4.00 0.75 3.70 3.80 8.00 0.06 3.70 3.80 8.00 4.00 4.00 0.36 0.75 1.50 1.50 8.00 3.70 16.0 3.80

Segment LCD


0 0 0 256 1024 0 0 64 1024 0 0 0 0 0 0 0 256 0 0 0 1024

Parallel Port

EEPROM (Bytes)

64 64 32 8 128 128 32 1.75 64 128 64 32 64 7 8 32 32 96 96 64 128

LIN CAN Total Timers Input Capture PWM Channels

Flash (KB)

3.07 3.07 3.07 3.08 3.08 3.09 3.09 3.11 3.11 3.12 3.12 3.12 3.12 3.13 3.15 3.18 3.18 3.19 3.19 3.20 3.21


5K $ Pricing

16 16 16 8 8 8 32 8 8 8 16 16 16 8 8 8 8 16 8 16 8



PIC24FJ64GB0 PIC24FJ64GA0 dsPIC33FJ32G PIC18F2331 PIC18F67K90 PIC18F87J50 PIC32MX320F0 PIC16F84A PIC18F86K90 PIC18F87J93 dsPIC33FJ64G dsPIC33FJ32M PIC24HJ64GP2 PIC16F737 PIC18F8390 PIC18F4510 PIC18F2520 PIC24FJ96GA0 PIC18F66J65 PIC24FJ64GA1 PIC18F87K22

LowPower Comparators ADC Channels ADC Bits Total UART SPI I2C

Product Family

technology in context

with Measurement Computing

2 to 3.6 2 to 3.6 3 to 3.6 2 to 5.5 1.8 to 5.5 2 to 3.6 2.3 to 3.6 2 to 6 1.8 to 5.5 2 to 3.6 3 to 3.6 3 to 3.6 3 to 3.6 2 to 5.5 2 to 5.5 2 to 5.5 2 to 5.5 2 to 3.6 2 to 3.6 2 to 3.6 1.6 to 5.5

Figure 2 Example Microcontroller Selection Matrix

OK, so we have made all the tradeoffs and adjusted our list of system resource requirements appropriately, now what? Well, this is where we get out the catalogs and start looking for an appropriate microcontroller. See Figure 2 for an example Microcontroller selection matrix. We have a good idea of the processing power required, the memory required (flash and RAM) and the peripheral mix required. Now, it is unlikely that we will find an exact match. More than likely, we will have to revisit some tradeoffs and make some hard choices. This is part of the reason we noted which peripherals were nice to have versus must have. The best approach here is try to find a microcontroller that is part of a family with upward and downward compatible siblings. This will provide options in the event that we have to either add or subtract memory and/or peripherals to add features or cut cost. There is a silicon and a test cost associated with each function, and the cost of each starts to add up. Some functions have more incremental costs than others. So, when the final product selection options are narrowed down, it’s good to refer back to the must have vs. nice to have lists. Also, consider the cost and complexity of the required design tools. These tools will be used not only by the design team, but also by the support, testing and production staff making the final product.

Another important design consideration is the availability of pre-built stacks and library functions. Some manufacturers make pre-built code available for specific functions, such as graphical display drivers, serial-communication functions and capacitive-touch functions. These standard blocks can save a considerable amount of time and testing, but the blocks must be examined to be sure they are compatible with the design. For example, some blocks may monopolize one or more peripherals, preventing other functions from accessing them. There may also be timing requirements that conflict with other functions in the system, so be sure to ask specific questions before committing to the use of prefab code. Most importantly, consider code reuse in the final decision. There is no reason to keep reinventing the wheel on every design. Find a manufacturer that produces a broad range of microcontrollers and stick with them. This will allow you to reuse a lot of what you develop in future designs, cutting development and testing time. Additionally, using a wide variety of manufacturers’ tools and parts can put a heavy burden on your test, support and production people.

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3/8/11 11:00:55 AM

ploration your goal k directly age, the source. ology, d products


connected Security for Networked Devices

Adding Extra Levels of Security for Connected Client Devices In order to form a secure platform, a combination of the latest hardware and software technologies is needed to protect our computer systems and networked devices from harm even if the network security has been compromised. by Robert Day, LynuxWorks


uch of today’s security focus is gently on new methods for attacking our on securing the network from systems, figuring out ingenious means for attack, as this has become a stealing or corrupting our sensitive inforstandard path for cyber crime and cyber mation. Some attacks, for example the rewarfare to infiltrate our computer sys- cent Stuxnet virus, are targeted on a partems. However, if malicious threats man- ticular type of device, and for a particular age to bypass the network security and reason. So, we are in desperate need for enter our systems, there is very little left new technologies to help us protect our to protect our sensitive data and applica- sensitive data even if our device is compromised by a malicious attack. tions from attack. In the enterprise world, virtualizaAs the enterprise attempts to move nies providing solutions now tion is often seen as a way of isolating everything to the “cloud,” offering greater ion into products, technologies and companies. Whether your goal is to research the latest and protecting applications and data held security and flexibility for applications ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you on PC clients and cloud servers. While and data, the actual world is struggling you require for whatever type of technology, adding a virtualized layer does help to a with the reality that much of the sensitive and products you are searching for. degree, many of these virtualization sysinformation both corporate and personal is tems still run on top of, or with the aid being carried around on our multitude of of, traditional desktop operating systems connected mobile, embedded and laptop that have a large and well known attack devices. The protection for this informasurface for malicious programs to exploit. tion has largely been reliant on protecting the network that we connect to (such as In fact, many viruses check to see if they with VPN connections) or assuming that are running in a virtualized environment the operating system that is being used on and change their behavior accordingly. In the device is not ripe for attack. The cyber embedded systems the use of traditional criminals, however, are working very dili- virtualization solutions is somewhat limited. In much the same way that regular hypervisors are not built for security, they Get Connected are also not built with real-time determinwith companies mentioned in this article. ism in mind either. An ideal solution to help protect our client devices would be a

End of Article


APRIL 2011 RTC MAGAZINE Get Connected with companies mentioned in this article.

real-time secure OS with a virtualization scheme built in. This technology exists today, and has been developed for and used in defense systems that require real-time performance, connectivity and, above all, security functionality that protects our very sensitive military information from real cyber attacks. The heart of this technology is a secure separation kernel. Rather like a safety-critical RTOS, the kernel provides a scheme that partitions applications and memory—hence the separation—but unlike safety kernels it has added security protection and definable security policies that enable developers to build a system that meets their exact security requirements. The separation kernel has become a fundamental platform for building secure systems to consolidate traditionally physically separate hardware onto a single platform. These systems will often be connected at different levels of security or to different networks that require secure isolation of the communication or data resident on the system. And therefore when these elements are combined onto a single physical environment, a secure separation system needs to be employed. These


ARINC 653 App


POSIX APEX Open-standards API


Linux App

Windows App App App API

Middleware Win32 API

App App

GLIBC Middleware Open-standards API



Virtual CSP/BSP/Drivers

Virtual CSP/BSP/Drivers

Virtual CSP/BSP/Drivers





CDS Guard


Open-standards API


Application Run-Time (ART)



Intersubject Communication HYPERVISOR

consolidated systems can be designed to a multiple independent levels of security (MILS) scheme with strict separation and secure communication policies that are enforced by the separation kernel. This technology gets really interesting and also applicable to the enterprise space when a hypervisor or software virtualization solution is combined with the separation kernel. With this virtualization technology each secure enclave provided by the separation kernel can actually contain a virtualized environment that allows multiple different virtualized “guest” operating systems to reside on a single physical system while still maintaining security for each by virtue of the separation kernel. Because the hypervisor is combined with the separation kernel, it is running directly on the hardware. This is often known as a type 1 hypervisor, which gives significant performance benefits compared to a more traditional “hosted” type 2 hypervisor that requires and runs on a desktop OS like Windows. This technology could radically change the way developers build and configure both embedded and enterprise systems by allowing the segregation of both applications and operating systems on a single system based on the real-time requirements, the desired user environment and the security needs of different elements of the system. No longer will the compromise of trying to make a desktop OS real-time, or a real-time OS a full GUI-based system be the developers headache. They can simply use a RTOS in one partition for the real-time element and a desktop OS in another partition for the user interface. This greatly simplifies the software architecture of the system, and allows for a more diversified development team with different skills to be used on the project. Figure 1 shows the architecture of the LynxSecure separation kernel and hypervisor, which is a good example of a military-grade secure virtualization solution.


technology connected

LynxSecure Separation Kernel and Embedded Hypervisor Exceptions and Interrupts

Device I/O, Memory Management


Figure 1 Example separation kernel architecture diagram showing multiple secure partitions running and RTOS, two desktop OSs and small bare hypervisor partitions for smaller applications. PARTITION 0
















Figure 2 Example of how devices may be directly allocated to secure partitions, or shared between partitions using the secure device server resident in its own partition.

A very key benefit of this new approach is the secure separation of the elements and data held in the system. The secure partitioning system helps protect connected devices from attack, even if malicious code has breached the network security, as it limits the attack to the partition where the malicious code entered the system, and the security within the separation kernel does not give the at-

tacker any visibility or access to the other parts of the system. Using a separation kernel allows not only the configuration of the guest operating systems and their applications, but also the configuration of the physical devices available in the system and the communication policies between the different partitions, allowing for different configurations on the same hardware platform based on the RTC MAGAZINE APRIL 2011


technology connected

user requirements and defined by the system developers. To understand how this configuration is applied, the function of the separation kernel needs to be explored first, then the virtualization schemes offered by the hypervisor component, and finally how both of these are linked with the underlying hardware platform. The separation kernel is a small, efficient real-time operating system that


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manages both the physical devices and the memory on the system. It offers partitioning and isolation of the memory regions and devices based on a configuration scheme that is put together by the system architect. This same configuration also contains the information about how the different partitions can communicate with one another, allowing two-way, one-way or no-way directional flows. All of the configuration information is held

3/8/11 3:01:50 PM

within the separation kernel image, so it is not accessible or hackable from the outside world. The separation kernel itself has limited operating system functionality for programmers, which keeps the kernel small and certifiable when used in security systems. Much of the high level OS functionality is provided by the guest operating systems that reside on top of the separation kernel, provided by the hypervisor. This means that the desired functionality of the OS is selectable per partition, by choosing the most appropriate guest OS for that part of the system. The hypervisor provides a virtualization interface for the guest OS to run on, with two different virtualization schemes available for the guests to use. Paravirtualization is a scheme where the hypervisor and the specific guest OS are tightly coupled together. Less virtualization support is required from the hypervisor as the guest operating system is modified to make direct calls to the hypervisor. This approach has traditionally offered better performance for the guest OSs as less virtualization code is required to run. The source code of the guest OS needs to be changed and an understanding of the hypervisor functions is required to apply this type of virtualization. The other virtualization approach is full virtualization, where the guest operating system requires no modification as the hypervisor presents a virtualized environment that looks identical to the native hardware that the guest would normally run on. This approach requires more virtualization code in the hypervisor, which has traditionally resulted in a performance degradation when compared to paravirtualization, but has the advantage of no modifications needed in the guest. This second approach is particularly useful if the source code to the guest OSs is not available for change, and requires little understanding of the hypervisor APIs as the guest just runs as if it was running on a native system. For both virtualization schemes applications that run on the guest OS require no modification, as they are using the normal API of the guest, and hence provide a very effective way of moving legacy applications to hardware platforms, maximizing reuse and shortening porting time dramatically.

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Another key component of the separation kernel/hypervisor approach is in the pairing of devices to partitions and guest operating systems. A traditional type 2 hypervisor will typically virtualize all devices in the system, offering a flexible, but often performance limited, environment for guests to use, especially for performance devices like graphics or network functions. The separation kernel approach can offer two schemes for device allocation, the first being direct device assignment. This approach allocates and assigns a specific physical device to a specific guest OS, allowing OSs and applications that require the best performance or the highest security to have full and total control of a physical resource. The second approach is to allocate a physical device to a server partition, and then offer shared virtual devices to other guest operating systems. This approach is particularly useful when physical resources are limited, especially true in embedded and mobile client devices and laptops. Figure 2 shows an example of how devices may be directly assigned and/or shared on the same physical system. Because the separation kernel and hypervisor are software approaches, there is often a concern that running an OS on top of a kernel or just using virtualization is too much of an overhead for use in real-time, embedded or mobile devices. However, many of the hardware processors have helped to reduce that overhead dramatically by introducing hardware virtualization technologies and processors with multiple cores. The hardware virtualization technologies help assist the memory, device and execution virtualization required by the hypervisor, allowing much of the software virtualization and guest OS switching to be directed to the hardware, increasing performance dramatically. Because of the increased use of virtualization in server and PC client systems, the Intel processor architecture has been innovating with many new hardware features such as Intel virtualization technology (VT) and extended page tables (EPT) that significantly increase guest OS performance. Taking advantage of these hardware technologies has brought the performance of both paravirtualized and fully virtualized guest OSs to within a

few percentage points of their native performance on the same hardware. The security of the separation kernel with the functionality of a hypervisor is providing a platform that developers can use to run embedded and enterprise systems on a single hardware platform, and protect the sensitive information and data from attack by partitioning resources in their own secure enclaves. This approach is performant enough that even with the

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increased security protection, the users will not notice application degradation and legacy software systems can be ported to new secure environments with having to rewrite a lot of code. LynuxWorks San Jose, CA. (408) 979-3900. [].


9:23:49 AM RTC MAGAZINE 4/12/11 APRIL 2011

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Developing with Programmable Logic



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Utilizing a Flexible Interconnect Architecture for System Design Network on Chip interconnect architectures provide a number of significant advantages over traditional interconnects, as the transaction and transport protocol layers are kept separate, allowing for independent design and optimization. by Aaron Ferrucci, Altera


PGAs are becoming larger and larger, and mounting pressures are being placed on design teams to implement more complex systems with increasing performance requirements in less time. System-level design tools are undoubtedly the most important component of a system designerâ&#x20AC;&#x2122;s toolbox, tools with the ultimate goal of designing high-performance systems with a minimum amount of effort. Some of these tools provide network-on-chip-based interconnects as a highperformance alternative to traditional buses. Network-on-chip (NoC) interconnects provide significant advantages over traditional interconnect implementations, based primarily on a clear separation between how different layers of the protocol stack can be provided. This separation of layers allows independent implementation and optimization, and allows system designers to take advantage of innovation at different layers of the network stack without invalidating working designs. Additionally, networks scale well to support systems of increasing size. This article presents the Qsys network-on-chip architecture. This NoC is designed to support high-performance operation on FPGAs, including a flexible interconnect architecture that implements only the minimum required functionality for a given application, a packet format that varies depending on properties of the system being supported, and a network topology that separates command and response networks for higher concurrency and lower resource cost. Performance comparisons are presented between this NoC interconnect and a traditional interconnect. The results show that the network-on-chip implementation provides higher performance with similar latency characteristics, and can provide up to two times the operating frequency when pipelining is enabled.


An NoC implementation of a transaction interconnect is different from traditional interconnects in one simple, yet powerful way. Instead of treating the interconnect as a monolithic system sub-component, an NoC approach treats the interconnect as a protocol stack where different layers implement different functions of the interconnect. As with more traditional protocol stacks, such as TCP/over IP/over Ethernet, the power RTC MAGAZINE APRIL 2011


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Transaction Interfaces

Transport Interfaces

Transaction Interfaces

Master Interface

Master Network Interface

Network Switch (Command)

Slave Network Interface

Slave Interface

Master Interface

Master Network Interface

Network Switch (Response)

Slave Network Interface

Slave Interface

Figure 1 Network-on-chip topology Legend Connections avalon-MM avalon-ST Components user s_1

response FIFO fabric m_0

master translator

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master translator

master agent

addr router

addr router

traffic limiter

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slave translator id router

rsp demux

rsp mux

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Figure 2 Two-master, two-slave system with NoC interconnect components.

in the network model comes from the information that exists at each layer when encapsulated by the layer below. Figure 1 shows the basic topology of a network-on-chip. Each processing node interface in the network, master or slave, is connected to a network interface component, which is responsible for capturing transactions and responses using the transaction layer protocol, and delivering them to the network for transport as packets of the appropriate format. The transport network delivers packets to the appropriate transport layer endpoints, which pass them to other network interfaces, where the packet is terminated and delivers the command or response to the transaction endpoint using the transaction layer protocol. In Figure 1, an application layer component such as a processor communicates with its application layer peer, (i.e. a memory controller). Although these application layer components logically communicate



with one another, they do so by relying on a transaction layer. Each of these application layer components uses the services of the transaction layer to communicate with one another, via a transaction interface, such as Avalon-MM or AXI. The network interfaces provide transaction layer services by communicating with their peers at the transaction layer in the other network interfaces. The transaction layer components provide these services with the use of the transport layer. Each component at the transport layer interprets the transport layer protocol. Decoupling the different layers of the protocol stack has a number of benefits over a traditional monolithic approach.

Benefits of Network-on-Chip Architecture

A common approach to complex engineering challenges is to divide the design problem into smaller problems with

well-defined interactions. With a networkon-chip interconnect, the design problem ceases to exist. How then is a flexible interconnect for a complex system designed? It is rather several simpler, independent problems that need to be solved, such as whatâ&#x20AC;&#x2122;s the best method for mapping transactions into packets or how to transport packets in the best way. If layers are kept separate, itâ&#x20AC;&#x2122;s also possible to individually optimize the implementation of each layer. For example, the transport layer team can experiment with a number of network topologies and implementations without changing anything at the transaction layer. At the transport layer, all commands and responses are simply packets carried by the network, and the network layer only needs to support the transport of these packets. That makes customizing the interconnect for a given application much easier than for a monolithic interconnect. For example, if it is determined that pipelining or clock-crossing is required between a set of masters and slaves, then these components can be inserted freely, as long as they faithfully transport packets. The influence of the pipelining and clock-crossing functions on transactions of different types, for example command vs. response, burst vs. single access, etc. can be disregarded. The interconnect can use different optimizations and topologies in different parts of a network. Imagine a design with a set of high-frequency, high-throughput components (processors, PCI Express interfaces, DMA controllers and memory) as well as a set of low-throughput peripherals (timers, UARTs, flash memory interfaces, I2C interfaces, SPI interfaces, etc.). A common network interface component can be used for all of these components, but the system can be divided at the transport layer, with high-performance components on a wide data width, highfrequency crossbar network, while the low-throughput peripherals use a less expensive mesh network with only a packet bridge between them. As technology changes, interconnects need to support new features, such as new transaction types or burst modes. With a layered interconnect, new features can be implemented via changes to the layer that

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supports the particular feature. For example, to support new burst modes, only the network interface components have to be changed. Likewise, if a new network topology, a new network switch, or a new transport technology is found to yield higher performance, it can be substituted for the original network without redesigning the entire system. IP cores intended for on-chip applications are available with different interface types, including AMBA AXI, AHB and APB interfaces, OCP interfaces, Wishbone interfaces and Avalon-MM interfaces. Once the interconnect has been implemented for a given interface type, the work to support a new interface consists of implementing the network interface to encapsulate transactions to or from interfaces of that type using the selected packet format. Systems with hundreds of masters and slaves are not uncommon, and traditional interconnects struggle to keep up. Interconnects designed for dozens of masters and slaves are difficult to scale up to support the hundreds of components required in today’s systems. In a network-on-chip implementation, it’s relatively easy to divide the network into subnetworks, with bridges, pipeline stages and clock-crossing logic placed throughout the network as required. A multi-hop network could support thousands of nodes, and could provide for a transport network spanning multiple FPGAs, or even geographically separated device nodes.

Network-on-Chip Architecture Optimized for FPGAs

The Qsys NoC architecture has features that are particularly well suited to FPGAs and the systems implemented in FPGAs. The Qsys NoC supports a wide variety of systems, including large high-performance systems with multi-gigabit data paths and complex bursting, as well as small systems composed of only a few components. To support such a wide variety of systems, this NoC tailors itself to the performance requirements of a given application. Qsys NoC generation begins by dividing the system into one or more “interconnect domains.” An interconnect domain is the set of all interfaces that have direct or indirect connections between them.

addr router m_0

master translator

master agent

traffic limiter

Figure 3 Detail of master network interface components.

Each interconnect domain is configured to support full throughput for the highest throughput connection in the system. This is done by examining all of the interfaces and connections in the domain. Once the interconnect domains have been identified, each interconnect domain is implemented by instantiating and connecting only those interconnect components that are required. For example, if there is a master in the system that is connected to only one slave, certain interconnect components (those implementing routing and in-order response guarantees) can be omitted. If a slave is connected by only one master, other components (those implementing arbitration) can be omitted. If a certain type of burst adaptation is not required by that application, then support is omitted from the interconnect. In addition to minimizing the components used by the interconnect, the Qsys NoC generation optimizes the systemspecific packet format to minimize logic use and adaptation. For example, the address and burstcount fields in the packet are the minimum width required to support the system components. A large data field width can be used for low latency, high throughput connections; alternately, a narrow data field width can be used to conserve resources, when high throughput is not required. Commonly, the notion of a “packet” is associated with “serialization.” Many network-on-chip implementations break up wide-data transaction into multiple narrow-data transactions, executed over multiple cycles in the transport layer. This approach increases the latency of transactions, which rules it out in many applications, such as communication between a microcontroller and its local memory. The sub-components of this NoC have been designed with combinational data paths, and the packet format is designed to contain a complete transaction in a single

cmd demux

cmd mux

cmd demux

cmd mux

Figure 4 Command network components.

clock cycle. This results in the interconnect supporting writes in a single cycle, and reads with a round-trip latency of 1 cycle. On the other hand, the system designer is able to set pipelining options to increase system frequency at the expense of latency. The Qsys NoC uses two independent networks, one for command transactions and one for response transactions, instead of a single network that supports both. This increases concurrency, since command and response traffic do not compete for resources. This choice also allows the two networks to be optimized independently, according to system topology and throughput requirements.

Interconnect Components

This section describes the functional blocks in a typical instance of a Qsys NoC. An example of a system that would contain this typical interconnect is a twomaster, two-slave system, with full connection between masters and slaves. Figure 2 shows a block diagram of an implementation of the two-master, two-slave system, including “user” components (original system components) in gray, and inserted interconnect components in green. As a framework for explaining the function of each component in the system, RTC MAGAZINE APRIL 2011


Tech In Systems

slave translator


readdata FIFO

slave agent

response FIFO

id router

Figure 5 Slave network interface components.

consider, in sequence, the events that occur when a master issues a read transaction to a slave. 1) The originating master issues a read transaction to a particular slave address. 2) The master translator component (Figure 3) receives the read transaction, and translates the signaling of that read transaction to a common


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format for the given transaction protocol. 3) T  he master agent converts the read transaction into a packet, and forwards it onward. The master agent supplies a network-domain-unique source ID in the packet, to be used for response routing. The master agent also receives response packets and translates their contents into the

transaction protocol response format. 4) The command router translates application-layer addressing information into packet network routing information, which consists of a) a network-domain-unique destination ID and b) a channel value used for local routing. 5) The traffic limiter component keeps track of all pending responses for a particular master, and prevents commands from being issued if they could result in out-of-order or coincident read responses. 6) Next, the packet is transmitted into the network switch (Figure 4). The Qsys network switch is a crossbar network that supports maximum concurrency, allowing all masters and slaves to communicate on any given clock cycle. The command demultiplexer (â&#x20AC;&#x153;cmd demuxâ&#x20AC;?) uses the local routing channel to pass the packet toward the correct slave. 7) The command multiplexer chooses which of its command inputs to accept and which to backpressure ac-

4/6/11 8:55:09 AM

tech in systems

cording to an arbitration algorithm. Because the command multiplexer receives the entire packet, it has the freedom to implement complex arbitration algorithms which take any aspect of the transaction into account. The command multiplexer forwards the packet that has won arbitration onward into the slave agent. 8) The read transaction packet arrives at the slave agent component (Figure 5), which terminates the packet and forwards the transaction contained within the packet to the slave translator. At the same time (for command packets that elicit a response), the slave agent captures the source ID field of the packet and stores it in a response FIFO. 9) The slave translator converts from the common transaction protocol format into the particular set of signals and signaling functions required by the slave interface. When the slave responds to the read transaction, the response returns to the slave translator, where it is once again converted into the common transaction protocol format and passed back to the slave agent. 10) The slave agent translates the response into a packet and forwards it to the response router (â&#x20AC;&#x153;id routerâ&#x20AC;?). 11) The response router translates the packet destination ID (the original masterâ&#x20AC;&#x2122;s network-domain-unique ID) to the channel value used for local routing. 12) The response packet is routed through the response network switch in a similar manner to the routing of the command packet, and back to the master network Interface. 13) The master agent translates the response packet into the common transaction interface protocol. 14)The master translator converts the arriving response data into the form required by the particular master.

as needed. The NoC generation also adds pipelining stages when required, to help with timing closure, as well as handshaking or dual-clock FIFO components to accomplish transaction propagation across clock domain boundaries. The Qsys design tool includes a flexible FPGA-optimized NoC implementation, which is generated based on the requirements of the application that the system design has captured. The inter-

connect can provide the same frequency of operation for the same latency and resource characteristics, and can provide up to two times the operating frequency as pipeline stages are added to the interconnect network. Altera San Jose, CA. (408) 544-7000. [].

In addition to the components described above, the Qsys NoC generation will add burst and width adapters as needed. These components inspect particular fields of their incoming packets, and create outgoing packets with fields adapted Untitled-4 1


4/8/11 1:46:44 PM RTC MAGAZINE APRIL 2011

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Developing with Programmable Logic

Programming ASP-Type Devices: New Approaches for a New Paradigm The application services platform (ASP) represents a new path for development of embedded systems. As this class of devices proliferates in the market, new approaches to development tools and methodologies will have to evolve with them. by Greg Brown, Xilinx



Processing System Static Memory Controller NOR, NAND, SRAM, QSPI

I/O Unit

2x SPI 2x I2C 2x CAN 2x UART GPIO 2x SDIO with DMA 2x USB with DMA 2x GigE with DMA

Dynamic Memory Controller DDR2, DDR3, LPDDR2


Programmable Logic:

ARM CoreSight Multi-core and Trace NEON /FPU Engines

NEON /FPU Engines

Cortex-A9 MPCore 32/32 KB I/D Caches

Cortex-A9 MPCore 32/32 KB I/D Caches


Snoop Control Unit (SCU)

512 KB L2 Cache CTRL Sys Ctrl Reg





System Gates, DSP, RAM


On-Chip Memory

AXI Interconnect

SysMon/ADC MultiStandards IOs (3.3V & High Speed 1.8V)

MultiStandards IOs (3.3V & High Speed 1.8V)


n application services platform or ASP, a name coined by RTC editorin-chief Tom Williams, is a new class of IC that combines a CPU, a standard set of configurable peripherals and a programmable fabric—all on a single device. Because they combine logic programming with software programming, these new devices offer design teams the maximum flexibility, enabling users to rapidly develop unique functionality for whatever application they are targeting. At the same time, the combination of hardware and software on one device raises many questions regarding the usage model. Luckily, the advent of the ASP does not mean that the software programming model, processes and tools have to change. When designed to use industry standards, ASPs can provide a programming model identical to that of fixed devices. Let’s examine a practical ASP flow that leverages industry standards and standard software flows. To set the stage, Figure 1 displays the block diagram for the Xilinx Zynq7000 EPP, an ASP device built around a dual ARM MPU core and development

PCIe Multi Gigabit Transceivers

Figure 1 Xilinx Zynq-7000 Extensible Processing Platform Block Diagram

architecture with functionality that can expand by making use of the device’s programmable logic resources. The device is implemented in 28-nanometer silicon

process technology to hit the targeted power/performance/cost points. Unlike previous processor-equipped FPGAs that required designers to program the FPGA

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Hardware Flow

Software Flow Customize Boot Code

Libraries (programming, drivers, middleware)

Boot code, Configuration and Memory Map Information

Configure Processing System

Develop Drivers for Custom IP

Develop Custom IP

Create BSP

Integrate Standard IP

Create Boot Image

Simulate, Synthesize, Place and Route

Develop Applications

Create Programmable Logic Programming File


Mergeboot, BSP, PL Programming images (if required) Create FLASH file

Figure 2 Conceptual Design Flow Diagram.

logic blocks before they could even activate the onboard processor, the new device uses a processor-first approach in which the processor runs the show and boots from startup. This particular ASP has an application processor that provides a dual, ARM CortexA9 MPCore with NEON SIMD and floating-point engines. Each core has 32 Kbytes of separate I and D caches as well as a unified 512 Kbyte Level 2 cache. The CPU cores can function in asymmetrical (AMP) or symmetric (SMP) multiprocessing mode, or even as a single CPU with the other processor gated off for power savings. An integrated DRAM controller supports DDR3, DDR2 or LPDDR2, while a set of flash controllers handles boot and configuration storage. The device also includes several peripherals. The processing system has its own set of I/Os with dedicated pins for DRAM and a muxed I/O for the peripherals and flash devices. Unlike an ASSP, design teams can use the ASP’s programmable logic I/O to fully pin-out the peripheral set if that is what the end application requires. The processing system—and indeed the entire device—is built around the ARM AMBA interface standard with a high-speed, crossbar-switch-style interconnect. Xilinx memory-mapped the registers, especially those for the integrated peripherals, and linked the entire processing system to the programmable logic using the AXI set of interfaces, which support control, data and memory.

Additionally, the device has an accelerator coherency port (ACP) to enable design teams to add cache-coherent accelerators to their system if required. To be a viable solution, an ASP must address the following programming challenges: • Programming model • Configuration of the processing system • Configuration of the programmable logic • Boot • Libraries to access unique hardware and system-level functions • Power management • Board support package (BSP) development • Operating system (OS) support • Debug support • Software development tools

Programming and Configuration

First and foremost, ASPs must have an easy-to-use and robust programming model. In the present case, the programming model is based on ARM’s well-established CPU instruction set. Thus, the same types of memory-mapped calls that are made to resources in the processing system are identical for the applicationspecific extended functionality that is added to the programmable logic. This is very important because for software to effectively use the extensions, the extensions must use a known and consistent set of interfaces. This also helps design teams

create sets of functions they can implement in software, in hardware or both. They can even create a library of software functions and hardware IP functions that share a common programming interface. Because these devices and their functions are built to common standards, thirdparty vendors can also create generalpurpose and application-specific software functions and hardware IP, benefiting the entire marketplace. To be a viable ASP, the device must have highly flexible CPU cores. Asymmetrical multiprocessing should support the use of different runtime environments on the different cores, either unsupervised or supervised, using hypervisors. SMP support, especially using OSs, provides an overall boost in processing performance and can remove much of the complexity of multicore design for application development. An ASP should also support single-core usage for applications that do not need or cannot take advantage of multiple CPUs. By supporting divergent use of the CPUs, the spectrum of single core and multiple core (AMP, SMP) can be delivered on a single platform, enabling application-specific use of the processing architecture. ASPs should also allow users to configure the functionality of the processing system itself. These devices will let designers set the type of DDR they want the device to use, along with peripherals and associated muxed I/O as well as the width of the interfaces between the memory controller and the programmable logic. Users can also access a smaller subset during runtime to change, for example, arbitration or priority on the memory controller to adapt to specific traffic patterns. To simplify making all these settings, ASP vendors must provide a configuration tool that outputs configuration documentation for use in hardware and software development. These tools must also create human-readable data files that the downstream tools will use directly, be hand-edited, or used for driving script-based build environments. Figure 2 shows a simplified flow diagram to illustrate this concept. Above and beyond being able to program the ASP’s processing system, an ASP device, by definition, allows users to offload functions to programmable logic. RTC MAGAZINE APRIL 2011



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Libraries & APIs Custom

OS Kernel High Level and Low Level Drivers

Processing System


Safety-critical and Redundant CompactPCI® and VMEbus

Reference Design & Board

… … … … … … … … …

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Programmable Logic

SW Development Tools


HW Development Tools

Figure 3 More than just ASP Device, A Comprehensive Platform.

Certifiable up to SIL 4 or DAL-A with safe operating system N Safe and reliable through triple redundancy N Simple software integration through lockstep architecture N Voter implemented as IP core in safe FPGA N Conductive-cooling options for harsh environments N Meets environmental standards DO-160 and EN 50155 N Developed according to DO-254 and EN 50129 N Guaranteed quality based on ISO 9001, EN 9100 and IRIS MEN delivers redundant computers on board and system level (COTS or customized) for safetycritical control systems for railway, avionics and industrial.

To make the system accessible to a wider variety of users (software developers as well as hardware engineers), configuration of the programmable logic should be under the control of the processing system. Ideally, the processing system should not require the programmable logic to be configured at boot time. Rather, it should be a choice the design team makes based on the needs of their targeted application. This enables the processing system to load a configuration based on parameters determined after boot. An ASP should also support dynamic partial reconfiguration, a technology analogous to dynamically loading and unloading software modules. The processing system can reconfigure a portion of the programmable logic to load in, for example, a new set of algorithmic parameters or even an entire new function needed at a particular time. Further, the configuration information for the programmable logic should support encryption and authentication to protect the IP. This is important not only for custom IP, but for IP purchased from third parties.

Basic System Management

ASPs should feature a multistage boot function that allows users to tailor boot-up for their specific applications. Users should also be able to select a boot device via mode pins or another mechanism. A boot ROM should support secure and nonsecure modes, including decryption

MEN Micro, Inc. 24 North Main Street Ambler, PA 19002 Tel: 215.542.9575 E-mail:


3/14/11 9:55:04 AM

and authentication. After the boot ROM, user-defined boot should make it possible to load additional boot images from not only the flash devices but any appropriate peripheral, such as Ethernet, USB or SD. Configuration of the programmable logic should be a parallel process that can be started during this stage as well. Fallback to a known-good image for both the processing system boot and the programmable logic image provides a recovery mechanism in case an image is corrupted, for example, during a remote field update. For an ASP, such operations involve not only software updates but hardware updates as well. For implementations that require it, the capability to combine the two images is very important. A tool that merges these images into a single flash image enables ease of flash programming and reduces the number of data files required in product data management. Any unique hardware or system-level functions should have an application programming interface. APIs simplify programming by providing a defined set of software functions that access available hardware and system resources. An example here is the dynamic configuration of the programmable logic. A set of API functions should exist to make such capability readily available to the software application to use. Similarly, ASPs should include fea-

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tures that allow users to manage their device’s or even system’s power usage. Further, they should be able to accomplish this by making tradeoffs in the processing system and the programmable logic. This can cover capabilities such as shutting down the programmable logic, slowing down the clocks or putting the processing system itself in sleep mode and waking on a LAN or CAN signal.

Development Support

ASP devices help narrow the board support package (BSP) development gap between fixed devices and completely programmable devices, such as soft processors in FPGAs. With fixed devices, OS vendors can provide a BSP that supports all the device’s features. Users can tailor these features for a specific implementation using that device. With a completely soft solution, vendors provide fixed BSPs only for reference, since almost every implementation uses a different set of peripherals and other capabilities. Thus a vast majority of these require custom BSPs. The design industry has tried to develop dynamic BSP generation technologies to help with this task, but the use of vendorproprietary ISAs has limited the adoption of this technology. With ASP devices, vendors can provide fixed BSPs that support the entire processing system. Since the programming model is consistent between the processing system and programmable logic, BSP development for the custom portion can leverage device driver libraries for a wider set of interface standardized IP. Design groups, device vendors or third-party IP vendors can develop libraries of soft IP with drivers that users can add, in turn, to a BSP. ASPs must support industry-standard OSs. In fact, the ARM architectures enjoy what is arguably the widest support among RTOS and OS vendors as well as suppliers of open-source operating systems such as Linux. Therefore, the availability of kernel ports is not usually an issue. Rather, the work generally centers around the availability of a BSP. As previously discussed, the ASP devices can be supported much like fixed devices with the libraries available to support the extensions into the programmable logic.

As complexity has increased and more functionality is being integrated into devices, more and more development time is often spent in the debug cycles. Therefore, a viable ASP must include a robust debug infrastructure. This infrastructure needs to provide more control and visibility into the internal workings of the devices. ARM provides such an infrastructure using the CoreSight debug and trace IP. On-chip trace using a few kilo-

bytes of memory is important, especially for field failure analysis, where the trace pins for off-chip collection are not available. Trace pins should be available as an option so that users can recover valuable pin resources once the product is in production. For multicore designs, CoreSight enables visibility into program execution and is OS-aware. The CoreSight standard enables tool support for JTAG and trace so that tools from multiple vendors can


Signal Processing HW IP & FrameWorks Development Tools Systems & Services

7MQTPMJ]*4+%-RXIKVEXMSRERH-QTPIQIRXEXMSR [MXL&MXX;EVI«W%80%28M7*VEQI;SVO Implementing complex signal processing on FPGAs? No need to spend most of your design effort on infrastructure and integration. BittWare’s ATLANTiS FrameWork provides a simpler, more efficient approach: s Follows a software-like FPGA development methodology s Provides flexible components, reconfigurable at build time and/or run-time s Allows straight-forward integration of components s Enables design portability and code re-use among different Altera FPGAs and BittWare boards Lower your development costs and decrease your time-to-market with BittWare, the essential building blocks for your innovative solutions.

Implemented in Altera® Stratix® family FPGAs



4/6/11 8:57:13 AM RTC MAGAZINE APRIL 2011

Tech In Systems

support a wide variety of ARM-based devices from multiple vendors. An embedded logic-analyzer capability that can trigger and capture events and data provides visibility into the programmable logic. Signals between the CoreSight IP and the programmable logic should exist, enabling cross-triggering between the two domains. Breakpoints set in the software debugger should trigger the capture of the embedded logic ana-

lyzer, while trigger points set in the logic analyzer can stop the debugger. This onchip cross-trigger keeps the debugger and logic analyzer in closer synchronization, and the data capture is much easier to correlate. Users can also create custom debug IP and add it to the programmable logic to increase control, visibility and capture. The software development tools for ASPs must leverage tools that software developers already use, from command-





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Available 3U VPX Cards


Xilinx San Jose, CA. (408) 559-7778. [].



line tools to integrated development environments. Since OS support for the ARM architectures is widely available, tool support is also widely available from the OS vendors and others. Open-source options such as GNU are well supported and available. The critical component for the software tools is having the information on how the processing system is configured, the memory map, the functions residing in the programmable logic and the boot parameters. The configuration tool should provide this information for the software development tool in a human-readable and editable format to fit into the specific build environment the software development team is using. The ASP devices that are now coming onto the marketplace present an exciting platform to address a variety of product development and employment challenges. These devices are hybrids in that they provide a fixed but extensible development capability. But when properly designed to use available standards, they can leverage what already exists while simultaneously opening up new application spaces and opportunities. The entire platform, especially programming, must be well thought through and addressed so as to enable a broad number of users to readily adapt the technology to build a variety of powerful and innovative products. A comprehensive platform must be the goal, as illustrated in Figure 3. This was the approach taken for the newly announced Xilinx Zynq-7000 Extensible Processing Platform. (510) 252-0870 ÂŞ5IFNJT$PNQVUFS "MMSJHIUTSFTFSWFE5IFNJT $PNQVUFS 5IFNJTBOEUIF 5IFNJTMPHPBSFUSBEFNBSLT PSSFHJTUFSFEUSBEFNBSLTPG 5IFNJT$PNQVUFS"MMPUIFS USBEFNBSLTBSFUIFQSPQFSUZ PGUIFJSSFTQFDUJWFPXOFST

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Developing with Programmable Logic

Portable and Reusable FPGA Frameworks Let Engineers Do What They Do Best – Design Reusing design elements should not require the redesign of those elements themselves. The use of a framework with well defined layers of abstraction and interfaces can go a long way toward relieving the need to reinvent the wheel. by Jeffry Milrod and Kristen Zaffini, BittWare


he definition of a design engineer, per Wikipedia, is one who “works with a team of engineers and designers to develop the preliminary design and the most critical parts.” In today’s FPGA-centric world, for most design engineers the development of “critical parts” is becoming an ever shrinking piece of their total effort. One major reason for this is that it is often difficult or impossible to reuse previously developed critical parts, requiring that they be redeveloped and revalidated with every new generation or feature. Moving to the next generation of an FPGA project, or updating an existing project typically requires rewriting interfaces, modifying timing constraints, reintegration and rebuilding of simulations of existing critical parts— the dreaded reinventing of the wheel. This work of reinventing the wheel can add up to days, weeks, or months with little or no time left for adding real value with the creation of new critical parts. If only we could hop in a time machine and go back to the days when design engineers spent the majority of their time developing the systems of the future rather than rebuilding and tweaking the systems of the past. What if tomorrow’s FPGA design could be built better and quicker, with time left over to add in features that wouldn’t even have been attempted if the design engineers had



Board Level (BoardLevel.vhd)

Physical Level (PhysicalLevel.vhd) Hierarchical Mapping

User Level (UserLevelvhd) Hierarchical Mapping

FPGA Boundary Figure 1 Hierarchical abstraction levels.

to spend their time writing yet another variant of their UART? When building the next FPGA project, the key to harnessing tomorrow’s cutting-edge technology today is to use a COTS FPGA framework that provides portable, reconfigurable and reusable FPGA components. A COTS FPGA framework can be like the iconic DeLorean DMC-12 from the movie, speeding up the design process to 88 mph so that the design engineer is transported back in time to find that the FPGA is already stocked with a fully validated project including data planes, control planes and physical interfaces for all board-level I/O communications and external memory. In addition to a wealth of proven, validated components that can be quickly

dropped in to a project, a COTS FPGA framework can have several other attributes that facilitate FPGA design portability and reuse. Hierarchical layers of abstractions support rapid changes of hardware at the board and/or FPGA level. Common interfaces create a building block approach to connecting components, thus enabling quick and easy component additions or replacements. Parameterized component reconfiguration allows designers to easily modify a given component without having to reintegrate or rebuild simulations. Finally, dynamic reconfiguration allows control software to modify the operation of FPGA components without needing to recode them.

tech in systems

Hierarchical Layers of Abstraction

Hardware flexibility is accomplished by using abstraction levels. As shown in Figure 1, each abstraction level can be thought of as a puzzle piece, with the ability to remove and replace each puzzle piece with another abstraction level. The board level is the lowest level of abstraction and is responsible for the interface between the FPGA physical signal interfaces (i.e. pins) and the ports on the FPGA device. The tool’s board-level definition file only needs to be created once per FPGA/board pair and can be shared across all projects that use that product; a COTS framework would provide this level for a supported board. The physical level contains all the physical interface components required to provide project support, converting data and control between the board level and user level. Finally, the user level contains the “meat” of the project such as the processing. This is where the real valueadded of the project resides, and where the designers should be spending their time. The designer is able to quickly move the project user level between boards and/ or FPGAs by simply swapping out one board-level definition file with another that contains the resources that a given physical level is using. From the perspective of the user level, it does not matter where it is getting its control or data from, nor where it is sending the processed data and status, so long as its input and outputs communicate using the common interfaces. As a result, it is possible to port the user level to different physical levels and thus, to different boards or FPGAs in a seamless manner.

Common Interfaces

Virtually every FPGA component requires some combination of: data in, data out and a control plane interface. By standardizing these interfaces—memory mapped for addressable transactions like control and status, and streaming for highspeed point to point transfers—components

Avalon Memory Mapped Interface

Register Bank Avalon Streaming Data Sink



Figure 2 Atlantis FrameWork component featuring common Interfaces

can be modular and interchangeable. One such standard is Altera’s Avalon Streaming and Avalon Memory-mapped interfaces, which are used by BittWare’s Atlantis FrameWork, as shown in Figure 2. Consider a design that uses an existing high-speed serial fabric endpoint between a SerDes physical interface and an internal DMA controller, but the new system spec requires a different fabric protocol. The framework greatly simplifies changing the protocol. Without a common interface, the design engineer would have to build adapters, gaskets, and interface translators each time they connected two different components together, then begin reintegration and validation. Using a common interface allows the developer to pull out one endpoint, drop the new one in and simply connect it back up to the existing SerDes PHY and DMA controller. Connecting the new endpoint’s standard memory-mapped registers to the control plane will then open up the dynamic reconfiguration options discussed later.

Parameterized Component Reconfiguration

Using high-level language parameterizations, the specific configuration

of a given framework component can be readily changed. Changing these parameters can reconfigure the component’s functionality, data widths, numbers of ports, speed, size, formats, etc. Scripts with included timing constraints can then be used to synthesize and simulate the reconfigured component. Since it is still basically the same component with the same interfaces but with just a different configuration, it is easily integrated into the project and project-level simulations. As an example of how powerful this can be, imagine a design that uses a data switch that has more ports than are required in a new project. The well designed framework component allows changing the number of ports by simply changing the component’s parameters. Using the parameterized component reconfiguration provided, the developer avoids having to waste resources for unused switch ports or having to write a new switch with fewer ports. Similarly, if a DMA controller was expecting 64-bit streaming data input while a new data receiver would be pumping out 128 bits, the developer could simply change the data width parameter on the DMA input receiver to 128. RTC MAGAZINE APRIL 2011


Tech In Systems

Dynamic Reconfiguration: Cut Down on Testing and Validation Time

Dynamic reconfiguration allows the developer to make changes to a component without having to change parameters and resynthesize via the components control registers; these are â&#x20AC;&#x153;on-the-fly,â&#x20AC;? or dynamic, types of changes. Even if a component supported dynamic reconfiguration, without a framework with a standard control plane and supporting drivers and software, it would be the developerâ&#x20AC;&#x2122;s responsibility to create an interface to control these dynamic reconfiguration settings. Some examples of changes that could be dyamically reconfigured are base addresses, DMA pointers and mux settings. A more complex application of dynamic reconfiguration could be applied to the new fabric endpoint discussed previously. Alteraâ&#x20AC;&#x2122;s FPGAs, such as the Stratix family, have SerDes transceiver configuration settings that can be reconfigured dynamically. These settings include voltage output differential (VOD), pre-emphasis, equalizer control and equalizer

gain. Since these are each an on-the-fly change, all that is required is writing to the reconfig register via the framework. So if during real-world system testing it is discovered that a given serdes fatpipe isnâ&#x20AC;&#x2122;t as clean as was expected and the bit error rate is higher than the spec allows, rather than spending weeks or months optimizing the analog controls, it can be dynamically reconfigured in milliseconds and reevaluated. Note that a more fundamental change, such as SerDes speed, might not be dynamically reconfigurable via run-time software but could be changed â&#x20AC;&#x153;staticallyâ&#x20AC;? via parameterized component reconfiguration and resynthesis. The nature of most designs is evolutionaryâ&#x20AC;&#x201D;adding value to existing designs via optimizations and new features. Hardware designers and software designers have gotten quite proficient at reuse of existing design elements to support this evolutionary style of development. Complex FPGA project-level design is a much younger discipline, and is still playing catch-up with hardware and software regarding design reuse. Depending on the

project, FPGA designers can spend more time reinventing wheels than actually developing real value-added and critical parts; itâ&#x20AC;&#x2122;s probably a toss-up as to whether that frustrates the project managers or designers more. FPGA Frameworks, such as BittWareâ&#x20AC;&#x2122;s Atlantis FrameWork (AFW), facilitate FPGA design reuse and portability by providing hierarchical layers of abstraction with components featuring common interfaces and reconfigurable capabilities, leading to more efficient development, less design maintenance, and more opportunity for inventing new critical parts. Using such tools, designers can go back to the days when their energy was focused on creating the systems of the future, rather than having to constantly hack up projects from the past. Start revving up the DeLorean, weâ&#x20AC;&#x2122;re goingâ&#x20AC;Ś Back to the Future. BittWare Concord, NH. (603) 226-0404. [].

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technology deployed Control for Advanced Energy Systems

Advanced Controls Enable Airborne Wind Power Generation Complex control challenges that a few years ago seemed impossible, have now become manageable thanks to improvements in processing power, FPGA technology and software control, making innovative wind power generation possible. by Brian MacCleery, National Instruments


ust a few thousand feet above our heads blows a vast untapped resource that could supply civilization with ample quantities of cheap, clean and abundant energy. No leaps of science are required to tap into it and no unsolvable technical hurdles prevent it from becoming a practical and reliable source of electricity. This resource has a terrific “energy payback ratio,” meaning the amount of energy required to build and maintain it is much less than the total energy produced during the system’s lifespan. Additionally, it has an impressive “capacity factor,” as its average power production is higher and more stable than other renewables. This could someday tap into the highest “power density” source of renewable energy on the planet. Finally, it has great “land use intensity,” meaning the amount of power produced per acre of real estate is excellent. It could be installed profitably almost anywhere in North America, even close to large population centers, and produce terawatts of clean energy, which is orders of magnitude less expensive than that from fossil fuels. Ultimately, you could extract enough power to supply the entire world’s energy demand without negatively impacting the climate. So why haven’t you heard of it before? The answer lies with the initial complexity, cost and Moore’s Law. Just ten years ago, the necessary processing, instrumentation, sensors and control software were prohibitively expensive and complex to design. Today, exponential increases in computing power, advanced instrumentation technology and high level software development tools, tightly integrated with COTS reconfigurable embedded systems, make it possible for the pioneers of



this new industry to build prototypes by the dozen and shorten time between designs. The world needs a clean energy hero as we all have a stake in the outcome, and the urgency is palpable. If necessity is the mother of invention, this child may break the “cost barrier” and reach the tipping point where natural market forces take over and drive adoption at hyperbolic rates. Please welcome to the stage a new contender that may have what it takes to carve out a healthy slice of the $6 trillion dollar clean energy technology (ET) market— airborne wind. This is not your father’s wind turbine. It has no blades. It has wings. No massive steel tower. It has a tether cable. There’s no human pilot aboard this experimental aircraft. Even Chuck Yeager could not survive the G forces.

How Does It Work?

Airborne wind borrows many established technologies from the conventional wind energy industry. The main feature that differentiates airborne turbines is the way they extract energy from the wind. Instead of a large steel tower structure, a tether cable anchors the system to the ground. Rather than rotating blades, specially designed airfoils sweep a path across the sky. This ability to sweep through a larger cross section of the wind is one of its fundamental attractions—facilitating a modestly sized airfoil to extract large amounts of energy from the stronger, more consistent wind higher up. Like the tip of a conventional turbine blade, the airfoil flies crosswind in a circle or

Figure 1 Ground-based turbine (left) compared to airborne turbine (right). (courtesy of KITEnergy.)

Technology deployed

figure 8 pattern at many times the speed of the wind, as shown in Figure 1. With a wingspan comparable in length to a wind turbine blade, an airborne turbine can sweep a larger region of the sky to harness nearly ten times more energy. Mechanically, airborne turbines benefit from being cushioned in a pillow of air during flight rather than rigidly connected to the ground. However, the G-force loads caused by their fast moving patterns can put significant stress on airfoil structures and tether lines. Flying one to two thousand feet above our heads, airborne wind is on track to become a cost-effective, practical and utility-scale-ready segment of the wind industry within the decade. Bringing utility-scale airborne wind to market at those altitudes Figure 2 doesn’t require any breakthroughs—just solid engineering work, A screenshot of the NI LabView graphical programming R&D investment and the support and guidance of the experisoftware used by Windlift to control their 12 kW mobile enced aerospace and wind engineering communities. power generation system. (courtesy of Windlift) At least thirty startups and research groups around the world are busy at work to make airborne wind a reality. Over the phase 1: Traction years, their prototypes have proven the basic principles of airborne wind and grown into the tens of kilowatts. The next step for the industry leaders is to prove their systems phase 2: Recovery can scale up to megawatt production levels and perform reliably during long-term continuous operation in the field. If airborne Z wind makes it off the ground, it just might change the world. Y “Would airborne wind have been costX effective ten years ago?” comments Joby KSU Wind Energy Business Development Director, direction Archan Padmanabhan. “No. It’s definitely advances in technology that make it costFigure 3 effective today—from inexpensive aircraft KITEnergy uses a design with the generator and kite steering unit (KSU) materials, to low cost GPS sensors, autonlocated on the ground. The 40 kW experimental prototype has been tested omous flight software and the increasing with tether lengths up to 3,000 ft. (courtesy of KITEnergy) power of embedded computing. The biggest technical hurdle that has been overcome is researchers in airborne wind are testing numerous design options in the area of control systems. Thanks to the aerospace indus- to determine what works best. Even with computer models, there try, flight control systems have become a lot more robust than are no substitutes for physical prototypes, which help convince any time before. Commercial airlines today are primarily flown skeptics and attract investors. on autopilot and people trust those systems—no one expects airplanes to come crashing down. The aircraft industry has a lot to From Prototype to Production with CompactRIO Windlift, a North Carolina-based airborne wind startup, is offer and we are learning from it.” Harnessing high altitude wind is a bold vision that brings developing mobile airborne wind turbines that have attracted inwith it a wide range of technical and logistical challenges—from terest from the U.S. military because their high power density finding tether lines that are strong and light enough to gaining makes them a future replacement for diesel generators and the Federal Aviation Administration (FAA) approval and airspace vulnerable fuel convoys that must supply them. Windlift uses clearance. Even at two thousand feet altitudes, FAA permitting National Instruments LabView graphical programming language questions need to be resolved. At least for now, making high alti- and NI CompactRIO ruggedized embedded instrumentation systude (tropospheric) wind commercially viable is likely to remain tems for control and dynamic monitoring, as shown in the interface for their 12 kW prototype system in Figure 2. elusive. Windlift chose to use National Instruments LabView softSimilar to the early days of the ground-based wind industry, RTC MAGAZINE APRIL 2011


technology deployed

ON BOARD Inertial station Transmitter & GPS




Pilot in the Loop Ground Station GPS receiver

Ground Station On board sensors measures - Current sensors - Force sensors - Motor Power

Figure 4 The NI PXI ground control unit computer wirelessly acquires onboard sensor signals and executes advanced control algorithms.

Figure 5 The SwissKitePower airborne wind control system involves multiple networked computers on the ground and in the air.

ware and CompactRIO hardware for several reasons including their FPGA processing performance and flexibility. Ultimately, they chose it because “National Instruments illustrated a clear development pathway with the CompactRIO from prototype to production with the same hardware and software.” For the controller, Windlift uses the embedded computer that runs LabView Real-Time and LabView FPGA. Within the system, the microprocessor and FPGA work hand in hand to share tasks. Seven I/O modules are included in the system, each providing the front-end conditioning for the type of signals needed to interface, including digital I/O, RTD temperature sensors, load cells and CAN fieldbus communication. These modules interface directly with the FPGA, which can perform high-speed signal processing and/or pass the signals through to the real-time microprocessor. Windlift’s system uses a three-line airfoil as the prime mover for their reel in/reel out system. A single tether attaches to the leading edge of the wing and carries most of the load. Two steering tethers attach to the trailing edge and are used to steer the wing and control its angle of attack. To steer, the system sends commands to two servo motors based on inputs from a human


pilot on the ground using a “fly by wire” interface. “The direction we’re heading is to make that flight control fully automated,” explains control design engineer Matt Bennett.


The prototype consists of two linear slides driven by a servo motor for steering, and an AC induction motor/generator, similar to what might be used in a hybrid bus. Each servo has its own internal controller, which receives position commands. For the tension control, the system adjusts the torque settings on the generator. CompactRIO uses proximity sensors to measure the rotation of the drum and calculate how much tether remains on the drum; the pilot only needs to steer the kite, while CompactRIO manages all of the power generation functions, including detecting the end of tether and retracting the wing. Windlift plans to add inertial measurement sensors and telemetry systems to automate steering of the wing and enable unattended operation. With two prototype systems that are working proofs of concept, Windlift estimates the next system will be productionready. They are developing a 12 kW system and hope to start on the design in Q2 of 2011. To put this in perspective, an equivalent conventional wind tower would measure 65’ tall with a 75,000 lb reinforced foundation. Windlift expects to offer a more affordable option compared to a conventional turbine in this size class, even with the cost of their built-in energy storage system. Ground-based generator systems, like those being developed by Windlift in the U.S., KITEnergy in Italy and SwissKitePower in Switzerland, produce power when the airfoil pulls a tether line. The torque and velocity of the tether cable produces electricity by spinning a generator which is attached to a rotating winch drum. As illustrated in Figure 3, there are two distinct modes of operation—the traction phase and the recovery phase. In the traction phase, the airfoil slowly pulls the tether line and electricity is produced until the maximum tether length or altitude is reached. Then the recovery phase begins; the airfoil is flown back while the tether cable is winched in. Recovery actually uses a small amount of power as the generator becomes a motor drive to retract the cable. Then the process repeats. For steering, the airfoil wirelessly transmits GPS coordinates and roll, pitch and yaw information from an inertial measurement unit (IMU) in the air to a kite steering unit (KSU) on the ground. KITEnergy uses the National Instruments PXI platform as the ground control unit, as shown in Figure 4, which acquires and processes the sensor signals and executes advanced control algorithms to command the winch motor/generator and steer the kite. “Theoretical, numerical and experimental results so far indicate that KITEnergy technology could provide large quantities of renewable energy, available practically everywhere, at lower cost than fossil energy,” comments Mario Milanese, KITEnergy founder. Shown in Figure 5, SwissKitePower also uses LabView in the networked computers for their airborne wind systems in addition to a ground-based generator approach. Other companies, such as Joby Energy and Makani Power, are pursuing airborne generator designs. In this case, a number of small, propeller driven generators located on the aircraft are used

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Technology deployed

for power generation and power is sent down the tether cable to the ground. Airborne generator systems are typically more like an aircraft and less like a kite—featuring an onboard computerized autopilot system and flight control surfaces to control roll, pitch and yaw like elevators and ailerons. A great deal of engineering effort at airborne wind companies is focused on perfecting these flight control systems and making them robust to withstand any sort of problem from gusting winds to actuator and sensor failures. The Makani Power system is being designed so it can even disconnect from the tether and land autonomously if needed. Not surprisingly, for such a budding child in the wind industry, the dust has yet to settle on which design choices prove to be the most practical and cost-effective. Airborne wind has a way to go before becoming a mature technology, but one thing is for sure—it’s an exciting time. Each new prototype that takes flight helps to convince skeptics and investors alike that “above ground wind power” isn’t such a crazy idea. Consider lending your talents to help airborne wind get off the ground.

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Safety-Critical Software

Safe Software: Things to Consider When Building Products That Can Cause Injury Software that can check its own behavior and that of the underlying hardware is essential to ensure the correct operation of safety-critical devices—in situations where it is often better to shut the system down rather than proceed with incorrect data. by Ken Maxwell, Blue Water Embedded


For the purpose of example we fair number of developers in will reference a hypothetical medical the embedded software industry instrument that displays some sort of are now building products that critical patient data during a surgical are considered to be moderate or high procedure. We can generalize these level of concern devices. This termiissues and apply them to many realnology means that if the product does world devices in all manner of safetynot function per specification, it may critical industries. What types of failcause injury to the patient, the user, or ures are we most concerned about in to the passengers in systems ranging terms of the user interface? A short from medical instrumentation, indusnies providing solutions now list might include the following failtrial controls, or airborne instrumenion into products, technologies and companies. Whether your goal is to research the latest ure modes, in order of severity: tation respectively. ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you 1) The UI is displaying incorrect Processes for designing and imyou require for whatever type of technology, data. software for fault-tolerant, and productsplementing you are searching for. 2)  The UI is displaying correct mission-critical devices are not somebut old data. thing most developers learned much 3)  The UI allows invalid or uninabout during their college years. They tended user input. therefore learn from their peers and from experience. Even in the area of Note that “The UI is displaying the user interface (UI), its software no data” is not included as one of the and related development tools, there are things that can go wrong and there critical failure modes. While this fault are ways of mitigating those potential might not meet the listed requirements of the product, the case of a missionfailures. critical device displaying no data at all is infinitely better than it displayGet Connected ing the wrong data. The reason for this with companies mentioned in this article. is that an instrument displaying no

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formation at all is unlikely to cause a surgeon or doctor to injure the patient. If the instrument has obviously malfunctioned the surgeon will generally proceed with caution. However, if the screen is displaying what appears to be valid data, but that data is actually incorrect, this can cause the surgeon to take action that injures the patient. This is the worst-case scenario that we want to avoid. Therefore we will focus on methods to prevent incorrect data display, and leave crashes and more obvious software faults for another day. The first two items above could be considered duplicates, since old data and incorrect data might be one and the same. However, the causes and mitigations for these failures differ, so they are listed separately.

Runtime Self Test

The fundamental idea is to have software that will continuously monitor itself to ensure everything is operating correctly, to the best of our ability to determine correctness. We will



Delay (ms) No Is Real-Time Data Being Displayed?


Run-Self Test Logic

Self-Test Passed?


Force Blank Display

Figure 1 Self-test task checks to see that valid real-time data is being displayed. If not, forcing a blank display will alert the user that the instrument is not functioning properly.

identify specific variables to monitor, time periods, and events that should occur within those time periods as part of our fault tree analysis. Once we have identified potential faults, we will design a task that performs selftests at specific intervals anytime the UI stack indicates that it is displaying critical real-time data (Figure 1). The task continuously executes these tests to ensure that everything is in order. When the tests are run and everything is found to be as it should be, the selftest task resets a hardware watchdog timer. If the self-test task finds a problem, it takes appropriate action to prevent invalid data display. If the self-test task fails to run at the desired interval (due to some other system failure), the hardware watchdog forces a system reset as our failsafe. This self-test configuration ensures not only that our tested variables are as they should be, but that tasking

itself is working and the low-lever OS timer interrupt facility is operating. If either of these has failed our self-test task will not execute and the watchdog reset will be triggered. Of course the watchdog timer itself must be failsafe. On recent devices, this hardware subsystem can only be enabled by a write-once register, cannot be disabled once enabled, and can only be reset with a sequence of data writes of specific values to multiple hardware registers. This is the type of secure hardware watchdog facility you may want to look for when identifying a CPU for your next safety-critical device.

Which Variables to Monitor?

Now that the architecture of our self-test task is in place, what things should we specifically be looking for in the UI operation? Letâ&#x20AC;&#x2122;s look at how pixels are actually turned on and off on a typical display and trace this back to determine that we are displaying recent, accurate information. First in line is the LCD driver. This hardware shifts color data from some memory buffer to the actual glass, typically updating the entire pixel array at roughly 60 - 70 Hz. Where does this data come from? In the case of an internal LCD controller subsystem like that present on many CPUs, a hardware register exists that specifies the physical memory address of the pixel data. This becomes our first self-test: Does the hardware frame buffer address register coincide with our UI softwareâ&#x20AC;&#x2122;s internal frame buffer pointer? We simply have to ensure that the data the UI software is writing into memory is actually being shifted out to the display, and there is no way around this. It does no good for the UI to furiously update critical data by drawing into one memory buffer while the hardware is busily updating the glass from a completely different memory location. This may not be a trivial test depending on your operating system, MMU configuration and other complicating factors such as double-buffering. This is one case

where in my opinion simpler is better. With some operating systems there are many layers of abstraction between the high-level UI drawing canvas and the low-level hardware frame buffer. It is better to have direct access to the UI buffer pointer(s) and hardware registers in order to easily verify that the hardware and software are working together. In inexpensive devices, we have also seen a trend to use displays that incorporate their own internal graphics driver IC. I believe this makes the task of verifying that the display is indeed displaying what we intended a bit more complicated. There must be a link between the CPU and the external controller, and this link might be in the form of a parallel or even a serial SPI type interface. If the link between the CPU and this external driver is severed, the external driver will continue to refresh the display with old data. This is exactly the situation we want to avoid, so when using this type of hardware architecture it is critical that we can continuously verify the correct operation of the communications link between the CPU and external display driver.

Timing Requirements

Now that we have verified that the pixel data is getting to the glass, what next? Most systems like this will have some timing requirements that specify the minimum update rate of the display. Showing the surgeon accurate heart rate data that is 20 minutes old is again a dangerous failure. Therefore, the UI software will need to set a flag each time the critical data is updated, and our self-test task will test and clear this flag during each execution of the monitor. If the UI software fails to signal that it has performed a display update, the self-test task immediately blanks the display or shuts down the system. Of course determining that the system is meeting the specified timing requirements can also get complicated as there are generally several steps in the pipeline with the UI pixel output pump just being the final piece of the RTC RTCMAGAZINE MAGAZINEMONTH APRIL 2011



Touch Input Driver Input Events stacked in event queue

Purge all Input Events


UI Software Stack

Is Screen in Transition?


Deliver input event to application

Figure 2 This task checks to see if the display is in transition before letting new input change the display. Input events are queued and only placed when the screen is idle.


Untitled-13 1


puzzle. Where is the data coming from and how old is it before it even arrives at the UI software stack for display? Since there are many possible causes for missing the timing requirements, there are also several mitigations. In this case there may not be a software failure at all, but instead a failure of a sensor that is causing the delay. For those cases it might be logical for the UI to indicate the sensor failure rather than shutting down the system. The important point to take from this is that the self-task is constantly monitoring the UI stack to ensure that we are not allowing the display of old data.

Protecting Against Invalid Input

We have so far examined two critical variables to monitor on the UI output side of the equation: the frame buffer address and the display refresh timing. There are of course many other potential critical variables and this

3/31/11 4:26:15 PM


will vary from one design to the next. We are simply starting down a path; how far you need to travel down this path depends on what level of concern your device might be. There are other potential failures in the UI software that expose themselves on the input side. By this I mean that our system might commonly allow some sort of user or operator input via a keypad, mouse, or touch screen, and we have to ensure that unintended inputs are rejected. As one specific example, the UI software should not allow the user to press buttons when the buttons themselves are in transition. “In transition” refers to some sort of screen animation or screen change that is not instantaneous. We all generally like eye candy and engaging display animations, and they make our products fun to use and sometime even convey information in ways that a static screen cannot. However, unless we are writing a game, allowing the user to click on buttons or change settings when the screen has not stabilized is a recipe for disaster. This failure can often manifest itself with a poorly debounced touch screen. The input driver might queue up several touch input events in rapid succession, and the UI software might sequentially process these events causing screens to change and buttons to toggle with serious unintended results. It is surprising how many UI stacks allow exactly this sort of failure. Granted intentional set up tests can be devised to try and cause this to happen, but the majority of UI stacks tested exhibit exactly the type of failure described. When building a phone or a game, allowing the user to click on a button as it’s sliding across the screen or fading out might be a desired operation. For a safety-critical device, we don’t want the user chasing buttons around or accidentally doubleclicking on the Start button. The easiest mitigation for this type of failure is to lock out all user input while the UI is in transition

(Figure 2). This might be done by preventing certain event types from being pushed into the UI event queue unless the UI is sitting in idle mode. Further, any existing input events should be purged from the event queue whenever a screen transition occurs to prevent the sequential processing of bouncy input.

Untitled-5 1

Blue Water Embedded Fort Gratiot, MI. (810) 987-3002. [].


4:47:07 PM RTC MAGAZINE 2/17/09 APRIL 2011

products &

TECHNOLOGY AdvancedMC Card with Second Generation Core Microarchitecture

A new AdvancedMC (AMC) high-performance processor board benefits from the recently introduced 2nd generation Intel Core processors. The AM 31x/x0x AMC single board computer from Concurrent Technologies features the 2nd Generation Intel Core microarchitecture, with the choice of the Intel Core i7-2715QE processor, Intel Core-i7 2655LE processor, Intel Core i7-2610UE processor or the Intel Core i5-2515E processor. The AM 31x/x0x also incorporates the Intel Series 6 Express chipset, and up to 8 Gbytes of DDR3-1333 ECC SDRAM, all within a single-width AMC form factor. The AMC.0/.1/.2/.3-compliant SBC offers eight PCI Express lanes (AMC.1 Type 8), configurable as 2 x (x4) or 8 x (x1) ports, and supporting Gen 1 or Gen 2 data rates. There are two 1000Base-BX channels (AMC.2 Type E2) as well as 4 x SATA (AMC.3 Type S2) interfaces. Bootable Flash memory can be supported via an optional onboard SATA Flash module. The front panel features a Gigabit Ethernet port, a DisplayPort interface, additional RS232 port and USB 2.0 port. The AM 31x/x0x features a dedicated microcontroller providing the Intelligent Platform Management Interface (IPMI) for PICMG system management features. This Module Management Controller (MMC) provides an administrator with the ability to monitor, manage, diagnose and recover systems. The AM 31x/x0x also supports full hot-swap capabilities for monitoring and controlling of the board. The AM 31x/x0x is available in single width, mid and full height formats and also available in two temperature grades: 0°C to +55°C (N-Series), and -25°C to +70°C (E-Series). Operating systems currently supported are Windows 7, Windows XP, Windows Embedded Standard 7, Linux and VxWorks. Concurrent Technologies, Woburn, MA. (781) 933-5900. [].

3U CompactPCI Serial Unmanaged 4+1-Port Ethernet Switch

A new CompactPCI Serial Ethernet switch extends the offerings of CompactPCI Serial boards for building a complete system based on the new specification. The 3U CompactPCI Serial Ethernet Switch G301 from Men Micro is equipped with four Gigabit Ethernet ports via RJ45 or M12 connectors in order to comply with the fast serial PICMG standard. Optionally, a fifth Gigabit Ethernet port can be made accessible at the rear via the J6 connector. The integrated self-test mechanisms help assure high reliability in communication systems and the board supports full and half duplex, fast non-blocking store-and-forward switching and autonegotiation as well as Layer-2 switching. The G301 is faulttolerant and restores itself automatically: If a link is temporarily unavailable, it will work again after the disturbance without any restart or reset. The board supports Power-over-Ethernet (PoE) with Power Sourcing Equipment (PSE) for up to 4 external devices with a total power consumption of 28W. Using a configuration EEPROM, the G301 can be exactly tailored to each application’s requirements (fixed management configuration). This includes features such as 802.1p priority and port-based priority, port-based VLAN or VLAN-IDs according to IEEE 802.1q. The Ethernet switch has especially been developed for mobile communication in harsh environments and is certified for operation in the extended temperature range according to railway standard EN 50155. All components are soldered to withstand shock and vibration and are prepared for conformal coating. MEN Micro, Ambler, PA. (215) 542-9575. [].



One Terabyte of Solid State Storage in Single 3U VPX Slot

One terabyte of solid state storage in a single 3U VPX slot is the boast of the newly available conduction- or air-cooled 3U VPX XPort6172 Solid State Disk (SSD) from Extreme Engineering Solutions. The basic module provides up to 512 Gbyte, or a half terabyte, of solid state storage with data encryption. However, 1 Tbyte in a single 3U VPX slot is achievable by mounting the XPort6103 512 Gbyte XMC SSD onto the XMC site of the XPort6172. The XPort6172 and XPort6103, individually or combined, satisfy the rigors of MIL-STD-810F and -461E—they are ready for the harshest deployments. The XPort6172 supports 256-bit AES encryption, utilizing the 123 NIST- and CSEcertified Enova Technology X-Wall MX-256C encryption chip. Additionally, the XPort6172 supports “zeroization” (i.e., enhanced erase) and satisfies DoD NISPOM 5220.22 and NSA/ CSS 9-12 specifications. Features include a x4 PCIe interface on the VPX P1 backplane connector, an XMC connector with a x4 PCIe interface (for XMC or XPort6103 use) and up to 512 Gbyte capacity (appears as two 256 Gbyte drives). Also available is ATA Secure Erase support and optional declassification via hardware or software control. The XPort6172 provides bestin-class performance, with up to 200 Mbyte/s sustained sequential read performance and 120 Mbyte/s sustained sequential write performance and 100,000 program/erase cycles. Operating temperature range is -40°C to 85°C. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].


ReadyFlow Board Support Package Speeds Development

Pentek has announced new features for its ReadyFlow board support package (BSP) to simplify embedded development for its Cobalt, Xilinx Virtex-6 based FPGA module family. Enhancements include a Command Line Interface that allows the hardware to run out-of-the-box without having to write any code, and the introduction of a turn-key Signal Analyzer for data display, validation and monitoring. ReadyFlow provides users of Pentek’s Cobalt module family with a variety of tools to help them at all stages of application development. There are numerous C-callable functions to handle initialization and test, data movement and communications and control of all board resources. Utilities such as Flash program memory loaders are also included, as are fully tested C-language application examples that demonstrate the capabilities of Pentek’s modules and serve as a springboard for application development. Library and example source code is also included. The new Command Line Interface of pre-compiled executables is specific to the hardware features of the board it supports. It allows single-command control of parameters such as the number of enabled channels, clock frequency, data transfer size and the like. The Command Line Interface is callable from within a larger user application, providing a convenient way to configure the hardware. Operating parameters canConnected be dynamically changed whileand the Get with technology application is running to address application conditions. companies providing solutions now When used with the Command Line Interface, the new Signal Analyzer allows users to immediately Get startConnected acquiring and displaying data.exploration is a new resource A/D for further into products, technologies and companies. Whether Data display is available in both time and frequency domains and includes built-in measurements for many standard parameters such as 2nd and your goal to research latest datasheet fromfrequency a company,and speak directly 3rd harmonics and total harmonic distortion (THD). Interactive cursors also allow users to mark dataispoints and the instantly calculate withsingle an Application Engineer, or jump company's amplitude of displayed signals. Each ReadyFlow package is specific to the module it supports. The developer license fee tois a$2,500 andtechnical allows page, the goal of Get Connected is to put you in touch with the right resource. royalty-free use of application and example code for multiple projects and includes lifetime support.

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Pentek, Upper Saddle River, NJ. (201) 818-5900. [].

AdvancedMC 6U cPCI SBCs Based on Second Generation Intel Core Processors

Two new single board computers are based on the latest Intel Core i7 processors. The MIC-5603 AdvancedMC and the MIC3395 6U CompactPCI single board computer from Advantech are designed to give OEMs the competitive advantage through the performance enhancements and scalability of the 2nd generation Intel Core processor family. The MIC-5603 AMC with the Core i7 processor targets a broad range of applications where network performance, graphics or vector processing and compute-intensive tasks are required. For supervisory or control applications, an optional front panel HDMI port connects to the processor’s on chip controller offering integrated Intel HD graphics DX10.1 and OpenGL 3.0 capabilities or simply replaces entry-level discrete graphics for a lower BOM cost. Up to 8 Gbytes of DDR3 1333 MHz SDRAM with ECC support, in a dual channel design, makes it ideal for mission-critical applications requiring low latency, reliable memory access. In addition, Advantech’s leading-edge, onboard fabric mezzanine interface enhances modularity for a wider range of fat pipes and I/O choice with standard or custom modules. The MIC-3395 6U CompactPCI SBC fits in a single 4HP slot and expands memory capacity to up to 4 Gbyte on board DDR3 with ECC support and one SO-UDIMM module for up to a further 8 Gbyte. I/O expansion is ensured via an XMC slot whilst mass storage is available with onboard 2.5” SATA-III support, onboard CompactFlash and RTM-based SAS storage options. Six independent gigabit Ethernet ports cater for a wide range of integration options with dual GbE connectivity to front, rear and PICMG 2.16 ports. Advantech, Irvine, CA. (949)798-7178. [].

Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for. Analog NTSC/PAL Embedded Vision System with Core2 Duo 2.26 GHz Processor

An embedded vision system features an Intel Core2 Duo processor and four independent analog NTSC/PAL ports with real-time Get Connected with technology and companies prov image acquisition rates up to 120 Get Connected is a new resource for further exploration into pro fps. The EOS-2000 from Adlink a datasheet from a company, speak directly with an Application Engine compact-size 200 (W) x 165 mm in touch with the right resource. Whichever level of service you requir (7.9” x 6.5” x 3.3”) vision supporting vision with channels, mak- and produc Getsystem Connected will helpfour you connect the companies ing it suitable for space-critical applications. Compared with smart era solutions in the market, the EOS-2000 provides a lower unit cost per channel with more flexible system configurations, as well as software development kit support that allows users to develop their own machine vision solutions. The EOS-2000 also features I/O support that includes two RS232/422/485 ports, four USB ports, 32 isolated digital I/O lines and dual storage options (a SATA interface and a CompactFlash slot) for factoryfloor networks. By selecting long-life embedded components and incorporating system monitoring components to monitor CPU temperature, fan speed and system responsiveness, the EOS-2000 provides a robust and reliable platform for mission-critical applications. Adlink’s embedded vision system is a ready-to-deploy vision solution. Get Connected with companies and The EOS-2000 system cansection. be developed around Microsoft Winproducts featured in this dows 7 Windows XP Embedded (XPe), with support for file-based write filter (FBWF) to provide a stable and secure software operating environment. Pricing starts at $1,750.


ADLINK, San Jose, CA. (408) 360-0200. []. Get Connected with companies and products featured in this section.




Second Generation Intel Core Processors on 3U OpenVPX Form Factor

A 3U OpenVPX embedded Single Board Computer features the 2nd generation Intel Core processor and 6 series chipsets from the Intel embedded roadmap. The TR 80x/39x from Concurrent Technologies provides support for quad-core or dual core 2nd generation Intel Core processors, up to 8 Gbyte of ECC DDR3 SDRAM, configurable PCI Express fabric interface supporting 1 x8, 2 x4, 1 x4 + 1 x4 at Gen 1 or Gen 2 data rates, dual Gigabit Ethernet or dual 1000Base-BX channels, dual SATA600, single XMC slot, serial RS232/422/485 port, dual USB 2.0 ports, independent VGA and display port all in a 3U VPX form factor. The Intel Core microarchitecture virtually doubles graphics performance of previous architectures, and when complemented by support for Intel Turbo Boost Technology capabilities and media acceleration, the TR 80x/39x offers cutting-edge technology for security, transportation, military and embedded systems. Operating systems currently supported for the release of the TR 80x/39x are Windows7, Windows XP, Windows Embedded Standard 7, Linux and VxWorks. The TR 80x/39x is available in three temperature grades; 0° to +55°C (N-Series), -25° to +70°C (E-Series), -40° to +85°C (K-Series). For extreme rugged applications the TR 80x/39x is available in VPX-REDI variants (type 1 and type 2); VPX-REDI Type 1 Conduction-Cooled VITA 47 Class CC4 -40° to +85°C (RCS - Series), VPX-REDI Type 2 Conduction-Cooled VITA 47 Class CC4 -40° to +85°C (RCT - Series). Concurrent Technologies, Woburn, MA. (781) 933-5900. [].

Standard Configurations for Electromechanical Development Tasks

D Space is now offering standard configurations of RapidPro, its modular rapid control prototyping hardware. These ready-made configurations support typical development tasks such as developing transmission controllers, and most importantly, current development trends such as powertrain electrification and continued optimization of fuel consumption and emissions in combustion engines. D Space RapidPro provides signal conditioning and power stages for connecting automotive sensors and actuators to D Space prototyping systems. The modular, compact RapidPro hardware from D Space provides signal conditioning and power stages for connecting automotive sensors and actuators to D Space prototyping systems. A large number of modules are already available for different sensors and actuators, and D Space continues to extend the RapidPro range. The new ready-made configurations give users complete solutions for connecting sensors and actuators, enabling them to concentrate fully on their real task—controller development. For example, developing new combustion processes is much easier with the engine control configurations for combustion engines with up to 6 cylinders. These configurations also help with current development trends such as downsizing and direct injection, by connecting the latest sensors and actuators. The configuration for e-motor control acts as a flexible rectifier output stage in the prototyping phase for a variety of electric motors. Each configuration is an optimal combination of RapidPro hardware. And if a user’s requirements differ from the ready-made configurations, the RapidPro system is flexible for adaptations and extensions. Mathworks’ Simulink I/O models that are designed specifically for the RapidPro standard configurations are also available. Tasks within the Simulink models contain the preconfigured I/O signals of the connected sensors and actuators: For example, angle-synchronous tasks provide the signals for combustion engine control. dSPACE, Wixom, MI. (248) 295-4700. [].



COM Express Compact AtomBased Module with Low Power, High Graphics

A new COM Express Type 2 module is based on the Atom E6xx processor series and the Intel Platform Controller Hub EG20. All components are specified for the industrial temperature range of -40˚ to +85°C. The conga-CA6 from congatec has a power consumption of less than 5 watts and a compact size of 95 x 95 mm. Long battery life, as a result of optimized power consumption and battery management, makes for a direct cost saving factor in portable devices. Hyperthreading technology allows the logical division of the physical processor core to enable multi-processing across two separate processors. This means that safety-critical applications can run on a real-time operating system with a logical core that is separate from the graphical user interface which, for example, can run on a Windows operating system. The conga-CA6 module is available as a 600 MHz, 1.0 GHz, 1.3 GHz and 1.6 GHz option with 512 Kbyte L2 cache and can access up to 2 Gbytes of rugged soldered DDR2-RAM. Memory access, sound and graphics are all integrated directly into the processor. The new integrated 3D-enabled graphics engine has received a 50 percent performance boost and can accommodate up to a 256 Mbyte frame buffer. The graphics support DirectX 9.0E as well as OpenGL 2.0; video applications benefit from hardware decoding in MPEG-2 and MPEG-4; while graphics output is via 24-Bit LVDS channel or SDVO. The conga-CA6 also offers up to 3 PCI Express x1 lanes, 2x SATA, PCI bus, EIDE interface, Gigabit Ethernet, High Definition Audio and 6 USB ports. Via the SATA interface, the module offers up to 32 Gbytes of optional onboard flash memory for robust mass storage. Pricing starts at $300 in OEM quantities. congatec, Cardiff-by-the-Sea, CA. (760) 635-2600. [].


CompactPCI Serial SBC Brings Serial Interfaces to Rugged Computing

A new single-board computer is based on the newly ratified PICMG CPCI-S.0 CompactPCI Serial specification that was announced at Embedded World 2011. The G20 from Men Micro uses the 64-bit Intel Core i7 processor with a base processing speed of 2.53 GHz that supports Intel Turbo Boost Hyperthreading technology to provide a maximum speed of 3.20 GHz. In addition to the standard, fast 8 Gbyte DDR3 ECC SDRAM soldered against shock and vibration, a CompactFlash and a microSD card slot are connected to the G20 via one USB interface can extend memory capacities. A CPU-independent microprocessor in the G20 based on the Intel Advanced Management Technology (AMT) allows remote access via an integrated Ethernet controller, even when the computer is in soft-off or stand-by state. This is especially useful in systems where the operating system has crashed or the hard disk is defective, since an error diagnosis with repair can be carried out remotely as long as the system has standby voltage. AMT also enables users to remotely access different functions such as reading status information, changing configurations, switching the PC on and off as well as forwarding or redirecting I/O devices like hard disks and CD-ROM (Serial Over LAN) via keyboard, video or mouse. Standard front I/O includes two PCIe-driven Gigabit Ethernet and two USB 2.0 interfaces as well as two DisplayPorts that can be used as an HDMI or DVI connection via an external adapter. A total of eight PCI Express links in the front and back of the G20 enable fast communication. For user-specific applications, the rear I/O also provides eight USB ports, six SATA ports, a Display or HDMI port as well as a PEG x8 port and five PCI Express x1 links. MEN Micro also offers the GM1 CompactPCI Serial mezzanine module that leads four of the possible eight Ethernet interfaces specified Get Connected with technology andin companies solutions the standard to the backplane where they are implemented on CompactPCI Serial connector P6 assembled on the GM1,providing saving costs and now increasing system flexibility. Get Connected is a new resource for further exploration intowatchdogs products, technologies and companies. Whether your goal The G20 includes an InsydeH2O EFI BIOS specially developed for embedded applications. Different for monitoring the processor is to research the latest datasheet from a company, speak directly and board temperature complete the functionality of the SBC, which is shipped with board support packages for Windows and Linux. VxWorks and with an Application Engineer, or jump to a company's technical page, the QNX are available upon request. The rugged board holds DIN, EN and IEC certifications to enable its use in harsh environments. It comes coated goal of Get Connected is to put you in touch with the right resource. for use in humid and dusty environments and has a guaranteed minimum standard availability Whichever of seven years. forrequire the G20 is $2,097. level of Pricing service you for whatever type of technology,

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MEN Micro, Ambler, PA. (215) 542-9575. [].

12-COM-Port Fanless Embedded Computers

An industrial and rich I/O fanless embedded computer comes with enhanced RF functions and LVDS and VGA dual display geared specifically for applications such as intelligent transportation, factory automation, home security, environmental monitoring and research. The MXE-1200 from Adlink includes a rugged fanless operation from -20째 to 70째C, 5 Grms vibration resistance, an Ethernet port and 6-36 VDC wide range power input. The MXE-1200 series is a compact-size 210 mm x 170 mm x 54 mm I/O platform and suitable for operating in a relatively limited storage space. The cable-free architecture and wide temperature range of the MXE-1200 greatly benefits customers who require compact and reliable computing solutions and a lower maintenance cost of systems. Featuring Rich I/O and RF support, two of the 12 COM ports can be configured to RS-232, RS-422 or RS-485 via a BIOS setting. The remaining COM ports are either RS-232 RS-422, or RS-485. The MXE1200 series also includes with a mini-PCIe socket, a USIM socket, and a pre-installed SMA-to-IPEX antenna cable to support expansion of wireless communication capabilities. The MXE-1200 is designed to perfectly communicate with external devices, which greatly benefits many applications such as toll gate controllers (RS-232), automatic fare collection systems (RS-232) and smart grids (RS-422/485). Single quantity pricing starts at $828. ADLINK, San Jose, CA. (408) 360-0200. [].

Get Connected will help you connect with the companies and products you are searching for.

3U CompactPCI XMC/PMC Carrier Upgrades cPCI Systems

An air-cooled, 3U CompactPCI (cPCI) XMC/ PMC carrier card enables the integration of additional processing or I/O Get Connected with technology and companies prov capability into a 3U cPCI Get Connected is a new resource for further exploration into pro system by mounting a datasheet from a company, speak directly with an Application Engine PMC, PrPMC, or in touch with the right resource. Whichever level of service you requir XMC mezzaGet Connected will help you connect with the companies and produc nine module on the XChange1200. The XChange1200 from Extreme Engineering Solutions features a single XMC/PMC site, a x1 PCI Express XMC interface, a 32-bit, 66 MHz PCI PMC interface along with I/O Routing from the PMC P14 connector to the cPCI backplane P2 connector. No drivers are required.


Extreme Engineering Solutions Middleton, WI. Get Connected with companies and (608) 833-1155. products featured in this section. []

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3U CompactPCI Enhanced by Second Generation Intel Core processors

A single-slot air-cooled 3U CompactPCI Single Board Computer (SBC) features integrated graphics and memory controller on a single 32 nm process technology. The TP 86x/39x from Concurrent Technologies leverages exceptional CPU and graphical performance with a choice of the Intel Core i7-2715QE processor, Intel Core i7-2655LE processor, Intel Core i7-2610UE processor or Intel Core i5-2515E processor and the enhanced features of the Intel Series 6 Express chipset, along with up to 8 Gbytes of DDR3-1333 ECC SDRAM. The TP 86x/39x SBC also features a 32-bit 33/66 MHz PMC or an XMC x4 PCI Express site along with a wide array of additional I/O; 2x USB 2.0, 2x SATA, 2x serial channels (RS232 and TTL), 1x Gigabit Ethernet port, 1x DisplayPort, and 64-bit PMC rear I/O. The front panel also features Gigabit Ethernet, serial port, 2x USB 2.0 and a VGA port; further I/O is supported with an optional second slot PMC/XMC board. The CompactPCI interface of the TP 86x/39x offers a system slot controller, which provides an Intelligent Platform Management Interface (IPMI) for PICMG 2.9 R1.0, support for up to 7 peripheral slots, full support for hot-swap capabilities and the ability to operate in satellite mode (CompactPCI interface disabled). Operating systems currently supported are Windows 7, Windows XP, Windows Embedded Standard 7, Linux and VxWorks. Addressing today’s demanding applications from medical to military the TP 86x/39x SBC is designed to scale from commercial temperature grade 0°C to +55°C (N-Series) through to extended temperature grade -40°C to +85°C (K-Series). Concurrent Technologies, Woburn, MA. (781) 933-5900. [].

Transient Recorder Combines Channel Density with High-Precision Measurements

A new transient recorder system provides up to 64 channels in one system. The TraNET EPC system from Elsys combines a family of high-speed LAN-controlled instruments featuring multiple acquisition modes with a series of robust industrial computers designed for high-precision measurements in industrial environments. TraNET EPC can be equipped with up to 16 of Elsys’ TPCX PCI-compatible digitizer modules that feature unique measurement precision of typically ±0.03%, sample rates up to 240 MS/s at a vertical resolution of 14 bits (up to 30 MS/s at 16 bits) and acquisition memories up to 128 Mpoints per channel. Available in 8-, 16-, 24-, 32-, 48- and 64-channel versions, the scalable TraNET EPC can be coupled and synchronized for clock and trigger with the unique “Sync-Link Box” for up to 512 parallel channels. With Elsys’ TransAS 3 software, TraNET EPC becomes a turnkey solution that enables both quick configuration of acquisition channels as well as a post-processing analysis of complex waveforms. In addition, two entirely separate instrument functions can run on a single EPC backplane using TransAS 3. Elsys’ complete TraNET series of transient recorders features several data acquisition modes. Scope mode, similar to an oscilloscope, enables the quick configuration of the acquisition parameters before working in a different mode or simply the ability to visualize and analyze single-shot events. The Elsys TPCX data acquisition modules, the heart of every TraNET EPC system, offer many advanced features such as single-ended and differential inputs, large input voltage and offset ranges, advanced trigger capabilities with an external trigger, programmable anti-aliasing filters as well as ICP input for piezo sensors and digital inputs. Pricing starts at $9,500 (8-channel). Elsys Instruments, Niederrohrdorf, Switzerland. +41 56 496 01 55. [].



Atom-Based 1U Platform Provides External PCI Card Access

A 1U rackmount platform with the Intel Atom D510 dual-core or D410 single-core processor, includes six GbE LAN ports and an externally accessible PCI slot. The externally accessible PCI card support on the PL-80300 from Win Enterprises means OEMs and system integrators can easily configure the unit to support a wide range of networking, telecom and security applications including, incremental GbE ports, FXO/FXS, T1/E1, Wi-Fi, Crypto acceleration and more. Features include support for the D410 or D510 Atom Pineview low-voltage processors plus the Intel 82801HM Controller, external access to the PCI card slot and a maximum of six GbE LAN ports via PCI-E x1. In addition, the unit includes USB 2.0, a 3.5” SATA HDD bay, CF socket, mini-PCI slot and Console port. The PL-80300 is RoHS compliant. Recommended operating systems for PL80300 include Windows XP Pro and Windows 7. Linux version support includes: Fedora 13, Debian 5.0.6 and openSUSE 11.3. The system supports 32-bit and 64-bit software. Additional Windows and Linux distributions are documented to support the Intel Atom D410/D510 + ICH8M with 82574L drivers. Users should check their operating system documentation for hardware compatibility or contact WIN Enterprises regarding their software selection. The 100 unit price with Dual-Core Atom D510 processor costs $459. WIN Enterprises North Andover, MA. (978) 688-2000. [].


XMC Module with Configurable FPGA Targets Cost-Sensitive Embedded Tasks

To address the need for low-cost configurable FPGA computing solutions, a series of new XMC-SLX mezzanine modules features an economical Xilinx Spartan-6 FPGA. The Spartan-6 FPGA’s logic structure leverages the premium-performance Virtex FPGA platform’s architecture and system-level blocks for faster, easier and more compatible development. Acromag supports the FPGA with a high-throughput PCIe interface, generous memory and convenient access to field I/O signals. Typical uses include hardware simulation, in-circuit diagnostics, communications, signal intelligence and image processing. Field I/O interfaces to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine I/O extension modules. 64 I/O or 32 LVDS lines are accessible through the rear connector. Acromag’s plug-in AXM mezzanine cards provide additional I/O processing capabilities. A variety of these AXM mezzanine I/O cards are available to provide front-end 14-bit 105 MHz A/D conversions or an interface for CMOS digital I/O, RS-485 differential signals, or extra LVDS I/O lines. Large, high-speed memory banks enable high-efficiency data handling. 256k x 64bit, or optional 1M x 64-bit, dual-ported SRAM facilitates high-speed DMA transfers to the bus or CPU. This memory provides direct links from the PCIe bus and to the FPGA. The high-bandwidth PCIe 4-lane interface ensures fast data throughput. Acromag’s Engineering Design Kit provides utilities to help users develop custom programs, load VHDL into the FPGA, and establish DMA transfers between the FPGA and the CPU. The kit includes a compiled FPGA file and example VHDL code as selectable blocks with Get provided Connected with technology and companies providing solutions now examples for the local bus interface, read/writes, and change-of-state interrupts to the PCI bus. A JTAG interface allows users to perform onboard VHDL simulation. Further analysis is supported with a ChipScope Pro interface. Get Connected is a new resource for further exploration products, technologies andfor companies. Whether your goal For easy integration of the boards with embedded Windows applications, Acromag developed a DLLinto driver software package compatibility to research the latest datasheet from a company, speak directly with Microsoft Visual C++ and Visual Basic. Sample files with “C” source demonstration programs isprovide easy-to-use tools to test operation of with an Application Engineer, or jump to a company's technical page, the the module. For real-time and open-source applications, Acromag offers C libraries for VxWorks, Linux and other operating systems. Pricing starts goal of Get Connected is to put you in touch with the right resource. at $2,895 with options for extra memory and extended temperature operation. Whichever level of service you require for whatever type of technology,

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Acromag, Wixom, WI. (248) 295-0310. [].

Double-Width AdvancedMC Processor Module with Core i7

A double-width AdvancedMC processor module is equipped with an Intel Core i7 Mobile processor and Hyper-Threading technology. The AM5020 from Kontron incorporates up to 2.53 GHz of dual-core performance to run Get Connected with technology and companies prov parallel, multi-threaded applications on MicroTCA integrated platforms. The module incorporates the Core i7 processor with an integrated memory controlGet Connected is a new resource for further exploration into pro datasheet from a company, speak directly with an Application Engine ler, PCI Express Gen2 I/O and Intel HD graphics coupled with the integrated in touch with the right resource. Whichever level of service you requir QM 57 platform controller hub (PCH). Get Connected will help you connect with the companies and produc With support for PICMG AMC.1/.2/.3 sub-specifications, the AM5020 ensures a comprehensive set of interconnecting capabilities. Eight PCI Express lanes to the backplane are configurable as 2 x PCIe x4 or 8 x PCIe x1. Four GbE interfaces, two on the front panel and two on the backplane in accordance with AMC.2, provide comprehensive networking capabilities. The AM5020 provides an extensive range of mass storage support with six SATAII channels. Users can choose between an onboard 2.5” SATA drive and/or up to 32 Gbyte of SATA flash memory, which is securely fastened to the PCB. In addition, four SATA channels are routed to the AMC connector (AMC Port 2, 3, 12 and 13), enabling applications with a high amount of storage capacity and RAID. The Kontron AM5020 also features a DVI-D interface at the front combined with two USB interfaces, two GbE and a serial port via RJ45. With this comprehensive set of internal and external I/Os on a single module, the Kontron AM5020 represents a space-saving and cost-effective solution for a broad range of I/O and data-intensive applications. The Kontron AM5020 has full hot-swap capabilities for monitoring, controlling and replacing the module. The Intelligent Platform ManageGet Connected with companies and ment Interface (IPMI) enhances the board’s availability while reducing the overall operating costs and mean time to repair. A dedicated Module products featured in this section. Management Controller (MMC) is used to manage the board and supports basic IPMI commands, which enable operators to monitor the state of the AdvancedMC module in the system. The mid-size, double-width Kontron AdvancedMC processor board AM5020 supports Windows XP, Windows 7, Windows Server 2008, as well as VxWorks 6.8 and Wind River Linux PNE 3.0.2.


Kontron, Poway, CA. (888) 294-4558. []. Get Connected with companies and products featured in this section.




Mini-ITX Embedded Board Based on Second Generation Intel Core Family

A new Mini-ITX form factor embedded system board is designed to provide high performance and flexibility for functional expansion and is suitable for applications in gaming, kiosk, digital signage, medical/healthcare, defense and industrial automation and control. The WADE-8012 from American Portwell supports the Intel Q67 chipset and the latest 2nd generation Intel Core processor platform, formerly codenamed “Sandy Bridge,” in an LGA1155 package, integrated with the memory and PCI Express controller supporting two-channel DDR3 memory and PCI Express 2.0 lanes to provide high graphics performance. The 2nd generation Intel Core processor family features a brand new monolithic design that provides greater performance while still maintaining power efficiency. The Intel Q67 chipset continues to push innovation with an architecture designed to deliver quality, performance and industry-leading I/O technologies on platforms powered by the dual-core/quad-core Intel Core processor. Combining the Intel Q67 chipset with a processor from the 2nd generation Intel Core processor family, it enables Portwell’s WADE-8012 Mini-ITX embedded system board to deliver smart security, cost saving manageability and intelligent performance for business platforms. The WADE-8012 Mini-ITX embedded board includes many practical features, such as support for next-generation SATA hard drives based on the new SATA 6 Gbit/s storage specification; configuration of six SATA (two SATA 6.0 Gbit/s and four 3.0 Gbit/s ports) connectors; RAID 0/1/5 and 10; support for the latest PCIe 2.0 (one PCI Express x16 slot) device for double speed and bandwidth, which enhances system performance; two long-DIMM memory slot for DDR3 SDRAM up to 8 Gbyte; up to 8 USB 2.0 ports (4 on rear I/O and 4 on board); VGA / HDMI / DVI-D; and two Gigabit Ethernet. American Portwell, Fremont, CA. (877) 278-8899. [].

AMD Fusion Combines with ETX and XTX for Form-Fit-Function Optimization

The ETX and XTX form factors are getting a boost to the future with the integration of AMD Fusion technology. Intel’s discontinuation of the 855 chipset family left a major gap in the market particularly for ETX computer modules, which primarily affected the higher performance range of applications. This gap has now been closed by AMD with the Fusion architecture. Fusion also opens up new perspectives for a wide range of innovative and graphics-oriented applications. Congatec supports the Fusion architecture with two new COM modules: conga-EAF and conga-XAF. While conga-EAF is an ETX module, conga-XAF is an XTX module based on the XTX standard. The difference between the XTX and the ETX standard is that XTX no longer supports the ISA bus, but instead a four-lane PCI Express bus. XTX also has more S-ATA and USB interfaces than ETX. The two modules have many similarities. Both run on processors from AMD’s G-series and are equipped with the Embedded Controller Hub Hudson E1, providing a two-chip solution with up to 4 Gbytes of single-channel DDR3 memory. congatec currently offers a total of five processors from the AMD embedded G-Series platform, ranging from a single-core 1.2 GHz AMD T44R (64 Kbyte L1 cache, 512 Kbyte x2 L2 cache) with 9 watt TDP, to a 1.6 GHz dual-core AMD T56N (64 Kbyte L1 cache, 512 Kbyte x2 L2 cache) with 18 watt TDP. The integrated graphics core with the Universal Video Decoder 3.0 for seamless Blu-ray processing via HDCP (1080p), MPEG-2 HD and DivX (MPEG-4) videos supports DirectX 11 and OpenGL 4.0 for fast 2D and 3D imaging as well as OpenCL 1.1. The APU has two independent graphics controllers providing a VESA-compliant video output with resolutions of up to 2560 x 1600 pixels. The Fusion architecture itself combines two previously separate computing functions, namely the CPU and the GPU) into an Accelerated Processing Unit (APU). Fusion architecture implements the graphics unit as General Purpose GPU (GPGPU). It contains many configurable parallel processing units that can also be used for tasks that have nothing to do with the graphics. The GPGPU can therefore be used to perform certain compute-intensive tasks in parallel, thereby increasing throughput significantly. Numerical calculations and tasks, which require intensive coding/ decoding effort, can be accelerated dramatically in this way. Applications that benefit from this technology, apart from multimedia processing, include encryption/decryption and packet processing in networks. From a programming perspective, these processes are transparent; manual parallelization is not required. congatec, Cardiff-by-the-Sea, CA. (760) 635-2600. [].




Software Verification Tool Boosts Automation and Transparency of Test Process

A test management and traceability component for the LDRA tool suite increases automation of verification tasks and result retrieval to complete workflow integration. TBmanager is a test management and traceability component within the LDRA tool suite. With the adoption of process-oriented standards such as IEC 62304, IEC 61508:2010 and ISO/DIS 26262, software developers must comply with programming standards and provide requirements traceability. To ease compliance and requirements traceability, TBmanager has been extended to deliver greater transparency, implement consistent test plans throughout a team, and manage the flux between requirements, code and tests. Traditionally, developers have been forced to drive test scenarios as a standalone process outside the reach of their overall development tool chain. Any findings would then have to be manually connected back into development processes. TBmanager’s solution creates access to otherwise isolated test teams with an integrated test management platform. Central to TBmanager’s management capabilities is its mapping between requirements, code and test. Once mapping is established, code changes can be seen within TBmanager and suspect links, such as unmapped or removed source, can be corrected and code retested. This increased Get Connected with technology and transparency and linkage dramatically pinpoints suspect code, enabling it to be quickly corrected and retested. companies providing solutions now If projects lack requirements, TBmanager quick-starts the transition to requirements-driven development, creatingis low-level requirements Get Connected a new resource for further exploration companies. Whether your goal identifiers that can be linked to high-level requirements. Such a solution significantly boosts automation into andproducts, ease oftechnologies use, whileand ensuring top-down is to research the latest datasheet from a company, speak directly coverage of the software lifecycle. with an Application Engineer, or jump to a company's technical page, the Thanks to filters and graphical improvements, developers can intuitively drive the execution and collection of results, easily navigating the goal of Get Connected is to put you in touch with the right resource. vast amount of requirement-related information. In addition, TBmanager confirms adherence toWhichever coding standards andyou quality unit testing, level of service require metrics, for whatever type of technology, project objective checklists—all essential for exposing gaps in requirement traceability, code coverage or standards compliance. Such integration Get Connected will help you connect with the companies and products you are searching for. ties together all phases of the testing process, providing a robust audit trail for internal quality control or certification.

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LDRA, Wirral, UK. +44 0151 649 9300. [].

Embedded UI Design Tools Integrated with RTOS

A complete family of graphical interface development tools is fully integrated with an RTOS. The PrismX framework from Blue Water Embedded is integrated with the ThreadX RTOS from Express Logic for efficiently designing and Get Connected with technology and companies prov deploying advanced graphical interfaces on embedded systems, providing a developer with the ability to make UI visions a Get Connected is a new resource for further exploration into pro reality. The PrismX family includes two major components: PrismX Runtime and PrismX Insight. datasheet from a company, speak directly with an Application Engine PrismX Runtime Framework incorporates a complete high-performance graphical drawing library and GUI widget in touch with the right resource. Whichever level of service you requir set. PrismX Runtime Framework allows you to incorporate any number of fonts, images, strings and other assets seamGet Connected will help you connect with the companies and produc lessly on your embedded target, with or without a file system. The widget set includes a wide variety of buttons, panels, scroll bars, text display and rich text editing controls, sliders, charts, graphs, animations, icons, and other graphical widget types. Developers can easily add their own custom widgets to the framework. Any combination of input devices including keypad, keyboard, touch screen, mouse, and multi-touch capable input devices can be utilized within this framework. Variations of PrismX Runtime Framework are available for all color depths, screen resolutions and hardware capabilities. Color depths ranging from monochrome to full 32-bit-per-pixel drawing with alpha channel are fully supported. PrismX Runtime Framework is provided ready to run with ThreadX on the embedded target without requiring any underlying support. PrismX Runtime Framework is also provided in desktop configurations, meaning that you can build and execute your complete UI design in a Microsoft Windows or Linux/X11 environment well before the availability of target hardware. PrismX Insight is the desktop UI design and resource editing tool. PrismX Insight allows you to completely design your user interface using a drag-and-drop WYSIWYG environment. A complete button designer allows you to define buttons and menus with the exact appearance you require. The Animation Designer allows you to specify screen flows and select from a wide range of built-in or even custom screen transition effects and animations. PrismX Insight generates output that is compatible with PrismX Runtime Framework. You can choose any combination of supported data output formats, depending on the requirements and capabilities of your target system. PrismX Insight can produce C++ source code, ready to compile and run on a resource conGet Connected with companies and strained target. This option usually provides the best runtime performance. PrismX Insight canproducts also produce XML description files, which are parsed and featured in thisscreen section. decoded by the PrismX Runtime Framework during system startup. This option requires a file system on the target, but also enables more sophisticated modifications and updates to your UI design even after a product has been released in the field. PrismX Insight also allows you to produce modular system resource files, in source or binary formats, containing any combination of colors, graphics, fonts, strings, screen flows and database schema. This capability allows you to “reskin” your user interface on the fly, add new screens or new display fields, or support any number of languages, all without doing any manual software coding.


Express Logic, San Diego, CA. (858) 613-6640. [].

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with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




ACCES I/O Products...................................

ADLINK Technology America, Inc.................





Innovative Integration.................................. 23...........................

End of Article

Lippert Embedded Computers..................... 18...................................

Advantech Technologies, Inc....................... 29.................................

Logic Supply, Inc........................................ 48................................

Get Connected with companies and products featured in this section. AMD..........................................................

Measurement Computing..mentioned .......................... with companies in this 19. article.

American Portwell Technology, Inc..............

MEN Micro, Inc.......................................... 32..................................

Get Connected with companies and products featured in this section.

Arbor Solutions........................................... 4..............................

Get Connected with companies mentioned in this article. One Stop Systems. .....................................

Avalue Technology...................................... 28................................

PC/104,PC/104 Express and ISM Showcase ..........................44,45................................

Avnet Electronics Marketing........................ 43.............................

Phoenix International................................... 4.....................................


The Math Works, Inc................................... 2.................................

Cogent....................................................... 38...................................

Themis Computer.......................................

ELMA Components Div...............................

WDL Systems.............................................

Extreme Engineering Solutions, Inc............. 35......................................


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May 2 - 5, 2011

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April 2011

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