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The magazine of record for the embedded computing industry

March 2011

www.rtcmagazine.com

MHz, Watts, Size Optimizing Energy Use

Merging Configurability with Programmability The Quest to Secure Networked Devices FPGA Family Spans Spectrum of Design Needs An RTC Group Publication


MHz, Watts, Size

Optimizing Energy Use

45 High-Resolution Signal Acquisition Module for Audio and Vibration Testing

46 SBC wtih New Atom N455/D525 Targets High Reliability

TABLEOF CONTENTS

48 Rugged 512 Gbyte Solid State Disk XMC with Data Encryption

MARCH 2011

Departments

5Editorial The Dance of Optimization: Waltzing Down to the Silicon Insider 6Industry Latest Developments in the Embedded Marketplace

10 & Technology 44Products Newest Embedded Technology Used by Industry Leaders Small Form Factor Forum If Memory Serves

EDITOR’S REPORT

Technology in Context

TECHNOLOGY IN SYSTEMS

Configurable and Programmable Devices

Optimizing Energy Use

and Programmable: 16 Configurable The Sweet Spot for the SoC Jamie Brettle, National Instruments and Greg Brown, Xilinx

TECHNOLOGY CONNECTED Security for Networked Devices

20

Securing Your Embedded Designs: Encryption and Authentication ‘Keys’ to Success Daryl R. Miller, Lantronix

24

Security Considerations in Embedded I/O Virtualization

David Kleidermacher, Green Hills Software

FPGA Family Spans the Spectrum

12

28 nm FPGA Device Portfolio Addresses Continuum of Design Requirements

Energy Savings in Real 28Managing Time Raman Sharma, Energy Micro and John Carbone, Express Logic

Debugging the Software: 34Power Optimizing the Power Consumption of an Embedded System

Lotta Frimanson and Anders Lundgren, IAR Systems

TECHNOLOGY DEPLOYED Small Modules in Transportation

Applications Find Value in Centralized Computing 38Transportation Platforms Walter Furter, Kontron

Tom Williams

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MARCH 2011

Conduction Cooled VME Solid State Disk Phoenix International’s VC1-250-SSD Conduction Cooled Serial ATA (SATA) based Solid State Disk VME blade delivers high capacity, high performance data storage for military, and y, aerospace p industrial applications requiring rugged, extreme emee envi eenvironmental i ron ronmen me tal and secure mass data storage.

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Editorial

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EDITOR-IN-CHIEF Tom Williams, tomw@rtcgroup.com CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, marinat@rtcgroup.com COPY EDITOR Rochelle Cohn

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The magazine of record for the embedded computing industry

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MARCH 2011 RTC MAGAZINE

To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com Editorial Office Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214

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EDITORIAL MARCH 2011

Tom Williams Editor-in-Chief

T

The Dance of Optimization: Waltzing Down to the Silicon

here appears to be a transition taking place that will significantly influence the way embedded systems are designed. For some time we have been witnessing developments in small form factor modules in various creative incarnations. The venerable PC/104 form factor continues its healthy acceptance along with such derivations as PC/104 Express and SUMIT-ISM, other stackable form factors like EPIC and EBX, and COM Express and its variants now shrinking down to the sub-credit-card “ultra” size. The list goes on. These innovations are the result of the push to find optimal solutions to a variety of problems and applications. That is what engineers do for a living. One such class of problems that cuts across the efforts of stackable and COM approaches has been how to combine the general-purpose functionality (CPU, memory) with the more specialized functionality (I/O). That gets far less than straightforward when you try to optimize the combination for size, cost, performance, power consumption and ruggedness. Still, the efforts and the results at the small module level have been mighty. It now appears that this titanic struggle will increasingly be taking place at the silicon level. Advances in programmable logic and the ability to combine it with hard-transistor IC implementations on a single die are leading to rapid advances. In this issue of RTC we have news of a major rollout from Altera and the productization of efforts by Xilinx that were first announced last year. In addition, Microsemi and Cypress Semiconductor already have products on the market with more to come. It has long been assumed that from a performance/size/power perspective, hard-wired ASIC would be the ideal solution. Little considerations like cost, however, have kept that from happening. Now, however, the effort to combine general programmability with application-specific circuits and functionality is moving from board to die. Lest I be misunderstood, this is not going to spell the end for small modules, but it may make them smaller and less critical in terms of form factor. Still you have to get the results of all this processing off the board and into the system and the real world, which is not measured in nanometers. Boards and connector technology have a bright future in the world of these developments. Many of these efforts combine a CPU with a programmable logic fabric as is the case with the Microsemi SmartFusion, the Xil-

inx Zynq, the Cypress PSoC and the combination of an Intel Atom processor with an Altera FPGA fabric in the Stellarton module. The latter has not (yet) combined these two elements on a single die and nobody is talking, but, well . . . it looks like a natural next step. In addition, Altera has just announced the rollout of its 28nm technology in the form of three families of FPGA devices. While these do not explicitly include an on-chip CPU, the Embedded Hardcopy Block (EHB) technology that allows the implementation of hard transistor circuits in the same die with the FPGA, makes that at least theoretically possible as well. Altera also offers the ability to take a proven FPGA or FPGA/EHB combination and move it directly to a fully hard-transistor ASIC implementation with the attendant advantages in cost, power, performance and size. And thus the general-purpose programmable functions of the CPU and the application-specific functions of the I/O subsystem—which have heretofore been accomplished with stackable or COM modules—become available on a single chip and at costs that no longer need be justified by huge volumes. The days when developers sent an ASIC design off to the fab and then sat staring blankly at a revolver on their desks hoping that some flaw would not turn up in the finished part may now mostly be over. You get to fully check out the FPGA-based design in the deployed product, correct any errors and then when more modest volumes and greater confidence allow, move it to the fully hardened part. Of course, the existence of these parts that have been dubbed by some as Application Services Platforms (ASPs) does not fully bridge the gap between software and hardware design. Writing C code for a well-known processor architecture such as the ARM is still a different discipline from developing hardware functions or implementing hardware algorithms on an FPGA. Advances in development tools have certainly helped and have at least greatly aided communication between the two disciplines, but there is more to do. One of the hopeful developments is that it will become much easier and less costly to experiment to see if it is better to implement a given function in software or hardware and to produce actual data on the differences. This is what we might call another round in the “dance of optimization.” It never ends. The words to the music go something like, “Wow. That’s really cool. But maybe we can tweak this part a little more.” And the band plays on. RTC MAGAZINE MARCH 2011

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INDUSTRY

INSIDER MARCH 2011 Bridgewater Surpasses 10 Million Machine-to-Machine Connections Bridgewater Systems has announced that during 2010 it surpassed management of more than 10 million devices supporting a range of machine-to-machine (M2M) applications. Bridgewater enables mobile operators to offer a variety of M2M services by securely managing M2M connections on 3G and 4G networks using intelligent broadband controls such as device service control, dynamic policy control and device identity management. More than 10 million devices, on a range of worldwide service provider networks, are supported today by Bridgewater solutions that: manage secure device access to 3G and 4G networks; model complex device network entitlements such as security requirements, time-of-day, dayof-week restrictions; and meter device usage in real time. These deployments support numerous M2M applications such as smart meters for utility companies, automotive infotainment services, in-vehicle tracking devices and mobile payment services. The Bridgewater Policy Controller/PCRF supports dynamic metering and Quality of Service (QoS) control for devices. An M2M service provider recently selected Policy Controller to meter network resource usage on a per-device basis, as part of their comprehensive M2M service offering to global operators. The Bridgewater Service Controller provides device service control (AAA), enabling secure device access to mobile data networks. Policy Controller and Service Controller are anchored by Bridgewater’s Subscriber Data Broker, a common subscriber and device identity management platform that allows operators to model devices and their corresponding network entitlements in logical groups, with the ability to target individual devices with unique security or resource requirements.

Imec and Holst Centre Bring Brain Wave Monitoring to the Home

Imec and Holst Centre have presented breakthroughs in enabling technologies for wireless electroencephalogram (EEG) systems enabling continuous ambulatory monitoring. The demonstrated EEG headset is compatible with dry electrodes and combines ease of use with ultra-low-power electronics. The prototype headset records high-quality EEG signals and wirelessly transmits the data in real time to a receiver located up to 10m from the system. Applications that can be envisaged with this EEG pro-

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MARCH 2011 RTC MAGAZINE

totype system include entertainment and infotainment, for example, an adaptive game environment reacting to the player’s cognitive state, or elearning where the difficulty can be adapted based on cognitive load; lifestyle, such as neuro-feedback; safety, for example monitoring drowsiness of drivers or cognitive load of occupational health services in action; and medical such as an early warning system for epileptic patients or brain typing enabling people with motor disabilities to communicate. At the heart of the system is imec’s 8-channel ultra-low-pow-

er analog readout ASIC (application-specific integrated circuit). The ultra-low-power readout ASIC consumes only 200 µW and features high common mode rejection ratio (CMRR) of 120 dB and low noise (input referred noise of 55 nV/√Hz). These performances are achieved at high input impedance (1 GΩ), which makes it compatible with the use of dry electrodes. The electronics, including ASIC, radio, and controller chips are integrated in a small wireless EEG system of 25 mm x 35 mm x 5 mm dimensions, can easily be embedded in headsets, helmets or other accessories. The signal to noise ratio of the system is 25 dB on real EEG signals. The entire system consumes only 3.3 mW for continuous recording and wireless transmission of 1 channel, and 9.2 mW for 8 channels. This gives between 1.5 to 4 days of autonomy on a small 100 mAh Li-ion battery, depending on the mode of operation.

CANopen Task Force for Operator Environments

CAN in Automation (CiA) has established the CANopen Task Force (TF) for operator environments. It is intended to develop the CiA 401-based recommended practice for operator environments with human-machine interface functionality dedicated but not limited to construction, mining, agriculture and forestry machines, harbor cranes, boats and vessels, wheelchairs and any other kind of machine on wheels. This includes any kind of operator environment such as driver and operator seats. The CANopen interface hides the OEinternal networking, which could be based on CANopen or other network technologies.

The CANopen recommended practice should describe a single interface hiding the sub-layered devices such as joysticks, foot-pedals, encoders, display, pushbuttons, pulse wheels, etc. For displays, it is intended to use the network variables as specified in the CiA 302 series. When the deeply embedded communication system of the operator environment is based on CANopen, it is recommended to implement the CiA 302-7 bridge/router functionality so the vehicle controller can access each operator device individually by means of Remote SDO services.

ETSI Enters into Partnership with Alliance for Telecommunications Industry Solutions

The European Telecommunications Standards Institute (ETSI) is pleased to announce that it has recently entered into a Memorandum of Understanding (MoU) with The Alliance for Telecommunications Industry Solutions (ATIS). The objective is to perform and promote regional and international standardization with the aim of contributing to the establishment of a global information and communications technology (ICT) infrastructure. The agreement formalizes an already successful collaboration in 3GPP, the global collaboration for the development of standards for advanced mobile communication technologies, in which ATIS and ETSI are two of six Organizational Partners. The new, formalized relationship between ATIS and ETSI serves to align various common activities and to enable an exchange of knowledge and expertise.


ETSI and ATIS are committed to avoiding duplication of technical work and both benefit from adopting a complementary approach to the standardization process in their areas of mutual interest. The MoU’s scope includes data-sharing agreements and calls for both organizations to participate in joint meetings with the principal goal of developing and deploying nextgeneration networks.

Teledyne Completes Acquisition of Dalsa

Teledyne Technologies and Dalsa have jointly announced the successful completion of

the previously announced plan of arrangement (the “Arrangement”). The Arrangement was completed following the approval of the Ontario Superior Court of Justice (Commercial List) and satisfaction of the various conditions precedent to the Arrangement. Pursuant to the Arrangement, Teledyne acquired all of the issued and outstanding Dalsa shares for CAD $18.25 in cash for each Dalsa share. The aggregate value for the transaction is approximately CAD $337 million, taking into account Dalsa’s stock options and net cash as of December

31, 2010. In connection with the completion of the Arrangement, Dalsa Corporation was amalgamated, with the resulting entity now named Teledyne Dalsa, Inc. Full details of the Arrangement and certain other matters are set out in the management information circular of Dalsa (the “Information Circular”) dated January 5, 2011. A copy of the definitive agreement, Information Circular and other meeting materials can be found on the SEDAR website at www. sedar.com.

Digi-Key and Interlink Announce Signing of Global Distribution Agreement

Electronic components distributor Digi-Key Corporation, recognized by design engineers as having the industry’s broadest selection of electronic components available for immediate shipment, and Interlink Electronics, today announced the companies have entered into an agreement in which Digi-Key will distribute Interlink Electronics products to customers worldwide. Products from Interlink Electronics are now available for purchase on Digi-Key’s global websites. These

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at rtcmagazine.com

RTEC10 Index

52.98

209.02

Adlink Technology

1.85

1.78

1.86

22.16M

Advantech

2.82

2.78

2.86

1.00M

466.62

466.62

466.62

106.49M

7.98

7.82

8.05

144.22M

Company Market Performance

Elma Electronic Enea Interphase Corporation

5.91

5.40

6.52

40.35M

Kontron

12.00

11.86

12.11

668.37M

Mercury Computer Systems

18.53

18.51

18.84

520.30M

Performance Technologies

1.97

1.90

1.99

21.90M

PLX Technology

3.57

3.56

3.67

158.91

RadiSys Corporation

8.50

8.49

8.60

206.46M

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: www.vdcresearch.com RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities.

RTC MAGAZINE MARCH 2011

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INDUSTRY INSIDER

products will also be featured in future print and online catalogs. Interlink Electronics is the innovator of thin film Force Sensing Resistor (FSR) technology, which measures the force in diverse applications such as robotics, Smartphone user interfaces and machine control. Initially used in electronic drums and other musical instruments, FSR technology is now optimized for use in devices such as handheld gaming devices, portable media players, mobile phones, digital cameras, navigation devices and other portable electronics.

IPSO Alliance Adds Five New Members

The IPSO Alliance, the organization defining the “Internet of Things,� has announced the

addition of five industry-leading companies—BII Group (Beijing Internet Institute) at the Promoter level and AvaLAN Wireless Systems, Tritech, Synapse Wireless and Ubilogix—as Contributors, bringing its total membership to 57 members. IPSO’s growing membership signifies the worldwide interest to employ Internet Protocol (IP) for Smart Objects, allowing items ranging from appliances to factories to cars to communicate as individuals do over the Internet. “The dynamic of 57 companies collaborating together is energizing,� said IPSO’s Chairman Geoff Mulligan. “As our membership continues to expand, so does our potential to deliver innovative applications based on IP. BII Group is the first organization from China to join the Alliance, showing a vibrant worldwide in-

terest for the Internet of Things.� The IPSO Alliance is the primary advocate for IP networked devices for use in energy, consumer, healthcare and industrial applications. The IPSO Alliance is a non-profit association of more than 50 members from leading technology, communications and energy companies. Their mission is to enable the foundation for a network that will allow any sensor-enabled physical object to communicate with another, just as individuals do over the Internet. Membership is open to any organization supporting an IP-based approach to connecting smart objects. For more information, visit www.ipso-alliance.org.

Freescale MPC8536e Computer On Module The CSB1880, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, network oriented, PowerPC based Computer on a Module (COM). The CSB1880 provides a small, powerful and flexible engine for embedded Linux based GIGe networking applications of all kinds. y y y y y y y y y y

1.25GHz Superscalar e500 Core w/512KB L2 Cache 512MByte 64-Bit Wide DDR2-667 Memory with 8-Bit ECC 64MByte NOR with Secure ID, and 512MByte SLC NAND Two PCIe x4 Port (or one x4 and Two x2's) Two 10/100/1000 ports via BCM5482S to Copper/Fiber PHY Two SATA Gen 2 (1.5Gbit or 3.0Gbit/sec) Channels Three 480Mbit USB 2.0 Host Ports <7W Typical, 12W Maximum, <3W in Jog Mode 95mm x 95mm x 8mm (using 5mm COM Express Connector) Linux 2.6.x BSP with available 1 year of support

Now Available for direct order from Digi-Key The CSB1880 is manufactured in our in-house state of the art, lead-free surface mount manufacturing line. All products carry a 1-year warranty and are available in commercial and industrial temperature versions. Cogent also offers standard and custom carrier boards, plus royalty free licensing options for the CSB1880.

&2*(17 "ALWAYS COMPLETE"

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MARCH 2011 RTC MAGAZINE

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SMALL FORM FACTOR

FORUM

Colin McCracken & Paul Rosenfeld

If Memory Serves

R

andom-access memory. Can’t live with it, can’t live without it. Whether you’re developing a system around a milliwatt 8-bit micro or a 64-bit superscalar rocket with unearthly onboard cache SRAM, the system won’t boot without the DRAM that holds most of the operating system and application code. Strap it in and prepare for a wild ride. RAM comes in various flavors—soldered (on the system board), standards-based modules and proprietary modules. RAM chips themselves churn nearly as fast as microcontrollers, microprocessors and chipsets do, with production lifecycles that are much shorter. Yet RAM escapes the blame for single board computer end-of-life (EOL) notices since memory chip vendors do a thorough job of designing pin-compatible functionally equivalent replacement parts. Imagine if the CPU folks did this as a rule, not an exception. In spite of flashy names and numbers like DDR3 and 800 / 1066 / 1333, memory performance has improved incrementally each year, but has been blown out of the water by more dramatic processor performance increases. It’s no wonder that the nearly free CPU transistors have been used for every core, cache and pipeline trick under the sun to overcompensate for the root cause of throttled system performance. Single-issue 5-stage pipeline 486 processors have given way to 6-core hyper-threading multi-Gigahertz multi-headed Hydras with on-chip memory and graphics controllers and megabytes of on-chip cache that burst-fill from the DRAM spigot. All this for only a modest thermal design power (TDP) penalty. Many of the old-style integer and floating point benchmarks fit neatly into the cache so that the performance numbers keep goosing new consumer processor sales. As usual, the SFF market drafts off higher volume primary markets for standard DDR RAM modules—enterprise and consumer computers and other consumer electronics devices. But the tiniest SBCs and computer-on-modules (COMs) often don’t use SODIMMs. There is a price to pay for soldered onboard RAM in terms of size flexibility, demand forecasts and inventory—not to mention warranty and repair responsibility. But for many of these alternative products, the cost is well worth it in terms of inherent ruggedness and reliability over time in harsh environments. Extremes of temperature, humidity, corrosive chemicals, dust, shock and vibration can wreak havoc on unsuspecting

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MARCH 2011 RTC MAGAZINE

SODIMM modules that were not designed to handle them. For decades, system manufacturers and integrators in military, aerospace and transportation markets have tried to tolerate these consumer modules with plenty of epoxy (RTV) or straps or clips or brackets. Imagine the puzzled looks on the faces of RMA technicians who thought they’d seen it all. Many of these users would be willing to pay more for a rugged-by-design memory module if a suitable standards-based solution existed. Over the years, some SFF SBC manufacturers have created modules using pin-in-socket technology or even surface mount board-to-board connectors. These solutions can stand up to harsh environments almost as well as soldered RAM, and can even be conformally coated if each board is coated separately first with the connectors masked. The downside has been single sourcing of these proprietary modules. As evidence of the resilience and determination of this very fragmented embedded market, a number of companies have been collaborating on various rugged RAM solutions. The most rugged solutions involve the use of board-to-board connectors, as some OEMs are concerned that card edge gold finger-in-socket approaches are vulnerable to gradual micro-etching and contamination and have not yet been proven definitively over many years in harsh environments. Board space is so limited on SFFs; every square millimeter is used for features. Any time a connector can be eliminated means greater feature density for OEMs who need to reduce size and weight. RAM interfaces are quite wide in order to support the Gbyte/second bandwidth required—64 bits wide for x86 SBCs and 8 more lines for medical and server applications that are supporting ECC. It’s quite efficient to add four lines to a 200-pin RAM connector in order to support SATA Flash on the same module. At the other extreme, it’s not efficient to run several SATA interfaces up an entire stack of cards through multiple large board-to-board connectors. A truly rugged memory module specification from an open standards organization will be a major step forward for the high end of our market, where the full costs of “blue screens of death” and data corruption far outweigh the price premiums above consumer grade modules. So it’s time for embedded-focused RAM manufacturers to step up and serve their market by advancing the state of the art for mission-critical apps.


X-ES 2nd Generation Intel® Core™ i7 Processor Solutions: Delivering Innovation In 2010, Extreme Engineering Solutions, Inc. (X-ES) developed more Intel® Core™ i7 processor products based on VPX, CompactPCI, VME, CompactPCI Express, and XMC form factors than anyone in the industry. This year, X-ES has added solutions based on the 2nd generation Intel Core i7 processor. Providing products customers want, when they want them – that truly is innovation that performs. X-ES offers an extensive product portfolio that includes commercial and ruggedized single board computers, high-performance processor modules, multipurpose I/O modules, storage, backplanes, enclosures, and fully integrated systems. 2nd generation Intel Core i7 processor solutions available in a variety of form factors. Call or visit our website today.


ploration your goal k directly age, the source. ology, d products

editor’s report FPGA Family Spans the Spectrum

28 nm FPGA Device Portfolio Addresses Continuum of Design Requirements A set of three product families based on a new 28 nm technology offers a range of configurable and hardwired options on devices addressing applications from handheld/mobile to high-end communications in an effort to optimize power, cost and performance. by Tom Williams, Editor-in-Chief

I

n these pages we have written quite a Hardcopy technology—the ability to conbit lately about the quest for the per- vert FPGA-based designs seamlessly into fect ASIC. It is some mystical com- hard logic to create custom ASICs—and bination of programmability, hardware made it into what it calls an Embedded configurability, performance, cost, low Hardcopy Block (EHB). An EHB can power consumption and the availability coexist with an FPGA fabric on the same of good development tools. In a sense, silicon die (Figure 1). Another technology wrinkle is what the first microprocessor was the beginningsolutions of thisnow quest—an integrated circuit Altera calls partial reconfiguration, or— nies providing that could be adapted to different appli- without turning off the power to the ion into products, technologies and companies. Whether your goal is to research the latest chip—the cations bya company's virtue oftechnical writing thetheappropriation Engineer, or jump to page, goal of Get Connected is toability put you to isolate a portion of a you require for whatever type of technology, device to take it offline and reprogram it. ate code. So much has come to the party and productssince you arethen searching for. For example in a communications device, in terms of integrated periphone could add another client without takerals, hardware-defined functions, proing down other ports on the device or ingrammable logic and all the rest. Yet the terfering with ongoing network traffic. quest continues. The product/technology rollout This time it comes in the form of a consists of three families: the CycloneV rollout of three major product families from Altera that incorporate select pro- equipped with 5 Gbit/s transceivers and cess technology combinations in 28 nm, running at under 5W; the ArriaV with a 28 Gbit/s transceiver technology, new 10 Gbit/s transceivers and coming in product architectures and system IP. In at under 10W power consumption; and addition, Altera has taken its established the StratixV, which boasts the 28 Gbit/s transceivers, a clock speed of greater than 350 MHz, and what Altera considGet Connected with companies mentioned in this article. ers the “lowest power in its class.” In www.rtcmagazine.com/getconnected addition, Altera is also formally an-

End of Article

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MARCH 2011 RTC MAGAZINE Get Connected with companies mentioned in this article.

Embedded HardCopy Block

Embedded HardCopy Block

Figure 1 Embedded Hardcopy Blocks (EHBs) are areas within the FPGA fabric that can be populated with hard gates for IP that has been proven and selected for hard implementation to save power and cost, increase performance and free up logic elements.

nouncing its 28 nm HardcopyV ASIC family onto which proven FPGA designs can be fully migrated for the associated performance gains and cost/ power savings. In an effort to serve a broad range of applications that require different trade-offs of performance and power consumption, Altera utilizes the 28 nm technologies of Taiwan-based TSMC. For the 5 Gbit/s and 10 Gbit/s families, it chose the 28LP technology that optimizes for optimal power and cost, while for the 28 Gbit/s StratixV high-performance line, it chose the 28HP process technology that aims for an optimal combination of power consumption and performance speed. The 28 Gbit/s transceiver technology featured in the StratixV parts is based on a proven core transceiver design, which is also the basis of the 5 Gbit/s and 10 Gbit/s transceivers. It is optimized for optical chip-to chip communication such that a 100 Gbit Ethernet channel can be accommodated by four 28 Gbit/s transceivers for short trace connections to


editor’s report

Hard PCS Hard PCS Hard PCS Hard PCS Hard PCS

Clock Networks

Embedded Hardcopy Block

Per Channel: Standard PCS, 10G PCS, Interlaken PCS Transceiver Channels

Fractional PLLS Embedded Hardcopy Block

Core Logic Fabric

DSP Blocks M20K Blocks

DSP Blocks M20K Blocks

DSP Blocks M20K Blocks

Embedded Hardcopy Block Fractional PLLS

In order to more specifically target the classes of applications served by the three FPGA families, Altera has implemented three different flavors of on-chip memory. The CycloneV family is aimed at mobile devices like handheld projectors or video surveillance cameras that require a relatively large number of memory ports for many small buffers to handle data from things like finite impulse response (FIR) filters and things that entail wireless signals and converting them and then outputting the results. For this the CycloneV has a M10K memory to enable high buffer performance. For the mid-range ArriaV, the memory has more bits per silicone area for line cards in systems such as remote radio units or broadcast equipment or network line cards. Here a relatively large number of bits per silicon area are needed in relation to ports to store and efficiently move data packets. These mid-range devices use an M20K memory block to address their needs. Another memory block that will combine with both the M10K and M20K blocks is called the memory logic array block (MLAB), which is present in all the devices. The MLAB is a small 640-bit chunk of RAM that is sprinkled throughout the architecture to make possible small FIFOs and delay elements where needed. In terms of the external interfaces to memory, the two lower-end families have been designed with hardened interfaces to accommodate the most popular methods of accessing external memory. That is not to say that one cannot design a custom memory interface using the programmable logic, but for the sake of convenience there are pins on the chip that

Core Logic Fabric

Embedded Hardcopy Block

Tailored Memory Architectures

I/O, LVDS, and Memory Interface

Transceiver Channels Per Channel: Standard PCS, 10G PCS, Interlaken PCS

onboard optical modules. The rest of the bandwidth is used for error correction. In addition, ten 10 Gbit I/O channels can be plugged into Ethernet ports for outside communication. Backplane communications up to five feet are possible at 14.1 Gbit/s. This greatly reduces the number of traces needed for high-speed systeminternal data transfers.

Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA

(2)

I/O, LVDS, and Memory Interface

Figure 2 The example of the StratixV architecture shows that in addition to the core FPGA logic, there are variable precision DSP blocks, M20K memory blocks and embedded hardcopy blocks. In addition, the transceiver structure can support 10G ports that can aggregate to 100G external Ethernet along with 28 Gbit/s transceivers that minimize the number of traces for chip-to-chip communication (28 Gbit/s) and backplane communication (14.1 Gbit/s).

are hardware memory interfaces: 400 MHz DDR3 for CycloneV and 533 MHz DDR3 for ArriaV. On the high end, however, customers still want to roll their own although IP exists to support 800 MHz DDR3 DIMM. But, of course, there are tweaks and special tricks that vendors make at this level and want the flexibility. For instance, there is also a push to use reduced latency DRAM (RLDRAMIII) and quad data rate (QDRIII) memory to name a couple. So Altera has not created a hardened memory controller interface for the StatixV family. This means more work but the ability to put in the “special sauce” at this level. In terms of other I/O, the low-voltage (3.3V) CycloneV is tailored to support industrial Ethernet variants like EtherCAT for applications in industrial automation, while the ArriaV and StratixV have 1.25 Gbits and 1.4 Gbit/s LVDS interfaces respectively. Altera has taken the initiative

to harden some of the I/O technology in the different device families that seems to be popular, stable and appropriate to that class of device. In fact, there could be potential changes or additions to the on-chip hardened IP depending on customer demands. For Altera, this would be a straightforward matter given that they have included the EHB technology as an option in all three families. Deciding exactly what to harden and what to leave open to customer configuration can be tricky, but there are also several “no brainers.” For example in the CycloneV family, in addition to the hardened memory controller mentioned above, there is an interface for PCI Express Gen2 x1. In the ArriaV that is expanded to PCIe Gen2 x4 and triple speed (1/10/100) Ethernet (TSE). After all, nearly everybody can find a use for that! ArriaV also offers a boon to DSP designers in the form of variable precision DSP. That means that beyond the RTC MAGAZINE MARCH 2011

13


editorâ&#x20AC;&#x2122;s report

typical (and popular) 18 x 18 element multiplier, one can choose different levels of precision such as 9 x 9, 27 x 27 or even 54 x 54. All these elements can be incorporated into the device architecture in addition to the core FPGA fabric to enhance the options for the developer (Figure 2). In the StratixV family, the PCIe hard offering goes up to PCIe Gen3 x8 along

with 100 Gbit/s Ethernet. In addition, there is a hardened IP block for the Interlaken high-speed chip-to-chip protocol, which is quite logic-intensive, and having it in hardened logic not only offers cost and performance benefits but also takes up far less die area leaving room for more programmable logic elements. Finally, the advent of the Hardcopy technology in both full custom ASIC

form and in EHB form gives designers a host of options. One can order parts with certain other, often proprietary IP in EHBs once the volume and acceptance of a product makes it economical, yet one can with this option also retain the option to implement certain and even newer ideas in the programmable fabric of the device. Or, once volume and business model dictate, one can order a full custom ASIC that takes a proven FPGA design and delivers it in the form of a whole 28 nm, 500 MHz IC with 14.1 Gbit/s transceivers. The partial reconfiguration option also allows those who have programmed their original designs to allow for it, to add or change programmed IP with the chip in circuit and with other elements on it running. The emphasis here is that the design must be able to accommodate the reconfiguration option in advance by reserving programmable fabric in a useable manner. So the lesson here is that there may not be one single device that is the ultimate ASIC, but there could well be a family of devices that shares technology, architectures and features in a continuum that lets designers pick the appropriate variant to meet their needs and to move easily up and down the line of capabilities using a uniform set of design toolsâ&#x20AC;&#x201D;in this case the Quartus II suite and others to comeâ&#x20AC;&#x201D;to get closer to that elusive grail. Altera San Jose, CA. (408) 544-7000. [www.altera.com].

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Technology in

context

Configurable and Programmable Devices

Configurable and Programmable: The Sweet Spot for the SoC Getting CPU cores to work smoothly with FPGAs poses some serious challenges in order to bring out the complementary advantages of both. Once an optimal architecture has been achieved, the issue of a comprehensive tool chain must be solved as well. by J  amie Brettle, National Instruments and Greg Brown, Xilinx

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MARCH 2011 RTC MAGAZINE

Sensors

Flash

FPGA CPU Core

MemC

Interconnect Custom Logic

Peripherals

Memory ASP

MPU/ Programmable Logic MCU

Displays

FPGA Displays

MPU/MCU ASSP

Memory

Flash

Communications

Communications

Displays

Memory

Communications

Flash

Communications

T

he February issue of RTC included the article titled, “MPUs Team with FPGAs to Solve Real-Time System Requirements,” a brief history of how FPGAs have evolved and how the programmable logic fabric can be used alongside either a dedicated microprocessor or a processor integrated into the FPGA. We will now build on this topic by discussing the three primary architectures and their respective programming challenges, and explain how designers can use tools like National Instruments’ LabView to address such challenges for various classes of users and applications. Architectures that combine the CPU with an FPGA are widely used in a number of applications and in almost every technology market. There are three basic implementations of this architecture in use today: (1) discrete MPU/MCU + FPGA, (2) soft or hardened CPU core embedded within an FPGA and (3) what has been called the Application Services Platform (ASP), a hybrid programmable, configurable, customizable part that combines a hardwired system-on-chip (SoC) with programmable logic in a single device.

Sensors

Peripherals

Discrete + FPGA

Sensors

Peripherals

CPU in FPGA

Sensors

Peripherals

Applications Services Platform (AS)

Figure 1 Basic CPU + FPGA Architectures.

Programming Challenges

Each of these architectures has programming challenges, mostly involving how each architecture handles communication between the CPU and the FPGA and in turn, the rest of the system. In the Discrete + FPGA architecture, the fact that an MPU, MCU or ASSP has been extended with an FPGA, can be the most challenging from a software development perspective. Typically, the interfaces available are limited to low-speed serial or parallel links, such as a general-purpose memory controller, or to the higher-speed

but power-hungry PCI Express. Partitioning the design must be well thought through to account for shared memory accesses, control and data passing, and so on. In addition, the types of hardware IP put into the FPGA and their interfaces can vary greatly, which affects whether and how software can access and utilize them. For these reasons, the programming model can be very different from one implementation to the next. Partitioning and programming must be well documented in order for each side to understand how the system can most effectively communicate. Debugging can be a challenge, but tools


technology in context

such as the FPGA Dynamic Probe (Agilent) or FPGAView (Tektronix)â&#x20AC;&#x201D;combined with a mixed-signal oscilloscope and logic analyzersâ&#x20AC;&#x201D;help address this task by providing visibility into each primary component. Standard board support packages (BSPs) are usually available for the discrete part, but the BSP may need to be extended in-house for the FPGA portion. Overall, the main challenge lies in the programming model, which is implementation dependent and left up to the development team to define, document and realize. The architecture that embeds a CPU inside an FPGA provides the most flexibility as well as the most variability during the development cycle, which can be problematic for software development. Hardware development teams begin with a nearly bare CPU core and build a complete custom processing system from a set of vendor-supplied, third-party and custom cores. This flexibility can have an impact on the software development as the hardware platform is more dynamic and can be easily changed. After the custom processing system is built, the software teams can access the platform for their development. Interfacing standards were previously largely vendor dependent until the recent introduction of version 4 of the Advanced Microcontroller Bus Architecture specification: AMBA 4. Unfortunately, programming models can be inconsistent unless an interfacing standard is utilized, and the need to apply an FPGA programming file before the processing system can boot creates a system-level paradigm shift. Debug uses traditional software tools over JTAG and trace ports, combined with embedded logic-analyzer capabilities such as ChipScope from Xilinx and Alteraâ&#x20AC;&#x2122;s SignalTap. In general, the availability of BSPs is much more limited for this type of architecture. Design teams will have to customize most of them in-house. Finally, various forms of the ASP architecture are being introduced to the market to address the limitations of the Discrete

NI RIO Hardware Real-Time OS Processor NI LabVIEW Programming Interface Library

C Language Programming Interface Library

DMA Interrupt, Bus Control Drivers

Xilinx FPGA NI LabVIEW FPGA Programming Interface Library

Onboard Processor Peripheral Drivers Hardware Startup Drivers

NI C Series I/O

Onboard I/O Module I/O Drivers Custom I/O

Figure 2 The NI RIO architecture enables high-performance deterministic operation by pairing a real-time processor with programmable FPGA fabric.

+ FPGA and CPU-in-FPGA architectures. The system paradigm is addressed with a complete, hardwired processing system that is mostly ARM-based and boots at power-up. Also, the interfaces to the programmable hardware are well-defined and based on the AMBA standard. Therefore, software can access the hardware modules in the programmable hardware using a standard interface with a consistent memory-mapped programming model. Hardware IP development is assisted by utilizing these standard interfaces, making this a more viable choice for ecosystem development of IP as well. Examples of this architecture include the MCU-class Cypress Semiconductor PSoC and Microsemi SmartFusion families, and the newly announced Zynq EPP (Extensible Processing Platform) family from Xilinx, which is an applications-processor or MPU class device. Debug is well-supported for all these devices due to widespread industry support for the ARM platform. Some of the vendors supply embedded logic analyzers for the programmable hardware. Though BSP availability varies, vendors can more easily create a standard BSP to support the hardwired MPU/MCU portion. The common programming model makes it possible for BSP extensions to account for the application-dependent portion in the programmable logic.

A consistent theme among these three architectures is that hardware configuration or customization presents the key challenge to the programming paradigm. In addition, the selected architecture has a primary impact on the programming model for both the software and hardware development teams.

Development Team Challenges

As the tools necessary to develop these heterogeneous systems and SoCs become more varied, so too do the teams required to build the hardware platform and to develop the software. These teams often have a combination of analog and digital engineers, firmware and application developers, and DSP designers, all working in tandem on different aspects of the system. After factoring in resources from sales, marketing and operations, even small teams working on embedded systems can potentially have more than 10 individuals contributing different input into the development process. Because of the large and varied number of voices making themselves heard, teams need to put methodologies into practice to ensure efficient collaboration among all parties. Unfortunately, as nearly all engineers have experienced, even the best methodologies can be rendered useless because of the failure to RTC MAGAZINE MARCH 2011

17


technology in context

tions have been developed for either fixed hardware platforms, single cross-platform software solutions or both.

Managing Configurable and Programmable Designs

Figure 3 LabView uses graphical programming to develop code for both processors and FGPAs.

effectively communicate. For example, if digital engineers working on FPGA designs, using VHDL, change the interfaces to data registers, it will affect the developers creating C-based applications on the processor, which is dependent on pulling data from the FPGA. If this process is not sufficiently communicated, the result will be bugs that are often difficult to track because each engineer is using a different set of programming tools to develop their portion of the application. The programming languages, tools and methodologies are, of course, different for the hardware and software development. HDLs are the dominant language on the hardware end, just as C dominates the software side. System-level modeling tools provide an opportunity to do system simulation in a single environment. There are various flavors available such as UML, System-C, etc. and different levels of modeling such as transaction, behavioral and cycle-accurateâ&#x20AC;&#x201D;each with their various advantages and disadvantages. The system model can then be decomposed into the appropriate language and

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MARCH 2011 RTC MAGAZINE

abstraction level for implementation. Additionally, code-generation tools exist for software and hardware, with prospective advantages and disadvantages. To get the most in terms of performance, code density and area utilization in hardware requires hand-tuning. Programmable and configurable systems provide design teams with incredible flexibility, allowing them to handle change requests from customers, competitive pressures or new industry standards by adapting either the software design or the FPGA logic. Feature requests and specification changes can often come late in the development cycle, leaving engineers scrambling to meet the design goals. By creating designs featuring SoC coupled with FPGAs, engineers provide greater flexibility out of the existing board-level components. However, they must make a trade-off between this flexibility and the need to manage the design process while requirements are in flux. To solve the issues associated with varied team member skill sets, differing development tools and late-stage feature changes, several solu-

A growing trend by commercial offthe-shelf (COTS) manufacturers is to create an embedded system that combines a processor and FPGA into an offering that can be used to either prototype a final system or act as the final product, speeding up the start of software development. Combining COTS platforms with software tools that simplify digital design and software development can make configurable and programmable systems much easier to manage and collaborate on. A case study for this approach is found with the National Instruments Reconfigurable I/O (NI RIO) architecture built around the combination of a discrete processor (x86 or PowerPC) running a real-time operating system, a Xilinx FPGA and hot-swappable I/O that is connected to the processor through the FPGA. To facilitate communication between components, NI developed discrete ASICs and driver technology that enable direct memory access to the processor from the FPGA. The NI RIO architecture is the heart of a number of prototyping and deployment platforms meant for embedded systems development. In the future, ASP devices are a natural evolution for the NI RIO architecture to utilize as they enable smaller, lower-cost and lowerpower implementations (Figure 2). In addition to the NI RIO hardware architecture, over the past 25 years NI has developed the LabView graphical programming environment. LabView is used by engineers and scientists to develop sophisticated measurement, test and control systems using intuitive graphical icons and wires that resemble a flow chart. Figure 3 illustrates how LabView programming is performed by wiring together graphical icons on a diagram and directly compiling it to machine code, so that the computer processors can execute it, or to an intermediate VHDL for FPGAs. The wires indicate the flow of data in a program in between functions that will process the incoming data. While represented graphically instead of with text, LabView


technology in context

contains the same programming concepts found in most traditional languages. For example, LabView includes all of the standard constructs, such as data types, loops, event handling, variables and recursion. Because LabView can generate either machine code or VHDL, it has the ability to program processors running in real time as well as FPGAs using the same environment. As a result, engineers only need to learn a single tool to develop code to execute on a heterogeneous processor-plusFPGA system. This can facilitate easier communication among teams, since the engineers are developing their systems using a single collaborative environment, reducing the need for disparate tool chains. Additionally, because of the portability of LabView code from processor to FPGA, an engineer can take advantage of highperformance FPGA fabric without being a digital designer. Ultimately, the underlying architecture is abstracted, whether it is the Discrete + FPGA, CPU-in-FPGA or ASP approach. This can potentially reduce the number of engineers required to create embedded systems by allowing engineers to do more with the tools they are familiar with. By applying correct-by-construction development, engineers can ensure the correct behavior of their system. Alternatively, several other approaches allow engineers to use high-level tools to program FPGAs. Electronic system-level (ESL) design is a methodology focused on using higher-level abstraction to develop a system. This allows engineers to model their entire system using programming languages such as C or C++. By using these tools, software developers, who may have little formal training designing digital circuits and working with hardware description languages, can now use programming tools they are familiar with to develop algorithms that run on processors or FPGAs. Much like the LabView approach, ESL methodology can potentially accelerate development by consolidating development languages and environments in order to ease communication among team members. By combining processors and FPGAs, engineers have the processing capabilities to not only create powerful systems but to also quickly adapt to changing requirements.

However, along with these processing powerhouses come technical and managerial challenges. Using tools that provide high-level hardware abstraction can shield users from the low-level technical details and open up these technologies to scientists, technicians and engineers who lack digital hardware experience. As architectures containing processors and FPGAs evolve and become more prevalent, it will be important that the tool chains needed to develop applications also

continue to evolve, taking a holistic systemlevel approach to software development. National Instruments Austin, TX. (512) 794-0100. [www.ni.com]. Xilinx San Jose, CA. (408) 559-7114. [www.xilinx.com].

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Untitled-8 1

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ploration your goal k directly age, the source. ology, d products

Technology

connected Security for Networked Devices

Securing Your Embedded Designs: Encryption and Authentication ‘Keys’ to Success Among the many facets of implementing networked device security are encryption and authentication. Careful attention to these aspects is essential to a comprehensive security strategy.

Daryl R. Miller, Lantronix

W

By virtue of their application, embedhile the world has focused on ded devices are expected to have a much providing better security for higher reliability and require lower mainservers and desktop computers, tenance than most other computing sysembedded systems have often been overtems. As embedded computers move from looked. As embedded devices are used to the realm of autonomy to members of a handle sensitive data and find themselves much larger, interconnected community, attached in some way to a broader infrasecurity concerns have escalated. structure, the need for advanced security One major security issue stems from in this area is imperative. Several high the fact that some common communicaprofile incidents nies providing solutions now have increased awareness tion protocols were not designed with seand sensitized developers to this need. ion into products, technologies and companies. Whether your goal is to research the latest curity in mind. In to most embedded ation Engineer, or jump a company's technicalapplications, page, the goal ofseGet Connected is to put youIn fact, the TCP/IP proyou require for whatever type of technology, curity should be a core consideration. tocol suite, which is very widely used, and productsProper you are searching for. implementation can improve sys- has some major security flaws inherent tem robustness, reliability and even open in the protocol. Some of these flaws exist up new avenues of product application. because hosts rely on IP source addresses Implementing security measures in an for authentication. Wireless communications is anembedded system has a number of chalother area of great security concern due lenges. System resources such as memory, to the openness of the communication processing power and battery life are ofvehicle. For example, technologies like ten limited. Time-to-market and overall cost concerns may limit how much can be 802.11 and Bluetooth are appealing not only to consumers but cyber-criminals implemented. as well. Even wireless standards where encryption was originally considered like IEEE802.11 with Wired EquivaGet Connected with companies mentioned in this article. lent Privacy (WEP) standard have been www.rtcmagazine.com/getconnected cracked and exploited necessitating

End of Article

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MARCH 2011 RTC MAGAZINE Get Connected with companies mentioned in this article.

stronger security methods (Wi-Fi Protected Access (WPA), 802.11i, WPA2 Personal and WPA2 Enterprise). What specific measures should an embedded developer consider in order to create a secure product? What are the limitations that can be anticipated when implementing a particular security feature? A good place to start (but definitely not finish) is data encryption.

Encryption Overview

Encryption plays a vital role in the overall security puzzle. It is instrumental in safeguarding private information and is undoubtedly an efficient method to ensure the safety of business and personal data. In its simplest terms, encryption is the translation of data into a secret code. To read an encrypted file, you must have access to a secret key or password that enables you to decrypt it. Modern encryption is achieved using algorithms with a “key” to encrypt text or other data into digital nonsense and then decrypt it by restoring it to its original form (Figure 1). Encryption algorithms protect data from intruders and make sure that only


technology connected

the intended recipient can decode and read the information. Each algorithm uses a string of bits known as a key to perform the calculations. The larger the key (the more bits in the key), the greater the number of potential combinations that can be created, thus making it harder to break the code and unscramble the contents. While encryption is one of the best and most popular ways to protect data on both embedded and desktop platforms, it incorporates some unique challenges to an embedded developer who might be restricted by memory resources and processing power. Each encryption algorithm should be selected based on the amount of security that is needed in conjunction with the amount of memory and processing power at the developer’s disposal. Consider an example where a steady stream of high rate unencrypted data is being encrypted by the processor. If the encryption method is CPU intensive due to the algorithm or the key length, other vital processes could be starved or data could be lost depending on the architecture. The upside of long keys is that they make it more difficult for an unintended user to decipher the data. For example, using the now industry standard 128-bit encryption key, it would be 4.7 sextillion (4,700,000,000,000,000,000,000) times more difficult than cracking a 56-bit encryption key. Given the current power of computers, a 56-bit key is no longer considered secure whereas a 128-bit key is. While a longer encryption key provides better protection, the embedded developer must keep in mind that it will also require more processing power to encrypt and decrypt data. When public key encryption is implemented on a large scale, such as a secure Web server, a digital certificate is required. A digital certificate is information that says that the Web server is trusted by an independent source known

Public Key Encryption Step 1: Give your public key to sender

Step 2: Sender uses your public key to encrypt the plain text

plain text

Step 3: Sender gives the ciphertext to you.

ciphertext

encryption

ciphertext

Step 4: Use your private key (and passphrase) to decrypt the ciphertext.

plain text

ciphertext decryption

Figure 1 Public key encryption can be described in four steps. First, give your public key to sender. Next, the sender uses your public key to encrypt plain text. After that, the sender gives you the ciphertext. Lastly, you use your private key (and passphrase) to decrypt the ciphertext.

as a certificate authority. The certificate authority acts as a middleman that both computers trust, and confirms that each computer is in fact who it says it is, and then provides the public keys of each computer to the other. Shared secrets are the most common security method for accessing confidential information. A shared secret is something known to both the user and the holder of the confidential information. The most common shared secrets are a user ID and password. These shared secrets allow the user to log into the site of the holders of confidential information such as financial institutions or online merchants. Shared secrets should be unique, and should be changed periodically in order to ensure continued security. All of these requirements add up to a fairly substantial task to provision and manage shared secrets for encryption.

Types of Encryption

There are many algorithms for encrypting data based on these types. Some of the most common are: • Data Encryption Standard (DES)— uses a 56-bit key to encrypt the data. DES is now considered to be insecure for many applications. This is chiefly due to the 56-bit key size being too small; DES keys have been broken in less than 24 hours. • Triple DES (3DES)—uses three successive DES operations to provide stronger encryption than DES. The algorithm is believed to be practically secure, although it is theoretically susceptible to some attacks. In recent years, Triple-DES has been superseded by the Advanced Encryption Standard (AES). • Advanced Encryption Standard (AES)—also known as Rijndael, can use 128, 192 or 256 bits to enRTC MAGAZINE MARCH 2011

21


technology connected

crypt and decrypt data in blocks of 128 bits. AES encryption is often a popular standard for embedded devices because it can run on very low level hardware and often can be implemented in less than 64K of code space. As mentioned, AES serves as a replacement for DES. DES has been cracked and declared no longer suitable for securing sensitive data. In 1997, the National Institute of Standards and Technology (NIST) started its effort to develop the AES. It brought together researchers from 12 countries who submitted encryption algorithms. Fifteen different formulas were “attacked” for vulnerabilities and evaluated by the worldwide cryptographic community. The winning algorithm was finally selected in October 2000. It incorporates the Rijndael encryption formula developed by two Belgian cryptographers, Vincent Rijmen and Joan Daemen. The final standard was published in December 2001. Rijndael (aka AES) is internationally accepted as a standard method of encryption for storing and transmitting data (Figure 2). It can also be implemented in a small amount of space, and can be run on a 16-bit, or even 8-bit processor, making it a very good choice for embedded applications. It is estimated that it would take a computer typing 255 keys per second approximately 149 trillion years to crack the AES code. In addition to the increased security that comes with larger key sizes, AES can encrypt data much faster than Triple-DES.

Authentication

Today’s networks are no longer isolated from outside intrusion and threats. Encryption protects data in storage and in transit. But it does not have the capability to validate and separate authorized users from potentially malicious ones. Authentication, which involves verification of the user’s identity, is a fundamental concern when it comes to the security of a device. Authentication is often the first line of defense against an attack. Authentication relies on something that

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MARCH 2011 RTC MAGAZINE

Encryption Time Comparison 450

clocks per byte

400 350 300 250 200 150 100 50 0 AES/ Rijndael

TwoFish

DES

Figure 2 In 1976, the DES (Data Encryption Standard) was selected as an official Federal Information Processing Standard (FIPS) and used a 56-bit encryption key to protect data. In 2001 the AES (Advanced Encryption Standard) / Rijndael was adopted by the U.S. government and uses a 256-bit encryption key. Rijndael was selected as the standard against 15 competing designs, including Twofish, which also uses uses a 256-bit encryption key.

the user has or knows which can be compared to a known constant. This “something” has to be unique, and either secret (like a password), or sufficiently complex to be almost impossible to forge, such as a retina, fingerprint, handprint or other unique identification. Authentication also can occur by proxy, such as a stored authentication token embedded in the user’s workstation memory, or on a smart card. In many cases authentication is not a high priority for embedded development because often times the assumption is made that whoever has physical possession of the embedded device has the right to utilize its functionality. As more and more embedded devices take hold in our everyday lives, user authentication will become more of a necessity. Each authentication method has strengths and weaknesses. Passwords are

considered the weakest because they can be shared or stolen. Complexity rules are largely unenforceable and modern browsers offer the “convenience” of remembering user passwords. Although attempts have been made to strengthen passwords by disallowing simple words, users are ingenious at finding ways around stronger password rules. While an attacker can attempt to crack passwords using the entire password space, an attack that utilizes words from a dictionary is faster because the number of dictionary words and combinations make a far smaller number than every possible character combination. Using a unique username / password combination can make a device harder for an attacker to exploit. For example, if the attacker knows a valid username (something like ‘admin’ is common on most home DSL / Cable routers), they will only need to devise a method to check that specific username against a number of passwords. If the attacker is forced to guess the username and password, the amount of attempts needed to do so will increase exponentially. To prevent novice hackers from gaining access to your computer or files, experts recommend using complicated passwords. There are many utilities that rate the strength of a password. It is good for a developer if given enough space and a visual interface, to coach the user to enter a strong password. Secure Sockets Layer (SSL) and Secure Shell (SSH) are two protocols that are used to provide secure communications over the Internet, as well as authentication. Both SSL and SSH have become extremely important to overall network security by maintaining strict authentication for protection against intruders as well as symmetric encryption to protect transmission of data. As processing power and memory density increase, SSH and SSL are showing up more regularly in embedded systems. While they work to provide similar security parameters, it is important to note that they are not identical in approach and application. SSL is a protocol that provides encryption services between a Web server and a Web browser using public-key cryptography. This protocol was basically designed


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to secure Web sessions among users via encryption and requires an application to drive it. SSLâ&#x20AC;&#x2122;s easy implementation as a drop-in solution makes it popular among designers looking for a quick solution. In contrast, SSH is a program that provides strong authentication and secure communications over unsecured channels. SSH can accomplish much more than SSL, essentially providing a secure tunnel between users. It is used as a replacement for Telnet, rlogin, rsh, and rcp, tools used to log into another computer over a network, to execute commands in a remote machine and to move files from one machine to another. SSH also supports AES as one of its many encryption algorithms. Once a session key is established, SSH uses AES to protect data in transit. Using authentication in conjunction with encryption can provide a high level of security against low level attacks. But as computers advance in technology, so does the technology that attacks them. Often attackers will use scripts, or well known holes in applications to exploit a system, bypassing authentication all together. A system that is designed from the beginning with security in mind will provide a good platform for added authentication and encryption. Encryption is an important part of an advanced security strategy. Encryption algorithms like Triple-DES and AES are some of the best and most popular ways to protect data in embedded products. It is important to understand, however, that incorporating encryption presents unique challenges in the form of memory resource restrictions; it can also be very processor intensive. In addition to encryption there is a group of very useful tools for adding security. Authentication can provide a defense against many attacks. To strengthen security even further, SSL and SSH are recommended for certain embedded applications. Encryption and authentication are most effective when used in conjunction with a hardened OS and TCP stack that has been developed and tested with security precautions in mind. All of these things will provide a secure perimeter between the non-secure application software, the secure applica-

tion software, and potential threats to your embedded device. It is crucial to integrate security in embedded devices. Today, embedded engineers are faced with new and increasing security challenges. Looking beyond just encryption, designing for advanced security requires consideration of authentication, hardened operating systems and testing specifically

Untitled-2 1

for security. A design philosophy with advanced security as a key factor will enable systems to be more robust, ensure greater reliability and provide new embedded design opportunities. Lantronix Irvine, CA. (949) 453 3990. [www.lantronix.com].

23

3/8/11 10:59:26 AM RTC MAGAZINE MARCH 2011


ploration your goal k directly age, the source. ology, d products

Technology

connected Security for Networked Devices

Security Considerations in Embedded I/O Virtualization As embedded hypervisors continue to grow in popularity across a variety of industries and applications, one of the biggest impacts on security and efficiency is the approach to managing I/O across virtual machines. by David Kleidermacher, Green Hills Software

I

n any embedded system, there is in- graphics and threadsâ&#x20AC;&#x201D;are proving inevitably a need for sharing a limited sufficient for emerging embedded apset of physical I/O peripherals across plications. In particular, developers workloads. The embedded operating need the flexibility of abstracting the system provides abstractions, such as OS itself. The networking example of layer 2/3/4 sockets, for this purpose. OS control and data plane workload conabstractions free developers to focus on solidation, with a Linux-based control plane and a real-time OS data plane, differentiation. Over time, this abstraction has is but one use case. Applications with grown dramatically up the stack. Instead mixed levels of criticality are becoming nies providing solutions now of simply providing a TCP/IP stack and the norm. A general-purpose operating ion into products, technologies and companies. Whether your goal is to research the latest system iswith sockets, operating ation Engineer, or jump to aembedded company's technical page, the systems goal of Get Connected to put its you sophisticated middleware and open source software availmust provide full suite of Web protoyou require for whatever type ofatechnology, and productscols you are searching for. ability is being combined with safety, and remote management functions. availability, security and/or real-time Furthermore, as SoCs become more cacritical applications that need to stay pable, application and real-time workisolated from the general-purpose enloads are being consolidatedâ&#x20AC;&#x201D;so the OS vironment. must provide a plethora of communicaThis evolution requires that system tions, management and HMI services software, in particular the virtualization while responding instantly to real-time layer, adapt to its new role of securely events and protecting sensitive I/O intermanaging I/O below and on behalf of faces from corruption. The typical OS abstractionsâ&#x20AC;&#x201D; the guest operating systems. Arguably files, devices, network communication, the most difficult challenge in embedded virtualization is the task of allocating, protecting, sharing and ensuring the effiGet Connected with companies mentioned in this article. ciency of I/O across the virtual machines www.rtcmagazine.com/getconnected and applications.

End of Article

24

MARCH 2011 RTC MAGAZINE Get Connected with companies mentioned in this article.

Methods of Virtualization

The traditional method of I/O virtualization is emulation: all guest operating system accesses to device I/O resources are intercepted, validated and translated into hypervisor-initiated operations (Figure 1). This method maximizes reliability, security and shareability. The guest OS can never corrupt the system through the I/O device because all I/O accesses are protected via the trusted hypervisor device driver. A single device can easily be multiplexed across multiple virtual machines (VMs), and if one VM fails, the other VMs can continue to utilize the same physical I/O device, maximizing system availability. The biggest drawback is efficiency; the emulation layer causes significant overhead on all I/O operations. In addition, the hypervisor vendor must develop and maintain the device driver independent of the guest OS drivers. In contrast, a pass-through model (Figure 2) gives a guest operating system direct access to a physical I/O device. Depending on the CPU, the guest driver can either be used without modifica-


technology connected

tion or with minimal paravirtualization. A single device can be shared between multiple guests by providing a virtual I/O interface between the guest that owns the physical device and any other guests that require access to that device. For network devices, this virtual interface is often called a virtual switch (layer 2) and is a common feature of most hypervisors. The pass-through model provides improved efficiency but trades off security: an improper access by the guest can take down any other guest, application, or the entire system. This model violates the primary security policy of system virtualization: isolation of virtual environments for safe coexistence of multiple OS instances on a single computer. If present, an I/O memory management unit (IOMMU) enables a passthrough I/O virtualization model without risking direct memory accesses beyond the virtual machineâ&#x20AC;&#x2122;s allocated memory. IOMMUs are becoming increasingly common in embedded microprocessors, such as Intel Core, Freescale QorIQ and ARM Cortex A15. As the MMU enables the hypervisor to constrain memory accesses of virtual machines, the IOMMU constrains I/O memory accesses (especially DMA), whether they originate from software running in virtual machines or the external peripherals themselves. The IOMMU model enables excellent performance efficiency with increased robustness relative to a pass-through model without an IOMMU. However, IOMMUs are a relatively new concept, and a number of vulnerabilities (ways to circumvent protections) have been discovered and must be worked around carefully. In most vulnerability instances, a faulty or malicious guest is able to harm security via device, bus, or chipset-level operations other than direct memory access. Researchers at Green Hills Software, for example, have discovered ways for a guest OS to access memory beyond its VM, deny execution service to other

Hypervisor

Hypervisor Driver NIC

NIC

Hypervisor

Figure 2 I/O virtualization using passthrough to guestâ&#x20AC;&#x201D;no hypervisor drivers needed.

NIC

Figure 1 I/O virtualization using emulation implemented with hypervisor device drivers.

Virtual Device Driver

Virtual Device Driver Thread

Virtual Device Driver

Virtual Device Driver Thread

Virtual Device Driver Thread

Mapped Video RAM

I/O Device API Microkernel

ISR

ISR

ISR

Figure 3 User-mode virtual device driver processes.

RTC MAGAZINE MARCH 2011

25


technology connected

Main Memory

Linux Physical Addresses IOMMU

Data Plane Driver

MMU

Data Plane Driver

Data Plane Driver

RTOS-Hypervisor core

Device

Data Plane Driver

core

core

core

core

core

core

core

CPU Figure 5

Device Addresses

Virtual Addresses

Figure 4 IOMMU for improved device driver architecture and robustness.

VMs, bluepill the system hypervisor, and take down the entire computerâ&#x20AC;&#x201D;all via IOMMU-protected I/O devices. For high reliability and/or securitycritical applications, the IOMMU must be applied in a different way than the traditional pass-through approach where the guest OS has unfettered access to the I/O device. Consult your hypervisor vendor to understand the myriad tradeoffs and options for use of the IOMMU and I/O virtualization in general. A major downside of a pass-through approach (with or without the IOMMU) is that it prevents robust sharing of a single I/O device across multiple VMs. The VM that is assigned ownership of the passthrough device has exclusive access, and any other VMs must depend upon the owning VM to forward I/O. If the owning VM is compromised, all VMs shall be denied servicing for that device. This deficiency has lead to emerging technologies that provide an ability to share a single I/O device across multiple guest operating systems using the IOMMU and hardware partitioning mechanisms built into the device I/O complex (e.g., chipset plus the peripheral itself). One example of a shareable, IOMMUenabled, pass-through device is an Intel processor equipped with Intel VT-c (Virtualization Technology for Connectivity) coupled with PCI Express Ethernet cards implementing Single-Root I/O Virtualization (SR-IOV), a PCI-SIG standard. With such a system, the hardware takes care of providing independent I/O resources, such as multiple packet buffer

26

MARCH 2011 RTC MAGAZINE

Linux and real-time data plane partitioning using microkernel-based virtualization.

rings, and some form of quality of execution service amongst the VMs. This mechanism lends itself well to networking devices such as Ethernet, Rapid I/O and Fibre Channel; however, other approaches are required for secure, independent sharing of peripherals such as graphics cards, keyboards and serial ports. Nevertheless, it is likely that hardware-enabled, IOMMUprotected, VM-shareable network device technology shall grow in popularity across embedded processors.

Virtual Device Drivers

Device drivers are frequently the cause of system reliability problems. For example, monolithic operating systems commonly install device drivers into the kernel where a faulty device driver can suffer a buffer overflow attack in which malware overwrites the runtime stack in order to install code into the kernel. User-mode device drivers, often called virtual device drivers, prevent these types of attacks because an infiltrated device driver can only harm the process containing the driver, not the kernel itself. In order to facilitate the development of virtual device drivers, the operating system needs to provide a flexible mechanism for I/O control to the virtual driver process. The virtual driver, however, need only be provided access to the specific device resources that the driver requires to achieve its intended function (Figure 3). As seen in Figure 3, the ideal virtual device driver requires very little devicespecific code to reside within the supervisor-mode kernel: the interrupt service routine (ISR) and, in the case of network

devices, access to direct memory access (DMA) programming registers. The ISR must be in the kernel while the interrupt vector is executed by the hardware in supervisor mode. The DMA programming is often kept in the kernel because the operation must be trusted: access to DMA registers enables the driver to overwrite any physical memory location, even the kernel itself. The user-mode approach reduces the privilege of the device driver so that it is critical only for the I/O operations pertaining to its managed device and cannot impact any other device, application, or the kernel. While a historic argument against virtual device drivers has been performance, the combination of hardware improvements and the ability of modern real-time kernels to optimize context switch and system call servicing times have demonstrably removed this barrier. Unfortunately, the virtual driver approach still leaves a bit of device-specific code in the kernel. For improved maintainability and a cleaner architecture, it would be better if the DMA programming could reside in user-mode without increasing the driverâ&#x20AC;&#x2122;s privilege. An IOMMU enables the DMA programming to reside in the virtual device driver. Figure 4 depicts the combination of an MMU and IOMMU protecting accesses to memory originating from either CPU-based applications or from network devices. Perhaps most importantly, by enabling direct access to memory mapped device registers and DMA programming, the IOMMU promotes a purer form of virtual device driver architecture without sacrificing performance efficiency.


technology connected

Virtual device drivers are commonly employed by microkernel-style operating systems. Thus, microkernel-based hypervisors are well suited to secure virtualization. Instead of the typical monolithic approach of placing device drivers into the hypervisor itself or into a specialpurpose Linux guest operating system, the microkernel-based hypervisor uses small, reduced-privilege, native processes for device drivers, I/O multiplexors, health managers, power managers, and other supervisory functions required in a virtualized environment. Each of these applications is provided only the minimum resources required to achieve its intended function, fostering secure embedded system designs. Figure 5 shows the system-level architecture of a microkernel-based hypervisor used in a multicore networking application that must securely manage Linux control plane functionality alongside high-throughput, low-latency data plane packet processing within virtual device drivers. Without virtualization, the application in Figure 5 could be implemented with a dual Linux/RTOS configuration in which the control and data plane OSs are statically bound to a set of independent cores (an Asymmetric Multiprocessing, or AMP, approach). One advantage of virtualization over an AMP division of labor is the flexibility of changing the allocation of control and data plane workloads to various cores. For example, in a normal mode of operation, the architect may only want to use a single core for control and all other cores for data processing. However, the system can be placed into management mode in which Linux needs four cores (SMP) while the data processing is temporarily limited. The virtualization layer can handle the reallocation of cores seamlessly under the hood, something that a static AMP system cannot support. Security can also be improved by adding applications, or even separate virtual machines (called virtual appliances), which perform a dedicated security function such as anti-malware or firewalling. Increases in software and system complexity and connectivity are driv-

ing an evolution in how embedded systems manage I/O and in the architecture of the OSs and hypervisors that are responsible for ensuring their security. The combination of a reducedprivilege, component-based design as well as intelligent I/O virtualization to enable secure consolidation without sacrificing efficiency will remain a focus of systems software suppliers in

Untitled-5 1

meeting the flexibility, scalability and robustness demands of next-generation embedded systems. Green Hills Software Santa Barbara, CA. (805) 965-6044. [www.ghs.com].

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2/17/09 4:47:07 PM RTC MAGAZINE MARCH 2011


technology in

systems Optimizing Energy Use

28

MARCH 2011 RTC MAGAZINE


tech in systems

Managing Energy Savings in Real Time The use of power-aware MCU features along with poweraware software and development tools can lead to significant optimization of low power consumption.

Raman Sharma, Energy Micro and John Carbone, Express Logic

P

icking the right microcontroller and development environment for applications that need to support many years or even decades of operation off a battery is not easy. A real-time operating system can take away issues with asynchronous task handling and improve power management. And the latest development tools make it easy to perform real-time debugging of application code to expose energy bugs. Still, the biggest challenge remains in finding the correct microcontroller in a steadily increasing “ultra low power microcontroller” market. The ARM Cortex-M3 architecture released a wave of new silicon vendors. Although a dramatic step up from 8- and 16-bit performance, the new 32-bit CPU immediately found itself surrounded by legacy peripherals incapable of meeting energy conscious requirements. For a host of battery-powered applications and energy-sensitive products in sectors such as metering, medical devices, wireless communication and security equipment, more advances in MCU design and development tools are needed to meet energy efficiency and processing power demands. With a fresh approach to energy-friendly design, Energy Micro has equipped the EFM32 microcontrollers, an ARM Cortex-M3-based design, with energy-efficient peripherals smart enough for the low-power 32-bit core architecture. The supporting software and hardware tools introduce the capability to perform real-time energy debugging, and embedded designers have a device capable of consuming a quarter of the energy needed by incumbent 8-, 16- and 32-bit MCUs. Thanks to these changes, product designers are now able to significantly reduce the cost and size of the battery powering their product. With modern microcontrollers becoming ever more power-conscious and incorporating various power-saving modes of operation, ARM’s Cortex-M3, widely adopted for microcontroller designs, employs some of the most advanced power-saving technology seen among 32-bit processors. Energy Micro’s Cortex-M3-based EMF32 adds low-power peripherals and offers a range of power-saving modes for various operational situations. The industry as a whole is focusing on power conservation, and the EMF32 architecture can serve as an example of industry trends in this direction. RTC MAGAZINE MARCH 2011

29


Tech In Systems

Hardware Reduces Energy Consumption

To deliver true energy-friendly products, microcontroller makers have to consider several factors, and with a finite amount of charge available from a battery cell, it is how the MCU uses energy—power over time—that makes the difference. Examining embedded applications shows that many systems spend up to 99% of their time waiting for a pin change, a timer to match a compare value or to receive data. Looking at these wait states where the CPU could be sleeping, it becomes evident that minimizing the power and time is as important during sleep as in active periods. Before we look at the sleep modes, consider the period when the CPU is awake and processing data. To achieve higher performance, processors can either work hard or work smart. A 32-bit CPU can finish tasks or crunch more data in less time, and the system can return to a low-energy sleep mode sooner. By taking a task-oriented approach and choosing the appropriate RTOS, the application can handle task control, communication and synchronization in such a way that the CPU overhead is minimized. This successfully reduces the active state. The EFM32 MCU is based on the Cortex-M3 architecture and has been designed to help designers significantly reduce the active-mode power consumption. In benchmark tests, EFM32 at 32 MHz on a real-world 3V supply will run proper application code from flash memory at 180 µA/MHz. With fast code execution and defined sleep modes, the low energy advantage is lost if the time it takes for the MCU to wake up from deep sleep and re-enter the active mode is too long. Because no processing can be done, the energy is wasted. For MCU applications with real-time demands, the wake-up time must be kept to a minimum to enable the application to respond to an event within a set period of time. With latency demands shorter than the wake-up time of many existing MCUs, the device is often inhibited from going into deep sleep at all. In response, EFM32 uses a combination of design techniques to reduce the wake-up time from deep sleep to 2 µs, ensuring as little energy as possible is used before the CPU is enabled.

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MARCH 2011 RTC MAGAZINE

Figure 1 Energy debugging is simplified because the effect of code changes can be monitored in real time on the energy profiling graph.

Figure 2

a.

b.

LEUART RX polling showing run mode (a) and sleep mode (b) current consumption.

In the opposite situation, when the CPU is sleeping, the peripherals affect the energy efficiency. By applying the right low power design techniques, 32-bit processors can easily deliver sub-µA standby modes. At only 900 nA, the EFM32 microcontrollers incorporate real-time clock, power-on reset, brown-out detection and baseline functionality to make sleep modes useful. If the microcontroller can leave peripherals functioning autonomously for extended periods, the CPU can either solve other high-level tasks or fall asleep, saving energy either way. The EFM32 peripherals are designed to look after themselves and communicate directly via the Periph-

eral Reflex System. The MCU incorporates several autonomous peripherals: • an 8-channel, 12-bit ADC using 350 µA at full resolution and 1 Msamples/sec conversion rate; • a 4x40 segment LCD controller using just 550 nA and providing boost, contrast, animation and blink functions; and • a special low-energy UART, a full UART with 32 kHz clock, consuming only 150nA at a data transmission speed of 9600 baud.

Optimize Software Too

Having a super ultra low power microcontroller will not by itself guarantee us-


tech in systems

ers the lowest possible energy usage. Writing embedded code requires as much care as engineering the hardware. Software is not usually seen as an energy drain, but every clock cycle consumes energy, and minimizing this becomes fundamental to reducing overall system consumption. Optimizing software begins by choosing the right tools. Tools able to identify and remove energy drains at an early stage of prototype development can significantly reduce the overall energy consumption of the end product. A good compiler starts energy-efficient design by generating smaller code that uses less memory. Since such memory is usually high speed, expensive and consumes more power, reducing the demands on memory yields multiple gains. A good compiler also produces code that runs more quickly, speeding entry into power-saving mode sooner than code taking longer to perform its functions. An efficient operating system is the next pivotal factor. An efficient RTOS performs requested services more quickly, taking the program into power-saving mode sooner. A good RTOS achieves realtime responsiveness and operation with a less powerful processor, which normally results in lower power demands. While these capabilities are fundamental to good compiler and RTOS technologies, some RTOSs go the second mile, providing additional capabilities for managing power resources. A properly equipped RTOS informs the application

Figure 4

a.

Figure 3 Function contribution to energy consumption.

how long before the next scheduled event. The application then knows how long it may be idle, enabling it to enter the deepest low-power state practical, given the wake-up time required to emerge from power-down mode, and the maximum duration of potential power-saving time. This ensures that, if the period of sleep or power-down is too brief, the overhead needed to reawaken does not waste all the gains of the low-power mode or even increase power consumption. RTOS technology, such as Express Logic’s ThreadX, lets developers select appropriate power modes with this “time budget” in mind, avoiding a costly “thrashing” in and out of low-power mode. Table 1 offers the wake-up time for each mode. As you can see, the power-saving modes that consume the least power also require the longest time for the system to wake up. It would not make sense, for example, to enter EM4 if a scheduled event were to occur within 100 microseconds, since 160 microseconds would be required to reawaken. Modes EM2 or EM3 offer a better combination of saving and wake-up time and can be employed beneficially, even with just a few microseconds of time available.

It’s also necessary to consider the power expended in start-up. This, too, might affect the decision of which mode to enter, coupled with the time it can expect to remain in that mode.

Additional Efficiency Resources

Energy-friendly embedded systems development can be seen as a three-stage cycle: hardware debugging, software functionality debugging and software energy debugging. For hardware debugging, the most common way to track how much energy a system draws is by sampling the current over a certain period followed by averaging and extrapolation to longer time periods. This kind of measurement can be done using a multimeter or oscilloscope, but it is not possible to relate the results to code routines. On the other hand, a logic analyzer can be used to keep track of the routines but cannot relate that to the energy consumption. Given the criticality of software efficiency, software energy monitoring tools are now available. In addition to using the RTOS to determine how long a period of power-reduction can last to direct the

b.

c.

LEUART RX Interrupt with LEUART TX polling (a), EFM32 in Sleep Mode between received bytes (b), and EFM32 in Deep Sleep Mode (c).

RTC MAGAZINE MARCH 2011

31


Tech In Systems void pollLEUARTTx(void)

EFM32 running real application from Flash memory with 3V power supply

EM0 Run Mode

Current consumption

180 µA/MHz

45 µA/MHz

0.9 µA

0.6 µA

20 nA

Wake-up time

0

0

2 µs

2µs

160 µs

32 kHz peripherals

Async IRQ, I2C slave, Analog Comparators, Voltage Comparator

Reset

EM1 Sleep Mode

Any

EM2 Deep Sleep Mode

EM3 Stop Mode

Wake-up events

Any

CPU

On

High frequency peripherals

On

On

Low frequency peripherals

On

On

On

Full CPU and SRAM retention

On

On

On

On

Power-on Reset/Brown-out Detector

On

On

On

On

EM4 Shutoff Mode

{ while

On

TABLE 1

An Example Application for Reducing Energy Consumption

Using a LEUART module, let’s take a look at how the different views in the energyAware Profiler work together with the autonomous peripherals on the EFM32 to reduce energy consumption and increase battery life in the widest range of applications. In this example, the LEUART module enables UART communication up to a 9600 baud rate while keeping energy consumption to a minimum. A common way of getting data from the reception buffer is to poll it until you get valid data and then read the buffer. By doing this, the processor must be in a run mode, which results in relatively high current consumption.

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MARCH 2011 RTC MAGAZINE

The profile for such a loop, shown in Figure 2a, is a constant current consumption of 3.33 mA. By clicking on the graph, the function causing the drain is highlighted. void pollLEUARTRx(void) { while

(

!(

LEUART0

->

STATUS

!(

LEUART0

->

STATUS

&

}

Energy saving for various Low-power modes of operation.

choice of low-power mode, monitoring tools, such as Advanced Energy Monitoring (AEM), continuously measure current consumed. This information is correlated with the program counter sampling and allows real-life use cases to be debugged for low power operation. Energy debugging software tools, such as the energyAware Profiler, enable the user to identify the source code being executed at a given moment in time as shown by an energy graph ( Figure 1). The engineer can instantly pinpoint any part of the program causing high-energy consumption, ensuring code optimization and energy savings can be managed more closely.

(

LEUART_STATUS_TXC) );

&

LEUART_STATUS_RXDATAV ) ); }

The highlighted code line is the polling loop, which checks if the buffer has received any valid data. The Profiler also shows each function and how much each contributes to total energy consumption. In this case, the only function in the code is pollLEUARTRx(), which accounts for all the energy consumption (Figure 3). A common workaround to avoid polling the RX buffer is to enable RX interrupts and set the MCU in sleep mode. If we enable the LEUART RX interrupt and put the EFM32 in Sleep Mode (shut off the CPU), it is easy to achieve significant energy savings. As we shut off the processor, the current drops to 1.40 mA (Figure 2b). Now, when the LEUART receives a frame of bytes, it wakes up and transmits the data back through the TX buffer. When the interrupt is triggered, the current spikes to around 2.5 mA, displayed by the Profiler (Figure 4a). By clicking on the graph, it is possible to detect another common mistake when using UART communication.

After sending the data, a while loop waits for the transmission to finish. The loop can be replaced by an interrupt that wakes up the processor once the transmission is finished, and the current consumption will again be reduced (Figure 4b). Now the processor goes into Sleep Mode between each frame byte. It is not necessary to poll the buffer to know when the transmission is finished. Replacing the loop with an interrupt routine is a much more elegant and energy-friendly solution, shown with the different profiles of the two approaches. Because the LEUART module on the EFM32 MCUs is functional in a Deep Sleep Mode, the low-frequency oscillators are available and clocking the LEUART. If we repeat the above example putting the EFM32 in Deep Sleep Mode, the energy consumption drops to µA levels. If we change the Profiler to logarithmic scale, we see the current dropping to 1 µA in Deep Sleep Mode and 80 µA when receiving the frame (Figure 4c). The improved energy savings from the traditional approach to this configuration is a factor of over 1000. Clearly, energy efficient has come a long way, now offering energy-efficient architecture such as the EMF32, compilers and RTOSs tuned to maximize energy-efficient opportunities, along with profilers that help developers pinpoint where their program is wasting energy using traditional methods. Combining these technologies ensures that you can reduce power consumption, extending your device’s battery life for significantly longer infield time. Energy Micro. Oslo, Norway. +47 23 00 98 00. [www.energymicro.com]. Express Logic San Diego, CA. (858) 613-6640. [www.expresslogic.com].


Computing/HMI

Serial

I/O

The challenge is as satisfying as the solution.

Rugged laptop docking 10-port USB adapter station complies with military designed to meet IEC 60601-1 specifications medical isolation standard

1U solid-state computer boasts 250 I/O points and battery backup

RISC-based HMI operates over wide temperature range without heaters

OEM customers often need a solution tailored to fit their unique requirements. Sealevel’s engineers understand the advantages an optimized design can offer. From design specifications to project management to compliance and certification, our engineers work with your team to develop a product that perfectly meets your specifications. For 25 years, OEMs have relied on Sealevel’s expertise and experience for their application needs. Broadcast Communications Medical Military Navigation Point of Sale Process Control Remote & Environmental Monitoring Semiconductor Transportation Test & Measurement

We set the design bar. Then we raised it. Learn more about our custom solutions at www.sealevel.com/rtc/custom or scan this QR code with your smart phone.

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technology in

systems Optimizing Energy Use

Power Debugging the Software: Optimizing the Power Consumption of an Embedded System In an active system, the power consumption depends not only on the hardware design, but also on how it is used. And that is controlled by the software. by Lotta Frimanson and Anders Lundgren, IAR Systems

P

ower debugging is a methodology that provides software developers with information about how the software implementation in an embedded system affects system-level power consumption. By coupling source code to power consumption, testing and tuning for power optimization is enabled. Recent innovative technology has integrated the system’s power consumption into the embedded software development tools. With this approach, developers get an insight into how power consumption can be minimized in embedded software. That is what we call power debugging. The technology for power debugging is based on the ability to sample the power consumption and correlate each sample with the program’s instruction sequence and hence with the source code. One difficulty is to achieve high precision with sampling. Ideally you would need to sample the power consumption with the same frequency the system clock uses, but power system capacitances will reduce the reliability of such measurements. Put simply, the measured power consumption will be blurred in relation to what is ac-

34

MARCH 2011 RTC MAGAZINE

PC (program counter)

PC sample clock

Power value (mA)

ADC clock

T Figure 1 In order to correlate the PC and the power samples, the time offset between the PC sample clock and the ADC clock must be considered. The debug probe calculates this offset and makes it part of the data packets sent to the debugger.

tually being consumed by the CPU and peripherals. In practice this is not a problem though. As from the software developer’s perspective it is more interesting to correlate the power consumption with the source code and various events in the program execution than with individual instructions, so the resolution needed is

much lower than one sample per instruction. Power is measured by the debug probe. For example, the IAR Embedded Workbench uses the IAR J-Link Ultra. This measures the voltage drop across a small resistor in series with the supply power to the device (Figure 1). The voltage drop is measured by a differential am-


tech in systems

plifier and then sampled by an AD converter. The key to accurate power debugging is a good correlation between the instruction trace and the power samples. The best correlation can be done if complete instruction trace is available. The drawback with it is that it is not available in all devices and, if it is, it often requires a special debug probe. Less accurate but still giving good correlation is to use a PC (program counter) sampling facility that can be found in some modern on-chip debug architectures. It will sample the PC periodically and each sample will be given a time stamp. The debug probe samples the power consumption of the device using an AD converter. By time stamping the sampled power values and the PC samples it is possible for the debugger to present power data on the same time axis as graphs like interrupt log and variable plots, and to correlate power data to source code (Figure 1).

Figure 2 The power log window shows a log of all measured power values. The time values are measured relative to program start. Double clicking a line in the log window will take you to the source code corresponding to the program counter.

Presenting the Power Debug Information

As stated before, power debugging is based on the ability to sample the power consumption and correlate each sample with the source code. To illustrate this, letâ&#x20AC;&#x2122;s look at how IAR Embedded Workbench displays this. The power samples can be displayed in different formats. The Power Log window is a log of all collected power samples. This window can be useful to find peaks in the power sampling, and since the power samples are correlated with the executed code, it is possible to double-click on a value in the Power Log window to get to the corresponding code. Depending on the power sampling frequency, the precision will be different, but there is a good chance that you find the code sequence that caused the peak (Figure 2). Another way of viewing the power samples is via the Timeline window. In the Timeline window, the power samples are displayed in a time scale together with the call stack and up to four application

Figure 3 The timeline window combines quantities on a common time scale: Top graph: Two application values sampled by the DWT unit. Second graph: All interrupts activities in the system. Third graph: The call stack. B  ottom graph: Power samples in milli-Ampere, double clicking on a power value takes you to the corresponding code.

variables that you can select (Figure 3). In embedded systems, peripheral devices often account for much of the power consumption, and software controls how they are used, regardless of whether they are integrated into the micro-controller or not. This view provides a very convenient way of viewing the power consumption in relation to both function calls and, if

variables that are related to the status of a certain peripheral are used, also to activities that increase the power consumption on the board. The goal here is of course to see if the code can be optimized in the power domain. Also the Timeline window is correlated to both the Power Log window and the source code windows, so that you are just a double-click away from the RTC MAGAZINE MARCH 2011

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Tech In Systems

source code that corresponds to the values you see on the time line.

Power Profiling

In practice and in a task-oriented system it is probably more interesting to see how a particular function affects power consumption than to see statement by statement of how the power consumption changes. The function profiler will help you find the functions where most time is spent during execution for a given stimulus. In this way you can expose regions in the application where optimizations for power consumption should be done. On a device with the ability to sample the PC, the debugger can provide statistical profiling. The profiler finds the function that correlates to the sampled PC value and builds an internal database of how often the functions are executed to generate function profiling information. The profiling information for each function in an application will be displayed in a debugger while the application is running. With power profiling we combine the function profiling with the power sampling to measure the power consumption per function and display that in the Function Profiler window (Figure 4). The Function Profiler window will list the number of samples per function and also the average values together with max and min values. Once again we have a convenient way of finding peaks and abnormal behavior when it comes to power consumption in an embedded system. The system can appear to be fully functional and behave as expected in tests, but the power consumption can be much higher than it should and now we have a way to see that.

Optimizing Code for Power

In general optimizing for power is very similar to optimizing for speed. The faster a task is executed, the more time can be spent in a low-power mode. So by maximizing the idle time we are reducing the power consumption.

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Figure 4 The profiling window lists all functions in the application together with statistical data from the PC sampling and the power sampling. Average, min and max power values are provided for each function.

Power consumption

I2 I1

I0

t0

t1

t2

t3

t4

Time

Figure 5 Power consumption in an event-driven system. The shaded area shows wasted power due to poorly scheduling the activation of two peripherals.

Some examples can help illustrate the difficulty in identifying how a system unnecessarily consumes energy and where the system can be optimized for power. Typically it is not explicit flaws in the source code that are exposed, but rather opportunities to tune how the hardware is utilized. Sometimes, however, it may involve what might be described as pure bugs. Power debugging can be used to diagnose the effects of different low-power modes. Many embedded applications spend most of their time waiting for something to happen: receiving data on a serial

port, watching an I/O pin change state, or waiting for a time delay to expire. If the processor is still running at full speed when it is idle, battery life is being consumed while very little is being accomplished. So in many applications the microprocessor is only active during a very small amount of the total time, and by placing it in a low-power mode during the idle time, the battery life can be extended by orders of magnitude. A good approach is to have a taskoriented design and to use an RTOS. In a task-oriented design, a task can be defined with the lowest priority, and it will only


tech in systems

sumption in a CMOS MCU is theoretically given by the formula: P = f x U^2 x k

Figure 6 An example of where the acquisition of a low-level analog signal is disturbed by a power spike caused by the switching of a high power stepper motor. Power debugging can help find better sampling points that do not interfere with the stepper motor switching.

run when there is no other task that needs to run. This idle task is the perfect place to implement power management. In practice, every time the idle task is activated, it puts the processor into a low power mode. Many microprocessors and other silicon devices have a number of different lowpower modes, in which different parts of the processor can be turned off when they are not needed. The oscillator can for example either be turned off or switched to a lower frequency, peripheral units and timers can be turned off, and the CPU stops executing instructions. The different low-power modes have different power consumption based on which peripherals are left on. A power debugging tool can be very useful when elaborating with different low-level modes. The Function Profiler could be used to compare the power measurement for the task or function that brings the system down to the low-power mode when different low-power modes are used. Both the mean value and the percentage of the total power consumption could be useful in the comparison. CPU frequency definitely affects power consumption as well. Power con-

where f is the clock frequency, U is the supply voltage and k is a constant. Power debugging allows the developer to verify the power consumption as a factor of the clock frequency. A system that spends very little time in sleep mode at 50 MHz is expected to spend 50% of the time in sleep mode when running at 100 MHz. The power data in the debugger will allow the developer to verify expected behavior and if nonlinear dependency on the clock frequency exists, to choose the operating frequency that gives the lowest power consumption. An example involving interrupts can serve to illustrate another situation where it is difficult to identify that a system consumes unnecessary energy. Figure 5 shows a diagram of the power consumption of an event-driven system where the system at t0 is in an inactive mode and the current is I0. At t1 the system is activated whereby the current rises to I1 which is the systemâ&#x20AC;&#x2122;s power consumption in active mode with one used peripheral device. At t2 the execution becomes suspended by an interrupt that is handled with higher priority. Peripheral devices that were already active are not turned off, although the thread with higher priority is not using them. Instead, more peripheral devices are activated by the new thread, resulting in an increase in current I2 between t2 and t3 when control is handed back to the thread with lower priority. The functionality of the system could be excellent and it can be optimized in terms of execution speed and code size. But in the power domain even more optimization can be done. In Figure 5, the yellow area represents the energy that could have been saved if the peripherals that are not used between t2 and t3 had been turned off, or if the priorities of the two threads could have been changed.

Using power debugging would have made it easy to discover the extraordinary increase in power consumption that occurs when the interrupt hits and identify it as abnormal. A closer examination of the Timeline window could have detected that unused peripheral devices were activated and consuming power for a longer period than necessary. Naturally there would have to be a review of whether it is worth spending extra clock cycles to turn on and off peripherals in a situation like this example. Mixing analog and digital circuits on the same board has its own challenges. Board layout and routing become important to keep the analog noise levels at a low level to ensure accurate sampling of low level analog signals. Doing a good mixed signal design requires careful hardware considerations and skills. Software design can also affect the quality of the analog measurements. Performing a lot of I/O activity at the same time as sampling analog signals will cause many digital lines to toggle state at the same time, a candidate for introducing extra noise into the AD converter (Figure 6). Power debugging will aid to investigate interference from digital and power supply lines into the analog parts. Interrupt activity can easily be displayed in the Timeline window along with power data. Studying the power graph right before the AD-converter interrupts could identify power spikes in the vicinity of AD conversions that could be the source of noise and must be investigated. All data presented in the timeline window is correlated to the executed code. Simply double-clicking on a suspicious power sample will bring up the corresponding C source code. IAR Systems Foster City, CA. (650) 287-4250. [www.iar.com].

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technology deployed Small Modules in Transportation

Transportation Applications Find Value in Centralized Computing Platforms

systems can improve total cost of ownership, increase performance and reliability, and deliver greater levels of passenger comfort and service. Designers are finding that proven, standards-based COTS solutions can put them on the competitive fast track with efficient, centralized systems.

Thinking Ahead

Transportation applications are constantly pushing for more performance and increased networking capabilities, while also requiring the highest levels of ruggedization and reliability. In public transportation, this applies to a very broad spectrum of applicationsâ&#x20AC;&#x201D;ranging from ticketing Fragmented markets find common ground in modular and outside information such as destination details, to inside features such as on-screen COTS systems that streamline performance and improve schedule updates, voice communication passenger experience. to passengers and fleet dispatchers, advertisements, driver identification, navigation, travel recording and more. Deployment expectations of service and versatility are generally increasing, requiring designs to go well beyond just satisfying longevity, low power and extreme processing demands. Applications are evolving fast to include a variety of wireless interfaces such by Walter Furter, Kontron Wi-Fi, GSM/3G and GPS, and warrant highly integrated designs that deliver high electromechanical reliability with a minimum of system cables. These same expectations hold significance for systems police and rescue vehicles, fire brigade and command ransportation markets are varied but unified in their need trucks, and also for high-performance applications such as data gatefor flexibility, longevity, reliability and performance. Apways for railways, video surveillance in buses or trams and more. plications are characterized by extreme conditions, nonYet too many individual systems can increase maintenance stop operation and steadily increasing performance requireand its associated costs, as well as complicate the process of data ments. Given the extraordinary longevity requirements essential to transportation system design (requiring 24-hour operation for acquisition and network control. Instead, transportation systems 180,000 hours or the equivalent of 20 years), flawless and seam- today demand a single, centralized and open embedded computless performance is a distinct competitive advantage. Advanced ing platform. Optimal data exchange is standardized between embedded computing platforms are essential in meeting these vehicles, control centers and traffic facilities, and will rely on needs and further support developments in innovative, high-per- customized solutions developed using COTS products and platformance applications and growing passenger expectations. forms. COTS-based application-ready platforms are not only Trends in this market can be difficult to identify given its streamlining and integrating in-vehicle applicationsâ&#x20AC;&#x201D;but also fragmented nature. Buses, aircraft, vessels, light rail and cargo positioning operators to deliver next-generation systems demandshipping are all very different types of transportation design and ing the highest safety levels, greater passenger security and comthey all have unique application requirements on top of inherent fort, increased mobility, higher data communication bandwidth demands for ruggedness, reliability and longevity. Even systems and a range of improved performance attributes. used in agriculture and mining fall into this category and illustrate new and evolving categories for embedded design where satellite Customized COTS, Application-Ready Platforms data is used to improve operations, competitiveness and output. Public transportation systems such as railway applications Addressing cost and inefficiencies, however, is a primary design also require design expertise within the EN50155 standard. This challenge across the market. Eliminating disparate or outdated standard defines all characteristics of electronic equipment used

T

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Technology deployed

Figure 1

interfaces (serial/parallel ports, video, audio, USB and LAN) with rugged interface connectors. Front access to drives or flash media makes this fanless Box-PC especially compact and ready to install for passenger infotainment or security applications, as saved media can easily be exchanged simply by swapping out the storage device. Designed for the general vehicle market, the MPCX28R with Intel Atom processor technology is certified for both e1 and EN50155 up to TX-compliant for -40° to +70°C environmental temperature. Moreover, its I/O capabilities and IP52 class rating (specifying the level of environmental protection provided by the system’s enclosure) make it more cost-effective and easier to install than a fully featured centralized system designed to a customer’s specific requirements.

The Rugged Railway Box-PC is EN50155-certified and TX-compliant, helping OEMS reduce hardware design costs and get to market faster. The long-term available MPCX28R is energy efficient based on its 1.6GHz Intel Aton Z530 processor; robust M12 connectors are used for 2x Fast Ethernet, USB 2.0 and power.

on rolling stock. Aspects like operating conditions, design, construction and testing of electronic equipment, as well as the basic hardware and software requirements, assume that electronic train systems must operate in harsh environmental conditions without failure over the entire system lifetime. This places demands on COTS-based solutions that must operate reliably beyond general operational characteristics and many times necessitates customization within the design. Customization allows these systems to withstand extreme environmental conditions such as extended temperature ranges (-40° to +85°C), humidity, shock and vibration, and power fluctuations. For road transportation, many operators also request “e1” certification, which is based on ISO 9001 (quality management) and on European approval for equipment to meet certain EMC characteristics. E1 or e1 stands for certification along the European rules by German authorities. A certification by French authorities is called E2 or e2 etc. The ECE regulation is respected by European and many other nations including Japan, Australia, Korea and Russia, however, is not yet accepted or relevant for the American NHTSA. E1 certification is required in order to be labeled and certified EMC-compatible for error-free and immune operations side by side with complex vehicle electronics. As a result, application-ready platforms based on COTS products are leading growth and evolution in transportation design. Standards-based products are economical in terms of development time and cost. Moving forward, COTS-based application-ready platforms match future expectations of reduced costs based on high-volume production. Transportation operators are using this ideal design approach as an effective means of meeting specific system requirements, reducing time-to-market, and supporting lifecycle and extended availability. Modular COTS systems deliver a hardware platform that can be fit to numerous transportation applications, assuring smooth implementation within EN50155 compliance. In addition, integration and cost can be managed by choosing the right level of I/O and features. The Kontron Microspace MPCX28R Rugged Railway Box PC (Figure 1), for example, includes a comprehensive range of standard

Figure 2 With only one tenth of the thermal design power and one seventh the size of ULV processors at an identical performance, the nanoETXexpress-SP COM offers an very low power consumption/performance ratio for x86-based ultra-mobile designs. Suitable for compact and rugged transportation design, the nanoETXexpress specification for ultra small COM Express has recently been approved by the PICMG’s nanoETXexpress Industrial Group. It powers c-Box, the central management system in the Venturo Light Rail/Road Vehicle Management System.

Enabling Technologies

Using high-performance, small form factor COMs (Computer-on-Modules), centralized systems are able to be combined and unified in one computer system with features that have been developed specifically for public transportation environments. This is a compact approach that provides a modular framework for ticketing, telematics services, communication and various vehicle interfaces. Service and fleet management is optimized using a single point of command for all central computing tasks such as data collection and distribution, fleet management, routing, ticket printing and passenger information. This type of centralized system provides various serial, network and wireless interfaces to allow data exchange between onboard and external devices. As practically complete computers mounted directly onto a carrier board, COMs are often the embedded computing solution of choice for devices and applications where the design requires a small footprint, high performance, low power consumption, flexibility of design, easy customization, or all of the above. With diRTC MAGAZINE MARCH 2011

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mensions of 84 mm x 55 mm, the COM Express “ultra” such as Kontron’s nanoETXexpress is now the smallest form factor COM Express specification, and is highly useful for compact and rugged transportation environments (Figure 2). Its size represents 39 percent of the original COM Express module “basic” form factor size and 51 percent of the original COM Express “compact” footprint. With the COM Express specification rev. 2.0, PICMG laid the groundwork for the ultra-sized modules by adding the Type 10 pinout, a next generation to the previously introduced Type 1 pin-out. The definition of the new pin-out Type 10, which provides another evolutionary path for modular solutions in addition to Type 1, is the most impactful update to the nanoETXexpress specification as it puts more capabilities within reach for embedded application developers. The new pin-out explicitly addresses the requirements of new and highly compact processor families such as the latest Intel Atom processors. For transportation operators, integrating COMs into a centralized solution enables simple upgrades for future additional functionality—ideal for evolving fleet management strategies and passenger service requirements. Since all the approved form factors are fully compatible with the COM Express standard, mounting holes line up on each of the modules and the cooling solution concept is the same. This assures that basic, compact and to a certain degree now ultra modules are interchangeable on carrier boards. Simplified development is inherent with interchangeable COMs technologies including proven connectors and pin-out schemes. Shorter time-to-market and reduced development costs are the resulting significant benefits of integrating a COMs solution, further supported by vendor independence and wide availability across numerous manufacturing sources.

Centralized Systems in Action

One such example of a centralized system is Venturo C-Box and G-Box (Figure 3), implemented for a public bus operator servicing various related cities and regions. This operator has very high-level functional and technical requirements, and its systems

Figure 3 The Venturo Light Rail/Road Vehicle Management System is e1 an EN50155 certified central vehicle management platform for road and railway vehicles. Flexible installation and control is enabled by its various subsystems including its central management device, called C-Box, along with a GSM voice and audio communication system called G-Box, display device and ticket called HMI and additional accessories such as RF badge readers and antennas.

demand the same EN50155 ratings used in tramways or light rail applications. Its buses are uniformly equipped with a ticketing system and optionally include a broad range of onboard equipment such as CCTV, an SMS dispatch system, support for system operations, communication and GPS. The operator has committed to using new technology to improve passenger services. For example, it offers its passengers the ability to receive SMS text messages alerting them to traffic disturbances or delays of individual buses. Venturo incorporates an Atom-based onboard vehicle management platform and GPS telematics device with dead reckoning, providing sophisticated performance as a foundation for add-on applications that are unique with this implementation. GSM and Wi-Fi services are embedded and allow for efficient communication and system updates; digital I/O and Serial line

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MARCH 2011 RTC MAGAZINE

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technology deployed

support a broad range of onboard devices. Venturo’s built-in nanoETXexpress-SP Computer-on-Module (COM) with Atom Z5xx processor is the central server of the CBox, which manages all in- and out-bound data. It interfaces to the vehicle through galvanically isolated digital I/O and serial lines, including a higher IP65 environmental protection rating, and to the “outside world” by integrated GSM and WLAN interfaces. Vehicle localization, to enable improved service management, is supported through a GPS receiver including dead reckoning options. The Venturo HMI is connected to the C-Box to provide fare information and tickets to the passenger, while providing applicationspecific software menus to the driver. The G-Box connects to the C-Box to extend the standard feature set with audio functionality for announcing passenger information or enabling an audio alarm channel to the stationary service department. The operator’s embedded goal is to bring together the core of the ticketing system and various peripherals into one system represented by a screen managing all applications. This transition from disparate systems was established to achieve greater autonomy and reduce costs associated with outsourcing to accommodate a proliferation of new devices and services. Twelve vehicles run by this operator were initially equipped with the centralized system in late 2009; today ticketing, SMS services and destination management information is fully integrated into the onboard console. Further, vehicles are now able to communicate with the back office via a wireless infrastructure. The entire fleet will be centralized by mid-2011 and ready to launch and

integrate its future smart card ticketing system in 2013. Transportation systems must deliver ruggedness, reliability and longevity—demands that are consistent even across highly fragmented market applications. Yet the shape of this varied market allows plenty of room for an incredibly broad range of systems, and many designers are eyeing ways to streamline and centralize processes as a means of saving money, improving service and optimizing fleet management. In determining where they want to take their transportation designs, it is crucial that designers continue to explore implementations that challenge them to improve today’s infrastructures. Systems must be developed not only to withstand very specific environmental conditions and rugged, high-performance criteria, but also to deliver greater levels of passenger safety and comfort. For instance, ask yourself, when will police cars switch from Land Mobile Radio System to computerized VoIP only communication? This change won’t happen overnight, but there are systems demonstrating significant advances in this type of user convenience—and the compact embedded technology is in place and available for long-term development. The market is moving with higher passenger expectations and operators are responding with better service and efficiency at every stop. Kontron Poway, CA. (888) 294-4558. [www.kontron.com].

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products &

TECHNOLOGY FEATURED PRODUCTS Device Family Integrates Dual ARM Cortex-A9 MPCore with Programmable Logic

A new family of devices tightly integrates a complete ARM Cortex-A9 MPCore processor-based system with 28 nm, low-power programmable logic for system architects and embedded software developers to extend, customize, optimize and differentiate their systems. The Zynq-7000 family from Xilinx is being called an Extensible Processing Platform (EPP) and was developed to achieve the levels of processing and compute performance required in high-end embedded applications targeting markets such as video surveillance, automotive driver assistance, factory automation and many others. Each Zynq-7000 EPP device is built with an ARM dual-core CortexA9 MPCore processing system with NEON and Double Precision Floating Point extensions that is fully integrated and hardwired, and includes L1 and L2 caches, memory controllers, and commonly used peripherals. The processing system boots at power-up and can run a variety of operating systems independent of the programmable logic. The processing system then configures the programmable logic on an as needed basis. With this approach, the software programming model is exactly the same as standard, fully featured ARM processor-based SoCs. Application developers can take advantage of the programmable logic’s parallel processing to handle large amounts of data across a wide range of signal processing applications, as well as extend the features of the processing system by implementing additional peripherals. Highbandwidth AMBA 4 Advanced Extensible Interface (AXI4) interconnect between the processing system and the programmable logic enables multi-gigabit data transfers at very low power, thereby eliminating common performance bottlenecks for control, data, I/O and memory. The Zynq-7000 family accelerates time-to-market by providing an open design environment that facilitates parallel development of software for the dual-core Cortex-A9 processor-based system and custom accelerators in the programmable logic. Software developers can leverage the Eclipse environment, Xilinx Platform Studio Software Development Kit (SDK), ARM Development Studio 5 (DS-5) and ARM RealView Development Suite (RVDS), or compilers, debuggers, and applications from leading vendors within the ARM Connected Community and Xilinx Alliance Program ecosystems, such as Lauterbach, Wind River, PetaLogix, The MathWorks, Mentor Graphics, Micrium and MontaVista. In parallel, the Zynq-7000 family’s programmable fabric can be tailored to maximize system level performance and application specific requirements, leveraging Xilinx’s ISE Design Suite, which provides a comprehensive hardware development environment that includes development tools and AMBA4 AXI4 Plug-and-Play intellectual property (IP) and Bus Functional Models (BFM) to accelerate design and verification. Following Xilinx’s acquisition of high level synthesis leader AutoESL Design Technologies, Inc., further tool enhancements are underway to provide C, C++ and SystemC synthesis optimized for the

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Zynq-7000 device architecture. Future releases will also enable a more seamless movement of key algorithms between the processors and the programmable logic of the Zynq-7000 family. The Zynq-7000 family’s programmable logic is based on Xilinx’s newest 7 series FPGA architecture to ensure 100% compatibility with respect to IP, tools and performance across all devices within the 28nm generation. The smallest Zynq-7000 devices, the Zynq-7010 and Zynq7020 device, are based on the Artix-7 family which is optimized for low-cost and low power. The larger Zynq-7030 and Zynq-7040 devices are based on the Kintex-7 family and include between four and twelve 10.3 Gbit/s transceiver channels and a PCI Express Gen2 block for highspeed off-chip connectivity. The Zynq-7030 and Zynq-7040 devices offer approximately 1.9 million and 3.5 million equivalent ASIC gates (125K and 235K logic cells) respectively and DSP resources that deliver 480 GMACs and 912 GMACs of peak performance. The Zynq-7010 and Zynq-7020 devices provide roughly 430,000 and 1.3 million ASIC gates (30K and 85K logic cells) respectively, with 58 GMACs and 158 GMACs of peak DSP performance. All 4 devices also include a new dual 12bit 1Msample/s ADC block. Developers can begin evaluating the Zynq-7000 family now by joining the Early Access program. First silicon devices are scheduled for the second half of 2011 with engineering samples available the first half of 2011. Based on forward volume production pricing, the Zynq7000 family will have an entry point of below $15 in high volumes. Xilinx, San Jose, CA. (408) 559-7778. [www.xilinx.com].


PRODUCTS & TECHNOLOGY

4-Port and 8-Port Power-over-Ethernet ICs Offer an HDBaseTCompliant Solution

3U VPX SBC Takes Advantage of 2nd Generation Core i7 Processors

New 4-port and 8-port Power-over-Ethernet (PoE) ICs offer a smaller form factor and lower power dissipation. The new 4-port PD69104 and 8-port PD69108 Power Sourcing Equipment (PSE) PoE Managers from Microsemi are optimized for both commercial and industrial applications, delivering power to devices ranging from video screen phones and WiMAX transmitters to pantilt-zoom cameras, thin-clients and laptop computers. A 3U OpenVPX rugged single board comIn addition, the new ICs are HDBaseTputer takes advantage of the potential of the compliant solutions. HDBaseT is the latest, 2nd Generation Intel Core i7 processors—formost advanced connectivity technology for merly codenamed “Sandy Bridge.” The SBC324 long-distance transmission of uncompressed from GE Intelligent Platforms features a quadGet Connected with technology and high-definition video, audio and power. The technology enables 5Play simultaneous connectivity core processor operating at solutions up to 2.1 now GHz, coucompanies providing to numerous entertainment devices over a single 100m Cat5e cable. pled with up to 8 Gbytes of DDR3 1,333 MHz Get Connected is a new resource for further exploration memory for exceptional performance in size-, Key features include multiple power management modes. Dynamic power management lowinto products, technologies and companies. Whether your goal weightand power-constrained in directly ers system cost by 40% by reducing the power supply size, plus emergency power management is to research the latest datasheet fromapplications a company, speak environments supports multiple power supplies for granular power addition. In addition, backplane power manwith anharsh Application Engineer, orsuch jumpastounmanned a company'svehicles. technical page, the goal of Get Connected is to put you in touch with the right agement allows sharing of power supplies between multiple switches in a system. Resilient power Supported by GE’s ecosystem of 3U VPXresource. Whichever level of service you require for whatever of technology, management increases system resilience while maximizing power supply use. capabilities—which includes NVIDIAtype CUDAGet Connected will help you connect with the companies and products based GPGPU functionality, advanced graphics, Microsemi, Irvine, CA. (949) 221-7100. [www.microsemi.com]. you are searching for. high performance switches, high density storage www.rtcmagazine.com/getconnected and rugged chassis—the SBC324 is expected to High-Resolution Signal Acquisition Module for Audio and Vibration be deployed not only in traditional 3U VPX apTesting plications such as command/control, but also in A new 24-bit high-resolution dynamic ISR (intelligence, surveillance, reconnaissance), signal acquisition module is specifically deradar/sonar and signal processing. signed for audio testing, acoustic measureSBC324 also anand upgrade GetThe Connected withprovides technology companies prov ment and vibration analysis applications. The for GE’s MAGIC1 Rugged Display Computer, PCI-9527 from Adlink Technology features Get Connected is a new resource for further exploration into pro which combines the throughput of a second gendatasheet from a company, speak directly with an Application Engine two 24-bit simultaneous sampling analog ineration Intelthe Core i7resource. processor with the advanced in touch with right Whichever level of service you requir put channels with a sampling rate up to 432 parallel processing of an NVIDIA CUDAKS/s, two analog output channels with an Get Connected will help you connect with the companies and produc enabled GPGPU. The SBC324 benefits from a www.rtcmagazine.com/getconnected update rate up to 216 KS/s, and one external range of PCI Express backplane configurations; digital trigger I/O connector. an XMC site with I/O; two 10/100/1000BaseT The PCI-9527 also features a dynamic Gigabit Ethernet interfaces; VGA graphics; input range of >100 dB, flexible input range HD audio; two SATA channels; four USB 2.0 from ±40 V to ±0.316 V, and analog inputs ports; a PS/2 keyboard/mouse port; and two that support software-configurable features RS-232/422 COM ports. for AC or DC coupling and integrated elecA rich software choice is planned for the tronic piezoelectric (IEPE) sensors to interface with an accelerometer sensor and microphone. SBC324, including comprehensive Deployed Combining it all, the PCI-9527 offers the flexibility needed to create a wide variety of automated Test Software (BIT and BCS) plus operating test systems. system support for Windows 7, Open Linux, The PCI-9527 includes drivers and SDK support for mainstream Windows operating sysVxWorks, LynxOS and LynxOS-SE. tems as well as third-party application including LabView. Adlink also provides Dynamic SigGet Connected with companies and GE Intelligent Platforms nal Assistant APP Utility, an easy-to-use application for system integrators to perform valiproducts featured in this section. Charlottesville, VA. dation and reduce overall design cycle time. The PCI-9527 is currently availablewww.rtcmagazine.com/getconnected for a list (800) 368-2738. price of $2,950. [www.ge-ip.com]. ADLINK Technology, San Jose, CA. (408) 360-0200. [adlinktech.com].

Ad Index

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Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected

RTC MAGAZINE MONTH MARCH 2011

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PRODUCTS & TECHNOLOGY

32-bit PIC Microcontroller Portfolio with Additional Memory Options

A new, six-member family of 32-bit PIC32MX5/6/7 microcontrollers from Microchip Technology provides the same integrated Ethernet, CAN, USB and serial connectivity peripherals with new, more cost-effective memory options. Additionally, design enhancements have been made that provide lower power consumption of 0.5 mA/MHz active current, higher flash memory endurance of 20k read/write cycles and better EEPROM emulation capability. And, by maintaining common pin outs, the PIC32 portfolio provides designers with a seamless migration path to achieve the correct balance of memory and cost for their high-performance applications. Embedded designers are constantly looking for ways to lower their costs without sacrificing performance or functionality. Microchip’s newest 80 MHz PIC32 microcontroller family meets these needs by maintaining best-in-class performance of 1.56 DMIPS/MHz, and integrating Ethernet, CAN, USB and multiple serial communication channels, while offering more cost-effective memory options that start at $3.71 each in 10,000 unit quantities. Specifically, the family offers 32 Kbytes of RAM and up to 140 Kbytes of flash. Example applications for this new PIC32 family include: Communications (point-ofsale terminals, Web servers, multi-protocol bridges); Industrial/Medical (automation controllers, medical devices, security monitoring); Consumer/Appliance (audio, MP3 decoders, displays, small appliances, fitness equipment); Automotive (aftermarket, car alarms, GPS). The PIC32 Ethernet Starter Kit was designed to enable easy Ethernet-based development, and the PIC32 USB Starter Kit II does the same for USB designs. Owners of the Explorer 16 Development Board can purchase a $25 plug-in module for development with this new PIC32 family. 10,000 unit pricing ranges from $3.71 each for the PIC32MX534F064H, up to $4.93 each for the PIC32MX764F128L. Microchip Technology, Chandler, AZ. (888) 624-7435. [www.microchip.com].

SBC with New Atom N455/D525 Targets High Reliability

A new ISA half-size Single Board Computer (SBC) features the latest high performance Atom single and dual core processors. The PCA-6782 in versions N and D from Advantech integrates the Intel Atom N455/D525, which are suitable for embedded applications that required a balance of performance and lower power. The latest Intel Atom single core N455 and dual core D525 processors have an integrated graphic and memory controller (GMCH) all on the same chip. The Atom D525 dual core CPU brings compact size, low power consumption and dual core parallel computing power, and a maximum of 2 Gbyte of DDR2 667 MHz memory makes PCA6782D a powerful small form factor embedded platform for today’s industrial applications that require high performance in small packages. The fanless single core Atom N455 CPU with a maximum of 2 Gbyte of DDR2 667 MHz memory makes PCA-6782N ultra reliable in all kinds of high-temperature and dusty environments. PCA-6782 has an integrated graphic core based on Intel’s Embedded Gen 3.5+ graphic technology with 224 Mbyte shared memory. This feature makes PCA-6782 capable of handling complex and intense 2D/3D graphic processing tasks without an additional graphic card. VGA and LVDS dual video outputs also make it suitable for applications requiring dual display or digital panel display capabilities. PCA-6782 provides a rich array of I/O interfaces: it has three SATA ports (300 Mbyte/s) for mainstream SSD (Solid State Disks), HDD and ODD connections, and legacy I/O connection: one IDE, one PS/2, one FDD and one parallel port. It also has a CF socket, a PC/104 expansion, one Gigabit Ethernet LAN for high networking capability, and two COM ports. Optional Advantech COM port upgrade module (P/N: PCA-COM485-00A1E) is also available to give an extra four RS-485 ports with auto-flow control capability. Advantech, Irvine, CA. 949-789-7178. [www.advantech.com].

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Monitor Provides RealTime Visibility into System Performance and Health

A graphical software tool provides real-time visibility into systems that use Real-Time Innovations’ Data Distribution Service. RTI Monitor collects information and analyzes data flows, errors and network traffic so users have better performance and health data on their deployed systems. RTI Monitor functions as a configurable dashboard for quick-read, real-time display of system data. RTI Monitor augments Data Distribution Service, RTI’s implementation of the Object Management Group (OMG) Data Distribution Service for Real-Time Systems (DDS) Standard. RTI Monitor displays real-time data in color-coded charts, diagrams, tables and trees. This insight is useful during multiple phases of application development and management, from component integration, debugging and performance tuning to network-usage tracking and traffic analysis. RTI Monitor’s window into complex behavior is key for developers, integrators and operators. The tool not only collects detailed statistics on middleware activity—network traffic and errors, component configuration and system connection state—but also serves as a vital component for tracking and tuning application performance. RTI Data Distribution Service provides a data-centric messaging and integration infrastructure for demanding, mission-critical distributed applications. It combines deterministic performance, low latency, high throughput and fault tolerance into a fast, scalable architecture for realtime systems. By decoupling applications, RTI Data Distribution Service significantly reduces long-term software lifecycle costs. Individual subsystems may be modified, added or upgraded without affecting existing software. Real-Time Innovations, Sunnyvale, CA. (408) 990-7400. [www.rti.com].


PRODUCTS & TECHNOLOGY

Compile-Time Analysis Spots Quality and Security Problems An enhanced compile-time analysis tool identifies quality and security problems, helping companies to avoid failures in the field. CodeSonar 3.6 from GrammaTech provides a radically improved graphical user interface (GUI) to streamline developer interaction and boost productivity. In addition, CodeSonar 3.6’s analysis engine is more efficient. For large code bases, the analysis time has been reduced by as much as a third. CodeSonar is an advanced static-analysis tool that performs a whole-program, interprocedural analysis on code and identifies complex programming bugs that can result in system crashes, memory corruption and other serious problems. Like a compiler, CodeSonar does a build of the code. However, instead of creating object code, CodeSonar creates an abstract model of the program, capturing information about the program’s control flow and the relationships between data. The program model is executed symbolically by CodeSonar’s analysis engine. Automated reasoning about feasible paths and program variables is used to identify tricky defects, including defects that result from complex interactions among procedures. CodeSonar 3.6 is available today starting at $18,000 for small projects. Licenses for larger projects are based on the size of the project.

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GrammaTech, Ithaca, NY. (607) 273-7340. [www.grammatech.com].

Server-Grade Network Appliance Supports the Latest Xeon 5600 Series Processor

A new server-grade network appliance supports the Intel Xeon 5600 series quad-core and six-core processor based on 32 nm processor technology. The CAR-5010 from American Portwell features a 2U rackmount chassis, dual sockets for Intel Xeon 5600 series processors with an integrated memory controller, up to 6.4 GT/s Intel Quick Path Interconnect (QPI) Technology links between the two processors and Intel 5520 I/O Hub with 36 PCI Express generation 2.0 lanes, six DDR3 DIMM slots for each processor. The CAR-5010 provides extensive throughput performance using PCI Express Gen 2.0 solutions of both GbE and 10GbE bandwidth, at a competitive price. The CAR-5010 also supports remote network monitoring and active management. The remote management features include KVM, IPMI 2.0, Power Management, Virtual Media, IPMI Authentication and Web GUI. The CAR-5010 network appliance built with a 10G PCIe SFP+ network interface card (NIC)—one of the many NIC options—delivers breakthrough performance of multicore, 10 GbE computing, in addition to supporting the Linux OS, the most secured carrier-grade OS for the network and communication industry. It allows network application developers to consolidate solutions and lower development costs with a great feature set supporting both the PCI Express Generation 1.0 and 2.0, GbE and 10GbE (Intel 82599ES/EB), Copper and Fiber NIC with bypass or without bypass (fail-over). Customers can choose from these different solution portfolios to enhance their development cycle and launch their products to the market faster. American Portwell Technology, Fremont, CA. (510) 403-3399. [www.portwell.com].

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly Slave SBC Serves Ethernet Diagnosis Buffertechnical page, the with anas Application Engineer, or jump to a company's goal of Get Connected is to put you inCPU touchboard with theserves right resource. A new 3U CompactPCI PowerPC-based slave Whichever level ofThe service you from requireMen for whatever of technology, as an Ethernet diagnosis buffer. F218 Microtype helps to Get Connected will help youfor connect with the companies and products reduce wiring and installation requirements easier implementation you are searching for.

and reduced maintenance. www.rtcmagazine.com/getconnected Two Ethernet controllers within the FPGA enable the host to view the F218 as an Ethernet device, similar to a front connection of two CPU boards via an Ethernet cable. Get Connected with technology and companies prov The use of FPGA technology Get enables the incorporation of Connected is a new resource for further exploration into pro from a company, speak directly with an Application Engine additional user-specific datasheet I/O in touch with the right resource. Whichever level of service you requir functionality into the board. Get Connected will help you connect with the companies and produc Built on the PowerPC www.rtcmagazine.com/getconnected Power Architecture, the F218’s MPC8314 e300-based core is a cost-effective, low-power and highly integrated processor that makes the slave board ideal for a number of embedded computing environments found throughout the transportation, medical and industrial markets. The core processor operates at up to 266 MHz. The F218 features up to 256 Mbyte of soldered DDR2 SDRAM system memory with a bus frequency of 133 MHz as well as 16 Mbyte of flash as standard. An optional 1 Mbyte of non-volatile FRAM is also available. The card is qualified for operation from -40° to +85°C and supports VxWorks and Linux as standard with QNX available upon request. The VxWorks board support package (BSP) boots Get Connected with companies and in less than two seconds. MTBF, according to IEC/TR products featured in this62380 section. (RDF 2000), is 427,994 hours at www.rtcmagazine.com/getconnected 40°C. Single quantity pricing is $940.

Products

MEN Micro, Ambler, PA. (215) 542-9575. [www.menmicro.com].

Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected

RTC MAGAZINE MONTH MARCH 2011

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PRODUCTS & TECHNOLOGY

Plug-and-Play Integration of Avionics Software

A combination of DDS-compliant middleware with an ARINC 653-compliant RTOS dramatically reduces the time and cost required to develop and integrate distributed avionics software. The combined solution also drives down lifecycle costs by supporting standardscompliant programming interfaces and protocols, eliminating the pitfalls inherent in traditional proprietary solutions. Real-Time Innovations has announced that its Data Distribution Service for Real-Time Systems (DDS) middleware now supports Wind River’s VxWorks 653 real-time operating system (RTOS). Today, most avionics software relies on custom, vendor-specific integration logic that couples integrated applications with the underlying communication mechanism. This tight coupling results in high maintenance and upgrade costs because all applications must be updated and tested in lockstep whenever the communication mechanism changes. This can occur, for example, when modifying separate federated components on a common communications bus, or moving federated avionics components into an integrated modular avionics (IMA) system. RTI Data Distribution Service eliminates this coupling and the resultant cost, complexity and maintenance. Instead of using hardcoded integration logic, applications communicate by simply publishing the data they produce and subscribing to the data they need. RTI automatically connects matching publishers and subscribers in a plug-and-play manner, so applications need no direct knowledge of each other. Communication is seamless, whether within an ARINC 653 partition or between partitions, cores or systems. This enables rapid scalability and system reconfiguration. RTI Data Distribution Service for VxWorks 653 is available today as an early-access release. Pricing begins at $21,000 USD for new customers. Real-Time Innovations, Sunnyvale, CA. (408) 990-7400. [www.rti.com].

Conduction-Cooled 1/2 ATR Box with 6-slot 3U VPX Backplane

A new ½ ATR conduction-convectioncooled enclosure with a unique, advanced airflow design that distributes air across external fins in sidewalls helps to ensure fast removal of dissipated heat, yet still maintain a low profile design. The ½ ATR box from Elma Electronic Systems ships with a 6-slot 3U OpenVPX (VITA 65) backplane on 1” pitch; it is also available with either a 3U cPCI backplane or a single-width MicroTCA backplane. The unit also offers the choice of a fixed mount or plug-in 28 VDC power supply. The unit weighs only 12.5 pounds prior to power supply or payload. The all-aluminum ATR is made from milled plates as well as punched and formed sheet metal. The main body is dip-brazed for optimum heat conductivity. The conduction-cooled card cage is completely sealed off to keep the electronic components in a clean environment. A removable front panel allows I/O customization to exact application requirements. Narrow screw spacing ensures high EMC shielding compliant to MIL-STD 461E. The enclosure meets ARINC 404A and ANSI/VITA 48.2 standards. Pricing for the 1/2 ATR configuration starts at $15,000 in low quantities. Elma Electronic Systems, Fremont, CA. (510) 656-3400. [www.elma.com].

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Rugged 512 Gbyte Solid State Disk XMC with Data Encryption

A conduction- or air-cooled solid state disk (SSD) XMC module provides up to 512 Gbyte, or a half terabyte (½ TB), of storage capacity with data encryption. With the ability to operate in demanding MIL-STD-810F environments that include harsh temperatures and rigorous shock and vibration conditions, the XPort6103 from Extreme Engineering Solutions is well-suited to rugged, deployed, military applications with secure storage requirements. The XPort6103 is available with the option to provide 256-bit AES encryption, up to a capacity of 256 Gbyte. The encryption chip used on XPort6103 is NIST and CSE certified. The XPort6103 supports enhanced erases, meeting both the DOD NISPOM 5220.22 and NSA/CSS 9-12 specifications. Features include the XMC PCIe x1 interface and an optional XMC SATA interface. The drive features up to 512 Gbyte capacity, which appears as two 256 Gbyte drives. 256-bit AES encryption is also available as an option. Declassification is available via hardware or software control and the XPort6103 offers ATA Secure Erase support. The operating temperature range is -40°C to 85°C with 100,000 program/erase cycles. The XPort6103 provides up to 200 Mbyte/s sustained sequential read performance and 120 Mbyte/s sustained sequential write performance. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [www.xes-inc.com].


PRODUCTS & TECHNOLOGY

COM Express Module Boasts Quad-Core Processor, USB 3.0 and Digital Display Interfaces

Parallel to the launch of the second generation Intel Core processor family, Kontron introduced the COM Express basic form factor ETXexpress-SC Computer-on-Module. These Computer-on-Modules incorporate an Intel Core i7 2715QE quad-core processor, Intel Mobile QM67 I/O Hub and USB 3.0. Additionally, they feature the fastest Intel graphics on the market. The new Computer-on-Modules are available with the Type 2 or Type 6 Pin-out of the PICMG COM Express rev. 2.0 specification, increasing the speed of new designs and upgrades. They also include new features such as enhanced Intel Turbo Boost Technology, Intel Advanced Vector Extensions and Kontron Embedded Application Programming Interface (EAPI) middleware. Based on the COM Express Type 6 Pin-out, the Kontron ETXexpress features three digital display interfaces for SDVO, DisplayPort and DVI/HDMI besides VGA (2048 x 1536) and dual-channel LVDS (1600 x 1200). Optionally, customers can also upgrade two of the eight USB 2.0 ports to the SuperSpeed USB 3.0. The Type 2 Pin-out differs from Type 6 by offering PCI and PATA. SDVO, Display Port or DVI/ HDMI is brought out by the Type 2 version with one DDI multiplexed with the PEG port. Both the Type 2 and 6 versions use VESA DisplayID to automatically indentify the connected displays, which simplifies integration. All versions feature 4x Serial ATA (2 x SATA II and 2 x SATA 3). Application developers that want to make use of leading edge SSD technology will benefit from the new SATA3 interfaces with 3 Gbit/s by full bandwidth and highest transfer rates. Furthermore, the new modules feature 1 x Gigabit Ethernet as well as Intel high-definition audio. In line with the terms of the COM Express Rev. 2.0 specification, the new Kontron ETXexpress-SC Computer-on-Modules offer a serial peripheral interface for external firmware boots. Standard operating systems such as Windows 7, Windows Vista, Windows XP, Windows Embedded Standard 7, Linux (including Red Hat Enterprise, SuSE, Red Flag, Wind River Linux) and VxWorks are supported. Kontron also offers COM Express Type 2 and Type 6 evaluation carrier boards. Samples of the new modules with Type 2 Pin-out will be available in Q1/2011. Type 6 versions will follow in Q2/2011. Kontron, Poway, CA. (888) 294-4558. [www.kontron.com].

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Tel: (732) 578-0200 Fax: (732) 578-0250 E-mail: sales@avalue-usa.com www.avalue-tech.com RTC MAGAZINE MARCH 2011

49


with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

www.rtcmagazine.com/getconnected

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

www.rtcmagazine.com/getconnected

Company

Page

Website

ACCES I/O Products..........................................................................................................27.............................................................................................................www.accesio.com Advantech Technologies, Inc..............................................................................................23.........................................................................................................www.advantech.com

End of Article Products American Portwell Technology, Inc......................................................................................2............................................................................................................. www.portwell.com

Avalue Technology.............................................................................................................49........................................................................................................www.avalue-usa.com Get Connected with companies and Get Connected products featured in this section. with companies mentioned in this article. www.rtcmagazine.com/getconnected www.rtcmagazine.com/getconnected Avnet Electronics Marketing...............................................................................................43.......................................................................................................... www.em.avnet.com Cogent...............................................................................................................................8........................................................................................................... www.cogcomp.com

Get Connected with companies mentioned in this article. Extreme Engineering Solutions, Inc....................................................................................11. ............................................................................................................. www.xes-inc.com www.rtcmagazine.com/getconnected Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected

Innovative Integration.........................................................................................................15................................................................................................... www.innovative-dsp.com ISI Nallatech Inc................................................................................................................14............................................................................................................www.nallatech.com Logic Supply, Inc...............................................................................................................42........................................................................................................www.logicsupply.com Measurement Computing...................................................................................................52............................................................................................................ www.mccdaq.com One Stop Systems.............................................................................................................51.................................................................................................www.onestopsystems.com Phoenix International..........................................................................................................4............................................................................................................ www.phenxint.com Sealevel Systems..............................................................................................................33............................................................................................................ www.sealevel.com Small Form Factor SIG & Wireless Network Showcase........................................................40........................................................................................................................................ Tech Design Forum............................................................................................................41.............................................................................................. www.techdesignforums.com Themis Computer..............................................................................................................19............................................................................................................... www.themis.com VersaLogic Corporation......................................................................................................9.......................................................................................................... www.versalogic.com

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.

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MARCH 2011 RTC MAGAZINE


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March 2011

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