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The magazine of record for the embedded computing industry

February 2011

FPGAs and CPUs



llies or ivals

Atomic Clock Shrinks to Chip Scale Small Modules Gobble Big Data Vital Code: Verify and then Comply An RTC Group Publication


fully-assembled turnkey solutions Run, drive, or fly your Simulink design in real time, using Rapid Prototyping or Hardware-in the-Loop simulations on low-cost PC-based hardware. xPC Target provides a library of device drivers, a real-time kernel, and an interface for monitoring, parameter tuning, and data logging. It supports a full range of standard IO modules, protocols, and target computers.

m ®

Find it at datasheet video example trial request


Simulink and xPC Target™


©2010 The MathWorks, Inc.


FPGAs and CPUs

Allies or Rivals?

42 QDR SRAM Hits 550 MHz While Reducing Power Consumption by 50 Percent

44 6U OpenVPX DSP Engine Features Two Quad-Core Core i7-2715QE Processors


46 Preconfigured Rugged Systems Combine Flexibility with Short Lead Time



6Editorial Sunshine on the Highway, Power to the Grid

Technology in Context


FPGAs and CPUs—Allies or Rivals?

Data Acquisition with Small Modules

Team with FPGAs to Solve 16 MPUs Real-Time System Requirements Lawrence Getman, Xilinx

Microprocessors or FPGAs? Insider 22 Making the Right Choice 8Industry Latest Developments in the Embedded Marketplace

12 & Technology 42Products Newest Embedded Technology Used by Industry Leaders

Small Form Factor Forum Do We Really Need COM Standards?

EDITOR’S REPORT Precise Timing for Small Modules

Atomic Clock in Miniature in Precise Timing for Small 14AnUshers Modules

Steve Edwards, Curtiss-Wright Controls Embedded Computing

Acquisition Solutions Stack 34Data Up Robert Burckle, WinSystems

Elusive Data Ensures 38Capturing Reliable Results Ben Haest, QED, SA and Klaas A. Vogel, Elsys Instruments

SoC Platform for Terrestrial and Space Applications 26 Next-Generation Esam Elashmawi, Microsemi

TECHNOLOGY IN SYSTEMS From Verification to Compliance

Requirements through to Verification: Improve Current 30 Tracing Practices for Standards Compliance

Mark Pitchford, LDRA

Tom Williams

Digital Subscriptions Avaliable at RTC MAGAZINE FEBRUARY 2011


FEBRUARY 2011 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

Art/Production CREATIVE DIRECTOR Jason Van Dorn, ART DIRECTOR Kirsten Wyatt, GRAPHIC DESIGNER Christopher Saucier, GRAPHIC DESIGNER Maream Milik, LEAD WEB DEVELOPER Hari Nayar,

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HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, Editorial Office Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214

Published by The RTC Group Copyright 2010, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


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To Contact RTC magazine:

10/16/09 11:43:57 AM

PC/104 Analog I/O Modules No Calibration Required Plus -40° C to +85°C Operation WinSystems’ PCM-MIO and PCM-ADIO provide high-density analog and digital solutions for rugged industrial applications. Both offer easy set-up and no adjustments over multiple input voltage ranges, saving both time and money.

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Sunshine on the Highway, Power to the Grid


’m sure that by now all of us have heard that admonition to “think outside the box” so many times that it has long since become a cliché. The idea of thinking outside the box is so old that it is now inside the box. I think that is one reason that truly innovative ideas usually look pretty crazy and improbable to those who are surprised by them. Still, there are ideas that may seem crazy at first, but whose actual craziness eventually becomes their strength. Just remember the put-down of the telephone—“That will never work because you’d have to run wires all over the country.” Duh! There is now an idea starting to gain traction that appears pretty crazy at first, but which, should it find its way to reality, has some pretty enormous potential. I happen to be attracted to it because if it is implemented, it will require truly massive numbers of microprocessors and embedded intelligence. This is a project known as the Solar Roadway and whose goal is nothing less than to replace asphalt and concrete road surfaces with hardened solar panels that can be driven on. In this scenario, the system for power generation would also become the system for power distribution and also be capable of carrying data traffic including phone, Internet, TV, etc. It may come as a surprise that certain levels of funding are already in place. The Federal Highway Administration is supporting some initial research and development, and prototypes of road panels are now being built. A panel consists of three layers. The road surface layer is made of high-strength translucent material rough enough to provide good traction, carry the heaviest loads placed on it and protect the underlying electronics. The electronics layer includes microprocessors, solar cells, heating equipment for snow and ice removal, lighting and communication systems. The base plate layer sandwiches the electronics layer for protection and carries the data and control signals to other panels. A road system built of 12 x 12-foot panels would act as a smart grid and national communications network. The generation of electricity by the roadway is being presented as the way to pay for the enormous construction costs—some of which must be expended anyway simply to maintain the existing infrastructure. Now if an idea like that doesn’t sound ambitious, I don’t know what will. Conservative estimates show that covering the entire 28,962 square miles of road surface in the country could result in over 13,961 billion kilowatt hours of useable power per year—as opposed to the approximately 3,741 billion kilowatt hours currently



Tom Williams Editor-in-Chief

consumed (based on EIA figures for 2009) each year by the U.S. This allows for northern roads producing less electricity than their southern counterparts due to the sun angle and other vagaries inherent in such a massive undertaking. Obviously, that can’t happen overnight, nor will every square mile of road surface be converted. The idea is to start with parking lots and driveways and expand out onto roadways. With the national highway (and Interstate) infrastructure in need of maintenance, the push from Solar Roadway will be to resurface those roads with the panels, gradually linking them all together with the Smart Grid. Such a grid system, completely decentralized, would be largely immune to wide system failure or to terrorist attack. In addition to providing eventually more electricity than currently needed, the solar highway would also be an intelligent highway, able to sense the traffic on it or even pedestrians in a crosswalk, communicate with control centers and by virtue of its embedded LED lighting, be capable of dynamically interacting with drivers. For example, lights in the roadway could warn of an accident ahead, guide drivers to detours or change speed limits for different conditions. RFID devices in vehicles could be used to track individual vehicles by both government and private entities and fleet management systems. For military applications, airstrips and forward bases could be built in remote areas and would automatically generate power without having to bring in generators or run power lines. Then there is the matter of electric vehicles. The limited length of a charge and the time required to recharge are among the biggest hurdles for the wide acceptance of electric vehicles. Installing charging stations at points along the solar roadway would be a natural outgrowth of its implementation. In addition, work is being done to develop ways to use mutual induction for charging electric cars as they travel down the solar roadway. The hope is that the elimination of fossil fuel power generation by a vast solar highway system would also eliminate both the fossil fuels needed to power the vehicles as well as fossil fuel and nuclear plants needed to charge them, vastly cutting down or eliminating greenhouse gas emissions. Does this all sound crazy? Good. At least that is thinking outside whatever multi-dimensional container now normally restricts creative thought. More concrete—or hardened translucent material— information may be found at It can be an entertaining and possibly inspiring experience to take a look.







INSIDER FEBRUARY 2011 NanoETXexpress 2.0 Specification Approved for Credit Card Sized COM Express Modules The nanoETXexpress Industrial Group has announced the approval and release of the nanoETXexpress 2.0 specification for ultra-small COM Express Computer-on-Modules. The PCI Industrial Manufacturers Group (PICMG) identified the need to adopt the COM Express specification to the new capabilities for ultra-small-sized modules with the latest processor technology. With the COM Express specification rev. 2.0, PICMG laid the groundwork for ultra-small-sized modules by adding the Type 10 pin-out, a next generation to the previously introduced Type 1 pinout. Keeping in line with the COM Express specification, the nanoETXexpress specification rev 2.0 implements all relevant parts of the current COM Express specification. The definition of the new pin-out Type 10, which provides another evolutionary path for modular solutions in addition to Type 1, is the most impactful update to the nanoETXexpress specification as it puts more capabilities within reach for embedded application developers. Consistent with the COM Express specification rev 2.0, the nanoETXexpress specification 2.0 calls out the same Type 1 and Type 10 pin-outs and keeps the overall footprint of the modules and the corresponding cooling solutions compatible to those called out for the COM Express basic and compact form factors. The most important addition to the new nanoETXexpress specification is the introduction of the new COM Express Type 10 pin-out. It explicitly addresses the requirements of new and highly compact processors families. COMs adhering to the nanoETXexpress specification utilizing the COM Express Type 10 pin-out support one Digital Display Interface (DDI) with SDVO port or alternatively DisplayPort or HDMI/DVI. As a result, developers get more design freedom and performance in display connectivity and still maintain backward compatibility to pin-out Type 1 designs. Combined with the single-channel LVDS, nanoETXexpress modules now support dual-display as well. New for both the Type 1 and Type 10 pin-outs defined in the nanoETXexpress specification is the support of PCI Express Gen 2 as well as the addition of dedicated pins for serial interfaces or CAN bus. Revision 2 of the nanoETXexpress specification now allows the BIOS or firmware interface for internal and external boots via serial peripheral interface (SPI).

Pigeon Point Systems Spins Out from Microsemi after Actel Acquisition

Pigeon Point Systems has reestablished itself as an independent company, following the recent acquisition of Actel Corporation by Microsemi. Pigeon Point Systems will continue their successful cooperation with the Microsemi SOC Products Group (formerly known as Actel) on the use of the industry-recognized SmartFusion intelligent mixed signal FPGAs in xTCA hardware platform management controllers. “Pigeon Point previously operated as a wholly owned subsidiary of Actel Corporation, so our customer interfaces and product offerings are unaf-



fected by these changes,” said Mark Overgaard, Pigeon Point Systems. “SmartFusion’s combination of hard ARM CortexM3 and programmable analog with an FPGA fabric provides an ideal core for compact, cost-effective, high-integration management controllers. Microsemi and PPS have agreed to continue to deepen and broaden the Pigeon Point management controller solution portfolio based on SmartFusion.” Pigeon Point will also continue to deliver and strengthen the Pigeon Point Shelf Manager, its industry-leading solution for shelf level management, with tens of thousands of installations in ATCA systems around the world.

Global Satellite Communications Network Called COMMstellation

Microsat Systems Canada Inc. (MSCI), Canada’s designer and builder of the Multi Mission Microsatellite Bus (MMMB) and Commercial Microsatellite Bus (CMB), has announced the development of COMMStellation, a polar communications constellation comprised of 78 microsatellites that will orbit the Earth at 1,000 km, providing backhaul capacity while connecting remote regions of the Earth to the Internet. “The influx of millions of data-hungry mobile devices, such as smartphones and tablets, is causing unprecedented strain on mobile networks, which have already reached, or are nearing,

capacity,” explains David R. Cooper, President and CEO, MSCI. “COMMStellation will provide essential backhaul capacity to mobile operators across the globe. It’s an initiative many governments are pushing for because of its ability to connect all of Earth’s citizens to the Internet.” Companies such as RIM, Apple, Microsoft, Google, Nokia, Yahoo!, Facebook and Netflix, whose business models increasingly rely on high-speed Internet communications to stream data, are reliant on mobile operators and Internet service providers to enable fast, reliable and uninterrupted data transfer. “While demand for backhaul bandwidth grows exponentially, there is downward pressure on consumer wireless pricing,” explains Michael Neuman, former CEO of Bell ExpressVu Satellite TV and Founder of Elevest Corporation. “This situation, together with the need to reach economically challenged population centers, calls for an innovative, low-cost satellite solution.” “High-speed backhaul infrastructure is the single most important enabler to the growth of Internet business models and wealth generation,” adds Mr. Cooper. “If a country does not have it, it will fall behind.”

STMicroelectronics and Bluechiip to Cooperate on MEMS-based Tracking Tags

STMicroelectronics and Bluechiip Limited have announced that the two companies are to cooperate in the manufacturing of MEMS-based tracking tags, aimed at a range of different markets, but initially in healthcare, such as biobanks. As the Bluechiip tracking tag is a mechanical device, it has

the unique ability to both survive and read the ID of samples in extremely high and low temperatures, in addition to its immunity to gamma irradiation. This robustness therefore provides significant advantages over more traditional identification or tracking solutions, such as labels, barcodes or RFID technologies, and provides the necessary high levels of data surety in the rapidly growing and labor-intensive healthcare markets, especially in biobanking. The growth of biobanks worldwide has been exponential; recent studies estimate that hundreds of millions of tissue samples are stored in U.S. biobanks

and greater than one billion are stored worldwide. The tags will first be molded into test tubes and vials for the expanding biobank market to identify, track, retrieve, monitor and store valuable and irreplaceable human biospecimens, including tissue, embryos and cord blood in liquid nitrogen. Although the Bluechiip tracking technology has initial applications in the healthcare industry, it also has applications in pathology, clinical trials, biorepositories and forensics. Other key markets for the technology could include security, defense, industrial, manufacturing, waste, aerospace and aviation.

This new technology enables data to be read at temperatures as low as those reached in liquid nitrogen, approximately -196 degrees Celsius, and as high as 200 degrees Celsius. Data can also be transmitted through frost. Bluechiip’s tracking solution has also been field-proven to survive autoclaving, gamma irradiation sterilization, humidification, centrifuging, cryogenic storage and frosting. The new technology is based on MEMS-based resonators within a tiny and purely mechanical chip, containing no electronics whatsoever. The tracking tag, which comprises this mechanical

chip and an antenna, can either be embedded or manufactured into a storage product, such as a vial or a bag. Easy identification along with any associated information from the tag can be detected by a reader, which can also log the temperature history of the tagged items.

BittWare Named to “NH’s Best Companies to Work For” List for the Third Year in a Row

Congratulations to our good friends at BittWare! BittWare, a designer and manufacturer of high-end

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at Closing Price 52 Week Low 52 Week High Market Cap

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Company Market Performance

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RadiSys Corporation





Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities.




COTS signal processing solutions, has, for the third year in a row, been named to Business NH Magazine’s “NH’s Best Companies to Work For” list for 2010. The company was ranked the number five best business to work for in New Hampshire amongst companies with less than 100 employees. While this is the third year in a row that BittWare has been named to the top 10 list, this is the fifth year the company has been within the top 20. The annual competition, run by Business NH Magazine and NH Businesses for Social Responsibility, seeks out companies in NH who truly invest in their employees. BittWare competed with numerous companies from across the state, submitting an extensive application, and then welcoming a panel of judges to BittWare’s Concord, NH headquarters where they conducted a site visit and interviewed a focus group of BittWare employees. Jeff Milrod, BittWare’s President & CEO, will join leaders from the nine other winning companies to share their best practices at the Breakfast with the Best forum to be held Feb. 17, 2011 at the Radisson Hotel, Center of NH in Manchester.

Report on the future of NAND Flash Memories NaMLab GmbH and Forward Insights have published a report on the future of semiconductor-based memories for data storage. Today, advanced NAND flash memories are currently being manufactured with feature sizes between 27 nanometer and 24 nanometer. In the race to reduce costs, NAND flash manufacturers are developing technology nodes in the low 2x nanometer range. However, in the near future, floating gate NAND flash will encounter fundamental scaling limitations. When floating gate NAND flash scaling comes to an end,



What’s after NAND? NAND flash suppliers are actively exploring a variety of alternatives including spin-torquetransfer MRAM, phase change memory, conductive bridge memory and metal oxide-based valence change memory. However, as lithographic scaling becomes more challenging, companies are turning their sights to vertically stacked implementations of memory cells or 3D memory. 3D memory technologies offer the promise of continued increases in storage capacities and lower cost per bit necessary to enable emerging applications such as solid state drives. Among the candidates are stacked NAND technologies employing charge trapping technology, vertical memory cells etched in a pillar and stackable crosspoint memory arrays. What’s after NAND? provides an independent analysis of the feasibility of each of these alternatives as a candidate to replace floating gate NAND flash memories within this decade.

You Heard it Here First— Eight Predictions for the Embedded Software & Tools Market in 2011

VDC Research Group analysts have announced their predictions for the key trends anticipated to shape the 2011 embedded software & tools market. Android to Catalyze Further Growth in Commercial Linux Market As device manufacturers take Android into new application classes beyond mobile, the commercial Linux market will experience further growth. Multi-OS Systems Will Grow in Designs More application classes will have sophisticated UI functionality that are not supported by traditional OSs and end-users will seek out systems based on multiple operating systems.

Virtualization in Embedded and Mobile Systems Will Increase Driven by hardware bill of materials savings and reduced concerns regarding additional run-time execution latencies and costs, operating system virtualization will provide increased growth opportunities and therefore will continue to be a significant focus for many suppliers. Symbian’s Loss to Become MeeGo’s Gain Intel’s increasing focus on embedded combined with Symbian’s loss of strategic direction will drive additional gains for MeeGo as Nokia turns their attention toward the Linux-based platform. OEMs to Increase Focus on the Use of Web Security Test Tools Increased interaction with the cloud and Web-based content by more embedded device classes will increase OEM focus on the use of Web security test tools. Telecom Vertical Will Reaccelerate Spending on Commercial Products The increasing burden of mobile device data usage is driving the need for investment in wireless infrastructure and the telecom vertical market will reaccelerate spending on commercial products. Microsoft Will Regain Relevance in the Mobile Phone Sector Riding the wave of Windows Phone 7 buzz, Microsoft will reemerge as a leading player in the mobile phone arena. Another Acquisition to Come? Following a string of highprofile acquisitions in 2009/2010, VDC anticipates yet another major embedded real-time operating system supplier will get acquired in 2011.

EVENT CALENDAR Real-Time & Embedded Computing Conference (RTECC) MINNEAPOLIS, MN March 22, 2011

Real-Time & Embedded Computing Conference (RTECC) CHICAGO, IL March 24, 2011

Real-Time & Embedded Computing Conference (RTECC) AUSTIN, TX April 12, 2011

Real-Time & Embedded Computing Conference (RTECC) DALLAS, TX April 14, 2011 Visit for Keynotes, Tech Seminars & Exhibitors!

FPGA Board & USB Showcase Featuring the latest in FPGA Board & USB technologies USB-AIO Series, USB Multifunction Analog Input/Output System

USB-AO Series: Multifunction USB/104 modules provide up to 16 Analog Outputs and 2 Analog Inputs

High-speed USB 2.0 device, up to 500kHz sampling rate Up to 128 signal conditioned analog inputs, 12 or 16-bit, and 2 analog outputs Eight input ranges, unipolar or bipolar Real-time hardware auto-calibration and oversampling for accurate data Wide range of signal conditioning types per channel A/D Starts via software, timer or external trigger 16-bit programmable counter/timer

ACCES I/O Products, Inc. Phone: (858) 550-9559 Fax: (858) 550-7322

4, 8, or 16 analog outputs with 12 or 16-bit resolution USB/104 form-factor for OEM embedded applications PC/104 module size and mounting compatibility Two 16-bit analog inputs and 16 lines of digital I/O Connections made via industrystandard 37-pin D-Sub connectors Alternate micro-fit embedded USB header connector

ACCES I/O Products, Inc. E-mail: Web:

Phone: (858) 550-9559 Fax: (858) 550-7322

Microsemi SoC (Actel) RTAX and RTSX Prototyping

Aldec, Inc. Phone: (702) 990-4400 Fax: (702) 990-4414

ProASIC3E- based reprogrammable adaptor board Supports RTAX-S/SL and RTSX prototyping Applicable for RTAX-S/SL 250, 1000, 2000, 4000 prototyping Applicable for RTSX-SU/SX-A A54SX32A, A54SX72A, RT54SX32S, RT54SX72S, RTSX32SU, RTSX72SU prototyping Compatible with CQFP 208, 256, 352 and CCGA 624 footprints Netlist Converter for automatic RTAX to ProASIC3E EDIF netlist conversion E-mail: Web:

HES-XCELL HardwareAssisted Simulation RTL Simulation Acceleration up to 10x Xilinx Virtex5 (~4 million ASIC gates) PCI Express, on board 4GB DDR II Extensive Debugging Automatic Design Partitioning 32/64 bit Windows /Linux 3rd Party RTL Simulators support

Aldec, Inc. Phone: (702) 990-4400 Fax: (702) 990-4414

E-mail: Web:

S4-AMC: Altera Stratix® IV GX AdvancedMC with VITA 57 Site

S4-3U-VPX: Commercial & Rugged Altera Stratix® IV GX 3U VPX Board

VITA 57 FMC site for I/O and processing expansion, available with high bandwidth A/D and/or D/A High density Altera Stratix IV GX supported by BittWare’s ATLANTiS™ FrameWork BittWare’s FINe™ III Host/Control Bridge provides control plane processing and interface Fully connected to AMC (16 ports SerDes, 4 ports LVDS) I/O includes 10/100/1000 Ethernet, SerDes, LVDS, RS-232, and JTAG

VITA 57 FMC site for I/O and processing expansion, available with high bandwidth A/D and/or D/A High density Altera Stratix IV GX supported by BittWare ATLANTiS™ FrameWork for FPGAs BittWare FINe™ III Host/Control Bridge provides control plane processing and interface Fully connected to VPX: GigE, 15 SerDes, 32 LVDS Additional I/O: 10/100 Ethernet, RS232, JTAG

BittWare Phone: (603) 226-0404 Fax: (603) 226-6667

E-mail: Web:

BittWare E-mail: Web:

Phone: (603) 226-0404 Fax: (603) 226-6667

E-mail: Web:



Colin McCracken & Paul Rosenfeld

Do We Really Need COM Standards?


o we really need COM standards? COM (Computer-onModule) products have taken the embedded market by storm over the past few years. They are becoming the mainstay of the exploding small form factor market. The market has been driven by popular standards such as COM Express, ETX, Qseven and others. Some of these standards have many incompatible sub-standards (e.g., pinout types), effectively driving the number of distinctly different COM architectures into the dozens. What benefits accrue to the market as a result of this standardization effort? Typically, these benefits would include: a broad ecosystem of ancillary products (I/O boards, enclosures, cooling solutions, etc.), second sourcing, lower pricing through competitive bid for each purchase, and upgradeability to higher performance. All of these are truly worthy of the standards effort. The trouble begins when examining the performance of COM solutions with respect to these benefits. First, there is no ecosystem per se for COM products. COM products by definition have a single interface to an application-specific baseboard that provides I/O and bus interfaces. Baseboards are custom to each application and/or implementation in form factor and functionality. There are no third-party I/O cards, enclosures, or cooling solutions for COM products (vendor-supplied heatspreaders don’t count). Secondly, the alternate sourcing issue fails due to the widely reported and well documented failure of interchangeability between modules implemented to the same COM standard. The issues, ranging from BIOS incompatibility to power sequencing to undocumented uses of “reserved” pins, mean that it is difficult if not impossible to change modules in production without also making changes to the baseboard. This failure shoots big holes in the other potential benefits of COM standards—lower pricing through competitive bid as well as the ability to upgrade performance by swapping the COM module. To be fair, some of these difficulties can be mitigated by designing the baseboard from the get-go to support more than one module, but this is rarely done and it frequently proves exceedingly difficult to resolve the differences on a single baseboard. And any BIOS incompatibilities must be resolved by the COM vendors.



This leads to the question of whether we would be better off (or at least no worse off) if every COM manufacturer went their own way with their own unique pin definitions, connectors and form factor. Probably not, because there is comfort in the illusion of compatibility provided by the standards that exist today. And because switching between manufacturers to a different pin definition, connector and form factor is a much more significant undertaking than simply trying to accommodate the differences that exist between modules today. That does not say, however, that what exists today has much value. Let’s face it—every COM solution is a custom solution. Period. Does this give the green light to COM suppliers to develop their own custom implementations with modified or tweaked pin definitions or form factor extensions? There’s a better way. Interestingly enough, the answer comes from the chip community where some of these benefits (second source, price competition) have been a big issue for decades. In this community, if true interchangeability/second sourcing is desired, the design is licensed to another chip company to produce. It’s time the COM manufacturers woke up and looked at the best way to perpetuate their technology. Because of the rigid pin definition, there is virtually no opportunity to incorporate any unique features or functionality. Every COM built to the same standard has the same components and layout and the same features and functions, with only those annoying little implementation details discussed earlier that make them different. It’s time for one COM manufacturer to take the lead, do the first design with a new processor / chipset combo, and share the design at no charge with other members of their standards group. Members could take turns with new designs so that no one member is burdened every time. This approach provides a rock solid, ironclad second sourcing and the opportunity to seek alternate suppliers with each purchase. It does not, however, deal with the upgrade issue. Ever wonder why virtually any memory module (DIMM and SODIMM) that you buy works in virtually every desktop or laptop? Because many are made from the same design shared among memory suppliers. COMs can do this too. Or could it be that COM suppliers only want the illusion of compatibility and not the reality. That they want to avoid second sourcing and direct price competition. Ouch! Hello users—are you out there?

FPGA Board & USB Showcase Kontron MICROSPACE® MSMST

Cobalt Model 53650 3U VPX Transceiver with Virtex-6 FPGA

PCIe/104™ SBC with the Intel® Atom™ E6x5C processor HSMC for custom interfaces Flexible FPGA I/O configuration for application-specific requirements E2 Industrial Temperature Range (-40°C to +85°C) available

Kontron Phone: (888) 294-4558 Fax: (858) 677-0898

Pentek, Inc. E-mail: Web:

Phone: (201) 818-5900 Fax: (201) 818-5904


Phone: (408) 273-4528 Fax: (408) 273-4628

Based on Xilinx® Virtex®-6 PCI Express Gen2 x8 Up to 8 GByte DDR2 SDRAM Up to 288 MByte QDRII+ SRAM 2 Gigabit Ethernet interfaces (RJ45) RoHS compliant FMC extension for custom daughtercards

PLDA E-mail: Web:

Phone: (408) 273-4528 Fax: (408) 273-4628

Device Server Serial-to-Ethernet Modules

Radicom Research, Inc.

USB 2.0 compatible External dongle and internal module formfactor available Linux, Windows and Mac O/S support -40°C to +85°C operating temperature (Modules) Compact size: 1” x 1” x 0.2” (Modules) Up to 56K bps data rate, fax and voice AT command

Radicom Research, Inc. E-mail: Web:

Phone: (408) 383-9006 Fax: (408) 383-9007

E-mail: Web:


SPI Storm™

GP-24132 is a USB 2.0 high speed digital patter generator, logic analyzer and bi-directional protocol (SPI/I2C) host adapter. Its 32 MB memory allows unprecedented recording length or digital patter depths at maximum frequency for sampling and pattern generation (logic generator).

SPI Storm™ is a Serial Protocol Host Adapter that supports SPI, dual-SPI, quad-SPI and virtually any user-defined custom serial protocols. First dual-/ quad- SPI host adapter in the world! 32MB buffer, 100MHz max signal frequency on serial port and 8bits DPG. Available March 2011 with software & accessories. $999.00

Saelig Company, Inc. Phone: (888) 772-3544 Fax: (585) 385-1768

E-mail: Web:

USB Dial-up Modems & Modules 3KV Isolation, IEC60601-1 (Medical) Compl.

Available Serial TTL or RS232 interface 3.3V, 48V or Power-over-Ethernet (PoE) support IEEE802.3 compliant 10/100BaseT network interface, auto detect TCP/IP, UDP, Telnet, HTTP, IGMP and ARP support DHCP and static IP support LED pin for monitoring LAN and link activity Phone: (408) 383-9006 Fax: (408) 383-9007

E-mail: Web:


Based on Altera® Cyclone® III Supports TI TUSB1310 USB 3.0 standard B connector RoHS compliant USB3.0 Device Controller IP provided


Supports gigabit serial fabrics including PCIe, RapidIO, and Aurora Two 12-bit 500 MHz A/Ds One digital Upconverter Two 16-bit 800 MHz D/As Xilinx Virtex-6 FPGA Clock/sync bus for multiboard synchronization COTS and ruggedized versions Also available in XMC and PCIe formats

Saelig Company, Inc. E-mail: Web:

Phone: (888) 772-3544 Fax: (585) 385-1768

E-mail: Web:

editor’s report Precise Timing for Small Modules

An Atomic Clock in Miniature Ushers in Precise Timing for Small Modules It doesn’t receive signals from Fort Collins. It measures time against the element Cesium in a space the size of an IC package and may open up a world of new applications. by Tom Williams, Editor-in-Chief


magine a small form factor singleboard computer with an actual atomic clock on board. Well, imagine no longer because one is now available from Symmetricom, a specialist in and supplier of precision time instruments and the only supplier of commercial Cesium oscillatorbased timing devices, specifically the newest version called the SA.45s Chip Scale Atomic Clock (CSAC). The CSAC comes in a package measuring only 1.6 x 1.39 x 0.45 inches high and consuming less than 115 mW while operating on a 3.3V power supply (Figure 1). According to Symmetricom Director of New Business Development Steve Fossi, the accuracy falls within 1/10 second over an 80-year human life span. It amounts to a stability of <2 x 10-10 @ 1 second. Atomic clocks in considerably larger form factors have been used for many years in communication applications such as network synchronization where somewhat higher accuracy is required. For that, Symmetricom offers its Miniature Atomic Clock (MAC), which operates on 5W and is about three times larger in volume than the CSAC. However, the gains in size, weight and power (SWaP) open a much larger world of applications for mobile and



battery operated systems that can take advantage of precise timing—a few of which have already been identified but many of which remain yet to be imagined. The CSAC is built with a physics package containing Cesium in a resonance cell that is heated so that the element is diffused as a vapor and can be excited by the application of a vertical-cavity surface emitting laser (VCSEL). The laser is tuned to a very precise optical frequency and is controlled by a microwave synthesizer to tune to the resonance of the Cesium. The entire physics package is powered by only 10 mW (Figure 2). As the Cesium absorbs the laser light, its electrons are raised to the next quantum level and then decay to emit photons, basically scattering in all directions. The laser light that gets through is picked up by a photodetector. The photodetector output signal drives a feedback loop that tunes the local oscillator toward the frequency associated with the lowest amount of light detected. That means that the Cesium is at maximum absorption and the output frequency is therefore in resonance with the element. The output of the tuned local oscillator is also the clock signal, which represents the stability of the atomic resonance.

Figure 1 The Symmetricom SA.45s chip scale atomic clock takes up just 16 cc in volume, runs on less than 115 mW at 3.3V and provides a 10 MHz CMOS-compatible output.

The entire physics package is hermetically sealed within a double-layer magnetic shield and braised to the substrate with connectors that fit onto the small circuit board that contains the other components of the CSAC (Figure 3). There is an extended temperature range (-40° to +85°C), which also draws slightly more power (<125 mW) and with a shorter MTBF. However the CSAC can also be programmed to operate in ultralow-power mode—averaging under 50 mW. In this mode, the physics package shuts down and the unit operates as a freerunning oscillator. Periodically, the physics package is turned back on and after a warm-up of less than 120 seconds it “redisciplines” the local oscillator. CSAC was originally a DARPA program whose goal was to develop an atomic clock that was 100 times smaller and used 100 times less power than existing technologies. As the program progressed, Symmetricom decided to use its own investment to commercialize the technology and accelerate development. Of course, this isn’t a clock in the sense that it will tell you to the nanosecond what time it is in Cleveland, but a highly precise time reference that can be used for control and synchronization of a vast number of possible applications. It can be powered off for considerable lengths of time and still be accurate upon being repowered. Atomic time sources are finding application in an increasing number of areas, one of the best known of which are GPS satellites where the time reference is required for accurate location. GPS satellites must periodically correct for the effects of relativity since their speed causes

editor’s report

Photodetector Upper Heater/Suspension Resonance Cell Waveplate Spacer Lower Heater/Suspension VCSEL

Figure 2 The physics package contains the VCSEL laser, the resonance cell with Cesium vapor, heater and photodetector and mounts on the 1.6 x 1.39 inch circuit board of the CSAC.

Error Signal

their onboard clocks to run at a slower rate relative to ground-based atomic clocks. Such atomic clocks, also designed by Symmetricom, have daunting requirements in terms of ruggedization, radiation hardening and magnetic shielding. All of this experience has, according to Fossi, been of great use in designing the CSAC. One major advantage of a super precise time signal that is also small and mobile is the ability to maintain synchronization with other devices that are not connected by either wired or wireless links—those which do not share a common clock reference signal as we are accustomed to in many applications. One such application under development for the military is a dismounted backpack jamming system for countering things like IEDs, which are the plague of troops in Iraq and Afghanistan. The roadside devices are typically set off by means of a remote radio signal such as a cell phone. Jamming such signals is vital to many operations. The problem is that generally jamming radio signals in a given area may well cut off the enemy detonation signals, but it also jams friendly communications. Another problem is that field jammers are mounted on vehicles while some 70 percent of all patrols are on foot. What is needed is a way to a) make jammers portable without unduly loading already heavily burdened individual soldiers and b) effectively jam IEDs and still allow needed radio traffic among friendlies. So how can CSAC address this problem? The light weight and low power consumption are pretty obvious, but what does it do to address the problem of communicating while jamming enemy signals? The answer is precise time synchronization between portable jamming units. Since the units are not connected, they need to be able to insert precisely coordinated time slots in which the jamming signal is turned off and communication signals can be sent. Synching up the units at the beginning of the mission will mean they are exactly on the same time base throughout and can execute whatever algorithms may be applied to the insertion of communication slots (frequency, duration, coded sequences, etc.) interspersing the jamming operations.

Physics Package

Control Loop

Microwave Synthesizer

Clock Output LO Tuning Local Oscillator

Figure 3 Atomic resonance is inherently more stabile than a local oscillator, so a control loop continuously steers the local oscillator frequency to atomic resonance and the RF output—typically 10 MHz—embodies the stability of atomic resonance.

Another commercial application involves undersea seismic analysis searching for oil and gas deposits. On land, this involves distributing sensors on the ground, whose location is known via GPS positioning and which synchronize to the time based on the GPS signal as well. This is not possible under water. Sensors can send data to an underwater antenna on a ship, but cannot interact with devices above water, let alone in space. If underwater sensors are placed by means of a remote submersible, are exactly synchronized with each other and with the systems on the ship, then the time

differentials between the arriving systems can be recorded and post-processed to yield a three-dimensional image of the different densities of material beneath the sea floor. This is basically the same sort of post processing that is done with seismic signals for surface analysis. The difference is the way the relative location of the sensors and the time stamping of the signals is carried out. Symmetricom San Jose, CA. (408) 428-7907. [].



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FPGAs and CPUs: Allies or Rivals?



technology in context

MPUs Team with FPGAs to Solve Real-Time System Requirements With today’s MPUs and FPGAs, it’s no longer a question of either/or. The two technologies can complement one another in solving data flow intensive applications using FPGA blocks that also benefit from the control functions of a processor. by Lawrence Getman, Xilinx


hen choosing the heart of a processing system, many embedded designers have the impression that they must pick either an FPGA or a microprocessor. In reality, design teams can often use the two technologies synergistically to yield optimal designs in terms of performance, scalability and minimum bill of materials. Today, applications like motor control or vision systems can best be implemented with an FPGA handling time-critical inner-loop functions alongside a microprocessor that handles the remainder of the application. The real question for the designer is not which to choose but how to best partition their system to realize the full potential of this powerful combination of technologies. Looking back to the FPGAs available in the mid-1980s, design teams primarily used FPGAs as glue logic—helping the processor work with other chips or discrete circuitry in a system. FPGAs allowed companies to build a more integrated design with a lower bill of materials. Moreover, the reprogrammable aspect of FPGAs meant that design teams could easily fix bugs in their design or even add last-minute features. Moving into the 1990s, FPGAs began to take on increasingly complex control tasks. The parallelism inherent in FPGA fabrics made the devices a good match for complex control algorithms and high-performance data plane applications that are DSP heavy. With its many I/Os and plethora of resources, an FPGA can handle many inputs for sensors, process the data in real time for even the most challenging of tasks, and output the results to drive multiple control elements in parallel. And again, reprogrammability over the entire design lifecycle has always been a key attribute for both bug fixes and updates. As FPGAs have grown larger and faster over the last decade, they have assumed a more central role in embedded processing applications. In many instances, design teams implement a soft-core microprocessor in the FPGA fabric. Designers customize these soft cores and the surrounding logic to the task at hand. In some cases, FPGA vendors have RTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


technology in context

FSL_Data Read 20

10 LSB

ROM sin(d) 1024 x 32

FSL_Data Write

fmul fadd

10 MSB

10 MSB

ROM cos(x) 1024 x 32

SRL 16x 10

ROM sin(x) 1024 x 32


FSL_Write SRL 16

Figure 1 This is an example of a simple implementation of an accelerator design in an FPGA used to calculate a sine value.

already implemented hardened processor cores alongside FPGA fabric in their FPGAs. Recently, FPGA vendors have taken this idea a step further, developing ICs that now include full ARM processing subsystems along with hardened peripherals, memory controllers, etc.—all tightly integrated with the FPGA fabric. This marriage of hardened processor core within the fabric gives designers the ease of programming with a familiar real-time operating system (RTOS), yet has opened up new doors for customization of the overall processing system, with much tighter linkage between data and control processing. Given the brief history of FPGA evolution, let’s examine how the logic fabric can be used alongside either a dedicated microprocessor or a processor integrated into the FPGA. We’ll focus on ways the programmable fabric can handle performance-intensive tasks.

Motor Control

Applications such as motor control require a control system design that constantly monitors data such as speed and



torque and almost instantaneously adjusts the voltage or current sent to the motor depending on the motor type and application. Analog control systems operate continuously and were long used in such applications. But it is almost impossible to implement some of the most advanced control scenarios—such as sensorless control and field-oriented control—in the analog domain. Therefore, most modern motor control systems convert inputs into the digital domain, handle the math-intensive algorithms in the digital domain and drive the motor through a conversion back into the analog domain. Numerous manufacturers offer microcontrollers (MCUs) and microprocessors that are in some way customized to the application. For instance, typical MCUs might integrate multiple analog-to-digital and digital-to-analog converters, many supporting floating-point math. Even with the wide array of customized processor systems, many applications still need some crucial additional hardware customization. Certainly processors can handle some lower-performance motor-control

applications in software. Software algorithms, perhaps running under an RTOS to handle complex connectivity like Ethernet stacks, for example, may suffice, depending on a number of factors such as complexity of the control algorithm, the speed/performance of the processors and the effectiveness of floating-point support. If the software implementation can meet the latency and precision requirements, then the pure-software approach is definitely the easiest and most cost-effective option. However, software-only approaches often fall short of meeting the real-time control requirements associated with more complex algorithms. Even if a system design has low-latency characteristics relative to interrupt response, it may not provide suitable performance in handling the complex math. A Xilinx customer, for example, was developing a precision milling system destined to manufacture telescopic equipment. The design team ran into limitations with a software-control algorithm and turned to an FPGA to implement a hardware accelerator to solve the problem. An FPGA accelerator can enable control scenarios based on precise ramp profiles for acceleration and deceleration, and can be easily interfaced to an external processor or to one integrated in the FPGA. Trigonometric functions represent one item that may be ripe for acceleration. Trigonometry is used to calculate motor position based on a variety of input. Some simple controllers may get position input from a Hall sensor, but more complex sensorless systems may have little more than back EMF (electromotive force) that’s captured from the drive circuit to use in determining motor position. Certainly, floating-point units that are increasingly common in embedded processors can execute trigonometric functions faster than processors that lack floating-point support. But what if you need the system to operate on multiple inputs simultaneously? Also, a design may need double-precision capability whereas some embedded processors only support

technology in context

a single-precision capability, and in most cases the floating-point unit is simply not fast enough for controller requirements. While an FPGA has no inherent magic trigonometric capability, you can use the DSP slices in a fabric to accelerate such operations. For example, a design can store the results of functions like sine (x) and cos (x) in BRAM (block RAM). The design can then use the multipliers and adders in DSP slices to output a result that’s sent back to the processor. Figure 1 depicts a simple implementation of an accelerator design that a design team created to calculate a sine value. The implementation uses the Fast Simplex Link (FSL) interface that’s available in Xilinx’s FPGA design tools to accept inputs from the processor and output the results back to the processor. An accelerator like this one can be augmented in terms of a pipeline and broadened to support a greater number of inputs. FIFO buffers on the inputs and outputs add the pipelining that allows the processor to continue to send data to the accelerator separately from fetching the results. A design team simply needs to replicate the accelerator to add parallel support for more inputs, or the team can add slightly modified accelerators in parallel to handle different trigonometric functions. Hardening the trigonometric functions in the FPGA fabric can impact a design in several ways. For example, a design team can rely on a lower-performance, lower-power, lower-cost processor while achieving a system with superior performance. The design team also has the option of pairing the accelerator implemented in an FPGA fabric alongside a soft processor that’s also implemented in the fabric. Even in a modestly sized FPGA family, a design team can implement a 32-bit soft core processor that’s equipped with functions such as a single-precision floatingpoint unit and capable of running a variety of standard processor OSs and embedded tools. A Spartan FPGA-class device can implement a processor with a system clock in the 100 to 200 MHz range. Since

accelerator yields 2x2-pixel kernel elements using four DSP blocks in the FPGA. Then the accelerator converts the pixel kernel into Y, Cr and Cb components. Both the color and monochrome image data is processed by separate denoise accelerator blocks. The monochrome data passes through an accelerator that can warp and rotate the image to prepare it for fusion with the color image. Then a fusion block combines the two data sets. The fused image can be output to a monitor and fed back to the microprocessor that controls the entire operation. The microprocessor in the iVeia system performs statistical calculations on the various intermediate image results and adaptively updates the coefficients for each image-processing block. The microprocessor also serves as the system controller, and interfaces with other, external systems via Gigabit Ethernet. The processor can run a user-accessible operating system such as Linux, while the FPGA accelerators ensure real-time processing of image data. A system such as the iVeia example could use either an internal or an external processor. iVeia ultimately chose to use a Virtex FPGA that integrates a hardwired PowerPC processor. Such FPGA ICs integrate a processor that can operate at 400

the soft-processor option is typically integrated into an existing FPGA, it can further reduce the bill of materials.

Stereo Image Processing

Let’s examine another imaging-centric example to further illustrate how processors and FPGAs can work together. iVeia set out to design a credit-card-size printedcircuit board for a highly compact imageprocessing system that it could sell as an off-the-shelf product that its customers could match to an application. iVeia sought both a tightly integrated design and one that could adapt to, and scale across, a broad set of image-processing applications. The iVeia design depicted in Figure 3 accepts inputs from two cameras. Depending on the end application, the system might use one color camera and a higher-resolution monochrome camera. Or perhaps the second camera might be an infrared monochrome model for night vision. The design handles most of the timecritical image-processing task in the FPGA fabric. The input blocks decode the camera inputs into 24-bit data elements and framecontrol signals. A second-stage accelerator handles formatting and scaling. The color-image path proceeds through a demosaic accelerator block that also handles color-space conversion. The A CameraLink B Decode C

A CameraLink B Decode C

Format/ Scale

Demosaic/ Colorspace Conversion

Cr Cb


CCIR656 Encoder/ NTSC Interface

Denoise Filter Format/ Scale

Warp (Rotate, etc...)

Denoise Filter




ff oe


Memory Controller

External Memory

Processor Gigabit Ethernet Interface

Figure 2 In this small but mighty stereo image-processing system, iVeia designers assigned most of the heavy-lifting, time-critical image-processing tasks to the FPGA fabric and used the on-chip PowerPC MPU core to run Linux, with a focus on system management. RTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


technology in context

to 550 MHz clock speeds, as opposed to the soft cores mentioned earlier that max out in the 200 MHz range. The iVeia implementation provides its customers significant flexibility in terms of customizing the image-processing platform. The design leaves two-thirds of the FPGA logic unused so that customers can add their own accelerator blocks. Moreover, iVeia provides the option of supplying a more feature-rich product with an FPGA that integrates two PowerPC cores to boost the amount of traditional embedded processing bandwidth.

Future-Proof Designs

Design teams undertaking a system design that combines embedded processing and FPGA accelerator elements should also consider next-generation requirements when contemplating an architecture. Some designers may think that applications realized purely in software on an embedded processor are the only path toward a design that can be reused and migrated across generations of hardware. In reality, FPGAs provide an ideal platform to achieve designs realized in both hardware and software that are easily portable and reusable at both a block and system level. One key is the use of the latest advanced microcontroller bus architecture (AMBA) AXI bus technology. AMBA 4 is the fourth generation of the open standard AMBA developed by ARM as an on-chip bus for SoCs. AMBA 4 adds three new interface protocols: AXI4, maximizing performance and power efficiency; AXI4Lite; and AXI4-Stream. The latter two are ideal for implementation in an FPGA. Xilinx worked closely with ARM on AXI4 to develop extensions tailored for the FPGA, and has standardized on AXI as the primary interconnect for all IP blocks. Detailed information on AXI4 and FPGA-tailored AXI4-Lite and AXI4Stream protocol specifications is available from the ARM website, The AXI4 interconnect provides a non-blocking, point-to-point fabric-based architecture that ensures timely data movement between masters and slaves,



and makes IP blocks reusable in future designs. This architecture allows the interconnect bandwidth to support the master’s peak bandwidth without requiring an increase in frequency of the interconnect. Designers can use both full DMA-capable AXI master implementations and AXI Lite implementations for slave operations in their FPGA-based designs. FPGA accelerators developed using AXI will be readily reusable in Xilinx’s next-generation Extensible Processing Platform SoCs due this year. The Extensible Processing Platform (EPP) provides a new class of product that tightly couples a dual-core ARM-Cortex-A9-based processing system to programmable logic through high-bandwidth AXI interfaces. The EPP SoCs use a processor-first, programmable logic-second architecture. As the system master, the ARM processor core boots first and then fully or partially configures the programmable logic. The processing system is the controller of the device. Keeping the processing and programmable-logic domains on separate power planes enables the processing system to control the power consumption of the programmable logic. Indeed, the processing system can completely shut down the programmable logic if need be. The EPP will further accelerate the system design process by providing a system behavior and programming model similar to ASSPs. The ARM CPU and AMBA interfaces provide a known programming model for software development. The processor boots at power-up and has its own set of dedicated pins to enable access to boot devices and system communications as a system processor requires. There is no need to configure the programmable logic to start doing traditional software coding. This allows software design teams to immediately begin the development process as they would on any standalone processor. At the same time, the hardware team can begin developing in parallel to migrate accelerator blocks they’ve previously created for Spartan and Virtex FPGAs to the new platform. Embedded-design teams may need to

rethink their approach to how an embedded processor handles data-rich applications with real-time performance requirements. Certainly a processor alone, combined with an RTOS, can handle many tasks. But in a growing number of applications, the data load will overwhelm many processors regardless of the low-latency attributes of the system in terms of interrupt response. FPGA accelerator blocks can take on the real-time data load using a combination of DSP slices and logic blocks configured in an application-specific manner. The FPGA architecture can scale in terms of parallel data paths that handle multiple sets of inputs simultaneously. FPGAs excel in sequential data-flow applications where accelerator blocks are cascaded while the embedded processor handles system management and adjusts operations by providing coefficients to the FPGA blocks taking care of the real-time data flow. Given where FPGAs are moving with regard to powerful, integrated processing subsystems that can run a variety of OSs and embedded tools; support from new classes of ESL tools that enable hardwareaware C programmers to program the FPGA fabric; and the continued drive down Moore’s Law providing more logic and lower cost, the future definitely seems exciting for the next generation of embedded designers using FPGAs as their palette of choice. Xilinx San Jose, CA. (408) 559-7778. []. iVeia Annapolis, MD. (410) 858-4560. [].

Expanding Upon the Intel® Atom™ Processor Avnet Electronics Marketing has combined an Emerson Network Power Nano-ITX motherboard that provides a complete Intel® Atom™ processor E640-based embedded system with a Xilinx® Spartan®-6 FPGA PCI Express (PCIe) daughter card for easy peripheral expansion. A reference design, based on an included version of the Microsoft® Windows® Embedded Standard 7 operating system, shows developers how to easily add custom FPGAbased peripherals to user applications.

To purchase this kit, visit or call 800.332.8638.

Nano-ITX/Xilinx® Spartan®-6 FPGA Development Kit Features tEmerson Nano-ITX-315 motherboard tXilinx Spartan-6 FPGA PCIe board tFPGA Mezzanine Card (FMC) connector for expansion modules tGPIO connector for custom peripheral or LCD panel interfaces tTwo independent memory banks of DDR3 SDRAM tMaxim SHA-1 EEPROM for FPGA design security tDownloadable documentation and reference designs

©Avnet, Inc. 2011. All rights reserved. AVNET is a registered trademark of Avnet, Inc. All other brands are the property of their respective owners.

Technology in


FPGAs and CPUs: Allies or Rivals?

Microprocessors or FPGAs? Making the Right Choice The “right choice” is not always either/or. The right choice can be to combine the best of both worlds by analyzing which strengths of FPGA and CPU best fit the different demands of the application.

by Steve Edwards, Curtiss-Wright Controls Embedded Computing


Motorola 7400 200 nm 400 MHz

FPGA Logic (>10X)

Xilinx Virtex-II V8000 130 nm 47K cells

Xilinx Virtex-II Pro VP100 130 nm 90K cells 20 serial links

Freescale 8640D 90 nm SOI 1.25 GHz 2 cores

Freescale P4080 45 nm 1.5 GHz 8 cores



Freescale 7448 90 nm 1 GHz MHz


Micro-Processor Performance (~6X)

Motorola 7410 180 nm 500 MHz



Intel Core i7 45 nm 2.5 GHz 2 cores



Growth Analysis


here has been stunning growth in the size and performance of FPGAs in recent years thanks to a number of factors, including the aggressive adoption of finer chip geometries down to 28nm, higher levels of integration, the use of faster serial and communication links, specialized cores, enhanced logic and innovative designs from the major FPGA vendors. Meanwhile, the overall performance growth curve of traditional microprocessors has somewhat flattened due to power density hurdles, which have limited clock rates to around 1.5-2 GHz because the faster the new processors go the hotter they get. This power density barrier has been somewhat mitigated by the emergence of multicore processors, but as the number of cores increases these devices bring their own set of issues including how to make optimal use of their parallelism while operating systems and automatic parallelization tools lag far behind. Improvements in FPGAs have driven a huge increase in their use in space, weight and power (SWaP) constrained embedded computing systems for military and aerospace applications. They are

Xilinx Virtex-II Pro FX 140 90 nm 140K cells 192 DSP blocks 24 serial links

Xilinx Virtex-5 SX240T 65 nm 240K cells 1056 DSP blocks 24 serial links

Xilinx Virtex-6 SX475T 40 nm 476K cells 2016 DSP blocks 36 serial links

Figure 1 Chart comparing the amount of logic needed to implement several different fixed point resolution calculations and floating point.

ideal for addressing many classes of military applications, such as Radar, SIGINT, image processing and signal processing where high-performance DSP and other vector or matrix processing is required. SWaP performance rather than cost is the key driver for this. Given this trend, system designers are more frequently asking the question, “Should I use FPGAs or microprocessors for my next embedded

computing project?” And the answer today is, “it depends.” FPGAs are an increasingly attractive solution path for demanding applications due to their ability to handle massively parallel processing. FPGAs tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform sometimes tens of thousands of calculations per clock cycle

technology in context





MPC 8640D

80 Pairs

Core Functions FPGA

90 Pairs 10



Xilinx Virtex-6 SX475T/ LX550T (FPGA 1)

Xilinx Virtex-6 SX475T/ LX550T (FPGA 2)

2 Aurora x4/(P2) 2 Aurora x4/(1-P4, 1-P5)



20 pairs (P5)


20 pairs (P5)

while operating in the low “tens of watts” range of power. Compared to FPGAs, microprocessors that operate in the same power range have significantly lower processing functionality. Typically, a similarly power rated microprocessor may run at 1-2 GHz clock rate, or roughly 4 or 5 times as fast as an FPGA, but it will be much more limited in how many operations it can perform per clock cycle, with a maximum typically in the range of four or eight operations per clock. This means that FPGAs can provide 50 to 100 times the performance per watt of power consumed than a microprocessor. This might seem to give FPGAs an unbeatable edge over microprocessors, but the advantage of FPGAs in these applications is, unfortunately, not that clear cut. Despite their apparent computational strengths, there are three key factors that determine the utility of FPGAs for a particular application. These factors are algorithm suitability, floating point vs. fixed point number representation, and general difficulties associated with developing FPGA software. The embedded system designer must carefully weigh the benefits of FPGAs against the real-world limits and the challenges of hosting their application on these devices. The first question to consider is for which types of algorithms FPGAs are best suited? FPGAs work best on problems that can be described as “embarrassingly parallel,” that is, problems that can be easily and efficiently divided into many parallel, often repetitive, computational tasks. Many applications in the military and aerospace environment fall into this class of problem, including radar range and azimuth compression, beamforming and image processing. On the other hand, there are types of computational problems for which FPGAs are not ideal, such as target classification and moving target indication problems. Problems like these, that are by nature unpredictable and dynamic, are much better performed on traditional micro-

8 diff pairs 4-(P3) 4-(P6)

PCIe x 8 DIO sRIO x 4 GbE Local Bus Control

PCIe 4 sRIO GbE 2 Aurora x4/(P2) x8 x4/(P1) (P4) 2 Aurora (P5) 2 B-T x4/(1-P5, 1-P6) 2 B-X LVDS SSTL 15 (20 pairs) RocketIO x4, 5.0 GHz RocketIO x12, 5.0 GHz

Figure 2 Champ-FX3.

processors because they require a more dynamic type of parallelization that is unsuitable for FPGAs, whose strongpoint is repetitive operations. With the advent of multicore processors that will soon be offered with 16, 32, or more cores, the question of how parallel an algorithm is will become more and more important. With more cores microprocessors become increasingly less suitable to address dynamic parallelization problems because the challenge of distributing the problem between the various cores can become intractable.

A second key issue when considering a choice between FPGAs and microprocessors, is the fact that FPGAs are not particularly well suited to floating point calculations, which microprocessors address with well developed vector math engines (Intel’s AVX and Power Architecture’s Altivec). While FPGAs can perform these types of calculations, it requires an undue amount of logic to implement them, which then limits the calculation density of the FPGA and negates much its computational advantage and value. If an application requires high-precision floating RTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


technology in context

point calculations, then it is probably not a good candidate for implementation on an FPGA. Even high-precision fixed-point calculations require a large quantity of logic cells to implement (Figure 1). The third key factor in determining whether an FPGA or a microprocessor is better suited for a project is the degree of difficulty that confronts a system designer


Untitled-5 1


tasked with implementing the application and the talent and resources available for the work. The challenges of designing with traditional microprocessors are well established and long familiar. On the other hand, while FPGA development tools have improved dramatically over the last few years, it still takes specialized talent to develop code for an FPGA. And even

2/17/09 4:47:07 PM

with expert talent, FPGA development often takes much longer than an equivalent development task for a microprocessor using a high-level language like C or C++. This is partly due to the time and tedium demands of the iterative nature of FPGA code development and the associated long synthesis/simulation/execution design cycle. System developers need to weigh the computational or SWaP density benefits that an FPGA brings to an application against the cost of development. In addition to these three main issues, there are other less critical considerations, such as which sensor interfaces are required by an application, which may also play into the FPGA vs. microprocessor decision. For example, if custom or legacy interfaces such as serial front panel data port (SFPDP) are needed for the application and which may not be supported on a modern processor, it might be preferable to use an FPGA. FPGAs have an inherent flexibility that enables them to be tailored to connect directly to a sensor stream as in the above case of legacy or custom interfaces. Microprocessors are limited to the interfaces provided on-chip, such as PCI Express, Serial RapidIO, or Gigabit Ethernet. FPGAs, on the other hand, often provide high-speed SERDES links that can be configured as a wide range of standard interfaces. In addition, the large number of discrete I/O pins on an FPGA can often be used to implement standard or custom parallel bus interfaces. When this I/O flexibility is combined with directly attached memories, SRAM for speed and random-access, SDRAM for memory depth, etc., FPGAs can be a powerful tool for front-end processing and a much better choice than a microprocessor. Once these factors have been weighed, it is clear that both FPGAs and microprocessors have clear, competitive advantages for different applications. Given all this, it seems that a system designer might have difficulty deciding whether to pick FPGAs or microprocessors for their application. The good news is that the designer can, in fact, have both. In the past, systems tended to be homogeneousâ&#x20AC;&#x201D;that is, composed of one type of processing element. Today, systems designers have a wide range of products to choose from and can often

technology in context

mix-and-match computing components to get just the right mix of computing and I/O to meet their application, SWaP and ruggedization requirements. They can choose from a mixture of board types based on a common communications fabric like Serial RapidIO or PCI Express. Another option, which provides the best of both worlds, is a hybrid FPGA/ microprocessor-based board like CurtissWright Controls’s CHAMP-FX3. This rugged OpenVPX 6U VPX board features dual Xilinx Virtex-6 FPGAs and an AltiVec-enabled dual-core Freescale Power Architecture MPC8640D processor (Figure 2). It provides dense FPGA resources combined with general-purpose processing, I/O flexibility and support for multiprocessing applications to speed and simplify the integration of advanced digital signal and image processing into embedded systems designed for demanding Radar Processing, Signal Intelligence (SIGINT), ISR, Image Processing, or Electronic Warfare applications. Using a hybrid FPGA/microprocessor board, designers can customize their system, providing FPGA components where they make sense with more general-purpose microprocessors or DSPs for the portions of an application for which they are best suited, all provided by standards-based components. This is an especially powerful approach when there is communications middleware and validated software drivers available to provide all of the common data movement and synchronization functions. Today’s embedded computing system designer has a wide range of computational and I/O components to choose from in a number of standards-based form factors. Suppliers are offering more choices with greater flexibility to mix components to solve any particular problem. In the near future, the market will likely see more and more product type fragmentation, with a myriad of different mixes of microprocessors and FPGAs offered on both the component and the board level. FPGAs will likely feature many features of traditional microprocessors and vice versa. While more options will surely make the decision process more complex, the wider range of choices in FPGAs and

microprocessors promises to empower innovative designers, enabling them to solve more difficult problems than they could solve before. Curtiss-Wright Controls Embedded Computing Ashburn, VA. (613) 254-5112. [].


Signal Processing HW IP & FrameWorks Development Tools Systems & Services

7MQTPMJ]*4+%-RXIKVEXMSRERH-QTPIQIRXEXMSR [MXL&MXX;EVI«W%80%28M7*VEQI;SVO Implementing complex signal processing on FPGAs? No need to spend most of your design effort on infrastructure and integration. BittWare’s ATLANTiS FrameWork provides a simpler, more efficient approach: s Follows a software-like FPGA development methodology s Provides flexible components, reconfigurable at build time and/or run-time s Allows straight-forward integration of components s Enables design portability and code re-use among different Altera FPGAs and BittWare boards Lower your development costs and decrease your time-to-market with BittWare, the essential building blocks for your innovative solutions.

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2/11/11 4:33:19 PM RTC MAGAZINE FEBRUARY 2011

Technology in


FPGAs and CPUs: Allies or Rivals?

Next-Generation SoC Platform for Terrestrial and Space Applications Developed in collaboration with UMC, the 65nm embedded flash process enables the development of programmable SoCs with an order of magnitude greater logic density and twice the performance with less than half the power of previous generations. by Esam Elashmawi, Microsemi


icrosemiâ&#x20AC;&#x2122;s SoC Product Group (formerly Actel) has completed a two-year technology development effort to produce a platform for its next-generation systems on chips (SoCs). With the acquisition of Actel, Microsemi adds customizable systems on chips (SoC) to its portfolio of high-performance, highreliability analog/RF devices and mixed signal integrated circuits. The combined companies share a common focus on defense, security and industrial markets, providing high-reliability solutions for both terrestrial and space applications. With this focus and alliance, a new platform is needed for future programmable SoC developmentâ&#x20AC;&#x201D;a platform that can address the requirements of both space and highreliability terrestrial applications. In November 2010, Microsemi, a manufacturer of high-performance analog/mixed signal integrated circuits, highreliability semiconductors and RF subsystems, acquired Actel. As a result of the integration, Actel is now the SoC Products Group of Microsemi. Both companies have long targeted the same markets with their products (se-








Figure 1 With the acquisition of Actel by Microsemi, elements from both companies are being brought together to create a new generation of customizable systems on chip.

curity, defense, aerospace and industrial), often doing business with the same customers. Moreover, both companies have

a shared vision of developing low power, highly reliable, highly secure products. With the acquisition, there is a renewed

technology in context

focus on developing an SoC platform that can address the needs of terrestrial applications as well as those for space.

ADD_SUB A[17:0]


Requirements for a NextGeneration SoC Platform

Since no single product can address all market needs, in developing the nextgeneration SoC platform, the designers focused on addressing specific market needs. For the terrestrial market, the choice is between addressing the needs of the datapath or the requirements for sense and control. Datapath needs are seen primarily in communications markets, where there is a need for extremely dense logic, high-performance, abundant block RAM, and signal processing at the expense of power and integration. This market segment typically has been addressed by large SRAM-based FPGAs. In contrast, the needs for sense and control as typified by industrial, medical and military/aerospace customers are integration, security and reliability rather than high density and speed. These applications typically have used a combination of FPGAs, microcontrollers and a number of ASSPs and discretes. As with the terrestrial market, the space market can be split into two distinct segments: control bus and data payload. The control bus is responsible for basic operation of the satellite, while the data payload performs the actual mission. Both of these areas require radiation tolerance and high reliability, but place different demands on programmable logic. The control bus performs fixed, must-not-fail functions that are typically implemented in nonvolatile, radiation-tolerant FPGAs. The payload typically needs greater density and performance that have often been addressed by ASICs. However, there is a desire for programmable logic in these applications.

65nm Flash – a New Foundation

In collaboration with UMC since 2008, Microsemi’s SoC Products Group has been working on a new process to power its next-generation products—65nm flash. This effort represents the industry’s first embedded 65nm flash process optimized for logic performance. The recently




SN [43:0]


CONST [43:0] SHIFT 17


SEL_CASC SN-1 [43:0]

Figure 2 Based on the new 65nm Flash technology, various functional blocks can be integrated into the fabric and implemented as either soft blocks or blocks of hard gates.

announced process offers some significant advantages over the company’s previous generation of flash process, providing twice the performance, an order of magnitude greater logic density and improved power performance. These improvements do not come at the expense of the traditional strengths of flash-based FPGAs, as this new flash platform still delivers single event upset (SEU) immunity for its configuration memory, as well as enhanced IP security. CMOS memory structures, for example static RAM cells and flip-flops, are susceptible to upset (change of state) when bombarded with high-energy particles. These particles can be alpha particles, neutrons, protons or a wide range of heavy ions, resulting from the collision of cosmic rays colliding with particles in the upper atmosphere and from secondary collisions from particles liberated by cosmic rays. When these charged particles strike the silicon substrate of an IC, they leave an ionization trail. Similarly, when a high-energy particle, for example a neutron, strikes the substrate, it collides with atoms in the substrate, liberating a shower of charged particles that then leave an ionization trail. This ionization can result in a charge sufficient enough to overpower the gate and cause a change in state (bit flip) of the memory element. This change in state is referred to as a single-event upset (SEU). The configuration memory of

SRAM-based FPGAs is susceptible to this type of upset, which could possibly cause changes in device functionality. The 65nm flash SoC platform is the basis for fourth-generation radiation-tolerant (RT) devices, offering designers up to 20 million gates and a large amount of flip-flops, memory and hardened embedded IP cores. The devices will include digital signal processing (DSP) blocks, PLLs and high-speed interfaces (such as SpaceWire, DDR2/3, PCI Express). The new architecture provides mitigation to total dose radiation and single event effects (SEE). The configuration switches are inherently immune to upsets, while the user flip-flops are implemented with built-in triple-module redundancy (TMR), eliminating the need for boardlevel mitigation schemes.

The New SoC Platform

At the heart of the new flash-based SoC platform is a new logic module. Unlike past flash architectures, the new platform is based on a logic module composed of one 4-input LUT and one D-type flipflop (Figure 1). A 4-input LUT structure was chosen over a 6-input LUT because of the better power versus performance curve. The new flash-based FPGA architecture is highly secure, immune to single event upset, IP-friendly and is also optimized for sense and control applications. The new architecture, when combined with the 65nm flash process, enRTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


technology in context

Flash Freeze + Power (Typical @ 25C) 0.350 IGLOO Power


Power (mWatts)

0.250 0.200 0.150 New 65nm Platform Power

0.100 0.050 0.000




Figure 3







Equivalent LUTs

The Freeze*Flash power-saving technology brought from Actelâ&#x20AC;&#x2122;s IGLOO product to the 65nm platform can offer even more effective power saving.

ables a great leap in density. New products developed using the platform will offer logic densities of tens of millions of gates, empowering designers to implement more complex designs. Moreover, the architecture was designed to be IP-friendly, enabling the integration of higher functions such as DSP blocks, SERDES, MCUs, analog blocks, etc. Basically any IP block that is compatible with the base 65nm UMC CMOS process is a possible candidate for integration. Blocks currently slated for inclusion in platform products are the ARM CortexM3 MCU, an 18 x 18 multiple/accumulate for DSP functions, plus SERDES functionality (Figure 2).

Optimized for Low Power

The need for low power operation is no longer just a concern for handheld/ portable devices. As system complexity grows, the need for reducing the power demand of individual devices increases. With this requirement in mind, the development team focused on reducing the dynamic power of the new flash platform, achieving a 65% reduction in dynamic power over the previous generation technology (Figure 3). But reducing dynamic power is only part of the solution for achieving lowpower operation. In any system, not all parts of the system need to operate 100% of the time. As a consequence, significant



power savings can be achieved by turning off parts of the system. Normally selectively powering down certain parts of the system is a complex task. However, this technique has been greatly simplified with Flash*Freeze technology. Introduced in earlier product generations, Flash*Freeze technology permits the easy entry and exit from an ultra-low-power mode, retaining SRAM and register data without a need to turn off supplies, I/Os , or clocks at the system level. For the 65nm flash platform, this capability has been enhanced and improved, adding more intelligent control of power within a device.

Security Built In

Microsemiâ&#x20AC;&#x2122;s SoC Group has a long history of supplying highly secure products, preventing overbuilding and IP theft. At its root, flash technology is secure. The microscopic size and sheer number of flash switches in a device make it essentially impossible to locate each cell and identify its programmed state. The new SoC platform builds on this security leadership, improving configuration security, as well as enhancing tamper protection. For example, hard IP (enhanced with optional soft IP) has been added to the platform to thwart attempts to use differential power analysis (DPA) to discover the internal workings of a design. Additional security and anti-tampering technologies are in the product plans.

Communication is essential in all systems. In addition to industry standard communication interfaces, such as USB, CAN, SPI, I2C and UARTs, the new platform also includes support of high-speed serial interfaces with the inclusion of SERDES functionality. When combined with the embedded, hard IP, this functionality enables the support for a wide range of serial communication standards such as PCI Express 2.0, XAUI and Gigabit Ethernet. This new process enables a range of new devices targeted at both terrestrial and space applications, offering an order of magnitude better density, higher performance and lower power over previous generations. Microsemi Irvine, CA. (800) 713-4113. [].

X-ES 2nd Generation Intel® Core™ i7 Processor Solutions: Delivering Innovation In 2010, Extreme Engineering Solutions, Inc. (X-ES) developed more Intel® Core™ i7 processor products based on VPX, CompactPCI, VME, CompactPCI Express, and XMC form factors than anyone in the industry. This year, X-ES has added solutions based on the 2nd generation Intel Core i7 processor. Providing products customers want, when they want them – that truly is innovation that performs. X-ES offers an extensive product portfolio that includes commercial and ruggedized single board computers, high-performance processor modules, multipurpose I/O modules, storage, backplanes, enclosures, and fully integrated systems. 2nd generation Intel Core i7 processor solutions available in a variety of form factors. Call or visit our website today.

technology in


From Verification to Compliance

Tracing Requirements through to Verification: Improve Current Practices for Standards Compliance Requirements traceability is essential for software verification. Actually implementing bidirectional traceability that adheres to standards requires analysis and implementation of the practices within a development organization. by Mark Pitchford, LDRA


ecent quality concerns are driving many industries to start looking seriously at ways to improve the quality of software development. Not surprisingly, there are marked differences in the quality of software in the different sectors. The automotive industry does a good job of listing all the requirements in a database and was the origin of the Motor Industry Software Reliability Association (MISRA) software coding standards. However, the railway and process industries have long had standards governing the entire development cycle of electrical, electronic and programmable electronic systems, including the need to track all requirements. The automotive sector has only recently introduced a draft standard for a similarly broad-based approach. By contrast, medical software guidelines are typically more in line with lowrisk applications, even when a software failure could result in serious physical injury or death. Despite this apparent disparity between medical software and other safety-critical standards, the case for software that has been proven to be reliable through standards compliance and



Software Requirements, & Defect Reports

Manage requirements; assign verification & debug tasks; track defects

Project Managers

Map requirements to architecture; generate defects

Requirements Traceability Matrix (RTM)

Model or Design Specification

Software Engineers

Code Base

Test Cases

Verifies requirements against test cases; generate defects Test Engineers

Implement requirements, map to code & verify design; generate defects Development & Build Engineers

Figure 1 RTM sits at the heart of the project defining and describing the interaction between the design, code, test and verification stages of development.

requirements-traceable process is becoming ever more compelling. The U.S. government is well aware of the incongruity of this situation and is considering ways to counter it with the Drug and Device Accountability Act. Recently, the FDA took punitive action

against Baxter Healthcare and their infusion pumps, which the FDA has forced the company to recall. The net result is that many medical device providers are being driven to improve their software development processes. A common concept in the standards

tech in systems

Tier 1

Graphics to High Level Requirements

Low Level requirements to code

High-Level Requirements

Requirements Traceability Matrix Tier 2 Model/Design Concepts

Legacy/ Hand Code

Software Specs

Requirements Traceability Matrix Tier 3

Implementation (Source/Assembly Code) Requirements Traceability Matrix

Static & Dynamic Analysis

Automated Test

Tier 4

Host Requirements Traceability Matrix

Tier 5 Target

Low Level to High-Level Requirements

Code & Quality Review Defects

Test cases to Low Level requirements

Test cases to Low Level requirements

Figure 2 The requirements traceability matrix (RTM) plays a central role in a development lifecycle model. Artifacts at all stages of development are linked directly to requirements matrix and changes within each phase automatically update the RTM so that overall development progress is evident from design through coding and test.

applied in the safety-critical sectors is the use of a tiered, risk-based approach for determining the criticality of each function within the system under development. Typically known as Safety Integrity Levels (SILs), there are usually four or five grades used to specify the necessary safety measures to avoid an unreasonable residual risk to the whole system or a system component. The SILs are assigned according to the risk of a hazardous event occurring based on the frequency of the situation, the impact of possible damage, and the extent to which the situation can be controlled or managed. For a company to make the transition to certified software, it must integrate the standardâ&#x20AC;&#x2122;s technical safety requirements into its design. To ensure that a design follows the standard, a company must be able to outline the fulfilment of these safety requirements from design through coding, testing and verification. To ease the adoption of this standard and manage the shift in requirements, many companies use gap analysis. Gap analysis begins by gathering and analyzing data to gauge the difference between where the business is currently and where

it wants to be. Gap analysis examines operating processes and generated artifacts, typically employing a third party for the assessment. The outcome will be notes and findings on which the company or individual project may act. Gap analysis enables companies to manage the implementation of a new process by evaluating the changes compliance to a standard requires of a system.

Requirements Management and Traceability

Requirements traceability is widely accepted as a development best practice to ensure that all requirements are implemented and that all development artifacts can be traced back to one or more requirements. For instance, the following quote from the automotive industry draft standard ISO/DIS 26262 requires bidirectional traceability and has a constant emphasis on the need for the derivation of one development tier from the one above it: Maintain Bidirectional Traceability of Requirements The intent of this specific practice is to maintain the bidirectional trace-

ability of requirements for each level of product decomposition. When the requirements are managed well, traceability can be established from the source requirement to its lower level requirements and from the lower level requirements back to their source. Such bidirectional traceability helps determine that all source requirements have been completely addressed and that all lower level requirements can be traced to a valid source. Requirements traceability can also cover the relationships to other entities such as intermediate and final work products, changes in design documentation, and test plans. While this is and always has been a laudable principle, last minute changes of requirements or code made to correct problems identified during test tend to put such ideals in disarray. Despite good intentions, many projects fall into a pattern of disjointed software development in which requirements, design, implementation and testing artifacts are produced from isolated development phases. Such isolation results in tenuous links between requirements, the development stages, and/or the development teams. The traditional view of software development shows each phase flowing into the next, perhaps with feedback to earlier phases, and a surrounding framework of configuration management and process (e.g., Agile, RUP). Traceability is assumed to be part of the relationships between phases. However, the reality is that while each individual phase may be conducted efficiently, the links between development tiers become increasingly poorly maintained over the duration of projects. The answer to this conundrum lies in the Requirements Traceability Matrix (RTM), which sits at the heart of any project even if it is not identified as such (Figure 1). Whether the links are physically recorded and managed, they still exist. For example, a developer creates a link simply by reading a design specification and using that to drive the implementation. This alternative view of the developRTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


Tech In Systems

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Untitled-1 1


5/13/10 3:34:59 PM

ment landscape illustrates the importance that should be attached to the RTM. Due to this fundamental centrality, it is vital that project managers place sufficient priority on investing in tooling for RTM construction. The RTM must also be represented explicitly in any lifecycle model to emphasise its importance, as Figure 2 illustrates. With this elevated focus, the RTM can be constructed and maintained efficiently and accurately. When the RTM becomes the center of the development process, it impacts on all stages of design from high-level requirements through to target-based deployment. The Tier 1 high-level requirements might consist of a definitive statement of the system to be developed. This tier may be subdivided depending on the scale and complexity of the system. Tier 2 describes the design of the system level defined by Tier 1. Above all, this level must establish links or traceability with Level 1 and begin the process of constructing the RTM. It involves the capture of low-level requirements, which are specific to the design and implementation and have no impact on the functional criteria of the system. Tier 3’s implementation refers to the source/assembly code developed in accordance with Tier 2. Verification activities include code rule checking and quality analysis. Maintenance of the RTM presents many challenges at this level as tracing requirements to source code files may not be specific enough and developers may need to link to individual functions. In many cases, the system is likely to involve several functions. Traceability of those functions back to Tier 2 requirements includes many-to-few relationships. It is very easy to overlook one or more of these relationships in a manually managed matrix. In Tier 4 host-based verification, formal verification begins. Using a test strategy that may be top down, bottom up or a combination of both, software simulation techniques help create automated test harnesses and test case generators as necessary. Test cases should be repeatable at Tier 5 if required. At this stage, we confirm that the

software is functioning as intended within its development environment, even though there is no guarantee it will work when in its target environment. However, testing in the host environment first allows the timeconsuming target test to merely confirm that the tests remain sound in the target environment. Tier 5’s target-based verification represents the on-target testing element of formal verification. This frequently consists of a simple confirmation that the host-based verification performed previously can be duplicated in the target environment, although some tests may only be applicable in that environment itself.

Incorporating the Standard

Obviously, any shift in current development practices requires change at a number of levels. Many companies use gap analysis to help them evolve from their current development practices. When evaluating current practices, it is often true that some degree of automation exists for gathering traceability information. However, automatic tracing to implementation and verification artifacts is typically weak. Where the gap between current working practices and those required to operate under safety-related standards is wide, much work needs to be done. Of course, the upside is that the scope for cost savings is potentially huge. Even ignoring the increasing pressures to adhere to standards, the techniques encouraged by them can be automated to provide much greater control of the development lifecycle, and the ability to find problems much earlier—which means cheaper, too. Using gap analysis, companies have an established method that isolates the areas in which they need to improve with respect to a standard. The results from the gap analysis allow the company to focus resources correctly and efficiently to achieve that improvement. When companies undergo gap analysis, the results reveal the level of maturity within each phase of the software development lifecycle and the amount of tool investment at each phase. Even when processes are mature and tools are adequate,

tech in systems

the greatest shortfall typically stems from a failure to establish traceability between the software development phases so that requirements directly link to design, code, test and verification stages of development. Gap analysis reveals the shortcomings in the system since even where each individual phase is well controlled and adequately tooled, traceability between the phases tends to be lacking. To compound that issue, a recent Forrester report noted that â&#x20AC;&#x153;Analyzing the interdependencies that software designs have with other cross-functional viewsâ&#x20AC;&#x201D;like linking a cameraâ&#x20AC;&#x2122;s zoom software with the electrical motor, the electronics processor, and the mechanical lens and bearingsâ&#x20AC;&#x201D;is often a late-stage process conducted only after the software is uploaded to the first physical prototype.â&#x20AC;? So, not only is traceability lacking between the various stages of development, but it is also lacking across engineering disciplines. For most commercially developed software, the construction and mainte-

nance of requirements traceability matrices is performed as a low-priority task and carried out via manual methods such as Excel spreadsheets. Given the strong correlation between requirements degradation and software defects, companies are becoming focused on ways to mitigate this risk through rigorous requirements and traceability management. As a result of the expense for traditional manual approaches to traceability, verification and certification, there is mounting pressure to find better ways to comply to standards while reducing costs. The transition to modern requirements engineering and traceability tools represents a way to maintain high-quality software and cost savings. Clearly the development of an RTM can be automated. When this is done, the return on investment from tools that manage requirements, support design and enable verification is significant. When the benefits of the construction of an RTM is pushed into the entire development pro-

cess through requirements traceability, much greater cost savings and process improvements are also available not only in the development level, but also after deployment where it helps avoid the costly litigation that takes place when software quality isnâ&#x20AC;&#x2122;t established and maintained. Gap analysis frequently highlights the fact that requirements traceability remains a low priority, and manual methods prone to error and omission often remain the primary approach. Consequently, when compliance to a specific standard is demanded, the time and effort required to construct a requirements traceability matrix (RTM) can be huge. LDRA Wirral, UK. +44 (0)151 649 9300. [].

Freescale MPC8536e Computer On Module The CSB1880, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, network oriented, PowerPC based Computer on a Module (COM). The CSB1880 provides a small, powerful and flexible engine for embedded Linux based GIGe networking applications of all kinds. y y y y y y y y y y

1.25GHz Superscalar e500 Core w/512KB L2 Cache 512MByte 64-Bit Wide DDR2-667 Memory with 8-Bit ECC 64MByte NOR with Secure ID, and 512MByte SLC NAND Two PCIe x4 Port (or one x4 and Two x2's) Two 10/100/1000 ports via BCM5482S to Copper/Fiber PHY Two SATA Gen 2 (1.5Gbit or 3.0Gbit/sec) Channels Three 480Mbit USB 2.0 Host Ports <7W Typical, 12W Maximum, <3W in Jog Mode 95mm x 95mm x 8mm (using 5mm COM Express Connector) Linux 2.6.x BSP with available 1 year of support

Now Available for direct order from Digi-Key The CSB1880 is manufactured in our in-house state of the art, lead-free surface mount manufacturing line. All products carry a 1-year warranty and are available in commercial and industrial temperature versions. Cogent also offers standard and custom carrier boards, plus royalty free licensing options for the CSB1880.

&2*(17 "ALWAYS COMPLETE" Untitled-1 1



1/14/11 9:32:23 AM RTC MAGAZINE FEBRUARY 2011

exploration r your goal eak directly page, the resource. hnology, nd products

technology deployed Data Acquisition with Small Modules

Data Acquisition Solutions Stack Up

who must interface to the real world for data acquisition, while ATX-type motherboards continue to give up ground as applications become smaller and more portable.

Form Factor Forensics

The 90 x 96 mm PC/104 form factor family, which includes the unifying factor of SUMIT-ISM, continues to offer expansion, flexibility, inclusion of legacy devices and ruggedness for an increasing range of data acquisition applications.

by Robert A. Burckle, WinSystems

panies providing solutions now

ation into products, technologies and companies. Whether your goal is to research the latest cation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ata Acquisition (DAQ) systems come in as many facets ce you require for whatever type of technology, and form factors as application areas. This is because syses and products you are searching for.

PC/104 stackable modules are known for their rugged design and small size. These selfstacking modules can serve as either a single mezzanine on top of an SBC or with multiple cards for even greater I/O requirements. During the past ten years, an abundance of new industry-standard and single-sourced form factors have posed challenges to the self-stacking 3.550” x 3.775” (90 x 96 mm) PC/104 single board computers (SBCs) and I/O modules. One worth comparing is the computer-onmodule (COM) phenomenon, which has crept into this space for high-volume applications. Yet each COM requires a new carrier board for all of the unique application-specific I/O circuits and connections, which incurs more NRE and resources than most projects can afford. Currently, the original legacy-friendly ETX COM (with ISA bus and serial ports) is giving way to high-speed legacy-free COM Express (“COMe”), but this is not a compatible upgrade path (different connectors, expansion buses and I/O). The smallest COMe outline measures 95 x 95 mm. Although similar to PC/104 in size,


tem designers need to consider a number of important issues such as size, performance, ruggedness, modularity, software support, connectors, packaging, operating temperature, long-term availability, sensor types and locations, network connectivity and power consumption as they decide upon their final system configuration. Data can be from the analog or digital domain or from remote sensors that have gathered information for further analysis and processing. Yet whether for portable data collection, medical instrumentation, laboratory analysis, environmental and utility management, pipeline, remote environmental monitoring, transportation or automated test equipment (ATE) for semiconductor, military/aerospace and telecommunications, DAQ system designers are under pressure Get Connected to reducewith sizecompanies and improve reliability while retaining application mentioned in this article. software compatibility. To that end, small form factor (SFF) computers and I/O cards continue to grow in popularity among OEMs

EBX 5.75x8’’



ISM 3.6x3.8’’


End of Article

PC/104 ISA Bus COMe Basic

COMe Compact



Figure 1 Get Connected with companies mentioned in this article.




Comparison of host computer form factors.

Technology deployed

Figure 2 This PC/104 DAQ module requires no calibration for the A/Ds and D/As.

Figure 3 This isolation and termination module fits directly on a PC/104 stack or can be mounted closer to the field wiring or signal sources.

the requirement to design and manufacture a custom, applicationspecific carrier board pushes the minimum cost and overall space to be similar to or greater than a PC/104 SBC with one I/O card. Yet a mezzanine card is still required if the potential for additional I/O modules needs to be added. In fact, some companies make carrier boards that support a COM on one side and a PC/104 interface on the other, since they want to have the option to take advantage of off-the-shelf, proven PC/104 I/O modules. Reduced legacy support, multiple incompatible pinout definitions, and the requirement to provide high voltage +12 VDC input reduce the likelihood that COM Express can make significant inroads into DAQ applications. Figure 1 compares popular SBC and COM form factors.

State of the Stack

Stackable data acquisition thrives in spite of the trend toward

computer-on-module (COM) CPUs in non-acquisition markets. This is largely because precision A/D (analog-to-digital converter) expertise continues to reside with specialty PC/104 I/O module manufacturers, while COM vendors have partitioned the architecture to include the greatest processing circuitry subset that is common to all applicationsâ&#x20AC;&#x201D;and data acquisition is not part of that subset. There are three types of PC/104 DAQ solutions already in widespread use in the market. The first is the pure I/O expansion module separate from the SBC, which allows a designer to mix and match from different manufacturers or even their own custom design. The second type of PC/104 DAQ consists of processor and analog I/O circuits on a single circuit board. Experts have diligently conquered the risk of noise coupling from high-speed digital sections to sensitive amplifier and sample-and-hold circuits, especially for 16-bit sampling. The third DAQ type consists of small, stand-alone modules that are networked by either â&#x20AC;&#x153;tetheringâ&#x20AC;? (cabled) or wireless links back to the main board stack. This is popular because of increased isolation and signal conditioning options over the other two DAQ types, and because of the great deal of mounting flexibility in the field. Networked signal-conditioning modules often can provide some signal preprocessing, are small and can be located next to the signal source being measured, which allows the host computer system to be further away. The key to each acquisition application is the ability to meet system requirements for a wide variety of sources and bandwidth necessary for sampling and processing the data. The higher the sample rate, the faster the system bus or interconnect required. However, this comes with a substantial power consumption penalty, which is a major setback for battery- or solar-powered DAQ devices. There is also a tradeoff between sample resolution (8/12/16 bits) and bandwidth. Sensitive low-noise input circuitry needs more settling time for 16 bits, which extends the sample period (inverse of the frequency). Most embedded applications reside somewhere on this spectrum. Many DAQ environments require isolation and signal conditioning, as will be explored later. Finally, there are business issues such as time-to-market, reconfigurability, multiple sources of supply and configuration, flexibility, and extended temperature operation that are benefits gained with stackable DAQ modules.

Getting the Drift

In order to achieve good accuracy and resolution in a typical system, a 16-bit A/D is desirable. However, it takes specially designed circuits to mitigate noise, drift and matching- and leakage-related inaccuracies over temperature. The challenge to board designers is to shrink all of this circuitry into a space-saving size while improving operation and cost of ownership over the long haul. New boards should not require user calibration to maintain data integrity. Older technology boards with trim pots (potentiometers) were prone to time- and temperature-related drift. Unpredictable and untraceable errors render data questionable and perhaps unusable. In addition, there is down time and the costs of a technician required to measure and adjust the system. To minimize the effects of drift error, analog experts are now approaching calibration and drift from the ground up through careful design and component selection. The single most important component in any analog converter RTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


technology deployed

Figure 4 PC/104 card with ZigBee for remote sensor network support.

design is the analog voltage reference. Any drift of the reference voltage directly affects analog conversion accuracy, expressed as full-scale (gain) error. The reference voltage tends to vary over temperature as well, although well-matched and compensated ICs keep the variations to a minimum. Over the years, circuits have evolved from manual calibration to auto-calibration with the entire analog section rolled into one chip. One example that targets small form factor boards such as the PC/104 board is the Linear Technologies LTC1859 data acquisition “system-on-chip.” It lends itself to 8-channel applications with 16bit conversions at fast sample rates. The device includes input multiplexer, range select, sample and hold, analog-to-digital converter voltage reference and associated control logic. Each high-resolution, high input voltage range ADC in this family has an on-chip, temperature compensated, curvature corrected, 2.50V factory-trimmed band gap reference. The use of precision, laser-trimmed thin-film resistors eliminates the need for user calibration. The PC/104 board shown in Figure 2 does not require any calibration for the A/D or D/A circuits but will still operate from -40° to +85°C within specification limits. Depending on the signal source, it may be necessary to isolate or provide other protection for the inputs and outputs so that the measurement circuit doesn’t load down the source, and also to eliminate ground loops due to common-mode voltages between the host computer and the monitor/control nodes. Figure 3 shows a digital I/O termination board that handles voltages from 3 to 28 VAC or DC, while relay outputs switch up to 1A @ 24VDC (60 VDC max.) or 0.5A @ 125 VAC while offering 1000 VAC or DC isolation for a wide range of industrial applications.

Faster, Better Data Acquisition

In the realm of the tiny 90 x 96 mm “PC/104” size I/O industrystandard modules, new applications are developing due to a third generation expansion interface called SUMIT. This connector provides support for the latest generation of ultra-low-power mobile processors. SUMIT is a stackable bus architecture from the Small Form Factor Special Interest Group (SFF-SIG), which is the only stackable PCI Express standard that allows low-cost, low-power PC/104 I/O modules to plug directly into new host SBCs. Data acquisition can



now be interfaced through a myriad of options from PC/104 ISA bus to two-wire SPI and I2C, and scaling up to high-speed PCI Express (“PCIe”). SUMIT offers solution methods for high-speed I/O that were not previously possible, plus it bridges existing data acquisition systems with the variety of SUMIT host SBCs on the market. The ISM (Industry Standard Module) form factor specification was created by the SFF-SIG to carry the 90 x 96 mm size and mounting holes forward regardless of what expansion bus exists or whether one is needed for a given module. This pure form factor is barely more than a board outline drawing, yet is flexible enough to allow compliant boards like the signal conditioning product shown in Figure 3. To get the SFF-SIG’s latest specifications including SUMIT and ISM, visit

Wired-in and Wireless

Traditionally, DAQ endpoint devices such as sensors, actuators, motor controllers, current loops and transducers were controlled by PLCs. Existing Modbus deployments are upgraded with Ethernet gateways to couple data acquisition directly to factory networks. USB DAQ modules are available that are capable of tens to several hundred samples per second—even at 16-bit resolution—powered through the USB connection for devices close to a host PC. Ethernet cable runs are used for broader deployments. Cable runs are expensive, impractical and sometimes unsafe in environments ranging from factories to oil fields. Two approaches to wireless DAQ include “Wi-Fi,” similar to consumer networks for laptop PCs, and ZigBee. The IEEE 802.11 standard divides the unlicensed 2.4 GHz spectrum into 13 overlapping channels 22 MHz wide but only 5 MHz apart. The large ecosystem of 802.11b/g access points and radios (consumer adapters) has contributed to broader usage in embedded applications. Data rates vary from 1 Mbit/s to 54 Mbit/s depending on noise levels (interference) and number of endpoints, with ranges up to 100 ft (indoor) or 300 ft (outdoor). Directional antennas can extend outdoor range to a mile or more, with transmit power governed by FCC Part 15 local regulations. The recent 802.11n addition increases data rate and/or range by occupying multiple channels and is typically overkill for embedded DAQ applications. For portable embedded DAQ devices, 802.11 consumes significant power and reduces battery life between charges. Although it is being positioned for the high-volume smart energy and home automation markets by its namesake alliance, the ZigBee standard is also gaining popularity in embedded markets such as industrial automation. Optimized for power conservation and short range on the IEEE 802.15.4 physical radio specification for 2.4 GHz, 900 MHz and 868 MHz unlicensed bands worldwide, ZigBee networks can be used with sensors, control nodes, actuators and process control (Figure 4). ZigBee solves the Wi-Fi battery life problem due to its low transmit duty cycle and extremely low 30ms wake-up latency. Up to 65,000 nodes can exist in a network, with 128-bit AES encryption for secure connections. Decentralized “mesh” networking brings reliability to wireless communications by re-routing data away from failed links using a pack-based protocol. Reliability is further bolstered by means of re-tries, acknowledgements and collision avoidance techniques. Each local sensor or control point gets its own Zig-

Technology deployed

Bee wireless modem in a dual in-line (through-hole) package the size of a quarter. The host end of the network can consist of an Ethernet gateway or an embedded board stack with its own RS-232 serial port ZigBee adapter. ZigBee is an affordable wireless alternative to WiFi where large numbers of DAQ endpoints exist, and yet long range is preserved due to the low transmit data rate and duty cycle. Radios are also available as stand-alone components to be used with any processor or microcontroller. ZigBee chip vendors like Freescale, TI, STMicro, Atmel and Samsung often sell integrated radios and microcontrollers with between 60 Kbyte and 256 Kbyte flash memory. The ZigBee software stack is available from the chip vendors or third parties. Visit to learn more. The SUMIT interface is the ideal multi-module board-level architecture for either of the wireless standards, since PCIe x1 interfaces to off-the-shelf PCI Express Mini Card Wi-Fi adapters and because LPC, SPI and I2C are easy to interface to low-speed ZigBee modems. Off-the-shelf LPC quad UART chips cost only a few dollars. The 90 x 96 mm PC/104 stackable board market benefits from the aforementioned new developments in performance, flexibility, connectivity and data acquisition options while retaining its ruggedness, reliability, industrial temperature range and long-term availability. SUMIT-ISM is the only form factor that allows PCI Express, USB, LPC, SPI, I2C and ISA (PC/104 bus) as expansion interfaces off a single host computer, which minimizes the size, cost and power consumption of new DAQ deployments. Legacy I/O support

is a common requirement in existing systems. Many applications require additional I/O as well, so PC/104 is the low-power, off-theshelf choice compared to COMs with custom carriers. As a result, SUMIT-ISM is the only viable architecture for these types of data acquisition environments. Using state-of-the-art, low noise 16-bit A/D and D/A converters with no calibration required, gives a shot in the arm to the PC/104 DAQ market. This clean, simple design yields smaller size, lower cost and much better accuracy by avoiding error-prone manual calibrations. The PC/104 bus platform provides a power-efficient and long-lifecycle 16-bit data path for these converters. And now SUMIT-ISM DAQ cards allow even higher data acquisition in the same, stackable, small form factor. This is attractive to both integrators and OEMs alike who need to integrate the PC and the DAQ circuitry together for their next designs, regardless of whether the host connection is wired or wireless. WinSystems Arlington, TX. (817) 274-7553. []. Linear Technology Milpitas, CA. (408) 432-1900. [].

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exploration r your goal eak directly page, the resource. hnology, nd products

technology deployed Data Acquisition with Small Modules

Capturing Elusive Data Ensures Reliable Results Data acquisition systems are continually advancing in functionality to provide practical and cost-effective solutions in those applications that generate elusive events. Event controlled recording can greatly increase the accuracy and ease the analysis of complex test scenarios.

sulting in a missed diagnosis. Another critical area where human safety is paramount is in the modern automotive industry where reliable component function is a top priority. The increasing amount of electronic components present in today’s cars not only need to coexist, but they need to operate autonomously from some and in conjunction with others without impeding safe operation…while withstanding a multitude of harsh environmental factors over an extended period of time. For example, over the lifetime of virtually any car, some lasting more than 200,000 miles, the electrical contacts within a connector have to withstand vibrations, heat, cold, humidity and dust under many different driving and parking conditions.

Ensuring Connections

Since electronics have entered the automotive scene, several standards for testing electrical contacts have been developed. The aim is to produce and to manufacture reliable connection systems between the different control and peripheral units within a vehicle. Reliability is of utmost importance to assure the proper functioning of by Ben Haest, QED, SA and Klaas A. Vogel, Elsys Instruments the Engine Control Unit (ECU), anti-lock brake system (ABS) and airbag systems to panies providing solutions now name a few. ation into products, technologies and companies. Whether your goal is to research the latest In the early days of testing, when the first cation Engineer, or jumpodern to a company's technicalsystems, page, the goal of Get Connected is to put you electronics whether found in industrial, electrical contacts were being incorporated into a car, they only ce you require for whatever type of technology, medical, automotive or other applications, are continu- carried the current for headlights and other basic components. es and products you are searching for. ally evolving to include additional functionality, to cram Nowadays, additional signals, such as audio, HD TV, phone and more components into a smaller space, and to provide better reli- GPS, are passed through the contacts of multi-pole connectors ability for fast access to the most accurate data. Regardless of the along with the critical operating signals. In addition, many of the environment, in most cases the information transfer is happen- actual signals are high frequency and low current, so they deing at a breakneck pace, and testing these advanced systems to mand especially stringent testing criteria. ensure data integrity becomes paramount since a system is only For each environmental parameter—vibration, temperature, as reliable as its weakest data packet. If information is lost or dust, humidity, etc.—different standards, typically conducted in a laboratory, have been developed to simulate the damaging infludelayed, the whole system can quickly fall apart. For example, in the medical field, information gathering ence of the environment on the quality of the electrical contacts is increasingly moving toward more data-based systems versus during a vehicle’s lifetime. A complete test specification will define the level, frequentraditional photo imaging systems. Some of the techniques that cies or shock level and test time for the excitation vibrations on a rely on accurate data measurement and recording include elecGet Connected shaker table and the simultaneous temperature cycles in a climatic troencephalography (EEG), magnetoencephalography (MEG) with companies mentioned in this article. chamber. In a typical automotive test, the connector is set up in exand electrocardiography (EKG). Improper information gathered from these critical tests can lead to image distortion that prevents actly that way. The combination of the simultaneous environmenproper diagnosis or could even mask an underlying problem re- tal parameters—vibration and temperature—is more rigorous than two separate tests with only one environmental condition, while being both more realistic and more time efficient. Get Connected with companies mentioned in this article. Different automotive standards also accurately define how


End of Article



Technology deployed

Contact Interrupt causes increased resistance


Trigger Point

Figure 1 Contact resistance goes up when connector pin comes loose due to shaking, temperature fluctuations, humidity, etc. When surpassing pre-programmed conditions like level, window, other, the particular channel in the transient recorder will trigger and the events will be stored together with time stamps.

GnΩstic64 - Measurement Set-up 120Ω


Real-time Data Acquisition with Embedded Transient Recorders 4-Lead Resistance Measurement with Integral Current Source

75 +- 3 mm

75 +- 3 mm

Connector pins

Figure 2 The QED GnΩstic64 (Gnostic) measurement set-up depicted here is repeated for each pin in the connector under test with maximum 20 channels per system and up to 64 channels networked together.

the connector should be mounted onto the shaker table. Because the cables are mounted to the connectors, the different electrical contacts are also heavily mechanically stressed through vibrations that come through the cables as well. It is important to note that the connectors and the cables must be fixed in a very specific way to ensure tests’ repeatability and guaranteed comparable results. One very common test requirement is the SAE/USCAR-2 standard: a DC current of 100 mA flows through each electrical contact. The standard specifies that as soon as the contact resistance is more than 7 ohm for a minimum of 200 nsec (0.2 μsec), an electrical contact is interrupted and does not function properly anymore. The standard uses a 12 V/DC voltage source with a series resistor of 120 ohm. The voltage across the electrical contact is measured to identify the increase of contact resistance during an environmental test.

Trigger conditions can be freely defined according to the test specifications, and many car manufacturers have developed their own test specifications over time. A good example is the FlexRay Communications System, a robust, scalable, deterministic and fault-tolerant digital serial bus system designed for use in automotive applications. Developed under an industry consortium comprised of several leading automotive manufacturers, this network communications protocol features high data rates of up to 20 Mbyte/s. Trigger conditions are 1 ohm contact resistance and 100 nsec (10-7 sec) interruption time (Figure 1). For non-automotive tests, quite often the temperature cycles are omitted. Only vibration conditions are simulated. Also the contact interruptions are defined differently: the maximum voltage across a contact should not be more than 10 V/DC. An interruption is defined as a voltage increase across the contact for more than 50% (5 V/DC) and 1 μsec (10-6 sec). These examples show just how versatile data recorders need to be to acquire accurate information under a variety of conditions.

Acquiring Elusive Data

Luxemburg-based QED, S.A., which develops customer-specific solutions in the fields of measurement, regulation and control technology for testing laboratories and production lines, was finding that many standard measurement systems failed to perform the necessary testing required by several industry standards. It has since developed an automotive testing method, using Elsys Instruments’ high-speed, high-resolution transient recorders with the Event Controlled Recording (ECR) mode, which allows targeted acquisition of cyclic or sporadically arising events, to gather the required test data. QED’s contribution to a bay of test equipment consists of vibration tables, environmental chambers and a 20-channel transient recorder system with 40 to 100 Msample/s sampling rate per channel at 14-bits vertical resolution and software (Figure 2).

Event Controlled Recording

The advanced ECR functionality of the recorder made it easy to set a great number of trigger filters that could respond to certain waveform behaviors, enabling the recorder to function as an “Intelligent Streaming Digitizer System” (ISDS). The registration of measuring data in ECR mode only occurs if certain signal conditions (trigger, time window, repetitions, etc.) are fulfilled, ensuring unwanted and unneeded signal data will not be stored. Take an arbitrary interruption in the connector testing application as an example. While the underlying slower signal phenomenon is being recorded at slow sampling rates for the duration of the test cycle (which may be many hours to days or even weeks), when a fast event occurs that fulfills the preprogrammed trigger conditions, it will be recorded at a high sampling rate, complete with time stamp. In a way, this is comparable to an oscilloscope with a triggered delayed time base. Also the mode forms an intelligent way of “streaming” waveform data to disk, as only the events of interest are being stored. ECR enables zero dead time between events, so no events are lost, even with many channels active at maximum scanning rate over a long period of time, since each channel possesses its RTCRTC MAGAZINE MAGAZINEFEBRUARY MONTH 2011


technology deployed

Ring-Buffer (TPCX-Card)


Recording with max. Sampling Rate T

..................................... PCI-Bus

Data Acquisition Architecture — Memory configuration and Trigger on multiple, parallel operating, TPCX PCI-modules


Typical Test Signal

Storage to RAID - System Hard Drives (*)







ECR-Trigger” Conditions (*) 0’’=striping 1’’=mirroring “

Figure 3 Transients are recorded in a circular memory buffer as large as 128M samples (14 or 16 bits) per channel, including pre and/or post trigger delay and time stamp information. Data recordings are off loaded to system hard drive files for further analysis. Data blocks recorded under ECR trigger modes are usually small in size, hence an enormous number of events can be gathered over a long period of time without supervision. The system can be programmed to automatically off-load recorded data to host hard drives from time to time. Thanks to LAN connectivity the host computer may be remotely stationed.

own signal buffer with up to 128 Msamples (Figure 3). With such a large buffer available so that data only needs to be transferred now and then to the onboard hard disk, data rates as high as 80 Msamples/s can be achieved. The trigger conditions can be individually set for each channel, with individually set complex trigger signal criteria such as pulse width/interval/height, slew rate, window-IN/OUT, etc. ECR supports three modes to enable extreme versatility in acquiring data for various testing parameters (see sidebar “Three Modes of Event Controlled Recording”). The Multi-Channel Mode allows different channels to be associated with each other, saving test time and critical resources. Single-Channel Mode, used in connector testing, allows different trigger conditions and trigger events per channel, where a trigger event for an oscilloscope or standard transient recorder typically starts the acquisition on all channels. While a micro-second interruption on one channel triggers the high-speed data acquisition on that channel for the recording of the time signal, all other channels stay armed. They remain ready for the high-speed data acquisition of the eventual micro-second contact interruptions on these channels. Each channel can essentially operate as an independent transient recorder. Also in this mode it is possible to associate channels with each other. For example, excitation frequency and temperature are measured simultaneously during the interruption of an electrical contact. The recorded frequency and temperature are then linked to the event of the contact interruption. After the test procedure has been finished, this information can be used to analyze the correlation between the



excitation frequencies and the number of contact interruptions. While the contact interruptions are recorded with a very high sampling rate—with a time resolution up to less than 10 nsec (10-8 sec)—various standards require that the electrical contacts be monitored during the entire test time. The Dual Mode, in conjunction with Single-Channel Mode, is especially useful by defining a second slower sampling rate. The high-speed sampling clock is divided by a specific parameter to obtain a low-speed sampling rate for monitoring. For example, a sampling rate of 40 Msamples/s can be divided by a factor of 4 x 107 to obtain a sampling rate of 1 Sample/s. A continuous, seven day test would take less than 1.2 Mbyte per channel for a trend analysis of the contact resistance after the test. In the case of automotive connector testing, without ECR, QED’s process of gathering data for analysis on the quality and durability of the electrical contacts would have required many parallel channels of high-speed streaming recorders, with massive buffer memories and complex data processing. To seek out such failures and quality issues would have required much more computing power and specialized software for pattern recognition. Elsys Instruments Niederrohrdorf, Switzerland. +41 56 496 01 55. []. QED Echternach, Luxembourg. 26 95 78 90. [].

Three Modes of Event Controlled Recording

All Elsys test systems have embedded PCI digitizers as their core, are LAN controlled, have single ended and differential inputs, sampling rates up to 240 Msamples/s at 14- and 16-bit resolution and extensive smart trigger modes, including the ECR method (below) of acquiring data. Clock synchronization up to 1024 channels is foreseen. Apart from housing PCI digitizer hardware, the instrument enclosure features server capabilities and hard drive, running in a Windows or Linux environment. ECR operates in three distinct modes:

ECR Multi-Channel Mode

The signal data is being recorded parallel on all active channels. After the initial start command, all the actual signal curves are constantly written into the module memory, which is configured as a ring buffer. Subsequently, each trigger event marks the range where the signal data will be read from the module memory and finally stored to the file. This kind of recording corresponds mainly to the well-known Multiblock Acquisition Mode, the way a digital oscilloscope records data in segmented memories. However in ECR, the stored time periods can overlap each other. Only with this method can a real zero dead time be guaranteed (also at acquisitions with a pre-trigger setting).

Technology deployed Data Acquisition Mode ECR - Event Controlled Recording

ECR Single-Channel Mode

The signal data is being registered separately for each channel. In this mode each selected channel serves as a single trigger source, which marks the area where the signal data is selected from and stored into the file. Only data from the corresponding channel is being registered. However, you can associate further channels parallel to a single channel. The signals of those associated channels are then stored in the same time frame as the triggering channel.

C1 C2 C3 C4 CN Time C1: Independent channel 1; 3 transients acquired C2: Associated channel 2; acquires synchronously to channel 1 same 3 blocks of waveform data (no transients showing) C3: Independent channel 3; 2 transients acquired C4: Independent channel 4; 1 transient acquired CN: Independent Nth channel; 2 overlapping transients acquired

Figure 1 Here, the way ECR is capturing transients with independent and associated channels is seen. Not shown is the underlying slower waveform on which these transients are riding. Each time a channel triggers, a time stamp is generated for precise retracing when and why a certain event occurred.

ECR Dual-Mode

ECR offers a third mode called Dual-Mode. This parameter in ECR defines a second sampling rate to digitize usually the underlying slower signal on which the transients ride. In ECR DualMode the high-speed sampling clock is divided by a specific parameter to obtain a low-speed sampling rate for monitoring. For example, a sampling rate of 60 Msamples/s can be divided by a factor of 105 to obtain a sampling rate of 600 Samples/s (10 times the AC frequency). At those rates, continuous testing of principle signal and the fast phenomena can go on for a very long time.

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Learn More > Š 2010 Logic Supply, Inc. All products and company names listed are trademarks or trade names of their respective companies.

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products &

TECHNOLOGY SDK Targeted for Designs Using PCI Express 3.0 Switches

An upgraded and free software development kit (SDK) supports the PLX ExpressLane PCI Express (PCIe) Gen 3 switches. This suite of software tools works in conjunction with PLX’s onchip diagnostic hardware, together called visionPAK. The SDK enables designers to get to market faster with instant access to internal chip registers, and offers diagnostic features as well as performance monitoring of an entire system’s performance, thus optimizing the usage of costly test equipment such as logic analyzers, traffic generators and high-speed oscilloscopes. Measuring the height and width quality of the SerDes eye, generating desired packets/traffic at line rate, injecting and counting errors, port utilization, and measuring performance are among the array of key features implemented in this multi-generation, backward-compatible SDK suite. Global designers continue to cite the cost-effectiveness of the PLX SDK in that it reduces the bottlenecks associated with expensive third-party analyzers and scopes and closes the loop on common buggy system issues. The ability to quickly debug systems in the lab while improving performance using the PLX SDK helps those designers streamline their designs. The SDK runs on Windows/Linux systems and connects to PLX devices through the host port or I2C interface provided on all PCIe Gen 2 and Gen 3 switches. Some of the additional key features of the PLX SDK beta version 6.4 include an updated Packet Generator tool, faster downloads because the SDK size has been reduced by half and special support for AHB register access as well as kernel drivers for PLX PCIe Gen 3 switches with on-chip DMA. There is a facility to compare register dump text files and a slave mode loopback for Gen 3 switches along with the ability to auto-detect requestor ID for setting up Non-Transparent Mode Address Translation. The suite also includes a Java-based PEX Device Editor GUI for Linux. PLX Technology, Sunnyvale, CA. ((408) 774-9060. [].

QDR SRAM Hits 550 MHz While Reducing Power Consumption by 50 Percent

New Quad Data Rate (QDR) and Double Data Rate (DDR) SRAMs at 36 Mbit and 18 Mbit densities are now the latest members of the 65nm SRAM family from Cypress Semiconductor. The new memories complete the broad portfolio of 65nm synchronous SRAMs, which includes densities up to 144 Mbit and speeds up to 550 MHz. Cypress’s patented process technology reduces power consumption up to 50% compared with 90nm SRAMs, enabling the new wave of “green” networking infrastructure applications. The new devices are form, fit and function compatible upgrades for the large installed base of 90nm QDRII/QDRII+ SRAMs (estimated at well over 60 million units), and are fully compliant with the QDR Consortium specifications. This compatibility enables designers of existing products to easily upgrade system performance without requiring board redesign. The 65nm SRAMs are suitable for networking applications, including core and edge routers, fixed and modular Ethernet switches, 3G basestations and secure routers. They also enhance the performance of medical imaging and military signal-processing systems. The QDRII+ and DDRII+ devices feature On-Die Termination (ODT), which improves signal integrity, reduces system cost, and saves board space by eliminating external termination resistors. Cypress Semiconductor, Jan Jose, CA. (408) 943-2600. [].



Desktop Networking Platform Features Dual-Core Atom

A family of desktop networking platforms powered by energy-efficient Intel Atom processors features up to 6 Intel Gigabit Ethernet ports. The PL-80260 from Win Enterprises is only 9.1” wide and designed for networking applications in small- to mid-size businesses and remote Enterprise offices. The device pairs either the Atom D410 single-core or D510 dual-core processor with the Intel 82801HM I/O Hub. Intel Hyper-Threading Technology increases logical CPU threads resulting in more efficient use of processor resources. The PL-80260 is designed to support a range of OEM applications such as routing, firewall/threat management, database and network attached storage (NAS). CompactFlash, SSD or HDD, DDR2 SODIMM (up to 2 Gbyte), Dual SATA-II interfaces and mini PCI slot are expandable features that can be upgraded through an easily removable chassis cover. A maximum of six Intel-based GbE LAN ports are provided with two-port bypass controlled by a programmable watchdog timer. Each Internet interface has an LED indicator to show activity and transfer rate. A fully loaded PL-80260 configuration has peak thermal design power (TDP) of approximately 30 watts. The unit is FCC, CE and RoHS compliant. Recommended operating systems for PL80260 evaluation units include Windows XP Pro and Windows 7. Linux version support includes Fedora 13, Debian 5.0.6 and openSUSE 11.3. The PL-80260 supports 32-bit and 64-bit software. Additional Windows and Linux distributions are documented to support the Intel Atom D410/D510 + ICH8M with 82574L drivers. Users should check their operating system documentation for hardware compatibility or contact WIN Enterprises regarding their software selection. The PL-8026A version with Dual-Core Atom D510 costs $379 in 1,000-unit quantities. WIN Enterprises, North Andover, MA. (978) 688-2000. [].


Cellular Gateway Connects Remote Devices in Harsh Environments

A rugged programmable cellular gateway for monitoring remote assets in harsh environments features advanced battery power features and a NEMA 4X/IP66 enclosure to protect the gateway from water, dust and dirt. The ConnectPort X3 H from Digi International is suitable for tank monitoring, pipeline, agriculture, utility and other rugged applications. The ConnectPort X3 H is integrated with the iDigi platform, a cloud computing service that makes it easy to remotely manage devices and integrate device information into a company’s back-end systems. The ConnectPort X3 H provides global connectivity to remote devices and device/sensor networks via GSM GPRS cellular networks. It is Class 1, Division 2 certified and features multiple power options including mains power, battery power or battery power with solar charger panel for harsh environments where power may not be available. It has advanced power management features including a sleep function that shuts down the device to conserve battery power when it is not running. The ConnectPort X3 H is available with an optional embedded XBee ZigBee module allowing the gateway to connect to a small network of ZigBee-enabled wireless devices or sensors for local data aggregation over a cellular network. It also features an optional analog I/O, digital I/O or RS-232 serial port for direct wired connectivity. Optional internal GPS is also available for asset tracking. The ConnectPort X3 H can be programmed using open-source Python or the iDigi Device Integration Application (iDigi Dia). It also includes an Eclipse-based integrated development environment that allows Web developers to rapidly develop embedded applications. The ConnectPort X3 H is shipped iDigi ready and is available to qualified customers now starting at $438 MSRP.

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Digi International, Minnetonka, MN. (952) 912-3444. [].

2- & 4-Channel Hot Swap I2C Multiplexers with Capacitive Buffering Supercapacitors

A pair of 2-wire bus multiplexers provides individual enable pins to connect an upstream I2C bus to any combination of downstream buses or cards. The LTC4312 and LTC4314 from Linear Technology are pinselectable multiplexers with bus buffers that reduce component count while promoting ideal I2C signal integrity. The LTC4312 multiplexes two channels, while the LTC4314 multiplexes four channels. These devices allow easy I2C address expansion, providing the ability to address one of multiple identical devices, thus resolving address conflict issues. Bidirectional capacitive buffering allows extension of the I2C bus size well beyond the 400pF I2C bus specification and prevents I2C signal corruption during live board insertion or removal. The LTC4312 and LTC4314 are suitable for a wide range of applications, including radial architectures in telecommunications systems such as ATCA, address expansion and level translators. Many I2C and SMBus devices operate at different supply voltage levels, yet must communicate in the same application. The LTC4312 and LTC4314 support level translation for bus voltages ranging from 1.5V to 5.5V. This enables the powering of devices from different supply voltages while maintaining fully bidirectional communications between all devices in the system. Pricing for the LTC4312 and LTC4314 starts at $1.95 and $2.65 each, respectively, for 1,000-piece quantities. Linear Technology, Milpitas, CA. (408) 432-1900. [].

Get Connected is a new for further exploration Second Generation iCore Processors onresource 6U VXS into products, technologies and companies. Whether your goal Form Factor is to research the latest datasheet from a company, speak directly

A 6U VXS single board computer with an Application Engineer, or jump to a company's technical page, the goal ofthe Get Connected is to put you in touch with the right resource. is fully compliant with Whichever VITA 41.x standard and fea- level of service you require for whatever type of technology, Connected will help you connect with the companies and products tures the enhanced Get processyou are searching for. ing and graphics performance of the quad-core Intel Core i7-2715QE processor or the dualcore Intel Core i5-2515E processor. Additionally, the VX 81x/09x from Concurrent Technologies supports up to 16 Gbyte of ECC DDR3 SDRAM, Get Connected with technology and1companies prov configurable PCI Express fabric interface operating at 1 x8, 2 x4, x4 + Get Connected is a new resource for further exploration into pro 1 x4 at Gen 1 or Gen 2 data rates. In addition, it features dual Gigabit Ethdatasheet from a company, speak directly with an Application Engine ernet, dual SATA600, dual PMC / XMC slots, dual serial RS-232/422/485 in touch with the right resource. Whichever level of service you requir ports, 6 USB 2.0 ports, Get dualConnected independentwilldisplay ports, onboard Compact help you connect with the companies and produc Flash and optional 2.5-inch hard drive. The VX 81x/09x provides support for quad-core or dual-core second generation Intel Core processors, enabling Concurrent Technologies to provide enhanced performance and features over previous Intel Core processor based boards. The second generation Intel Core processors offer enhanced graphic capabilities resulting in virtually double the graphics performance of previous architectures, and with support for SATA600, PCI Express Gen 2, Intel Turbo Boost Technology capabilities and media acceleration, this single board computer offers cutting-edge technology for tomorrow’s applications. The VX 81x/09x is available in three temperature grades: 0° to +55°C (N-Series), -25° to +70°C (E-Series), -40° to +85°C (K-Series) and two ruggedized grades: Ruggedized Conduction-Cooled -40° to +85°C (RC), Ruggedized Air-Cooled -40° to +75°C (RA). Inand addition to the VX 81x/09x, Get Connected with companies Concurrentproducts Technologies also be releasing Intel Core processor-based featuredwill in this section. boards for 3U CompactPCI, AMC and 3U VPX. Operating systems currently supported for the release of the VX 81x/09x are Windows 7, Windows XP, Windows Embedded Standard 7, Linux and VxWorks.


Concurrent Technologies, Woburn, MA. (781) 933 5900. []. Get Connected with companies and products featured in this section.




Second Generation iCore processors on 3U OpenVPX Form Factor

A new 3U OpenVPX high-performance embedded single board computer features the second generation Intel Core processor and 6 series chipsets from the Intel embedded roadmap. The TR 80x/39x from Concurrent Technologies features the enhanced processing and graphics performance of the quad-core Intel Core i7-2715QE processor and the dual-core Intel Core i5-2515E processor while maintaining the power consumption of the previous Intel Core processors. The TR 80x/39x is a 3U OpenVPX processor board providing support for quad-core or dual core second generation Intel Core processors, up to 8 Gbyte of ECC DDR3 SDRAM, configurable PCI Express fabric interface supporting 1 x8, 2 x4, 1 x4 + 1 x4 at Gen 1 or Gen 2 data rates, dual Gigabit Ethernet or dual 1000BaseBX channels, dual SATA600, single XMC slot, serial RS-232/422/485 port, dual USB 2.0 ports, independent VGA and display port all in a 3U VPX form factor. The Intel Core microarchitecture virtually doubles graphics performance of previous architectures and when complemented by support for Intel Turbo Boost Technology capabilities and media acceleration, the TR 80x/39x Single Board Computer offers cutting-edge technology for security, transportation, military and embedded systems. The TR 80x/39x is available in three temperature grades; 0° to +55°C (N-Series), -25° to +70°C (E-Series), -40° to +85°C (K-Series). For extreme rugged applications the TR 80x/39x is available in VPX-REDI variants (type 1 and type 2); the VPX-REDI Type 1 Conduction-Cooled VITA 47 Class CC4 -40° to +85°C (RCS - Series) and the VPX-REDI Type 2 Conduction-Cooled VITA 47 Class CC4 -40° to +85°C (RCT - Series). Operating systems currently supported for the release of the TR 80x/39x are Windows 7, Windows XP, Windows Embedded Standard 7, Linux and VxWorks. Concurrent Technologies, Woburn, MA. (781) 933 5900. [].

3U VPX SBC Features Second Generation Core i7 Processor

A conduction- or air-cooled 3U VPX Single Board Computer (SBC) is based on the second generation Intel Core i7 processor. The XPedite7470 from Extreme Engineering Solutions utilizes the processor’s quad-core technology operating at 2.1 GHz to deliver enhanced performance and efficiency. XPedite7470 customers will benefit from the performance boost provided by the Intel Advanced Vector Extensions (Intel AVX) incorporated into the second generation Intel Core i7 processor. X-ES has teamed with RunTime Computing Solutions to support applications that can take advantage of the SIMD architecture of Intel AVX. VSI/Pro, the premier math and signal processing library available from RunTime Computing, will be supported on the XPedite7470 and all X-ES products based on the second generation Intel Core i7 processor. The XPedite7470 initially will be based on the Intel Core i7-2715QE processor and Intel QM67 Express chipset. Other XPedite7470 processor options will be available later in 1Q11. The XPedite7470 features include a quad-core Intel Core i7-2715QE processor with Intel HyperThreading Technology and up to 8 Gbyte of DDR3-1333 ECC SDRAM in two channels along with 32 Mbyte of boot flash and up to 16 Gbyte of user flash. The board supports an XMC/PrPMC site, two x4 Gen2 PCI Express VPX backplane interconnects and two optional 10/100/1000BASET or 1000BASE-BX Ethernet ports. In addition, there are two DVI graphics ports and, optionally, two each USB 2.0 high-speed ports and SATA 3.0 or 6.0 Gbit/s ports. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].



6U OpenVPX DSP Engine Features Two Quad-Core Core i7-2715QE Processors

A rugged, high-performance OpenVPX DSP engine is based on the new quad-core Intel Core i7-2715QE processor. The new CHAMP-AV8 is also Curtiss-Wright Controls’ first DSP engine to offer IDT’s upcoming Gen2 PCIe-to-sRIO protocol conversion bridging semiconductor product, bringing the performance and bandwidth advantages of sRIO switch fabrics to the second generation Intel Core i7 processor-based embedded computing applications. The CHAMP-AV8 incorporates the enhancements of the OpenVPX (VITA 65) standard with a complete suite of data plane, expansion plane and control plane interfaces. Supporting Gen2 SRIO and Gen2 PCIe interfaces, the CHAMP-AV8 offers triple the bandwidth of first generation VPX products with up to 32 Gbyte/s of fabric performance, thus ensuring that application performance can scale commensurately with the much higher CPU performance. The CHAMP-AV8 multiprocessing board brings the floating-point performance of the quad-core Intel Core i7-2715QE processor to the OpenVPX form factor standard. Utilizing a pair of processors, the CHAMP-AV8 delivers performance rated at up to 269 GFLOPs. With a 21 Gbyte/s (peak) DDR3 memory subsystem connected directly to the processor, the Intel Core i7-2715QE is able to maximize the throughput of its Intel AVX vector processing units and process larger vectors at peak rates significantly greater than was possible with previous AltiVec-based systems. The CHAMP-AV8 features a high-bandwidth PCI Express (PCIe) architecture, with onboard PCIe connections between the processors and the XMC site. With 8 Gbyte of flash and up to 16 Gbyte of SDRAM, the CHAMP-AV8 is designed for applications with demanding storage, data logging and sensor processing requirements. The CHAMP-AV8 is supported with an extensive suite of software including support for Wind River VxWorks and Linux operating environments. Additional software support includes Inter-processor communications (IPC) and Curtiss-Wright Controls’ Continuum Vector AVX-optimized signal processing library. Pricing starts at $19,900. Curtiss-Wright Controls, Ashburn, VA. (613) 254-5112. [].


3U CompactPCI Express Module with Core i7

An air-cooled, 3U CompactPCI Express Single Board Computer (SBC) is based on the Intel Core i7 processor and Intel QM57 chipset. The XPedite7331 from Extreme Engineering Solutions, with its dual-core Core i7 processor, operating at 2.53, 2.0, or 1.06 GHz, delivers enhanced performance and efficiency for industrial control and test and measurement applications. The XPedite7331 feature set includes, in addition to the Core i7-610E, -620LE, and -620UE processors with hyper-threading technology and the QM57 chipset, up to 8 Gbyte of DDR3-1066 ECC SDRAM on two channels. There is also up to 16 Gbyte of user flash and 32 Mbyte of redundant boot flash and one XMC site. A Gigabit Ethernet and USB UART serial port are also provided for additional flexibility. Operating system support includes board support packages for Green Hills Integrity, Wind River VxWorks with Windows drivers and a Linux BSP. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

Updates to xTCA Management Controller Solutions for SmartFusion

Pigeon Point Systems has announced the release of significant enhancements to its xTCA management controllers solutions based on the Microsemi SmartFusion intelligent mixed signal FPGA. The new releases allow reduced management controller footprint and bill of material costs via support for a new smaller SmartFusion package type and for integration of power management functions into the SmartFusion FPGA, displacing external devices. The updated solutions cover IPM Controllers (IPMCs), Carrier IPMCs and Module Management Controllers (MMCs) for AdvancedTCA (ATCA) and AdvancedMC (AMC) boards

and modules. The updates will be released during Q1, 2011. The new solutions support the Microsemi CS288 11x11 mm package, enabling IPMCs that are about 40% smaller than those built with Pigeon Point’s widely used Renesas H8S-based IPMC solutions, even while adding advanced LAN attach capabilities that are not present in those earlier offerings. The LAN attach feature enables dramatic productivity improvements during development and operation by allowing the management controller to share access to existing high-speed LAN fabrics in a shelf. The new support for power rail management leverages the ARM Cortex-M3 microcontroller, the programmable analog subsystem and the flash-based fabric in the SmartFusion FPGA to sequence, monitor and margin onboard power rails, optionally eliminating the need for specialized power rail management devices on the board or module. Power rail sequencing is managed by Cortex-M3 firmware, with fault monitoring supported by FPGA logic, both using analog measurements collected and assessed by the SmartFusion Analog Compute Engine (ACE). In addition, the new releases support in-field upgrades of the SmartFusion FPGA fabric. This support uses the same PICMG-specified HPM.1 upgrade architecture that is already supported for firmware upgrades in all Pigeon Point management controller solutions. Like all Pigeon Point Board Management Reference (BMR) management controller solutions, these come with full reference schematics, firmware source code and FPGA design, plus comprehensive documentation, a year of technical support and bench top hardware. The bench top Carrier IPMC can be tested directly with standard AMC modules and the bench top MMC can be installed in standard AMC slots for additional testing flexibility. Pigeon Point Systems, Scotts Valley, CA. (831) 438-1565. [].



Preconfigured Rugged Systems Combine Flexibility with Short Lead Time

A new family of rugged, off-the-shelf systems is designed to reduce the cost and timeto-market of developing solutions for a range of military vehicle platforms including UAVs, manned and unmanned ground vehicles and launch vehicles. The CRS-C2P-3CC1 and CRS-C3P-3CB1 from GE Intelligent Platforms are 2-slot and 3-slot pre-validated, application-ready, CompactPCI-based computer systems. They are available in a wide range of application-specific configurations that can be delivered in a rugged, convection or base plate cooled 3U chassis. These computers are supplied as standard with a Freescale-based single board computer and the VxWorks real-time operating system and feature I/O capabilities including Ethernet, serial, USB, MIL-STD-1553 and ARINC 429 as well as discrete I/O. The CRS-C2P-3CC1 and CRS-C3P3CB1 integrate GE Intelligent Platforms boards and modules, drawn from GE’s selection of COTS boards, into open modular systems that are tested and qualified for rugged systems deployment. They are configured with a single board computer featuring a Freescale MPC7448 processor operating at 1.4 GHz, together with 512 Mbytes of RAM and 256 Mbytes of flash memory. The CRS-C2P3CC1 has dimensions of (H x W x D) 3.96” x 7.15” x 9.03” (excluding connectors) and weighs only 11 pounds; and the CRS-C3P3CB1 has dimensions of (H x W x D) 5.60” x 4.25” x 8.76” (excluding connectors) and weighs 9 pounds. GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [].


High-Density Isolated CompactPCI Async Serial Communication Modules

Two new isolated asynchronous serial CompactPCI modules are designed for applications in transportation, COTS, communications and process control. The latest additions to Tews Technology’s cPCI line include the TCP469 and TCP470. The 3U 32-bit cPCI modules offer 8- or 4-channel high-performance serial interfaces. Each serial channel can be programmed via a CPLD register to operate as an RS-232, RS-422 or RS-485 interface. The RS-422 and RS-485 interfaces can be programmed as Full Duplex or Half Duplex interface with programmable termination. The modules can operate with 3.3V and 5.0V PCI I/O signaling voltage. Each RS-232 channel supports RxD, TxD, RTS, CTS and GND. RS-422 and RS-485 Full Duplex support a four wire interface (RX+, RX-, TX+, TX-) plus ground (GND). Half Duplex supports a two wire interface (DX+, DX-) plus ground (GND). All channels generate interrupts on PCI interrupt INTA. For fast interrupt source detection the UART provides a special Global Interrupt Source Register. All serial channels use ESD protected programmable multiprotocol transceivers. ESD protection is up to ±15 KV. The TCP469 is based on the Exar XR17D158 and the TCP470 on the Exar XR17D154 universal PCI UARTs. In order to offload host CPU processing, each channel has separate 64-byte transmit and receive FIFOs to significantly reduce the overhead required to provide data to and from the transmitters and receivers. The FIFO trigger levels are programmable, and the baud rate is individually selectable up to 921.6 kbit/s for RS-232 channels and 5.5296 Mbit/s for RS-422/RS-584 channels. The UART offers readable FIFO levels. The modules offer front panel I/O with a HD50 SCSI-2 type connector. Each of the channels is isolated from the system and each other by digital isolator and onboard integrated DC/DC converter. The TCP469 and TCP470 operate in extended temperature range (-40° to +85°C) and feature a five-year warranty. Software support for major operating systems such as Windows, Linux, VxWorks, and QNX available.and Get Integrity Connected with is technology companies providing solutions now TEWS Technologies, Halstenbeck, Germany. +49 (0)4101-0458-19. [].

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18-bit, 1.6 Msample/s, Serial SAR ADC Achieves 101dB SNR Performance

A serial 18-bit, 1.6 Msample/s SAR analog to digital converter (ADC) achieves an unrivaled 101dB signal-to=noise ratio (SNR) and -118dB total harmonic distortion (THD) while supporting a fully differential ±5V input range. The LTC2379-18 from Linear Technology features a maximum internal nonlinearity (INL) of ±2LSB with no missing codes and guaranteed specifications over the -40° to 125°C temperature range. Operating from a 2.5V supply, the LTC2379 18 consumes only 18 mW and is available in small 3 mm x 4 mm DFN and MSOP-16 packages. The LTC2379-18's high SNR, fast throughput and low power dissipation make it ideal for high-performance medical, industrial and automotive applications. Complementing the LTC2379-18 is the pin- and software-compatible 16-bit, 2 Msample/s LTC2380-16. The LTC2380-16 achieves a 96 dB SNR and ±0.5LSB maximum INL. The LTC2379-18 and LTC2380-16 are the first in a family of 18-/16-bit high-performance SAR ADCs with speeds ranging from 250 Ksample/s up to 2 Msample/s. These devices offer a revolutionary new digital gain compression feature that eliminates the need for a negative supply on the ADC driver, dramatically lowering the total power consumption of the signal chain. The devices' shutdown mode further reduces power dissipation to 1.25 µW when idle. The true no-latency operation enables accurate one-shot measurements even after lengthy idle periods with no minimum sample rate required. The explicit Busy and Chain pins, along with a user-friendly SPI interface, support I/O voltages from 1.8V to 5V, simplify digital timing and minimize external component count. The LTC2379-18 and LTC2380-16 are now available, priced at $29.95 each for the LTC237918 and $24.50 each for the LTC2380-16 in 1,000 piece quantities. Linear Technology, Milpitas, CA. (408) 432-1900. [].

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal Mini-SAS Cables Perform to 6 Gbit/s SAS is to research the latest datasheet from a company, speak directly Specifications with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. A new line of Whichever level of service you require for whatever type of technology, Mini-SAS cable asGet Connected will help you connect with the companies and products semblies comes in you are searching for.

the form of formance, cost-effective cabling solutions for high-speed serial buses supporting 4X Serial Attached SCSI (SAS) architectures. Get Connected with technology and companies prov The copper cables from Tyco Electronics are designed to be fully compliant Get Connected is a new resource for further exploration into pro with 3 Gbit/s SAS and 6 Gbit/s SAS protocols. Target product applications datasheet from a company, speak directly with an Application Engine include mass storage systems, storage area switches, servers in touch with the rightnetworks resource. and Whichever level of service you requir and routers. Get Connected will help you connect with the companies and produc The Mini-SAS cable assemblies were recently submitted for testing at the SCSI Trade Association (STA)-sponsored 11th Serial Attached SCSI (SAS) Plugfest, held in October 2010 at the University of New Hampshire InterOperability Laboratory (UNH-IOL). Plugfest was an event held to validate the latest SAS 2.1 specification, which underlies the 6 Gbit/s SAS generation in supporting equipment such as servers, storage, switches, etc. as well as cable assemblies. At the event, Tyco tested its Mini-SAS external cables within the large system build included at Plugfest. Tyco tested its standard 24 AWG, 10m cable and raised the bar by also testing longer length cables (30 AWG at 5.5m, 28 AWG at 7m and 26 AWG at 8.5m) with 6 Gbit/s SAS signaling speeds— demonstrating its wide breadth of customized cable assembly solutions. Getresults Connected with that companies Final test concluded no bitand errors were detected, which products featured in this section. indicates that Tyco Mini-SAS cables perform without dropped data for tem builders using the 6 Gbit/s SAS technology. Prior to the event, internal S-parameter and near-end-crosstalk tests were conducted on the cable assemblies to meet the requirements for 6 Gbit/s SAS specifications.


Tyco Electronics, Berwyn, PA. (610) 893-9800. []. Get Connected with companies and products featured in this section.




Deterministic, Low Latency, High Speed Memory Sharing for Demanding Applications

A low-profile PCI Express reflective memory node card is designed for realtime applications such as simulation and training, industrial process control and data streaming and acquisition. The PCIE5565PIORC from GE Intelligent Platforms will also serve a broad range of commercial, telecommunications and military/ aerospace applications that require redundancy for high availability. Such applications are characterized by the need to move and share data at fast, deterministic rates and, in many cases, the only solution in such environments is reflective memory. The board features 2.12 Gbaud serial connection speed, improved Programmed I/O (PIO) read performance, field upgradeable firmware and RoHS compliance, and the maximum PCI burst rate has been doubled to 512 Mbytes/s: larger memory (256 Mbytes) is also supported. GE’s reflective memory networks can be scaled to 256 nodes and operate at speeds up to 174 Mbytes/s. Distance between nodes can be up to 10 kilometers. A reflective memory network is a special type of shared memory system that enables multiple, separate computers to share a common set of data. It autonomously replicates the contents of one processor’s memory to the memory nodes of all other network members. Reflective memory can offer an attractive solution in many demanding applications because of its low latency and determinism. Using reflective memory, the typical node-to-node propagation time is on the order of 1 microsecond. Thus, in a system of 30 nodes, it would take only 30 microseconds to propagate through the network to all nodes. Achieving the same latency using other network technologies, such as Ethernet, is extremely difficult—if not impossible—even using datagram broadcast because of IP protocol overheads, addressing, and memory write times. GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [].

XMC Module Sports Dual 10 Gigabit Ethernet Interfaces

A conduction- or air-cooled, dual 10 Gigabit Ethernet XMC with front-panel or rear I/O support offers dual 10 Gbit Ethernet interfaces. A x8 PCI Express 2.0 port provides a high-speed interface between the XPort3300 and the host module via the P15 connector. The XPort3300 from Extreme Engineering Solutions is based on the Intel 82599, dual 10GbE controller and is well suited to rugged, embedded-computing applications such as remote sensor interfacing, traffic aggregation, storage and data offloading. Additional XPort3300 features include frontpanel I/O for the 10GbE interfaces that can be provided with either dual-optical, SFP+, fiber-optic connectors or a single RJ-45 10GBASE-T connector. The module supports dual rear 10GBASET interfaces through the P16 connector. It utilizes X12d I/O mapping per VITA 46.9 and also offers a x8 PCI Express 2.0 interface to the host module per VITA 42.3. The XPort3300 is engineered to scale from an air-cooled, commercial version (0° to 55ºC) to a rugged, conduction-cooled version (-40° to +85ºC) in accordance with appropriate environmental test methods. It comes with a guaranteed 4-hour technical response to all hardware questions. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].



Single-Chip GPS Requires Only 7 x 8 mm PCB Area

Designed for small, low-power, low-cost applications, a single-chip GPS device from u-blox delivers the positioning performance of u-blox 6 technology in a micro-miniature package: only 5 x 6 x 1.1 mm. Its high level of integration means a complete, stand-alone GPS system design can now fit on a PCB area smaller than the size of a thumbtack. The chip requires no external host. The UBX G6010NT provides high sensitivity, down to -162 dBm or -148 dBm during cold start, and fast acquisition times. Advanced RF-architecture and interference suppression ensures maximum performance even in GPS-hostile environments. UBX G6010-NT minimizes PCB area to less than 7 x 8 mm for a complete stand-alone GPS receiver. With most passive components integrated, the total system BOM requires as few as 5 external components including SAW filter and TCXO. An LDO and LNA are integrated and costly external memory is not needed. Lower price GPS crystals as well as TCXOs are supported. 2-layer PCB integration capability and small footprint ensures further cost savings. Designed for low power consumption, the chip includes breakthrough intelligent power management to support low-power applications. The chip operates from -40° to 85°C. u-blox, Thalwil, Switzerland. +41 44 722 7470. [].

Support Across The Board. From Design to Delivery Now, you can have it all.™ Faster and easier than ever before. Our commitment to customer service is backed by an extensive product offering combined with our supply chain and design chain services – which can swiftly be tailored to meet your exact needs. We have dedicated employees who have the experience to provide the highest level of customer service with accuracy and efficiency. All of our technical experts are factory certified on the latest technologies, providing you the expertise to move projects forward with speed and confidence. Avnet offers the best of both worlds: extensive product and supply chain knowledge, and specialized technical skill which translates into faster time to market – and the peace of mind that comes from working with the industry’s best. Avnet is ranked Best-In-Class* for well-informed sales reps, knowledgeable application engineers and our design engineering services – proof that we consistently deliver: > Industry recognized product expertise > Specialized technical skills Ready. Set. Go to Market.™ Visit the Avnet Design Resource Center™ at:

1 800 332 8638 *As rated by Hearst Electronics Group: The Engineer & Supplier Interface Study, 2009. ©Avnet, Inc. 2011. All rights reserved. AVNET is a registered trademark of Avnet, Inc.

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with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




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MEN Micro, Inc.......................................... 32..................................

Arbor Solutions........................................... 4................................................. www.arbor End One Stop Systems. of..................................... Article Products

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FPGA Board & USB Showcase.................. 11,13...............................................................


Logic Supply, Inc........................................ 41................................

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February 2011

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