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The magazine of record for the embedded computing industry

January 2011


Software Saves Power in High-End Networks Sort Out the Best Choice for Motor Control OpenVPX Opens Options for System Cooling An RTC Group Publication

EMBEDDED WINDOWS: The Next Generation

46 Rugged 6U OpenVPX 10 Gigabit Ethernet Switch Enables for ISR, C4I Systems

48 Compact 300 Watt 3 x 5” Switcher Comes in Five Models


50 Hybrid Flat Panel USB Controller Board – Ethernet and Wireless



Technology in Context


Managing Network Systems

Motor and Motion Control

for Power Efficiency 5Editorial 16 Mandates Security? Security You Say? Hah! Push Telecom Providers toward Software Optimization Industry Insider 6Latest Developments in the Embedded Marketplace Carter Edmonds, Kontron

10 & Technology 46Products Newest Embedded Technology Used by Industry Leaders Small Form Factor Forum The Little Engine that CAN

EDITOR’S REPORT Programmable Configurable ASICs

Atom Platform Integrated with Altera FPGA Already in OEM 12Intel’s SBC Product Tom Williams

TECHNOLOGY IN SYSTEMS Embedded Windows: The Next Generation

20 Goes Multicore: Microsoft 26 CEWindows Embedded Compact 7 Windows 7 Goes Embedded John R. Malin and Sean D. Liming, SJJ Embedded Micro Solutions

Douglas Boling, Boling Consulting

Precision High34Implementing Speed Linear Motion Control Todd Shearer, Galil Motion Control

Taxonomy of Motion Control 38AEncoder Technologies Foo Hong Thong, Avago Technologies

Industry watch New Approaches to System Cooling

New Approach to 3U VPX Conduction Cooled 42APreconfigured Systems Bill Ripley, Themis Computer

Embedded Systems More Secure with Windows Embedded 30 Making Standard 7 John Lisherness, Avnet Technology Solutions

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EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

10/16/09 11:43:57 AM

The magazine of record for the embedded computing industry

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Tom Williams Editor-in-Chief

Security? Security You Say? Hah!


K, folks, let’s get real. If you put it on a computer and that computer is connected to a network, it’s not secure. It may be difficult to get to, but it’s just plain not secure. I know, I know—I will surely get blowback explaining things that the responders are not “at liberty” to fully explain, telling me that things really can be made secure. But I’m not buying it. We’ve seen too much. The recent WikiLeaks imbroglio is but the latest example. When some Pfc can walk into his workplace with a Lady Gaga CD and walk out with all kinds of military and State Department cables, the word “security” becomes a laughing stock. Yes, I know there are higher levels of security and more “secure” networks, but all these things are really just a means of making difficulty of access appear greater than the value of that access to the intruder. They do not make the systems “secure.” In the case of the WikiLeaks breach, that relation was insufficient. The word “secure” comes from the Latin word “securus” meaning carefree, without care. It can also mean reckless or careless. It is the combination of se (without) plus curus (care). People working on computer security are definitely not carefree types. They are better off as paranoids. Securus is what we are not. At the time of this writing, the WikiLeaks upset is still in full swing. Recently there have been—in addition to the attempts of several governments to take down WikiLeaks—attacks by anonymous WikiLeaks hacker support groups against organizations they perceive as opposed to their champion. They have at least temporarily taken down sites for Master Card, Visa and a Swiss bank to mention a few. What we have been seeing is the outbreak of the world’s first infowar. Most of these have been denial of service attacks but things could easily turn more ominous and may give us a picture of what might happen if the PhD-studded cybertroops of nation states started going after each other. The recent rather successful attack on Iranian nuclear sites with the now infamous Stuxnet worm is an example. There is an irony in all this. The more our advanced technologies like power generation, transportation and communication depend on embedded computer intelligence, the more vulnerable they become to attacks using the same technology they are based

upon. For example, the Smart Grid is, in most informed opinions, essential to a more efficient, reliable and expandable system for energy distribution. Still, it depends heavily on embedded intelligence and networking—all of which can be compromised if hackers can breach the perimeter. It is being designed to prevent the uncontrolled spread of accidental outages but could as easily leverage the spread of intentional malicious access. We constantly hear hype about “evaluation assurance levels,” e.g., “EAL-5,” as if these meant anything about actual security. They are assurance levels that the claims made about the security of a software product have been evaluated to that level of assurance. To know anything about the actual security of the product, you also have to carefully examine those claims. And some of the documents filed that describe the strength of the security that is supposedly provided can have some pretty slippery language. But hype doesn’t make us secure. Besides, that which technology can supposedly reliably protect can also be breached by people by means of carelessness (there’s that word again), subterfuge or sex. How do we know there was only one Pfc with a Lady Gaga disc? How do we know there aren’t more of them and more sophisticated breachers going after even higher-level networks? The fact is that we don’t. The fact is that we never will for certain. The fact is that if you put it onto a computer that is connected to a network, it is not secure. It is at the very best simply more difficult to access than some bad guy feels is worth the trouble. In the end, of course, that is actually worth something. We have to try. We have to do better. But we cannot operate on illusions. We have to at some point be prepared for a catastrophic breakthrough. And we have to have the means of recovery at hand. What that might entail has been little studied, or at least little discussed. Could the same Smart Grid that is being designed to limit the scope of an outage also be designed to automatically detect and limit the damage caused by an intentional break-in? Could such techniques be applied to other systems? Maybe if we admit that the walls will never be perfect, we can develop more in-depth resistance to damage to go along with increased efforts to achieve the unachievable—complete security. RTC MAGAZINE JANUARY 2011



INSIDER JANUARY 2011 LynuxWorks and Themis Team to Demonstrate Rugged and Secure Server Solutions LynuxWorks and Themis Computer have announced that they have teamed up to demonstrate a new rugged, high-performance multilevel secure platform solution. The companies are showcasing LynuxWorks’ LynxSecure secure separation kernel and embedded hypervisor running on Themis’ CoolShell blade server. LynxSecure is a highly secure virtualization solution that utilizes the CoolShell’s hardware-virtualization technology and multiple processor cores to provide a versatile platform for secure environments. LynxSecure makes it possible to securely run multiple guest operating systems and their applications in separate partitions on a single platform. For example, it is possible to securely bring together multiple applications with varied security classifications and run them in separate partitions on a single server. This would allow low security applications such as C/ JMTK mapping, chat messaging and weather to run together on the same server with high security applications such as software defined radio (SDR). LynxSecure provides the necessary infrastructure for secure communication and works in conjunction with encryption and other protections required by specific applications. It conforms to the multiple independent levels of security (MILS) architecture, which provides strict guidelines for data isolation, damage limitation and information flow policies. Furthermore, LynxSecure’s virtualization environment allows legacy applications to run unmodified, enabling systems to be modernized with increased information sharing and security. Consolidating multiple applications on a single compact platform allows a savings in Space, Weight and Power (SWAP). It also reduces equipment costs and system maintenance. Themis’ CoolShell blade servers combine network connectivity with up to eight optical/copper ports and a simplified cabling system for easy installation and maintenance. Low total cost of ownership (TCO) is ensured by modular, front panel-only access for all active components. Network and I/O security is ensured through the use of independent controller channels, including both Copper and Fiber Gigabit Ethernet NICs. Themis’ CoolShell technology provides kinetic management and thermal headroom to accommodate aggressive scaling of commercial microprocessor and GPU core density, speed and power.

DDS Messaging Middleware Scores for High-Speed Gaming Platform

Real-Time Innovations (RTI) and Xuenn Limited, a mobile and non-mobile business and entertainment software solutions provider, have announced that Xuenn has deployed RTI messaging middleware in AgileBet, a popular sports betting platform. Used by some of the largest gaming companies in the industry, AgileBet uses RTI Data Distribution Service to enable the rapid processing of transactions. AgileBet requires low-latency, high-performance messaging with multicast capabilities and data-caching for odds engines, transactions, risk management and more. RTI’s messaging middleware easily meets these de-



mands while providing real-time communication between multiple distributed subsystems as well as high availability through redundancy and automatic failover. AgileBet can process at least 50,000 concurrent users at any given time, making such factors essential. Recently, Xuenn engaged the RTI Professional Services team to optimize Quality of Service (QoS) to assist with a large-scale deployment. The implementation involves the extensive use of RTI Data Distribution Service as the core messaging solution and a robust RTI monitoring system set up alongside. RTI Monitor, a graphical diagnostics tool, captures critical messaging traffic patterns for business analytics.

OpComp in October: A New Conference on Optical Computing

A new forum dedicated to optical computing technologies is being launched in October 2011. OpComp 2011 will take place on October 24th and 25th at the Wyndham Hotel in San Jose, California. It is intended to bring together academia, research and development, and application developers in one place to discuss optical computing technologies for critical embedded computing systems. Technology to be covered at OpComp includes connectors, waveguides, backplanes, chipsets and other key technologies. OpComp is a concentrated forum that provides the technical description of a sweep of new op-

tical technologies for computing that are currently under development or research. The business rational for these new technologies will be presented, as well as the practical challenges and opportunities associated with new optical computing technologies. Targeted for attendance at the sessions and exhibits are system architects, system designers, hardware designers, manufacturing and test engineers, product strategists, corporate and private investors, senior corporate managers, and government research organizations. A conference advisory panel is currently defining the program details. Companies interested in participating are encouraged to contact OpComp event organizers now at

Renesas and Green Hills Collaborate to Develop Software for CPU Virtualization

Renesas Electronics and Green Hills Software have announced collaboration to jointly develop basic software supporting CPU virtualization technology suitable for real-time control applications as well as a software development environment. Through the collaboration, Renesas will develop added functions necessary for the efficient operation of virtualization software. This will enable high-speed real-time control and improve the usability of the software development environment. The functions will be incorporated into microcontrollers (MCUs) with a V850 CPU core. Green Hills Software will port the Multi integrated development environment (IDE), which includes components such as a compiler and a debugger that already support Renesas V850

cores. The new CPU virtualization technology will provide support for software that enables multiple applications to run independently and simultaneously on a single CPU, such as the Integrity RTOS. The Green Hills IDE will generate compact and high-speed instruction code optimized for the CPU virtualization technology provided by the Renesas Electronics V850 core. When combined with virtualization software such as Integrity Secure Virtualization, which supports safety standards such as IEC 61508, the software development environment will deliver the

means to develop and implement with high efficiency applications with excellent functional safety. There are also plans to include support for the emerging ISO 26262 functional safety standard. The software development environment will be available through Green Hills Software as part of the Multi product family.

Cavium Networks Extends MIPS Architecture License

MIPS Technologies has announced that long-time MIPS licensee Cavium Networks has reaffirmed its commitment to the

MIPS architecture by renewing its license of the high-performance MIPS64 architecture. The MIPS64 architecture provides a high level of performance for applications including networking and computing. Incorporating powerful features, standardizing privileged mode instructions, supporting past ISAs and providing an upgrade path from the MIPS32(R) architecture, the MIPS64 architecture provides a solid high-performance foundation for future MIPS processorbased development. Cavium’s Octeon multicore processor family, based on the MIPS64 architecture, offers a

scalable, high-performance, lowpower solution for intelligent networking applications ranging from 100 Mbit/s to 40 Gbit/s. The Octeon processors have been widely adopted in mainstream and leading-performance routers, switches, storage networking equipment, security appliances, data-center equipment, and a broad range of 3G, WiMAX and LTE infrastructure equipment including base stations, radio network controllers, aggregation systems, mobile subscriber gateways and deep packet inspection (DPI) equipment.

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at Closing Price 52 Week Low 52 Week High Market Cap

RTEC10 Index



Adlink Technology


















Company Market Performance

Elma Electronic Enea Interphase Corporation










Mercury Computer Systems





Performance Technologies





PLX Technology





RadiSys Corporation





Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities.




Emerson and Mercury Team to Promote Interoperability Standards in Military and Aerospace

Emerson Network Power and Mercury Computer Systems have announced that they will collaborate to promote interoperability on open standards-based subsystems for military and aerospace applications. This alliance seeks to provide interoperability between the companies’ range of embedded computing solutions, in order to enable defense customers to migrate their performance away from proprietary closed architectures to flexible open solutions, reducing risk and lowering development and deployment costs as a result. This alliance combines the strengths of both companies— Mercury’s leadership in high-

performance signal and image processing, open standards hardware and software and systems integration and services—with Emerson Network Power’s leadership in standards-based embedded computing technology for the telecommunications, industrial automation, aerospace/defense and medical markets.

Energy Micro Appoints World’s First VP of Simplicity

Energy Micro has announced the appointment of Ă˜yvind Grotmol as VP of Simplicity. Supporting the company’s aim of dramatically reducing MCU system complexity and development times, Ă˜yvind will head up the evolution of Energy Micro’s software tools, code libraries and

development kits, including the recently announced Simplicity Studio and RF protocol stacks for the upcoming Energy Friendly Radio (EFR) products. Grotmol moves to Energy Micro from Medallia, Inc., where he was director of research and innovation, building a marketleading SaaS platform including OLAP, data mining and visualization, and text analytics technology. He relocates from Sunnyvale, California to Energy Micro’s Oslo, Norway headquarters. Ă˜yvind previously developed patented technology for hardware data compression for Tandberg Storage and won the Microelectronics Award from the Norwegian Microelectronics Forum and the industry magazine Elektronikk for his thesis written at Nvidia. He has won medals

in the International Mathematical Olympiad, the International Physics Olympiad, and the ACM International Collegiate Programming Contest World Finals, and holds an MSEE from NTNU in Trondheim, Norway. The ultra-low-power EFM32 Gecko microcontroller’s comprehensive development environment comprises Energy Micro’s own energyAware software tools and code libraries, development kits and a broad range of third-party IDE/compiler, debug adapter, programmer and RTOS products.

Freescale MPC8536e Computer On Module The CSB1880, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, network oriented, PowerPC based Computer on a Module (COM). The CSB1880 provides a small, powerful and flexible engine for embedded Linux based GIGe networking applications of all kinds. y y y y y y y y y y

1.25GHz Superscalar e500 Core w/512KB L2 Cache 512MByte 64-Bit Wide DDR2-667 Memory with 8-Bit ECC 64MByte NOR with Secure ID, and 512MByte SLC NAND Two PCIe x4 Port (or one x4 and Two x2's) Two 10/100/1000 ports via BCM5482S to Copper/Fiber PHY Two SATA Gen 2 (1.5Gbit or 3.0Gbit/sec) Channels Three 480Mbit USB 2.0 Host Ports <7W Typical, 12W Maximum, <3W in Jog Mode 95mm x 95mm x 8mm (using 5mm COM Express Connector) Linux 2.6.x BSP with available 1 year of support

Now Available for direct order from Digi-Key The CSB1880 is manufactured in our in-house state of the art, lead-free surface mount manufacturing line. All products carry a 1-year warranty and are available in commercial and industrial temperature versions. Cogent also offers standard and custom carrier boards, plus royalty free licensing options for the CSB1880.



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Colin McCracken & Paul Rosenfeld

The Little Engine that CAN


n a surprising new round of I/O Whac-a-mole, embedded SBCs are popping up all over the place with an onboard interface that used to require a separate I/O expansion card. Once relegated to automotive applications, the Controller Area Network (CAN) bus can now be found in myriad industrial automation, military and even some medical applications. So CAN interfaces on SBCs shouldn’t be a surprise; applications seem to be the driving force. That should make for an interesting Embedded World in Germany this year. The Germans savor their CANbus just like a tall cold weissbier in the Altstadt. Actually, this latest SBC trend hasn’t come about due to target application demand. The new Intel Atom E-series (“Tunnel Creek”) processor family is behind it. Or, to be more precise, its companion chip, the E620T “Topcliff” I/O Hub, is the culprit. Despite repeated denials from the chip manufacturer that it is not targeting only high-volume “IVI” (In-Vehicle Infotainment) applications (“car PCs” in lay terms), all signs point to IVI as the target market for this processor / I/O Hub combo. The result is an integrated CANbus controller in the E620T chipset. Once again, the broad embedded market reaps rewards from the 15-billion-connected-devices strategy of the mother ship. For that, we are eternally grateful, as we understand that rising development costs will forever prohibit a true “designed by embedded, for embedded” x86 system on chip. But even a leftover meal still counts as a meal. Not only will automotive, military vehicle and factory applications enjoy reduced size, weight, power and cost (SWaPaC) compared to legacy PC/104 card stacks, but this free integrated CAN controller has the potential to drive the adoption of CANbus and its high-level protocols into completely new applications. The significance of this milestone cannot be understated. SBCs ranging from motherboard form factors down to PC/104 SBCs will become available in 2011 with a CAN-do attitude. This will gradually reduce the need for legacy single-purpose and even multifunction I/O cards. Four free serial ports in that same I/O hub just add more fuel to the fire. Yes, after years of stripping application-oriented I/O and buses out of the chipset for desktop and laptop use, a reversal of fortune has come from a most unsuspecting place. And as usual, for all the wrong rea-



sons—but who’s complaining?!? Say “Thank you” and don’t bite the hand that feeds us. SBCs have the intrinsic luxury of supporting new I/O features, such as CAN, via pin headers or PC-style connectors while maintaining existing standards (board form factors and bus connectors). It’s a good thing, since it takes far too long for trade groups to wrangle through even simple changes to standards, and legacy compatibility is usually sacrificed. Unfortunately, life is not so easy for the fragmented computer-on-module (COM) form factor standards since, by definition, the only path off the board for chipset signals is through the baseboard connector(s). With hundreds of signals crammed onto high-speed-capable surface mount connector pins, standards architects rarely leave any reserved pins for future “unanticipated” chipset interfaces. Consequently, most COMs are CAN’t-do when it comes to the E620T windfall. Major changes will be required to take advantage of the new “free” CAN interface. COMs have rapidly penetrated most high-volume market segments. These small form factor modules contain only the processor, memory, chipset and LAN controller, which form the greatest common factor (subset) of modern embedded apps. COMs are the little engines that run the system software—OS(s) and application(s)—that power each baseboard full of I/O boxcars, hopper cars and tanker cars that are hooked together to form each unique embedded system. Of course, not encumbering COMs with the particulars of diverse applications was what allowed COMs to reach heads of steam in the first place. But the lack of an easily implemented CANbus might keep the latest round of little engines from crossing over into CAN territory the way that new SBCs can. Quietly, a dark horse express train is chugging along new high-speed digital-only COM tracks. CoreExpress is the first open standard COM form factor to feature CAN support. While rival standards sit stranded at their respective bridges, scrambling to lay tracks for new pinout types, the CoreExpress form factor enters the scene as the Little Engine that CAN. Could this be a sign that other “application COMs” are just around the corner? We will all have to put our ears to the ground to find out.

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editor’s report Programmable Configurable ASICs

Intel’s Atom Platform Integrated with Altera FPGA Already in OEM SBC Product Code named Stellarton, the new platform mates an Atom CPU with an Altera FPGA via PCI Express for a configurable and customizable platform as the basis for a PCIe/104 SBC. by Tom Williams, Editor-in-Chief


he trend we have been witnessing with its device. This may or may not make over roughly the past nine months of a difference, but it will be interesting to integrating FPGAs with embedded see how the perspective of the processor processors for custom I/O functionality, company influences the character of the just got another validation with the en- part. We have noted in previous coverage try of Intel. Originally code named Stel- of this area that there are potentially many larton, Intel’s entry consists of a series of approaches and many application areas modules featuring an Atom E6xx proces- that will benefit from those approaches. In the case of Microsemi (especially), sor (formerly code named Tunnel Creek) and Xilinx as well to a certain extent, combined with an Altera Arria II GX there is a goodly amount of preconceived FPGA. The two devices are mounted on a nies providing solutions now functionality installed on the FPGA por37.5 mm x 37.5 mm, 0.8 ball pitch module ion into products, technologies and companies. Whether your goal is to research the latest tion from the beginning. The Microsemi with two PCI Express x1 lanes connected ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you SmartFusion, for example, has a big slant to a hard-wired PCIe link on the FPGA. you require for whatever type of technology, toward analog processing already built in. The Intel for. introduction differs from and products you are searching The Xilinx effort looks like it will also previous devices introduced by Actel— have a certain amount of A to D and a now merged with and under the brand few other I/O functions preinstalled. Of name of Microsemi—and Xilinx (see The course, the customer can always alter what Application Services Platform: A New Class of Devices for Embedded Develop- is in the programmable section. In addiment and Systems, RTC April, 2010, p. 12). tion, the ARM-based examples also inIn the previous two cases, FPGA manu- clude a number of standard peripherals in facturers integrated ARM processors with the CPU section of the design. The Atom their own FPGAs. Intel is the first CPU portion of the E6x5C series integrates vendor to bring in an FPGA to integrate such things as display control, graphics processing, memory control and audio on the CPU die as well (Figure 1). Get Connected The Intel E6x5C series by contrast with companies mentioned in this article. is not delivered with any preinstalled IP.

End of Article



Get Connected with companies mentioned in this article.

That is left up to the OEM customer to install by means of Altera or third-party IP libraries or through the use of Altera’s Quartus II development tool. Lest this seem harsh, it should be noted that the E6x5C is only one option for the use of the E6xx Atom family. Intel designed the processor with a PCIe link to the outside world so that developers could take advantage of a variety of I/O options. Intel itself supplied an I/O hub that supports a range of common I/O interfaces such as GPIB, USB, PCIe, CAN, etc. Other hubs are coming to be available from thirdparty vendors with sets of interfaces targeted at specific areas such as in-vehicle entertainment or IP media. In fact, it is also possible to use the E6x5C series with an I/O hub connected to the processor’s other external (2 x1) PCIe connection. The second PCIe connection can be used for anything including another I/O hub. The point of the FPGA is to offer flexibility and the ability to tightly integrate specialized, custom and proprietary I/O functionality without adding additional components. Such specialized I/O functions represent a good part of an OEM’s value add. In terms of flexibility, it is also straightforward to implement different product versions and variations with the same hardware inventory and often during the same production run simply by changing the IP in the FPGA. Just how these new devices—and we predict there will be more and different variations from these and other vendors— will compare in terms of cost and performance is yet to be determined. The E6x5C series is currently available in six version—three clock frequencies of 0.6G Hz, 1.0 GHZ and 1.3 GHz in two temperature ranges each—commercial 0° to 70°C and industrial -40° to 85°C. The current offering also still consists of two devices mounted on a small circuit board with a ball grid array on the bottom. Intel is not talking about future products but it would appear that the eventual integration of the two devices into a single IC package if not onto the same die would be a logical next step. The E6x5C is already debuting on an

editor’s report

OEM product, the Microspace ModuleST (MSMST) from Kontron (Figure 2). The MSMST is implemented on a PCIe/104 form factor, which also includes an interface to the High-Speed Mezzanine Card (HSMC), which is a specification from Altera meant to simplify interfacing I/O connections to its FPGAs. This is a part of the Kontron design and is not required by the Intel platform. In this iteration of the MSMST, the multimedia interfaces SVDO and HD audio are brought off to a separate media board along with a PCIe connection to Ethernet. So not only is the FPGA itself a support for flexibility and configurability, but so are the other external interfaces from the CPU die (Figure 3). Kontron Product Marketing Manager Christine Van De Graaf notes that Kontron had already noticed that OEM customers were going around the I/O hub supplied by Intel and programming directly onto FPGAs—which is actually one of the options offered by Intel with the introduction of the Tunnel Creek parts. The availability of the E6x5C series with the FPGA preintegrated and verified now makes that much easier and so it was a natural step to produce a ready-to-go platform that customers could use to get their proprietary IP up and running for their specialized needs. For example, there are apparently a number of specialized I/O functions in the transportation arena that were already being solved with FPGAs on separate modules connected to the SBC. While Actel’s (now Microsemi’s) SmartFusion is now appearing in products, the Kontron MSMST appears to be the first OEM single board computer available in a standard form factor that developers can take and use to develop whatever application they have in mind and/or integrate it with other off-theshelf modules to address a given set of needs. The E6x5C can support embedded Windows with a variety of BIOS options and is also offered by Intel with the support of the now Intel-owned Wind River MeeGo or VxWorks operating systems, making it as general-purpose a product as many other Atom-based modules with the

Intel Atom Processor 512 KB L2 (600 MHz, 1.0 GHz, 1.3 GHz) DDR2

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OEM I/O Blocks



DSP Multipliers Internal Memory

Figure 1

Intel Atom Processor E6x5c Series Altera FPGA

The Intel E6x5C platform consists of an E6xx series Atom CPU in one of three clock frequencies and one of two temperature ranges integrated on a ball array circuit board with an Altera via a hard-gate PCIe connection. Other peripheral interfaces including two more PCIe lanes are available directly off the CPU. Clock generator and power management ICs are available from third parties.

Figure 2 The Kontron MSMST module is implemented on a PCIe/104 board with a connector off the FPGA for attaching an Altera high-speed mezzanine card (HSMC).

added attraction of the programmable and configurable FPGA option. The HSMC connection allows the developer to easily bring out the I/O connections of the FPGA package so that they can be connected to external devices. These

connections can be routed to whatever IP the OEM or the customer has placed on the FPGA and then to the appropriate external connectors. In addition to the IP that can be purchased from libraries and can be developed from scratch using the RTC MAGAZINE JANUARY 2011


editorâ&#x20AC;&#x2122;s report

MediaBoard VGA/DVI VGA/DVI Mic, Line, SPDIF LAN RJ45

Intel Atom E6xc5C (Stellarton)




Quartus II design tools, Kontron also offers a service through which they will help the customer develop that custom IP. Like Intel, Kontron has not installed any predetermined IP blocks in the FPGA, although that does not preclude any other vendor who may wish to from doing so.



PC Ie 1 x1



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Altera San Jose, CA. (408) 544-7000. []. Intel Santa Clara, CA. (408) 765-8080. [].


PCIe 2x1




Kontron Poway, CA. (888) 294-4558. [].



Figure 3 Block diagram of the Kontron MSMST.

Extreme Environment Barebones Â&#x2018;Â&#x2122;ÇŚÂ&#x201D;Â&#x2018;ƤÂ&#x17D;Â&#x2021; Â?Â&#x2013;Â&#x2021;Â&#x17D;ĚžÂ&#x2013;Â&#x2018;Â?ĚżÂ&#x2018;Â?Â&#x2013;Â&#x201D;Â&#x2018;Â&#x17D;Â&#x2018;Â&#x161; &Ä&#x201A;ŜůÄ&#x17E;Ć?Ć?Ç Ĺ?Ć&#x161;Ĺ&#x161;ͲϰϏΣʹϳϏΣĹ˝Ć&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x;ĹśĹ?Ć&#x161;Ä&#x17E;ĹľĆ&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x161;ĆľĆ&#x152;Ä&#x17E;Ć&#x152;Ä&#x201A;ĹśĹ?Ä&#x17E;Í&#x2DC; /ĹśÄ?Ć&#x152;Ä&#x17E;Ä&#x161;Ĺ?Ä?ĹŻÇ&#x2021;Ä?ŽžĆ&#x2030;Ä&#x201A;Ä?Ć&#x161;Ä&#x201A;ĹśÄ&#x161;ĨƾůůĨÄ&#x17E;Ä&#x201A;Ć&#x161;ĆľĆ&#x152;Ä&#x17E;Ä&#x161;Í&#x2013;ŜŽÄ?ŽžĆ&#x2030;Ć&#x152;ŽžĹ?Ć?Ä&#x17E;Ć?Í&#x2DC;

High-End IntelÂŽ Coreâ&#x201E;˘2 Duo with PCI Expansion &Ä&#x201A;ŜůÄ&#x17E;Ć?Ć?Ĺ˝Ć&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x;ŽŜÍ&#x2013;Ç Ĺ?Ć&#x161;Ĺ&#x161;Ć?Ć&#x161;Ä&#x201A;ĹśÄ&#x161;Ć?ͲϰϏΣʹϳϏΣĆ&#x161;Ä&#x17E;ĹľĆ&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x161;ĆľĆ&#x152;Ä&#x17E;Ć&#x152;Ä&#x201A;ĹśĹ?Ä&#x17E;Í&#x2DC; tĹ?Ä&#x161;Ä&#x17E;Ć&#x152;Ä&#x201A;ĹśĹ?Ä&#x17E;ŽĨ/ÍŹKĹľÄ&#x201A;ĹŹÄ&#x17E;Ć?ĨŽĆ&#x152;Ä&#x201A;Ĺ&#x2021;Ä&#x17E;Ç&#x2020;Ĺ?Ä?ĹŻÄ&#x17E;Í&#x2022;Ć&#x152;ĆľĹ?Ĺ?Ä&#x17E;Ä&#x161;Ĺ?Ç&#x152;Ä&#x17E;Ä&#x161;Ć&#x2030;ĹŻÄ&#x201A;Ć&#x17E;Ĺ˝Ć&#x152;ĹľÍ&#x2DC;

Expertise only an Industry Leader can provide. ^Ä&#x17E;ĹŻÄ&#x17E;Ä?Ć&#x;ĹśĹ?Ä&#x201A;Ä?ŽžĆ&#x2030;ĹŻÄ&#x17E;Ć&#x161;Ä&#x17E;Í&#x2022;Ä&#x161;Ä&#x17E;Ä&#x161;Ĺ?Ä?Ä&#x201A;Ć&#x161;Ä&#x17E;Ä&#x161;Ć&#x2030;ĹŻÄ&#x201A;Ć&#x17E;Ĺ˝Ć&#x152;ĹľĨĆ&#x152;Žž>Ĺ˝Ĺ?Ĺ?Ä?^ĆľĆ&#x2030;Ć&#x2030;ĹŻÇ&#x2021;Ĺ?Ć?Ć?Ĺ?ĹľĆ&#x2030;ĹŻÄ&#x17E;Í&#x2014;WĆ&#x152;Ä&#x17E;ͲÄ?ŽŜĎĹ?ĆľĆ&#x152;Ä&#x17E;Ä&#x161; Ć?Ç&#x2021;Ć?Ć&#x161;Ä&#x17E;ĹľĆ?Ć&#x2030;Ä&#x17E;Ć&#x152;ĨÄ&#x17E;Ä?Ć&#x161;ĨŽĆ&#x152;Ä?Ĺ˝Ć&#x161;Ĺ&#x161;Ä?ĆľĆ?Ĺ?ĹśÄ&#x17E;Ć?Ć?Î&#x2DC;Ä&#x161;Ä&#x17E;Ć?ĹŹĆ&#x161;Ĺ˝Ć&#x2030;ĆľĆ?Ä&#x17E;Í&#x2022;tĹ?ĹśÄ&#x161;Ĺ˝Ç Ć?Î&#x2DC;>Ĺ?ŜƾÇ&#x2020;Ä&#x161;Ä&#x17E;Ç&#x20AC;Ä&#x17E;ĹŻĹ˝Ć&#x2030;ĹľÄ&#x17E;ĹśĆ&#x161;Ć?Ä&#x17E;Ć&#x152;Ç&#x20AC;Ĺ?Ä?Ä&#x17E;Ć?ĨŽĆ&#x152; Ĺ?Ć&#x152;Ä&#x17E;Ä&#x201A;Ć&#x161;Ä&#x17E;Ć&#x152;Ć?Ç&#x2021;Ć?Ć&#x161;Ä&#x17E;ĹľÄ?ĆľĆ?Ć&#x161;ŽžĹ?Ç&#x152;Ä&#x201A;Ć&#x;ŽŜÍ&#x2022;Ä&#x201A;ĹśÄ&#x161;Ä&#x201A;Ç Ä&#x17E;Ä&#x201A;ĹŻĆ&#x161;Ĺ&#x161;ŽĨŽŜůĹ?ĹśÄ&#x17E;Ć&#x152;Ä&#x17E;Ć?ŽƾĆ&#x152;Ä?Ä&#x17E;Ć?Ä&#x201A;ĹŻĹŻÇ Ĺ?Ć&#x161;Ĺ&#x161;Ĺ?ĹśÄ&#x201A;ĨÄ&#x17E;Ç Ä?ĹŻĹ?Ä?ĹŹĆ?Í&#x2DC;

Learn More > Š 2010 Logic Supply, Inc. All products and company names listed are trademarks or trade names of their respective companies.


Untitled-2 1


10/8/10 9:50:23 AM

Technology in


Managing Network Systems

Mandates for Power Efficiency Push Telecom Providers toward Software Optimization New hardware investments offer a range of features for power savings. But these can only be truly realized with the proper software techniques. Together these can attain up to 32 percent power savings. by Carter Edmonds, Kontron


ower efficiency has emerged as one of the key areas for long-term improvement in telecom applications. Reduced energy usage means lower costs and diminished environmental impact. In turn, potential savings for carriers are significant when evaluated against the “always on” central office or data center. Hardware is commonly the starting point when evaluating telecom power efficiencies, given current silicon advances that provide capabilities for effectively managing a server’s power consumption. Software is considered less often and is routinely overlooked in the quest for power savings. However, dramatic energy savings can be achieved by focusing attention on the operating system, its configuration and the application itself. Software optimization techniques add significant value to hardware investments, and can contribute up to a 32 percent reduction in power consumption under various workloads common to the data center or central office.

Industry Perspective

Industry-wide focus on energy savings, driven by Verizon’s initiative targeting an aggressive 20 percent annual power reduction on deployed systems, il-



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2.6.27 50000


Throughput (Transactions per Second) Figure 1 A sample workload using two popular releases of the Linux kernel, 2.6.27 and 2.6.18. In particular, 2.6.27 adds the tickless kernel and 2.6.18 does not. Using the less sophisticated timing mechanism on the earlier kernel, the idle machine consumed 163W versus 133W with the tickless kernel, which delivered an 18 percent savings in power. Even with a significant workload, savings topped 12 percent by using the more sophisticated timing feature of the current Linux OS.

lustrates the urgency carriers are placing on power efficiency policies. Energy cost management is extensive, and includes not only the initial cost to supply energy but also the expense of removing it again as heat. The resulting thermal management requirements can double the cost of the

energy usage alone. Moreover, waste heat limits equipment density, consuming valuable space and restricting service capacity, especially in well-established central offices with fixed building outlines. Verizon’s initial poll of telecom vendors and manufacturers indicated con-

technology in context

fidence in achieving a 10 to 15 percent reduction in power consumption for new equipment; the resulting initiative was intended to push that envelope by setting a 20 percent goal. The initiative is based on formulas designed to test the power consumption of equipment in various operating conditions, and includes a specific measurement process and series of Telecommunications Equipment Energy Efficiency Ratings.

Opportunities to Find Power Savings

Telecom equipment is typically deployed adequately for expected peak traffic plus headroom. As a result, portions remain partly idle and the system rarely operates at peak load. For telcos, this creates a unique opportunity to increase power savings by effectively matching power consumption to server workload. Applying software techniques to control CPU power usage, for example, creates different levels of usage by defining a performance cycle and a sleep cycle. P-states, or the level of CPU performance, represent particular CPU frequencies. This refers to how fast the CPU and its various cores process data, along with its corresponding power requirement. Cstates represent sleep states achieved when portions of the processors are directed to remain inactive. Deeper sleep states consume less power but require more time to return back to work. Since higher speeds consume more power, system architects would logically assume that reducing processing speeds will save power. However, occasionally P-states and C-states work against each other, requiring deeper knowledge of the application itself. For example, applying C-states may be a particularly prudent option given the high number of cores that can be found in enterprise servers or data center systems. A server may be implemented with eight cores but only require one to complete a particular task. An installed operating system would make some of these decisions by default; however, system expertise is often required to define the ideal settings for performance and power, often locked in for long-term operation. Optimization techniques address this conflict, matching the

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2.6.27 30000


Low P-State 50000


Throughput (Transactions per Second) Figure 2 The power savings achieved by choosing a lower power state for our particular workload. The top two curves are copied from Figure 1, which used only the “on-demand” kernel. The bottom line shows the power savings achieved by taking the tickless kernel (2.6.27) and applying the “user space” governor to place the processors in the lowest power state (i.e. lowest frequency).

workload to the best hardware management scheme and evaluating P-states and C-states for ideal performance. Self-tuning policies on performance vs. power are anticipated in the future. However, today’s system architects must not only evaluate power/performance schemes up front but also understand how the application itself impacts chosen software techniques and options.

Software Optimization

Not long ago, servers were largely unaware of power as a strategic asset in achieving top performance. Servers were always on, or at best turned on and off to match usage patterns—and idle servers used as much power as servers under load. Recent hardware generations have included power reduction circuitry that cooperates with software enhancements to reduce idle power consumption as well as power consumption under load. This hardware has power savings built in, however, benefits are only realized if the software implements power saving algorithms. Unused parts of the chip can be turned off automatically through hardware and software, akin to turning off the lights as you walk through the house. Unlike power management schemes that turn entire servers on and off, these power transitions take milliseconds instead of

minutes and the OS remains alive and operational during the process. Note that the power readings presented here are not intended as benchmarks. Rather, they describe techniques for optimizing hardware and workload. Tests used a Kontron CG2100, commercially available Linux distribution, and a modified version of the open-source eBizzy workload generator. Upgraded Kernels Coupling new hardware with a recent OS is a great step forward for many telco systems. In Linux, for example, more recent kernels have an improved scheduler that makes better use of the hardware’s power and sleep states. While all recent Linux kernels contain some support for sleep states, 2.6.21 introduced the “tickless” kernel. The tickless kernel leverages the High Precision Event Timer (HPET) found on today’s chipsets to schedule events; processors sleep longer, conserve significant power and no longer require a CPU to wake up in order to increment a counter. A demonstration of the effects of using the tickless kernel is shown in Figure 1. This simple advantage is not necessarily common to every OS distributor; each has a different policy for releasing new kernels, and several major distributors in the server space do not yet include the tickless kernel. RTC MAGAZINE JANUARY 2011


technology in context

be known by characterizing the workload on a real machine or suitable simulator. Moreover, power efficiency is only one goal and must be considered within quality of service, and the metrics of throughput and latency.

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175 150



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Low P-State 40000

X Attempts



Throughput (Transactions per Second) Figure 3 Changes in data points, resulting from changing the number of threads and the number of active cores. Data points below the original three lines indicate the parameters that outperformed the built-in options, implemented with an optimized power governor.

Power Governors Servers need a strategy for how fast to process data and how often to sleep, i.e. controlling the P-states and C-states to achieve the largest energy and performance advantage. Policies such as these are implemented in the Linux power governors, and often start by asking some tough questions. Since processors consume more power at higher frequencies and minimal power while sleeping, is it better to finish a task quickly and sleep more or is it better to sleep less but consume less power while awake? For some workloads, system administrators may determine that it is ideal to have the processor running as fast as possible. Although consuming greater power, it completes its task quickly and returns to C-state. Other workloads, however, perform to improved power settings by letting the CPU run as slowly as possible. Even though a particular core is kept awake longer, it consumes less power during the task. The answer is workload dependent and requires tradeoffs between throughput, latency and power consumption. Three different types of workloads must be considered, including processes that are CPU-bound, memory-bound or I/Obound. For example, some workloads are CPU-bound for brief spikes of activity, such as when new packets come in to



be processed. In these cases, the processors run at high frequencies to complete their work quickly and then immediately return to sleep until the next spike, maximizing the amount of sleep time and minimizing power consumption. The Linux “on-demand” governor implements this particular policy and it is the default in most distributions. Figure 2 illustrates a memory-bound application and shows the power savings achieved by choosing a lower power state for this particular workload. Changes in processor frequency affected it slightly, but increasing cache size improved throughput greatly. As a result, the sample workload showed greatest power savings when run at the lowest frequency because much of the processor’s time was consumed waiting for data to return from the memory controller. Overall, telecom applications driven by I/O present an interesting challenge. If the thread begins with the arrival of a packet, the best strategy depends on what is happening to that packet. A packet compared against an in-memory lookup table might benefit from the lower processor speed since execution speed is gated by memory throughput whereas a mathematical operation on the packet might benefit from a higher processor speed. Further, none of this considers cache locality. In all cases, the answer can only

Interrupt Handlers Interrupt handlers present telcos with tradeoff options between power and performance. Dispersing hardware interrupts as widely as possible may maximize throughput, however, at less than peak load this merely wakes processors that could otherwise sleep. Consider a packet forwarding application that receives incoming packets on multiple network interfaces. At peak load, it often makes sense to assign each interrupt handler to a separate core. At less than peak load, it is possible to achieve the requested throughput and latency while consolidating interrupt handlers on a smaller number of cores. The OS makes no attempt to optimize this sequence for ideal power usage. Achieving power reduction here requires continual re-balancing of the interrupts based on quality of service measurements such as throughput and latency. A software daemon would consolidate or disperse interrupt handlers to achieve the desired balance. For consistency, these tests pushed all interrupts to a single core. A real-world telecom application would need to spread interrupt handlers more widely when quality of service required better throughput or latency. Application Tuning One non-power-aware application in the mix can spoil overall power savings. For example in a packet inspection application, worker threads might be dispatched to perform the actual decoding, analysis and lookup as new packets arrive. Without optimization for power awareness, the application could let the worker threads sit in a polling loop while waiting for new work items to appear in the queue. The processor handling the thread would be fully awake, consuming full power. A power-aware application would allow these threads to block, returning to the scheduler while waiting for the new event. In this instance, the

technology in context

processor would sleep until needed, again saving significant power. Core selection is another power vs. performance tradeoff that can be controlled by the user. If coded correctly, idle cores consume minimal power. As threads are assigned to cores however, performance tradeoffs may arise because certain resources are shared. For instance, hyperthreaded core siblings share most of the same CPU resources, and cores within a single CPU share input/output (I/O) and cache. Adding a second CPU doubles the cache, and sharing cache may or may not be preferred depending on the application. By default, the OS scheduler will dispatch threads as widely as possible although this can be adjusted through CPU affinity. If threads do share data, cache locality suggests that threads should be kept as close together as possible, for example using cores in the same package behind the same cache. In contrast, many applications benefit from sharing as little hardware as possible. In a dual-processor server, bringing the second package online also doubles the amount of cache, a real benefit to performance in most cases. Figure 3 show some gains that can be achieved by changing the number of threads and active cores.

global basis. As a result, system architects must understand the range of hardware and software options for meeting and exceeding energy efficiency standards today. Software optimization can differentiate significantly greater results than achieved with hardware alone, ideally driving telcos to leverage both resources for the right combination of bandwidth, performance and reliability within the most competitive power threshold. Blending the know-how

of hardware development with extensive software expertise provides the fine tuning that distinguishes an efficient system from one optimized for long-term, application-specific power awareness. Kontron Poway, CA. (888) 294-4558. [].

Putting It All Together

The most competitive power efficiencies result from a well-written application running on the latest hardware and software. By adding greater levels of software optimization, power savings are advanced even further with a daemon that adaptively adjusts CPU affinity, interrupt handlers and CPU frequencies or power states. By using a workload generator and tuning each system, a dramatic 18 to 32 percent power savings was realized at various workload levels when compared to the original power/performance curve with the out-of-the-box (2.6.18) kernel. A truly adaptive policy would monitor incoming requests and quality of service metrics to determine if additional hardware resources would benefit the workload presented at any given time. Telcos are challenged to meet new energy protocols, and future goals will likely set an even higher bar, intended to continually improve energy savings on a Untitled-5 1


1/11/11 11:33:28 AM RTC MAGAZINE JANUARY 2011

technology in


Embedded Windows: The Next Generation



tech in systems

Windows 7 Goes Embedded It has been almost a decade since a new Windows Desktop OS migrated to the embedded space, and Windows Embedded Standard 7 does not disappoint. John R. Malin and Sean D. Liming SJJ Embedded Micro Solutions


indows Embedded Standard 7 (WES 7) takes the latest Windows desktop operating system, Windows 7, into the embedded space just as its predecessors, Windows XP Embedded and Windows NT Embedded did for Windows XP and Windows NT before that. WES 7 still offers the ability to create custom Windows OS images and continues the use of embedded enabling features that go beyond the normal desktop capability. WES 7 does take a departure from the development of the predecessors, but the benefits of these tools help to support the product life cycle. Best of all WES 7 supports creating 32-bit and 64-bit Windows OS images. Applications can still be developed with the latest Visual Studio and .NET Framework SDK development tool. All the application and custom driver development work can take place on the desktop before spending time or money with the WES 7 tools. The three driving factors for using Windows embedded have been familiarity with the Windows desktop operating systems, familiarity with the Windows application development tools that provide access to a rich graphical user interface (GUI), and the open PC architecture with readily available off-the-shelf hardware. These driving factors apply to WES 7 as well, but there are several deeper reasons why WES 7 is an improvement over its predecessors: new, from the ground-up development tools, shorter development time, easier target deployment and better servicing.

The .NET Framework Bet

Windows XP Embedded has found its way into a variety of embedded systems such as gaming machines, medical test equipment, set top boxes, in-vehicle computing, shipping equipment, test and diagnostic systems, kiosks, ATM machines, think clients, digital displays, vending machines and security systems just to name a few. The ability to quickly develop a graphical user interface (GUI) application has been the main reason for this success. Certainly there are different GUI development packages available for different operating systems, but the ease of programming and the ability to find the resources is very important. Javaâ&#x20AC;&#x2122;s popularity sparked an idea to re-think the way Windows applicaRTC MAGAZINE JANUARY 2011


Tech In Systems

tions were developed. .NET Framework launched several years ago made writing Windows applications faster without having to deal with mundane tasks like memory management. Once accepted by Windows programmers, new capabilities to create rich and dynamic applications have been added with the latest .NET Framework releases. The big bet on .NET Framework is now paying dividends. Because Java has not advanced as rapidly as .NET Framework, we have had a few developers looking to use .NET Framework and Windows rather than Java and Linux. In essence, Windows is the support structure for .NET Framework application development.

New Building Blocks

Windows XP Embedded had over 15,000 components with which to build a custom operating system. Around 1,500 were for operating system-specific capabilities, and the rest were device drivers. Some components were for only a single file like OLE32.dll. The advantage was that small image sizes could be created. The disadvantage was the difficulty of supporting all these individual build files in the field. In the end, due to component dependencies, many of these individual components got included in the image anyway. In order to address the needs of the full product life cycle, the WES 7 building blocks and tools are derived from the Windows 7 OEM Pre-installation Kit. WES 7 is still a modularized Windows 7 operating system, but the concept of components has been replaced by larger modules known as feature packages. WES 7 has a common core that includes the kernel, HAL and critical boot drivers needed to ensure that the system will always boot, eliminating any worries about BSOD Stop 0x7B issues. Feature packages store the rest of the operating system features such as IIS, Media Player, MSMQ, Internet Explorer, etc. These packages are signed .CAB files that are stored in a distribution share. Windows XP Embedded required a database engine to manage the individual components. A distribution share frees you from the component database and the requirement for a database engine, making backup and/or sharing of the distribu-



IBW 32 or 64 OR


Installation to the target via IBW

Once the image has been installed on the target, you can perform the final tweaks

Figure 1

Run Sysprep, and use ImageX, Norton Ghost or Rectiphyâ&#x20AC;&#x2122;s Active Image Protector to capture the OS image

Duplicate the image for manufacturing

The new WES 7 development process addresses the needs for development and manufacturing. The new tools shorten the development time.

tion share easier. Best of all, WES 7 comes with support for building both 32-bit and 64-bit Windows images, and a separate distribution share exists for each. Bigger packages built on top of a common core produce bigger operating system builds. One could build a 40 Mbyte image using Windows XP Embedded, but WES 7 is a little bigger. The minimum 32-bit kernel is about 570 Mbyte, with typical builds running between 900 Mbyte to 2 Gbyte depending on the feature set installed. The image size for a 64-bit target is approximately double that of an equivalent 32-bit image. Size might be a drawback for some, but the real treat comes in the form of the new development process and life-cycle support that starts with the new development tools.

Development Tools

WES 7 introduces a change in development direction from previous Windows Embedded versions. The Windows XP Embedded image had to be built on a development machine and finished on the target hardware. WES 7 just installs the OS on the target like a desktop OS. WES 7 provides two paths for installing the operating system. The first is to install directly from DVD. The WES 7 toolkit comes with 32-bit and 64-bit WES 7 installation Image Builder Wizard (IBW) DVDs. These DVDs boot to WinPE and run a wizard, which allows you to select the features and functions for the image. IBW gives you a fast method for installing operating systems, but it doesnâ&#x20AC;&#x2122;t give you the most control over what gets installed and feature configuration (Figure 1). The second path is the Image Configuration Editor (ICE), the IDE tool that

provides a more advanced build method similar to Target Designer for Windows XP Embedded (Figure 2). ICE is not an update of Target Designer used by Windows XP Embedded, but a re-coding of the Windows System Image Manager used in the Windows Application Installer Kit. ICE works in conjunction with the Image Builder Wizard (IBW). The output of ICE is not a WES 7 OS image but an answer file that is used by IBW to select and configure the desired feature packs and install them on the target hardware. The answer file includes information about the packages you select, but also any settings and custom applications / drivers. ICE lets you create a custom IBW disk based on the answer file, which includes the selected feature packages, custom settings, any custom software, and WinPE boot files. ICE also manages the distribution share, where the OS packages are stored. Either path makes for a straightforward development process, significantly shortening the time required to develop the image. Once the OS has been installed, you can then perform any changes and further setups to the image. Once completed, the image can be packaged up for manufacturing. Sysprep and ImageX (Figure 1) are a couple of tools that come with WES 7 to manage the manufacturing process. The Sysprep tool makes it possible to clone a WES 7 image for volume production deployment. WES 7 requires each system to have a unique Security ID (SID), which plays an important role in Windows networking and NTFS file permissions. Sysprep rolls back a WES 7 image creating a master image for production. Each production deployment of the master image generates a new SID on first boot.

tech in systems

Finally, ImageX.exe allows you to capture and deploy images for production or in the field. ImageX creates WIM files that store the OS image. The WIM files can be mounted locally to apply any updates or modified for country-specific localization.

Embedded Enabling Features

The Embedded Enabling Features (EEFs) offer unique capabilities that address the needs of an embedded system / appliance versus a desktop platform. The EEFs are what differentiate WES 7 from the Windows 7 desktop operating systems. WES 7 provides write filters that protect the WES 7 OS image from direct access and protect the life of flash memory systems. The Enhanced Write Filter (EWF) provides write filtering for a disk partition or an entire disk volume. When activated, EWF redirects writes to the protected partition or volume to a RAM overlay. The File Based Write Filter (FBWF) provides write filtering on a file-by-file basis. As with EWF, FBWF redirects writes to the protected files to a RAM overlay. The Registry filter preserves certain registry keys when a RAM overlay is used by EWF or FBWF to protect the registry. Time to boot is always a concern for embedded systems, and WES 7 provides a mechanism to shorten boot time: Hibernate Once, Resume Many (HORM). The system boots and saves the hyberfil.sys file, once. Then the system is subsequently booted and resumed from the saved hyberfil.sys file in subsequent boots, thus reducing the system boot time. WES 7 provides the Bootable Windows USB Stack feature pack that supports booting from USB flash disks or USB hard drives. The target system must support USB 2.0 boot and have the USB hard drive option in the BIOS. Embedded systems typically run 24/7 and often run unattended. Even with the best designed systems errors can occur, which can cause error message dialog boxes to appear. WES 7 provides the Message Box Default Reply EEF to handle these occurrences. Message boxes can be automatically intercepted and given a default response, i.e. ‘OK’ or ‘Cancel’, and the Message Box error events can be logged.

Figure 2 Image Configuration Editor is the graphical tool to develop custom images. ICE is a modified version of the Windows System Image Manager.

Like system error message boxes, applications can open dialog boxes that require responses. The Dialog Box Filter has been provided to block certain applications or known windows from running. A Dialog Filter Editor Tool has been provided that identifies all windows that are open on a test system, allows selection of the windows that are to be suppressed in the target embedded system, and creates a configuration file for the Dialog Box Filter. When the Dialog Box Filter and the configuration file are added to the WES 7 image, the windows and applications designated in the configuration file will be automatically blocked from running.


Product maintenance is an important part of a product’s complete life cycle. Field service has always been a challenge with Windows NT Embedded and Windows XP Embedded. With smaller components comprised of files and registries, Windows XP Embedded images were difficult to maintain. WES 7 uses packages instead of components, which makes the difference in servicing support. With WES 7, you can update a single package instead of individual files and registry keys. WES 7 provides a new servicing tool

for the development phase called Windows Embedded Developer Update (WEDU). The WEDU tool automatically checks the development environment to be sure that the latest product revisions are installed. WEDU downloads and installs updates as they become available to update the distribution shares. For the OS images themselves, there are new tools that are built in, such as the Deployment Image Servicing and Management (DISM.EXE) and Windows Update Standalone Installer (WUSA.EXE). The powerful command line tool, DISM, installs, uninstalls, configures and updates features and packages for a WES 7 image. DISM.exe builds into every WES 7 image. DISM can be used to update images in the factory for manufacturing servicing or in the field for field support servicing. The images can either be online or offline providing multiple scenarios to update the image. WUSA is a simpler command line utility. Both tools can be scripted to apply updates to images in the field. How the update gets to the target is still up to you.

Real-Time Support

WES 7 is not a real-time (“deterministic”) operating system like other solutions in the embedded market. Windows RTC MAGAZINE JANUARY 2011


Tech In Systems

CE (Windows Embedded Compact) is the embedded Windows offering designed to be a small real-time operating system. This doesn’t mean WES 7 is limited in this area. There are some unique add-ons that help add real-time support to WES 7. If you have no investment in a realtime kernel now, then a product like TenAsys’ INtime should be considered.

INtime is an add-on kernel to Windows. The INtime kernel runs as a process in Windows memory. INtime applications run at a higher priority level, while Windows itself is held at a lower priority. INtime comes with an SDK that integrates into Visual Studio. The result is a dual kernel solution that addresses both realtime and non-real-time applications. In a

multicore system, you can assign each operating system to use a different core. The interesting result of the combined architectures is that you can create Windows applications that call real-time threads. The Windows graphical applications and real-time threads can pass information back and forth between each other. If you already have a significant investment in a real-time kernel, then a product like TenAsys’ embedded Virtual Machine (eVM) should be considered. TenAsys’ eVM for Windows runs on multithreaded Intel processors that have VT-x support and VT-d support. eVM allows any real-time OS like iRMX, QNX, VxWorks, etc. to run alongside Windows on the same hardware platform. You can communicate between Windows and the OS running in the virtual machine via shared memory, virtual COM ports, or virtual Ethernet ports. You can keep your investment in your current real-time operating system and take advantage of Windows as a front-end user interface. WES 7 is based on the new popular desktop operating system, Windows 7, but WES 7 goes beyond the desktop so you can integrate the rich desktop features and functionality into unique embedded systems. The development tools provided with WES 7 are new from the ground up. Because of this, WES 7 offers quicker development time and better servicing options than prior embedded Windows versions. Best of all, you can take advantage of the off-the-shelf software and hardware available for the PC. .NET Framework can be used to create feature-rich applications and add-ins can be used to support real-time requirements. With all of these advantages, WES 7 should be given serious consideration for your next embedded project. SJJ Embedded Micro Solutions Yorba Linda, CA. (714) 970-7523. []. []. TenAsys Beaverton, OR. (503) 748-4720. [].


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1/11/11 11:43:51 AM

technology in


Embedded Windows: The Next Generation

CE Goes Multicore: Microsoft Windows Embedded Compact 7 The latest version of Microsoft’s Windows Embedded CE operating system provides significant improvements in the area of networking, user interface and the base kernel.

by Douglas Boling, Boling Consulting




The improvements to Compact 7 start with a rewritten kernel. Compact 7 is the first of the Windows CE line to support

Button 2

Button 3

Windows Embedded Standard 7. Componentization, the ability to pick and choose various OS components to include in a build, can dramatically shrink the image size. A small “update image” of Compact 7 that contains the kernel, file system and communication stack is easily under 1 Mbyte on an x86 system. Fleshing out the OS with a GUI, shell and various basic subsystems increases that to perhaps 4 Mbyte. Of course, adding everything provided by Microsoft can balloon an image to over 20 Mbyte if that’s what is needed. As with all previous versions, Compact 7 is accompanied by the Platform Builder 7 tool set. Platform Builder is an integrated development environment that allows componentization of the OS, the compilation of drivers and applications, and the downloading and debugging of the OS image. Improvements in Platform Builder 7 are centered on a new suite of tools used with Silverlight for Embedded.

Button 1


icrosoft sells two operating systems tailored to the embedded community, confusingly named Windows Embedded Standard 7 and Windows Embedded Compact 7. Windows Embedded Standard 7 (WES), or just Standard 7, is a repackaged Windows 7 operating system described elsewhere in this magazine by my colleague Sean Liming. Windows Embedded Compact 7, or Compact 7, is a purpose-built operating system designed for mobile and embedded systems. Yes, Microsoft guidelines specify the addition of “7” to the end of the name of each operating system. Apparently, “7” is the new “.NET”. Compact 7 differs from Standard 7 in its CPU independence, as it supports ARM and MIPS, as well as x86 architectures. In addition, hardware requirements differ. Where WES 7 requires a “WinTel” compatible PC motherboard, Compact 7 simply needs a supported CPU type, some RAM, a place to store the OS, a real time-clock and a periodic interrupt for the scheduler. All other hardware decisions are left to the OEM. Of course, Windows Embedded Compact 7 is significantly smaller than

Button 4

Figure 1 A simple user interface of four buttons created with Expression Blend.

symmetric multiprocessing. The kernel has been written to support up to 250 cores although it runs best with eight cores or fewer. Still, the ability to run across multiple cores dramatically increases the responsiveness of the system, especially under conditions where a thread is under load. To ensure that older applications run correctly under Compact 7, applications

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compiled to Windows CE 6 and before will have all their threads run on the same core. This prevents any untested thread timing problems from being exposed by the multicore kernel. Applications compiled to Compact 7 will have their threads distributed across all the available cores. New API calls have been added to manage the multiple cores. Applications can set a thread’s affinity to a specific core, or all threads to a specific core. In addition, developers can power down cores (with the exception of the primary core) of the CPU to save power. All interrupts are handled by the primary core of the CPU. Windows Embedded Compact 7 also has improvements in memory management. Previous versions of Windows CE supported up to 512 Megabytes of physical RAM. Additional RAM available on the system could be used as an I/O buffer, but was not managed by the kernel. Compact 7 increases the maximum supported physical RAM to 3 Gigabytes. Individual processes are still limited to the virtual space available within that process, but the increase removes a significant point of pain for complex systems where large amounts of RAM are required for image processing or data caching. This RAM is a welcome improvement that finally mirrors the improvements to the process virtual space that were made in Embedded CE 6. Compact 7 also has a redesigned heap manager for applications. The new heap manager design reduces fragmentation by dividing the heap into various arenas designated for commonly sized allocations. Embedded applications by their nature tend to run for a long time, making them especially susceptible to fragmentationbased memory loss. This bucket-based approach was used for kernel heaps in CE 6 and now is used by the application heaps in Compact 7. On the security front, Compact 7 adds two features that have been brought down from the Windows desktop operating system. The first of these is Address Space Randomization or ASR. ASR is a feature of the module loader in the kernel that randomizes the load address of the Dynamic Link Libraries (DLL) as they are loaded by various processes. The goal of ASR is to make it more difficult

<UserControl xmlns=”” xmlns:x=”” xmlns:d=”” xmlns:mc=”” x:Class=”RTC_Demo.MainPage” Width=”640” Height=”480” mc:Ignorable=”d”> <Grid x:Name=”LayoutRoot”> <Grid.Background> <LinearGradientBrush EndPoint=”0.5,1” StartPoint=”0.5,0”> <GradientStop Color=”#FF1BD652” Offset=”0.965”/> <GradientStop Color=”#FFEED906”/> </LinearGradientBrush> </Grid.Background> <Button x:Name=”Btn1” Margin=”10,215,0,175” FontSize=”24” RenderTransformOrigin=”0.5,0.5” Content=”Button 1” HorizontalAlignment=”Left” Width=”300” Click=”Btn1_Click”> <Button.RenderTransform> <TransformGroup> <SkewTransform AngleX=”-45”/> <RotateTransform Angle=”-90”/> </TransformGroup> </Button.RenderTransform> </Button> <Button x:Name=”Btn2” Margin=”160,65,180,0” FontSize=”24” RenderTransformOrigin=”0.5,0.5” Content=”Button 2” Height=”90” VerticalAlignment=”Top” Width=”300” Click=”Btn2_Click”> <Button.RenderTransform> <TransformGroup> <SkewTransform AngleX=”45”/> </TransformGroup> </Button.RenderTransform> </Button> <Button x:Name=”Btn3” Margin=”310,215,30,175” FontSize=”24” RenderTransformOrigin=”0.5,0.5” Content=”Button 3” Click=”Btn3_Click”> <Button.RenderTransform> <TransformGroup> <SkewTransform AngleX=”-45”/> <RotateTransform Angle=”-90”/> </TransformGroup> </Button.RenderTransform> </Button> <Button x:Name=”Btn4” Margin=”160,0,180,25” FontSize=”24” RenderTransformOrigin=”0.5,0.5” Content=”Button 4” Height=”90” VerticalAlignment=”Bottom” Width=”300” Click=”Btn4_Click”> <Button.RenderTransform> <TransformGroup> <SkewTransform AngleX=”45”/> </TransformGroup> </Button.RenderTransform> </Button> </Grid> </UserControl>


for malicious software to guess the location of code within the address space of a process. ASR is especially useful in embedded systems that—unlike desktop systems—typically boot the same software in the same sequence. In my experience with earlier versions of Windows

Embedded CE, the load address of DLLs was very predictable under most conditions. ASR randomizes the load address within the 512 Mbyte range allocated to user mode DLLs. Sure, it would be possible to search for various code patterns to locate a specific DLL, but ASR does make RTC MAGAZINE JANUARY 2011


Tech In Systems

it a bit more difficult for the hacker. Another security feature of Embedded Compact is Data Execution Prevention (DEP), which is similar to execution prevention features on other operating systems. It flags data pages so that code cannot be executed from those pages. DEP is an optional feature that can be enabled with a simple build switch in Platform Builder. Unfortunately, DEP is only supported on Embedded Compact systems running on ARM 7 architectures.

Silverlight for Embedded

If I were to point to one feature of Windows Embedded Compact 7 that separates it from other full-featured embedded operating systems it would be Silverlight for Windows Embedded, or SWE. Silverlight is Microsoft’s cross-platform, Web development environment available on Windows desktop, Windows server and OS X operating systems among others. Silverlight for Embedded takes the power of the Silverlight presentation engine and adapts it to the embedded market. SWE has the same Extensible Application Markup Language (XAML) user interface description language, but the “code behind it” is implemented in C++ running natively on the device. This combination of a rich design language along with native code that can directly access the hardware and is not subject to .NET “garbage collection” pauses, is ideal for creating the rich user interfaces that many modern embedded devices demand. The key to SWE is the Silverlight rendering engine. This graphical front end essentially replaces the classing Windows GDI/User user interface API with a new class-based API that provides control and event handling back to the C++ business logic. The class library mimics the C# class library of standard Silverlight, easing the transition for Silverlight developers and providing a lifeline for embedded developers who can utilize the significant amount of literature discussing Silverlight development. One of the features of Silverlight and SWE is the ability to bridge the gap between user interface designers and developers who write the business logic code in the core of the application. The tool used by user interface designers for Silverlight



//===================================================================== // btn1_Click // // Description: Event handler implementation // // Parameters: pSender - The dependency object that raised the // click event. // pArgs - Event specific arguments. //===================================================================== HRESULT MainPage::btn1_Click (IXRDependencyObject* pSender, XRMouseButtonEventArgs* pArgs) { HRESULT hr = E_NOTIMPL; if ((NULL == pSender) || (NULL == pArgs)) { hr = E_INVALIDARG; } // Find the storyboard IXRStoryboard* pStoryboard = NULL; m_pLayoutRoot->FindName (TEXT(“RotateButtons”, (IXRDependencyObject**)&pStoryboard); // Play the storyboard if (pStoryboard != NULL) { pStoryboard->Stop(); pStoryboard->Begin(); } return hr; }


is Microsoft’s Expression Blend. Blend is a WISIWIG tool that enables designers to create elaborate user interface designs. Blend works with standard Microsoft solution files so projects created with Blend work with Visual Studio and vice versa. While it can be used as the sole tool for Silverlight development, Blend is typically used in conjunction with Visual Studio. For SWE, Blend is used with Platform Builder where the Blend-generated XAML is integrated with the C++ backend code compiled by Platform Builder. In Figure 1, a trivial user interface of four buttons was created using Expression Blend. The buttons are skewed and some are rotated and flipped. Each of the buttons is fully functional and could be filled with images instead of, or along with, text. The XAML generated by Blend for the interface above is shown in Code Example 1. Each of the buttons is described within a Grid control. The transforms that manipulate each of the buttons can be seen within the button declarations. The power of XAML is that the Grid and Buttons declared in the XAML describe classes that are also accessible programmatically through properties of the classes. For example, the first button

class named “Btn1” causes the Silverlight runtime to create an instance of a button class named Btn1. The application can access the properties such as FontSize, Width and many others not initialized in the XAML declaration while the application is running. Another powerful feature of SWE is the concept of Storyboards. Storyboards are predefined animations that can be run during application execution. Instead of having the C++ code provide the heavy lifting of manipulating the screen elements, the Silverlight rendering engine can directly play a storyboard that describes the animation. Storyboards are typically created in Blend using a timeline style animation creator. Code Example 2 is the code for the event handler that is fired for clicking on Button 1. In the handler, a storyboard is played with a handful of calls. The click handler is auto generated by the tool that imports the Blend project into Platform Builder. The only code added was that needed to find and start the storyboard named “RotateButtons.” Silverlight for Embedded is packaged as another Embedded Compact component that can be added during the operating sys-

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tem generation process in Platform Builder. Adding the SWE component doesn’t preclude applications using the standard Win32 graphics and windowing APIs. Traditional Windows CE applications can run side by side with SWE applications. In addition, SWE applications can host conventionally built GDI-based controls in the XAML user interface. This is convenient for two reasons. First, systems that need unique custom controls that aren’t supported in SWE can be built using standard Win32 APIs and incorporated into the SWE application. Second, supporting custom controls that were built in legacy systems eases the upgrade path for OEMs wanting to leverage the user interface “bling” of Silverlight for Embedded.

Other Improvements

Complementing the complex user interfaces created by Silverlight for Embedded, Compact 7 supports a Gesture API. This API supports single and multi-touch gestures including touch, drag, pinch and pan. The OS-provided controls can be set to recognize gestures if desired. In addition, a physics engine is provided to help with those springy, bouncy actions that users now expect. Compact 7 has improved various parts of the communication infrastructure as well. The operating system contains a new communications infrastructure including a new WinSock stack ported from the desktop. This new stack has improved security and extensibility compared to the communication stacks in previous versions. A new version of Internet Explorer dubbed “Internet Explorer Embedded” has also been added. This version of IE is based on the desktop IE 7 code base with selected performance improvements from IE 8 back ported into the rendering engine. IE for Embedded also includes new pan/zoom support that was added for Windows Phone’s version of IE.

Platform Builder

The development tools for Windows Embedded Compact 7 have evolved as well with the latest edition. Platform Builder 7 now is an add-in to Visual Studio 2008 instead of VS 05 that was used for CE 6. While some may wonder why PB doesn’t use Visual Studio 2010 in-

stead, the add-in interface for the newer Visual Studio was different enough that the effort to go to that IDE was deemed not worth any gains. While essentially identical to the feature set of Platform Builder 6, the new version does add one or two items that are worth noting. First is the addition of “Checked” builds. Platform Builder has always supported two build types, “Debug” and “Retail.” Debug builds turn off compiler optimizations, enable numerous asserts, add arena checking for heap allocations and various other debug related features. Retail builds disable all those debug checks and enable compiler optimizations. As one might expect, Debug builds are significantly larger, up to 40% larger than Retail builds. This size difference frequently caused problems for systems with limited RAM and storage. Checked builds enable compiler optimizations while also enabling the various debug checks such as arena checking and asserts. Checked builds are therefore smaller than debug builds while retaining the useful debug checking. For those not familiar with Windows Compact, the debugger can attach to any of the (now) three build types. Platform Builder 7 also includes improved compilers that take advantage of the newer ARM architectures. Code produced by the new compilers is both smaller and faster than the code produced by the compilers in Platform Builder 6. The testing suite, now dubbed the “Compact Test Kit,” has been upgraded for Compact 7. This new suite has an significantly upgraded PC-based front end that can sequence tests and collect results while testing a remotely attached Compact 7 device. The new features of Windows Embedded Compact 7 will be welcomed by experienced users of Windows Embedded CE. In addition, the upgraded kernel and the new Silverlight for Embedded feature set may just attract more than a few new developers to the OS. Check out Windows Embedded Compact 7. Despite the confusing name, it’s a powerful embedded OS. Boling Consulting Saratoga. CA. [].

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11/3/10 10:48:30 AM

technology in


Embedded Windows: The Next Generation

Making Embedded Systems More Secure with Windows Embedded Standard 7 Security mechanisms built into the new Windows 7 can also be used to secure remote and even unattended embedded systems and devices.

by John Lisherness, Avnet Technology Solutions


icrosoft’s Windows Embedded Business supplies OEMs with platforms and technologies for embedded systems. Released in the spring of 2010, Windows Embedded Standard 7 delivers the power, familiarity and reliability of the Windows 7 operating system in a highly customizable and componentized form. Windows Embedded Standard 7 is available in three versions: “C”, “E” and “P”. The “C” version is targeted at the consumer entertainment set-top box market. The “E” version has features most users of Windows are familiar with such as Internet Explorer, Windows Media Player and Remote Desktop Protocol. Windows Embedded Standard 7’s “P” version adds many features, including Multi-touch support, BranchCache, Windows Media Center, AppLocker, BitLocker and DirectAccess. The focus here is on BitLocker and DirectAccess and how they can be used to enhance the security of embedded systems.

Figure 1


Security components that can be used when implementing BitLocker scenarios.

If the used copiers in the accompanying news story had an operating system with BitLocker enabled, the hard drives



tech in systems

removed from them would have been unreadable. BitLocker was introduced with Windows Vista and is included in the Ultimate and Enterprise versions of Windows 7. Windows Embedded Standard 7 has BitLocker available as well. With BitLocker turned on, all the data stored on the computer’s protected volumes are automatically encrypted. If a hard drive is removed from the system, its protected contents are unreadable. There are several ways a system can be set up so that the entire drive or a volume on a drive can be locked and then unlocked. For the entire drive to be locked, the system needs to be equipped with a Trusted Platform Module (TPM 1.2) chip. Since 2006, TPMs have been commonly designed into many motherboards and even laptops. Since the TPM is part of the hardware, its presence is transparent to embedded application software and the end user. When the system starts, BitLocker automatically knows to retrieve the key stored in the TPM and unlocks the protected drive. If there isn’t a TPM, it is necessary to have an unprotected boot volume that can be given a passcode by the system’s user to unlock the protected volume. The BitLocker Wizard is a utility that creates a non-encrypted system partition on the hard drive that has the files necessary to start the computer. This partition does not show up in the computer folder and has no letter assignment. The rest of the drive, which can include the operating system, applications and data, is encrypted and cannot be read if removed from the system. One simple way to automatically unlock a protected volume is to set it up to unlock when a specific user logs onto the system. In this way, the user’s log-on acts as the key. Another way a user can unlock a volume is to assign a password or use a smartcard. Systems with multiple drives can have some drives encrypted and others not encrypted and files moved back and forth between drives are stored as encrypted or not, according to how the drive is set up. Some embedded scenarios come

to mind that could use BitLocker. Imagine a digital video surveillance recorder. The video data could be stored on a protected drive (Figure 1). For USB flash drives and external attached drives, there is “BitLocker to Go.” Systems using BitLocker to Go can make it so that USB thumb drives and other removable storage devices (Figure 2) have the data on them encrypted and readable on another machine only with the use of a passphrase. If the embedded system is connected to and is part of an enterprise network, IT administrators can set a policy controlling the required passphrase length and complexity. IT administrators can also require users to apply BitLocker protection to removable drives before being able to write to them. It isn’t hard to imagine the types of systems that could take advantage of BitLocker. Medical devices can use BitLocker to allow the transport of medical records via USB connected storage without fear of the contents being accessed by someone inadvertently getting physical access to the storage device. Another example would be to use BitLocker to secure security video recordings or recorded legal proceedings.


For years, companies have relied on Virtual Private Networks (VPNs ) to ensure secure connections between remote laptop users connecting to sensitive data on the enterprise. Remote laptop users requiring VPNs are familiar with having to launch the VPN software and enter a code produced by a VPN key in order to gain a secure connection with the company’s intranet. VPN users are also familiar with lost connections, slow or restricted Internet access, lost keys and firewall problems. Embedded systems need secure, reliable connections, but can’t rely on an attendant with a VPN key. Quite often, the embedded system can have no attendant at all or even be headless, without keyboard, video or mouse. The solution to this situation is DirectAccess.

Figure 2 Even small, removable devices can be secured with BitLocker.

DirectAccess can replace VPNs and supply a secure connection between client systems and the company server without many of the downsides associated with VPNs. There is no electronic key to read, or the need for someone to initiate the VPN session. The secure connection is automatically created by virtue of the server and client both being on the Internet and able to connect. When an embedded system client with DirectAccess connects to the Internet, it uses IPv6-over-IPsec to connect to the corporate DirectAccess server. Unlike using a VPN, DirectAccess is always on. One interesting aspect of DirectAccess is its ability to actually reduce traffic between the client and the server. With a VPN, all of the client’s Internet requests go through the server. This includes streaming media and non-sensitive Internet browsing. With DirectAccess, IT administrators can enable remote client devices to directly access websites outside of the intranet without having to access the Web via the server. This can dramatically reduce the amount of data flowing through the company’s servers (Figure 3). Imagine a remote kiosk in a retail setting being able to handle financial transactions and serve intranet content that’s also able to provide streaming media and Web browsing without burdening the dedicated, securely connected servers. Conversely, RTC MAGAZINE JANUARY 2011


Tech In Systems

Sex, Crime and Embedded Systems? A recent news story documented how most office copiers have a hard drive that stores copies of the documents being printed and faxed. The news crew randomly purchased three used machines and discovered that one had been used by a sex crimes division of a police department and another had been used by a medical insurer. They were able to retrieve thousands of highly sensitive documents including medical records, criminal records and even copies of pay stubs.

imagine streaming real-time video being securely sent to a server. Another huge upside to DirectAccess is that IT departments can easily update and service remotely connected embedded systems. With the secure connection being “always on,” setting Group Policy and distributing software updates can be done at any time, with the embedded client system unattended.

Windows Embedded

OEMs eager to adopt Windows Embedded Standard 7 “P” to utilize DirectAccess on their clients need to be aware that it will require one or more DirectAccess servers running Windows Server 2008 R2 with two network adapters: one connected

directly to the Internet, and a second connected to the intranet. Additionally, the cost of the Windows Embedded Standard 7 “P” version is approximately 50 percent more than the “E” version. The cost of Windows Embedded is still far less than the non-embedded “OEM System Builder” version of the operating systems. There are other advantages of Windows Embedded, as well. All Windows Embedded products are available for fifteen years from their release date. This means that Windows Embedded Standard 7 is guaranteed available until 2025. For those OEMs who are unable to migrate from Windows XP Embedded to Windows Embedded Standard 7, Windows Embedded Standard 2009 is available until 2024.

Intranet Internet

DirectAccess client

DirectAccess server

Corporate resources

Internal traffic Internet traffic Internet servers

Figure 3 With Direct Access, users can access the wider Internet normally while only using corporate resources for the access that needs to be secure.



Beyond the cost and extended availability advantages, there are features unique to Windows Embedded Standard 2009 and Windows Embedded Standard 7. These operating systems do not require that an activation key be entered for each system, both can be configured to consistently boot quickly using Hibernate Once Resume Many (HORM), and valuable data can be protected from accidental corruption using Enhanced Write Filtering (EWF) and File Based Write Filter (FBWF). EWF and FBWF protect data on the storage media from corruption or tampering by using a RAM overlay to be written to instead of the hard drive. With EWF in place, the system can experience an abrupt loss of power and, because the system is writing to RAM instead of the volume that contains the OS, the OS is protected from a hard-drive power-down corruption. Systems using EWF can also use HORM. HORM allows the system to boot at a fraction of the normal boot time using the EWF protected volume and a hyberfile. The system not only boots faster, but the boot time never changes. More information on Windows Embedded can be found at the Microsoft Embedded website: com/embedded and the Windows Embedded News Center for updates: http:// embedded/. More technical information can be found on the Embedded section of MSDN: windowsembedded. Avnet Technology Solutions Tempe, AZ. (800) 409-1483. [].

11 Conference and Exhibition Alpexpo, Grenoble, France March 14 - 18, 2011 The 14th DATE conference and exhibition brings together designers and design automation users, researchers and vendors,as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on both ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software. General Chair: Bashir Al-Hashimi, University of Southampton, UK • Program Chair: Enrico Macii, Politecnico di Torino, Italy





Entrance to the Exhibition is FREE Open Times:

Biologically-inspired massively-parallel architectures – computing beyond a million processors

Tuesday, 15th March (1830-1930 Evening Reception)

1000 – 1930

S Furber, ICL Professor of Computer Engineering, School of Computer Science, Manchester U, UK

Wednesday, 16th March

1000 – 1800

Thursday, 17th March

1000 – 1700

How technology R&D leadership brings a competitive advantage in the fields of multimedia convergence and power applications P Magarshack, Central R and D Vice-President, STMicroelectronics, FR


Special Focus Days

WIRELESS INNOVATIONS FOR SMARTPHONES KEYNOTE – Wednesday, March 16th, 14.00 Hannu Kauppinen, Director, Head of Radio Systems Laboratory, Nokia Research Center, FI SMART ENERGY AT ST KEYNOTE – Thursday, March 17th, 13.30 Carmelo Papa, Executive VP Industrial and Multisegment, STMicroelectronics, IT

Event Secretariat European Conferences 3 Coates Place, Edinburgh, EH3 7AA, UK Tel: +44-131-225-2892 Fax: +44-131-225-2925 Email: or

technology deployed Motor and Motion Control

Implementing Precision High-Speed Linear Motion Control The selection of the proper components for the application and then carefully tuning them with software tools is the key to fast and precise motion control. The principles of this linear motion example can be applied to a host of unique applications.

by Todd Shearer, Galil Motion Control


eveloping high-performance motion control applications requires that a design engineer not only be able to select the proper components, but also be able to tune these components for the required performance. Many of these high-performance motion applications fall into one of two categories: highspeed applications with less stringent accuracy requirements, or high-accuracy applications that don’t require high-speed motion. The most difficult applications to design and implement are those that require both. Examples of these high-speed, high-accuracy applications are found in most industries: test and measurement of electronic components, semiconductor die bonding, fluid dispense for PCB manufacturing, and sample analysis in bio-tech applications. Some of these applications require position accuracies down to the nanometer level, with motion times on the order of milliseconds. In order to achieve this level of performance, a design engineer will need to make sure that all the motion components in the system are up to the task. The design engineer is also responsible for tuning all the components in the servo loop so that the performance can be achieved. A recent application for a semiconductor component test-



ing machine shown in Figure 1 provides a good example of how to design high-performance motion control into a system. The application consisted of an existing test fixture, which was being updated with newer motion components for higher throughput. The sensor is automatically loaded into a probe, which is attached to a linear motor. A custom shaped disc rotates in front of the sensor to create a magnetic field. The sensor is moved through a series of short, accurate moves to positions within this field, and the sensor output is read for a full sensitivity “map.” Each sensor must be read at up to 50 distinct positions, so short move and settle times are critical.

Selecting Components to Meet the Requirements

In this example application, the step moves of the linear motor range from a minimum of 0.001” up to 0.511”. The goal is for the motor to move and settle within a position window in a time of 1-2 ms per 0.001”. For example, a 0.001” move should take 1-2 ms, while a 0.01” move should take no more than 10-20 ms. Most importantly, the motor must not overshoot the target position by more than 0.0005” as this would invalidate the test measurement. In order to benchmark the system performance, the customer required measured move and settle times for distances of 0.001”, 0.002”, 0.004”, 0.008”, 0.016”, 0.032”, 0.064” and 0.128”. Motion was considered complete when the motor was within the position window of +/-0.0005”. Y Axis Probe Linear Motor (X Axis)



Figure 1 Probe moving sensor towards a rotating disc. The X axis moves sensor linearly, while the Y axis controls the rotational velocity of the disc.

Technology deployed

Once the motion specifications of the system have been determined, the next step is to select the components that allow this motion to occur. The critical components that will affect the motion of the system are the servo motor and mechanics, encoder or other position feedback device, power amplifier and motion controller. Each must be chosen based on their ability to individually provide the performance defined in the motion specification. The first decision for component selection is to determine what type of motor technology should be used. There is a wide range of technologies available to the design engineer, ranging from DC servo motors with ball screw translation to brushless linear motors to piezo-ceramic actuators. Some motor technologies can be ruled out immediately based on limitations. This application isnâ&#x20AC;&#x2122;t appropriate for stepper motors due to the high accelerations, nor would hydraulics or pneumatics be suitable. This leaves three main technologies: rotary servo motors driving a ball screw, linear servo motors, and piezo-ceramic actuators. The decision on which technology to use depends on the details of the application. A piezo-ceramic actuator could be very good for this type of application, but has limitations on payload and travel distance. A rotary servo motor with a ball screw linear translation could be a good choice, but there are sacrifices that would be made due to backlash in the transmission. Backlash has the potential to add positional errors or motion instability into a system. For this application, a brushless linear motor is the best choice. This type of motor is able to provide the full travel length required, sufficient torque for the high accelerations, and being a linear motor, the load is directly coupled to the motor to remove any backlash concerns. Once this motor type was determined, a manufacturer was contacted for help with motor sizing. The next step is to determine the proper feedback device. As with motors, there are many encoder technologies available to the design engineer such as rotary quadrature encoders, linear encoders, absolute binary encoders and absolute serial encoders to name a few. Given that a linear motor was selected for the motor technology, some sort of linear encoder would be suitable for positional feedback. When selecting a linear encoder, a design engineer could select a standard TTL quadrature output encoder, or could choose a model that provides a sine and cosine output. The sine/cosine encoder outputs a sine and a cosine waveform, which are then interpolated by the motion controller for accurate positioning. The benefit of this technology is that it gives flexibility of design, as most motion controllers allow a software selectable level of interpolation. It also reduces cost, as the encoder does not need to have an expensive integrated interpolation circuit. As for raw numbers, the typical period of a sine/cosine encoder is 20 microns, which when interpolated up to 4096x will give a position accuracy down to 4.88 nanometers. This encoder technology was suitable for the application, and was thus specified for the final machine. The power amplifier for the most part is a decision that comes down to proper sizing, although there are also various technologies available. Power amplifier technology includes digi-

Figure 2 Graphical display of a 0.010â&#x20AC;? move. This move took approximately 10ms to move and settle. Parameter



Servo bandwidth


62.5usec gives a 16kHz servo bandwidth

Encoder interpolation


2 6 interpolation (64x) of the sin/ cos encoder, yielding 0.3125um on a 20um pitch scale

Proportional gain


Integral gain


Derivative gain


Integrator limit


Feedforward acceleration


Feedforward deceleration


Custom command added for this application

Pole filter


Low pass filter used to remove high frequency resonances



Motor speed of 250,000 counts/ sec



Acceleration of 650,000,000 counts/sec 2



Deceleration of 15,000,000 counts/sec 2

Limits integral term to 1V and freezes while profiling

TABLE 1 Commands and settings applied to the linear motion control example.

tal sinusoidal servo amplifiers, analog sinusoidal servo amplifiers, analog trapezoidal amplifiers and linear servo amplifiers. Analog servo amplifiers give good performance, but donâ&#x20AC;&#x2122;t have RTC MAGAZINE JANUARY 2011


technology deployed

Move distance









Old design (ms)









New design (ms)









TABLE 2 Improved motion times of new design over previous design of linear motion system.

easy software programming interfaces for tuning of high performance applications. Linear servo amplifiers give very smooth motion performance, but at high current and voltage levels may be cost and size prohibitive. If the goal is smooth operation, high power output for high accelerations and high level software tools for tuning a digital servo amplifier with sinusoidal output is the proper choice. The sinusoidal output ensures smooth motion, and the digital interface allows for easy tuning of the amplifier. This tuning is a critical aspect of the power amplifier, as it allows the design engineer to increase the performance of the drive to meet the application specifications. The final step is to select the motion controller. In some respects, this is the most critical choice as the motion controller is the heart of the system. The motion controller is responsible for the positioning and control of the motors, coordination of motion, integration of I/O and even the user interface for the operator to control the machine. With all of these requirements, a high-performance motion controller is a necessity. There are many factors that need to be considered when selecting the motion controller. Will the controller reside within a PC or external to a PC? What type of communication to the motion controller is required; Ethernet, serial or PCI bus? How many I/O points should the controller support, and will there be both analog and digital I/O? As for programming, should the unit program in C++ or Visual BASIC? In GCode or Ladder logic? Or some proprietary language? Every manufacturer’s motion controller has differences from their competitors’, so it is the role of the design engineer to sort through all the specifications and determine which is the best fit. The above factors are some that should be weighed when making a decision. However, given that the goal is to select a motion controller to control a high-performance machine, some specifications are more important than others. The controller should support high servo bandwidth. A servo loop closure time of 125 microseconds or less would be ideal for the example application. The ability to receive and interpolate the sine/cosine feedback from the encoder is also a requirement. Finally, an advanced filter for controlling the motor is important. A proportionalintegral-derivative (PID) filter with additional features such as feedforward terms and low pass filter is a good selection for this application.

How to Tune for High Speed, High Accuracy

With all of the components selected, the next step is to connect the system and begin tuning the motion for required performance. This step is every bit as important as component selec-



Figure 3 Graphical display of a 0.100” move. This move took approximately 44 ms to move and settle.

tion, but should be made easier by advanced software packages from both the motion controller and power amplifier. At this step, the bulk of the work is done with the motion controller, as it is responsible for positioning of the system. In this application, the Galil DMC-4040 controller was selected based on its high servo bandwidth (up to 32 kHz) along with its ability to take feedback from a sine/cosine encoder and interpolate at a selected resolution. The controller also gave the customer the required number of I/O points, along with the stand-alone Ethernet capability they were looking for in the application. Setup and tuning of the system with regards to the motion controller had two major portions: sine/cosine feedback connection, and tuning of the servo filter. First, the sine/cosine encoder is connected to the internal motion controller interpolation board. This sine/cosine interpolation allows the user to select an interpolation resolution from 32-4096x. An interpolation of 64x was set in the software, giving a positional accuracy of 0.3125 micron, which was well within the required accuracy of 0.0005” (12.5 micron). With the feedback signals connected at the motion controller, the software command TP (Tell Position) was used to read and verify proper encoder positions. Next, the motion controller’s PID filter is to be tuned for optimum performance. Servo tuning is a process of moving the motor back and forth in a step function and adjusting the filter gains

MicroTCA Showcase

Technology deployed

for optimum performance. Graphical tools, in this case Galil’s software package “GalilTools,” were used to visually display the system response in an oscilloscope format. The software graphed responses for actual encoder position (TP), commanded encoder position (RP), position error (TE) and motor torque (TT). As the motor is moved through its commanded step function and the filter gains adjusted, the goal is to minimize the position error to meet the customer specifications. From testing, it was found that a servo update rate of 16 kHz was a sufficiently fast time base for this system, so the TM value (servo update) was set to 62.5 usec. This is the rate at which the servo system reads its positions and calculates the appropriate response. When tuning a servo system, the basic PID filter terms are tuned first, giving the basic performance to the system. They are raised to values that minimize error, yet don’t cause excessive overshoot or instability. The higher level servo parameters are added last. For this application, feedforward terms were critical. These terms (acceleration and deceleration feedforward) minimize position error at the acceleration and deceleration phases of the motion, without causing instability. An integrator “freeze” was added to prevent integrator windup during motion. And finally, in order to remove higher frequency mechanical resonances in the system, a low pass “pole” filter was added. Table 1 shows the filter gains and motion parameters that were finally settled upon for this system. With these numbers, the motion control system was able to meet or exceed the customer requirements at all move distances. As shown in the customer supplied results in Table 2, the system greatly decreased the motion times for the full range of move distances. Figures 2 and 3 show some screen captures showing the motion profile for various move lengths. Galil Motion Control Rocklin, CA. (916) 626-0101. [].

Featuring the latest in MicroTCA technologies S4-AMC: Altera Stratix® IV GX AdvancedMC with VITA 57 Site VITA 57 FMC site for I/O and processing expansion High density Altera Stratix IV GX supported by BittWare’s ATLANTiS™ FrameWork BittWare’s FINe™ III Host/Control Bridge provides control plane processing and interface Fully connected to AMC (16 ports SerDes, 4 ports LVDS) I/O includes 10/100/1000 Ethernet, SerDes, LVDS, RS-232, and JTAG

BittWare Phone: (603) 226-0404 Fax: (603) 226-6667

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Embedded Modem Modules, the Half-Inch Modems Serial TTL interface -40C to +85C operating temperature Compact size: 1” x 1” x 0.2” up to 56K bps data rate 14.4K bps fax, voice AT command DTMF, ring and Caller ID detection Transferable FCC68, CS03, CTR21 telecom certifications Global safety: c/UL, IEC60950-1, IEC60601-1 (Medical) approved CE marking

Radicom Research, Inc. Phone: (408) 383-9006 Fax: (408) 383-9007

E-mail: Web:

Best Scope Selection Unique oscilloscope selection: high-end 16-bit 12GHz TDR units to standalone, economical LCD benchscopes; thumbdrive-sized scopes, scope-in-aprobe, and 7-instruments-in-1 toolbox essentials; high-end mixed signal scopes with simultaneous logic analysis. Also: signal generators, spectrum analyzers, DMMs, dataloggers, counters, SPI/I2C, panel PCs, etc.

Saelig Company, Inc. Phone: (585) 385-1750 Fax: (585) 385-1768

E-mail: Web:

technology deployed Motor and Motion Control

A Taxonomy of Motion Control Encoder Technologies

encoders include resolution specified as pulses per revolution (PPR) or counts per revolution (CPR) and output type. However, several other criteria must be considered in the final decision including operating environment, materials, noise immunity, inertia, reliability, life expectancy and more. Electromechanical encoders use a series of sliding contacts attached to a stationary portion. Each contact wipes against a rotating metal disc at a different distance from the shaft. These designs commonly generate six pulses per revolution (PPR), but designs with up to 36 PPR are not uncommon. Speed and mechanical wear of the contacts are typical design concerns. There are many choices for tracking the speed and However, thumbwheel measurements easily fit within these constraints. Common apposition of a motor shaftâ&#x20AC;&#x201D;important in a vast array of plications include level, cursor, frequency, widely different applications, so some guidelines are temperature, time, volume, tone and tuner controls. required to choose the right one. For magnetic encoders, a permanent magnet is firmly mounted on the rotating shaft of a motor or strips of magnetized material are attached to a disk. The output signals are obtained typically by Hall effect or magnetoresistive (MR) sensors. Since magnetic encoders have non-contact by Foo Hong Thong, Avago Technologies operation, mechanical wear is not a design consideration. Typically Hall sensor-based magnetic encoders provide 10 to 13 bits of resolution to otion control encoders are used for position and veloc- address different application needs. Packaging the magnetic IC ity sensing in a wide range of applications from print- and magnet within a single housing simplifies assembly and iners, copiers and scanners to servo and stepper motor tegration into applications by eliminating the process of aligning feedback systems, robotic arms, wafer-handling machines and the encoder against the rotation shaft of the motor. Efforts can medical devices. This class of device includes electromechanical, then be taken to further increase the resolution of the magnetic magnetic, capacitive, inductive and optical solutions. The selec- encoders from 10 bits to 16 bits. Figure 1 provides an example tion of the right motion encoder for the application is a classic of an incremental magnetic encoder in a molded plastic housing. example of engineering optimization of many factors including The encoder provides up to 256 CPR and has a maximum rotatsize, weight, accuracy, speed, power and cost. ing speed of 12,000 rpm mechanical and 7,000 rpm electrical. Magnetic encoders can withstand a variety of application Types of Encoders hazards including dust, dirt, water, oil and wide temperature Encoders arenâ&#x20AC;&#x2122;t the only approach to measuring motion. Re- cycles. As a result, they help provide long life and highly reliable solvers are also an option. These are electromechanical devices measurements. Typical applications include: test and measurewith a mechanical design similar to a motor (or revolving trans- ment equipment, security surveillance, white goods, cable and former) that are quite heavy, have limited interchangeability and satellite dishes, toys, gaming machines, oil dispenser machines, produce an analog (sine-wave) output for position and velocity textile equipment, actuators, pumps and many more. sensing. In contrast, encoders are lighter, have considerable interCapacitive encoders transmit an AC field with a fixed frechangeability and have an inherently digital output. quency past a patterned rotor to a field receiver using capacitive Depending on the application, motion control encoders use rather than magnetic sensing. This class of encoders can take adelectromechanical, magnetic, capacitive and optical technologies vantage of application-specific integrated circuit (ASIC) technolto satisfy application requirements. Common specifications for ogy to convert the output pulses. Some products have program-




Technology deployed

Figure 1 The AEAT-601B magnetic encoder has a 23 mm diameter and 19 mm height and attaches to 6mm shafts.




A Amplitude

mable resolution ranging from 48 to 2048 PPR. The capacitive technique provides very low current consumption but is not widely available. Like with magnetic encoders, the components can be assembled into a single package to simplify their usage. Optical encoders use visible or infrared (IR) LEDs as a light source and light receiving phototransistors or photodiodes as detectors. A code wheel with interspaced slots and solid areas interrupts or commutates the flow of light. As the light passes through the slots on the moving code wheel, it creates alternate light and dark patterns. Where a dark area is detected, a low state (0) is created. When the light successfully penetrates the slot, a high state (1) is created. The position of the shaft is detected by reading the pattern of 1’s and 0’s. Similar to magnetic and capacitive encoders, the components of the optical encoder can easily be assembled into a single package to simplify their usage. Table 1 shows a summary comparison of encoder technologies. The comparisons are for consumer or commercial applications, where the encoder attaches to a printed circuit board (PCB), and not for harsh industrial applications that would have a much broader and, in some cases, much different ratings for many parameters. In addition to the parameter comparison shown in Table 1, optical encoders are attractive due to the industry’s ability to continue to shrink the form factor and reduce the weight and the range of products that are available that make optical encoders extremely flexible and widely used. Typical applications for optical encoders include the factory and industrial automation industry such as robotic arms, valve controls, test and measurement equipment as well as printers, copiers, card readers, scanners, digital still cameras, camcorders, camera phones, projectors and other consumer products.


Optical Encoder Selection Criteria

Once it’s determined, for example, that an optical encoder is the right choice for the application, several other decision factors come into play. These include: linear vs. rotary (or shaft), absolute vs. incremental, multi-turn vs. single turn and reflective vs. transmissive designs. The easiest choice is linear or rotary, since the application essentially determines this. However, unless selecting an encoder is performed routinely, the other design options need additional details. The first level of output differentiation for encoders is absolute versus incremental. However, as Table 2 indicates, there are several other classifications. Incremental encoders provide relative position, where the feedback signal is always referenced to a start or home position and each mechanical position is uniquely defined. This type of encoder provides a pulse for each increment of shaft movement, so the current position is an increment from the previous position and is indicated by a quadrature output device. Quadrature output also applies to other encoder types so it needs further explanation. With quadrature output, the signals from two channels are

Position Figure 2 Quadrature encoding uses two square waves that are 90 degrees out of phase.

offset by 90 degrees. These signals can be read on any edge. Direction information can easily be obtained from the quadrature output. When the codewheel moves in one direction, Channel A leads Channel B. In contrast, when the codewheel passes in the other direction, Channel B leads Channel A. The addition of an indexing pulse, as shown in Figure 2, allows the encoder to observe four states in a single cycle. Optical incremental encoders are used extensively as position (rotary and linear) feedback devices due to their durability and ability to achieve high resolution. For example, the AEDB9140 has two channel quadrature outputs plus a third channel index output. This index output is a 90 electrical degree high true index pulse, which is generated once for each full rotation of the codewheel. The result is a three-channel encoder. Due to a highly RTC MAGAZINE JANUARY 2011


technology deployed

Type of Encoder\Property















very low















very low



very small

very light


very high

very high



TABLE 1 Summary of the parameters for encoder technologies identifies the tradeoffs that designers must consider in selecting a particular technology.

collimated light source and a unique photodetector array, these modules are extremely tolerant to mounting misalignment. Unlike incremental encoders, absolute encoders generate a unique code for each position. When power is initially applied, absolute encoders do not require a home cycleâ&#x20AC;&#x201D;even if the shaft was rotated while the power was switched off. Absolute encoders come in two categories, single-turn and multi-turn, and are offered in a variety of resolutions (e.g., up to 23-bit for single-turn and 16-bit for multi-turn available in the market). Compact absolute encoder modules are easily integrated into space-constrained applications. Single-turn encoders can be designed with an integrated chip or by using an array of photodiodes. Coupled with a highly collimated light source and a uniquely patterned code wheel, these encoders provide a high-resolution output for positional information, typically through a serial data output, e.g. serial synchronous interface (SSI) or the open source protocol bidirectional communication interface for industrial automation (BiSS ). These encoders provide unique positional information for each shaft location. This location is independent from all other locations. In an absolute single-turn encoder application, there are several tracks with common centers and a single light source. For higher resolution single-turn encoders, incremental tracks are added. These tracks enable the interpolation of signals. In addition, these single-turn encodersâ&#x20AC;&#x2122; use of the non-proprietary serial communication protocol allows them to match the output requirements of most applications that require end-to-end communication. Absolute single-turn encoder modules come in a package that is simple to assemble and addresses the needs of a range of applications in the factory and industrial automation industry such as robotic arms, valve controls, test and measurement equipment and more. Multi-turn absolute encoder modules are optoelectronic/ mechanical units that consist of an IR-LED circuit board, a phototransistor circuit board and gear head code wheels. This construction method enables the multi-turn encoders to provide absolute multi-turn positioning information without the need for a battery to back up the power supply in the event of power failures or sudden stoppage. Multiple turns are achieved by placing the multi-turn gear head module onto the primary high-resolution code wheel and single-turn encoder module. High reliability and consistency in providing highly accurate absolute information for multiple revolutions are among the top criteria to look for in these types of encoders. Multi-turn module resolution of 12 bits and 14 bits make multiple turn absolute encoders applicable for a wide range of applications. These encoders are commonly used in industries




bar Index window channel Codewheel



Figure 3 In a reflective type encoder, the bar absorbs light and window reflects light. In a transmissive type encoder, the bar blocks light and window passes light.

Figure 4 At 3 x 3.28 x 1.26 mm, the AEDR-8400 series (resolution up to 318LPI) is the smallest optical encoder employing reflective technology for motion control purposes. A codewheel is required but the output directly interfaces with most of the signal processing circuits.

requiring linear positioning, such as the X&Y Positioning Tables, found in medical institutions and hospitals; pitch and yaw controls, in wind turbines; valve controls; solar tracking; and factory automation equipment.

Reflective Versus Transmissive Encoders

A range of optical encoders that are easily matched with compatible code wheels (such as glass, metal, mylar and plastic) ensures convenience, efficiency, optimum performance and costeffectiveness for a variety of applications. The different designs are classified as reflective or transmissive. With a reflective optical encoder (Figure 3), the reflective area (window) of the codewheel (or codestrip) reflects light back

Technology deployed







Gray Code






Quadrature with Inded


Sine Wave



Pulses Only

Table 2 Several different output types are available from optical as well as other encoders.

to the photodetector IC that is mounted in line with the LED source. No light is reflected by the non-reflective area (bar). Alternating light and dark patterns corresponding to the window and bar fall on the photodiodes as the codewheel rotates and the encoderâ&#x20AC;&#x2122;s detector circuitry produces digital outputs representing the rotation of the codewheel. Figure 4 shows an optical encoder that uses reflective technology and combines an emitter and a detector in a single surface-mount leadless package. In a transmissive encoder, the light is collimated into a parallel beam through a single polycarbonate lens located directly over the LED. The integrated detector circuit is mounted opposite

Untitled-3 1

the emitter. As the code wheel passes between the emitter and detector, the light beam is interrupted by the pattern of spaces and bars on the codewheel. The photodiode detectors are spaced so that a light period on one pair of detectors corresponds to a dark period on the adjacent pair of detectors. The form factor of the reflective encoder (single plane) versus the transmissive encoder (codewheel passes through a groove) is one of the factors that dictate the choice of one technology over the other. As the number of motor controls increases to satisfy the needs of many new applications in consumer, commercial and industrial applications, designersâ&#x20AC;&#x2122; decisions will continue to proliferate for the most appropriate encoder technology. Increasingly smaller and lighter weight encoders with very high precision and accuracy will continue to make optical encoders a widely accepted and frequently preferred technology of choice for these applications. New designs that combine emitters and detectors in very small surface-mount packages will be among the many reasons to evaluate optical encoders. For example, new encoder technology will integrate an index channel to the two existing channels of digital output. In addition, the next-generation encoder will feature a builtin interpolator that allows users to set the interpolation factors to one, two or four times the base resolution of 304LPI. Avago Technologies San Jose, CA. (800) 235-0312. [].


1/18/11 10:38:54 AM RTC MAGAZINE JANUARY 2011

ploration your goal k directly age, the source. ology, d products



New Approaches to System Cooling

A New Approach to 3U VPX Preconfigured Conduction Cooled Systems The OpenVPX specification has provided a great deal of flexibility in system design. This applies not only to configuration of modules via various backplane options, but also to the design of innovative cooling strategies.

by Bill Ripley, Themis Computer


ize, weight and power (SWaP) serial fabrics. This 3U VPX also introrequirements have dramatically duces new hardware design features to the changed the embedded military military and aerospace embedded system and aerospace system landscape. As VPX marketplace consisting of two unique 3U systems mature, the size and modularity VPX chassis baseline designs: • A ½ ATR chassis with universal of the 3U form factor make it the card of cooling options choice for many high-performance rug•  A small form factor conductionged computing platforms including emcooled chassis with fins bedded security systems, rugged-mobile devices, man-wearable packs and robotnies providing now the growing requirement Supporting ½ ATR Chassis Design ion into products, technologies and companies. your goal is to research The the latest for preconfigured systemsWhether in smaller form baseline configuration of the ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you factors, Themis is focused on two mission ATR chassis is a ½ ATR short footprint you require for whatever type of technology, payload initiatives: 3U VPX and an and all configurations of this chassis fit in and productsand you are searching for. evolving small form factor, VITA-74 (also a standard ½ ATR Short mounting tray known as Nano-ATR). This article dis- (Figure 1). The baseline configuration of cusses an innovative approach to 3U VPX the chassis has hole patterns on the sidesystems. walls and rear that allow the installation A new line of conduction-cooled 3U of various “Cooling Kits” for forced air VPX hardware is designed to provide a conduction cooling (FACC), conduction standards-based COTS solution that sup- cooling using natural convection (CCNC), ports modern military applications and conduction cooling using liquid cooling enables faster speeds, higher band¬width (CCLC), as well as cold plate conduction and improved connectivity via high-speed cooling (CPCC). The FACC cooling kit is considered the baseline cooling solution. The FACC variant of the ½ ATR Get Connected chassis utilizes a rear-mounted plenum with companies mentioned in this article. with quad redundant cooling fans. These

End of Article



Get Connected with companies mentioned in this article.

fans pull air through sidewall-mounted heat exchangers. The air path allows for air to be sucked into the front of the sidewall heat exchangers, pulled down the sidewalls, diverted into the rear plenum, and exhausted out the rear of the chassis. A chassis manager module that is installed inside of the chassis assembly controls the speed of the four fans. To improve reliability and to reduce power consumption, the fans only run at the speed required to keep the sidewalls at or below a user-defined limit, usually on the order of 50°C. An additional benefit of using four fans is that any one fan can fail and the failure will not impact the cooling capacity of the system under full power supply unit load. The FACC variant is designed for application of up to 300 watts of power supply unit loading, maintaining +85°C at the card-chassis thermal interface, in a +71°C ambient temperature environment. The CCNC variant of the chassis uses sidewall-mounted fins to radiate the heat using natural convection. In normal mounting configurations, these fins are oriented vertically to provide for


Figure 1 Baseline ½ ATR short footprint chassis.

optimal radiation efficiency. Depending on airflow across the fins, this configuration is designed for application of up to 125 watts at +71°C ambient temperature. The CCLC version uses sidewallmounted heat exchanges for liquid coolant. This configuration is desirable for limited space, high power and applications where forced air is not practical and there is an available infrastructure for liquid cooling. The CCPC cold plate version uses low thermal resistance hardware to “fix mount” the chassis to a vehicle structure or a dedicated cold plate. Borrowing from enterprise and telecommunications trends, the new ½ ATR chassis design uses an integrated chassis manager module to provide a variety of overhead functions inside the chassis. Functionality includes fan speed control, interface to temperature sensors, I 2C interface to each properly equipped card in the system, Built-in-Test (BIT) reporting, and Ethernet switching. An optional electronic hour meter can also be fitted onto the CMM. The total number of operational hours on the chassis may be read via the Ethernet front panel test port. Each of the fans utilized in the system has pulse width modulation (PWM) speed controls. The CMM measures the temperature in the system and adjusts the fan speed under servo con-

trol to maintain the system temperature at a preset value, defaulting to +50°C. The CMM communicates with each card in the system via I 2C. Each properly equipped card can communicate its part number, serial number, temperature, BIT Status and setup information to the CMM. The CMM makes this information available to third-party management software or a maintenance/ administration agent, via an Ethernet port on the front panel test connector of the chassis. Themis 3U VPX cards have the I2C interface required to communicate with the CMM. The CMM also has an Ethernet switch that can communicate via Ethernet with two cards in the system, allowing for example, two different single board computers to communicate between themselves and the front panel test connector. The ½ ATR chassis has optional accessories for removable mass storage. An optional storage receptacle is available for extended temperature, rugged 2.5” solid state disk (SSD) modules. Up to two individually replaceable SATA modules can be fitted in the top of the baseline ½ ATR chassis. Each module can have up to 256 Gbyte capacity. Similarly, a receptacle with a USB connected PC Card receptacle can be added to the baseline configuration. PC Cards are available with up to 64 Gbytes of

Flash storage. Compact Flash cards can be used with appropriate card adapters. The system can be designed in such a way that the SBC boots either from its internal Flash (if so equipped), external removable Flash, or from the network. This allows the system to be completely declassified by removing all Flash storage using the top-mounted storage receptacles. The high top afforded by the external storage receptacles, as well as by another optional 1” top without storage (Figure 2), allows radio frequency (RF) and fiber optic cable routing to the front panel connectors without violating the bend radius constraints of the cable. This feature is especially valuable for software defined radio applications where multiple RF cables must be routed from the front of a 3U VPX SDR card to the front panel of the system. The ½ ATR chassis is designed to be easily modifiable for special system requirements. The front panel I/O comes from an I/O transition connector panel (IOTCP). The IOTCP routes the backplane I/O to either standard D38999 circular MIL connectors, or to a custom connector set that is specified by the customer. Similarly, the baseline backplane connectivity can be easily changed from one program to another, with nonrecurring engineering (NRE) costs much less than required for a scratch designed backplane. If the chassis is required to be shorter in an effort to save space and weight, the design permits easy modification from eight slots to (for example) six or four slot configurations. The second Themis 3U VPX Chassis family has 5 slots at 1-inch pitch, and a 150 watt power supply unit. This chassis has fins and is a conduction-cooled chassis, cooled by natural convection (CCNC). Like the ½ ATR chassis described above, this chassis is designed to allow the inclusion of a removable mass storage device. The power capacity of this system depends on the thermal loading of the included cards, as well as the ambient airflow around the chassis. The chassis can be either mounted in an ATR style tray with swing-nuts and dagger pins, or affixed directly to a vehicle structure, using the optional footpads.




Figure 2 Chassis with side-mounted cooling fins and top receptacle for storage or cabling options.

3U VPX Modules

Themis 3U VPX mission and payload module applications are listed in Table 1. Each board supports the ½ ATR chassis integrated chassis manager via the I2C bus. The backplanes of both systems are designed for maximum flexibility. While backplanes can be customized for particular board sets and applications, predefined configurations can enable very short lead-time programs with very low NRE charges. These applications include: • Mission computer • Display processor • Digital map • Avionics recorder • SIGINT recorder • Network attached storage • Network application server • Payload and I/O controller The backplane connectivity for both chassis designs is designed so that buses and discrete interfaces can be configured with jumpers and “stuff options” to meet the requirements of the above applications. This flexibility allows a significantly shorter delivery time. Just as short lead times and low NRE are critical to fast-paced acquisition requirements, so is the ability to quickly de-



VPX Module



Intel i7 based Single Board Computer


I/O PMC/XMC Carrier Board


8-Port SAS/SATA RAID Board with PMC/XMC Site


SAS/SATA Mass Storage Carrier for FLASH Disks


nVidia E4690 Graphics Processor/Frame Grabber

Table 1 Example mission and payload modules.

ploy such systems. The baseline configurations for both chassis designs are qualified against MIL-STD-810G, MIL-STD-461F and MIL-STD-704F. This data is available to customers as evidence that these reference systems have been prequalified. The VPX standard addresses the rugged SWaP requirements of high-performance military and aerospace, embedded applications. Providing unique benefits for rugged high-performance computing, the VITA 3U VPX standards have greater flexibility, performance and reliability than alternative small form factor standards. 3U VPX enables Themis and other MIL COTS vendors to design powerful processing solutions that provide high

performance and long service life, as well as high reliability and maintainability. Themis Computer Fremont, CA. (510) 252-0870. [].

Accelerating Your Success.

Three Times the Power People. Products. Services. The powerful combination of Avnet and Bell Microproducts provides the expertise you need to accelerate your success. Our combined team gives you access to world-class resources. Bringing industry leading line cards together, we now deliver the most extensive inventory of brand name systems, embedded hardware, displays, storage and software. And, with our enhanced services you have access to Avnet’s leading ISO integration centers, financial solutions and supply chain strategies.

1 800 332 8638 ©Avnet, Inc. 2010. All rights reserved. AVNET is a registered trademark of Avnet, Inc.

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TECHNOLOGY COM Express FPGA Starter Kit for Quick Evaluation with Flexible I/O

A new COM Express starter kit featuring the Altera Cyclone IV GX FPGA provides all the required components to evaluate board designs with open-definable I/Os. With this COM Express FPGA Starterkit from Kontron, OEM developers can get an immediate start in the development of FPGA-based, dedicated applications, thus reducing the overall R&D costs and time-to-market for purpose-built platforms that rely on I/O unique to the application. The components of the starter kit are assembled in minutes allowing the user to move directly to programming on the platform that consists of the selected Computer-on-Module and the individual High Speed Mezzanine Cards (HSMC) to carry out the physical interfaces. OEMs can use the Starterkit to develop dedicated full-custom SBC designs or individual custom carrier boards for scalable x86-based COMs, both with I/Os integrated in Altera’s transceiver-based FPGA, Cyclone IV GX. As a design partner, Kontron offers development and manufacturing services that include, but are not limited to, revision management and industry-specific certifications including ITAR and ISO 13485—a certification necessary for the design and manufacturing of medical devices. FPGA-based I/Os on x86 processor platforms are applicable to many target markets since FPGAs can universally map to nearly all I/Os. The main component in the kit is the COM Express FPGA Baseboard for pin-out Types 1, 2 and 10 COMs. The Altera Cyclone IV GX FPGA is designed into the carrier board and the specific I/Os are configured via enclosed IP bit streams. The configuration of the FPGA is possible through the enclosed USB-Blaster download cable, and the physical interfaces are brought about by two High Speed Mezzanine Cards (HSMCs); one Communication Board and one Mass storage and Video Board. An ATX PSU and mounting kit complete the elements of the Kontron Starterkit. Kontron, Poway, CA. (888) 294-4558. [].

Rugged 6U OpenVPX 10 Gigabit Ethernet Switch Enables for ISR, C4I Systems

A 10 Gigabit Ethernet solution supports highthroughput interprocessor communication (IPC) between 10GigE-enabled processing nodes for deployed applications. With 20 (optionally 24) 10GigE data plane ports and 16 GigE control plane ports, the GBX460 from GE Intelligent Platforms supports non-blocking, low-latency data transfers across a multiprocessing cluster at up to full wire speed. It is designed to provide a high-speed interface for sensor I/O, IPC and data distribution to the back end processing clusters typically found in C4I (command, control, communications, computers and intelligence) infrastructures. The GBX460 is an unmanaged Layer 2 switch that can support multiple OpenVPX slots/module profiles for maximum flexibility and throughput. “An unmanaged switch like the GBX460 is ideal for customer applications requiring the switch to be fully functional for network-connected devices as soon as possible after power-on; this is a capability required by a number of military programs,” said Rob McKeel, president, Military & Aerospace at GE Intelligent Platforms. The GBX460 meets the requirement to support a large number of 10GigE ports to maximize data throughput capabilities, and can optionally support up to four front panel 10GigE fibre ports to enable connectivity to external networks. It is OpenVPX compatible, allowing it to easily integrate with other OpenVPX-compatible products. The GBX460 is available in conduction-cooled variants to allow deployment in harsh environments. GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [].



RF Energy Harvesting Kit for Wireless Battery Charging

An RF energy harvesting kit from Powercast makes it easy to prototype and develop rechargeable battery-based micro-power systems such as wireless sensor networks that are reliably and perpetually powered by radio waves—eliminating the expense and hassle of traditional battery replacement. The Texas Instruments eZ430-RF2500 wireless development tool is also included as a demonstration application. In the kit, Powercast’s 915 MHz RF transmitter and receiver energy-harvesting system broadcasts and then converts RF energy and stores it in a capacitor, which then provides a pulsed regulated voltage output to wirelessly trickle charge energy storage devices. Such devices include the paper-thin and long-life Thinergy MEC as well as other thin-film batteries, and traditional rechargeable batteries such as Alkaline, Lithium Ion, or Nickel Metal Hydride (Ni-MH). When embedded into micro-power devices, such as wireless sensors, instrumentation and controls, the included receiver can charge batteries from more than 40 feet away from the included transmitter. Designers could also use other 850-950 MHz RF transmitters as a source of energy for battery charging. Broadcasted RF energy creates a perpetual power source, unlike potentially unreliable solar, heat or vibration energy sources, to provide power-over-distance, one-to-many charging, and controllable wireless power (continuous, scheduled or on-demand). A wireless power source enables zero-maintenance devices that deploy to inaccessible locations, and embeds within sealed devices for use in wet or harsh environments. Single unit price is $900. Powercast, Pittsburgh, PA. (724) 238-3700. [].

USB 3.0 Flash Drive Enables a Virtual PC to Run on Any PC

With the introduction of USB 3.0, external storage devices can now function at unprecedented speeds. This new found speed blurs the line between internal and external storage and has enabled some exciting new usage models, such as the Ceedo Personal that is being offered with the new USB 3.0 Express RAM Cache flash drive from Super Talent. Ceedo Personal is a portable Windows environment that runs from a USB 3.0 flash drive. It can transform a flash drive into a virtual PC. Using Ceedo, many standard Windows applications can now be made portable for use on any PC; making it possible to install, carry and run the same standard Windows applications that a user already owns and already knows how to use. By combining Ceedo Personal and the USB 3.0 Express RAM Cache drive, Super Talent has created a Windows Virtual PC environment that is fast, flexible and portable. The Ceedo virtual desktop is targeted for anyone who uses more than one PC, shares a PC or travels. And since Ceedo works in user mode, it's suitable for students. Computers located in the computer labs and campus libraries are generally "locked down" in user mode with no hope of installing an application. Now students can take their applications with them and utilize any PC on campus as their own Not quite ready for USB 3.0 yet? Not a problem. The four channel architecture and DRAM caching system found in the USB 3.0 Express RAM CACHE not only works in USB 3.0 but also makes it an extremely fast USB 2.0 drive. Four channels of cache enable filling the USB 2.0 bus to capacity. And the DRAM Caching system delivers high performance, even on the USB 2.0 bus. The caching system elevates small block performance, which is very important for many Windows application calls; and all this still works even from a USB 2.0 port. Super Talent, San Jose, CA. (408) 941-0808. [].

6U VME Single Board Computer with Multi-Function I/O

A 6U, VME Single Board Computer (SBC) combines multifunction and communications I/O options. The 64EP3 from North Atlantic Industries effectively eliminates the need for a separate SBC for I/O-intensive system applications. The processor provides real-time, intelligent sensor data acquisition and local data management operations such as analysis, algorithm manipulation and control of all I/O functions. It also supports direct data management and distribution between dual Gigabit Ethernet and communication interfaces such as MIL-STD-1553, ARINC 429/575, RS232/422/485 and CANBus. The 64EP3 includes four module slots for numerous mix-and-match configurations from a wide selection of multi-function I/O and communication modules. The available I/O functions include A/D, D/A, Discrete/TTL/CMOS/Differential I/O, RTD, Synchro/Resolver/LVDT/ RVDT Measurement and Simulation and Encoder/Counter. Available communication functions include MIL-STD-1553, ARINC 429/575, RS232/422/485 and CANBus. The enhanced motherboard design, using multiple DSPs, enables higher processing power and dedicated control for each I/O module. The U3 Processor Module utilizes Freescale’s 1.25 GHz e500 core MPC8536 PowerPC processor, coupled with Wind River’s VxWorks 6.x BSP and NAI’s full complement of libraries; system integrators are given complete control over the development of their I/O systems using a total NAI solution. The U2 Processor Module is designed with Analog Devices’ 500 MHz low-power Blackfin BF-533 processor. Users can take advantage of the real-time Visual DSP++ Development environment. Armed with NAI’s function module libraries, real-time “C” code applications can be developed and deployed quickly for sensor control and communication management systems.

Quad-Channel MIL-STD-1553 in XMC Module

Curtiss-Wright Controls Embedded Computing (CWCEC), a business group of Curtiss-Wright Controls and a leading designer and manufacturer of commercial off-the-shelf (COTS) VME, VPX, OpenVPX and CompactPCI products for the rugged deployed aerospace and defense market, has announced the availability of the XMC-603. This new rugged quad-channel MIL-STD-1553 XMC interface module speeds and simplifies the integration of dual redundant ports of MIL-STD-1553 into military and aerospace embedded computing systems. The XMC-603 from Curtiss-Wright Controls Embedded Computing is a single-width XMC module and is available in both air-cooled and conduction-cooled configurations. Designed in accordance with the IEEE 1386 and IEEE 1386.1 specifications, the module supports carrier cards with the PMC J4 mezzanine connector for backplane IO and XMC J5, or XMC mezzanine connectors Pn5 and Pn6 for backplane IO. Front panel IO is not supported. The XMC-603 is also backward pin-compatible for 1553 support to CWCEC’s PMC-601 dual port MIL-STD-1553 PMC mezzanine card. Key performance features include up to four independent dualredundant MIL-STD-1553 interfaces along with support for MIL-STD1553A, MIL-STD-1553B Notice 2 and STANAG 3838 and support for both transformer-coupled and direct-coupled interfaces. The module uses the XMC form factor (the IEEE 1386/IEEE 1386.1). BC, RT, MT modes are independently selectable for each channel and there is a PCI Express (PCIe) Gen 1 interface and backplane I/O support. Software support includes drivers for Linux, VxWorks and Windows XP-E operating systems, sold separately. Curtiss-Wright Controls Embedded Computing, Ottawa, Canada. (613) 254-5112. [].

North Atlantic Industries, Bohemia, NY. (631) 567-1100. []. RTC RTCMAGAZINE MAGAZINEJANUARY MONTH 2011 2010



L-Band RF Tuner Integrated with Xilinx Virtex-6 FPGA for Satellite TV, Wireless Comm

An L-Band RF tuner and dual digitizer module incorporates an onboard Xilinx Virtex-6 FPGA. The instrument targets reception and processing of digitally modulated RF signals such as satellite television and terrestrial wireless communications. The Model 71690 from Pentek requires only an antenna and a host system, such as a personal computer, to form a complete L-band SDR development platform. The 71690 RF tuner and digitizer module is capable of directly receiving and digitizing signals in the 925 MHz to 2175 MHz (Lband) frequency range with a dynamic range of -75 dBm to 0 dBm. The MAX2112 direct-conversion tuner IC integrates variable-gain amplifiers, dual downconverting mixers and configurable-bandwidth low-pass filters to produce baseband analog in-phase (I) and quadrature (Q) signals for digitization. Dual 16-bit, 200 MHz ADCs synchronously sample the I and Q signals, passing them to a Xilinx Virtex-6 FPGA for processing tasks such as demodulation, decoding and decryption. Customers can choose from a variety of FPGAs, including the LX130T, LX240T, LX365T, SX315T and SX475T, to obtain the processing performance they need at the lowest cost. Four independent memory banks provide the 71690 with a capacity of up 2 Gbyte of DDR3 SDRAM for applications requiring deep memory, or up to 32 Mbyte of QDRII+ SRAM for applications requiring fast random access. The module’s external interfaces include a Gen2 PCI Express bus (x8) for native connection to the host system for control and data transfer. In addition, the module offers applicationspecific options for installation of 20 LVDS pairs for general-purpose input/output and four gigabit interfaces to support serial protocols. Software IP for the onboard Virtex-6 FPGA provides customers with a combination of turnkey and custom functionality. The board ships with the FPGA configured to provide data acquisition, synchronization, triggering and memory control as well as a test signal generator and control of the RF receiver tuning and bandwidth for a complete baseband signal receiver solution. The additional space available even in the smallest FPGA option also provides users ample opportunity to add their own IP using Pentek’s GateFlow Design Kit. The 71690’s native form factor is a ruggedized XMC module. It can also be implemented in PCI Express (Model 78690) and VITA 65 3U VPX (Model 53690) form factors. ReadyFlow software support for the Model 71690 includes drivers for Windows and Linux platforms, as well as future support for VxWorks. Pricing starts at $9,995. Pentek, Upper Saddle River, NJ. (201) 818-5900. [].

Compact 300 Watt 3 x 5” Switcher Comes in Five Models

A new Series of 300 watt High-Density / HighEfficiency switching power supplies in a compact 3.00 x 5.00 x 1.34” open-frame package comes in five models. The VHD300 Series from PowerGate comes in versions with main output voltages ranging from 1248 VDC and auxiliary outputs of 5VSb @ 1A and 12V Fan @ 1A. All models of the VHD300 family feature Remote On/Off Control; DC OK Signal; Universal AC Input (90-264 VAC); High Efficiency operation up to 89%; Active Power Factor Correction for EN61000-3-2 Class D compliance; Full load operation up to 50°C with 20 cfm airflow (150 watts convection cooled); and Reliability in excess of 100k Hours. The series has been qualified for Class B Emissions and is safety approved to UL/cUL 609501, EN60950-1 standards and bears the CE Mark. Pricing starts at $76 in 500 piece quantities. PowerGate, Santa Clara, CA. (408) 588-1751. [].



Extreme Rugged PC/104-Plus SBC with Atom Processor

Supporting a range of Intel Atom processors from the power efficient N450 running at 1.66 GHz to the performance oriented dualcore D510, a new PC/104-Plus module takes advantage of Atom’s two-chip solution architecture with integrated memory and graphics controllers to balance excellent performance with very low power requirements. With a TDP as low as 9W, the CoreModule 745 from Adlink simplifies cooling requirements and enables conduction-cooled solutions for small sealed enclosures in space-constrained applications. Rugged by design, the CoreModule 745 supports a wealth of legacy I/O interfaces including ISA and PCI buses. Serial ports, one GbE port and up to 2 Gbyte of DDR2 667 MHz RAM are also incorporated into an expanded PC/104 footprint. This stackable PC/104-Plus SBC allows OEMs in military, avionics, transportation and other rugged markets to add a state-of-the-art Intel Architecture controller to their systems without the need for a custom carrier board. The CoreModule 745 also provides a simple upgrade path for the broad base of existing PC/104 system designs. Adlink’s Extreme Rugged design methodology enables operation at temperatures from -40° to +85°C, vibration up to 11.95 Grms, and shock up to 50Grms. The CoreModule 745 also features a full 16-bit ISA bus, PCI 32-bit bus, one GbE port, two RS-232 serial ports, one RS-232/422/485 port, four USB 2.0 ports and eight GPIO. In addition, it offers graphics performance with an LVDS panel interface and legacy CRT support. For harsh environments, optional conformal coating is offered. The CoreModule 745 is available with QuickStart Kits including cables, 2 Gbyte DDR2 RAM, device drivers and board support packages (BSPs) for many popular operating systems including VxWorks, Windows CE, Windows XP Embedded, Linux and QNX. ADLINK Technology, San Jose, CA (408) 495-5557. [].


PCIe-Based 2-Channel, High-Speed Digitizers Hit 1.5 GHz per Channel

A new PCIe-based wideband A/D board captures two synchronized analog channels at sampling rates up to 1.5 GHz, or one channel at up to 3 GHz when interleaving the ADC data. 1 Gbyte of onboard memory configured as a large FIFO and a PCIe x8 bus ensures the PX1500-2 from Signatec can continuously sustain long recordings at up to 1.4 Gbyte/s through the PCIe x8 bus (both mechanical and electrical) to PC disk storage without any break in the analog record. The PX1500-2 can be set up to use either a transformer-coupled front end or an amplifier connection. The transformer connection can only be set for AC-coupled operation and has a frequency capture range of 5 MHz to 2 GHz. The amplifier can be set for either AC-coupled or DC-coupled operation with a frequency range of up to 1 GHz. Beyond its high-speed, multi-channel performance capabilities, the PX1500-2’s frequency synthesized clock allows the ADC sampling rate to be set to virtually any value from 200 MHz—the minimum allowable ADC clock—up to 1500 MHz. Additional divide-by-2 circuits are provided for sampling at even lower frequencies. This frequency selection flexibility comes at no cost to the acquisition clock quality/performance when locked to either the onboard 10 MHz, 5 PPM reference clock or to an externally provided 10 MHz reference clock. The ADC may also be clocked from an external clock source. Up to three PX1500-2 boards may be interconnected in a Master/Slave configuration via a ribbon cable that connects at the top of the boards. In this configuration, the clock and trigger signals from the Master drive the Slave boards so that data sampling on all boards occurs simultaneously. Up to 18 boards can be set up for fully synchronized operation by utilizing the SYNC1500-6 as the clock and source forwith sixtechnology master boards, Gettrigger Connected and solutions nowallows where all 18 boards can function synchronously even when placed into different PC chassis. This scalabilitycompanies of chassisproviding and system resources for increasing the sustained data rate per channel for high-speed signal recording and/or real-time processing Get applications. Connected is a new resource for further exploration

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Signatec, Newport Beach, CA. (949) 729-1084. [].

16k CMOS-based Line Scan Camera Hits 1146 Mpixels/s

A new high-speed CMOS-based line scan camera features 16k resolution with a 3.5 µm pixel size and a 70 kHz line rate for ultra-fast 1146 Mpixels/s throughput. The Piranha3 from Dalsa features CMOS technology that provides on-chip analog to digital conversion (ADC) and Correlated Double Sampling (CDS). The camera delivers high speed with low noise and high dynamic range. It is suited for the inspection of large area flat-panel displays and printed circuit boards, along with high-performance document scanning and other high-throughput applications. The new Piranha3 16k delivers this precision and speed within a compact form factor of 150 x 80 x 77 mm. To deliver its full bandwidth, the Piranha3 16k high speed uses the new HSLink machine vision connectivity interface pioneered by Dalsa. HSLink takes the key strengths of Camera Link, adds new features and functions, and combines them with scalable bandwidth in 300 Mbyte/s steps (from 300 to 6000 Mbytes/s) while using globally available, off-the-shelf components. The Piranha3 16k camera is supported by Dalsa’s Xcelera-HS PX8 frame grabber. The Xcelera-HS PX8 also leverages Dalsa’s new HSLink interface to deliver unprecedented image acquisition bandwidth of 1.8 Gbytes/s and host transfer bandwidth of 2 Gbytes/s over multiple-lane PCI Express implementations. All Piranha cameras are supported by Dalsa’s Sapera vision software. This core development platform includes over 400 image processing primitive and industrial strength image analysis tools such as pattern finding, 1D and 2D barcode and OCR tools for part identification and detection, color processing tool, separation and measurement applications, blob analysis tool and inspection metrology tool for real-world dimensional measurements. Dalsa, Billerica, MA. (978) 670-2000. [].

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u-blox, Thalwil, Switzerland.+44 722 74 44. [].

Get Connected with companies and products featured in this section.




MIL-STD 1553 Modules for Industrial PCs and Embedded Systems

Two new versions of MIL-STD-1553 bus modules are being made available to interface avionics and weapons subsystems to an embedded control system. Acromag’s IP570 is an Industry Pack ANSI/VITA-4 card that plugs into VME, CompactPCI and PCI bus mezzanine carrier cards or high-performance single board computers. The company’s IOS-570 models are designed for use within Acromag’s I/O Server industrial PC, a small fanless box computer. Both 1553 bus modules offer the choice of one or two interface channels. A DDC Micro-ACE device controls the 1553 interface. Extended temperature models support -40° to 85°C operation. All models feature a DDC Micro-ACE bus terminal that supports both MIL-STD-1553 revision B and MIL-STD-1760 transceivers, as well as the STANAG 3838 protocol. Users can choose from models with one or two complete dual-redundant interface channels. Each channel can be wired for either direct or transformer coupled operation and operates at data rates of up to 1 Mbit/s. The DDC Micro-ACE controller provides a flexible host-side interface that is compatible with Mini-ACE or ACE architectures and supports multiple configurations (bus controller, remote terminal, or bus monitor). Users get a highly autonomous bus controller with many powerful capabilities and options. Acromag offers several programmer support tools. A Windows development package provides API development software and Win32 DLL drivers, plus examples for C, Visual Basic, .Net and LabVIEW environments. The Linux software includes a library of I/O function routines to speed code development. IP modules are additionally supported by C libraries for VxWorks and QNX real-time operating systems. These packages include demonstration programs with C source code to test and exercise the I/O module operation. Single quantity pricing starts at $1,695. Acromag, Wixom, MI. (248) 295-0310. [].

Ruggedized VPX Boards Offer Xilinx Virtex-6 FPGAs

A family of ruggedized boards for high-performance military and avionics applications utilizes Xilinx’s Virtex-6 FPGAs for onboard signal processing, delivering digital sampling rates to 1 GHz in a compact 3U VPX form factor. The 53xxx Cobalt board family from Pentek combines processing, data conversion and preconfigured functions and is suitable for such applications as UAV, CommINT (Communications Intelligence) transceivers, airborne communications recorders, airborne radar countermeasures, shipboard diversity transceivers and armored vehicle anti-IED systems. Pentek’s 53xxx Cobalt family brings Virtex-6 FPGA technology to the VPX format. With more than twice the resources of previous Virtex generations, including new enhancements in digital signal processing, logic and clocking, the Virtex-6 family provides developers with a previously unavailable level of customizable processing power. Pentek gives the FPGA full access to all data and control paths and then harnesses its raw processing power by preconfiguring boards with key functions. This strategy provides a wealth of useful turn-key operations, while leaving enough unused FPGA capacity for adding customer-developed IP. All Cobalt VPX products are available with a choice of Xilinx Virtex-6 LXT or SXT FPGA devices to match the application. Other common features of Cobalt boards include PCI Express (Gen 2) interfaces up to 8 lanes wide, synchronous clocking locked to an external system reference, and an LVPECL synch bus for synchronizing multiple modules to increase channel count. Users can readily integrate custom processing algorithms with the factory-installed IP in Cobalt devices using Pentek’s GateFlow FPGA design kits. Software development tools for Cprogramming include ReadyFlow Board Support packages for Windows, Linux and VxWorks operating systems. Pricing starts at $14,490. Pentek, Upper Saddle River, NJ. (201) 818-5900. [].



Hybrid Flat Panel USB Controller Board – Ethernet and Wireless

A controller board family for industrial flat panel solutions is available in 4 basic versions from Display Solution. The d.screen Hybrid board matches and exceeds the needs of industrial display applications as well as portable multifunctional monitors. Innovative control via Ethernet or USB / WUSB (Wireless USB) for displays is now possible. The d.screen Hybrid controller supports resolutions up to Full-HD/WUXGA/QWXGA, allows one to connect up to six additional LCD displays without an extra graphic card and is based on DisplayLink’s latest chip generation. It includes an Onboard USB Hub to connect up to three additional USB devices. Its high efficient power supply of 5V or 12/24V, the Ethernet 10/100/ Gigabit or USB2.0/WUSB interface and optional DVI/RGB output interface allow the development of outstanding modern TFT applications. For Touch applications, an onboard optional Touch Controller for 4- or 5-wire resistive Touch Screens can be offered. Small display applications up to 2.5 watt power consumption could be bus powered via USB cable, in this case no external power supply is needed. A Power over Ethernet option will be ready for the market in Q2 2011. All members of the d.screen USB Hybrid family are designed for industrial use to meet the specific requirements of embedded applications including the critical long-term availability aspect often not found in consumer or Far Eastern products. Display Solution Gilching Germany. +49 (0) 81 05 - 73403-0. [].


OpenVPX Xeon-Based Rugged Server-Class SBC for ISR Applications

A high density server for rugged deployed intelligence surveillance and reconnaissance (ISR) systems brings Intel enterprise server-class processing to deployed sensor-based systems. The HDS6600 from Mercury Computer Systems supports 8-way symmetric multiprocessing (SMP) and is based on Intel’s Xeon processor, enabling enterprise-class performance typically found in data centers to be forward deployed, in the air and other harsh environments. With the familiar Intel architecture, Linux operating system and server-class performance, applications can more easily migrate from workstations and ground stations to tactical environments, facilitating a common code base between the lab and deployed environments. The HDS6600 is designed to the OpenVPX standard for ease of integration with traditional sensor hardware, supporting rapid deployment in harsh air- and conduction-cooled environments. In addition to deployed server applications, the HDS6600 achieves new performance levels in traditional signal and image processing applications. With dual quad-core Intel Xeon enterprise server-class processors in a standard one inch OpenVPX slot, a ten-board system reaches over one tera floating point operations per second (TFLOPS) of peak performance, and an order of magnitude improvement in signal and image processing throughput performance compared to rugged Intel modules available today. To achieve the highest efficiency, an ISR subsystem must have performance balanced with both I/O and memory. The high-performance communications among HDS6600 modules is facilitated by Mercury’s Protocol Offload Engine Technology (POET), which encapsulates standards-based protocol management, such as Serial RapidIO and PCIe, with high-speed real-time switching capability. The 12 Gbytes of onboard SDRAM memory is well balanced for the 8 Intel Xeon cores, and represents a 4x increase over previous generation module memory size. For applications requiring even more memory, 24 Gbyte offerings are planned. For the ultimate size, weight and power (SWaP) performance, such as is required by persistent ISR applications, the HDS6600 Intel rugged server can be combined with Mercury’s latest GPGPU offerings. For example, two high-end GPGPU-based GSC6200 modules, each with two GPGPUs, can be directly connected to a HDS6600 through the OpenVPX expansion plane. This 3-slot slice achieves performance well into the TFLOPS range of processing and can be replicated multiple times in a chassis to create unprecedented computational performance in an ISR subsystem. The product is supported by an open development environment based on Linux and Eclipse, and includes the MultiCore Plus Software Development environment and OpenSAL libraries. Mercury Computer Systems, Chelmsford, MA. (978) 256-1300. [].

Rugged, Removable SSD Supports 256-Bit Encryption and Declassification

A ruggedized, removable SATA solid-state disk (SSD) supports 256bit AES encryption and declassification capabilities. With its storage capacity of up to 256 Gbyte and its maximum performance of up to 240 Mbyte/s (read) and 215 Mbyte/s (write), the XPort6192 from Extreme Engineering Solutions is suitable for conduction- or air-cooled applications requiring secure, high-capacity and high-performance removable storage media. The XPort6192 features a small form factor that fits within a standard 3U 0.8” pitch slot. It is based on reliable SLC NAND flash technology with up to 256 Gbyte capacity. It boasts up to 240 Mbyte/s read and 215 Mbyte/s write performance with optional AES 256-bit encryption and ATA Secure Erase support with optional declassification (enhanced erase) support. The XPort6192 is designed for rugged environments (-40° to 85°C operating temperature range) and provides 100,000 program/erase cycles with global wear leveling support for added memory endurance. An easy insertion and extraction mechanism along with a high-reliability connector support 100,000 insertions/extractions.

ATX Motherboard with Core i5/i7 Processors Features “Greener” Technology

Extreme Engineering Solutions, Middleton, WI. (608) 833-1155.

Aimed at customers who seek significant computing performance and lower power consumption improvements, an industrial ATX form factor motherboard is based on Intel’s Mobile QM57 Express Chipset supporting the latest Core i5 or i7 processor for Quad Core CPU support. The RUBY-M710VG2AR from American Portwell Technology is the tool to help build environmentally friendly, greener embedded PC solutions. The new motherboard features: two 240-pin DIMM sockets to support dual-channel DDR3 1066/800 SDRAM up to 8 Gbyte; dual display via VGA/DVI-D/HDMI/ LVDS; one PCI-E x16, one PCI-E x4, one PCI-E x1, four PCI expansion slots and one Mini PCI-E socket; dual Intel GbE LANs (one of which can support iAMT 6.0); plus SATA (supporting RAID 0, 1, 5, 10), Audio and USB. The new RUBY-M710VG2AR also provides legacy support for Intel Celeron processor P4500. The key difference is that the RUBY-M710VG2AR industrial ATX motherboard is based on the mobile processor with CPU and chipset thermal design power (TDP) at 38.5W. This configuration saves more than 60 percent energy over most of the off-the-shelf PCs currently on the market. Today, the major portion of the cost for those industries requiring high-performance computing is the yearly energy charge.


American Portwell Technology, Fremont, CA. (510) 403-3399. [www/]. RTC RTCMAGAZINE MAGAZINEJANUARY MONTH 2011 2010



First PCI Express 3.0 Switches Start Sampling

What appear to be the industry’s first PCI Express 3.0 (PCIe Gen 3) switches have begun to become available as samples from PLX Technology. Each of the six new Gen 3 switches is designed to upgrade today’s widely deployed PCIe-based systems including computing and communications platforms. The new PLX ExpressLane PCIe Gen 3 switch family, designed on 40nm process node, includes broad lane counts ranging from 12 to 48 lanes. Board and system designers can take full advantage of the latest PCIe specification—8 Gbit/s in both directions (Tx/Rx), per lane— thus enabling one PLX 48-lane Gen 3 switch to handle an astounding 96 Gbit/s of full peer-to-peer bandwidth. PLX’s Gen 3 switches also offer hot-plug controllers, virtual channels and a non-transparent (NT) port feature, which enable the implementation of multi-host systems in communications, storage and blade server applications. PLX’s new Gen 3 switch family is comprised of: • PEX8712: 12 lanes, 3 ports • PEX8716: 16 lane, 4 ports • PEX8724: 24 lane, 6 ports • PEX8732: 32 lane, 12 ports • PEX8747: 48 lane, 5 ports • PEX8748: 48 lane, 12 ports PLX PCIe Gen 3 switches include software-driven on-chip hardware debug and monitoring features such as measurement of the SerDes eye inside the device; PCIe packet generation to saturate x16 Gen 3 port; injection of error in live traffic; error logging; port utilization count; as well as PCIe and traffic monitoring for easy bring-up of PCIe systems that would otherwise require days of lab set-up and hundreds of thousands of dollars in test and measurement equipment. Furthermore, PLX offers designers a software development kit that simplifies design-in of the switch and its value-added features. The PLX ExpressLane PCIe Gen 3 switches are available in 19x19 mm (PEX8712, PEX8716 and PEX8724) or 27x27 mm (PEX8732, PEX8747 and PEX8748) packaging. Volume pricing ranges from $40 to $80. Sampling with key customers begins this week with production slated for mid-2011. PLX Gen 3 switches are fully backward compatible to PCIe Gen 2 and Gen 1 and are recommended for all new designs. PLX Technology, Sunnyvale, CA. (408) 774-9060. [].

Serial Synchronous Interface Module for Motion Control and Position Sensing

A communications interface between digital encoders and SNAP PAC System I/O processors or programmable automation controllers provides two isolated serial synchronous inputs (SSI) for acquiring data from optical and mechanical encoders and other types of linear and rotary transducers. Designed for use in motion control and other applications where tracking and identifying the movement and position of machinery or components is critical, the SNAP-SCM-SSI from Opto22 connects to and accepts input from either binary or Gray code encoders. This allows the module to process and communicate position-related data from heavy duty industrial machinery and apparatus (such as floodgates, drawbridges and rotating or elevating platforms) as well as machine tools, stepper motors, servos, and other moving or robotic components. The SNAP-SCM-SSI accommodates an SSI clock frequency of up to 2.5 MHz, functions at cable lengths up to 500 feet, and can be configured for clock frequency, data bits (i.e., encoder resolution), time interval between data samples and more. The module can be used with both SNAP PAC Ethernet (EB-series) and SNAP PAC serial (SB-series) I/O processors, standard SNAP PAC standalone and rackmounted controllers, and all SNAP PAC Wired+Wireless controllers. Pricing starts at $295. Opto22, Temecula, CA. (951) 695-3000. [].



Desktop Comm Appliance Supports Atom D510/D410/N450 Processors

A new desktop communication appliance features a reset button that will change the system back to the manufacturer’s default setting, if required. The CAD-0210 from American Portwell is also suitable for customers who need 6 GbE ports and applications that require the high performance and low power consumption of Intel’s dual-core Atom D510 processor. The new CAD-0210 desktop communication appliance features Intel’s Atom processor D510, D410 or N450 with ICH8M I/O controller. It supports: fanless operation (when used with the N450); up to 4 Gbyte DIMM with D510/D410 and up to 2 Gbyte DIMM with N450; 6 GbE ports (Intel 82583V) with two bypass segments; two SATA ports and one CompactFlash card slot; onboard RS-232 via an RJ-45 connector and two USB ports; one Mini PCI slot and one PCI slot; LEDS on front panel for Power and HDD status; reset and factory defaults button; a 12V 40W/60W DC adapter; and support for Wake-On-LAN (WOL) function. Available now, CAD-0210 is a solution for system integrators (SI), OEM customers, software developers and SOHO and remote/ satellite office users in security networking applications such as network intrusion, prevention and detection; spyware control; content filtering; P2P control; and instant message recording. American Portwell Technology, Fremont, CA. (510) 403-3399. [www/].


Boundary Scan Platform Scanflex with New PXI Express Controllers

A new family of PXI Express controllers features TAP Transceivers, which are now integrated in the 1 slot/3U controllers. The new Scanflex boundary scan controllers (SFX Controller) from Goepel Electronic is named SFX/PXIe1149/C(x) and includes altogether nine models with different signal conditions and performance classes. In addition to a 2 TAP version, a 4 TAP solution and a so called FXT Version, also with four TAP, has been developed. All controllers are available in three performance classes: A, B and C. The models differ in the maximum Clock frequency (TCK) (20, 50 and 80 MHz, respectively) and in the degree of implementation of the enhanced Space chip set for high-performance scan operations. In contrast to conventional solutions, the integrated Fastscale technology allows an upgrade of the controller’s performance class “on the fly,” without intricate fitting of additional hardware. The x1 interface of SFX/PXIe1149/C(x) achieves transfer rates of up to 264 Mbyte/s in the zero wait state burst mode, and is based on the PXI Express hardware specification 1.0, whereby defined local bus, trigger and synchronization mechanisms are supported. In combination with the modular Scanflex component portfolio, PXI Express-based high-performance boundary scan systems with up to four independent TAP can be configured and open synchronized with other functional modules. All TAPs provide, among others, programmable input and output impedances. Furthermore, resources such as 32 dynamic I/O, two analog I/O channels, three static I/O and trigger lines are parts of the basic equipment. For particularly critical application, the specific FXT version is available. In this version, so called TAP Cardswith (TIC) are coupled Get Interface Connected technology and externally to the controller. The TIC work as active test heads and enable a complete signal conditioning, e.g. directly within a fixture or an environcompanies providing solutions now ment chamber for HASS/HALT applications. There are various TIC types, identified automatically, for different utilizations. Their fastforcoupling Get Connected is a new resource further exploration guarantees an interference-free TAP signal transmission even for multi transitions of up to four meters atinto a TCK frequency of up to 80 MHz.Whether your goal products, technologies and companies.

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Standard ½ ATR Footprint Standard 3U VPX Backplane I/O Transition Board Forced Air Conduction Cooled Standard Optional External FLASH Drive Receptacles 'JOOFE $PMEQMBUFPS-JRVJE$PPM0QUJPO Integrated Chassis Manager Multi-port Ethernet Switch Optional Electronic Hour-Meter I2C Interface to Cards and Test Port Multiple Temperature Sensors Dynamic Fan Speed Control Web Browser Management Interface Variable Speed Redundant Fans 28 VDC Power Supply Unit 350 Watts 8 x 1.0â&#x20AC;? Pitch Slotss

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Available 3U VPX Cards


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TIOC-300X 3U VPX XMC/PMC Carrier Module


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TSC-300X 3U VPX 8-Port SATA/SAS RAID Module with PMC/XMC Site TSM-300X 3U VPX SATA/SAS Mass Storage Drive Module


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RTC magazine  

January 2011

RTC magazine  

January 2011