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The magazine of record for the embedded computing industry

November 2010

Open VPX:

Getting from Spec to System

ARM and Power Modules Go After the Details Preconfigured Industrial PCs—Think Inside the Box Wearable Computers Morph to Fit the User An RTC Group Publication


fully-assembled turnkey solutions Run, drive, or fly your Simulink design in real time, using Rapid Prototyping or Hardware-in the-Loop simulations on low-cost PC-based hardware. xPC Target provides a library of device drivers, a real-time kernel, and an interface for monitoring, parameter tuning, and data logging. It supports a full range of standard IO modules, protocols, and target computers.

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Find it at datasheet video example trial request


Simulink and xPC Target™


©2010 The MathWorks, Inc.


OpenVPX: Getting from Spec to System

46 “VPX Cube” 3U Rugged Conduction-Cooled Enclosure

48 PrPMC/XMC Module Targets Freescale Dual-Core QorIQ P2020


51 Compact MicroTCA Platform Holds Four Double-Width AMC Modules



6Editorial Can the Cloud Simplify Remote Maintenance? Industry Insider Latest Developments in the Embedded Marketplace

8 Form Factor Forum 12Small FPGAs – The Logical Choice & Technology 46Products Newest Embedded Technology Used by Industry Leaders EDITOR’S REPORT Homing in on Power Management


Technology in Context


ARM and Power Modules

OpenVPX Part 2

Architecture Technology Navigating OpenVPX: Developing 18 Power 30 Enables Differentiated Solution for and Building Systems Using LTE OpenVPX Profiles Fawzi Behmann,

Ken Grob, Elma Electronic

ARMing the 22 Appropriately Embedded World



Industrial Computers Make Inroads on Rack34Preconfigured Based Systems

Susan Wooley, Micro/sys

Network Convergence


The Internet of Things and the Convergence of Networks

Stamatis Karnouskos, JP Vasseur, Patrick Wetterwald, Jerald Martocci, Ted Humpal and Ming Zhu, The IPSO Alliance

Getting to Low Power Consumption Depends on the Right Data—and Using it Tom Williams

Preconfigured Industrial PCs

Joseph Primeau, Acromag

Industry watch

Wearable Computers – Form and Function Still Reign 38Modern of PSoC in Electronic 42Application Medical Devices Tiziano Modotti and Haritha Treadway, Eurotech

Sammy Lee, Cypress Semiconductor

Digital Subscriptions Avaliable at RTC MAGAZINE NOVEMBER 2010


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EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

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EDITORIAL november 2010

Can the Cloud Simplify Remote Maintenance?


uch is being made these day of “cloud computing,” in which often sophisticated applications reside on rented server capacity on the Web. This allows application developers to charge for their services by both creating original applications to provide them while at the same time taking advantage of shared resources already available on the Web that may be available for use to the application developer either for free or for a fee. For example, if a particular application requires location information, it is possible to utilize the already existing and debugged Google Earth to pinpoint locations as if it were an integral part of the application. Google Earth is reportedly available for such use free of charge up to a point after which fees apply. This lets a developer get the application written, debugged and working in a real business environment before having to spend real money. Other such applications are available in the cloud under similar conditions. By the same token, since the computing resources are available from service providers, they can be leased as needed and scaled appropriately as the acceptance of the application grows. It is not surprising that cloud computing is encouraging increased innovation from developers who are more risk-averse and have access to more limited resources than was previously possible. Until recently, cloud computing was mostly used by applications with more of an IT character, but now it is expanding to include embedded applications as well. “Device to cloud” is the name being applied to the model in which the cloud application interacts with embedded devices that may be distributed all over the world but which are connected to the Internet and hence to the application. Such devices can be almost anything imaginable, but let’s pick a mundane example such as vending machines. It wasn’t long ago that the idea of a model for managing and maintaining devices over the Web was to have a little embedded Web page in each device that would present the needed data to the user when logged on and allow access and control of appropriate functions. Thus it was possible to determine what was wrong with the arctic oil rig and what parts were needed before dispatching maintenance personnel over the frozen tundra to look into the matter.



Tom Williams Editor-in-Chief

That model may work well with something as small in numbers and as complex as an oil rig, but how does it scale to thousands of vending machines? It is not practical to log onto each one individually to see how many cans of Jolt Cola are left. The memory and overhead to maintain even a tiny Web page on each one soon becomes impractical as well. The less software you have running on the individual device, the less cost and potential trouble you have. The device to cloud model can greatly simplify this and can offer a general model that can be adapted to myriad specific applications. With all the application intelligence resident in the cloud within the application running and storing data on those leased server resources, the hardware and software requirements on the devices can be minimized. And communication protocols can be simplified as well. All the device really has to be able to do is to send and receive packets of bits. The values of those bits can be defined by the application. For example, bits 0-255 are the device ID; 256-511 are temperature, and so on. The device simply writes the values into the proper bit field in the packet and sends it. The application reads that data, stores it and takes appropriate action. If control functions are needed on the remote device, the same paradigm applies with the added complexity of control functions resident on the device to carry out the instructions contained in the received packet’s bit fields. Beyond the data exchange and the sending of control commands, all the intelligence can reside in the application in the cloud. Communication protocols are straightforward and the application can be expanded, modified and linked to other applications without the need to access the devices unless it is necessary to build in some sort of new sensor or actuator, which would require direct access in any event. The location of each device could easily be determined by matching it with location data and pinpointing it on a program like Google Earth. With data and applications available on the cloud, data can be shared among applications. For example, maintenance data could also be used by a fleet management application coordinating with delivery and maintenance truck routing and feeding into inventory and purchasing. Thus the device to cloud paradigm would have direct input to the IT end of a business operation and require less computing resources in the remote devices while providing more utility for expanded operations.



SAL, MultiCore SAL, VSIPL and MultiCore VSIPL are components of Mercury’s MultiCore Plus Software Environment, open, flexible and optimized libraries for real-time programming. Various accelerated versions of OpenSAL for PowerPC processors and Intel processors, as well as GPUs are available from Mercury under commercial license, and also through engagement with Mercury’s Services and Systems Integration team. OpenSAL is available for download at www.opensal. net or via projects/opensal/.

Systems to translate Elliptic’s portfolio of security IP into system-level models, which can be used by SoC architects, hardware and software teams that are working in SystemC environments. The growing complexity of Semiconductor Intellectual Property (SIP) security solutions has driven the need for higher levels of abstraction and modeling. This approach enables complex SoC and system solutions to be modeled, analyzed and designed accurately early in the development cycle. Verification of system architecture and other system-level attributes can be orders of magnitude faster than RTL models. High-level SystemC virtual prototypes have emerged as the de facto standard, but the creation of these cycle-accurate models has been a time-consuming and complex engineering task—until now. Carbon Model Studio allows companies to create high-performance system-level models called “Carbon” models directly from RTL. The cycle-accurate models enable SoC architects to rapidly evaluate, analyze and profile the underlying RTL. Software engineers can develop and debug embedded software, firmware, drivers and diagnostics concurrent with hardware development. System integrators can design-in thirdparty IP, and develop, evaluate and benchmark accurate virtual platforms ahead of full hardware integration or silicon availability. Carbon Model Studio also provides industry-standard interfaces such as PCIe, AHB, AXI, or TLM so that end-users can integrate with interfaces that work best for them.

Elliptic, Carbon Design Partner to Create Accurate System-Level Models

Renesas Launches RX Microcontroller Design Contest

Wind River and Alcatel-Lucent Team to Boost Wireless Network Performance Wind River has announced that it is collaborating with Alcatel-Lucent to develop common platform assets for Alcatel-Lucent’s wireless network base station portfolio. Alcatel-Lucent’s common platform provides the hardware and software foundation for present and future generations of its wireless network products, including both time division duplex and frequency division duplex variants of 4G or LTE base stations. Alcatel-Lucent will use Wind River Linux, optimized for the Freescale QorIQ P4080 multicore processor, to develop and support the common platform. Given the growing demands from ever increasing wireless data traffic, Alcatel-Lucent evaluated a number of solutions to ensure it would be able to create a common foundation with high performance and reliability for its wireless network infrastructure. Wind River Linux delivered on AlcatelLucent’s needs for open source innovation and customization available from Linux, coupled with the benefits of a stable, carrier grade commercial product as well as the latest in multicore software technologies. The Alcatel-Lucent common platform is based on Wind River Linux and includes the recently released Linux kernel version 2.6.34. The latest revision of PREEMPT RT was used to advance pre-emption capabilities and create a Linux kernel that is more deterministic, with reduced latency for a real-time response. To ensure its readiness for the latest multicore architectures, Wind River Linux was optimized to fully support the QorIQ P4080 processor.

Mercury Releases OpenSAL – Open Source Version of Scientific Algorithm Library

Mercury Computer Systems has announced the availability of OpenSAL, an open source version of its award-winning Scientific Algorithm Library (SAL) for vector math acceleration. SAL is a high-throughput, low-latency signal processing library containing efficient algorithms with the fewest possible instructions and computing resources. OpenSAL provides a robust API, C code reference design and documentation for over 400 SAL math functions. Mercury’s SAL is a de facto industry standard, with thousands of production installations in highly compute-intensive, real-time applications such as radar, electronic warfare and signals intelligence.



Elliptic Technologies has announced that the company has partnered with Carbon Design

To spur embedded design creativity and competition, Renesas Electronics America has

launched its Renesas RX Design Contest, featuring the new RX family of 32-bit microcontrollers (MCUs) and software support environment provided by Renesas Electronics America and its Alliance Partner community. These include tools from partners including CMX Systems, IAR Systems, Micrium, Micron Technology, SEGGER, Rowebots and TotalPhase. The Renesas RX Design Contest provides an open, creative environment in which embedded engineers can showcase their skills in any type of design using an RX MCU. Starting October 13, 2010 to March 4, 2011, there will be 1,000 RX62N Renesas Demonstration Kits (RDKs) available for contestants. The use of the RDK is encouraged but not required. The contest will be coordinated across the North American, European and Asian regions. To join the competition, visit http://www.renesasrulz. com/rx-contest to register. The design entries will be available on the Renesas RX Design Contest website for audience comments and voting. In addition to recognition for the overall “best” designs, the Renesas RX Design Contest will offer weekly challenges and prizes. Renesas Electronics America will award the top three winners: $5,000 (first place); $3,000 (second place); and $1,000 (third place); and five honorable mentions receiving $500 each. Selections will be based on a scoring of technical merit, design originality, usefulness, cost effectiveness, documentation and public voting. Participating Alliance Partners also will present their own prize awards, based on criteria for their respective prizes. Final judging and the winner selections will be announced during a special ceremony at Embedded Systems Conference Silicon Valley 2011.

Enea Launches Machine to Machine (M2M) Competence Center

Enea has announced that in order to take full advantage of the opportunity presented by the rapid growth in the machine to machine (M2M) communications market, it has launched the Enea M2M Competence Center ( in Linköping, Sweden. Enea’s M2M Competence Center will offer a full range of hardware and software development consulting solutions, training and support. In addition, Enea provides a flexible M2M development platform that can be cus-

tomized to meet application requirements. M2M communication is a rapidly emerging application segment in which device nodes capture data or information from sensors, meters or other components, which is then transmitted over fixed or wireless networks to a computer system. The computer system may review and respond to the information itself or translate and forward the information on to other nodes or system operators for further action. M2M communication streamlines and accelerates business processes, lowers costs and improves organizational efficiencies. While M2M

is applicable to many markets, it has seen the widest adoption in building and industrial automation, supply chain management, monitoring and security and remote payment systems. The Enea M2M Competence Center has extensive experience in all aspects of the M2M topology including edge devices, communications technology and protocols, as well as IT-centric management systems. In addition, Enea’s background in real-time and highly reliable embedded devices uniquely positions the company to tackle the development of complex M2M systems. Enea experts can design and build entire

M2M systems, discrete parts of a system, perform system integration or execute testing and quality programs. In order jump start projects, Enea offers an extensible M2M development platform, which can be adapted to particular customer requirements.

Attached SCSI–2.1 Draft Standard Forwarded to INCITS

The SCSI Trade Association (STA) has announced that the draft standard of Serial Attached SCSI (SAS)–2.1 was forwarded to the International Committee

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at Closing Price 52 Week Low 52 Week High Market Cap

RTEC10 Index



Adlink Technology



















Interphase Corporation










Mercury Computer Systems





Performance Technologies





PLX Technology





RadiSys Corporation





Company Market Performance

Elma Electronic

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities.




for Information Technology Standards (INCITS), a committee under the direction of the American National Standards Institute (ANSI) for public review on September 16, 2010. INCITS is the primary organization for fostering the development of technology standards in the United States. The SAS–2.1 draft standard was developed by the T10 Committee, an INCITS Committee with the responsibility of developing SCSI standards. The earlier SAS–2.0 standard was divided into two separate standards: one for physical layers (SAS–2.1) and one for

SAS Protocol Layers (SPL). Minor revisions have also been included in this process. Nearly all second-generation SAS products were designed and implemented in accordance with SAS–2.1 and SPL standards, and as such, do not represent a new generation of SAS. Products implemented to the SAS–2.1 standard, now in the review process with expected publication early next year, will continue to be referenced as 6 Gbit/s SAS. The SPL standard was forwarded to INCITS on July 15, 2010 for public review.

MIPS Joins TSMC IP Alliance to Optimize MIPS IP Cores for TSMC Process Technology

MIPS Technologies has announced that it has joined the TSMC Soft IP Alliance Program to speed customers’ time-to-market. Through the Soft IP Program, TSMC is expected to provide specific design documents and technology information so that MIPS and other Alliance partners can optimize IP cores for TSMC’s process technologies. The companies will also collaborate on roadmap alignment to expedite IP readiness.

“The combination of TSMC’s foundry-leading technologies and manufacturing capability with MIPS Technologies’ soft IP cores will enable customers to gain early insight into the power, performance and area trade-offs inherent in their SoC designs. This is an increasingly critical factor in meeting time-to-market objectives. We are pleased to be able to deliver this important information to our customers to help them make the best possible decisions,” said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC.

Mini-, Nano- and Pico-ITX Showcase

Featuring the latest in Mino-, Nano- and Pico-ITX technologies NITX-315

USB Embedded Modem Modules

Ultra Low Power Nano-ITX Motherboard Ideal for low power embedded applications 1.0 GHz Intel® Atom™ Processor E640 Intel® Platform Controller Hub EG20T 1GB soldered DDR2 memory Gigabit Ethernet, SATA and USB PCI Express x1 and PCI Express Mini Card slot Dual display support

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Mini-ITX board, 64-bit VIA Nano™ E series CPU, available in both 1.6GHz and fanless 1.2GHz SKUs Hardware acceleration for VC1, MPEG-2, H.264 and WMV9 at 1080p DDR3 memory up to 8GB HDMI, VGA, LVDS, SATA, USB, COM, PCIe & GigaLAN port Windows 7, Windows Embedded Standard 7, XP, XPe, CE & Linux

VIA Technologies, Inc.

USB modems, in module or standalone form factor Linux, Windows and Mac O/S support -40C to +85C operating temperature (Module) Compact size: 1” x 1” x 0.2” (Module) USB 2.0 compatible up to 56K bps data rate, fax and voice AT command Transferable FCC68, CS03, CTR21 telecom certifications Global safety: IEC60950-1, IEC606011 (Medical) approved CE marking

Pico-ITX board, the smallest x86 full HD embedded board 1.2 GHz VIA Nano™ E Processor Ideal for mobile and intelligent devices, space-critical applications 1080P video hardware decoding acceleration in MPEG-2, VC1, WMV9, and H.264 GigaLAN/USB/VGA/HDMI/LVDS Supports digital I/O

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Colin McCracken & Paul Rosenfeld

FPGAs – The Logical Choice


he ability to customize logic has underpinned the electronics industry since the early days of the 74xx glue logic family. Whether for simple chip selects, shift registers, registers, or flip flops, these building blocks proved invaluable to designers in all parts of the market. A far cry from the automated environments of today, these popcorn 7400-series parts were arranged like Legos to implement 8-bit processing cores, buses, communications and I/O. Moore’s law advanced the design task from Karnaugh Maps to EDA tools, and the domain gradually shifted from board-level to chip-level design. The doubling of transistors every 18 months took us from small-scale integration (SSI) to medium- to large- to very large-scale integration (VLSI), and flexible gate array structures. One-time-programmable ICs and test vectors gave way to complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) that load their “brains” from serial flash firmware upon power-up, immersing us in a veritable alphabet soup of four letter acronyms. With easy field upgradability, advanced design tools and high-level “languages” like Verilog and VHDL, hardware design has evolved to resemble software coding. Programmable logic appeals equally to the few designing smart phones as well as the many designing wide ranges of small(er) volume non-consumer devices. How do these technological advances impact our small form factor corner of the world? Regardless of which 4-bit microcontroller or 64-bit RISC or x86 microprocessor architecture, CPLDs play a critical role in interfacing system buses to I/O—or, if you prefer the outside-looking-in perspective—how the real world can access processors. Easy-tointerface parallel buses required address decoding, FIFO buffers, interrupt- and DMA-generating logic, not to mention computational or control logic behind the analog front-ends. The next step up in terms of complexity is FPGAs with integrated RISC processor cores. Some of the FPGA vendors push their own integrated processor cores, with compilers and kernels, while others embed standard PowerPC or ARM cores in their chip offerings. Cores can also be in “soft” form (synthesizable Verilog or VHDL), which are merged and simulated with custom logic before being synthesized into gates. Configuration options can be selected prior to synthesis, giving a measure of flexibility. “Hard” cores are optimized at the transistor level, saving cost and die space while increasing speed and the gate count available for custom logic.



FPGA suppliers have created the impression that such smart devices will replace discreet microprocessors. Have no fear. This is nothing more than overzealous marketing hype. Even so, these chips remain quite useful for distributed control systems and smart I/O (dare we say “intelligent I/O?”). As parallel buses give way to high-speed serial bus topologies, design challenges are increasing while fewer devices are available that meet interface requirements. The acronym “SERDES” refers to the serialize / de-serialize nature of the point-to-point interconnect. This is a far cry from traditional multi-drop local buses. A SERDES PHY (physical layer) must be implemented to interface to the 1.25 GHz (2.5 Gbit/s) PCI Express link. This ain’t your mother’s FPGA. Some devices have not only the requisite PHY but also a bus bridge or a registered parallel bus interface behind it in “hardened” form. Otherwise designers need to integrate a Verilog or VHDL “socket” type of interface with their custom logic, and away they go. One downside for FPGAs is their use in stacking architectures, especially in sealed enclosures. The incremental power consumption over previous parallel buses is stark, reaching 0.51W or more. Although not a big deal for line-powered systems, every milliwatt counts for battery-powered devices, from handheld instruments to forklift HMIs to vehicle computers. Besides battery life, heat removal is a necessary design consideration. FPGAs can be “multi-bus” by connecting to both high-speed and low-speed buses, with internal circuits attached according to the data bandwidth needs. This approach is quite optimal, as interfacing low-speed I/O to PCIe is akin to sipping from a fire hose. Examples of low-speed buses include LPC (low pin count) Bus, SMBus (system management bus for x86) / I2C, and—yes, finally gaining popularity in the x86 space—the SPI bus (serial peripheral interface). Each of these takes very few pins, simplifying FPGA design tasks. Conserving board space is generally more important than minimizing cost in the smallest form factors. Rather than having myriad distributed timing circuits (analog or digital), separate bus and I/O transceivers, smart I/O controller chips, power sequencing logic, GPIOs or discreet CPLD for each section of a design, FPGAs are the logical choice to combine all these functions into a single component for I/O-oriented small form factor designs.

editor’s report Homing in on Power Management

Getting to Low Power Consumption Depends on the Right Data— and Using it. Data sheets don’t tell the whole story about processor power consumption. The details of power-saving modes, data on the state of execution and the needs of the application can lead to true power optimization. by Tom Williams, Editor-in-Chief


ith the proliferation of handheld and mobile devices, often used in conjunction with larger, server-based applications, and the spread of small, distributed devices that may be unattended for long periods of time, conserving power in embedded systems is definitely a topic that is on the front burner. Today’s embedded processors are being designed for minimum power consumption starting at the level of silicon process technology and going from there to the careful design of applications, the minimization of memory footprint, the optimization of clock speeds and more. The race by Intel to try to overtake ARM with its Atom family in the low power arena is being closely watched and with good reason. On the surface, putting a processor into a sleep mode for 37Ms may sound trivial, but if those periods of 37Ms cumulatively amount to 29 percent of the time an application is running, the power savings—and battery life—can be enormous. Thus modern processors are not



only designed to be inherently low power; they are also increasingly being designed with built-in power conservation features. These include the ability to adjust the speed of the clock for different parts of the CPU and the availability of “sleep” modes and “power down” modes that may turn off certain elements of the processor (Table 1). In addition, reducing memory size with efficient compilers and operating systems can also contribute significantly to power saving. The trick, however, is that since different CPU architectures and even variants within those architectures have a wide variety of power-saving mechanisms and features, knowing how and when to use them has become the job of the application developer. To do that job, he or she not only needs information about that particular processor’s power features and their capabilities, but also information about the current state of the system with regard to invoking those mechanisms. This involves information supplied to the programmer by the operating system as

well as a deep understanding of the needs of the application. For example, the EFM32 Gecko microcontroller family from Energy Micro is based on the ARM Cortex-M3 architecture, yet is available with a wide range of peripherals and memory options (Figure 1). This—as well as variants from other manufacturers—potentially presents the developer with a wide range of options as to what combination of elements can be put into sleep mode for what amount of time. Depending on the modes provided by the hardware manufacturer, such choices need input from the operating system as well. Included in the development tool suite for the Gecko family is an energyAware profiler that enables designers to perform real-time energy debugging directly on their system. According to John Carbone of Express Logic, the operating system is capable of providing information that the developer needs to make a decision on the use of a given processor’s power saving modes based on the needs of the application. What the RTOS does not provide are specific calls to invoke those modes. For one thing, the large number of variants in the implementation of such modes is so great that it would be impractical, and for another, using a given sleep or other mode is fairly trivial and mostly involves changing a bit in a control register. Knowledge about the details of each mode is also needed to effectively implement the application, but should be gained by reading the processor manual. Based on that understanding, along with data supplied by the RTOS, the developer can make valid decisions on how best to use those modes for a given application. For example, the Express Logic ThreadX RTOS is capable of helping a user manage scheduled events by supplying such information as the time remaining until the occurrence of the next scheduled event. This is particularly useful when the processor comes to a quiescent state where no tasks are running. At this point, the developer can consider whether it is a good idea to enter a sleep mode, which mode that should be, and for how

editor’s report

long. To assist in making this decision, the RTOS supplies information on how much time is available before the next task is scheduled to run. Note that this decision does not apply to random interrupts that may come in from the outside world. That is a different matter, but one which may also be partially addressed by the information supplied by the RTOS. ThreadX has a data structure that keeps track of all time-related deadlines and alarms. This information can be returned to the developer who can then decide how much sleep he can afford and at what level. “The general problem,” Carbone notes, “is that the deeper a sleep you go into, the more power you save, but the more cycles you waste awakening.” Having said that, he notes that the ARM Cortex-M3 architecture has some very efficient sleep modes that you can get into and out of very quickly. In such modes, the processor may be stopped but some of the timer and clock signals continue to run with other parts of the system—such as the bus and selected peripherals—turned off. A deeper mode, the “power down” mode, turns off most logic and has a greater restart latency that may not preserve the processor state and could add complexity to the recovery process. All these factors need to be weighed in terms of the application to optimize power saving while preserving performance. For example, repeatedly going into a sleep mode for short periods might be counterproductive given the recovery overhead. Here again, knowledge of the processor’s individual characteristics along with the timing information provided by the RTOS and an understanding of the application can help deliver that ultimate tweak to power consumption. This is also where processor designers add value. The ARM Cortex-M3, for example, has a wake-up interrupt controller (WIC) that can bring the CPU out of sleep mode in 12 to 18 cycles from sleep and deep sleep modes. These are details that one can’t easily find on a spec or data sheet but which provide definite strategic advantages in the battle for low power . . . providing the developer can take advantage of them.

Core and Memory ARM Cortex-M3 Processor Flash Memory (KB) 32/64/128

RAM Memory (9KB) 8/15/16

Debug Interface

Clock Management Memory Protection Unit DMA Controller

High Frequency Crystal Oscillator Low Frequency Crystal Oscillator

High Frequency RC Oscillator Low Frequency RC Oscillator

Watchdog Oscillator

Energy Management Voltage Regulator

Voltage Comparator

Power-on Reset

Brown-out Detector

32-bit bus Peripheral Reflex System

Serial Interfaces USART


3x Low Energy UART 2x


I/O Ports General Purpose I/O 85 pins

External Bus Interface

External Interrupts

Pin Reset

Timers and Triggers Timer/ Peripheral Counter Reflex 3x System Low Energy Real Time Timer Counter Pulse Counter Watchdog Timer 3x

Analog Interfaces ADC


Security AES

2x LCD Analog Controller Comparator 4x40 2x

Figure 1 As shown in one example of the extensive EFM32 Gecko MCU family from Energy Micro, there are many peripheral options available around the ARM Cortex-M3 core.

Knowing the recovery latency is essential because it will help determine which level of sleep to choose in a given situation. It probably does not make sense to enter a sleep mode for 300 microseconds, but may very well for 300Ms. However, one must also consider the latency in order to be able to time the wake-up interrupt so that the system is fully awake and ready for the scheduled task when it occurs. The information returned by ThreadX is how many ticks until the scheduled event from the current clock count. One final piece of the puzzle from the application’s point of view might be whimsically called the “Rip Van Winkle” question. And that is when the processor has been asleep for some period, it is not obvious to the application when it reawakens how long it has been asleep. There is also an RTOS routine that returns that information based on the fact that you cannot turn off all the clocks on the CPU. With that information the developer can update all the application-related timers so that they think the system has been running all the time. Three vital questions the operating system can answer are: 1) When is it

OK to go to sleep (nothing is running)? 2) For how long can I remain asleep? and 3) When I wake up, how long have I been asleep? All of these questions apply to scheduled tasks and not to random interrupts. However, there are cases involving random interrupts where latency may not be critical and in such cases this same information may be of use. This probably

Figure 2 The HiTex PowerScale module supports four probes in parallel capable of sampling two different power domains in any combination. The ACM probe (below) is capable of measuring very low currents directly on the processor pins. RTC MAGAZINE NOVEMBER 2010


editor’s report













Slow Clock












Power Down






TABLE 1 For a generic example processor, the relative effects of processor clock rate on power consumption in different modes. Source: Express Logic

does not apply to applications like cruise missiles where interrupts are coming thick and fast and there is no room for delay. However, there may be applications where random interrupts do occur but are relatively infrequent and do not require ultimate fast response. Here there may be time to wake up on the interrupt, go through the wake procedure and still have time to service that interrupt. This is entirely an application decision. All interrupts incur some latency such as for context switching, but with today’s fast processors, such latencies have become less critical. Here, one may also weigh the added cost of a sufficiently fast CPU versus the potential power savings and again against the added overall power consumption of the faster processor. Of course, engineering at this level also cries out for means to accurately measure and evaluate results. In a recent development, HiTex Development Tools has developed a probe called the PowerScale,


Untitled-3 1


which provides active current measurement and can connect to a PC with a USB cable (Figure 2). The probe can measure in a range of 1 mA to 1A to a maximum of 58V, and in another range from 200nA to 500 nA with a voltage drop of only 0.1V, which is small enough not to affect the operation of the processor. A graphical user interface provides display of current and power over a measured time segment and statistical information like how long the CPU was in sleep mode. Other companies such as IAR Systems are developing similar probe technology, as well as possibly partnering with HiTex, with the aim of integrating power measurements with their debugging tools and eventually providing the ability to correlate power consumption with instruction execution. Microprocessors and microcontrollers appear in product literature with competing specifications for power consumption, which are not to be dismissed

lightly. However, wringing the real potential for power saving requires concentrated engineering effort that requires information from several sources. One is the actual functionality of power-saving modes associated with the different processor architectures. Another is information about the state of the program in terms of the time available for sleep modes or other modes in regard to scheduled tasks and under certain conditions to interrupts. The third source is an understanding of the capabilities and needs of the application and how it can best be served by the optimal use of power-saving strategies. Express Logic San Diego, CA. (858) 613-6640. []. HiTex Development Tools Irvine, CA. (949) 863-0302. []. IAR Systems Foster City, CA. (650) 287-4250. []. Energy Micro Nydalen, Norway. +47 23 00 98 00. [].

11/11/09 3:45:15 PM

Technology in


ARM and Power Modules

Power Architecture Technology Enables Differentiated Solution for LTE The demands of the next-generation mobile telecom infrastructure are daunting. They demand the utmost of the silicon that will support them. by Fawzi Behmann,


ext messages sent and received via mobile devices have exceeded the population of the planet. The emergence of the iPhone and other Internet and multimedia-enabled smart phones has shown the potential of mobile data services beyond that of simple text messaging and emails, and has dramatically driven exponential mobile data traffic growth. The average smart phone user generates 10 times the amount of traffic generated by the average non-smart phone user. As a result, mobile data traffic is growing at a rate of 40% per year. Currently, some service providers are challenged in building out their 3G wireless infrastructure quickly enough to keep up with the demand generated by smart phone users. Hence, the aggressive industry push for Long-Term Evolution (LTE) to accommodate huge traffic growth and for LTE to become essential to take mobile broadband to the mass market. According to the Global mobile Suppliers Association (GSA), as of Q2 2010 the mobile market has reached 4.96 billion subscriptions. GSM subscriptions (including WCDMA-HSPA) now stand at almost 90% of all mobile technologies (Figure 1). As of Q2 2010, systems evolu-






GSM family subscriptions

>4.45 billion including more than 529 million WCDMA subscriptions (including HSPA)


(c) GSA - Global mobile Suppliers Association

Figure 1 Mobile market share worldwide: Quarter 2, 2010.

tion to 3G are shown in the Figure 2. The wireless access market segment is dominated today by the realities of Long-Term Evolution. Many companies are strongly committed to LTE and believe that it offers simplified technology, better scalability and ultimately a better user experience for next-generation mobile broadband. From its conception, LTE was intended to support downlink bandwidths of up to 300 Mbit/s. Today some claim it may reach as much as 1 Gbit/s. This level of performance is essential to support cur-

rent and future mobile applications such as Internet browsing, interactive TV, mobile video blogging, etc. Mobile broadband subscriptions are projected to be 2.7 billion by 2014. Considering that in 2009 packet data consumed nearly 20 times the bandwidth of voice data, 2.7 billion users implies a required global wireless network capacity measured in trillions of packets per second. New classes of multimedia applications are emerging that will doubtless demand even greater bandwidth. This explosive growth rate is fueling an intense

technology in context

effort to rapidly provide more network throughput, while controlling the costs of infrastructure (e.g., space, cooling and power.) This intense effort strongly affects both LTE infrastructure providers and silicon providers. Carriers are considering LTE deployments in emerging regions where mobile Internet is becoming a real fixed line alternative. LTE is likely to begin its life cycle with data cards and connectivity modems. Upgrade to existing 3G networks will lead to a smoother transition to LTE. LTE will provide the reduced latency, increased peak bandwidth and greater network capacity required for the advanced voice, data and video applications made possible by the latest mobile phones. HD video, which the iPhone 4 supports, is only the latest in a stream of new applications that will stretch 3G networks to the breaking point. LTE is backward compatible with existing solutions, and it will meet the long-term needs of carriers and their customers for high-speed data traffic supporting Internet browsing, voice and video. For LTE infrastructure providers, the realities of the market segment mean that they must aggressively define system architectures that will simplify and reduce the cost of network roll-out and management. Therefore, LTE providers require that the costs of both silicon—in terms of throughput-per-unit cost—and software development must decrease dramatically. Furthermore, power constraints are a primary consideration imposed by densely packed infrastructure components. These cost, programmability and power requirements directly affect silicon providers. For silicon providers, these realities mean enabling more processing in parallel using multicore systems. In addition to the bandwidth and power requirements, the complexity of per-packet processing required to support advanced network and application features continues to increase, demanding increasingly powerful processor cores to sustain system throughput goals. For these reasons, the LTE market segment views both system throughput and single-thread processor performance as key metrics. As a result, the silicon roadmap to support LTE must satisfy extremely rigorous demands for high levels

Q2 10 market share






3GPP Core Network WCDMA


EDGE Evolution

CDMA2000 1x First Step into 3G




cdma 9.6%

CDMA2000 1x EV/DO Rev0 3G phase 1



others 0.7%

Evolved 3G

Figure 2 Growth and consolidation of wireless systems toward 3G. Source: GSA

of on-chip and chip-to-chip integration within tight power budgets. To meet these demands, there is a need for a balanced SoC architectural approach consisting of cores, cache memories, I/O and accelerators to achieve a specific system throughput within a tight budget. The current generation of chips integrates as many as eight high-performance, highly efficient processor cores on a device along with various networking-specific hardware accelerators. The level of integration is expected to continue to increase throughout the next decade. In addition to requirements for high throughput, high single-thread performance and managed power consumption, there is also a need for high-quality tools, system software and networking stacks. Without these, LTE providers cannot respond quickly to the growth in numbers of advanced wireless devices in use and the accompanying rapid emergence of new mobile applications. Only a potent combination of silicon and software will enable LTE infrastructure providers to compete and win in their market segment.

LTE Deployment

2011 will be the year when LTE goes live in a big way, as Verizon in the United States and DoCoMo in Japan will begin wide-scale roll-outs by the end of 2010. 132 networks have reported trials or plans to launch LTE commercially, 32 more than the end of 2009. Verizon has also hinted at the availability of LTE-based handsets by May 2011. AT&T plans to begin LTE tri-

als in the next few months and will start commercial service in 2011. 3GPP LTE is an evolution of the GSM/UMTS (comprising WCDMA, HSPA), and specifies the next-generation mobile broadband access system. LTE will be conforming to Release 9 of the 3GPP (Figure 3). Specification for LTE downlink speed is 150 Mbit/s compared to 21-84 Mbit/s for HSPA+, 14.4 Mbit/s for HSPA and 384 Kbit/s for 3G/WCDMA. According to ITU’s definition of 4G, requirements include average downlink speeds of 100 Mbit/s in the wide area network, and up to 1 Gbit/s for local access or low mobility scenarios. Next-generation LTE (LTE Evolution) will address the target of 1 Gbit/s downlink speed. Throughout 2009, 3GPP has worked on a study to identify the LTE improvements required by ITU IMT-Advanced. A major reason for aligning LTE with IMT-Advanced is to ensure that today’s deployed LTE mobile networks provide an evolutionary path toward many years of commercial operation. LTE utilizes a new state-of-the-art radio air interface technology known as Orthogonal Frequency. Division Multiple Access (OFDMA) provides several key benefits including significantly increased peak data rates, increased cell edge performance, reduced latency, scalable bandwidth, coexistence with GSM/EDGE/UMTS systems, reduced CAPEX and OPEX. LTE is also scalable to allow operation in a wide range of spectrum bandwidths, from 1.4 - 20 MHz, using both RTC MAGAZINE NOVEMBER 2010


technology in context

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11/3/10 10:58:13 AM

Frequency Division Duplex (FDD) and Time Division Duplex (TDD) modes of operation, thus providing flexibility to suit any carrier’s existing or future frequency allocation globally.

Power Architecture Differentiated Solution for LTE

Requirements for LTE infrastructure providers include a system architecture that will simplify and reduce the cost of network roll-out and management. This implies that the costs of both silicon and software development must decrease dramatically. In addition, power constraints become a primary consideration imposed by densely packed infrastructure components. The cost, programmability and power requirements directly affect silicon providers. For silicon providers, this translates to enabling more processing in parallel using multicore systems. In addition to the bandwidth and power requirements, advanced network and application features continue to increase, demanding increasingly powerful processor cores to sustain system throughput goals. For these reasons, LTE views both system throughput and single-thread processor performance as key metrics. As a result, the silicon roadmap to support LTE must satisfy extremely rigorous demands for high levels of on-chip and chip-to-chip integration within tight power budgets. The requirements of LTE are best satisfied using a systems-oriented solution in the form of a heterogeneous systemon-chip (SoC), including a scalable set of multicore processors and application-specific accelerators such as pattern matching engines, security engines, packet process-

ing engines and other features to improve overall system performance, programmability and power efficiency. This type of solution requires that the processor cores be designed from the start to integrate well, to scale to meet performance requirements in multicore configurations, and to be power efficient. A technology offering a key advantage is embedded virtualization, which provides I/O virtualization to enable sharing and management of hardware accelerators. This is an example of the sophistication and flexibility of sharing that’s enabled by the very complete hypervisor and virtualization architecture in Power ISA 2.06. The hypervisor is a true hardwaresupported operating mode that ensures protection of the virtual kernel from guest operating systems. Thus, the hypervisor allows different software systems to run on different cores at the same time with high integrity. This approach allows each software system and its associated private hardware resources to be protected from interference from the others. While different systems are insulated from direct interactions, software systems can establish communication mechanisms with other software systems in a controlled and reliable manner. A hypervisor alone does not guarantee multicore efficiencies. Heterogeneous multicore processing efficiency requires additional hardware support from the processor core. LTE requires numerous system-wide statistics to be maintained across many threads of computation. If such counters are implemented as shared memory locations, then access to them must be controlled to prevent race condi-

technology in context

tions. In software, this synchronization can lead to serious performance degradation because of the time required to obtain a semaphore before accessing and updating the statistics counter. Furthermore, many interactions with hardware accelerators are performance-using accesses to memory mapped registers, which can be time-consuming if the interactions must be done through a read-modify-write transaction to these registers. Power Architecture technology supports efficient interaction with shared statistics counters and with hardware accelerators using decorated load and store instructions. These instructions allow an efficient three-operand (address, data, command) format that replaces a series of transactions between cores and memory or between cores and accelerators with highly optimized transactions. Power Architecture cores provide important capabilities for dynamic power management. Some of these are enabled internally in the core. For example, it is common for execution units in the processor pipeline to be power-gated when idle. Furthermore, Power Architecture cores offer software-selectable power-saving modes. These power-saving modes reduce function in other areas, with some modes limiting cache and bus-snooping operations, and some modes turning off all functional units except for interrupts. These techniques are an effective way to reduce power, because they reduce switching on the chip and give operating systems a means to exercise dynamic power management. But sometimes only the application software running on the processor has the knowledge required to decide when power can be managed without affecting performance. Recognizing this fact, Power Architecture technology provides application software with a means for power-optimized solutions through the wait instruction (Power ISA 2.06). This instruction allows software to initiate power savings when it is known that there is no work to do until the next interrupt. With this instruction, power savings can now be achieved through user-mode code. This feature is well matched to the requirements of the LTE market segment, which requires that total SoC power be managed effectively. The combination of

CPU power-savings modes, the wait instruction and the ability to wake on an interrupt has been demonstrated to achieve deep sleep power savings with wake up on external event—with no packet loss.

Quality Software

A large portion of the time required to develop products using embedded multicore processors is spent on testing and optimizing application software. Sophisticated heterogeneous SoCs require powerful debug and runtime support as well. To meet that need, Power Architecture multicore SoCs support standardized debug, performance monitors, load spreading, device virtualization and virtualization with real applications. But providing tools and runtime capabilities is only part of the equation. Time-to-market is greatly affected by software development effort as well. The Power Architecture community is addressing this impact by providing vertical solutions for market segments such as the LTE segment. For example, Freescale’s VortiQa solutions speed development by providing fully integrated, architecturally compatible application software. VortiQa software is optimized to take full advantage of Freescale’s heterogeneous SoC architectures, including pattern matching engines, security accelerators, data path accelerants and other features, thereby boosting performance in embedded systems. It eliminates the time-consuming task of creating application-optimal mapping of functions and core assignments for asymmetric multiprocessing (AMP), symmetric multiprocessing (SMP) and hybrid AMP+SMP configurations. In addition to vertical solutions that enhance time-to-market, the Power Architecture hypervisor further provides a solid foundation for system software in heterogeneous SoC environments, because it allows an existing embedded operating system to run in guest state or bare-metal state with at most minor changes. Customers can therefore quickly bring up their operating system and associated runtime libraries in a configuration that is optimized for their application, a key requirement for the LTE market segment. [].

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11/3/10 10:48:30 AM

Technology in


ARM and Power Modules

Appropriately ARMing the Embedded World Thanks to the availability of standard operating systems, the well-known advantages in power efficiency and a wide selection of performance options, the ARM architecture is rising to challenge the dominance of x86 in the small module arena. by Susan Wooley, Micro/sys




60 50 40


or years Intel x86 was the go-to processor for low-end to mid-range board-level embedded designers, but no longer is this the case. More and more of these designers are choosing ARMbased CPU boards for their embedded system needs. So it begs the question, why? Have the needs of these embedded users changed? Absolutely not, in fact the core needs—simplicity and ease of use, low power and application appropriate processors—are more paramount than ever. Why is it then that the de facto “PC/104” embedded users are making the switch to ARM? For years, Intel’s x86 line of processors aligned well with the needs of “work horse” embedded applications. Recently, Intel has neglected these needs while pursuing the glitz and glam of the ever increasing ultra high-end performance needed by PCs and servers. On the other hand, since its inception, ARM has stayed singularly focused on efficient, applicationappropriate processors well-suited for a broad range of embedded applications. Now with the emergence of user-friendly software on the ARM platform coupled with the void of appropriate lower end Intel processors, ARM technology makes the most compelling argument for what used to be “PC/104” applications. ARM’s breadth of processor performance categories makes it the appropriate choice for the eternal em-

30 20 10 0

ARM ARM ARM ULV Atom Pentium M Cortex-M Cortex-R Cortex-A Pentium III

Core2 Duo


Figure 1 Processor Power Consumption of Typical SBCs.

bedded reasons: ease of use, low power and broad choice of processor performance.

Ease: Operating System Flexibility

ARM has leveled the operating system playing field with its variety of OS support from sophisticated to simple. As DOS has begun to disappear, most mid-range system designers today have come to prefer Linux and WindowsCE, which are widely available on the ARM platform. These OSs provide compact and efficient kernels with images that have fast boot times and small footprints in flash, which are ideal for

“PC/104” applications. In addition to these, BSPs for well-respected RTOS systems like VxWorks, QNX or Integrity, as well as new emerging OSs like Android, are readily available. Now that the same popular, easyto-use and well-supported operating systems and tool chains of the embedded PC world are available for ARM single board computers, ARM processors are more attractive to the embedded system designers in this segment of the COTS market. At the same time, a strong selection of microcontroller development platforms and tool chains such as Keil, IAR and GNU tools has been introduced. The most

technology in context

Figure 2 Micro/sys SBC1651 i.MX515 ARM Cortex-A8 Processor Board.

significant attribute of these tool chains is their ease of use. They are intuitive, compact and conceptually similar, so adapting to a new microcontroller tool chain has become a second nature skill. With these affordable tools, designers can be confident that an easy-to-use OS or runtime environment is readily available regardless of their ARM CPU choice. Selecting the right operating system or development platform is critical to producing the most cost-efficient embedded system. One important decision in achieving efficiency is specifying the right software environment for an application. There is a tendency to select an operating environment that is overkill for the application. The unfortunate impact of such a selection is that the OEM application is burdened with unnecessary hardware costs to support the OS for the entire life of the OEM product. For example, if you have no display and are just switching a few LEDs on and off and reading some registers to sense when a motor should be turned on and off, your application might be considered “low level.” If you were to seek out a WindowsXP environment for this application, you would soon discover your CPU options are only “high performance” CPU boards requiring 10 to 25 watts of power. This means your final application will require larger enclosures, more cooling mechanisms to exhaust the heat generated by the CPU and more memory to accommodate the software, not to mention an overly complex system. The outcome: each OEM system manufactured carries with it more heat, power, memory and system costs resulting from an operat-



ing system requiring excessive hardware overhead. Granted, using such a platform provides access to some very powerful fullfeatured PC data acquisition software packages and graphical interfaces with drop-and-click programming to ease software development. Prudent system designers must determine if the anticipated savings in software development costs will offset the burden of the associated hardware, which can run several hundred dollars per system. With the abundance of software tools on the market today, this becomes a difficult justification for most OEM applications. The exciting opportunity offered by ARM-based single board computers is the advantage of choice when developing an embedded system.

Power: Conservation and Efficiency

Power consumption is on the mind of everyone in this “green” era. For the “work horse” embedded system designer, power has always been a serious consideration as the typical environments are not as userfriendly as an office or environmentally controlled facility. Embedded applications often operate in environments where power is limited and the need for battery support is critical. In other instances battery support may not be the hurdle, while heat is, and using power generates heat and the more power used the more heat generated. The fundamental difference between an ARM processor and an Intel-based PC processor is buried in the silicon upon which the CPU core is built. Intel’s approach is based on millions of transistors, each arranged in a complex architecture (CISA) and designed to optimize maximum functionality while the ARM’s architecture is about efficiency, using a smaller number of transistors in a more targeted, application-specific approach (RISC). For any given level of performance, a RISC processor has fewer transistors consuming less power than its Intel equivalent CPU. It is true; with fewer transistors the RISC performance is not equivalent to the CISA performance. While one could debate, benchmark and compare the two CPU performances forever, the argument is a mute point as long as the given pro-

cessor possesses the required compute power for the application at hand. Unlike consumers purchasing a laptop based solely on its GHz performance with no constraints on power consumption, an industrial embedded system is judged on the sum of it “parts” from power consumption to operating temperature to throughput, where tradeoffs are required to bring the ideal system together. Throughput ends up being relegated to “ballpark” rather than absolute. This is especially true because of the dramatic difference in required power for similar performance. Figure 1 compares the relative power usage of ARM Cortex processors to the “embedded” Intel processors. Intel’s lowest-power processor, the Atom, still consumes twice as much power as the ARM Cortex-A. When you consider the functionality, though, of an ARM Cortex-A processor board such as the Micro/sys SBC1651 i.MX515 ARM CortexA8 (Figure 2), functionality has not been sacrificed for low power; it still offers all the same fully featured suite of I/O as the Atom, if not more.

Performance: Processor Breadth

The third important reason to use an ARM processor is to take advantage of the sheer simplicity and elegance that comes from designing an embedded system with the most appropriate processor. ARM’s processor breadth embodies ease, power and performance all in one. ARM technology enables embedded designers to choose the processor with the appropriate mix of power and functionality rather than be forced to select the “runt of the litter” out of a family of power-house processors for what is essentially a low- or mid-level application. During the emergence of the PC, year over year performance improvements lulled embedded designers into the “bigger and faster is better” mentality. We’ve been awakened though by a tough reality check, as we’ve come to realize that with each new release, Intel has “slashed and burned” (EOL’ed) all of the low- and midrange processors that have performed so ideally in “PC/104” embedded systems. The applications that were well-matched with 186, 386 and 486 processors from Intel’s line, are now being forced to fig-

technology in context



ARM Processors


Cortex Processors

Cortex Processors Cortex-A15 Cortex-A9

Performance Functionality

ure out how to put a 1 GHz CPU into a slot once occupied by a 25 MHz DOS machine. When you add on the excess memory, excess number crunching and system speed now required by Intel processors, the “bigger and faster is better� mentality becomes the greater burden and the greater inefficiency. Whereas Intel’s processors are all 1 GHz and higher, ARM processors service separate distinct tracks targeting “lowend,� “mid-range,� and “high-end� applications (Figure 3). ARM has no corner on the market against the EOL of chips; however, they do maintain an application-appropriate roadmap for each level of performance with product updates and revisions. Although the needs of the “PC/104� embedded user have not changed, to accomplish the ideal balance of power, performance and ease, system designers are faced with a growing number of tradeoffs. Is the cost burden of more sophisticated PC-like software warranted? Can your system accommodate the added power and heat generated from GHz performance? Do you want to stuff a power-house proces-

Cortex-A8 Cortex-A5 Cortex-R4


Cortex-M4 ARM9

Cortex-M3 Cortex-M1


Cortex-M0 Capability

Figure 3 ARM Processors. Source: ARM

sor (and the baggage it brings) into a simple application instead of upgrading your software from DOS to the more popular Linux or WinCE embedded platforms? These and other considerations are real factors and sometimes the answers will be “yes,� but more often the answers are “no.� When

this is the case, ARM technology provides the most appropriate solution. Micro/sys Montrose, CA. (818) 244-4600. [].

Extreme Environment Barebones ‘™nj”‘ƤŽ‡ Â?–‡Ž̞–‘Â?Ěż‘Â?–”‘Ž‘š &ĂŜůĞĆ?Ć?Ç Ĺ?ƚŚͲϰϏΣʹϳϏΣĹ˝Ć‰ÄžĆŒÄ‚Ć&#x;ĹśĹ?ĆšÄžĹľĆ‰ÄžĆŒÄ‚ĆšĆľĆŒÄžĆŒÄ‚ĹśĹ?Ğ͘ /ĹśÄ?ĆŒÄžÄšĹ?Ä?ůLJÄ?ŽžƉĂÄ?ĆšĂŜĚĨƾůůÄ¨ÄžÄ‚ĆšĆľĆŒÄžÄšÍ–ŜŽÄ?Ĺ˝ĹľĆ‰ĆŒĹ˝ĹľĹ?Ć?ÄžĆ?͘

High-End IntelÂŽ Core™2 Duo with PCI Expansion &ĂŜůĞĆ?Ć?Ĺ˝Ć‰ÄžĆŒÄ‚Ć&#x;ŽŜ͖Ç Ĺ?ƚŚĆ?ƚĂŜĚĆ?ͲϰϏΣʹϳϏΣĆšÄžĹľĆ‰ÄžĆŒÄ‚ĆšĆľĆŒÄžĆŒÄ‚ĹśĹ?Ğ͘ tĹ?ĚĞĆŒÄ‚ĹśĹ?ÄžŽĨ/ÍŹKžĂŏĞĆ?Ä¨Ĺ˝ĆŒÄ‚ŇĞdžĹ?Ä?ůĞ͕ĆŒĆľĹ?Ĺ?ĞĚĹ?njĞĚƉůĂƞĹ˝ĆŒĹľÍ˜


Learn More > Š 2010 Logic Supply, Inc. All products and company names listed are trademarks or trade names of their respective companies.

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10/8/10 9:50:23 AM RTC MAGAZINE NOVEMBER 2010


connected Network Convergence

The Internet of Things and the Convergence of Networks The use of IP to communicate with and control small devices and sensors opens the way for the convergence of large, IT-oriented networks with realtime and specialized networked applications. The synergy of the access and potential data exchange opens huge new possibilities. by S  tamatis Karnouskos, JP Vasseur, Patrick Wetterwald, Jerald Martocci, Ted Humpal and Ming Zhu, The IPSO Alliance


ccording to the vision of the Internet of Things, billions of devices will be connected, interacting with each other and with enterprise systems, eventually blurring further the line between the physical and virtual world. We are still at the dawn of this era, but very soon consumers will be connected not only to their friends and family, but will be able to interact in a ubiquitous way with almost any aspect of the physical world such as buildings, houses and cars. The Internet Protocol Suite (IP) has already played a key role in the convergence of media and is expected to empower the Internet of Things Era, for example in commercial buildings—an ecosystem of ubiquitous heterogeneous devices, people and systems that will interact in real time. A migration toward a full IP-enabled building is already underway, as key business and technology enablers such as cost savings compared to current technologies become more compelling. A sense of the potential of the Internet of Things can be shown by the example of a commercial building, which can be applied to many other areas. When we enter office buildings, hotels, hospitals, retail stores or theatres, we seldom think about how they work. We just expect that they



will work and that we will expect to feel comfortable inside. With the trends toward smart infrastructure, new technologies are being considered to make the buildings more responsive to our needs and to interact with us in real time and adjust to our customized comfort and personal preferences. To understand what makes it all work, let’s first review the systems behind today’s commercial buildings: Business Systems (IT), Building Management System (BMS) and Specialty Systems. BMS systems and specialty systems have the potential to integrate with IP business systems leading to a vision of the “converged” network in the future as shown in Figure 1.

Coexisting Networked Systems

Business systems describe mainly the IP infrastructure such as routers and switches that permeate the interior of a building and the associated IT applications, like document management, Internet access, paging, texting, etc., that are used to run any business. New dataintensive applications such as VoIP and IP video cameras are pushing the IP network toward more reliable and real-time behavior. High reliability and real-time performance are necessary ingredients

for building management and specialty systems, thereby further endorsing the convergence of these systems. Enterprise-wide building management systems predate IP systems and have been installed in commercial buildings since the 1970s. While these systems are widely utilized and understood by building personnel in a company’s facility management department or corporate services, they are often transparent to most building occupants. These systems are designed and installed to increase occupant comfort while minimizing overall energy usage. The BMS will monitor indoor and outdoor environmental conditions and automatically control the indoor environment to match the selected energy and comfort profiles requested by the users. These systems control the core of any building in terms of heating, ventilation and air-conditioning (HVAC), lighting and elevator systems. Building access, security, smoke control and fire monitoring features are also deployed to increase the safety level of the building occupants. BMS systems were deployed as proprietary bundled hardware and software solutions up until the mid-1990s, when two open building automation and control network protocols, BACnet and LON,

technology connected


IT: application domain includes email, document management and Internet access, paging, and texting


BMS: designed to monitor and control thousands of sensors and actuators installed in commercial buildings


Vertical Market Specific

Figure 1

The Convergence of Commercial Building Systems can serve as an example for the convergence of other control and specialty networks with IP-based business systems.

Application Servers

User Interface (Enterprise Network, CAT-5)

IP Switch

Building Controller

(Field Bus, EIA-485)

were developed within the industry and fostered interoperability of the software objects. In the first decade of the 2000s, systems started to support native Web services in the network control layer of the architecture, making the systems able to serve HTML and support other Web technologies such as Obix and BACnet Web services. These developments have lead to a convergence of hardware platforms and an explosion of software interoperability. It is now possible to choose from a wide range of third-party software applications that can consume data from most major BMS systems. These days most BMS vendors utilize Ethernet IP running BACnet/IP or LON/IP for enterprise data, and twisted-pair for control network communications in the lower layers of the architecture. The introduction of IPbased wireless sensor networks using, for example, 6LoWPAN and ROLL technologies, will likely further integrate building systems and IP business system networks. Today, most BMS are highly interoperable with most building equipment manufacturers. An example of the classic BMS system is depicted in Figure 2. A third kind of enterprise-wide system has emerged in certain markets in the past decade. These consist of a suite of synergistic applications for a selected market segment. As an example, if we look at the healthcare market, we see that hospitals have myriad custom-made applications that need to be readily available to doctors and patients across the enterprise. Medical records, clinician collaboration, outcome improvement, prescriptions, as well as medication tracking and costing are but a few of the widely used applications needing to be delivered pervasively across the site. Patient and staff tracking, medical telemetry and the real-time view of a hospital’s information to the backend systems are new promising applications entering the arena. Mobile access to all this data needs to be readily available to the healthcare staff for patient care through host

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Figure 2 Classical Building Management System.



technology connected

Security Voice Telephony




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Care Delivery Processes (Info Availability, Clinician Collaboration, Outcome Improvement, Cost Containment, Location Tracking, etc.) Advanced Clinical Applications (Charting, Critical Care Systems, Medication Administration, etc.)

Figure 3 An application running on an IP network in the healthcare market coexists with building management and normal IP applications. BUILDING SYSTEMS


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Figure 4 Convergence of the networks and applications onto a single IP-based network.

devices called carts-on-wheels (COWs). Similarly also in other domains, the timely acquisition, processing and actuation of information linking the business and physical world is underway.

Building System Convergence

The overlay of the three systems functionality is depicted in Figure 3. While these systems could cohabitate on the IP network as independent applications as is currently often the case, there is further synergy available by melding



reliable communication network clearly makes more sense than supporting three independent networks. Hence, the convergence of such networks is in process as shown in Figure 4. As illustrated by the building example, systems that traditionally run independently to support a building’s operation are now being interconnected. Such connection raises the questions on why some of these devices have to be separate, and the possibility of multi-function devices that merge the existing separate devices. The traditional system dividing line is blurred as the information needs and technology capability converges. For example, people traditionally search for information on a computer, but now people also do that with their phones, their iPads, and very soon, they will be able to find real-time information from their in-home display panels such as their refrigerator panel or their home energy management system panel.

these separate applications into a cohesive set. For example, facility alarms could be directed to facilities personnel using SMS texting, email, instant messaging and similar applications. The energy management system might interrogate the healthcare location tracking subsystem to determine room occupancy before setting temperature set points. The IP data center may interoperate with the cooling systems to provide reliable IP server farms with minimal energy impact. The installation and maintenance cost savings of a single

Cost benefits in operational efficiency for the three systems to converge are compelling. Some studies show that converged IP and BMS systems will eliminate standalone gateways by ~50%, reduce installation and integration cost by ~20%, decrease energy cost by ~20%, and reduce operation and maintenance cost by ~30%. We can also look back at voice integration onto data in the past decade for the overall cost considerations. Just as voice data becomes a marginal cost consideration on a converged network, incremental application support on a converged network provides significant cost savings when maintenance, upgrade, changeover, remote monitoring, dynamic real-time response and other operational management aspects are taken into consideration. Reliability and real-time performance are necessary ingredients for building management and specialty systems, and the increased ability of IT systems to support reliability and real time further endorses the convergence of these systems. In a user-centric digitally connected world, more real-time response will be required across geographical building locations. An IP-based system that can meet such demands provides an affordable and feasible solution.

technology connected

The Internet of Things increasingly consists of IP smart objects, which can be defined as small micro-electronic devices that consist of a communication device, typically a low-power radio, a small microprocessor and a sensor or actuator. New IP protocols and technologies are being developed specifically for IP smart objects such as sensors and actuators used in buildings, factories, smart cities, etc. These technologies allow for efficient use of the network and enable devices to expose resources and capabilities that have historically been inaccessible to other network participants. With efficient compression to address the limited bandwidth of lower speed media often used at the edge, sophisticated routing is able to take into account the unique characteristics of these devicelevel networks. Thus IP can reach down to the device level while addressing the unique issues associated with the edge devices. The IETF 6LoWPAN Working Group has specified mechanisms to allow for such header compression and other mechanisms (e.g. fragmentation of large packets). Furthermore, the 6LoWPAN technology can also help in the convergence of legacy twisted pair into the IPv6 infrastructure. The new routing protocol specified for IP smart objects (called RPL) has been designed by the IETF ROLL Working Group. In addition, there is a lot happening with the application layer in standardization that will make IP more and more useful in building automation. Here are a few examples: • The OASIS organization’s oBIX (Open Building Information Exchange) v1.1 is being completed and includes a compact binary payload format useful with Web services. • BACnet, which originated in 1987, is “a data communication protocol for building automation and control networks.” BACnet is a protocol and it makes possible the interconnection of different vendors’ equipment that uses BACnet. It is now also working on integrating IPv6 support. • IETF CoRE, which is an Internet Engineering Task Force’s working group on Constrained RESTful Environments, is working on lightweight security bootstrapping and Web service optimizations for building automation.

This CoRE working group will define a framework for a limited class of applications: those that deal with the manipulation of simple resources on constrained networks. This includes applications to monitor simple sensor (e.g. temperature sensors) to control actuators (e.g. light switches), and to manage devices. • The World Wide Web Consortium (W3C) has worked on standardizing compact XML representations with EXI (Efficient XML Interchange). EXI brings significantly improved performance and reduced bandwidth requirements compared to regular eXtended Markup Language (XML). The notion of network convergence using IP is fundamental and relies on the use of a common multi-service IP network supporting a wide range of applications and services. This not only means that such networks are conducive to fostering innovation, but it also leads to dramatically reduced overall cost and complexity in contrast with myriad incompatible, specialized networks interconnected by hard-to-manage gateways. History speaks for itself: the IP protocol that was invented about 30 years ago and used to accommodate slow file transfers and remote terminal control is now used to carry an impressive and fast-growing set of applications and services with a variety of constraints and network requirements. Thanks to its layered architecture, the IP protocol suite has been enriched with a number of new advanced features and capabilities over the past three decades: • Multicast: Technology allowing for sending data traffic to a set of hosts while minimizing traffic replication in the network so as to save network resource usage. For example, you can think of this as a one-to-many communication method. • VPN: Virtual Private Networks can be built on top of a common IP infrastructure offering a complete isolation between the VPN with technologies such as VLANs, MPLS VPNs. You are likely to have used this technology when you log onto your company’s computer network remotely from home or hotels.

• Quality of Service (QoS): Is the ability to provide a different priority to different applications, users, or data flows, or to guarantee a certain level of performance to a data flow. For example, an application itself can indicate the required priority of the message as they are routed over the IP network. A number of IP-based technologies have been developed to truly support a wide variety of qualities of service: IP packets are “colored” when entering the network or by the application itself to indicate the required level of QoS, and then they are routed in the network and handled so as to meet the SLA (Service Level Agreement) thanks to scheduling and congestion avoidance techniques. Current QoS technologies allow for the support of real-time application with tight SLA (Service Level Agreement) constraints. For example, in a converged BMS and IT network in a building, a fire alarm message would take precedence over email traffic. • Reliability: A number of techniques have been developed to provide an extremely high level of reliability thanks to built-in redundancy, the ability to quickly (in a few dozens of millisecond) re-compute a route should a network element fail in the network and so on. In other words, the network can intelligently and autonomously reconfigure an alternative route if the first one should fail. • Security: IP networks can be highly secure. A number of technologies have been developed over the years to ensure authentication, authorization, privacy, support encryption, avoid Denial of Service (DoS) attacks, etc., just to name a few. Thanks to the development of these IP-based technologies, it has become possible to share a common IP network in support of vast numbers of applications having a variety of constraints in terms of quality of service, security, VPNs, reliability and more. IPSO Alliance [].



technology in

systems OpenVPX Part 2

Navigating OpenVPX: Developing and Building Systems Using OpenVPX Profiles Having seen an introduction to the OpenVPX specification, the next issue is how to go about designing practical systems based on it. Taking advantage of the initially daunting flexibility and variety involves a number of steps with close attention to the specification. by Ken Grob, Elma Electronic





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art one of this two-part article provided an introduction to the VITA 65 OpenVPX specification (“The Quest to Navigate the OpenVPX Standard: VITA 65,” RTC September 2010). New concepts introduced by OpenVPX, such as Module, Slot and Backplane profiles were discussed with a guide to navigating the specification. OpenVPX is built on existing base VPX specifications including VITA 46.x, and therefore VPX systems are largely based on serial fabrics implemented using pairs of differential pointto-point interconnects. In moving from a parallel bus-based scheme of interconnect to a serial fabric-based interconnect, the notion of one general backplane topology such as VME or cPCI is gone. The industry has been using a set of backward-compatible standards for years that have allowed plug-compatible modules to be used with common backplanes. For over 20 years, VME boards have been interoperable with little concern as to whether a board would operate when plugged into widely available standard backplanes. With the serial fabrics used in OpenVPX, board-to-board I/O is now point-to-point, and unique. A central goal

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Figure 1 Example Slot Profiles from left to right: Payload, Peripheral, Switch and Storage.

of the OpenVPX standard is to promote interoperability. Thus OpenVPX has introduced a language to describe and label interconnects required to implement specific system topology, and has also given us named profiles to identify unique to-

pologies for interconnecting modules. In part two, we will look at how systems can be implemented using the standard Profiles defined by OpenVPX. Before we get started, let’s look at some general items to consider when

tech in systems

weighing OpenVPX versus other existing legacy system standards. For instance, when comparing VME or cPCI to VPX, the following points and features can be reviewed when comparing the technologies: • Available form factor – 3U or 6U • Convection- or conduction-cooled environment, supported by OpenVPX • More available power in 3U and 6U form factors than VME and cPCI • Higher bandwidth differential interconnects up to 6.25 Gbit/s • Required system topology: Mesh, Star, Dual Star; the need for multiple signal planes • Need for redundancy, for instance dual star architecture • Legacy support for parallel VME is a hybrid system • Single plane or multi-plane architecture: Control plane, Control and Data, need for Expansion plane • Type of Fabric Protocol: PCI Express, Ethernet, SRIO, etc.

More Planning Required – Picking Hardware

Determining the required architecture, backplanes and modules may be an iterative process when looking for an off-the-shelf solution using OpenVPX. In approaching a system implementation in VPX, a few additional steps are required in specifying boards or modules to be considered for the system. In part one, a table was introduced called “Profiles at a Glance.” This table describes the types of profiles defined by OpenVPX. OpenVPX defines profile descriptors for modules to be used in a system, and then also defines slot profiles (Figure 1), which define the mapping of I/O onto connectors used in the backplane. The module profile is specific to the physical protocol to be used, such as PCI Express or 1000Base-T Ethernet, while the slot profile maps I/O onto a connector but is agnostic in terms of physical protocol. Further interconnect between the slots in a backplane is defined by the backplane profile (Figures 2 through 4). In that the backplane profile references slot profiles, the designer must identify the profiles associated with the standard boards that will be selected for the system. In order

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Figure 3 3U Mesh Backplane Profile Example.

to do this, each board manufacturer must specify the module profile description of the OpenVPX board, to identify the physical interfaces of the module. This would be a starting point in identifying interoperable modules to be used in a specific OpenVPX system topology. In addition, one must consider the system topology that will be required of the modules or

boards to be used in the system. By way of review, slots are defined as Payload (PAY), Peripheral (PER), Switch (SWH), Storage (STO) and Bridge (BRG). Backplane topologies are identified as Central, or Star (CEN), Distributed, or Mesh (DIS) and Hybrid—VME & VPX (HYB). Typically the system designer will be breaking an application down into funcRTC MAGAZINE NOVEMBER 2010


Tech In Systems

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VME VME VME VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX VPX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VME Bus (VITA46.1)

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Figure 4 6U Hybrid Profile VME and VPX Example. Payload Slot

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Figure 5 Central switch star example: Single Root, Data Plane - Star Architecture is Typical with one SBC and 8 carriers.

tional elements, and identifying functional blocks such as SBC, Switch and I/O boards. These boards or modules will be connected uniquely through a backplane defined by a backplane profile describing the interconnect. At this point, it should be mentioned that the developer will typically require a standards-based development chassis to plug boards into to support system development. At a minimum, OpenVPX and the existing profiles initially defined were identified to do exactly this, provide a backplane topology suitable to support initial system development. What should



be made clear is that the development profiles specified by OpenVPX may not provide the topology necessary to implement the user’s end architecture. The end architecture may require a “yet to be defined” interconnect at the backplane level; however, existing module and slot profiles may be suitable, but the end backplane interconnect may require tailoring. OpenVPX provides a language to describe the modules and slots, and provides a way to draw and describe a tailored backplane. Here, the end application profile can be described as a target application profile TAP), the one that will ulti-

mately be needed by the end application. Where the TAP may use standard slot and module profiles, the backplane profile will end up being specific. This has been anticipated by the OpenVPX standard. In certain cases, it may be desired to apply for a new backplane profile to be added to the standard. The VITA standards body has made provisions for new profiles to be considered for addition to the standard, however it is not required. In identifying a backplane that is appropriate, review the topologies described by 6U module profiles and 6U backplane profiles in the specification that will identify the architectures that are available. 3U tables are also in the spec. Many manufacturers will tend to point the user to a reference development system, or specify module profiles that can assist in identifying a suitable development chassis with an appropriate backplane. For a sequence of steps in defining a system, see “What are the Steps to Define a VPX System?” p. 33.

Identifying a Development Backplane

After review of the topology needs, the system architect will determine if a simple star architecture is needed, or whether a more complex central switched architecture may be required. Review of the backplane profiles will identify the standards. Next, one needs to know if they are actually available. Conversations with the board manufacturer or a packaging company will reveal which standard backplanes have been brought forward. If not, typical lead times to have a backplane built to the standard are on the order of 10 to 16 weeks. Such backplanes can usually be added to a standard development chassis. The backplane in Figure 5 is a simple central switched star, using a single root SBC in slot one, with eight peripheral slots using UTP PCIe x 1 link. The peripheral modules can be simple VPX Carrier cards.

Adding Temporary Pipes to a Backplane

Adding connections to an uncommitted backplane is a method to test an evolving topology. A way to do this is via offthe-shelf differential cables, organized as

tech in systems



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What Are the Steps to Define a VPX System?

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Figure 6 A target application profile (a) modifies a standard backplane profile with an extension that specifies the interconnect needed to add the extended version of the management switch (b).

OpenVPX jumpers. These cables can be made with wafer based connectors, organized as Ultra Thin, Thin and FAT Pipes, allowing a point-to-point connection to be added to the backplane. For instance, a PCIe x 4 connection can be added from an SBC Payload slot to a Peripheral slot to drive a required expansion connection.

Development in Steps

If the target application can’t be implemented via a released OpenVPX backplane, it is likely that parts of it can be implemented with an off-the-shelf backplane. If the end application requires tailoring, then a target application profile (TAP) must be developed. Figure 6a shows how two standard profiles can be used to begin development, with a notional view of a topology required when multiple FPGA payload cards are used in an application. In this case, a TAP is required to specify the interconnect required of the

end-use backplane. It is useful to describe it based on standard slot and module profiles as shown. The TAP in Figure 6 extends BKP3CEN-07-15.2.3-n, by adding expansion plane interconnect between 3U front end processor boards. Single board computers are connected via the data plane, and control plane to the 3U Switch. The switch provides PCIe Gen 2 fabric on the data plane, and Gigabit Ethernet via UTPs on the control plane. An extended version of the SLT3-SWH-6F6U-14.4.1 switch profile shown in Figure 6b is included in the target application profile. In summary, designing with OpenVPX requires the user to be sensitive to the unique I/O mapping of each backplane to be used. The specification has provided a means to identify module I/O specific to the fabric protocol used, and slot I/O as a general mapping of the I/O per slot, in order to allow unique in-

1) Define the architecture a) Determine the backplane topology for the data flow and application (Central Switched, Star, Distributed or Full Mesh, etc.). b) Determine if a standard backplane profile exists for the application—Don’t worry if it does not; this will be common. 2) Choose the slot profiles required for the I/O and your boards a) Pick the slot profile that defines and maps the I/O that you need—choices include Payload, Switch, Peripheral, Bridge and Storage. b) This process may be repetitive; there are over 30 slot profiles. 3) Obtain the module profiles for your boards a) The module profile specifies the ports and protocols. Examples: i) T wo ports of PCIe x 4 (2F = 2 Fat Pipes). ii) T wo ports of 1000-Base-T Ethernet (2T = 2 Thin Pipes). 4) Associate module profiles with the slot profiles a) More than one module profile can be used with a slot profile. b) Slot profiles are protocol agnostic. c) A board may comply with many module profiles. 5) This process may be iterative—It may start with the boards, or with the architecture.

terconnect of the slots defined by a backplane profile. Care must be exercised in selecting the backplane, since the fabric interfaces support different bandwidths, thus requiring better materials as the bit rate is increased. OpenVPX has provided a set of profiles, or recipes for implementing VPX-based systems. Variants of the existing backplane profiles are expected, and will be necessary to implement specific applications that can be described as Target Application Profiles. Elma Electronic Fremont, CA. (510) 490-7388. [].



technology deployed Preconfigured Industrial PCs

Preconfigured Industrial Computers Make Inroads on Rack-Based Systems

solution that the buyer can adapt to meet requirements. There is an emphasis on design and knowing the environmental and application considerations and requirements for the preconfigured system. Prepackaged solutions are modular, flexible and adaptable to accommodate change or expansion. As PC-type processors have become smaller and faster, preconfigured systems have evolved to a new level of processing power, modularity and robust software. Other advances have mitigated concerns about mechanical parts that can fail. Optional compact flash and solid-state drives address ruggedness when conventional, mechanical hard drives may be at risk. Fans Modern preconfigured industrial PCs provide an attractive that wear or break and need to be replaced are replaced by convective-cooling strateoption for many embedded computing applications in gies. Thus, these systems are able to meet rugged environments. the demands of rugged environments while offering robust and integrated I/O support. by Joseph Primeau, Acromag What further positions this “new class” of industrial PC as a compelling alternative to rack-based systems is its advantage in terms ith the continuous performance improvements in PC- of size, weight and power. The Industrial I/O Server shown in Figure 1 is a rugged inbased systems and the associated PCI bus architecture, dustrial PC with truly integrated support for user I/O. The server many traditionally rack-based embedded computing apcontains two boards. It has a top board with a built-in CPU and plications have migrated to preconfigured, ruggedized industrial I/O support for video, audio, Ethernet, serial and USB devices. computers. The popularity of Windows Embedded and Linux operating systems is also fueling this trend. These small form The bottom board is a user-selectable carrier board that can perfactor (SFF) industrial PCs typically offer modular flexibility to form a wide variety of analog, digital, counter/timer and serial select the processor, memory, operating system and even I/O that I/O functions (Figure 2). A cut-away view of advanced heat-sink is pretested for compatibility. methodology is shown in Figure 3. Conduction-cooling plates Growing concern for size, weight and power restrictions, par- and thermal pads draw internal heat to the aluminum enclosure ticularly in mobile systems, also favors preconfigured systems, where external cooling fins dissipate the heat (“Thermal Manwhich deliver an integrated solution that is mindful of these critical agement for the Small Box,” RTC, Sept. 2009). factors. The complication of predicting power consumption, heat management and other compatibility issues in assembled multi- Advances in PC-based Platforms vendor systems is eliminated. Additionally, and perhaps most imIn the past, it took a robust CPU and many components to portant, preconfigured industrial PCs offer considerable cost sav- create a CPU board that was suitable for industrial applications. ings compared to VME, CompactPCI, rackmount PCI and PC/104 systems. Given all these considerations and the increasing pressure to shorten engineering development cycles, modern preconfigured industrial PCs provide an attractive option for many embedded computing applications in rugged environments.


Preconfigured Systems

The advantage of VME-based or CompactPCI systems is starting to be outweighed by the cost of putting a system together. For one, buyers traditionally must deal with multiple vendors for rack, CPU, I/O, power supply and operating system components. All the pieces must be brought together and engineered. With a preconfigured system, the work is done by the seller to provide a prepackaged



Figure 1 Preconfigured industrial PC with plug-in I/O modules.

Technology deployed

But smaller and smaller packaging developed through small form factor engineering has reduced CPU size while increasing capability. Designers can design a package with the right amount of processing power for the application. An AMD Geode processor may be sufficient for a simple application; whereas moving up to an Intel Atom handles industrial applications. If an even more powerful processor is needed, devices such as the new Intel Core i5 CPU offer Turbo processing speeds above 3 GHz. Although the PCI bus architecture is not new, it represents a major breakthrough in PC technology that drives substantial benefits even today. And it is being enhanced with the software-compatible extension of PCI Express. In large part, it is responsible for the convenient modularity that PC technology enjoys. Components are automatically configured when the system boots up and resource allocation is handled to ensure there are no conflicts. PCI is key to support “plug & play” setup. Also of high importance, PCI is fast and has the bandwidth to take full advantage of the powerful CPUs that are available today. Advances in storage technology, including solid-state storage devices and flash memory, have broadened available options to achieve a smaller form factor with increased ruggedness while also offering lower power consumption. Solid-state drives (SSDs) use the same interface as hard disk drives (HDDs) and have a similar form factor of only about 2 1/2 inches. SSDs and HDDs are basically interchangeable and fit well with a preconfigured approach in which choices become a tradeoff between cost versus application and environmental requirements. Also fairly recent to the marketplace are compact and efficient operating systems that are now available for small form factor computing. Developed with streamlined functionality for embedded computing applications, a chief advantage of these systems is their small footprint. These operating systems offer additional design advantages for industrial PCs in terms of memory management, power consumption process management and reliability. Because preconfigured systems must be fully integrated by design, there is ensured compatibility of all modules, components and drivers.

I/O Options

Not only must Industrial PCs support the standard I/O one would expect, namely, video, audio, Ethernet, serial and USB, they must also meet the challenging I/O demands of an industrial application and potentially advanced communication protocols. For industrial applications, industrial PCs must support a wide variety of analog inputs and outputs, digital I/O (for TTL, LVDS and higher voltage levels) and counter-timers, as well as serial interfaces including RS-232/422/485 and may need to support I/O for specialized communications such as CAN-bus and

Figure 2 I/O carrier board shown with thermal conductive covers.

MIL-STD-1553. Some applications require custom signal processing algorithms and logic routines requiring user-configurable FPGA modules. Modular I/O addresses the challenge while keeping the cost of one-off solutions at bay. With modular I/O, you “plug in” the I/O that is needed and mix and match I/O options to meet application requirements. Standard connectors (for example, SCSI3) receive cables that typically go to a termination panel, which acts as the interface to the field. Modularity is again important to adapt I/O for specialized communications that may require special cabling. Software development tools greatly simplify the interface between the I/O modules and the application program. Modular, prepackaged I/O has an additional advantage in that cabling is already wired within the “box” so the installer does not have to do the internal cable routing as needs to be done with PC/104 modules.

The “SWaP” Challenge

The idea behind preconfigured systems is to control size, weight and power. Rack-based systems have a fairly large package with a 6U or 3U form factor that may be 19 inches wide and 10 or 12 inches tall. For applications with many different functions and in a benign environment, for example, in a laboratory with plenty of space, rack-based systems make sense. But when you start moving these systems to factory floors, into machinery, for use with transport-station vehicles, or anywhere with high environmental stress, the physical size of the board and ruggedized requirements lead to systems with weight and package-size characteristics that can overcome the benefits. A goal for preconfigured systems is to design the whole package in order to optimize all the design elements to achieve a smaller package. Most preRTC MAGAZINE NOVEMBER 2010


technology deployed

Enclosure Walls Heat spreader Friction plate Thermal gap pad PC board Components

Figure 3 Cut-away view of the heat sink methodology.

configured systems designed for a small form factor are typically no more than 10 inches wide and 3 or 4 inches tall. The big advantage of preconfigured systems is that engineers have control to design a single package to meet known requirements while providing for necessary flexibility. Weight, as with size, becomes a design parameter. Power consumption is known, and tradeoffs can be made to achieve an optimal solution for the application. Innovative design for heat dissipation helps in the equation to manage heat and potentially increases the maximum allowable power consumption. Conduction-cooling, for example, provides a mechanism to quickly move heat from components to the body of the enclosure, thus allowing the outside ambient air temperature to draw the heat away. Ruggedness comes down to the capability to operate in environments where high or low temperatures, sudden shock and vibration are factors. Rugged preconfigured systems typically

Figure 4 Hurricane data collection using a Global Hawk UAV rather than a manned aircraft.

Freescale e500 Computer On Module (COM) The CSB1880, designed, developed and manufactured by Cogent Computer Systems, Inc., is a high performance, network oriented, PowerPC based Computer on a Module (COM). The CSB1880 provides a small, powerful and flexible engine for embedded Linux based GIGe networking applications of all kinds. y y y y y y y y y y

1.25GHz Superscalar e500 Core w/512KB L2 Cache 512MByte 64-Bit Wide DDR2-667 Memory with 8-Bit ECC 64MByte NOR with Secure ID, and 512MByte SLC NAND Two PCIe x4 Port (or one x4 and Two x2's) Two 10/100/1000 ports via BCM5482S to Copper/Fiber PHY Two SATA Gen 2 (1.5Gbit or 3.0Gbit/sec) Channels Three 480Mbit USB 2.0 Host Ports <7W Typical, 12W Maximum, <3W in Jog Mode 95mm x 95mm x 8mm (using 5mm COM Express Connector) Linux 2.6.x BSP with available 1 year of support

Development Kit includes CSB1880 COM, CSB1801 uATX Carrier and Case, with 1 Year of Support and Updates The CSB1880 is manufactured in our in-house state of the art, lead-free surface mount manufacturing line. All products carry a 1-year warranty and are available in commercial and industrial temperature versions. Cogent also offers standard and custom carrier boards, plus royalty free licensing options for the CSB1880.



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Technology deployed

do not have a fan and employ advanced thermal technology along with high-performance components to accommodate a wide operating temperature range of -40° to 75°C. Modules must be held securely in place for shock and vibration resistance. Reducing the number of cables and focusing on cable management is critical to reduce the risk of cables coming loose by shock or operational vibration. Tradeoffs between ruggedness and cost become design factors, and these vary for the application environment whether out of doors, in a vehicle, in military or extreme conditions, or part of a specialized lab or factory.

Vertical Markets

Rugged and compact, preconfigured industrial PCs are used in a growing number of vertical markets where real-world analog and digital data is collected in rugged environments that require a small form factor computing solution. Some of the vertical markets deploying industrial PCs include the following: • Machine control for factory automation • Turbine control and solar power grid monitoring • Military and homeland security systems • Transportation and mobile servers • Outdoor signage and display systems • Test & measurement systems requiring robust data acquisition • Scientific research and simulation

To cite just two specific examples, one involves an I/O server industrial PC that is used in the Global Hawk—a drone flown in hurricane research where shock and vibration are evident challenges (Figure 4). The Global Hawk flies above a hurricane and collects hours of data on wind strength, velocity and acceleration that forecasters can use to establish storm formation, intensity and direction. In a second example involving aircraft design and inspection, an industrial I/O server is used to monitor aircraft body sensors during stress cycling. The aircraft is pressure cycled during the design phase. Engineers can use the collected data to aid in material selection and structural component design to avoid stress concentrations and increase fatigue resistance. Acromag Wixom, MI. (248) 624-1541. [].

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11/3/10 10:52:35 AM RTC MAGAZINE NOVEMBER 2010



Modern Wearable Computers – Form and Function Still Reign Intelligent wearable technology that can exchange data in real time under extreme conditions is no longer a goal for the future—it is being deployed today.

by Tiziano Modotti and Haritha Treadway, Eurotech


eveloping a full-function computer to mount on the body requires a delicate balance of computing power, usability, ruggedization and ergonomics. In contrast to mobile devices, wearable computers must provide computational support while the user’s hands, voice, eyes and mind are actively engaged in their physical environment. Over the past 50 years, wearable computers have evolved from concept to reality. The first wearable computer was a smart phone-sized pocket computer designed to predict roulette wheels. Wearable computers may have entered the market as a novelty, but today they offer an extremely useful way to tie field personnel to a central computing system. Wearable computers are most prevalent in military, healthcare, transportation, industrial and emergency service applications. Nearly every advancement in embedded computing can also be applied to a wearable computer. As long as the technology can be put to use in a small form factor while taking ergonomics and vibration into account, it can be utilized in a wearable computer. Therefore, recent



advancements in wireless communication and COTS technology have greatly benefitted the wearable computing market. On the horizon, wearable computers are becoming more cost-effective, are easier to use, and offer more functionality than ever before while mounted to the body.

Expanding the Possibilities of Useful Work

Wearable computers have the capacity to transform where and how we use computers, enabling hands-free operation and greater freedom of movement in applications where the use of traditional computers is impractical. As wearable computers become pervasive, the sight of a clipboard and pen in a warehouse is soon to become extinct. In order to expand the possibilities of useful work, wearable computers must be seamlessly integrated with how the user operates. Wearable computers must be powerful, usable, rugged and comfortable. Designers need to make a number of considerations when developing a wearable computer. The first of these is location on the body. Wrist wearable computers are the

Figure 1 Eurotech’s Zypad is an example of a wrist-wearable computer.

most common form (Figure 1), although wearable computers can be designed for many other locations such as the belt, ankle, eyes and chest pocket. Weight is an important consideration depending on where the computer will be worn. Less than a pound feels comfortable on the


Wearable Devices in the Cloud

Figure 2 Flex circuits connect stacked PCBs to incorporate wireless functionality in a wearable computer.

wrist, but a heavier, two-pound device is better suited for a belt loop. In addition, the materials used should be carefully selected with their potential environment and use conditions in mind. Wearable computers must be made of a strong, lightweight material. Regardless of the application, the product must be able to withstand shocks and vibration since it will be worn on the body. Even the warehouse is a very tough environment, and military environments are typically the most rugged application. When operators use a wearable device, they have to pay attention to their duties. The user will not be able to take care of the device, so it must withstand impact without consequence. Anti-bacterial materials are also important, since wearable computers are often passed from one employee to another. Designers must consider removable wrist bands and other long-term solutions for wearable computers that will be used in a rugged environment for many years. Since wearable computers are by definition portable, mobile devices, bat-

tery technology plays a vital role. Since lighter is better, improvements in Lithium battery technology have made wearable computers more comfortable. Wearable computers should also be extremely efficient in power usage, since longer battery life means increased productivity. The wrist-wearable Zypad from Eurotech includes power sequencing to control power usage during Switch On, Standby (Light Sleep), Suspend (Deep Sleep), Wakeup and Forced Power Off. The available modes extend battery life—the Zypad can run 168 hours in Suspend mode, able to power back on and resume operations in just moments. The device uses a Smart Battery that can easily run for several hours using a duty cycle typical of a full warehouse shift. The ergonomic design of a wearable device often determines the product’s success. If the device is not comfortable and easy to operate, the wearable computer can be more of a hindrance than an asset. The shape must fit to the body and be comfortable to wear for long periods of time.

Cloud computing has penetrated almost every industry, and now Web-based computing where shared resources are provided on demand is beginning to come of age in the embedded industry. With the cloud, an embedded device or wearable computer connects to the cloud through an edge node or other networking device. The data can then be stored in the cloud, where the administrator can access, compare and compile the data. For instance, in an oil and gas plant all of the meters can feed data into a cloud service. Then, a manager uses a Web-based desktop application to access the application in the cloud and see how many barrels of oil have been manufactured, where they are located and other pertinent information. In addition to the desktop, a mobile device, or even a wearable computer, can access this information for real-time access to data. Benefits of using wearable devices in the cloud include near infinite scalability, data security, on-demand connectivity and the ability to interface with almost any type of application. It used to take months and even years to plan, procure and deploy IT infrastructure to connect wearable computers to a network and capture valuable data. With cloud computing it can be done in minutes. Studies on ergonomics have highlighted the importance of weight, wearability and screen size in a wearable electronic device. To satisfy these prerequisites, designers miniaturized the computer’s circuit card assemblies to make it easy to use and comfortable to wear. Designers used stacked PCBs connected with rigid flex circuits (Figure 2) to integrate functionality, including all the antennas for GPS, Wi-Fi and Zigbee.

Architecture and Communication

In the past, portable devices were not easily transformed into wearable devices. RTC MAGAZINE NOVEMBER 2010



connected via Zigbee to the wearable computer to measure user biometric data (blood pressure, heart rate, etc.). A BAN connection can be very useful to monitor a patient in the healthcare industry or a soldier under stress in a military environment.






Figure 3 The various ways for a wearable computer to connect over a wireless network.

With the advent of the low-power Intel Atom processor, now designers can save time and money by easily porting an application written for a PC or a mobile computer to an x86-based wearable device. Consider a mission-critical application for defense or transportation that must be certified. Traditionally the application is developed for a laptop, and developing the software is a huge investment. Now the designer can leverage common software architecture between the development environment and the targeted wearable device to make ongoing support and certification easier. While wearable devices can perform computations without a connection, wireless communication is perhaps the most important consideration today to make a wearable device useful. Each wearable computer must be part of a system that connects to a building, server, an automobile, or even to a Cloud service provider (see “Wearable Devices in the Cloud,” p. 39). There are many ways for a wearable computer to communicate over a wireless network depending on the application (Figure 3). These include: • Wi-Fi technology for WLAN networks



• Bluetooth technology for WPAN networks • Cellular technology (either GSMworldwide and CDMA-mainly USA standards) for WWAN networks and military communication tactical radios technology networks for WWAN networks • Zigbee technology for body area networks (BANs) A WLAN network is used to link a wearable computer to the building IT infrastructure in a client-server architecture. WPAN is used when you need to connect to a device that is not more than a few yards away from the user, such as a Bluetooth barcode scanner. While WLAN and WPAN meet only a few standards, WWAN depends on the application and could be a link over a cellular network to stay connected with the headquarters. WWAN could also link via tactical radio to stay connected to the control room in a defense application. Wrist wearable computers can also have a GPS receiver, which allows for the use of location-aware applications. The body area network (BAN) is relatively new concept and consists of sensors

New Directions in Wearable Devices

Wearable computers are no longer new, but they are much more powerful. Since they are more powerful, they are becoming more commonplace and more useful, especially in transportation, military and industrial applications. Recent market research indicates that wearable computers are expected to surpass the early adopter phase and become more widely deployed in the next five years. Exciting new features in wearable devices include cameras, voice activation, and microphones to capture sound. These types of features give wearable computer users complete, hands-free mobility. Instead of users sitting at a desk and interacting with their computers for part of the day, wearable computers are becoming so tightly integrated into the life of the user that they hardly notice their presence. Ergonomics has always been key for wearable computers, and designers are getting more and more creative while developing devices that truly blend in with the user’s clothing and lifestyle. When higher power devices are required, designers are finding innovative solutions such as storing the heavy part of the computer on the belt, with a very light display housed on the wrist. The Eurotech Zypad, for example, can connect to a barcode scanner that is placed on the finger, which is ideal for warehouse management applications. As we have seen in cell phones, wearable computers today can get better resolution on smaller screens. New display technologies such as the organic light emitting diode (OLED) can also enhance the wearable computing experience. An OLED display is thinner and lighter than liquid crystal displays and does not use a backlight. OLED displays are used in prototype “augmented reality eye glasses” among other devices.


As previously discussed, advances in embedded and mobile technology are rapidly changing the wearable computing industry. New wireless technology allows users and managers to see remote data and send local data easily. Now warehouse supervisors can view an instant snapshot of data at various locations. Cloud computing technology is simplifying this process, requiring less development time, less storage space and providing for the faster collection of data. While hundreds of wearable computers are already deployed in military applications, technological advancements are making these devices more practical for other industrial applications that can benefit from hands-free computer access and a constant network connection. Nonmilitary deployments include a number of application areas. First responders can take advantage of wearable computers in emergency situations. Wearable computers can help coordinate teams and rescue workers by permitting on-scene workers to exchange information in real time and locate workers’ exact locations. Another big and growing area is health care. Wearable computers can provide medical personnel and paramedics with real-time updates on patients’ clinical status. In addition, medical staff in first aid situations can have wireless connections to the ambulance, which can then communicate with the control center via radio. This allows medical staff to exchange information with the control center directly from the emergency site while maintaining contact with the patient. In logistics operations such as shipping, wearable computers can save time by simplifying inventory tasks, goods sorting in courier hubs, and pickup and delivery from express couriers. A worker’s ability to read data from bar codes and RFID tags while simultaneously performing the physical tasks required in such tasks can greatly increase the efficiency and accuracy of such operations. Arguably the most pervasive use of wearable computers is in the armed forces, where soldiers are using wrist-wearable

computers in the field. Net-centric warfare aims to achieve a robustly networked force for shared situational awareness, which in turn dramatically increases military mission effectiveness. Wearable computing technology provides soldiers with the computing power needed for combat, thereby increasing the success of net-centric war-

fare. But beyond this, the potential of wearable computing is finding its way into ever more non-military applications as well. Eurotech Columbia, MD. (301) 490-4007. [].

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10/12/10 11:23:07 AM RTC MAGAZINE NOVEMBER 2010

ploration your goal k directly age, the source. ology, d products



Application of PSoC in Electronic Medical Devices Medical devices are getting smaller and more sophisticated. To achieve portability, high functionality and low cost, a programmable system on chip can be configured to serve a number of different functions to create a medical device on chip. Sammy Lee, Cypress Semiconductor


n order to respond to the increase of medical expenses and the rise of health insurance costs, home health examinations that reduce the number of hospital visits and cut down the squandering of medical resources have become the latest trend in the medical health community. The often large and cumbersome measurement devices such as the infrared electronic thermometer, blood pressure moninies providing now tor, solutions blood glucose meter, pulse oximeter ion into products, technologies and companies. Whethersmaller your goal is and ECG monitor have become into research the latest ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you terms of dimensions, remain durable for a you require for whatever type of technology, and productslonger you are period searchingof for.time, and are less expensive as the electronic technology evolves to maturity. Portable electronic medical devices, in general, have a number of working components in common. Figure 1 For example, all the devices shown in Examples of portable electronic medical devices. Figure 1 require some form of vital sign biosensor or transducer to provide the signals. These signals must then be ampli- nals. A microcontroller is required for sig- needed in all such devices. Then, dependfied with the appropriate circuitry and/or nal analysis and processing as well as for ing on the particular system requirements, converted between digital and analog sig- logic judgment. Battery power is required other components can be included such as for portability as are power control com- those for data access and storage; wired or ponents to optimize power usage. Human wireless communication, and sometimes Get Connected interface components such as the screen, feedback components using vibration or with companies mentioned in this article. keyboard, button and switch are also voice are included.

End of Article



Get Connected with companies mentioned in this article.


As they are portable electronic devices, the engineer also needs to consider the design scope of consumer electronics during the product development. For example, performance: The measurement result shall be sufficiently accurate, so the proper, yet not excessive range of performance must be selected. Low power consumption is also a vital consideration. As a rule of thumb, the product should function normally without changing the battery for more than 6 months. The product shall be as small as possible, easy to carry and more energy-saving. Quick evolution is as important as it is in the consumer market. You need to be the first to release new products to claim or secure the market. And of course, low cost is paramount. The product has to be affordable. After understanding the needs of portable electronic medical devices, we now turn to how PSoC helps the engineers to develop more advanced products. PSoC combines the programmable digital and analog components, indicating that it is able to provide the signal amplifier, analog-to-digital converter/digital-to-analog converter, filter and PWMs required for the portable electronic medical devices. PSoC includes the 8-bit (8051) or 32-bit (Arm Cortex M3) microprocessor, meaning that it is able to support various unifunctional medical devices, or integrates three to four functions to become the control chip of the physiological monitor (infrared electronic thermometer, blood pressure, blood oxygen analysis and heart beat). The USB, UART, I2C and SPI transmission managements inherent to PSoC allow free-flowing communication among ICs.

Medical Devices on Chip?

Let us take as an example the application of a programmable system on chip (PSoC) in the blood pressure monitor. The PSoC integrates an ARM Cortex M3/8051 processor on the same silicon die as an array of programmable I/O logic. It takes advantage of the oscillometric method, which

Band Pass Filter

Pressure Sensor


AC Coupling M U X


Unity Gain Buffer

13-Bit A D C 16x2 Character LCD Display

M8C/8051 Timer PWM 8-Bit

PWM 8-Bit

Valve Control

Motor Control

Motor Driving Transistors

Air Chamber

Figure 2

PSoC Keypad

Rolling Pump

Relay Valve

Blood Pressure Monitor Diagram.

Current source

Bias Generator LED switch

Sync AMP demodulator

Carrier generator

Low-pass filter Integrating ADC RS-232

PSoC Pulse Beats

Service routines

Pulse-rate calculation

Software Implemented

Smart peak detector SPO2 calculation


High-pass filter High-pass filter

Low-pass filter Low-pass filter

Figure 3 Pulse Oximeter Diagram.

is the most widely used method in portable electronic blood pressure monitors. Referring to Figure 2, the PSoC uses the built-in pulse width modulation (PWM) to drive the air motor for pressurizing the cuff on the arm. During the gas release, the pulse

of the internal artery, through the cuff and air pressure sensor, is converted to the signal that is transmitted to PSoC. As the signal is only a few mV, it is amplified (InAmp + PGA) and the noise of the blood in the blood vessel is filtered (band pass filter). FiRTC MAGAZINE NOVEMBER 2010



nally, the signal passes through the analogto-digital converter to become the digital signal for PSoC to measure the subjectâ&#x20AC;&#x2122;s systolic blood pressure (SBP), diastolic blood pressure (DBP) and mean arterial pressure (MAP). All of these components can be configured in the digital and analog subsystems of the PSoC. These signals are displayed on the LCD screen to complete blood pressure measurement.

Whatâ&#x20AC;&#x2122;s worth mentioning is that all electronic components other than the external components such as the LCD screen, motor, air pressure sensor and motor driver are replaced by one single PSoC. This is able to save much space and accomplish the product development swiftly. PSoC can thus be regarded as a BPM on chip! Next, consider the application of PSoC in the pulse oximeter. The oxygen

saturation SaO2/SpO2 is the ratio of oxyhemoglobin (HbO2) to total hemoglobin (oxyhemoglobin + reduced hemoglobin) in the blood. Usually, the higher the ratio the healthier a person is. Most oximeters are fixed on top of the finger. There is an infrared LED above the finger and an infrared sensor below the finger. According to the difference in the infrared absorption between the oxyhemoglobin and reduced oxyhemoglobin, one can calculate the blood oxygen concentration based on the infrared signal intensity. As it varies with the heartbeat, one can then figure out the heartbeat rate based on the cycle alteration and measure the heart rate and the blood oxygen content simultaneously. As indicated in the PSoC pulse oximeter of Figure 3, one can see that, except the current source (LED driver) and infrared sensor, all other components are replaced by PSoC. All the calculations are completed inside PSoC to save the development cost and time. After the examples of the applications of PSoC in the blood pressure monitor and pulse oximeter, we hope readers may have a more advanced understanding about PSoC. You are welcome to download the PSoC work environment PSoC Designer and PSoC Creator on the Cypress website and consult the application notes of the blood pressure monitor [] and pulse oximeter [http://www.cypress. com/?id=1001&rtID=5&rID=40117] for the practical operations. We believe that the powerful functions of PSoC will present more surprises and benefits to you. Cypress Semiconductor San Jose, CA. (408) 943-2600. [].


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9/2/10 3:20:44 PM

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A ruggedized 4-slot conductioncooled enclosure for VPX 3U modules is designed to MIL-STD-810F, DO-160E and MIL-STD-461E standards, and is compliant with applicable VITA 46 (VPX), VITA 48 (REDI) and VITA 65 (OpenVPX) specifications. The CCE-3VPX4 VPX Cube from Dawn VME Products features 4 slots of 3U VPX on a 1” pitch high bandwidth backplane and an integrated, wide temperature range 400 watt power supply. The chassis is cold plate base-coupled, conduction cooled. Its short and efficient thermal conductivity path provides for robust cooling performance and maximum power dissipation. Operating temperature range is -40° to +85°C. Full environmental sealing ensures reliable, allconditions operation. The backplane is Fabric Mapping Module (FMM) overlay ready and configurable to meet any data plane connection fabric. Front I/O mapping overlay enables signal path customization from card I/O, such as PMC and XMC, to front panel I/O interface connectors. Dawn has filed for a provisional patent for this revolutionary interconnect technology. The I/O panel to backplane is interfaced via shielded differential connectors for applications from 3.125 Gbit/s to 10+ Gbit/s. The I/O panel connectors can be linked to optical as well as SMA and other RF connectors for application enhancement. Dawn’s RuSH System Health Monitor technology for intelligent, precision monitoring and control of critical system performance parameters is embedded in the integrated Power Supply in the standard VPX Cube configuration. Temperature, power supply voltage and current on all VS(n) and AUX rails are real-time monitored, with optional humidity monitoring available. Dawn VME Products, Fremont, CA. (510) 657-4444. [].

Building Blocks for Ticketing, Fleet Management and Communication in Public Transit

An application-ready set of building blocks for computing and communications tasks in buses and light rail trains in public transportation offers solution providers, system houses and system integrators a complete platform for improved time-to-market, which can be individually combined and also customized to meet individual requirements. The EN50155-compliant Kontron Venturo Vehicle Management System for buses and light rail trains consists of three elements. First is the Venturo CBox, central management and communication computer; second is the Venturo HMI driver and passenger display unit with integrated ticket printer; and third is the Venturo GBox, an audio and emergency call unit. The integrated Kontron platform centralizes all tasks such as ticketing, passenger information, location identification, data acquisition, vehicle and system diagnostics, as well as internal and external communications management on a single platform. The system features rugged, fanless design with a high mean time between failure (MTBF) of 80,000 hours and a temperature range of -25° to +60°C. The Kontron Venturo CBox is the central computing device to maintain the vehicle management. Based on the energy-efficient Intel Atom processor Z5xx with 1.1 GHz or 1.6 GHz and 1 to 4 Gbyte RAM, it centralizes all communication and computing tasks. For communication flexibility, it features an internal Universal Mobile Telecommunications System (UMTS) module, a Wi-Fi module for wireless networking with IEE 802.11/a/b/g WLANs plus a GPS module with gyroscope and odometer interface for dead reckoning. The Kontron Venturo HMI is the central driver interface. It features a sunlight-readable 8.4-inch SVGA (800 x 600 pixel) touch screen for intuitive handling and operational safety. A ticket printer and a two-line fluorescent display for customer information (e.g., for displaying fares) are integrated into the driver console, both centrally controlled by the Kontron Venturo CBox via serial RS-422 interfaces (American EAI-422). An optional RFID badge reader for driver identification/authorization allows two ISO 14443A/B-compliant RFID cards to be simultaneously read. Designed as an independent system, the EN50155-compliant GSM-voice and audio box Venturo GBox combines emergency call functionality with an integrated audio switch. It can be placed anywhere near the audio sources to minimize the amount of wiring. Independently from the board computer, the audio box takes over key security functions. Activation of one of a total of two connectable emergency switches automatically initiates a voice connection via an integrated quad band GSM module for mobile communication.

Kontron, Poway, CA. (888) 294-4558. [].

Grid-Connected Solar Micro Inverter Reference Design

A fully digitally controlled grid-connected solar micro inverter reference design with an advanced, high-efficiency topology is being offered by Microchip Technology. The solar power industry is evolving to meet the requirements of a changing landscape, as it moves from a cottage industry to mass production. Solar design engineers are being challenged to optimize energy harvesting, reduce installation costs, and improve system reliability and efficiency while standardizing their designs. This reference design enables them to achieve these goals through digital power conversion techniques, supported by the features of Microchip’s dsPIC33F ‘GS’ series of digitalpower Digital Signal Controllers (DSCs). The reference design connects to any standard solar panel and converts the panel’s DC output into AC power, which can then be fed into the public power grid. In a real-world application, multiple units can be connected together to achieve the desired power output. Additional features of Microchip’s Grid-Connected Solar Micro Inverter Reference Design include a peak efficiency of 95%, a power factor of >0.95 and an output Current THD <3%. It achieves a maximum power point tracking of 99.5% and has a nighttime power consumption of less than 1W. It supports system islanding to detect grid failure and has full digital control. This reference design works with any photovoltaic (PV) panel that supplies a maximum 220 watts output, and it comes in two versions supporting either 110V or 220V power grids. Both versions of this reference design are implemented using a single dsPIC33F ‘GS’ digital-power DSC, which provides fully digital control of the power-conversion and systemmanagement functions. Complete documentation, including software, schematics and application note, can be downloaded for free today from Microchip’s Web site at Microchip Technology, Chandler, AZ. 888-624-7435. [].

Multicore Processor Family with Intelligent SoC Management

A multicore processor system-on-a-chip (SoC) family is designed with advanced subsystem and offload acceleration hardware to enable new levels of security, high availability, low latency and power management for embedded applications. Packet Pro is AppliedMicro’s second generation of embedded processor SoCs and the first to feature expandability from one to four 32-bit PowerPC 465 cores ranging in performance from 600 MHz to 1.5 GHz. The SoC subsystem design features the Scalable Lightweight Intelligent Management processor (SLIMpro) to enable high flexibility in SoC power management, asymmetric multiprocessing (AMP), failover protection, resiliency and end-to-end security for a wide range of communications, multifunction printer, industrial, wireless access point and other applications. Each device introduced into the Packet Pro family enables multiple, concurrent operating system (OS) while providing resource protection (processors, memory and I/O) for each domain for transparent, independent and protected operation. It also enables application-aware and usage-based power management to reduce energy consumption. The multi-level crypto engine offers investment protection against product cloning and hardware-software tampering. The AppliedMicro PacketPro family features performance of up to 3,000 Dhrystone MIPS per 1.5 GHz core, 32 Kbyte L1 I/D & 256 Kbyte dedicated L2 cache per core, support for full symmetric multiprocessing (SMP) and ultra flexible asymmetric multiprocessing (AMP). Memory and bus architecture supports 16/32/64-bit DDR2/3 up to 1,600 Mbit/s with ECC option. Connectivity features include one-lane and four-lane PCI-e Gen 2 controller, GE, 10GE, SGMII, RGMII, IEEE1588 Rev2 on all Ethernet ports, USB 2.0 – H/D, OTG, all with integrated PHY, SATA ports and SDHC. The PacketPro family is manufactured on a 40nm TSMC CMOS process and is available in both wire-bond and flip-chip packaging. The first PacketPro device begins sampling in November. AppliedMicro, Sunnyvale, CA. (408) 483-3139. []. RTCRTC MAGAZINE MAGAZINE NOVEMBER MONTH 2010



3U CompactPCI Building Blocks for Rolling-Stock and Rugged In-Vehicle Applications

A series of new railway-compliant 3U CompactPCI products is targeted to accelerate OEMs’ time-to-market and reduce hardware design-in costs for a host of rolling-stock and rugged in-vehicle applications. The EN50155-compliant building blocks from Kontron are aimed at providing railway-compliant products from a single solution provider so that OEMs will benefit from faster application development and reduced costs throughout the extended life cycles in trains. The Kontron CP305-TR is a 3U, 4HP extension module for the Kontron CP305, a 3U CompactPCI CPU board, which combines the performance-per-watt ratio of the Intel Atom processor with a feature set tailored to transportation needs. This includes EN50155compliant reliability, extremely low thermal design power (TDP), plus a soldered processor, chipset and RAM for harsh environments. With two USB 2.0 service ports via M8 connectors and two Fast Ethernet ports via M12 D-coded connectors, it is well suited for all mobile and transportation-oriented applications where robust, mechanically secured connections are required. The EN 50155-compliant plug-in power supply unit CP3-SVE-M100DC is especially designed to meet the demanding requirements of harsh train environments with regard to reliability and ruggedization, such as an extended operating temperature range (E2) of -40° to +70°C (EN50155 TX), a holdup time of 10ms (EN50155 S2) and full EN50155 compliance with regard to shock and vibration, EMC and isolation requirements. With its ultrawide input range, supporting all voltages between 24 VDC and 110 VDC, and a maximum output power of 100W, the PSU is suitable for both onboard and wayside applications in the rail sector. The new CP3923 Gigabit Ethernet switch can provide four (CP3923-4M) or eight (CP3923-8M) Gigabit Ethernet ports via rugged M12-D connectors, as well as IPv4/IPv6 routing and full management capabilities. It supports a powerful set of CLI, Telnet, Web and SNMP management interfaces to configure the entire set of protocols and parameters including Layer 2 and Layer 3 (IPv4/IPv6) protocols, Multicasting, QoS and Security. In addition, the CP3923 maximizes the reliability of rugged COTS applications by supporting Intelligent Platform Management (IPMI) and hot-swap capabilities. Kontron, Poway, CA. (888) 294-4558. [].

AMC Card with FMC Module Slot and FPGA Flexibility

PrPMC / XMC Module Targets Freescale Dual-Core QorIQ P2020

An air-cooled PrPMC/XMC module based on Freescale Semiconductor’s dual-core QorIQ P2020 processor has already earned design wins in commercial, telecom and aviation applications that require the latest in dual-core PowerPC technology, where processor performance is enhanced by the low power nature of the QorIQ processor family. The XPedite5500 from Extreme Engineering Solutions features the Freescale QorIQ P2020 processor with two 1.2 GHz PowerPC e500 cores, up to 4 Gbyte of DDR3-800 ECC SDRAM and up to 8 Gbyte of NAND flash and 256 Mbyte of redundant NOR flash. It runs 32-bit, 66/33 MHz PCI on PMC interface and also offers a x4 PCI Express or Serial RapidIO XMC interface. Two Gigabit Ethernet ports connect to P14/P16 and one Gigabit Ethernet port to front panel. Two serial ports to P14/P16; two serial ports are available on the front panel as is one USB port. Operating system support includes boards support packages (BSPs) for Green Hills Integrity, Wind River VxWorks and Linux. Pricing is based on memory configuration and annual volumes. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

A standard AMC.1 module offers a user-programmable XC6SLX25T-2 or XC6SLX75T-2 Xilinx Spartan-6 FPGA. Designed for industrial, COTS and transportation applications, where specialized I/O or long-term availability is required, the TAMC631 from Tews Technologies provides a number of advantages including a customizable interface for unique applications and a FPGA-based design to extend product lifecycle. For flexible front I/O solutions, the TAMC631 provides a VITA 57 FMC Module slot with a low-pin count connector, allowing active and passive signal conditioning. All FMC I/O lines are directly connected to the FPGA, which maintains the flexibility of the Select I/O technology of the Spartan-6 FPGA. The low-pin count interface includes one multi-gigabit link. In addition, the FPGA is connected to two banks of 128 Mbyte, 16-bit wide DDR3 SDRAM. The FPGA is configured by a platform Flash. The Flash device is programmable via a JTAG header. The JTAG header also supports readback and real-time debugging of the FPGA design using Xilinx ChipScope. A programmable clock generator provides up to three different clock output frequencies between 5 kHz and 200 MHz. The clock generator settings are programmable via JTAG and are stored in an EEPROM. In addition, two differential reference clocks are available from the FMC slot to the FPGA. User applications can be developed using the design software ISE WebPack, which can be downloaded free of charge from Extensive software support for major operating systems such as Windows, LynxOS, Linux, Integrity, VxWorks and QNX is available. TEWS Technologies, Halstenbeck, Germany. +49 (0) 4101 4058-0 []




Conduction Cooling Augments Legacy PC/104 Arena

A new design in the legacy PC/104 arena combines rugged design with advanced manufacturing process techniques to achieve a simple and innovative thermal design among stackable SBCs to reduce size, weight and power and cost (SWaPaC) compared to legacy VME and PC/104 SBCs. The Aurora from Diamond Systems combines the 1.6 GHz Atom Z530 processor with SODIMM RAM up to 2 Gbyte, Gigabit Ethernet, USB Flashdisk, Serial ATA (SATA), four RS-232 serial ports (two with RS-422/485 capability), four USB 2.0 ports, PS/2 keyboard and mouse, and both SUMIT-A and PC/104 ISA bus expansion. In previous designs, this extensive feature set was typically accomplished by two-board stacks or SBCs with “wings” (form factor excursions). Compared to COM Express modules, which require +12V input and full custom carrier card designs, Aurora saves power by operating off a single +5V input, yet still allows I/O customization in the form of a plug-in SUMIT module. Diamond supports Windows Embedded Standard and Linux 2.6 operating systems. Rugged features include -40˚C to +71˚C operation and a new SO-DIMM solution with optional mounting holes for ruggedness. Diamond’s rugged RAM offering will be manufactured by multiple embedded suppliers. The on board SATA connector interfaces to SSDs use short 3” latching cables and have no need for an external SATA convertor. Diamond chose to convert IDE (PATA) to SATA on board since IDE drives are EOL and SSDs are at risk of higher prices and shorter lifecycle compared to 2.5” SATA SSDs. Conduction cooling is the ideal solution for sealed (waterproof / dustproof) metal enclosures in order to prevent thermal runaway and maximize the reliability and longevity of electronics. Supported operating systems currently include Windows XP and Linux 2.6, with support for additional OS and RTOS (real-time available on request. Get OS) Connected with technology and companies solutions now Aurora is a space-efficient interface for PCI Express x1, USB, LPC and I2Cproviding buses. The combination of SUMIT and PC/104 expansion interfaces is on a growth trajectory to support the largest overall ecosystem Get Connected is a new resource for furtherofexploration into products, and companies. stackable I/O cards, as PCI chips are going EOL in favor of PCI Express chips. System OEMs who use PC/104 I/O technologies cards can now continue Whether to use your goal is to research the latest from a company,I/O speak directly such cards without having to increase their stack height with a bridge card, or completely re-engineer their software anddatasheet stack for PCI-based with an Application Engineer, or jump to a company's technical page, the cards. Pricing in OEM volumes starts in the upper $400s.

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Diamond Systems, Mountain View, CA. (650) 810-2500. [].

goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

XMC Module Mates Virtex-5 FPGA with PCIe Interface and Deep Memory

A set of new XMC-VLX mezzanine modules features a configurable Xilinx Virtex-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCIe interface. Field I/O interfaces connect to the FPGA via the rear J4/P4 connector and/or with optional front mezzanine plug-in I/O modules. Three models provide a choice of logic-optimized FPGAs to match the performance requirements. Cards can be ordered with a Xilinx VLX85T, VLX110T, or VLX155T FPGA featuring up to 155,000 logic cells and 128 DSP48E slices. Each model is ready for use in conduction-cooled systems and offers an option to upgrade with extended temperature range parts suitable for -40° to 85°C operation. Get Connected with technology and companies prov 64 I/O lines are accessible through the rear (J4) connector. Additional I/O Get Connected is a new resource for further exploration into pro processing is supported on a separate mezzanine card that plugs into the FPGA datasheet from a company, speak directly with an Application Engine base board. A variety of these mezzanine I/O cards is available to provide frontin touch with the right resource. Whichever level of service you requir end 14-bit 105 MHz A/D conversions or an interface for CMOS digital I/O, RSGet Connected will help you connect with the companies and produc 485 differential signals, or extra LVDS I/O lines. Large, high-speed memory banks provide efficient data handling. Large 32M x 32-bit DDR2 SDRAM buffers store captured data prior to FPGA processing. The data is directly accessible through the FPGA. Afterward, data is moved to the 1M x 64-bit dual-ported SRAM for high-speed DMA transfer to the bus or CPU. This memory provides direct links from the PCIe bus and to the FPGA. The highbandwidth PCIe 4-lane interface ensures fast data throughput. Acromag’s Engineering Design Kit provides utilities to help users develop custom programs, load VHDL into the FPGA and to establish DMA transfers between the FPGA and the CPU. The kit includes a compiled FPGA file and example VHDL code provided as selectable blocks with examples for the local bus interface, read/writes and change-of-state interrupts to the PCI bus. A JTAG interface allows users to perform onboard VHDL simulation. Further analysis is supported with a ChipScope Pro interface. For easy integration of the boards with embedded Windows applications, Acromag developed a DLL driver software package for comGet demonstration Connected withprograms companies provide and patibility with Microsoft Visual C++ and Visual Basic. Sample files with “C” source easy-to-use tools to products featured in this section. test operation of the module. For connectivity with real-time application programs, Acromag offers C libraries for VxWorks, QNX and other operating systems. Free Linux example programs are also available. The boards start at $5,500 with several options for FPGA logic capacity and extended temperature operation.


Acromag, Wixom, MI. (248) 295-0310. []. Get Connected with companies and products featured in this section.




Mini-ITX Motherboard with Core i7/i5/i3 Processors

A new industrial-grade, Mini-ITX motherboard supports the latest Intel Core i7/i5/i3 processors with LGA 1156 sockets. The Intel 45nm Core i7 and Core i5 700 series processors are quad core CPUs with integrated memory controller. The 32nm Intel Core i5 600 and Core i3 series processors are dual core with integrated graphics and memory controller, and Intel HD Graphics with DX10 support. The AIMB-280 from Advantech is capable of SATA RAID 0, 1, 5 & 10 to ensure reliable storage and system protection for network-intensive applications. The Intel Turbo Boost Monitor application is a Microsoft Windows sidebar gadget that provides a simple display of processor frequency when Intel Turbo Boost technology is active. This further improves performance by allowing processor cores to run at higher frequencies within the available thermal envelope. Supported operating systems are Microsoft Windows Vista 32-bit and 64-bit editions with Service Pack 2, and Microsoft Windows 7, 32-bit and 64-bit editions. The AIMB-280 comes with high connectivity and expansion options including: one PCIe x16 expansion slot, two serial ports, eight USB 2.0 ports and four Serial ATA II 300 Mbyte/s connectors. AIMB-280 also comes with software RAID 0, 1, 5 and 10 support, offering abundant data storage and reliable data protection, and dual PCI Express-based Intel 82578DM and 82583V Gigabit Ethernet ports delivering up to 1000 Mbit/s of bandwidth for network-intensive applications. All this connectivity is packed into a space-saving, power-efficient and cost-effective Mini-ITX form factor. With the graphics engine integrated into the processor, these two-chip solutions provide enhanced graphics performance compared with previous Intel platforms. The integrated graphics controller includes Intel Dynamic Video Memory Technology and Intel Clear Video Technology featuring: MPEG2, WMV9/VC1 and AVC hardware acceleration as well as advanced pixel adaptive de-interlacing. Advantech provides drivers and APIs for different operating systems including GPIO, SMBus, watchdog timer, hardware monitor, panel backlight on/off and brightness control. Supported operating systems include Windows 7, Windows XP, XP Embedded, Windows CE and Linux— hardware drivers for these are readily available.

Advanced Static Code Analysis Tool Integrated with MULTI IDE Write Code

Recode to fix bugs found by Double Check



Recode to fix bugs found in internal testing


Recode to fix bugs found after product deployment




3U VPX Module with Freescale Dual-Core QorIQ P2020 Processor

A user-based static code analyzer is now provided as a standard feature with the Multi Professional tool suite from Green Hills Software. The integration of the DoubleCheck tool increases both developer productivity and code quality while enabling better management and control of code complexity and the overall coding process. This enabling technology is a critical requirement for medical and industrial device development where advanced software development processes are the norm. Application complexity has become the most significant challenge for embedded software developers who need to develop reliable, safe, and secure applications while meeting time-to-market windows. Traditional debugging and testing methodologies fall short when dealing with today’s sophisticated code bases. The DoubleCheck static analysis tool provides a fundamental development and design strategy to cope with the explosion in code complexity. By taking advantage of accurate and efficient analysis algorithms that have been tuned and field proven over the past 28 years in Green Hills C/C++ compilers, DoubleCheck can be used as an integrated tool with Multi to perform compilation and full program defect analysis in the same pass. DoubleCheck is fast enough to be used continuously in a rapid iterative development environment by all developers. Furthermore, unlike other offerings, DoubleCheck automatically uses the same code configuration as is used during the final build process. This allows developers to be certain that the executed code is the same as the code that was “double-checked.” The DoubleCheck static analysis tool helps automate the enforcement of coding standards by measuring and optionally limiting software component complexity by using standardized metrics such as McCabe—making code easier to understand, maintain and test. A range of configuration options adds a number of intelligent quality controls to the DoubleCheck tool’s bug finding mission, including a number of MISRA compliance checks and enforcement of optional but important language standards.

Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

Green Hills Software, Santa Barbara, CA. (805) 965-6044. [].

Advantech, Irvine, CA. (949) 789-7178. [].

An air- or conduction-cooled 3U VPX single-board computer (SBC) is based on Freescale Semiconductor’s dual-core QorIQ P2020 processor. The XPedite5570 from Extreme Engineering Solutions provides a low-power, high-performance SBC for Size, Weight and Power (SWaP) constrained military applications. Consuming less than 20 watts, the XPedite5570 can host nearly any high-performance, FPGA-based, A/D or camera-interfaced XMC module for UAV surveillance applications. The XPedite5570 features include the Freescale QorIQ P2020 processor with two 1.2 GHz Power Architecture e500 cores along with up to 4 Gbyte of DDR3-800 ECC SDRAM and up to 16 Gbyte of NAND flash and 256 Mbyte of redundant NOR flash. The board provides two x4 PCI Express VPX data-plane links as well as two 1000BASE-X Gigabit Ethernet VPX control-plane links to the backplane. There are additionally two optional 1000BASE-T Gigabit Ethernet links to the backplane. Additional interfaces include one XMC/PrPMC site, two serial ports and one USB port. Operating system support includes board support packages (BSPs) for Green Hills Integrity, Wind River VxWorks and Linux. The XPedite5570 is engineered to scale from air-cooled commercial (0° to 55°C) to conduction-cooled rugged (-40° to +85°C) specifications with appropriate shock and vibration testing to satisfy military applications with MIL-STD 810F/G requirements. Pricing varies depending on memory configuration and ruggedization level.




Credit-Card Size COM Express Module Equipped with Atom E6xx Series

The launch of a new Computer-on-Module (COM) brings four major innovations to the market, available in a single product. In addition to being an ultra small form factor COM Express-compatible module (55 mm x 84 mm) with the new Intel Atom processor E6XX, the COM nanoETXexpress-TT from Kontron is also equipped with the newly defined PICMG COM Express COM.0.R.2 Type 10 pin-out that was added to the COM.0 R2.0 specification. With industrial grade components, functional in the range (E2) -40° to +85°C and different options for data storage, it is suitable for use in harsh environments and thus complements the existing portfolio. Finally, the nanoETXexpress COM family gains four new members broadening the scalability from 600 MHz to 1.6 GHz and throughout the industrial-grade temperature range. With the Kontron Computer-on-Module nanoETXexpress-TT customers can benefit from the availability of four PCIExpress lanes of which three can be utilized for dedicated customer-specific interfaces. This enables the use of even more dedicated mini-devices in a semi-custom solution. In addition to LVDS it offers the newly implemented Digital Display Interface (DDI) for SDVO, Display Port or HDMI that allows two displays to be controlled independently. This enables applications to fully utilize up to 50% improved 3D graphic performance compared to previous solutions based on Intel Atom Z5xx processors. Users can also take advantage of the newly implemented SPI (Serial Peripheral Interface) enabling external boot processes that in the past could only be accomplished through the LPC Bus. The Kontron nanoETXexpress-TT also features Intel’s Platform Controller Hub EG20T, allowing the new Computer-on-Module to be configured very flexibly. In addition to three PCI-Express Lanes for custom extensions, the module also supports two different options for data storage: either a robust micro-SD Card socket offering up to 32 Gbyte and 2x SATA II 300 Mbyte interfaces or a planned version with industrial-grade SATA Flash Memory (up to 16 Gbyte) and 1x SATA II 300 Get Connected with technology and Mbyte connector. As a value-added custom service, Kontron will also offer conformal coating for improved electromagnetic interference immunity andnow protection companies providing solutions against corrosion for the Flash version. CAN bus support is available as an optional feature, for example, to support in-vehicle control applications. Get Connected is a new resource for further exploration The Kontron Computer-on-Module nanoETXexpress-TT supports a wide range of operating systems including River VxWorksand 6.8,companies. Linux, Windows intoWind products, technologies Whether your goal is to research the latest datasheet fromfor a company, XP, XPe and WES 7. This comprehensive support of operating systems emphasizes the versatility of this Computer-on-Module making it suitable a varietyspeak of directly with an Application Engineer, or jump to a company's technical page, the applications in diverse vertical markets.

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Kontron, Poway, CA. (888) 294-4558. [].

Low Power PCI-E 2.0 Quad Copper Gigabit Ethernet Adapter Includes Bypass Mode

For applications requiring increased throughput and High-Availability (HA) on server-based systems, American Portwell has introduced a new PCI-E Gen 2 (5 Gbit/s) quad copper Gigabit Ethernet adapter. Based on the Intel 82580EB controller, the NIC-51240 adapter includes a built-in watchdog timer (WDT) to switch to bypass mode for Ethernet ports on host system "hang" or power failure. Configuration of a selectable Normal/Bypass mode and software programmable WDT time-out setting is quick and easy. The NIC-51240 also features both onboard LED and LED pin-out for LAN status and bypass mode to provide variable LED location for system integration; support for most network operating systems, including Linux, FreeBSD and Microsoft Windows; and PCI-E 2.0 x4 host interface. The new Ethernet adapter is PCI-E 2.0 5 Gbit/s solution-ready and backward compatible with PCI-E 1.0 2.5 Gbit/s bus. Its bypass function can be disabled completely for use as a regular Quad GbE port NIC-type adapter. The PCI-E Gen2 offers a definite increase in throughput when compared with the PCI-E Gen 1. The inclusion of quad ports increases network reliability, and the adapter's support for most network operating systems allows for widespread deployment. In addition, NIC-51240's built-in bypass mode (failure or power-off) enables the unit to bypass a failed system and provide maximum uptime for the network. The Intel 82580EB controller operates at an economically low powered 4.2W and VMDq support of 8TX and RX queues of up to 8 VMs per port helps reduce I/O bottlenecks and latency, and increase throughput. American Portwell, Fremont, CA. (510) 403-3399. [].

goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searchingSystem for. Embedded Board with Dual-

3.5-Inch ECX Core Atom D525

Achieving increased performance while keeping power consumption in check is the aim of a new Get Connected with technology and companies prov 3.5˝ ECX compact Get Connected is a new resource for further exploration into pro embedded system datasheet from a company, speak directly with an Application Engine board that includes in touch with the right resource. Whichever level of service you requir the performance en- Get Connected will help you connect with the companies and produc hancing advanced features gained from Intel’s second-generation dual-core Atom processors. The new compact (146 mm x 105 mm) PEB-2771VG2A from American Portwell is suitable for a range of general applications such as medical devices, industrial automation and handheld gaming as well as embedded applications. Based on Intel’s dual-core Atom processor D525 with Intel NM10 Express Chipset, the PEB-2771VG2A board supports DDR3 800 SODIMM system memory up to 4 Gbyte, dual display via VGA and LVDS, dualGet Gigabit Ethernet, 12V Connected withonboard companies and DC input, two SATA interfaces, one 44-pin IDE connector, products featured in this section.Type II Compact Flash socket, six USB ports, four serial ports and GPIO. The dual-core 1.8 GHz processor can handle most essential applications in the low-power segment.


American Portwell, Fremont, CA. (510) 403-3399. [].

Get Connected with companies and products featured in this section.




Busless PMC Carrier Card Allows Use of FPGA Modules in Stand-Alone Mode

A busless PMC module carrier card allows use of a PMC module in an independent stand-alone mode. The APMC4110 carrier card from Acromag delivers power to a PMC module and regulates the PCI bus start-up sequence to prevent a system lock-up by the connection to the local bus. The APMC4110 is suitable for custom computing applications based on a re-configurable FPGA module operating independently of VME, CompactPCI, or other bus-level resources. With the busless carrier card, no expensive card cage or other computer chassis is required. The Virtex-5 FPGA modules offer plenty of computing power for engineers who would like to apply the DSP and logic capabilities without all the costly overhead of a full embedded system with a backplane, rack, CPU card and more. Acromag’s PMC-VFX module even has a hard-core PowerPC on the configurable FPGA to provide additional processing abilities for a stand-alone implementation. As a single-slot non-intelligent carrier, the board acts simply as an adapter to route signals to and from a PMC module. The user has full access to the field I/O via two 50-pin ribbon cable connectors. Using an external power supply, this carrier card allows use of any industry-standard PMC module. The onboard DC-DC converter creates +3.3VDC from the external +5VDC source, lowering the number of external power connections required. For troubleshooting, a 14-pin Xilinx JTAG connector facilitates boundary scan debugging. Users have access to the TDI, TDO, TCK and TMS signals. Also, a manual reset button allows the user to force a PCI reset when needed. The voltage monitor helps prevent code execution errors during power-up, power-down, or potential brown-out conditions if the +5V DC supply dips too low. Pricing starts at $275. Acromag, Wixom, MI. (248) 295-0310. [].

Compact MicroTCA Platform Holds Four Double-Width AMC Modules

A MicroTCA platform specifically designed for up to four high-end AdvancedMCs features a 10 Gbit/s Ethernet switched backplane enabling high data flow rates. In the maximum configuration with four processor modules, the 5U OM6040D platform from Kontron hosts up to 16 Intel Xeon processor cores and 96 Gbyte of RAM. Thus, the compact and modular 42HP/5U MicroTCA platform is suitable for applications with demands on performance and data throughput. Applications in these spaces will benefit from the densely packed, parallel processing power of up to four high-performance doublewidth AMC modules, like the Kontron AM5030 and the high-speed fabric of 10GbE on the backplane. Target applications can be found in embedded markets with a high demand for processing capacity, high communication bandwidth and high availability. The Kontron OM6040D platform is based on a compact chassis (266 x 428 x 365 mm), which provides four double-width slots for AdvancedMC modules (up to 80 watts) and one slot for the MicroTCA Carrier Hub (MCH). The Kontron OM6040D comes in a cost-optimized design with two pluggable AC/DC power supply units, integrated power management and fan control on the backplane. The fans are housed in a removable fan tray, which is easily accessible from the front for maintenance purposes. Kontron, Poway, CA. (888) 294-4558. [].

Programmable DC Motor Controller Targets Mobile Robot & Automation Applications

A new intelligent controller is capable of directly driving two DC motors up to 150 amps each at up to 50V. The HDC2450 from Roboteq is targeted at designers of mobile robots, Automatic Guided Vehicles (AGVs), or any other high power motor control application. The controller accepts commands from analog joystick, standard R/C radio, USB or an RS-232 interface. The controller can be used by way of the USB or serial port to design fully or semi-autonomous robots by connecting it to single board computers, wireless modems or Wi-Fi adapters. The HDC2450 incorporates a Basic language interpreter capable of executing over 50,000 Basic instructions per second. This feature can be used to write powerful scripts for adding custom functions, or for developing automated systems without the need for an external PLC or microcomputer. The controller’s two channels can be operated independently or combined to set the direction and rotation of a vehicle by coordinating the motors on each side (tank-like steering). The motors may be operated in open or closed loop speed or position modes with a 1 kHz update rate. The HDC2450 includes inputs for two Quadrature Encoders up to 250 kHz, for precise speed and traveled distance measurement. The HDC2450 features intelligent current sensing that will automatically limit the power output to 150A in all load conditions. The controller also includes protection against overheat, stall and short circuits. The controller includes up to 11 analog, 19 digital and 6 pulse inputs. Eight 1A digital outputs are provided for activating, lights, valves, brakes or other accessories. The controller’s operation can be optimized using nearly 80 configurable parameters, such as programmable acceleration or deceleration, amps limits, operating voltage range, use of I/O and more. A free PC utility is available for configuring, tuning and exercising the motor. The controller can be reprogrammed in the field with the latest features by downloading new operating firmware from Roboteq’s web site. The HDC2450 is built into a compact 9.0”L x 5.5”W x 1.6”H (228 mm x 140 mm x 40 mm) robust extruded aluminum case, which also serves as a heat sink for its output power stage. The large fin area ensures sufficient heat dissipation for operation without a fan in most applications. Pricing is $645 in single quantities, complete with cable and PC-based configuration software.

Roboteq, Scottsdale, AZ. (602) 617-3931. [].




1 GHz PC/104 SBC Supports Networking and Communications

A PC/104-compatible 1 GHz single board computer (SBC) is designed for headless space- and powerlimited systems in medical, communications, security, transportation, utilities, Mil/COTS and industrial test/measurement applications. The PCM-VDX-2-512 from WinSystems has two Ethernet, four USB 2.0 and four asynchronous serial channels plus expansion connectors for both PC/104 and Mini PCI I/O cards. The board measures 90 mm x 96 mm (3.6” x 3.8”), draws 5.5W, and will operate from -40° to +85°C without a fan. The PCM-VDX-2-512 is based on the DM&P ultra-low-power Vortex86DX processor and is populated with 512 Mbyte of soldered-on DDR2 SRAM plus a 1 Mbyte SRAM that can be battery backed. Its x86 architecture runs Linux, DOS and other x86-compatible operating systems as well. This SBC is supplied with downloadable drivers that are available free of charge from WinSystems’ website. Electrostatic Discharge (ESD) suppressors rated to ±15kV are included on the USB, Ethernet and serial data ports for additional protection and will withstand multiple ESD strikes. Additionally, the USB ports have in-rush and over-current protection. All four independent, full-duplex serial channels support RS-232/422/485 levels and operate at data rates up to 115.2 Kbit/s. The PCM-VDX-2-512 also has a PATA controller that will support a Compact Flash card and an IDE drive. Other onboard peripherals include 16 lines of TTL-compatible digital I/O, PS/2 keyboard and mouse controllers, LPT interface, real-time clock, watchdog timer, activity LEDs, and a piezo speaker for audio annunciation of the BIOS status beep codes. Mini PCI and PC/104 connectors support expansion I/O cards for wireless networks, video, etc. With this diverse range of functions, many applications will not require any additional I/O cards. Get with technology and WinSystems can customize this SBC for OEM applications either by depopulating certain features or by Connected adding soldered-on flash memory, companies providing solutions now a CF card retention clip, and/or a Mini PCI video card. The processor speed and amount of SDRAM can be reduced to lower the price and power Get Connected is a new resource for further exploration consumption as well. The PCM-VDX-2G-512 is priced at $342 in OEM quantities.

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WinSystems, Arlington, TX. (817) 274-7553. [].

Two-Slot Conduction-Cooled 6U VPX Development Platform for Rugged Designs

A two-slot 6U VPX (VITA 46) conduction-cooled chassis provides system engineers with an inexpensive desktop or lab bench platform to jump-start software or hardware development when using Freescale- or Intel-based CPU boards. The XPand1010 from Extreme Engineering Solutions allows customers to utilize fully rugged, conduction-cooled cards in a small footprint, low-cost development chassis. Customers can then install those same 6U VPX cards into deployable ATR or similar chassis with no changes to the 6U modules. This is in contrast to the traditional model of development for conduction-cooled systems, in which early work is performed using non-rugged, air-cooled cards that are mechanically and thermally incompatible with the final deployed system. The XPand1010 hosts up to two 6U VPX conduction-cooled cards, providing fabric interconnect between the two slots, as well easy access to Gigabit Ethernet, SATA, USB, DVI, and serial port I/O from one or both of the installed 6U VPX SBCs. The XPand1010’s design eliminates card cages, rear transition modules, and large noisy fans typically found in air-cooled development chassis. Powered by an external ATX supply and featuring an integrated conduction-cooling system, the XPand1010 chassis is ideal for office desktop or lab bench use. The conduction-cooled nature of the chassis allows for near-silent operation on a desktop or lab bench. Front and rear acrylic panels provide an impressive showcase for safe viewing of the installed cards and can be removed. The complete XPand1010 development system includes a backplane with integrated I/O connectors, conduction cooling system, and power supply and is priced at $3,295. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. 6U, OpenVPX I/O Cardlevel for Multifunction Whichever of service you require for whatever type of technology, Connected will help you connect with the companies and products I/O and Serial Get Communications you are searching for.

A new single slot, OpenVPX, 6U, multi-function I/O and serial communications card supporting VME, Gigabit Ethernet and Serial RapidIO (sRIO) or PCI Express (PCIe) control interface options Get Connected with technology and companies prov enables users to take advantage of the Get Connected higher speed, switched fabric commu- is a new resource for further exploration into pro datasheet from a company, speak directly with an Application Engine nication architectures, offering significantly in touch with the right resource. Whichever level of service you requir greater capability. TheGet 67C3 from North Atlantic Industries Connected will help you connect with thecontains companies and produc six independent module slots, each of which can be populated with a function-specific module and can now be controlled by VME, dual Gigabit Ethernet and sRIO or PCIe. This design eliminates the need for multiple, specialized, single function cards by providing a single board solution for a broad assortment of signal interface modules such as Synchro/Resolver/ LVDT/ RVDT Simulation and Measurement, A/D, D/A, Discrete/Differential/TTL/CMOS I/O, RTD, Encoder and communications such as RS-232/422/485, MIL-STD-1553, ARINC 429 and CANBus. This approach increases packaging density, saves enclosure slots, reduces power consumption and adds continuous background BIT testing. Further, the 67C3 provides a highly cost-effective, off-the-shelf alternative to a custom-built solution. with companies and Get Connected The 67C3 is available an operating temperature range of -40° products featured in with this section. to +85°C. Pricing for a rugged, conduction-cooled 67C3, configured with 96 programmable 0 to 60V discrete channels, starts at $9,982 in quantities of 100+, within 12 to 14 weeks.


North Atlantic Industries, Bohemia, NY. (631) 567-1100. []. Get Connected with companies and products featured in this section.



with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




Actel Corporation.......................................




Mini-, Nano- and Pico-ITX Showcase........................................10......................................

American Portwell Technology, Inc............... End One Stop Systems. of..................................... Article Products

Avnet Embedded........................................ Get Connected with companies and products featured in this section. CM Computer.............................................

Phoenix International................................... 4.....................................

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with companies mentioned in this article. Red Rapids, Inc.......................................... 16...........................................

Get Connected with companies and products featured in this section.

Get Connected with companies mentioned in this article. Sealevel Systems.......................................

IEI Technology............................................ 17.........................................

The Math Works, Inc................................... 2.................................

Innovative Integration.................................. 55...........................

Themis Computer.......................................

Interface Concept.......................................

TRI-M Systems..........................................

ISI Nallatech Inc......................................... 44...................................

Viking Modular Solutions Sanmina-SCI Corporation.........4..........

Kontron America.........................................

XTech........................................................ 37............................

Cogent....................................................... 36...................................

Logic Supply, Inc........................................ 25................................

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.



We are conscious that not all military ŝŶƚĞŐƌĂƚŽƌƐǁŝůůƌĞƋƵŝƌĞĂƚŽƉĐůĂƐƐdZ ĐŚĂƐƐŝƐ ůŝŬĞ ŽƵƌ ŶĞǁ ^ŝdž,Ğdž ƐĞƌŝĞƐ͕ ďƵƚ ǁĞ ĐĂŶ ĞŶƐƵƌĞ ƚŚĂƚ ŽƵƌ ĨŽƌƚƵŶĂƚĞ ĐƵƐƚŽŵĞƌƐ ǁŝůů ĞŶũŽLJ ƚŚĞ ĞdžƉĞƌŝĞŶĐĞ͘ /ƚ ŚĂƐ ďĞĞŶ ĚĞŵŽŶƐƚƌĂƚĞĚ ŝŶ ƚŚĞ ĮĞůĚ that ATR enclosures are crucial to your end system reliability and performance. dŚĞƌĞĨŽƌĞǁĞŚĂǀĞĚĞǀĞůŽƉĞĚĂƐƵƉĞƌŝŽƌ ƉƌŽĚƵĐƚ ƚŽ ŐƵĂƌĂŶƚĞĞ ƚŚĂƚ LJŽƵƌ ƉĂLJůŽĂĚ ĞůĞĐƚƌŽŶŝĐƐĂƌĞŵĂƚĐŚĞĚǁŝƚŚĞdžĐĞůůĞŶĐĞ͘


¾ ATR, 7 Slot, 800W PSU


All our chassis products are delivered Tested and Certified by independent authorized Labs per MIL-STD461E & MIL-STD-810F for immediate deployment in US Navy & US Air Force military Fighters and Helicopters.

- Contaminant-free enclosure - Available in ½, ¾ & 1 ATR size - VPX, VME & cPCI ready ͲĐĐĞƉƚƐŽŶĚƵĐƟŽŶ& Air-cooled 6Us Ͳ&ůĞdžŝďůĞƚŽƉΘďŽƩŽŵ/ͬKǁŝƌŝŶŐ Ͳ/ŶƚĞŐƌĂƚĞĚdĞŵƉĞƌĂƚƵƌĞŽŶƚƌŽůhŶŝƚ Ͳ^ŝdžŝŶƚĞƌŶĂů,ĞĂƚdžĐŚĂŶŐĞƌƐ ͲhƉƚŽϭ͘ϴ<tƚŽƚĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ - Up to 150 W per slot ͲƌĂŵĂƟĐĂůůLJŝŶĐƌĞĂƐĞƐƉĂLJůŽĂĚDd& ͲϮhƐĞƌĚĞĮŶĞĚW^hŽƵƚƉƵƚƐ ͲϮϬΣůĞƐƐƚŚĂŶŚĞĂƚĞdžĐŚĂŶŐĞƌdZƐ ͲϰϱΣůĞƐƐƚŚĂŶĐŽŶǀĞŶƟŽŶĂůdZƐ Ͳ^ƚĂŶĚĂůŽŶĞůŽǁǁĞŝŐŚƚƐŽůƵƟŽŶ ͲƵƐƚŽŵŝnjĂďůĞƚŽƐƉĞĐŝĮĐƌĞƋƵŝƌĞŵĞŶƚƐ ͲDŽƵŶƟŶŐdƌĂLJǁŝƚŚƋƵŝĐŬƌĞůĞĂƐĞƐLJƐƚĞŵ

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