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The magazine of record for the embedded computing industry

October 2010


Smart Grid

PCI Express—New Applications, New Generation Solid State Drives Challenge Old Assumptions Smarter Chips Ease System Management An RTC Group Publication

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48 Core 2 Duo Embedded Computer Now with QNX Support


51 EBX SBC Features Intel Core 2 Duo Processor



5Editorial The World of Embedded Systems Continues to Expand—but How Far into the Consumer Realm?

Insider 6Industry Latest Developments in the Embedded Marketplace Form Factor Forum 10Small New Challenges Face Even Smaller Boards & Technology 46Products Newest Embedded Technology Used by Industry Leaders



New Developments in Embedded Processors

System Monitoring and Management


Intended or Not, Intel and ARM Appear More Directly Competitive Tom Williams

Technology in Context Solid State Storage

Intelligent Mixed Signal 30Using FPGAs for Hardware Platform Management Mark Overgaard, Pigeon Point Systems

TECHNOLOGY DEPLOYED Technologies for the Smart Grid

Ounce of Prevention: Bringing the HDD Form Factor Monitoring to the Grid 34AnReal-Time SSDs in Embedded System Design 16 “SWaP” Adrian R M Proctor, Viking Modular Solutions


Aboard! The PCI Express – 3 20 AllGeneration Akber Kazmi, PLX Technology

Supreet Oberoi, Real-Time Innovations

Phones for the Smart(er) Grid 38Smart not Enforcement, is Key to Smart Grid Success 42Information, Eugene Fodor, Digi International

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Area Network Speeds Data 24 System Transfer between Servers with PCI Express Joey Maitra, Magma

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PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

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The World of Embedded Systems Continues to Expand—but How Far into the Consumer Realm?

Tom Williams Editor-in-Chief


he editorial page in a magazine can, in our opinion, be used in a number of ways. Mostly it is used to express an opinion or perspective regarding the editorial focus of the publication—in this case, embedded systems in all their variegated glory. We do sometimes get feedback from these pages but we like to hope that whatever views are expressed here help to engage thought on whatever is the topic at hand. This month, we are moved to simply express some questions for which we have no hard and fast answers. However, such questions may help us all toward some perspective on what appears to be the changing universe of what we think of as “embedded systems” and the burgeoning variety of processors that power them. I’ll start off with a riddle that may at first seem unrelated—what do WindowsCE, Linux and Java have in common? Answer—they were all originally conceived with no thought to their use in embedded or real-time systems. The first version of WindowsCE was developed for miniature laptops that would today be compared to netbooks. At the time, these devices simply flopped in the market. Linux was developed as a free, open-source and improved version of UNIX, and Java was targeted to be a better object-oriented environment that could be quickly ported to large numbers of different systems. Yet developers in the embedded community were so enthusiastic about the attractive aspects of all three of these technologies that they spent man-millennia of effort to adapt them for use in embedded and real-time systems. In so doing, they greatly expanded the scope of what we today would think of as an embedded system from a small control module running a special-purpose RTOS to the vast world of powerful, semi-autonomous connected systems we know today. The use of these much larger and more powerful software environments has also been fueled by the advances in processor power, which in addition to multicore and 64-bit architectures has also ridden Moore’s law to bring very powerful computing capacity ever further down into very small devices with continuous connectivity all the way up to huge enterprise servers. If this were all that was going on, it would be easy to just say, “Well that is now the universe of embedded systems.” But it gets bigger. At one point, consumers had no need to be aware of the fact that their cars, their appliances, their cell phones and their stereos were all running on little programmed microcontrollers. The trick was to “hide the computer behind its own usefulness.”

But now increased connectivity and handheld and mobile devices are migrating the PC experience into contexts in which the user of a cell phone, a car or a TV is very much aware that he or she is dealing with a computer and that in many cases that computer is dedicated to a particular purpose . . . except that increasingly many other purposes can be addressed at the same time. With an Internet TV you can monitor your manufacturing process and check inventory while watching “Glee.” You can do the same with your iPhone, your iPad or any number of PC-based, Android-enabled phones and tablets. GPS-based applications can learn from your interactivity and guide you to restaurants and stores in a strange city. The world of apps seems unlimited. And at the beginning of this page I was going to wonder, “Are all these devices legitimate topics for an embedded systems publication?” My answer is, “For an industrial and engineering publication, no, not really.” They cannot be totally ignored as adjuncts to a wider embedded infrastructure, but their design is pretty well set and not an issue for the readers of RTC. More specialized handheld devices that operate in a connected context may be a different story. Behind all these things, however, lies an infrastructure whose design and operation as we get into such areas as cloud computing and “device to cloud” becomes ever more vital—in terms of the devices that talk to the cloud and the kinds of applications they support. It is also true that we can no longer limit our consideration of what constitutes an embedded system to isolated small modules and devices and control elements in larger systems and machines—and then say, “Oh yeah, they are also connected to the Internet or a local area network.” The synergistic effect of that connectivity must also be considered as an integral aspect of the embedded system—and that includes their communication with what we call the “enterprise,” or “IT,” because that is often where the ultimate application is located. PCs remain PCs—except of course when they’re embedded PCs or x86 processors, and there are a LOT of them, so we need to differentiate in terms of use and functionality. For example, in the case of the Smart Grid, there is a huge amount of embedded intelligence, networking and security on the infrastructure side. Yet without the consumer interface on the user side, much of the potential benefit of the Smart Grid cannot be realized. The boundaries between industrial and consumer in terms of embedded still definitely exist, but in some places they have become a little bit blurry. RTC MAGAZINE OCTOBER 2010



INSIDER OCTOBER 2010 Wireless USB 1.1 Specification Now Available The Wireless USB Promoter Group has announced the completion of the Wireless USB 1.1 specification, the technical map for product developers to bring the next generation of Wireless USB products to the market. Wireless USB 1.1 delivers key performance enhancements to Wireless USB technology, as well as added UWB upper band support for frequencies of 6 GHz and above, and offers backward compatibility with Wireless USB products currently in use by consumers. Wireless USB is evolving with optimized power efficiency and ease of use. Lower idle power requirements and improved battery life enhance Wireless USB power efficiency, and the new association model offers support for Near Field Communication (NFC) and proximity-based association, making Wireless USB even easier to install and use. “The Wireless USB 1.1 specification is the next step in Wireless USB technology,” said Jeff Ravencraft, USB-IF president and chairman. “Consumers want a fast, easy-to-use solution to wirelessly transfer content from PCs to devices. Wireless USB 1.1 is the solution supporting robust, high-speed wireless connectivity among devices.” To download the Wireless USB Revision 1.1 specification and adopter agreement, visit http://

Fluffy Spider Technologies Joins ARM Connected Community

Fluffy Spider Technologies, a provider of enhanced user interface technology for embedded systems, has announced membership in the ARM Connected Community. As part of the ARM Connected Community, Fluffy Spider Technologies will gain access to a full range of resources to help in marketing and deploying innovative solutions to help developers to get ARM Powered products to market faster. Fluffy Spider Technologies’ FancyPants user interface framework for consumer electronics and multimedia devices is now available and optimized for ARM-based devices and systems. The latest version of this multimedia applications framework separates user interfaces from the applications that use them through scriptable Autonomous User Interface (AUI) technology. This revolutionary approach to UI design and implementation goes



beyond the custom themes, icon sets and color schemes common on many consumer electronics, mobile phones and other intelligent devices, by delivering complete control of the end user experience to developers, integrators and other ecosystem participants. The ARM Connected Community is a global network of companies aligned to provide a complete solution, from design to manufacture and end use, for products based on the ARM architecture. ARM offers a variety of resources to Community members, including promotional programs and peer-networking opportunities that enable a variety of ARM Partners to come together to provide end-to-end customer solutions.

Zigbee Alliance Surpasses 100th Zigbee Certified Product Milestone

The ZigBee Alliance has surpassed the 100th ZigBee Certified product milestone as rising popu-

larity and demand for innovative ZigBee products increases across the world. According to a recent report by ON World, ZigBee has been adopted by more than 350 global manufacturers with annual revenues exceeding $1 trillion dollars. ZigBee achieved several critical milestones over the last year, building on the momentum realized by ZigBee members in the energy, commercial and consumer electronic marketplaces. With approximately 400 members across a wide spectrum of industries, the Alliance has enjoyed success as an open-standard for product manufacturers wanting to offer consumers smarter and greener products that offer easyto-use control capabilities. With more than 100 ZigBee Certified products on the market—and growing—many manufacturers are using the standard as part of their product portfolio, delivering control benefits offered by ZigBee to millions of consumers and businesses. These products include: • ZigBee Smart Energy – ZigBee provides the core technology for monitoring, controlling and automating the delivery and smart use of energy and water. More than 64 ZigBee Certified products are available today and include a range of products covering energy service portals, meters, displays, programmable communicating thermostats and smart plugs. • ZigBee Home Automation – With 24 Certified products providing the easy-to-use control offered by ZigBee Home Automation, consumers, do-it-yourself and professional installers can easily create smart homes. These smart homes give consumers more control of home appliances, lighting, security, heating and cooling systems, allowing them to use less energy.

• ZigBee Telecom Services – Launched in 2010, ZigBee Telecom Services enables delivery of value-added services ideally suited for mobile network operators, businesses and government agencies. Today 13 ZigBee Certified products offer a variety of communication platforms, access points, terminals and location nodes. This year the Alliance expanded into new industries with the release of ZigBee Remote Control, ZigBee Telecom Services and ZigBee Health Care specifications. The Alliance also began development of a new standard, ZigBee Retail Services. With each standard completed, more manufacturers will seek the official ZigBee Certified designation, further expanding the ZigBee ecosystem of control products for consumers and businesses.

Wave and LynuxWorks Demonstrate Self-Encrypting Drives in a Secure Virtual Environment

Wave Systems and LynuxWorks have announced their collaboration on the use of a selfencrypting hard drive to provide data-at-rest protection alongside the LynxSecure separation kernel and hypervisor securely running multiple operating systems on a PC. This capability solves the complexity and performance issues typically associated with encrypting data on virtual machines running different operating systems. Virtualization allows IT to run multiple virtual machines on a single physical machine. Each virtual machine shares the resources of a single computer across multiple environments, allowing different operating systems and multiple applications

to run simultaneously. Although virtualization technology isn’t new, it’s becoming increasingly viable as computing becomes more powerful and disk capacity increases. Secure virtualization helps to partition traditionally unsecure environments like Internet browsing from corporate applications and data that are housed on the same PC. The use of virtualization in a laptop (made possible via a hypervisor) can make it difficult to protect data using software encryption, which is a key method for securing data on laptops. A separate software encryption program must run on each virtual

machine. Self-encrypting hard drives (SEDs) are a better option; they are more secure and because encryption is “built in,” data is protected at all times, regardless of which virtual machine or operating system is used. The result: laptop data is always protected if a device is lost or stolen. The combination of an SED with a secure virtualization solution could offer laptop users the best of both worlds. As many companies are evaluating client-side virtualization as part of their overall security strategy, SEDs should be given strong consideration.

Eurotech Launches Cloudbased Services for Secure and Reliable Device Data Management

Eurotech has announced the availability of cloud computing services to manage Eurotech devices and deliver data, regardless of where devices are deployed. The cloud-based offering, coupling the Isidorey device cloud with the Eurotech Everyware Software Framework (ESF), allows organizations to access Eurotech devices as well as cloud computing connectivity services, for fast and simple device deployment through Eurotech, a single, trusted point of contact.

With the Isidorey device cloud and ESF enabled hardware from Eurotech, businesses can concentrate on their application development to meet their market requirements while Eurotech provides the embedded hardware platforms and devices, the intelligent software framework and communications capabilities. By leveraging this cloud-based solution, customers can remain focused on their core competencies, not on building, operating and maintaining a device data infrastructure delaying time-tomarket and increasing overall project costs. The Isidorey device cloud

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at Closing Price 52 Week Low 52 Week High Market Cap

RTEC10 Index



Adlink Technology



















Interphase Corporation










Mercury Computer Systems





Performance Technologies





PLX Technology





RadiSys Corporation





Company Market Performance

Elma Electronic

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. Do not use for buying or selling of securities.




service simplifies access, control and management of devices in an enterprise environment, whether they are deployed in a distributed campus environment, spread across a country on utility poles, or dispersed to locations around the world. The Isidorey device cloud offering is based on proven public cloud services for data storage and connectivity, which Eurotech manages for each customer engagement.

Cortus and RivieraWaves in Partnership for a Range of Bluetooth IP Solutions

Cortus and RivieraWaves have announced a partnership to provide a range of complete, turnkey, easy to integrate, Bluetooth IP solutions. One of the platforms coming out of this partnership is a complete, fully qualified, Bluetooth Low Energy solution,

specifically designed for ultralow-power systems requiring exceptionally long battery life. The IP is a complete solution combining RivieraWaves’ RF, modem and baseband hardware and the protocol stack running on the integrated APS3 processor from Cortus. All these elements form a common reference platform including bus system, memory interfaces and peripherals. This ready-to-use integrated solution, called the RiCoW Platform, ensures first time success and reduces time-to-market when used as the backbone of an SoC, or as a subsystem in a bigger SoC such as baseband or application processors. RivieraWaves provides a set of Bluetooth IP blocks composed of basebands, modem, radio and software protocol stack to address Bluetooth 2.1+EDR, Bluetooth 3.0 and Bluetooth 4.0

(aka Bluetooth low energy) standards for integration into System on Chips. RivieraWaves recently announced the world’s first qualified Bluetooth low-energy baseband IP. The Bluetooth IP blocks are flexible to accommodate the requirements of any Bluetooth enabled product such as sport & fitness wireless sensors, medical wireless sensors, watches, remote controllers, home/building control & automation devices, set top boxes, mobile phones, PCs/ laptops and audio peripherals (mono/stereo headsets, hands free car kits, stereo speakers).

The Future Underlying Growth for I/O Modules Expected to Recover

The total world market for I/O modules was $6.1 billion in 2009, 15% less than in 2008. The

future underlying growth primarily comes from the performance of the control systems markets that use I/O modules; it varies with the control platform, including PLC, DCS and PC control. According to UK-based IMS Research, from 2009 to 2014, faster than average growth rates, (CAGRs of 8.9% and 10.3% respectively) are forecast for PLC and PC-based I/O. They are used mainly in discrete industries, which were hit badly particularly by the situation in the automotive industry and machinery production from the end of 2008. However, these industries benefited from large government stimulus packages in all major industrial nations in 2009, so that machinery production has been growing again since early 2010. The PLC and PC-based I/O market, in turn, has shown signs it will grow from 2010.

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Colin McCracken & Paul Rosenfeld

New Challenges Face Even Smaller Boards


ne of the primary driving forces behind the SFF revolution has been Moore’s Law. For those few of you who may not be acquainted with this little jewel, it states that transistor densities double roughly every 18 months. That means that next year’s chips will pack twice the number of transistors into the same die space. Processors we were using only ten years ago would take 2% of the same die today. And it means that next year’s processors will need to integrate big chunks of functionality to fill the available space. Why not just make the die smaller? With today’s 1000-plus ball microBGA packages, most of these designs are pin-limited. That means the space required for the I/O pin pads defines the size of the die, not the number of transistors required for the basic functionality. Hence, all those extra transistors are free—sort of. Over the last decade, the trend has been to fill this extra space with no-brainers—first with lots of cache and next by adding processor cores. Simple to design and very low market risk. But in addition, we’ve seen functionality that was originally supplied through additional components sucked into the processor or, more often, the chipset. We’ve become used to chipsets with Ethernet MACs, lots of USB ports, SATA and graphics controllers. Remember that Moore’s Law applies to chipsets as well as processors. Finally, in just the last year or so, we’re seeing the chipset logic itself get sucked onto the processor die. The great advance of the new Tunnel Creek parts is because the transistors that implement what used to be called the northbridge or memory hub, consisting primarily of a memory controller and a graphics controller, got sucked into the processor chip itself, saving board space big time. This evolution has translated directly into smaller and smaller CPU boards. SBCs have moved from the decidedly unsmall EBX form factor of the late 80s (203 x 146 mm) to today’s smallest expandable SBC standard, Pico-ITXe, at 100 x 72 mm without any loss of functionality. And the evolution of Computeron-Module (COM) technology takes the size down even smaller,



with today’s smallest COM, CoreExpress at 58 x 65 mm. All these advances in size are completely due to Moore’s Law. But there is a threat on the horizon. Actually, it is already here—one that we have been dealing with for some time. Just as chips are pad-limited, the challenge in these very small boards has been how to get all the I/O off the board. Standard PC-style connectors such as Ethernet, USB, audio, video and/or graphics displays and power take far too much space for even the larger of the small form factor boards. Some years ago, the smaller boards, such as PC/104 began using pin headers for virtually all I/O, using transition cables to convert from a pin header to a PC-style connector. While this solution frequently created a cable rats nest in embedded systems (and the resulting manufacturing / maintenance nightmare), it worked. But with sizes shrinking even further, the .1 inch, or even the 2 mm pin headers are simply too large to support the amount of I/O on some of these small boards. Something new is needed. But, you might say, COMs don’t have that problem. COMs pass all the I/O through one or more higher density connectors to the baseboard. But in essence, they simply “pass the buck” from the CPU board to the baseboard. Even if COMs were to shrink another 50%—not an impossibility if you follow Moore’s Law through the next 3-5 years—getting the I/O off the baseboard will limit overall size reductions. What good is a tiny COM with a super dense processor chip on an EBX-sized baseboard? And in this case, dumping more functionality on the baseboard is far from free and may have little or no use in the end application. It’s time for a “from scratch” creative solution that will allow SFF processor boards to continue to shrink as processor densities grow. Intel’s Light Peak optical initiative is promising, but lots of questions remain—particularly, how can it be applied to embedded applications where I/O feature content varies from board to board? Our problem is size, not speed. How will this help? Whatever the solution, it must be pervasive and ubiquitous— and supported by connector and board manufacturers everywhere. Let’s get going.








editor’s report New Developments in Embedded Processors

The conception of what is an “embedded” system is expanding, often blurring the line between commercial, consumer and industrial systems. As semiconductor vendors try to track this expanding world they are going to bump into each other.

x16 PCIe DMI


PCI Express System Agent













2ch DDR3

PECI Interface to Embedded Controller

Notebook DP Port


by Tom Williams, Editor-in-Chief

here appears to be a growing rivalry emerging between Intel and ARM, although neither company nor company’s camp of users seems to want to acknowledge it publically. Maybe they are just aggressively pursuing their market goals and bumping into each other with increasing frequency. At any rate, it’s all very gentlemanly. Intel’s major move, announced at the Intel Developer Forum in September, is the second generation of its Core 2010 family, which was rolled out as products at CES last January. Code named “Sandy Bridge,” the second generation has been announced as a new microarchitecture with actual products to follow (Figure 1). It is being implemented in 32nm technology and consists of enhancements to the Core 2010 architecture. This is following Intel’s now well-known “Tick-Tock” model in which the Sandy Bridge architecture now being implemented in 32nm can be—if the model holds—expected to eventually be incarnated in 22nm. Performance enhancements over the previous generation are being implemented with improvements to the micro-



Intended or Not, Intel and ARM Appear More Directly Competitive

2011 PCH

architecture. For example, the addition of a second load port, a new scheduler and bigger out-of-order execution buffers results in the ability to execute more instructions per clock. In addition, a new cache and internal ring bus design provides 4x 32 byte paths between cores, cache, memory controller and graphics. This means increased bandwidth and reduced latencies for internal data transfers as well as more efficient cache access. Dynamic power sharing between the cores and the graphics section increases energy efficiency thanks to a next-generation Turbo Boost. When processor temperature drops during periods of light load, some sections can then be run above normal load limits for short periods of time. These limits are set by fuse settings, sensors and algorithms. The next-generation Turbo Boost allows the power usage to be more dynamically shared across processor subsystems. Integrating and enhancing graphics processing is a big priority for Intel in its latest generation processors. The Sandy Bridge graphics processor is centered around an array of unified executions units

Figure 1 The new Sandy Creek architecture has enhanced instruction execution and graphics processing and implemented a circular buffer among the cores and caches to reduce latency for internal data transfers.

for 3D graphics, texture rendering as well as hardware acceleration for video decoding and encoding. Up to four independent or concurrent displays can be run simultaneously on a single system, and there is a wide variety of display outputs including: HDMI, DVI, VGA, DP, SDVO or LDVS. Intel is including its Advanced Vector Extensions (AVX) instructions for improved floating point execution. This is expected to enhance audio and video processing as well as radar and other advanced signal processing applications. The prior generation Core 2010 family had versions in power ranges from 18W to 35W. So far, Intel has not announced the power characteristics of actual silicon products based on Sandy Bridge. One got the distinct impression from watching the demos and presentations at IDF that Intel is strongly focused on the mo-

editor’s report

Cortex - A15 MPCore ARM CoreSight Multicore Debug and Trace Generic Interrupt Control and Distribution FPU/NEON Data Engine

FPU/NEON Data Engine

FPU/NEON Data Engine

FPU/NEON Data Engine

Integer CPU Virtual 40b PA

Integer CPU Virtual 40b PA

Integer CPU Virtual 40b PA

Integer CPU Virtual 40b PA

L1 Caches with ECC

L1 Caches with ECC

L1 Caches with ECC

L1 Caches with ECC

Snoop Control Unit (SCU) and L2 Cache Direct Cache Transfers

Snoop Filtering

Private Peripherals

Accelerator Coherence

Error Correction

128-bit AMBA4 - Advanced Coherent Bus Interface

Figure 2 The ARM Cortex-A15 has four SMP cores with NEON floating point engines and a 128-bit AMBA bus. The AMBA bus can be used to tie multiple chips into larger SMP clusters.

bile, handheld business and embedded consumer devices that take the PC experience into smaller more dedicated devices such as netbooks, tablets, smart phones, digital signage as well as paying attention to the more traditional ideas about what embedded systems are. In addition to the higher end represented by Core 2010 and the Sandy Bridge effort, Intel rolled out its Atom 600 product line, which is aimed squarely at the embedded market and perhaps by inference as a growing challenge to ARM. Intel has not yet broken through the 1W power barrier that would make it a threat to ARM in areas like medical devices, but the intent and direction seem clear. On the other hand, ARM looks like it may be moving up the scale to get into those same applications where Intel currently dominates: gaming consoles, mobile computing, navigation, home entertainment and wireless infrastructure. The dual-core ARM 9 has been gaining some traction over the past couple of years, and now with the introduction of the quad-core ARM Cortex-A15 (Figure 2), the challenge, stated or implied, appears clear. The Cortex-A15 has four SMP cores in a single cluster with multiple SMP clusters possible via its 128-bit AMBA 4 bus. Each processor core has an FPU/NEON data engine to support signal processing, DSP processing and media acceleration within the general-purpose architecture.



The Cortex-A9 is a dual-core design using NEON and AMBA as well. It is interesting that Via Technologies, which is widely known in the U.S. for its low-power implementations of the x86 architecture, has now decided to add the ARM architecture—initially, the A9— to its embedded portfolio in the U.S. Via had licensed the ARM architecture some three years ago through its Wonder Media group in China and has been selling it into designs for a wide range of consumer products such as digital frames, printers, projectors and a low-cost tablet. In the case of Via, however, this may be a more synergistic approach than direct rivalry between the two architectures. They are bringing in ARM, and will be starting to offer an ARM 9 development board and supporting the Android operating system. However, this is in addition to their support of x86, not instead of it. For its part at the lower embedded end, Intel has announced the Atom E600 family, which was formerly code-named “Tunnel Creek.” The family consists of four members, each with a commercial and industrial temperature version. The core frequencies range from 0.6 GHz to 1.6 GHz and the thermal design power ranges from 2.7W to 3.9W. This still gives ARM an edge in the small, handheld, battery-powered device arena as far as power consumption is concerned.

With the E600 series, Intel has continued the integration of graphics processing and memory control on the single chip. The peripheral interfaces consist of four x1 PCI Express lanes that connect to an I/O hub (IOH), eliminating the North Bridge and other external chipsets. Intel is offering one IOH and it is possible to use ASICs, FPGAs or discrete peripheral interfaces—practically anything with a PCIe interface—to connect to the outside world. Already three third-party silicon vendors are beginning to make interconnect chips that can work with the Atom 600 series. Oki Semiconductor has announced the ML7213 and the ML7223(V) that integrate I/O such as USB, SATA, Video input, I2C and GPIO. The ML7223(V) also supports Gigabit Ethernet MAC and IPsec hardware accelerator and is also equipped with echo and noise cancellers. In addition, Realtek Semiconductor will be supplying a device for connected services gateways and medical devices. STMicroelectronics is planning to introduce its ConneXt IOH in Q1 of 2011 targeting in-vehicle entertainment systems. Figure 3 shows a preliminary block diagram of the ConneXt chip with the PCIe, video and other interfaces that have been chosen for this application area. A similar approach can be used to provide a different set of peripheral interfaces for other targeted application areas. It is to be expected that as the Atom 600 family becomes more widely used there will be more of these third-party IOH designs targeted at specific application areas. It is also a very natural step to pair an Atom 600 with an FPGA by means of a PCIe interface implemented on the programmable fabric. In fact, Intel has given a hint as to where it is taking this ability in announcing a partnership with FPGA maker Altera. Two other FPGA companies, Actel and Xilinx, have already announced devices based on pairing their programmable logic with an ARM processor. In the case of Actel, it was the SmartFusion with an ARM Cortex-M3 and with Xilinx, a dual Core ARM Cortex A-9. With multicore versions of the Atom also available and a simple PCIe link as opposed to the more complex AMBA bus, there seem to be many possible variations on this theme open to Intel. The example shown during a keynote was obviously a

editor’s report





10-100 MAC Ethernet AVB


The future of CompactPCI ® is serial...

Video-IN 656/dRGB

System Interconnect

PCIe Bridge

4 HS I2C

system DMA





6 Sample Rate Converters


Open LDi / dRGB




0 1 2 3 4 5



MEN Micro leads the way again:

Figure 3 The ConneXt IOH from STMicrosystems integrates peripheral interfaces targeted at automotive infotainment systems. This preliminary block diagram shows how a variety of interfaces can be linked to the PCIe lanes of the Atom 600 series embedded processors.

prototype—the code name is “Stellerator”— with two devices on a small circuit board. However, it is to be expected that when the idea becomes a product we will see the two devices on a single silicon die. This will also make possible custom peripherals as well as custom algorithms, such as DSP blocks that may be needed for some function, and will eliminate the need for a DSP coprocessor, its own software and interfaces with their latencies and attendant costs. The performance, I/O and peripheral requirements for deeply embedded designs have always been fragmented. Those for more consumer-oriented but nonetheless embedded devices have been less so as the need for performance has steadily increased. Silicon vendors have to track this ever expanding universe so it is not surprising that they will be bumping into each other and trying to carve out turf in creative ways. Actel Mountain View, CA. (650) 318-4200. []. Altera San Jose, CA. (408) 544-7000. [].

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Star architecture Full Ethernet mesh No bridges, no switches Support of 8 peripheral slots Fast 12 Gb/s connector Proposed CPCI-S.0 CompactPCI® Serial specification currently under development

Count on MEN Micro to get you to the future of harsh, mobile and mission-critical embedded technology first!

VIA Technologies Fremont, CA. (510) 683-3300. []. Xilinx San Jose, CA. (408) 559-7778. [].

June 3-4, 2010 Booth 700

MEN Micro, Inc. 24 North Main Street Ambler, PA 19002 Tel: 215.542.9575 E-mail:

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Technology in

context Solid State Storage

“SWaP” the HDD Form Factor SSDs in Embedded System Design The solid state storage solutions now available enable industrial and embedded system engineers to optimize the size, weight and power of their latest designs, breaking the mold of old rotating media form factors.

by Adrian R M Proctor, Viking Modular Solutions


n today’s platforms, embedded and industrial rugged system designers continue to search for better ways to deliver solutions with optimal SWaP (Size, Weight and Power) characteristics. These are critical for improving operational life, reliability, mobility and cost. The term “SWaP” was first coined by the military, who needed to create small, lightweight and rugged systems solunies providing solutions tions, yet a now new breed of embedded and ion into products, technologies and companies. Whether your goal is the latest industrial designs are now investing into research Figure 1 ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you the technologies required to minimize you require for whatever type of technology, Chip-sized, solderable solid state and productsthe you footprint are searchingof for.their equipment. Nearly drive. all of the components used in high-performance system design have been optimized in some way, i.e. smaller, faster or developments in processor and memory more dense, proving Moore’s Law. The technology at a healthy clip. There has been a notable exception to law, named for Intel co-founder Gordon this rule—the physical size and weight of E. Moore, posits that the number of tranthe storage component of system design. sistors that can be placed on an integrated circuit board doubles approximately For years the governing bodies that create every two years, and the theories behind industry standards for storage have been this idea have helped to push along the focused on supporting Hard Disk Drives (HDD) that meet the industry standard 3.5”, 2.5” or 1.8” form factors. What has Get Connected evolved is higher-performing, more robust with companies mentioned in this article. and higher-capacity storage, but no great

End of Article



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innovative leaps to deliver all of this in a reduced size. However, with the widespread adoption of Solid State Drives (SSDs) in a multitude of embedded and industrial applications, these SSDs have offered not only the “W” (Weight) and “P” (Power) benefits of SWaP over HDDs, but also significantly higher levels of Reliability, Availability and Service (RAS)—all highly desirable features for mission-critical commercial applications, especially those in rugged or mobile environments. But what about the “S” in SWaP, namely “Size”? There are a number of these BGA solderable “chip-sized” SSDs available in the market (Figure 1), but they will typically only deliver up to 4, 8 or 16 Gbyte of SATA/PATA storage at relatively low levels of performance (enough for OS/Boot or storing code). These single-chip SSDs do provide low density support for space constrained and rugged environments (Figure 2), yet they fall significantly short of the mark when requiring high performance (100 Mbyte/s+) or high capacity (100 Gbyte+) for the application.

technology in context

There is no physical reason why Solid State Drives (SSDs) should be inhibited by the HDD form factor constraints. Unlike traditional hard disks, SSDs do not rotate a platter or require mechanical housings, yet the additional weight of these metal housings are added to embedded rugged applications unnecessarily. Additionally, the infrastructure that has historically supported HDDs (rails, brackets, etc.) was designed to reduce vibration, something that an SSD will not require, yet the weight of all this metal remains in place purely because the standard 3.5”, 2.5” or 1.8” infrastructure demands it (Figure 3). While a standard 2.5” form factor SSD will deliver a far reduced weight and power solution when compared to an equivalent HDD, there is still significant room for improvement. The unnecessary metal used in standard SSD integration can easily be removed by using some of the newer and more innovative “NonHDD-like” SSD solutions available in the market today. These “SWaP optimized” SSDs can take the form of a DIMM, volumetrically efficient Cube design, reduced size, or simply a case-less standard form factor SSDs. System designers can free up their valuable board space with these “SWaPfriendly” SSD solutions while achieving the data reliability, rugged requirements, performance and capacity needs that the embedded, industrial, rugged and military markets demand. The current crop of AdvancedTCA, MicroTCA, cPCI, AMC and other embedded products are available as multicore, high-performance solutions that deliver the processing punch demanded by many of today’s embedded applications, yet the rugged storage component is typically located in other areas of the system or takes up a whole card (Figures 4 and 5). These small form factor processing cards will host the CPU and main memory (in some cases with multiple DRAM module sockets), yet rarely

Figure 2 Chip-sized solid state drive on single board computer.

Figure 3 A hard disk drive’s housing infrastructure is not needed for solid state drives.

have any more storage than that of a “chip-sized” device—until today. For example, an Advanced Mezzanine Card (AMC) will house a single 2.5” HDD or SSD for storage, yet by using a Slim SATA SSD (a form factor ratified by JEDEC as MO-297), the system designer can fit multiple SSDs on the AMC card enabling aggregated bandwidth / performance, RAID capabilities, increased redundancy or simply save space for other components or features on the card. Looking further at the space efficiency of some of these unique, volumetrically optimized SSD solutions, a SATA Cube (Figure 6) can provide the same storage capacity as a 2.5” SSD in 1/6th of the area, but perhaps more importantly; this

Figure 4 AMC card with 2.5-inch SSD/ HDD.

Figure 5 Storage-optimized ATCA blade.



technology in context

Figure 6 This SATA Cube offers six times more capacity or performance in the same space as a 2.5â&#x20AC;? SSD.

solution can deliver six times more capacity and performance in the same physical area. This means that the embedded system designer can deliver either highcapacity storage, high-performance storage or ultra-compact storage; something that will surely provide a high degree of value to the end user. This Cube SSD, like the â&#x20AC;&#x153;chip-sizedâ&#x20AC;? SSDs, has a solderable interconnect for increased levels of ruggedness; environments where this would be useful include vehicle-based systems or black box / event recorders.

There are of course many hundreds of applications that are severely size and weight limited, and the primary design considerations are typically those of SWaP. Even in the large mechanized world of rail transportation infrastructure companies today are rapidly adopting high-tech solutions to help them manage and maintain their transportation fleet. Embedded systems designers are able to deliver rugged, high-performance and high-capacity event data recording equipment that is able to record the data that is essential for operating and maintaining safe and efficient vehicles. These data recorders, often utilizing small form factor, rugged SSDs, provide vital and valuable information for accident investigations, train handling studies, fuel conservation, vehicle performance and preventative maintenance programs. There is considerable evidence that the continued investment in R&D has clearly allowed the embedded design world to focus on wide scale miniaturization and certain technologies that have been driving SWaP reduction. However, in the case

of the SSDs highlighted in this article, the industrial embedded system designer can breathe life into their new designs with the confidence that these solutions deliver a balance between SWaP and price. Moreover, they will deliver a higher degree of performance and capabilities, something that is sure to set them apart from their competition. The bottom line is that design engineers no longer have to be constrained by HDD storage standards. These engineers are now free to explore creative 3-D designs that have been limited by the old standards originally developed for rotating media. Additionally, these â&#x20AC;&#x153;SWaP-optimizedâ&#x20AC;? SSD storage solutions can give rise to new ways of managing challenges in the increasingly difficult areas of thermal efficiency, vibration, shock resistance and efficient use of space management. Viking Modular Solutions Foothill Ranch, CA. (949) 643-7255. [].

Low-Power, Multi-Core RISC SOM The CSB1725, based on the Marvell MV78200 Dual Sheeva Core SoC, is a highly integrated System On a Module (SOM). The CSB1725 provides an ultra small, powerful, flexible engine for low-power 10/100/1000 Ethernet based networking systems. The main features include: y y y y y y y y y y

1GHz Dual Superscalar ARMv5TE Cores w/512KB L2 Cache 512MByte 64-Bit Wide DDR2-667 Memory with 8-Bit ECC 64MByte NOR with Secure ID, and 512MByte SLC NAND Two PCIe x4 Port (or one x4 and four x1's) Two 10/100/1000 ports via 88E1121R RGMII to Copper PHY Two SATA Gen 2 (1.5Gbit or 3.0Gbit/sec) Channels Two 480Mbit USB 2.0 Host Ports <6W Typical, 10W Maximum, Both Cores Enabled 70mm x 75mm x 5.2mm (on 4.3mm Low Profile MXM Socket) Linux 2.6.x BSP

Coming soon: CSB1724 - 2Ghz 88F6282, Sub-3W, Dual GIGe, Dual PCIe x1, 256MB DDR2, 70mm x 50mm x 5.2mm The CSB1725 is manufactured in our in-house state of the art, lead-free surface mount manufacturing line. All products carry a 1-year warranty and are available in commercial and industrial temperature versions. Cogent also offers standard and custom carrier boards, plus royalty free licensing options for the CSB1725.



Untitled-9 1



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128 MB to 16 GB storage capacities Burst transfer speeds up to 16.6 MB/s Wide operating temperature range Sophisticated error checking and wear-leveling algorithms ensure high reliability Withstands 2000 G’s shock /16.3 G’s vibration Greater than 2-million program/erase cycles In-stock and long-term product availability Responsive and knowledgeable technical support

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connected Advances with PCI Express

All Aboard! The PCI Express â&#x20AC;&#x201C; Generation 3 The new Generation 3 specification for PCI Express is about to become final and manufacturers are ready to start rolling out silicon. With the new performance comes a number of design challenges and complexities that must be met to realize the promise of higher performance. by Akber Kazmi, PLX Technology


Loss (dB)

he PCI-SIG, an industry consortium 50cm Comm Channel Model that developed and enhanced PCI/ 4.0 5.0 6.0 7.0 0.05 0.1 0.5 1.0 2.0 3.0 0.000 PCI Express (PCIe) technology, is in the final stages of developing its third -5.000 generation of the PCIe specification, comX -10.000 monly referred to as Gen 3. The group has Gen 2 been both writing the specification and -15.000 X experimenting with the actual technology Gen 3 -20.000 since early 2008. With PCIe Gen 3-based systems al-25.000 nies providing solutions now ready in development and expected to be -30.000 ion into products, technologies and companies. your goal is to research the latest in production starting in Whether 2011, designers ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you could benefit from a more thorough underyou require for whatever type of technology, -35.000 of thefor. key aspects of the technoland productsstanding you are searching Frequency (Ghz) Loss ogy, the specificationâ&#x20AC;&#x2122;s projected industry Figure 1 adoption, and technical challenges related The increase in Gen 3 performance also comes with a significant loss of signal to the design and potential solutions to strength. overcome them.

PCIe Gen 3 Technology Overview

The goal of the PCI-SIG work group defining this next-generation interface was to create a standard that doubles the bandwidth offered by the current genera-

End of Article Get Connected

with companies mentioned in this article.


tion (Gen 2 at 5 GT/s) of PCIe interfaces. One option was to double the signaling rate to 10 GT/s or to reduce the encoding overhead from the current 20 percent and increase the signaling rate to a level where it offers double the effective bandwidth without doubling the signaling rate. After much debate and analysis, the PCI-SIG decided to go with 8 GT/s signaling rate


Get Connected with companies mentioned in this article.

and reduce the encoding overhead to offer twice the effective bandwidth of PCIe Gen 2. The signaling rate of 8 GT/s and encoding scheme of 128b/130b, complemented by scrambling, resulted in almost doubling the bandwidth without significant increase in complexity of the physical layer protocol. The signaling rate of 8 GT/s still poses

technology connected

challenges for board and chip designers as the clock duration is reduced from 200 ps to 125 ps, and jitter tolerance drops from 44 ps to 14 ps. Designers are working on complex Gen 3 schemes, such as decision feedback equalization to support high signal integrity for extended reach. These are needed in environments such as backplane designs or cabled implementations. The Gen 3 specification enhances signaling by adding transmitter precursor as well as post-cursor emphasis, receiver equalization, and optimization of Tx/Rx Phase Lock Loops and Clock Data Recovery. The specification also requires devices that support Gen 3 to dynamically negotiate up or down to/from Gen 1 and Gen 2 data rates, based on signal conditions.

Gen 3 Specification Progress

The original plan was to complete the standard by fourth quarter of 2009, which moved to mid-2010, but Murphy’s Law struck again as extensive experiments exposed some corner cases that had to be covered, pushing the specification’s release to the fourth quarter of 2010. Skeptics may still doubt it but this timeline looks achievable. The 0.9 revision has been released for sixty-day member review, which should be completed by mid-October. If all goes well in early silicon testing by PCIe vendors, Murphy’s Law won’t come into play and the changes will be limited to editorial modifications, enabling the group to release the 1.0 revision by end of 2010. It is important to note that the key developers of the PCIe Gen 3 components (CPUs, chipsets, switches, GPUs and I/O devices) will test their silicon based on the 0.7 release. They will provide test results and feedback for potential changes to the specification before 1.0 can be released in late 2010. Leading chip vendors, such as PLX Technology for PCIe switches, along with CPU and GPU providers, are developing early Gen 3 silicon in order to allow the specification to be fully validated before it is finalized.




Figure 2 One way of dealing with PCIe integrated on CPUs is to locate a PCIe switch adjacent to the processor thus maintaining signal strength while also possibly offering more lanes than provided by the CPU.

Similar to the adoption of PCIe Gen 2, gaming-system vendors are expected to adopt Gen 3 as soon as shippable silicon becomes available. Next, enterprise systems vendors will start supplying servers and storage products based on Gen 3. Communications and embedded systems vendors are designing with the PCIe Gen 2 now and are expected to move to Gen 3 after embedded CPU, ASIC and FPGA vendors deliver Gen 3 PCIe in their respective products. Designers considering development of their next-generation systems are being encouraged by suppliers to use PCIe Gen 3 instead of current Gen 2 technology to make their systems future-proof. Based on publicly available information, one can assume that I/O device, switch and CPU vendors are testing and validating early silicon and are in a position to quickly spin their respective products compliant with the 1.0 specification as soon as it becomes available. It is expected that silicon vendors will release a wide range of PCIe Gen 3 products in 2011, enabling early ramp-up of next-generation systems.

Design Challenges

Besides the protocol-level complexities of PCIe Gen 3, system designers will have to watch signal loss and jitter in their hardware designs. Figure 1 illustrates that loss in a communication-channel model. The channel loss almost doubles when fundamental frequency goes from PCIe

Gen 2 to Gen 3. Developers will have to design their hardware with extra care and in some cases will have to use re-timers in order to condition the signal to meet the trace-length needed for their designs. This challenge will be more prominent for server and storage motherboard designers as the x86 architecture is moving toward integrating PCIe on the CPUs as opposed to on the chipset or northbridge. Currently, some x86 CPU vendors are offering PCIe Gen 2 on the CPU sockets. If this trend continues, we will similarly see PCIe Gen 3 on future CPUs. Placing PCIe Gen 3 directly on the CPU poses an interesting challenge, as illustrated in Figures 2a through 2c. Figure 2c shows a traditional design with the CPU bus connecting to a northbridge, which then provides PCIe connectivity to the slots or endpoints. When the northbridge is removed (Figure 2b), the PCIe signals from the CPU will have to travel not only longer distances but also through congested areas on the board, thus making the signal weaker and susceptible to crosstalk from other traces on the board. This can be resolved through the use of PCIe switches by placing them where the northbridge used to be, as depicted in Figure 2c. The use of a PCIe switch may offer additional ports and lanes for fan-out implementations and enable designers to select a specific CPU for its processing power instead of its PCIe lanes and ports. The additional benefits of this approach RTC MAGAZINE OCTOBER 2010


technology connected

Root Complex


TxReq Response

PCIe Endpoint


Tx Response

PCIe Endpoint

Tx Preset1 Root Complex

Tx Response

Figure 3 A new protocol-aware re-timer will be required to calibrate the connections in PCIe Gen 3.

PCIe Endpoint

Root Complex

Root Complex

PCIe Endpoint


Root Complex


Root Complex



PCIe Endpoint


PCIe Endpoint



Figure 4 As PCIe proliferates, the need for the newer re-timers will become more prevalent in different design situations.

are to minimize cost, space and power on the motherboard, as PCIe switches are smaller, less expensive and consume less power than CPUs. Things get extremely complicated when a designer uses re-timers or repeaters to connect two PCIe Gen 3 devices. Traditional re-timers will not work in PCIe Gen 3 applications as the specification requires transmission of training sets and calibration of Tx_presets and decision feedback equalizer (DFE). For example,



Figure 3 shows a traditional re-timer (in yellow) that passes the request for calibration to the end device. However, response from the end device will not be seen by the requester, hence the re-timer Tx will remain unchanged. To solve this problem designers will need â&#x20AC;&#x153;protocol-awareâ&#x20AC;? retimers. A protocol-aware re-timer (shown in red) will not pass the calibration request to the endpoint; it will adjust its Tx facing the root complex as requested. The endpoint will communicate with the protocol-

aware re-timer for adjustment of its Rx/ Tx signals. Potential uses of re-timers are depicted in Figure 4. As PCIe Gen 3 gets deployed in server clusters, communication backplanes and embedded systems, the need for PCIe Gen 3 protocol aware retimers will become prevalent. Additionally, as more systems start using spread spectrum clocks (SSC) and subsystems with local reference-clocks, designers would have to figure out how to isolate these clock domains. PCIe switches and re-timers with built-in capability to isolate these clock domains would be required to make such subsystems run harmoniously. It is expected that the protocol-aware retimers with clock isolation capabilities will be needed for a system using cables and backplanes for connectivity. PCIe Gen 3 will provide the muchneeded performance boost in interconnect technology for next-generation systems, supporting the growing needs of bandwidth between CPUs, endpoints and subsystems. Completion of the 1.0 revision of the Gen 3 specification is imminent and vendors are ready to roll out their solutions in 2011. The higher speed of PCIe Gen 3 presents new challenges for hardware designers, but at the same time provides potential opportunities for silicon vendors to solve these problems and offer value to designers through innovative silicon solutions. PLX Technology Sunnyvale, CA. (408) 774-9060. [].




The right connection creates incredible power. Connectivity and control. Making your interface as reliable as the tidesâ&#x20AC;&#x201D;and just as strong. Sealevel creates hardware and software solutions for both digital and serial interface requirements. We Listen. Think. And Create. Experience exceptional computing at low power with the SBC-R9, an application-ready platform for your next product design. > > 864. 843. 4343

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connected Advances with PCI Express

System Area Network Speeds Data Transfer between Servers with PCI Express A new network switch technology is targeted to answer the phenomenal demands on intercommunication transfer speeds between servers, which are becoming all too evident in todayâ&#x20AC;&#x2122;s client-server architecture that is found in all data processing environments. by Joey Maitra, Magma


he proliferation of the raw processing power of computers has resulted in system architectures where processing tasks are distributed and assigned to various processing elements in the system in order to spread the load and derive better system throughput. The execution of these tasks is closely coordinated and then integrated by some central processing (CPU) entity to produce the desired output. The intent is to have the entire set of these elements share the processing load thereby contributing to boost the overall throughput of the system. Processing elements must then communicate with the central entity and/ or among themselves to synchronize the execution of their respective tasks. In most scenarios, there is also volatile and non-volatile storage elements dedicated to these distributed processing elements comprising the system. For instance in blade centers, blade servers have their own private storage facilities and also communicate with each other over high-speed connections on the mid-plane as well as to devices on a storage area network (SAN) through a switch module. This is typically



CPU PCI Express Endpoint PCI Express to PCI/PCI-X Bridge

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PCI Express

Root Complex


PCI Express


Transaction Data Link Physical

Swtich PCI Express Legacy Endpoint

PCI Express Legacy Endpoint Communication Controller Device

PCI Express Layers

PCI Express PCI Express Endpoint

PCI Express PCI Express Endpoint Communication Controller Card

Figure 1 A typical Root Complex Processor architecture prevalent in almost all current computer motherboards.

technology connected

Application Layer Server Motherboard Routing Information on Internet Routing Information on Internet

Application Layer Server Motherboard

TCP Layer IP Layer

IP Layer

Link Layer

Routing Information on Internet

Link Layer

PCI Express Datalink Layer

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Ethernet Driver Code Ethernet MAC Layer Ethernet Physical Layer

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Server 2

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PCI Express Physical Layer 10 Gigabit PCIe Ethernet CArd

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Routing Information on Internet

PCI Express Datalink Layer Ethernet Driver Code Ethernet MAC layer Ethernet Physical Layer

10 Gigabit Ethernet TCP/IP Packets embedded in Ethernet Frames

Figure 2 TCP/IP packet data flow from the Application layer of the sending server through the network to the Application layer of the destination server.

the case in mid- to high-end server environments. However, to extend this paradigm to an environment made up of servers physically located in separate enclosures would require a fast interconnect mechanism. In other words, these servers must communicate among themselves via some sort of a network. In such environments, there is also the need to access vast amounts of data via network attached storage (NAS) devices. This scenario is all too prevalent in datacenters and server farms to mention a few. Today, these access mechanisms are implemented via local area network (LAN) with technologies such as InfiniBand, 10 Gigabit Ethernet, Fibre Channel and the like. Another point to note, the phenomenal rate of deployment of the Internet has resulted in most LANs using TCP/IP in the upper layers of the communication

stack. IP packets from the TCP/IP layers are essentially encapsulated within the frames of the communication protocol used to form the LAN. The physical connections to the network fabric for servers and computers take place through either a network I/O controller card or a network controller device resident on the motherboards. These motherboards host a root complex processor as shown in Figure 1. A root complex denotes the root of an I/O hierarchy that connects the CPU/ memory subsystem to I/O devices. This hierarchy consists of a root complex (RC), multiple endpoints (I/O devices), a switch and a PCI Express to PCI/PCI-X bridge, all interconnected via PCI Express links. PCI Express is a point-to-point, low-overhead, low-latency communication link maximizing application payload bandwidth and link efficiency. Inherent in the

PCI Express technology is a very robust communication protocol with its own set of Transaction, Data Link and Physical Layers. The network I/O controllers implement some specific communication protocol and provide the interface to the physical media constituting the LAN. The controllers interface to a PCI Express endpoint of the root complex processor (RCP) of the server node participating in the network. Incidentally, this architecture is not restricted to servers since it is common in workstations, desktops and laptops. The vast majority of the industryâ&#x20AC;&#x2122;s prevalent communication protocols was invented before the advent of PCI Express technology. These protocols have their own set of almost identical infra-structure made up of Transaction, Data link and Physical layers. As depicted in Figure 2, data originating at the Application layer are transformed into TCP/IP packets and then embedded in PCI Express packets. These packets are then sent to the Ethernet controller that de-packetizes the TCP/ IP packet from the PCI Express packets and re-packetizes it to be sent in Ethernet frames over the 10Gigabit Ethernet physical media. The reverse process takes place at the destination server end. It is obvious from the discussion so far that there is an awful lot of protocol duplication. The cost of such duplication measured in terms of overall throughput of the network becomes more poignant when the nuances of the various communication protocols are considered as they relate to efficiency, i.e. data rate, maximum payload, packet header overhead, etc. It turns out that the duplication of the communication protocol, even though it may be executed in hardware, causes unnecessary software and hardware overhead burdens that seriously impact the overall throughput of the network infrastructure. Another important factor impacting the overall performance of a network is the bandwidth limitations of the physical media associated with the communication protocol used. This encompasses transfer rates, maximum distances supported and the connection topography to name a few. RTC MAGAZINE OCTOBER 2010


technology connected

Server 1

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TCP Layer

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IP Routing Application

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PCI Express Physical Layer 40/80 Gigabits/sec

40/80 Gigabits/sec 80/160 Gigabits/sec Full Duplex

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Virtual Internet

Figure 3 An alternate approach to sending TCP/IP packets via PCI Express links with the use of a PCI Express Switch. Network Switch

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Server x System Memory

Figure 4 The mechanism for the transfer of TCP/IP packets between server memories without any involvement on the part of the server processors.



For instance, with 10 Gbit/s Ethernet the restriction of the data transfer rate to10 Gbit/s is potentially a very serious limitation for many applications. Given this scenario, the ideal approach to boosting the overall performance of the network would be to use the PCI Express technology as the network fabric. Embedded in the PCI Express packet is the IP datagram with the destination IP address of the server node. PCI Express is a point-to-point communication protocol and consequently does not have a media access control (MAC) address. Therefore, the most natural and logical approach to routing data from one node in the network to another would be to have some entity route the data based on the destination IP address. Implementation of this type of routing methodology essentially makes that entity an IP router. This is where the PCI Express switch comes into play as shown in Figure 3. All of the downstream ports of the PCI Express switch connect to servers comprising the nodes of a system area network. Intelligence tied to the upstream port of the switch has already established the knowledge of the correlation between the downstream ports and the corresponding IP address of the server attached to it. Data flows from one server to another through the PCI Express switch. Consequently, it requires that the root complex processor (RCP) tied to the upstream port of the switch communicate with the RCP of the server. This poses the question of how best to communicate between two RCPs. Bus enumeration techniques in PCI Express architecture, which is the same as in PCI bus architecture, cannot allow one RCP to go through the discovery of devices on a bus that belongs to another RCP. However, there is a technique pioneered by PLX Corporation during the heyday of the PCI bus that addresses this issue and it is called Non Transparent Bridging (NTB). This method allows two RCPs to communicate through the use of base address registers (BARs). This interchange of information is applicable for memory, I/O and configuration spaces in the context of PCI Bus architecture and is applicable for both systems.

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This can only be supported if the underlying hardware of the PCI Express switch provides NTB functions on the respective downstream ports. The RCP of the IP router sets up the BAR registers on the individual PCI Express Switch ports attached to the respective servers and maps their system memories to respective windows in the logical address space of its own system memory. This then allows for the visibility of individual system memories of all respective servers in the network by one entity. This access mechanism is used to transfer data, in this case TCP/IP packets, between servers comprising the LAN. This method allows for the transfer of memory or I/O data between attached servers through the switch ports at the maximum data rate supported by the respective physical links. For example, with 8 lanes of PCI Express links using Gen 2 technology the data transfer rate is 40 Gbit/s and with 16 lanes it is 80 Gbit/s. PCI Express incorporates full duplex communication technology meaning transmit and receive can happen at the same time. This then makes the full duplex bandwidth for 8 lanes of Gen 2 to be 80 Gbit/s and for 16 lanes it is 160 Gbit/s. Gen 3 technology, which is currently being developed, will more than double these numbers.

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RAID Subsystem

Data Base Server

Mail Server

Fiber at 80 Gigabits/sec Fiber at 80 Gigabits/sec Internet

80 Gigabit/sec TCP/IP over PCI Express System Area Network Fiber at 80 Gigabits/sec

Optical Juke Box

Tape Library Fiber at 80 Gigabits/sec Fiber at 80 Gigabits/sec Fiber at 80 Gigabits/sec Application Server

Figure 5 Is an example of how servers with disparate functions participate seamlessly in a symmetrical TCP/IP based System Area Network.

Magmaâ&#x20AC;&#x2122;s patent pending technology, which covers all aspects of a network based on running TCP/IP protocol over PCI Express fabric inclusive of the IP Router, is

the basis of the network switch design. It relies on the pull-model for data transfer through the network switch. This allows for the processors on the sending servers


11/11/09 3:45:15 PM RTC MAGAZINE OCTOBER 2010

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to be totally free and oblivious of how IP data is transferred to the destination server. This significantly reduces the processor overhead on transferring data to and from the network. This is illustrated in Figure 4. With the PCI Express-based network switch technology, the maximum number of nodes that can be on one network is 256

because of the restrictions imposed by PCI configuration space that supports a maximum of 256 buses. This may be construed as a limitation, but it allows for a very symmetrical topography with one RCP, that of the network switch, servicing all of the nodes as devices underneath it. There is no additional RCP involved on expanding

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the number of nodes and, therefore, no additional memory resources are required. Consequently, adding nodes to the network simply implies daisy-chaining PCI Express switches resulting in significant cost per port decrease as the number of nodes in the network is increased. Moreover, as compared to 10Gigabit Ethernet and other legacy networks, adding nodes to the network switch is seamless because of the plug-n-play attributes of the PCI bus architecture. Since the servers have no direct visibility into a remote server’s memory, any data transfer operations necessarily require the root switch to be involved. For instance, when a source server needs to read/write data from/to a target server, the server notifies the root switch rather than attempting to communicate with the target server. It is the root switch that accesses the memory of the source as well as the target server. To further reduce data transfer latencies, the new switch technology uses DMA controllers built into the NTB ports of the PCI Express switch. This relieves the network switch processor from moving data between servers and allows for concurrent transfers between nodes in the network. This amounts to peer-to-peer transfers within the PCI Express switch array contributing to drastic reduction in data transfer latencies in the network. Based on the destination IP addresses of all of the individual packets in a particular server’s kernel space, the RCP on the network switch sets up the DMA descriptor file and then fires the DMA engine. PCI Express technology is fast becoming ubiquitous and the result has been that all server and workstation manufacturers now provide a certain number of PCI Express slots for I/O expansion. These form the PCI Express endpoints of the RCP on the host computer backplane. A host PCI Express card will take the PCI Express signals from the backplane and bring them out on fiber, or alternately on copper, to attach to the ports of the network switch. The number of PCI Express lanes operational between the server and the network switch will depend on the number

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of lanes supported by the server hardware. PCI Express allows for link negotiation whereby both ends of a PCI Express link negotiate to support the minimum number of lanes supported by either of the two connection points. Consequently, each port of the network switch will negotiate down to the number of lanes supported by the host connection to that individual port. These ports support Gen 2 PCI Express signaling standards and will negotiate down to Gen 1 signaling to support the corresponding connection to the server. This makes the network switch highly scalable. The network switch technology is based completely on standards with no aspects of the technology being proprietary. With the industryâ&#x20AC;&#x2122;s commitment to PCI Express technology, it provides a migration path to a newer generation of technology thus potentially extending its life cycle. This technology allows for the coexistence of legacy networks as it goes through its adoption cycle phase and, moreover, can serve as a fallback mechanism for mission-critical applications. This allows for a fail safe deployment. Another significant advantage is the cost per port as nodes get added to the network since there is only one root complex processor (RCP) on the network switch in this network topology. Figure 5 shows an example of how servers with disparate functions participate seamlessly in a symmetrical TCP/ IP-based system area network. This also shows how storage and processing servers coexist in one homogeneous network. This is facilitated by the increasingly popular implementation of iSCSI on communication with network attached storage devices. iSCSI is essentially the SCSI protocol embedded in TCP/IP packets. SCSI protocol is widely used in the industry to communicate with storage devices. Also, the connection to the Internet implies simply transferring all IP packets intact that are not destined for any server on the network via a wide area network (WAN) interface. The deployment of the network switch as shown in Figure 5 is representative of a topography that with different software modules can be used

for clustering, I/O virtualization and cloud computing applications. It is a highly flexible architecture. Magma San Diego, CA. (858) 530-2511. [].

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10/8/10 10:05:42 AM RTC MAGAZINE OCTOBER 2010

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System Monitoring and Management

Using Intelligent Mixed Signal FPGAs for Hardware Platform Management As systems become more complex, managing their internal functions becomes more demanding to maintain “five nines” or better reliability. Now devices that integrate processor, peripherals, FPGA and analog circuits can greatly ease the task of providing comprehensive system management. by Mark Overgaard, Pigeon Point Systems


ophisticated systems that are designed to be highly dependable usually include some sort of platform management function that monitors and manages the health of the hardware, including, for instance, its temperature and power consumption aspects. This management function may conform to a standardized or proprietary framework that enables coordinated management of a collection of boards or boxes; alternatively, it may be ad hoc—designed to meet the needs of a particular piece of hardware. This function, whether standardsbased or ad hoc, can be effectively implemented using an intelligent mixed-signal FPGA, which combines a microcontroller, an analog subsystem and a traditional field programmable gate array to provide a single device capable of addressing the needs of this application. One widely implemented hardware platform management framework is defined by the PICMG xTCA specifications. Recent articles in RTC magazine (including two in 2009) provide background on this framework. LAN-attached xTCA Management Controllers: How to Build and Use Them,





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Figure 1 Example mixed signal intelligent FPGA, SmartFusion, consists of three elements: the microcontroller subsystem (blue), programmable analog (yellow) and the FPGA fabric (red).

in the October issue, focuses on techniques and benefits for connecting xTCA controllers to an in-shelf LAN. Using I2C for “Behind-the-Scenes” Management, in the

June issue, covers some of the many ways in which the Inter-Integrated Circuit (I2C) bus can be used for auxiliary management functions. The scope of this article goes

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beyond xTCA to address other hardware platform management frameworks, as well as ad hoc approaches.

Examples of Hardware Platform Management Frameworks

Such a device is capable of being configured and programmed to support a number of example frameworks. As shown from left to right in Figure 2, these include: A. AdvancedTCA (ATCA) and AdvancedMC (AMC), which define a three-level hierarchy below the System Manager: 1) shelf (or chassis), 2) ATCA board or AMC carrier board and 3) AMC module. Each of these levels is managed by a controller type with specific responsibilities: Shelf Manager, IPM Controller (IPMC, with a Carrier IPMC variant handling subsidiary modules) and Module Management Controller (MMC), respectively. B. MicroTCA (µTCA) and AdvancedMC, also with a three-level hierarchy: 1) shelf, 2) µTCA carrier and 3) AMC


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As previewed above, this category of device augments a traditional FPGA with a microcontroller subsystem (MSS) that includes a central processing unit (CPU) and a suitable complement of peripherals. The MSS is complemented with an analog subsystem that supports multiple analog inputs, either generic or specialized, and provisions for configuring and orchestrating the collection of analog data. Platform management firmware runs on the CPU and uses peripherals either within the MSS or implemented in the FPGA fabric to implement digital management interfaces. The analog subsystem interfaces to the wide range of analog inputs and outputs that can be relevant to hardware platform management, such as voltage and current measurements for power rails, chassis, board and die temperatures, and the like. Figure 1 is a block diagram for an example intelligent mixed signal FPGA, Actel’s SmartFusion device. Consistent with the definition above, this device includes an FPGA fabric (red), plus a microcontroller subsystem based on an ARM Cortex-M3 processor (blue) and an analog subsystem (yellow).


System Manager


What Is an Intelligent Mixed Signal FPGA?





Figure 2 Example hardware platform management frameworks: A) ATCA/AMC, B) µTCA/AMC, C) VITA 46.11, D) DCMI.

Functional Area

Extent of Involvement for Each FPGA Subsystem µController

FPGA Fabric

Multiple I 2C Ports


Low Pin Count (LPC) Bus Support, with IPMI Registers and LPC Peripherals


Absorbing Auxiliary Logic from Managed Board



Power Rail Sequencing, Monitoring, Fault Detection and Recovery

Analog Sensor Monitoring, Threshold Assessment, Event Reporting


✔+ ✔+

TABLE 1 Example functional areas in a management controller and corresponding roles of intelligent mixed signal FPGA subsystems.

module, with corresponding controller types, including Carrier Manager and MicroTCA Carrier Management Controller (MCMC) for the middle level and the new Enhanced MMC (EMMC) in the bottom level, respectively. C. VITA 46.11, a two-level hierarchy that addresses VITA’s VPX and OpenVPX architectures: 1) chassis and 2) plug-in module, with corresponding Chassis Manager and IPMC controller types, respectively. The VITA 46.11 standard, now in development, aims to adapt and extend the ATCA management framework to fit

the needs of the VPX community. D. Data Center Manageability Interface (DCMI), which defines one level below the overall management software in which each server box or blade is represented directly by a Baseboard Management Controller (BMC). DCMI aims to provide a manageability interface optimized for large data centers (perhaps supporting Internet services with hundreds or thousands of servers). A given data center might have a single preferred set of overall management software but implement multiple server types from RTC MAGAZINE OCTOBER 2010


Tech In Systems

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Figure 3 Example of an intelligent mixed signalFPGA based control platform with the colored areas representing respectively processor (blue), FPGA (red) and analog (yellow). Two other subsections are also shownâ&#x20AC;&#x201D;additional I2C interfaces (1) and a LAN interface (5).

different vendors, all conforming to a unified framework based on DCMI. An intelligent mixed signal FPGA could play a primary or secondary role in each of the management controller blocks below the System Manager layer in these frameworks. In Figure 2, the three colors in each block represent the presence of the three elements presented in Figure 1: microcontroller subsystem, programmable analog and FPGA fabric. Furthermore, all the above frameworks are based on IPMI, the Intelligent Platform Management Interface, which provides a hardware independent architecture for doing platform management. IPMI is widely used in the PC and server space and has been adopted as a management foundation layer for open modular architectures such as xTCA and VPX. For the three multi-level frameworks (A, B and C on the left), Figure 2 shows a (typically optional) direct connection to an in-box Ethernet represented by the red line. Such a connection can enable LAN-level communication with connected controllers, facilitating such useful services as LANbased access to serial ports on managed boards, upgrades to the firmware and FPGA fabric, tracing of IPMB traffic, and so on.



Any of the frameworks in Figure 2 can be chosen by companies who are designing proprietary platforms that do not aim to comply with any standardized form factor, but who wish to leverage one of the standardized management architectures. Some such companies may choose to define and develop an entirely proprietary management architecture. The bottom line, however, is that the fundamental functions of hardware platform management tend to be similar across a wide range of implementations, whether multi-chassis or single box, standardized or proprietary, framework-based or ad hoc, IPMI-influenced or not. How do these functions map to the capabilities of an intelligent mixed signal FPGA, and which of them especially benefit from capabilities of such an FPGA?

Mapping Key Controller Functions to an Intelligent Mixed Signal FPGA

Traditionally, management controllers are based on microcontroller devices. A number of management controller functions can especially benefit from combining an analog subsystem and an FPGA fabric with the microcontroller core. One

key theme is that this model can allow integrating critical functionality of the managed board that would otherwise require separate devices, with corresponding reductions in bill of material costs and board footprint requirements. Management controllers often need multiple I2C ports, including for the in-thebox management buses such as the I2Cbased dual redundant Intelligent Platform Management Bus (IPMB) defined by xTCA. In addition to framework-defined uses, such ports can access onboard I2C peripherals like digital temperature sensors. For boards that can host managed mezzanine modules, like AdvancedMC carrier boards, implementing a distinct I2C bus for the local IPMB connection with each module site can yield performance and reliability benefits. An FPGA fabric in the management controller can be populated with additional I2C IP blocks as necessary to meet the needs in this area of a particular board. IPMI-based management controllers often need to communicate with one or more onboard main processors. A key IPMI-defined implementation for that communication is a register interface that is often implemented via a Low Pin Count (LPC) bus connection between the main processor and the management controller. In fact, management-focused microcontrollers often include a direct implementation of this IPMI register interface. With an FPGA fabric in the management controller, this function can be added via an IP block. Furthermore, various LPC peripherals such as serial ports can also be added in the FPGA fabric, absorbing functions that would otherwise require separate devices on the board. An FPGA in a management controller can also absorb arbitrary auxiliary logic on the board, possibly eliminating one or more Complex Programmable Logic Devices (CPLDs) or discrete logic. If any of this logic (say, power enables or other signals affecting the main part of the managed board) involves signals that need to be persistent across watchdog resets of the microcontroller, they can be implemented in the FPGA fabric and configured so that soft resets of the microcontroller subsystem do not affect them. xTCA management controllers are required to be protected by watchdogs, which typically do a soft reset

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of the controller when they expire. Another use for auxiliary logic could be the sequencing of onboard power rails. With an FPGA and an analog subsystem coupled to the FPGA, more sophisticated power rail management can be integrated into the management controller. For instance, the FPGA logic can connect with triggers from the analog subsystem that signal that a given power rail has reached its required voltage threshold during a power-up sequence or has fallen below its minimum level in a fault-detection scenario. These triggers can result in FPGAimplemented hardware responses or interrupts to request firmware involvement. Meanwhile, in addition to orchestrating onboard activities such as power rail sequencing, the management controller can provide visibility to upper layers of management for analog and digital sensors, such as temperatures, voltages and currents (including for monitored power rails), digital signals such as switch states and summary status signals like Power Good. Table 1 summarizes these key areas of functionality, highlighting the extent of

involvement in each of them for the microcontroller, analog and FPGA subsystems of an intelligent mixed signal FPGA.

Example Management Controller Based on Intelligent Mixed Signal FPGA

What would a specific management controller built to this model look like? Figure 3 shows a block diagram for an AdvancedTCA IPMC or Carrier IPMC reference design that is delivered in the corresponding Pigeon Point Board Management Reference (BMR) solution kits for xTCA. Figure 3 includes numbered examples of several of the key functional areas described in the last section, including: 1. This section provides for additional logic, including an I2C port, for each site on the board that can host an AdvancedMC module. 2. This set of GPIO interfaces is latched across Cortex-M3 watchdog resets, so that power rail enables and other key signals are not affected. 3. The analog section monitors a wide range of sensors, including voltage and current

for various power rails, plus temperature sensors. This subsystem in the SmartFusion device does all threshold checking itself; the Cortex-M3 only gets involved when a threshold has been crossed. 4. Here, a CoreLPC block in the FPGA fabric implements, via an LPC bus, the IPMI-defined register interface for communicating with the main processor (referenced as the payload, in this diagram). In addition, area 5 in Figure 3 shows a way to implement the LAN attachments captured in Figure 2: either the supplementary connections in the frameworks ATCA, ÂľTCA and VITA 46.11 frameworks or the primary connection in a DCMI framework. The SmartFusion-based reference design shown in Figure 3 is now being incorporated in the ATCA board designs of numerous leading ATCA, AMC and VPX board and module developers. Pigeon Point Systems Scotts Valley, CA (831) 438-1565. [].

Extreme Environment Barebones Â&#x2018;Â&#x2122;ÇŚÂ&#x201D;Â&#x2018;ƤÂ&#x17D;Â&#x2021; Â?Â&#x2013;Â&#x2021;Â&#x17D;ĚžÂ&#x2013;Â&#x2018;Â?ĚżÂ&#x2018;Â?Â&#x2013;Â&#x201D;Â&#x2018;Â&#x17D;Â&#x2018;Â&#x161; &Ä&#x201A;ŜůÄ&#x17E;Ć?Ć?Ç Ĺ?Ć&#x161;Ĺ&#x161;ͲϰϏΣʹϳϏΣĹ˝Ć&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x;ĹśĹ?Ć&#x161;Ä&#x17E;ĹľĆ&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x161;ĆľĆ&#x152;Ä&#x17E;Ć&#x152;Ä&#x201A;ĹśĹ?Ä&#x17E;Í&#x2DC; /ĹśÄ?Ć&#x152;Ä&#x17E;Ä&#x161;Ĺ?Ä?ĹŻÇ&#x2021;Ä?ŽžĆ&#x2030;Ä&#x201A;Ä?Ć&#x161;Ä&#x201A;ĹśÄ&#x161;ĨƾůůĨÄ&#x17E;Ä&#x201A;Ć&#x161;ĆľĆ&#x152;Ä&#x17E;Ä&#x161;Í&#x2013;ŜŽÄ?ŽžĆ&#x2030;Ć&#x152;ŽžĹ?Ć?Ä&#x17E;Ć?Í&#x2DC;

High-End IntelÂŽ Coreâ&#x201E;˘2 Duo with PCI Expansion &Ä&#x201A;ŜůÄ&#x17E;Ć?Ć?Ĺ˝Ć&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x;ŽŜÍ&#x2013;Ç Ĺ?Ć&#x161;Ĺ&#x161;Ć?Ć&#x161;Ä&#x201A;ĹśÄ&#x161;Ć?ͲϰϏΣʹϳϏΣĆ&#x161;Ä&#x17E;ĹľĆ&#x2030;Ä&#x17E;Ć&#x152;Ä&#x201A;Ć&#x161;ĆľĆ&#x152;Ä&#x17E;Ć&#x152;Ä&#x201A;ĹśĹ?Ä&#x17E;Í&#x2DC; tĹ?Ä&#x161;Ä&#x17E;Ć&#x152;Ä&#x201A;ĹśĹ?Ä&#x17E;ŽĨ/ÍŹKĹľÄ&#x201A;ĹŹÄ&#x17E;Ć?ĨŽĆ&#x152;Ä&#x201A;Ĺ&#x2021;Ä&#x17E;Ç&#x2020;Ĺ?Ä?ĹŻÄ&#x17E;Í&#x2022;Ć&#x152;ĆľĹ?Ĺ?Ä&#x17E;Ä&#x161;Ĺ?Ç&#x152;Ä&#x17E;Ä&#x161;Ć&#x2030;ĹŻÄ&#x201A;Ć&#x17E;Ĺ˝Ć&#x152;ĹľÍ&#x2DC;

Expertise only an Industry Leader can provide. ^Ä&#x17E;ĹŻÄ&#x17E;Ä?Ć&#x;ĹśĹ?Ä&#x201A;Ä?ŽžĆ&#x2030;ĹŻÄ&#x17E;Ć&#x161;Ä&#x17E;Í&#x2022;Ä&#x161;Ä&#x17E;Ä&#x161;Ĺ?Ä?Ä&#x201A;Ć&#x161;Ä&#x17E;Ä&#x161;Ć&#x2030;ĹŻÄ&#x201A;Ć&#x17E;Ĺ˝Ć&#x152;ĹľĨĆ&#x152;Žž>Ĺ˝Ĺ?Ĺ?Ä?^ĆľĆ&#x2030;Ć&#x2030;ĹŻÇ&#x2021;Ĺ?Ć?Ć?Ĺ?ĹľĆ&#x2030;ĹŻÄ&#x17E;Í&#x2014;WĆ&#x152;Ä&#x17E;ͲÄ?ŽŜĎĹ?ĆľĆ&#x152;Ä&#x17E;Ä&#x161; Ć?Ç&#x2021;Ć?Ć&#x161;Ä&#x17E;ĹľĆ?Ć&#x2030;Ä&#x17E;Ć&#x152;ĨÄ&#x17E;Ä?Ć&#x161;ĨŽĆ&#x152;Ä?Ĺ˝Ć&#x161;Ĺ&#x161;Ä?ĆľĆ?Ĺ?ĹśÄ&#x17E;Ć?Ć?Î&#x2DC;Ä&#x161;Ä&#x17E;Ć?ĹŹĆ&#x161;Ĺ˝Ć&#x2030;ĆľĆ?Ä&#x17E;Í&#x2022;tĹ?ĹśÄ&#x161;Ĺ˝Ç Ć?Î&#x2DC;>Ĺ?ŜƾÇ&#x2020;Ä&#x161;Ä&#x17E;Ç&#x20AC;Ä&#x17E;ĹŻĹ˝Ć&#x2030;ĹľÄ&#x17E;ĹśĆ&#x161;Ć?Ä&#x17E;Ć&#x152;Ç&#x20AC;Ĺ?Ä?Ä&#x17E;Ć?ĨŽĆ&#x152; Ĺ?Ć&#x152;Ä&#x17E;Ä&#x201A;Ć&#x161;Ä&#x17E;Ć&#x152;Ć?Ç&#x2021;Ć?Ć&#x161;Ä&#x17E;ĹľÄ?ĆľĆ?Ć&#x161;ŽžĹ?Ç&#x152;Ä&#x201A;Ć&#x;ŽŜÍ&#x2022;Ä&#x201A;ĹśÄ&#x161;Ä&#x201A;Ç Ä&#x17E;Ä&#x201A;ĹŻĆ&#x161;Ĺ&#x161;ŽĨŽŜůĹ?ĹśÄ&#x17E;Ć&#x152;Ä&#x17E;Ć?ŽƾĆ&#x152;Ä?Ä&#x17E;Ć?Ä&#x201A;ĹŻĹŻÇ Ĺ?Ć&#x161;Ĺ&#x161;Ĺ?ĹśÄ&#x201A;ĨÄ&#x17E;Ç Ä?ĹŻĹ?Ä?ĹŹĆ?Í&#x2DC;

Learn More > Š 2010 Logic Supply, Inc. All products and company names listed are trademarks or trade names of their respective companies.

Untitled-2 1


10/8/10 9:50:23 AM RTC MAGAZINE OCTOBER 2010

technology deployed Technologies for the Smart Grid

An Ounce of Prevention: Bringing Real-Time Monitoring to the Grid

Situational Awareness for the Next-Generation Grid

There is little ability to analyze events that threaten the performance or operation of the grid. Worse, without the support of increasingly rare human-expert operators, there is essentially no ability to detect, analyze and correct anomalies in real time. Systemic failures are a constant risk. “Synchrophasor” technology will improve this situation. Collecting phase angle measurements (phasors) from disparate locations at the same instant allows control centers to directly measure the state of the grid and take corrective action. If used in After years—perhaps decades—of falling behind the real time, it offers the possibility of proactively stopping failures by alerting the technology curve, the power industry now has an system operators where the grid is going opportunity to upgrade its infrastructure. Done correctly, it unstable, and either isolating or correcting the problem. will lead to a secure grid that utilizes existing infrastructure The North American SynchroPhasor to increase electricity transmission while reducing and Initiative (NASPI) seeks to provide the preventing blackouts. sensors, communication capabilities and control centers required to implement this by Supreet Oberoi, Real-Time Innovations key functionality. The network connecting phase sensors will be called NASPInet. NASPI’s vision is to implement a wide-area he electrical grid is in transition. Currently, grids are con- network capable of monitoring and controlling the entire grid. By trolled by aging SCADA systems with primitive or no com- collecting data in real time with minimal latency from multiple munications between generation stations. Despite the obvi- points on the grid, operators or automated programs can quickly ous fact that these systems are critical to the health and growth detect and respond to anomalies and threats. of the national infrastructure, today’s electrical grid is largely NASPInet is an effort to develop an industrial grade, secure, running “open loop,” with poor monitoring, poor metrics, and no standardized, data communications infrastructure for the electric real concept of distributed control. grid. In particular, NASPInet data bus aims to enable utilities to The Northeast blackout of 2003 occurred on August 14. Ten share their phasor information in real time. million people in Ontario and over 45 million people in eight states At the heart of the NASPInet architecture is a Phasor Meaof America were left without power. Many regions lost water supply. Sinusoidal Wafeform Phasor Representation Regional airports were closed and cellular and cable services were disrupted. In Ottawa and New York, people resorted to looting. While the investigations found many reasons for the black1 (Phase) out—from trees not being topped to computer bugs—one thing was clear. With a modern grid infrastructure, with utilities shar1 ing their information in real time in a more fault-tolerant manV1 V1 ner, this blackout could have been caught earlier. The investiga(Magnitude) tion revealed that during the precious minutes following the first outages in Ohio, when action might have been taken to prevent the blackout spreading, the local utility’s managers had to ask time=0 their operators by phone what was happening on their own wires. Meanwhile, the failures cascaded to neighboring regions. In other Figure 1 words, the grid operators were flying blind! This incident delivered a sense of urgency to modernize our A graphical representation of the data represented by the PMU device electric grid infrastructure.




Technology deployed

surement Unit (PMU). This simple device receives a GPS clock signal and voltages and currents from the electric power system. The measured values are then time-stamped and are called synchrophasors since they are time-synchronized phasor values. The word phasor indicates a measurement of both the signal magnitude and the angle (Figure 1). These PMU data create wide-area visibility across the power system in ways that let grid operators understand real-time conditions, see early evidence of emerging grid problems, and better diagnose, implement and evaluate remedial actions to protect system reliability. The PMU data does not provide new ways to remedy a fault in the grid, but provides high-fidelity information before the occurrence of the event for the operator to take corrective action (Figures 2 and 3). As shown in Figure 4, a Phasor Data Concentrator (PDC) correlates the phasor data from a number of PMUs and PDCs by time and feeds it as a single stream to other applications. PDCs allow us to capture wide-area disturbances, improve system security and coordinate substation visualization. The Phasor Gateway (PGW) in the NASPInet lexicon controls access to all signals from its substations. Think of it as a router that enables the NASPI network to access data from within the organization by verifying cyber security, access rights and data integrity, among other things.The Phasor Gateway is extremely critical because it also manages traffic format, timing compatibility, and setting traffic priority according to classes of data. NASPInet will enable the exchange of different classes of data with different priorities. For example, NASPInet will enable exchange of large-volume historical data with high reliability but without strict end-to-end latency needs. On the other hand, NASPInet can mandate strict latency needs on exchange of PMU data while allowing some samples to be lost. To do this, NASPI defines classes of data, which indicate the type of contract a publisher and a subscriber need to have when exchanging that class of data (Table 1).

Figure 2 Screenshot from a PMU monitoring application shows phase angle differences across WECC control areas. Deviations from zero result in colors according to the bar at the lower left. (

PMU data showed a much larger frequency swing associated with the event where frequency oscillations lasted several seconds.

Solving Complex Distributed System Challenges

As NASPInet evolves from a concept to a prototype to a production-ready deployment, it will face increasingly complex technical challenges that the networking layer will need to address. Scalability: The current number of deployed PMUs across North America is in the hundreds. However, as the needs and the means to provide situational awareness for the grid increases, not only will the number of deployed PMUs grow exponentially, but there will be other types of sensors providing valuable visibility into the state of the grid. What this means is that there could be tens of thousands on sensors, exchanging information in real time. The middleware, being the foundation for such a data grid, should be able to support such a scale. Low Latency: For the phasor data to be useful for aligning the grid, it should not only be accurate, but also be available within a strict time window. As mentioned, PMU data is time-aligned data; it does not make sense to receive the data after the time window has elapsed. Usually, the time window is in the tenths of a millisecond, with a trending toward even a finer resolution. In addition, this data needs to be delivered over vast geographical

Figure 3 PMU data for an event that occurred on February 7, 2010. The frequency excursions captured by the PMUs helped capture more accurate information about the event. (Courtesy

distances and this information is most useful when the electricity is delivered from one grid to another. The middleware should able to support real-time and low-latency transmission characteristics over a wide-area network. Fault Tolerance: The grid will support transmission of various categories of data. To support fault tolerance for data transmission, the grid cannot rely only on hardware redundancy or multiple pathsâ&#x20AC;&#x201D;either these options will be prohibitively inefficient or they will not be available. The middleware protocols should be able to support reliability without sacrificing the ability to multicast for scalability Quality of Service: Put simply, different categories of data may have different data transmission needs. Some classes of data, RTC MAGAZINE OCTOBER 2010


technology deployed



Kind of Data

A1: Closed Loop Cntl A2: Small Signal Stability Analysis


Low Latency Need

Predictable Latency (relative)

Availability (relative to latencies)

Data Quantity (per source)









Stream of Signal Updates


B: Feed-Fwd Control

B1: State Estimators

Stream of Signal Updates


C: Visual

Stream of Signal Updates





D: Hist

Bulk Transfer





E: Research

Bulk Transfer






Key: VH (Very High), H (High), M (Medium), L (Low), VL (Very Low)

NASPInet classes of data.

such as PMU readings, may be able to afford lost samples, but not high latency. The historical sensor data, requested after an “incident,” may not have low-latency transmission needs, but will require strict reliability. What this implies is that the network should be able to send different classes of data with different qualities of service (QoS). While a networking layer that sends all data with the strictest needs would suffice, it will be inefficient, preventing scalability and ensuring inefficient use of network resources. What is required is a middleware that can optimize the use of network resources depending upon the classes of data. Security: There are multiple reasons why the PMU data transmissions need to be confidential and tamper proof. Unauthorized access to PMU readings can expose utilities and transmission operators to legal liabilities, particularly in cases when the loads need to be dropped or worse, when there is a blackout. In addition, by tampering with the PMU readings, hackers could adversely affect the flow of power on our nation’s grid. The middleware should support protocols to protect data confidentiality and integrity, and support access control schemes that let only the authorized users have access to the data. Heterogeneity: The Power utilities will not develop the NASPInet from scratch. These utilities have significant investments in legacy networking protocols at the substation level, which cannot scale and perform to meet the NASPInet needs. What is required is a middleware protocol that can not only meet the needs of NASPInet, but also interoperate with legacy protocols, some dating back multiple decades.



Many Industries Have Solved Similar Problems

Fortunately, many other industries have been facing, and have solved, such network integration problems. High-performance middleware based on the “Data Distribution for RealTime Systems” (DDS) standard offers publish-subscribe peerto-peer networking with extremely configurable delivery parameters. These “quality of service” (QoS) parameters allow DDS to connect disparate systems with varying delivery needs into a single real-time networked system. DDS-compliant middleware is proven in hundreds of mission-critical applications. It is rated to the Department of Defense’s highest Technology Readiness Level (TRL) 9, indicating that it is field-proven in actual missioncritical applications. DDS is an adopted international standard. It is actively developed and maintained by the Object Management Group (OMG), the largest systems software standards body. First picked up by the Navy, it is now mandated by the U.S. military for high-performance networking. DDS adoption is also growing rapidly in many industries beyond military systems. The standard includes both API definitions (for source-code portability) and a wire specification that offers inter-vendor interoperation. Note that the wire specification is also an IEC standard, IEC 61148. DDS supports intelligent partitioning, dynamic deployment, “plug and play” discovery and configurable reliability. It scales well; it is proven in systems that require over 11 million publishsubscribe pairs. It also has initial success in the electrical industry. For instance, the Grand Coulee dam is retrofitting its control

Technology deployed

Utility A







Utility C PMU PMU



Utility B PMU




PGW Monitoring Center 1 Apps PGW Historian

Monitoring Center 2



Apps PGW




Figure 4

ing dark fiber in many transmission lines. DDS offers detailed QoS control of reliability, liveliness detection, redundancy and more. It implements reliable multicast for wide-area multi-point integration. DDS can also work over WAN networks and intelligently traverse firewalls. It integrates easily and securely with other protocols and standards, Web services, databases and enterprise architectures. Finally, DDS offers both standard APIs— for source portability between vendors—and an internationally accepted standard wire protocol for interoperability between implementations. Real-Time Innovations Sunnyvale, CA. (408) 990-7400. [].

Conceptual diagram on NASPInet elements.

system to offer N-way redundant “never stop” operation based on DDS middleware. The Army Corps of Engineers is in full test now, and plans to go live with this design in Q4 2010. Thus, DDS will be online in a significant power generation application soon. DDS provides a data-centric infrastructure that focuses on how data is moving and transforming in the system. It manages the flow of data, the data schema and all essential aspects of a distributed application. DDS can provide sub-millisecond deterministic delivery over dedicated transports such as the exist-

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Untitled-4 1


9/10/10 10:20:09 AM RTC MAGAZINE OCTOBER 2010

technology deployed Technologies for the Smart Grid

Smart Phones for the Smart(er) Grid

Smart Grid Device Ecosystem

As embedded designers and engineers, we know that to enable Smart Grid applications, an ecosystem of other embedded devices needs to exist. Fortunately, that backbone is starting to take shape with the Smart Energy profile defined by the ZigBee AlliThe build-out of the Smart Grid is involving a tremendous ance. This application profile sits on top of the ZigBee Network stack and provides the engineering effort to make it more efficient and more definition for the devices that are now startmanageable. But for the Smart Grid to achieve its true ing to be deployed such as meters, programmable communicating thermostats, smart appotential will require the participation of energy consumers pliances, in-home displays and other devices. on the other side of the meter. Technical tools are also Initially, these networks were designed to needed to help them fulfill their role. provide power companies with a magic â&#x20AC;&#x153;curtail your load now please, Mr. Consumerâ&#x20AC;? button to help drive down demand during by Eugene Fodor, Digi International peak loads, but this is clearly the beginning of a huge opportunity to allow consumers to take control of their energy usage. Until the existence of these devices, power usage was a passive activity since the obile applications on smart phones change the way we meter sat on the outside of residences and businesses, and energy interact with the world. We can find out what the local consumers only viewed their bill once a month. In-home displays traffic patterns look like before we walk out our front now increase energy awareness by informing customers of their doors, enabling us to calculate which roads to take to save time. power usage via a thermostat-like device on their wall. They allow us to shop smarter through camera bar code scanner applications that allow us to compare prices online, and will eventually even allow us to find items more quickly in the store Mobile Applications (e.g., your phone will tell you the dog food is on aisle two on the Mobile applications take it a step further by allowing conbottom shelf). Mobile devices put at our fingertips a host of em- sumers to access energy usage data on their phones from anybedded accessories that weâ&#x20AC;&#x2122;ve not had access to before in a sleek, where a cellular connection is available. This further empowers pocket-sized package: GPS, accelerometers, cameras, sensors, Utility lighting and Internet access. They combine these technologies Company allowing us to easily connect with coworkers, colleagues, friends, SE Certified family and even strangers with a similar background. Mobile In-Premise Display devices also change consumer behavior. We can sample music SE Certified before we buy it, shop online, arrange for goods to be shipped diThermostat rectly to our homes, buy and sell stock, check account balances, Smart Meter Network pay bills, watch our weight, and so on. Mobile applications influInternet/ ence and change the way we behave by increasing awareness. Frame Relay/ XBee SE SSl Wall Router Awareness is critical in tackling the energy problems that the Ethernet Smart Grid begins to address. The inherent intelligence we build into the energy backbone of the world needs to require change in human behavior if we want to make a significant impact and see real savings and curtailment of peak energy use. Fortunately, moConnectPort X2 Smart Energy bile applications are now being extended to influence how we use energy, and how we interact with the intelligent devices that we, ZigBee Smart Energy as engineers, design. They enable the consumer to monitor and Network control air conditioners, dish washers and other home devices SE Certified from their mobile phones. Beyond the consumer, mobile applicaSmart Meter Figure 1 tions for the Smart Grid allow a whole new class of applications for diagnosing and monitoring network health, and ultimately An end-to-end Smart Energy ecosystem using a mobile application to monitor and control HAN devices. easing the burden of connecting devices.




Technology deployed

Figure 2

Figure 3

The list of devices in a HAN as viewed through a mobile application.

User interfaces provide the ability to remotely control devices like thermostats.

the tech-savvy, Smart Grid user by allowing him or her to change their home energy usage on demand. Mobile devices cannot yet talk directly to low-power RF ZigBee devices. Even if they could, much of the business logic needs to sit on an IP network so that the user does not have to be in proximity of their home area network (HAN). Smart phones work through IP networks and require them to leverage the smart energy ecosystem. Mobile applications need to interface with large, scalable, secure, IP cloud-based services to support the business logic to drive behavior anywhere. It is also necessary to enable remote device control, and to provide back-end data management, analytics and warehousing. For example, cloud-based solutions exist that provide the basis for creating these mobile applications by connecting smart energy devices to cloud services and the end application. This provides not only for consumer-facing applications, but also for applications supporting network and device diagnostics and health. These installer-facing applications make it easier to bring devices on board existing networks.

Mobile Facing

So what does a typical mobile application that changes behavior look like? First of all, it must connect to the smart energy devices on the home area network as well as receive and send information from the utility such as pricing alerts, messages, curtailment events, confirmation noticeâ&#x20AC;&#x201D;think pay the bill! It must allow the user to affect his or her environment remotely, for example, change the set point on the thermostat or turn off the lights. It must empower the user to review historical data for both recent and long-term usage and to set goals while receiving positive and negative feedback. Additionally, it should be able to drive behavior through social networking to compete and share information Solutions exist that utilize these key components to help consumers drive behavior. For example, an application presents a dynamic view of the smart energy devices on a home network, and through the application and the smart energy ecosystem, each device can be told to â&#x20AC;&#x153;identifyâ&#x20AC;? itself. Usually, a device then RTC MAGAZINE OCTOBER 2010


technology deployed

Figure 4 An avatar helps drive consumer behavior by providing visual feedback (smiles or tears for goals met or unmet) to make energy saving actions more interesting/exciting.

responds by sending a visual or auditory queue to the user. The application extends the behavior required by the specification by empowering the user to remotely control the thermostats within an account. The user can create a monthly budget to track their current usage against each meter and sub-meter in their account and receive instantaneous demand readings to see where and when energy is being consumed. An energy saving avatar in the form of a piggy bank or fruit bearing tree could be used to represent how the user is tracking against his or her goal. Interfaces to social networking tools drive competition by encouraging users to compare their energy usage against their friends and homes with similar profiles. Applications exist that can aid in device installation for both non-technical and technical people. In smart energy, all devices are required to join a network with a unique installation code that ensures that the device is authorized to join the HAN. Typically, this code must be hand entered, and despite a CRC-16 check at the end to ensure correct entry, manually entering and supporting the entry of tens of millions of codes is an expensive endeavor.



Furthermore, RF networks are notoriously difficult to set up, particularly when some devices cannot be physically relocatedâ&#x20AC;&#x201D; washer/dryer hook-ups are located right next to the meter, and no one has aluminum siding, right? Installer/diagnostic applications exist that can reduce installation costs and make set up easy. This is accomplished through back-end key management and bar code scanning through a camera, and network discovery tools that securely connect to back-end systems. Installers are presented with tools to help them look at link quality indicators and RSSI values to ensure strong connectivity. This enables the installer to identify networks where range extenders need to be deployed decreasing the need for truck rolls.

Figs 7-8. Installer Application Examples

Mobile applications for the Smart Grid are just now being deployed, but are rapidly being developed. In the future, consumers will be able to compare their energy usage with similar homes by identifying comparable homes using cloud service data and mapping tools built into their mobile applications. Consum-

Technology deployed

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Figure 5 The ability to create reports on demand provides a realtime view into energy usage.

ers will control, monitor and even sell energy back to the power company during peak periods when the price of energy favors their pocketbooks. Installers will use GPS to identify which residence they are at and ensure that the right devices get installed in the right home. Mobile applications will diagnose connectivity issues on the fly ensuring cost-effective and reliable delivery of energy data and management. In short, mobile applications integrate the technologies that will drive positive change.

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technology deployed Technologies for the Smart Grid

Information, not Enforcement, is Key to Smart Grid Success To realize the full potential of the advent of the Smart Grid, data must be presented to the energy customer as well as to utilities, but in different form. Consumers have grown accustomed to fun and informative devices like the iPhone. This dry data about kWh and peak loads needs to be turned into usable and actionable information for the customer. by Jason Williamson, Altia, Inc.


or most consumers, energy has traditionally been a passive purchase. Energy usage has been tracked by the meter readers from the utility company. The typical electric bill arrives weeks after the energy was used, and the data provided is difficult for the customer to comprehend. In such a system, users are isolated from the cost, environmental impact and potential for system overloads. Thus, they cannot contribute to the solution to these tricky problems that plague electricity providers. Customers need a way to help them understand how much energy their appliances are consuming. While they are learning about their own energy consumption, they can develop an awareness of peak and off-peak times—and how their home energy usage burdens the grid. It is unrealistic to dump raw data out and expect consumers to devise a system for calculating this information. The logical solution is for their home appliances to track and report the relevant data. At the March 2010 launch of the Smart Grid Consumer Coalition, Katherine Hamilton, president of an advocacy group called GridWise Alliance, stated, “We don’t think the Smart Grid is smart until the consumer is actually involved.” She further commented that customers’ control of how they use energy will help them make changes to lower their consumption. The Demand Response and Smart Grid Coalition support this statement. “Demand response not only reduces demand on the grid during peak periods, but in almost all cases produces a ‘conservation effect’ that lowers overall energy consumption.” Their report continues to state that the “total energy reduction averages around 4%, but can range upward of 11%.”



As appliances become more computer controlled, that energy consumption data becomes more readily available. Most large appliances already have a board in place that monitors energy usage for performance and troubleshooting purposes. Providing a platform for consumers to access this data and use it to modify their own energy consumption behaviors is a logical evolution. It is just a question of where it makes the most sense to put that display and, more importantly, how these choices impact the presentation of that data on the Human Machine Interface (HMI).

Individual Displays, Individual Reporting

One solution is to include a separate display in each appliance. From a cost standpoint, this makes a lot of sense since the user does not have to invest all at once in an entire system. Instead, smart appliances can be added to a home one at a time as the need to replace existing appliances arises. Newer appliances are already being offered with high-end displays, so the hardware is already in place to display energy consumption data. Home appliance manufacturers need only expand their software engineering efforts to include the processing and display of power consumption data (Figure 1). This method is more expensive than its alternatives. Because each device has its own display, total engineering costs to develop the human machine interfaces (HMI) add up. For 60% or more of the home appliances that are out there, embedding displays is the likely direction because developers want to provide advanced features and enable control algorithms in an intuitive way. However, if you are interested in monitoring your total household energy usage, it is difficult to get the big picture from

Figure 1 There are several options available for monitoring home energy usage. A single display for each home appliance allows customers to become grid-wise—one appliance at a time.

Technology deployed

Figure 2

Figure 3

Another possible solution is a central appliance with an embedded display that will report energy consumption data for the household. This option offers home owners the opportunity to see “big picture” energy information for their home.

A stand-alone device that serves as the energy consumption portal in a household is another great option. Not only do customers gain the benefit of combined reporting of energy data from a single source, but the appliances maintained in the home can be less expensive models with traditional interfaces.

a bunch of little pictures. The energy consumption readout for each of your appliances would only tell you a part of the story. Consider the information that you would miss from devices that have no “picture” at all. Essential household devices like indoor and outdoor lights will never include a display, but that does not mean their energy consumption data is not important. To make informed, effective choices about when and where to spend power in your house, it is vital to examine energy consumption data across the entire network of household appliances.

Central Appliance Display, Combined Reporting

That idea of having a central overview suggests the value of a central appliance—a single, common appliance that is large enough to contain a significant-sized display so that total energy consumption data can be shown in a meaningful way. A refrigerator, for example, might fit the bill for that central appliance (Figure 2). The refrigerator is a necessary appliance for a typical household and it could easily house a screen large enough to fit the bill. The central device scenario allows all data to be combined into a single access-point. Engineers can focus their HMI development for presenting and controlling the data in one device. Consumers can see what is going on across their household and make decisions based on the entire system. This method would lower overall system cost. Yes, consumers will need to purchase the central appliance (which would probably cost more than its traditional replacement), but other appliances in the home—washers, dryers, ovens, HVAC units and the like—could be simpler, less expensive models. This does mean, however, that consumers who are ready to become “Smart Grid smart” cannot get the benefits of the system just by upgrading their washing machine when it breaks down. They would also need to purchase the new central appliance to start taking advantage of the energy reporting benefits that it offers. Additionally, all appliances must use the same inter-appliance communication mechanism or the complexity of the central unit is increased as it aggregates data using multiple protocols. So if all of

your appliances are not compatible, the need for potentially costly software patches or central appliance add-ons might be necessary to get your appliances to speak the same language. The risk here is small since appliance manufacturers have seen this difficulty coming and have put in a lot of thought to compatibility.

Stand-alone Display, Combined Reporting

What about obtaining energy consumption data from a stand-alone device? Each of your appliances has the ability to capture energy consumption data and all of the data is sent to an independent device (Figure 3). This method offers the benefit of combined access and reporting similar to the previous scenario. The stand-alone device could be something that hangs on the wall for easy access by the energy customer—or it could even be an existing personal electronic device, like a smart phone. While the smart phone option sounds enticing, it does not make the smartest access point for this type of information. The display would need to be designed around the limited real estate of a pocket-sized display. Limited space offers limited understanding. In order to communicate data in a way that offers intuitive, actionable data, sufficient space is needed for the display. A home computer would provide a better option for an access point. In that case, the area available on the computer screen offers a better option for clear communication and control of the overall system load. The stand-alone device method also allows for lower overall system cost. You need only the device or the energy reporting software for your existing personal electronic device. Your remaining home appliances could be less expensive models than their high-end counterparts.

The Smartest Solution

So what is the right solution? In the real world, houses are already full of appliances that are perfectly functional—but not Smart Grid capable. Motivated consumers will likely be able to purchase adapters that let these existing devices report to the RTC MAGAZINE OCTOBER 2010


technology deployed

Figure 4 Consumers get the best smart grid understanding when they combine smart appliances with a central reporting device. Users can see and adjust energy consumption data for each appliance—and understand how their household energy use burdens the grid.

Untitled-2 1

10/5/10 10:58:31 AM


Dual IF for PCI Express with 16-bit ADCs (200 MSPS)

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Two IF inputs (DC to 300 MHz) — adjustable sample rates Giant congurable FPGA (XC6VLX240T) 10 MHz timebase with timestamping capability Pairs with EDT’s x8 PCIe main board for high-speed DMA, plus additional FPGA resources and memory

Altia. Colorado Springs, CO. (719) 598-4299. [].


Untitled-1 1

larger system. This scenario requires a centralized or stand-alone device to aggregate and display data. However, many customers will not want to invest in updates to their aging appliances. They need to be able to gradually integrate Smart Grid ready appliances into their households without purchasing a stand-alone or specific centralized device. In the real world, consumers have divergent goals and we cannot force-fit a one-size-fits-all solution. The best approach is combining appliances with their own displays with a master appliance that presents data from all devices. This is the most adaptable and complete solution. Touch screens are rapidly permeating the home appliance industry. As break downs require users to replace old appliances, the newer models will most likely include some kind of embedded display. This is an opportunity for users to implement the system incrementally and become accustomed to the benefits of energy awareness. When the central appliance or stand-alone energy monitoring center is added, the overall system view is possible. This is where users really start to be able to contribute to a solution and avoid heavy handed regulation of energy consumption (Figure 4). One study showed that, just by making the energy usage information available to customers, 95% of users shifted their energy usage—with 83% checking more frequently during highdemand periods. 59% took action to use more energy-efficient appliances and 42% modified their use of existing appliances. These numbers are a compelling argument for Smart Grid technology and a ringing endorsement for smart appliances. Intelligent, intuitive interfaces are the key to informing and, thus, empowering home owners to reduce their burden on the grid. While they cannot completely eliminate their need to use energy to manage their households, with a logical means for monitoring energy consumption data, it is possible to turn present-day energy consumers into future energy conservationists.

OCTOBER 2010 RTC MAGAZINE 9/14/10 10:08:46 AM


X Marks the Spot. At Extreme Engineering Solutions, you’ll find products that are designed from the ground up to handle any environment. From boards to integrated systems, our embedded solutions are rugged and reliable–ensuring your application is a success, no matter how extreme the conditions. Embedded solutions that always hit the mark. That’s the Extreme way.

Extreme Engineering Solutions 608.833.1155

products &

TECHNOLOGY Modules Provide Two CAN Bus Isolated Interfaces

Two versions of a new CAN bus interface module interface network sensors and actuators to high-performance control systems. Introduced by Acromag, the IP560 is an Industry Pack ANSI/VITA-4 card that plugs into VME, CompactPCI and PCI bus mezzanine carrier cards or singleboard computers in embedded systems. The IOS-560 models are designed for use within Acromag’s I/O Server industrial PC, a small fanless box computer, which services mobile computing, machine control and test applications. Both CAN bus interface modules feature two channels with optional isolation. Each channel has an NXP SJA1000 CAN controller with a TJA1041 transceiver. Extended temperature models support -40˚ to 85°C operation. Single quantity pricing starts at $500. All models have two complete CAN bus interfaces, each using an NXP SJA1000 CAN controller with a high-speed TJA1041 transceiver. The advantage of this design is that it allows reporting of bus fault conditions directly from the transceivers. It also has the ability to transmit, receive and perform message filtering on extended and standard messages. The modules support CAN 2.0B protocol compatibility and ISO 11898 compliance for Part A (11-bit) and Part B extended (29-bit) arbitration IDs. PeliCAN mode extensions provide numerous communication capabilities. An isolation option eliminates ground loop potentials and protects equipment from electrical noise, surges and spikes. The 1000V isolation barrier safely separates channel-to-channel and channel-to-host. To simplify software development, Acromag offers several programmer support tools. A Windows development package provides API development software and Win32 DLL drivers, plus examples for C, Visual Basic, .Net and LabVIEW environments. The Linux software includes a library of I/O function routines to speed code development. IP modules are additionally supported by C libraries for VxWorks and QNX real-time operating systems. These packages include demonstration programs with C source code to test and exercise the I/O module operation. Acromag, Wixom, MI. (258) 624-1541. [].

3U VPX Air Baffle Board

A new VPX air blocker board in the 3U height is designed to fill in unused slots and redirect (or contain) airflow. VPX systems can require high levels of heat dissipation. The air baffle helps keep the air contained to aid cooling effectiveness and subsequently can reduce static pressure build-up in a system. Custom panel and handle options are available to ensure continuity of the systems’ appearance. Bustronic also offers VPX accessories such as load boards, extender boards, RTMs and SerDes test devices. Pricing for 3U VPX air baffle is under $150 depending on volume and type. The lead time is 2-3 weeks ARO. Elma Bustronic, Fremont, CA. (510) 656-3400. [].



Optical 4-Port Serial Mezzanine Board Supports Multiple I/O Protocols

Targeted for its direct-to-disk, longduration recording and playback systems, Conduant has introduced its StreamStor Optical High Speed Serial Mezzanine Board. It can be used with compatible StreamStor controllers to provide direct data input utilizing Serial Front Panel Data Port (sFPDP) and other protocols including bonded and multi-channel versions of SeriaLite II. When combined with the StreamStor Amazon Express controller, the interface can support recording and playback performance up to 800 megabytes per second for applications in defense, scientific research and commercial markets. The StreamStor Optical High Speed Serial Mezzanine Board supports independent multiport recording and playback for up to four data streams. Some protocols support the bonding of all 4 channels to aggregate the performance for a single channel at higher speed. The board demonstrates flexibility by supporting widely used cabling and data protocols to ensure maximum data transfer rates with minimum overhead. An on-board Altera field programmable gate array (FPGA) allows for configuring multiple input/output (IO) protocols and other parameters. The StreamStor Optical High Speed Serial Mezzanine Board can be ordered with support for data rates from 1.06 to 3.125 gigabytes per second and wavelengths of 850 nm or 1300 nm to support cable lengths up to 25 kilometers. The board uses standard LC optical connector style for easy connection to compatible data sources. Pricing starts at $3,500. Conduant, Longmont, CA. (303) 485-2721. [].


3U Power Supply with 60ms Hold-Up Capacitance

A new 3U PICMG 2.11 power supply solution takes in MIL-STD-704 28V-DC input voltage and provides up to 300W on 3.3V, 5V and 12V at 90% efficiency. The XPm2010 from Extreme Engineering Solutions is extremely versatile, operating over a wide input voltage range from 16V to 50V steady state while maintaining up to 300W isolated output power. It provides up to 25A on 3.3V, 22A on 5V and 8.3A on 12V in a compact 3U cPCI form factor. Integrated MIL-STD-461E EMI filtering is provided, and with an optional hold-up capacitor, the XPm2010 provides up to 60 ms of hold up time (at 120-W). With support for current sharing, two XPm2010s can be connected in parallel to provide increased power output. The XPm2010 redefines the rules on what can be done with a 3U power supply. Key features include a PICMG 2.11 standard 47 position connector pin-out, conduction cooling, and optional on-card hold-up capacitor for up to 60 ms of hold-up time and load sharing support with another XPm2010. The XPm2010 is already in use by both domestic and international military/avionics customers and is the standard power supply used in X-ES cPCI ATR systems. Pricing varies based on options selected and volume purchased, with list price starting at $2,995. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

COM Express Basic Form Factor Now with the New Type 6 Pin-Out

Coinciding with the launch of the COM Express 2.0 specification by PICMG, Kontron has introduced an additional version of the Computer-onModule ETXexpress-AI based on the new COM Express Type 6 pin-out definition. As compared to the Type 2 pin-out definition for COM Express Basic form factor modules, the new Type 6 pin-out offers configurable Digital Display Interfaces (DDI) SDVO, DisplayPort and HDMI/DVI along with 23 PCI Express Gen 2 lanes. This provides more native display options and higher serial bandwidth than previously possible. Most noteworthy is that the native support for all the new display interfaces simplifies carrier board designs, reducing time-to-market and total cost of ownership for graphics-intensive applications. The extensive PCI Express support underscores the trend of moving away from legacy parallel interfaces toward pure serial embedded system designs for higher bandwidth and reduced latency. This represents a smooth transition path for application designers looking to enhance their designs with next-generation technology such as faster drives and peripherals. The performance of the Kontron Computer-on-Module ETXexpress-AI is scalable using four Intel Core i7 and Core i5 processors. All versions support up to 2 x 4 Gbyte Dual Channel DDR3 ECC SODIMM memory modules and offer a comprehensive set of interfaces via the COM Express Type 6 connector: 1x PCI Express Gen 2 Graphics (PEG) also configurable as 2 x PCIe x8, 7x PCI Express x1, 4x Serial ATA, 8x USB 2.0, Gigabit Ethernet and Intel High Definition Audio. All graphic interfaces of the new COM Express module can also be used in parallel. In addition to dual-channel LVDS and VGA, developers can draw from the Kontron ETXexpress-AI Type 6 exported interfaces DisplayPort, HDMI and SDVO. The integrated Intel Active Management Technology Intel AMT 6.0 offers extensive remote management capabilities including out-of-band management. An 8V – 18V wide range power adapter for simplified power supply rounds out the feature set. Operating systems supported include Windows 7, Windows XP, Windows Embedded Standard 7 and 2009, Linux (such as Red Hat Enterprise, SuSE, Red Flag, Wind River Linux) and VxWorks. Kontron, Poway, CA. (888) 294-4558. [].

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6U FPGA-based VMEbus SBC Boasts Triple Get Connected with technology and Redundancy companies providing solutions now

A 6U FPGA-based, Get Connected is a new resource for further exploration triple-redundant 64-bit into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly VMEbus SBC emwith an Application Engineer, or jump to a company's technical page, the ploys a lockgoal of Get Connected is to put you in touch with the right resource. step architecWhichever level of service you require for whatever type of technology, ture keeping Get Connected will help you connect with the companies and products software deyou are searching for. velopment at a minimum. With this redundant lock-step system that increases system reliability, the SEU-resistant A602 from Men Micro runs the same set of operations in parallel to ensure that the programming only views the hardware components Get once,Connected making the new withboard technology and companies prov suitable for mission-critical applications including those in Get Connected is a new resource for further exploration into pro the avionics and railway markets. according to DO-254, the datasheet Developed from a company, speak directly with an Application Engine single-slot COTS-based A602 reliability andWhichever economical in touchoffers with the right resource. level impleof service you requir mentation with high reliability up to Design Assurance Level (DAL) and produc Get Connected will help you connect with the companies A (catastrophic) in avionics and up to Safety Integrity Level (SIL) 4 in trains, the most stringent level in each class. To ensure high safety standards, the 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of the FPGA are triple-redundant. Critical functions, like voters implemented as IP cores in the FPGA, monitor at least two of the three redundant components to provide the same result to guarantee system reliability. In the event one of the three redundant components fails, the system remains completely operational providing the required availability for highly critical systems. Standard I/O contained in the FPGA is accessible via the rear. This includes a sextuple UART, an I²C bus and an RS-232 interface that can also be led to the front. The A602 also provides two PMC slots, Get and be used with all standard one accessed viaConnected the front or with rearcompanies I/O that can products in thisfor section. PMC modules andfeatured the other an AFDX PMC connection via rear I/O. Operating temperature is -40° to +50°C with qualified components. Pricing is $12,994. MEN Micro, Ambler, PA. (215) 542-9575. [].


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6 Channel Resolver Interface Daughter Card Adds I/O Channels

A daughter card for the Anything I/O series of FPGA based-interface cards from Mesa Electronics is a 6 channel resolver interface with 6 additional +-10V analog outputs. The 7I49 is intended for applications that read stand alone resolvers, as the 7I49 generates the resolver reference excitation. The 7I49 can be used with 1:1 and 1:2 transformation ratio resolvers. The 7I49 has approximately 14 bits of resolution and 12 bits of absolute accuracy. The 7I49 FPGA interface module allows velocity and absolute position readout by the host. Data is presented to the host in simple parallel register form. The 7I49 has selectable excitation frequencies from 2.5 KHz up to 10 KHz. Host position register is updated at 256 times the excitation frequency to reduce aliasing when host sampling is not synchronous with the excitation frequency. Velocity resolution is approximately 1 RPM. The 7I49 uses an oversampling A-D followed by a tracking filter. Filter coefficients may be changed to trade off noise versus acceleration tracking ability. All resolver and analog I/O is via 3.5 mm pluggable screw terminal blocks. The 7I49 requires a single 5V power supply. Price of the 7I49 is $123 in quantity 100. Mesa Electronics, Richmond, CA. (510) 223-9272. [].

Core 2 Duo Embedded Computer Now with QNX Support

Triadem Solutions, the official QNX Distributor & Reseller in Switzerland, has developed a Board-Support-Package for the PIP20 platform boards from MPL that are integrated in its PIP20 and PIP22 embedded box computers. Therefore, with immediate effect, a board-support-package for QNX 6.4.1 & 6.5.0 is available. QNX Photon provides a graphical user interface. The QNX BSP further supports the following on board interfaces: Ethernet, USB, Serial ports, PS/2 ports, as well as IDE and SATA ports for mass storage modules or drives. A complete computer without any additional wiring is implemented on a 270 x 160 mm board. The processor and the SDRAM chips are soldered directly on board, which leads to an increased system security. Thanks to the energy efficient design and the low power consumption (typ. 28W), no active cooling is required to operate the computer. The passive cooling concept of the PIP solution, allows the board to be operated under full load from -40° up to +75°C. The unit is well suited for extreme conditions (cold, heat, vibration, shock, low maintenance ) and still can be operated like a normal PC with standard software, and now also with the RealTime OS QNX. The PIP Family is extremely flexible. There are several housings (IP51 & IP67) in different colors available. The solution is expandable through its internal expansion buses (PC/104-Plus, PMC, PCI, PCI-Express Minicard), allowing the ability to add any required additional functionality, even for single quantities. Any power supply with an output voltage between 8 - 28 VDC (optional up to 48 VDC) can be used.. MPL, Dättwil Switzerland. ++41 56 483 34 34. [].



Qseven Module Uses Atom Z510/ Z530 and Supports up to 4 PCIe x1 Lanes

Built with Intel’s Atom Z510 (1.1 GHz) or Z530 (1.6 GHz) processor and Intel System Controller Hub (SCH) US15W, a new Qseven module supports onboard 1Gbyte or 2Gbyte DDR2 SDRAM, onboard NAND Flash (4Gbyte with optional upgrade to 8Gbyte). In additioen, the PQ7-M104G from American Portwell offers two SATA and three PCI-E x1 lanes (with an option of four) from its Qseven Golden Finger and dual independent displays via LVDS and SVDO. A Mini-ITX carrier board (PQ7-C200) and 3.5˝ carrier board (PQ7-C100) are available as a developer kit. With its low power consumption—under 10W (+5V)— the PQ7-M104G can be in a fanless configuration and battery-operated. Portwell’s PQ7-M104G provides reduced time-to-market and true expansion capability and flexibility. It can help development time and costs during initial phase of development, achieve a faster time-to-market, a simplified future upgrade path, scalability and an increased application lifecycle. In addition, Portwell also can provide services to customers on the carrier board design and development, review schematics and BIOS customization. American Portwell Technology, Fremont, CA. (510) 403-3399. [].


COM Solution Uses Latest Atom Embedded Processor Family

A new COM Express board is based on the new Intel Atom E6xxx Series processors, formerly code named Tunnel Creek. The E6xx series is the first Intel Atom processor-based system-on-a-chip (SoC) for embedded applications. The highly integrated SoC uses PCI Express (PCIe) as the chipset interface, which means the processor can pair up with any PCIe-compliant device such as a proprietary ASIC, FPGA or application-specific I/O hubs. A combination of this SoC with the Intel Platform Controller Hub EG20T is called the Queensbay platform by Intel. Built in the small COM Express Compact form factor of 95 x 95 mm, the Toucan-TC embedded PC module from Lippert Embedded Computers takes advantage of the Queensbay platform and features the Intel Atom E6xx in versions ranging from 0.6 GHz to 1.6 GHz and up to 2 Gbyte of soldered DDR2 memory. The Toucan-TC also offers both SDVO and LVDS graphics interfaces, 3 SATA ports, one PATA port and five PCIe x1 ports. Additional interfaces include seven USB 2.0 ports including a client port, a Gigabit Ethernet port with PHY, a Micro-SD Card Slot, a CAN bus and four UART ports on mechanically lockable option connectors. In addition to the COM Express features, the Toucan-TC offers a Fail-Safe BIOS function, an optional solid-state drive (up to 32 Gbyte), a uSD card slot and comprehensive condition monitoring. The Fail-Safe BIOS functionality allows secure remote BIOS flash upgrade, while the Condition Monitoring (LEMT), available on all new products from LiPPERT, provides numerous additional software functions. LEMT comes with a programming interface in source code. As a special feature of the Toucan-TC, the user can determine in real time the current consumption and thus the power requirements for different operating states of the CPU. The Toucan-TC is also optionally available in the extended temperature range of -40°C to 85°C. Cooling is supported with a suitable heat spreader. All memory is soldered to the board, in order to achieve high levels of shock and vibration resistance. LiPPERT Embedded Computers, Mannheim, Germany. +49 621 4 32 14-0. [].

Two Servers in One for an Improved Technology ROI

A new high-performance server delivers the benefits of two servers in a single 1U (1.75” height) rack space. The SR-1600 from Stealth Computer is designed to address demanding highperformance computer workloads for applications that require significant processing power and system performance. Designed with a total of four Intel Xeon 5500/5600 processors (two per node), the SR-1600 is capable of handling high intensity computing needs for today’s most demanding applications. The system employs fully scalable DDR3 ECC memory with options up to 288Gbyte (144Gbyte per node). The cable-free, modular system design allows for complete component swap out in mere minutes eliminating the time and financial costs of extended downtime. The SR-1600 supports four front accessible hot-swappable 2.5” hard drives (two per node) with up to 2Tbytes’s of storage space for archived data. For applications that require extra system performance, solid state drive (SSD) options are available. The Stealth rack server is powered with an energy-efficient 1100 watt (80 plus) power supply that can be removed and replaced in seconds. Systems are compatible with Microsoft Server 2008/2003, Red Hat, VMware and can be custom configured to meet the needs of the end user. The Stealth model SR-1600 rack’s targeted deployment includes applications that require maximum computer density for manufacturing, financial services, scientific/engineering, aerospace, and energy, to name a few. Stealth Computer, Woodbridge, Ontario, 905-264-9000. [].



Edge-Lit Light Guides Provide Backlighting for Touch Display Graphics

Ultra-thin light guides from Global Lighting Technologies (GLT) utilize the company’s LED-based edge-lighting technology to provide a solution for backlighting touch-enabled display graphics in a wide variety of applications. GLT’s light guides provide bright, uniform light exactly where needed for directional symbols, on/off buttons, company logos, rotary switches, sliders and whatever other graphic icons need to be illuminated, from large to small. The LEDs are strategically spaced along the edge of the light guide, providing the most efficient LED-based backlighting technology available and offering numerous benefits such as better control of color and uniformity, lower part count (fewer LEDs required), reduced power consumption, and the thinnest possible backlight panel. The ultra-thin profile of the light guides is suitable for graphic interfaces employing capacitive or field effect touch technology. Placed between the PC board / circuit sensor and the graphic overlay, their extreme thinness makes it easy for the signal to go from the graphic overlay through the backlight and to the sensor. The user can touch right through them with no loss of sensitivity. They can eliminate the need to use individual LEDs for each icon, button or symbol as well as multiple LEDs for larger areas such as company logos. Now, in many cases, larger graphics and multiple smaller icons can be vividly illuminated with a one or two LEDs positioned along the edge of a light guide. Global Lighting Technologies, Brecksville, OH. (440) 922-4584. [].


Single Board Computer Targets Very Low Power Consumption Applications

A rugged 3U CompactPCI single board computer is based on Intel’s latest Atom E6XX processor (codenamed ‘Tunnel Creek’), which integrates both 3D graphics and memory controller. The ACR301 from GE Intelligent Platforms responds to the growing requirement for embedded computing solutions that consume minimal power and dissipate minimal heat. It delivers optimum performance/ watt, and can operate in harsh environments such as those found in military/aerospace applications and growing numbers of industrial applications. Not only does the ACR301 offer exceptional performance/watt characteristics (sub-10 watts), it also offers outstanding flexibility. It is offered with four alternative versions of the Intel Atom processor (0.6 GHz, 1.0 GHz, 1.3 GHz, 1.6 GHz) and in five ruggedization levels. Flexibility is further enhanced by the provision of a mezzanine (PMC) site that enables it to be precisely configured for specific application profiles. Comprehensive input/output and communications capabilities—including two Gigabit Ethernet interfaces, two USB 2.0 ports, two full duplex asynchronous serial ports, two Gen 2 SATA ports, keyboard/mouse and DVI video— are provided. The ACR301 also features support for CAN-bus, the communications standard designed specifically to facilitate the exchange of electronic information within a vehicle. 1 Gbyte of DDR2 SDRAM is soldered to the board for optimum reliability. The ACR301 represents a technology insertion opportunity for existing users of GE’s CR4 and CR5 single board computers, and benefits from the extensive range of long-term support programs available from GE Intelligent Platforms. Supported operating systems include VxWorks, Linux and Windows. Deployed test software (BIT and BCS) is also provided. GE Fanuc Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [].

EBX SBC Features Intel Core 2 Duo Processor

An ultra-fast single board computer (SBC) on an industry standard EBX form factor is designed around an Intel Core2 Duo P8400 processor. The Mamba from VersaLogic performs at 2.26 GHz with mid-range power consumption of only 18.5 watts (typical). Mamba is a suitable solution for OEM developers working on high-speed data or graphics-intensive applications in medical, defense, robotics, and security systems With an industry standard EBX footprint of 5.75 x 8 inches, Mamba is designed for applications that require high-performance CPU and video processing. Enhanced Intel SpeedStep technology allows users to finetune the balance between power dissipation and performance. It allows adapting to performance needs while minimizing power draw and heat Get Connected with technology and dissipation. Intel’s GM45 + ICH9M chipsetproviding offers graphics companies solutionscore nowspeeds up to 533 MHz for high-end graphics, advanced 3D rendering, high-defGet Connected is a new resource for further exploration inition video playback, and media acceleration for video CODECs.Whether Ana- your goal into products, technologies and companies. log VGA and LVDS flat panel video the interfaces supportfrom flexible display is to research latest datasheet a company, speak directly configurations. with an Application Engineer, or jump to a company's technical page, the of Get Connected is togigabit put you in touch withtwo the right Basic on boardgoal features include dual Ethernet, SO-resource. Whichever level of service you require for whatever type of technology, DIMM sockets for up to 8 Gbyte DDR3 RAM (4 Gbyte per socket), six Get Connected will help you connect with the companies and products USB ports, four serial ports, two SATA ports, HD audio, eUSB interyou are searching for. face for removable flash storage and three general purpose timers. The on board PCI Express Mini Card socket supports plug-in Wi-Fi modems, GPS receivers, flash data storage, and other cards for added flexibility. On board data acquisition features include up to sixteen analog inputs, up to eight analog outputs and thirty-two digital I/O lines. The Mamba is available in both commercial (0º to +60ºC) and full industrial (-40º to +85ºC) temperature versions and meets MIL-STD-202G specifications Get Connected with technology and companies prov for mechanical shock and vibration for use in harsh environments. OEM Get Connected is a new resource for further exploration into pro pricing is around $1,430.

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datasheet from a company, speak directly with an Application Engine

VersaLogic, Eugene, OR. (541) 485-8575. []. in touch with the right resource. Whichever level of service you requir

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Embedded Development Kit for Wind River Software and Intel Core i7

A new Embedded Development Kit enables design engineers to quickly begin developing their application. Part of the Wind River On-Board Program, the Embedded Development Kit from Emerson Network Power includes an Emerson MicroATX motherboard based on the Intel Core i7 processor with optimized trial versions of Wind River’s operating systems, development tools, embedded hypervisor and graphics software to help equipment manufacturers save time and money on application integration for a faster, more efficient time-to-market. By putting cutting-edge development tools in a single box for evaluation, Emerson Network Power aims to accelerate and simplify design engineers’ startup process. The LiveUSB format enables designers to boot directly from the included USB flash drive to evaluate a fully operational development environment, eliminating the installation process. Get Connected with companies and Design engineers will quickly be able to evaluate and develop using Wind River Linux products featured in this section. 3.0 and/or Wind River VxWorks 6.8 running on Wind River Hypervisor 1.1. The 30-day trial software from Wind River is optimized for developing, running, debugging and prototyping embedded software directly onto the Emerson Network Power MATXM-CORE-411-B motherboard using Wind River Workbench 3.2. Each kit also includes all required cables, a comprehensive startup guide, sample projects and tutorial videos to ensure that customers new to Wind River products will be able to start development right away.


Emerson Network Power, Carlsbad, CA. (760) 930-4600. [].

Get Connected with companies and products featured in this section.



Accelerating Your Success.

Three Times the Power People. Products. Services. The powerful combination of Avnet and Bell Microproducts provides the expertise you need to accelerate your success. Our combined team gives you access to world-class resources. Bringing industry leading line cards together, we now deliver the most extensive inventory of brand name systems, embedded hardware, displays, storage and software. And, with our enhanced services you have access to Avnet’s leading ISO integration centers, financial solutions and supply chain strategies.

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multiple guests sharing single core LYNX OS-SE

Phoenix Internationalâ&#x20AC;&#x2122;s VC1-250-SSD Conduction Cooled Serial ATA (SATA) based Solid State Disk VME blade delivers high capacity, high performance data storage for military, and y, aerospace p industrial applications requiring rugged, extreme emee envi eenvironmental i ron ronmen me tal and secure mass data storage.

guest with processor affinity




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The Intel Core i7 family has been widely used in the desktop and laptop market, and now the quad-core versions of the processor are available for embedded designs. Now LynxSecure 4.0 from LynuxWorks provides a flexible virtualization solution for use in embedded systems. The availability of LynxSecure on the latest quad core processors from Intel allows large GUI-based OSs such as Windows or Linux to securely co-reside with more traditional embedded real-time OS solutions such as the LynxOS family of RTOSs from LynuxWorks. The advanced software virtualization in LynxSecure is integrated with the hardware virtualization technologies, such as vt-x and vt-d, on the Intel processors to give native performance and functionality of all the OSs that are running as â&#x20AC;&#x153;guests.â&#x20AC;? Another key feature that LynxSecure offers is the ability to runUntitled-6 guest OSs that have Symmetric Multi processing (SMP) capabilities. The new quad-core devices from Intel make this feature a reality by allowing one of the guest OSs to run across multiple cores, offering performance never seen before in a virtualized embedded system. For embedded systems that require a sophisticated user interface coupled with networked connectivity, and also hard real-time data response, the combination of LynxSecure with the quad-core Intel core-i7 processor allows all of this functionality to be easily developed, or migrated from existing systems, giving an unprecedented development window for the next generation of complex embedded systems. Taking advantage of the hardware virtualization capabilities of the Intel Core i7, LynxSecure offers the ability to run guest OSes at near-native performance. It enables an unmodified OS such as Windows to run at much higher performance than other solutions that rely on the traditional emulation layer approach. LynxSecure also offers built-in virtual networking, allowing Windows applications to seamlessly communicate via TCP/IP with other virtualized OSs, such as Linux, running in a separate partition. This rapid and secure inter-partition communication is handled entirely by LynxSecure without modifying the applications or the virtualized OS.

High Operational Hi Temperature +85° C

Operational Altitude to 80,000 feet

'PSPVSFOUJSFMJOFPGTUPSBHFQSPEVDUTXXXQIFOYJOUDPNt 714ď&#x161;ş283ď&#x161;ş4800 An ISO 9001: 2000 CertiďŹ ed Service Disabled Veteran Owned Small Business


LynuxWorkrs, San Jose, CA. (408) 979-3900. [].

10/16/09 11:43:57 AM

;HYNL[LKMVY! â&#x20AC;˘ Embedded â&#x20AC;˘ Communication â&#x20AC;˘ Enterprise

++9,**:THSS-VYT-HJ[VYZ â&#x20AC;˘ 244-pin MiniDIMM & VLP MniDIMM â&#x20AC;˘ 204-pin SODIMM â&#x20AC;˘ All ECC Registered or Unbuffered â&#x20AC;˘ JEDEC Compliant â&#x20AC;˘ Commercial & Industrial Temperature ZZZYLNLQJPRGXODUFRP_VDOHV#YLNLQJPRGXODUFRP RTC MAGAZINE OCTOBER 2010

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3/15/10 11:18:23 AM

with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

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MicroTCA or Linux and Java products ........ 41.................................................................

Apacer....................................................... National Instruments................................... 9............................................... End of Article Products Arbor Solutions........................................... Get Connected with companies and products featured in this section. Avnet Embedded........................................

One Stop Systems......................................

CM Computer.............................................

Phoenix International.................................. 53.................................... Get Connected with companies mentioned in this article.

Get Connected with companies and products featured in this section.

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with companies mentioned in this article. Pentek, Inc.................................................

Cogent....................................................... 18...................................

Red Rapids, Inc.......................................... 27...........................................

EDT........................................................... 44............................................

Sealevel Systems.......................................

ELMA Electronic Inc...................................

The Math Works, Inc................................... 2.................................

Extreme Engineering Solutions, Inc............. 45......................................

Themis Computer.......................................

IEI Technology............................................ 13.........................................

VersaLogic Corporation..............................

Innovative Integration.................................. 55...........................

Viking Modular Solutions Sanmina-SCI

Logic Supply, Inc........................................ 33................................


MEN Micro, Inc.......................................... 15..................................

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.



We are conscious that not all military ŝŶƚĞŐƌĂƚŽƌƐǁŝůůƌĞƋƵŝƌĞĂƚŽƉĐůĂƐƐdZ ĐŚĂƐƐŝƐ ůŝŬĞ ŽƵƌ ŶĞǁ ^ŝdž,Ğdž ƐĞƌŝĞƐ͕ ďƵƚ ǁĞ ĐĂŶ ĞŶƐƵƌĞ ƚŚĂƚ ŽƵƌ ĨŽƌƚƵŶĂƚĞ ĐƵƐƚŽŵĞƌƐ ǁŝůů ĞŶũŽLJ ƚŚĞ ĞdžƉĞƌŝĞŶĐĞ͘ /ƚ ŚĂƐ ďĞĞŶ ĚĞŵŽŶƐƚƌĂƚĞĚ ŝŶ ƚŚĞ ĮĞůĚ that ATR enclosures are crucial to your end system reliability and performance. dŚĞƌĞĨŽƌĞǁĞŚĂǀĞĚĞǀĞůŽƉĞĚĂƐƵƉĞƌŝŽƌ ƉƌŽĚƵĐƚ ƚŽ ŐƵĂƌĂŶƚĞĞ ƚŚĂƚ LJŽƵƌ ƉĂLJůŽĂĚ ĞůĞĐƚƌŽŶŝĐƐĂƌĞŵĂƚĐŚĞĚǁŝƚŚĞdžĐĞůůĞŶĐĞ͘


¾ ATR, 7 Slot, 800W PSU


All our chassis products are delivered Tested and Certified by independent authorized Labs per MIL-STD461E & MIL-STD-810F for immediate deployment in US Navy & US Air Force military Fighters and Helicopters.

- Contaminant-free enclosure - Available in ½, ¾ & 1 ATR size - VPX, VME & cPCI ready ͲĐĐĞƉƚƐŽŶĚƵĐƟŽŶ& Air-cooled 6Us Ͳ&ůĞdžŝďůĞƚŽƉΘďŽƩŽŵ/ͬKǁŝƌŝŶŐ Ͳ/ŶƚĞŐƌĂƚĞĚdĞŵƉĞƌĂƚƵƌĞŽŶƚƌŽůhŶŝƚ Ͳ^ŝdžŝŶƚĞƌŶĂů,ĞĂƚdžĐŚĂŶŐĞƌƐ ͲhƉƚŽϭ͘ϴ<tƚŽƚĂůWŽǁĞƌŝƐƐŝƉĂƟŽŶ - Up to 150 W per slot ͲƌĂŵĂƟĐĂůůLJŝŶĐƌĞĂƐĞƐƉĂLJůŽĂĚDd& ͲϮhƐĞƌĚĞĮŶĞĚW^hŽƵƚƉƵƚƐ ͲϮϬΣůĞƐƐƚŚĂŶŚĞĂƚĞdžĐŚĂŶŐĞƌdZƐ ͲϰϱΣůĞƐƐƚŚĂŶĐŽŶǀĞŶƟŽŶĂůdZƐ Ͳ^ƚĂŶĚĂůŽŶĞůŽǁǁĞŝŐŚƚƐŽůƵƟŽŶ ͲƵƐƚŽŵŝnjĂďůĞƚŽƐƉĞĐŝĮĐƌĞƋƵŝƌĞŵĞŶƚƐ ͲDŽƵŶƟŶŐdƌĂLJǁŝƚŚƋƵŝĐŬƌĞůĞĂƐĞƐLJƐƚĞŵ

RTC magazine  

October 2010

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