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The magazine of record for the embedded computing industry

May 2010

www.rtcmagazine.com

Embedded Moves to the Heart of

GREEN ENGINEERING

Ethernet Moves to 40 Gbit, Takes Aim at 100 Gbit Bring out the Promise of Multicore Touch Screen Input Battles the Noise An RTC Group Publication


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Embedded Moves to the Heart of

GREEN ENGINEERING 51 OpenVPX Rugged SBC Features GPGPU Technology Taking CUDA beyond Graphics

52 PICMG 1.3 2U Butterfly Backplane for PCI Express Gen 2 System Designs

TABLEOF CONTENTS

54 MMC Management Solution Using ACTEL SmartFusion

MAY 2010

Departments

Technology in Context Making the Most of Multicore

TECHNOLOGY IN SYSTEMS Touch Screen Input Technology

Software: To Gain Speed, the Challenges of Touch Eliminate Resource Contention 6Editorial 14 Multicore Power, Processing and Communication Screen Design 34Facing Insider Multicore Software for 8Industry Latest Developments in the Embedded TECHNOLOGY DEPLOYED Embedded Processors 22 Optimizing Marketplace Green Engineering Small Form Factor Forum 10LAN’s End Is Just the Tip of the Iceberg TECHNOLOGY CONNECTED Fiber Optics Is the Path to Reliability in Wind Turbine 40 Products & Technology Generators and Wind Farms Ethernet Hits 40 Gbit, Aims at 100 Gbit Embedded Technology Used 50Newest Levels of Interface by Industry Leaders 28 High Integration to Enable 10, 40 Energy Harvesting and Power and 100 Gbit/s Ethernet Balance in Wireless Sensor 44 over Optical Nets Networks Steve Graves, McObject

Arild Rødland, Atmel

Stephen Blair-Chappell and Max Domeika, Intel

Mickaël Marie, Avago Technologies

EDITOR’S REPORT

New Developments from the Field

David Yeh, AppliedMicro

Analysis Debug, Java and 12Power Specs

Martin R. Johnson, Illumra Eugene You, EnOcean

Tom Williams

Digital Subscriptions Avaliable at http://rtcmagazine.com/home/subscribe.php RTC MAGAZINE MAY 2010

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MAY 2010 Publisher PRESIDENT John Reardon, johnr@rtcgroup.com

Editorial EDITOR-IN-CHIEF Tom Williams, tomw@rtcgroup.com CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, marinat@rtcgroup.com COPY EDITOR Rochelle Cohn

Art/Production CREATIVE DIRECTOR Jason Van Dorn, jasonv@rtcgroup.com ART DIRECTOR Kirsten Wyatt, kirstenw@rtcgroup.com GRAPHIC DESIGNER Christopher Saucier, chriss@rtcgroup.com GRAPHIC DESIGNER Maream Milik, mareamm@rtcgroup.com DIRECTOR OF WEB DEVELOPMENT Marke Hallowell, markeh@rtcgroup.com WEB DEVELOPER Hari Nayar, harin@rtcgroup.com

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To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com Editorial Office Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214

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MAY 2010 RTC MAGAZINE 1/12/10 9:59:27 AM

Published by The RTC Group Copyright 2010, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


336 Volts of Green Engineering MEASURE IT – FIX IT

Developing a commercially viable fuel cell vehicle has been a significant challenge because of the considerable expense of designing and testing each new concept. With NI LabVIEW graphical programming and NI CompactRIO hardware, Ford quickly prototyped fuel cell control unit iterations, resulting in the world’s first fuel cell plug-in hybrid.

MEASURE IT Acquire

Acquire and measure data from any sensor or signal

Analyze

Analyze and extract information with signal processing

FIX IT Present

Present data with HMIs, Web interfaces, and reports

Design

Design optimized control algorithms and systems

Prototype

Prototype designs on ready-to-run hardware

Deploy

Deploy to the hardware platform you choose

Ford is just one of many customers using the NI graphical system design platform to improve the world around them. Engineers and scientists in virtually every industry are creating new ways to measure and fix industrial machines and processes so they can do their jobs better and more efficiently. And, along the way, they are creating innovative solutions to address some of today’s most pressing environmental issues. >>

Download the Ford technical case study at ni.com/336

©2009 National Instruments. All rights reserved. CompactRIO, LabVIEW, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies. 1123

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EDITORIAL MAY 2010

Power, Processing and Communication

W

hen we talk about embedded systems, the word “power” is commonly associated with two other words: heat and processing. Sometimes it is easy to confuse them, but both are central to the optimization of performance. That can be thought of as maximizing computation while minimizing electricity consumption and hence the generation of heat. Applying such (idealized) computational power to the solution of real-world applications is greatly multiplied by connectivity. These three elements are increasingly becoming the common denominators in the development of embedded systems. Years ago someone advised me, “If you’re going to start developing an application, give it more functionality than your present hardware system can bear. That way, by the time you’ve got it developed there will be hardware resources available that will make it a winner.” Now in those days, everybody just wanted raw computational power and there was not much regard to the amount of juice it was slurping up because we were talking about workstations. Things are very, very different in the embedded space. The “will to power” is insatiable in the computational sense, but as applications gain ever more functionality and target devices get ever smaller and more mobile, the more critical becomes the source of electrical power to drive the compute power. This has obviously led to advances in process technology that draw dramatically less power, and in on-chip power management. Such approaches have their limits. Especially if one wants to maintain a certain clock speed, there is a definite bill to be paid in terms of power drawn. You can’t put a processor to sleep forever; it needs to … well, process. This conflict between electrical and computational power is leading us onto the path of parallelism—or should that be “paths?” And parallelism is appearing at a number of levels. The one that we are all familiar with is the emergence over the past few years of multicore processors. But there are other manifestations of parallelism that are resulting in very powerful applications and relatively low electrical consumption. With multicore processors, of course, you can spread operating systems, applications or threads within applications and theoretically achieve higher performance without flogging the clock speed to infinity. There’s just one little detail—parallelism requires communication. Chip vendors have made great strides in equipping their multicore devices with shared caches and on-chip data paths to allow

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MAY 2010 RTC MAGAZINE

Tom Williams Editor-in-Chief

different threads to exchange data. But the real secrets lie in the software, and so we have also seen the rise of various multicore tuned items such as hypervisors that facilitate the efficient use of multiple cores by different operating systems, or the spread of multithreaded applications across a number of cores, all in a quest to exploit the underlying hardware parallelism to boost performance at a given level of power consumption. Other aspects of software design needed to bring out the potential of multicore CPUs include the ability to identify and avoid potential contention for resources outside the CPU such as data memory or peripherals. There is a need to analyze code for those sections that can benefit from parallelism and to make them run effectively on multiple cores. All this will incur a certain amount of overhead to coordinate and synchronize parallel operation, but it should result in significant net performance gains. Parallelism in the pursuit of computational power, however, goes well beyond processor architectures and the software that supports them. A vast web of embedded devices and systems is now able to communicate via a wide variety of interconnect and networking technologies, all of which are eventually able to find their way to communication via the Internet if their designers so desire. Distributed applications at this level often appear as machine-to-machine systems where sophisticated embedded devices communicate autonomously and frequently over distances in the service of a quite large application such as a transportation system. In the future we can also expect that connected mobile and nonmobile medical devices will cooperate in communicating in ways that will give medical professionals access to real-time networked data, which will also eventually feed into computerized medical records systems. One thing that also grows out of the ever expanding web of data generated and consumed by embedded systems is . . . synergy. By that I mean the phenomenon that data available from systems that were designed and networked for an intended purpose suggests new applications that may not have been thought of at the time. Creative developers can see data from even disparate systems and applications and think of new ways to combine and correlate it and then feed it back to selected devices to do new things on existing hardware and software. Thus does the power-stingy multicore, interconnected world of embedded systems become ever more useful and, well . . . powerful.


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INDUSTRY

INSIDER MAY 2010 Personal Computer Pioneer Ed Roberts Dies Ed Roberts, who produced what may have been the first personal computer, the MITS Altair 8800, has passed away. The Altair 8800 was sold as a kit starting in 1975 and turned into a $13 million business. It was based on an Intel 8-bit 8080 microprocessor running at 2 MHz and had a maximum memory of 64 Kb. It was also based on a bus architecture called the S-100 bus. The Altair 8800 was introduced in an edition of Popular Electronics and soon became a darling of hobbyists. Perhaps the most significant aspect of the Altair 8800 was the fact that it needed a programming language that hobbyists could use. That prompted two MIT students, Bill Gates and Steve Ballmer, to develop an 8080 version of BASIC by simulating an 8080 on a DEC computer at MIT and copying it on a paper tape of the type that could be read by a teletype machine. Gates took his tape of BASIC to MITS and it ran on the Altair. It was later also made available on a cassette tape that could be loaded into memory on the Altair. One did that by first setting switches on the front panel that constituted the instructions for a boot loader and loading them byte by byte into the machine’s memory. Then BASIC could be loaded. Later, 8-inch floppy disk drives became available and a primitive “Star Trek” game became wildly popular. The Altair soon motivated emulators to produce competitive machines and the personal computer phenomenon had begun. Not long after, a couple of students named Steve Jobs and Steve Wozniak introduced their first Apple computer to the Homebrew Computer Club in California, and publications were launched such as Byte and Dr. Dobb’s Journal. The world has not been the same since.

VITA Members Form FMC Marketing Alliance

VITA, the trade association dedicated to fostering American National Standards Institute (ANSI) accredited, open system architectures in critical embedded system applications, today announced the formation of the FMC Marketing Alliance. The purpose of the FMC (FPGA Mezzanine Card) Marketing Alliance is to establish an ecosystem of interested parties that promotes and grows adoption of the FMC specifications and technology. The Alliance is responsible for promoting the capabilities of the FMC specification and educating, training,

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MAY 2010 RTC MAGAZINE

informing and promoting FMC use to the press and the broader electronics community. FMC, as defined in VITA 57, provides a specification describing an I/O mezzanine module with connection to an FPGA or other device with reconfigurable I/O capability. The low-profile design allows use on popular industry standard slot card, blade and motherboard form factors, including VME, VPX, CompactPCI, AdvancedTCA, MicroTCA, PCI, PXI, and many other low-profile motherboards. The compact size is highly adaptable to many configuration needs and complements existing common lowprofile mezzanine technology such as PMC, XMC and AMC.

Companies that develop FMC products are encouraged to contact VITA to join the FMC Marketing Alliance. VITA announced the ratification of the FPGA Mezzanine Card standard under ANSI/VITA 57.1 on April 13.

ZigBee Smart Energy 2.0 Technical Requirements Available for Public Comment

The ZigBee Alliance has announced that the ZigBee Smart Energy version 2.0 Technical Requirements Document (TRD) is available for public comment by the Smart Grid community at large, opening it beyond those who have been active in its creation. The Alliance makes this unprecedented move for an organization engaged in standards development because it recognizes the important role ZigBee Smart Energy plays in the Smart Grid and the need to expedite the broadest consensus possible on its capabilities. The Alliance has entered into numerous liaison relationships with key stakeholder groups to engage directly in the collaborative development process for the HAN and the Smart Grid. The TRD represents input from a broad set of players into the development of the IPbased version of ZigBee Smart Energy. The TRD is driven by the Market Requirements Document that was made publicly available in June 2009.  ZigBee Smart Energy version 1.0, currently in wide deployment, was made publicly available in May 2008.

LDRA and Netrino Partner on Static Analysis Tool to Enforce Embedded C Coding Standard

LDRA and Netrino are partnering to implement the Embedded C Coding Standard. Support for the Embedded C Coding Standard complements the LDRA tool suite’s support for C language programming standards such as MISRAC:1998 and MISRA-C:2004, CERT C, SEC C and GJB (Chinese Military Standard). The Embedded C Coding Standard was developed by Netrino to minimize firmware bugs by creating rules that keep bugs out while also improving the maintainability and portability of embedded software. The coding standard details guiding software programming principles, specifies naming conventions and outlines rules for data types, functions, preprocessor macros, variables and much more. Individual rules that have been demonstrated to reduce or eliminate certain types of bugs are highlighted. The C language is widely used by organizations in the development of safety-critical software applications. The LDRA tool suite provides the most comprehensive C coding standards enforcement available on the market today. Support of the Netrino Embedded C Coding Standard extends LDRA’s already comprehensive list of C/C++ language standards.

Actel Announces Keil’s Support of New SmartFusion ASP Family Actel has announced that Keil now supports the application services platform (ASP)


family in the Keil  MDK-ARM Microcontroller Development Kit. The latest release of MDK-ARM  supports the ARM Cortex-M3 microcontroller subsystem (MSS) on SmartFusion devices and includes setup files, device-specific views and example projects. MDK features the industry-standard compiler from ARM, the Keil uVision4 Integrated Development Environment, the fully functional  RTX  RTOS and sophisticated analysis tools. MDK provides a complete development environment for creating, debugging and verifying embedded applications. SmartFusion, the first intelligent ASP, integrates an FPGA, hard ARM  Cortex-M3-based

MSS and programmable analog, offering full customization and ease of use. SmartFusion devices meet the needs of hardware and embedded designers who require a true system-onchip (SoC) solution that is more flexible than traditional fixedfunction microcontrollers and less costly than soft processor cores on conventional FPGAs. MDK-ARM v4.10 is available for download now at www.keil. com/demo/eval/arm.htm.  

Express Logic ThreadX Available for Tensilica’s Dataplane Processor Cores

Tensilica and Express Logic have announced that Express

Logic’s ThreadX real-time operating system (RTOS) is now available for Tensilica’s new third-generation Diamond Standard dataplane processor (DPU) cores. A free demo download of the ThreadX RTOS is available on the Tensilica Web site. Designed for small-footprint, demanding real-time control, the ThreadX RTOS is a suitable match for the Diamond Standard family of general-purpose, low-power cores aimed at deeply embedded control and signal processing functions. ThreadX is designed for fast real-time performance. It helps applications quickly respond to external events with its priority-based, preemptive scheduling. It is also deter-

ministic, providing bounded real-time response regardless of the size of the application. A high-priority thread starts responding to an external event in the amount of time it takes to perform a highly optimized ThreadX context switch—under 250 nanoseconds on a DPU core running at 1 GHz. It is also small with a minimum kernel size under 2 Kbytes. Tensilica’s Diamond Standard series DPU family covers a broad range of embedded control performance with synthesizable cores ranging from a very small 32-bit ultra-low-power, cache-less RSIC DPU to a powerful highperformance 3-issue VLIW processor.

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at rtec10.com Closing Price 52 Week Low 52 Week High Market Cap

RTEC10 Index

41.75

150.66

Adlink Technology

1.25

1.16

1.26

150.53M

Advantech

2.06

2.01

2.06

1M

370.43

363.46

370.43

84.54M

Enea

4.87

4.86

4.88

89.4M

Interphase Corporation

2.08

2.08

2.13

14.21M

Kontron

8.19

7.98

8.29

455.95M

Mercury Computer Systems

11.75

10.76

12.05

278.2M

Performance Technologies

2.64

2.64

2.76

29.35M

PLX Technology

4.64

4.25

4.77

171.88M

RadiSys Corporation

9.62

9.33

9.82

231.51M

Company Market Performance

Elma Electronic

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: www.vdcresearch.com

9

RTEC10 involves time sensitive information and currency conversions to determine the current value. All values converted to USD. Please note that these values are subject to certain delays and inaccuracies. RTCRTC MAGAZINE MAGAZINEMONTH MAY 2010 Do not use for buying or selling of securities.


SMALL FORM FACTOR

FORUM

Colin McCracken & Paul Rosenfeld

LAN’s End Is Just the Tip of the Iceberg

D

evice manufacturers and OEMs have been “trained” that processor and chipset vendors determine the life cycle of single board computers (SBCs) and computer-on-modules (COMs)—typically 5 to 7 years. However, there’s more to SBCs and COMs than meets the eye, meaning that EOL of any other active component can wreak the same havoc on your product line as the EOL of processors and chipsets. Clock generators, super I/O chips, Ethernet controllers, switchers, regulators and embedded controllers for power rail sequencing are all lurking behind the scenes. And an end of life notice for any of these ICs can bring your SBC or COM board to EOL just as rapidly as the EOL of a processor or chipset. While some SBC vendors have been known to stockpile low-cost ICs without notifying customers of end of life, this puts you at the mercy of their forecasting accuracy. Right now, certain LAN controllers are testing the will of embedded suppliers and customers. The PCI-based 10/100 Ethernet controller has become entrenched throughout the entire embedded market as stand-alone systems have given way to connected ones. These controllers are well supported in all major operating systems with all major RISC and CISC architectures. Alas, thanks to desktop market churn, all good ICs must come to an end. High-volume desktop markets have already moved to PCI Express x1 Gigabit Ethernet controllers, while server blades are all the way to the 10Gig realm. It’s the end of the ubiquitous PCI LAN controller as we know it. Intel is well into its 12-month EOL / last-time buy period for all of its PCI 10/100 controllers. This paves the way for VIA, Realtek, Davicom and National controllers to follow suit unless any of these chip vendors have thoughts about grabbing market share by extending the life of their chips. Besides the many board designs that will be affected, many off-the-shelf small form factor (SFF) boards are quite exposed to this EOL as well. Specifically impacted are ETX and active backplane SBCs (EBX, EPIC and PC/104-Plus form factors), primarily those using Pentium M, Celeron M and even Geode platforms. Most board suppliers are coming clean about how

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MAY 2010 RTC MAGAZINE

long production could last, since the last-time order date for the popular 82551 MAC+PHY and 82562 PHY chips is upon us.  Many ETX manufacturers have switched over to designing COM Express, CoreExpress, or Qseven modules exclusively by now, so good luck finding a drop-in ETX replacement with a non-EOL 10/100 PCI Ethernet controller. Unfortunately, GigE requires two more differential pair signals, which were never part of the ETX interface definition and hence cannot be easily adopted into an ETX solution. The four ETX reserved pins are spread out all over the place, unsuitable for design rules that require signal pairs to be routed closely together. While a few opportunistic module vendors may change LAN vendors to save system OEMs from a horrific baseboard redesign fate, they only delay the inevitable. Stackable architectures are impacted in a much more dramatic way. It’s not just a matter of replacing one module with another as in the ETX case. Affected 10/100 LAN cards use the PCI bus on a 3.6” x 3.8” (PC/104 or ISM form factor) card. But replacement Gigabit cards require a PCI Express bus. Thus the SBC baby must get thrown out with the LAN bath water. And this can lead to a disaster as support for your ISA-based I/O cards could disappear as well unless you can find an SBC that provides both PCI Express AND legacy PC/104 ISA support up the stack. At least the LAN controller issue won’t be repeated. In many cases, the LAN controller is now integrated into the chipset. Hence, new Atom- and Nano-based SBCs come with PCIe GigE on board as if part of a re-emergence SBC comeback world tour. In addition, legacy-free COM Express modules and MiniITX SBCs also build the LAN controller into the basic feature set. Some new SBCs blend PCIe GigE with legacy-friendly ISA stacking. From the device driver point of view, PCIe is a transparent change from PCI. But in regulated markets such as avionics and medical, a change is a change, and the driver for the new LAN controller must be installed and a new OS image generated and re-qualified. After placing your last-time buy, update your design and drop us a line at sf3@rtcgroup.com.


5 YEARS OF EVOLUTION LEADS A TECHNOLOGY REVOLUTION! The biggest and most successful 32-bit event in the world, once exclusively dedicated to ARM cores, has opened its doors to all providers in the embedded industry.

2005-2008: ARM Developers’ Conference – Launch and build the largest gathering of engineers, developers and decision makers committed to ARM technology.

2009: ARM techcon3 – Expands to include three distinct facets of the electronic design process: MCU & Tools, Internet Everywhere, and Energy Efficient SoC Design.

2010: Global Technology Congress – Opens the conference to all processor technologies and their surrounding ecosystems to create the largest 32-bit embedded event in the world.

2010

STAY CONNECTED

www.globaltechnologycongress.com October 5-7, 2010 Santa Clara Convention Canter


editor’s report New Developments from the Field

Power Analysis Debug, Java and Specs Figure 1

Just in time for the May issue are some interesting developments—among many—found in expeditions around Silicon Valley and environs. by Tom Williams, Editor-in-Chief

A

re you worried that perhaps your sub-watt processor core is drawing too much power? With an increasing number of CPUs offering more sophisticated power management options, such as a variety of sleep modes and the ability to selectively shut down on-chip peripherals, there is a growing need to correlate and analyze these activities with the application code. Even more options include voltage scaling, clock scaling and partial use of networks. Now technologies are starting to come online that will enable the measurement of power consumption correlated with the execution of the code. Pioneering this approach is Hitex Development Tools, which has introduced its PowerScale probe with active current measurement (ACM) technology. The PowerScale box connects to the PC with a USB cable and can have up to four probes connected to the system under test. Standard probes measure current ranging from 1mA to 1A, to a maximum voltage of 58V. The ACM probes can measure current as low as 200 nanoAmps up to 500 nA with a maximum voltage of 12V (Figure 1). PowerScale can be connected to the system using any combination of probes for a total of four power domains that can be measured in parallel. The probes connect to the power supply line and to ground. The probes contain the necessary shunt resistors that fit into the given current range to be measured. Even with the ACM range that covers from

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MAY 2010 RTC MAGAZINE

200 nA to 500 nA, the voltage drop is only about 0.1V. Thus even when the current rises extremely quickly, the voltage drop is small enough that the processor can continue operating normally. In addition to the USB adapter, there is also a power over Ethernet adapter that allows the connection of the probe to Ethernet-powered systems. Hitex offers a graphical user interface that displays the diagnostics of power consumption. The normal PowerScale view shows the current, power and voltage views over a measured time segment. With the additional use of the trigger pin, application events can be collected and shown as markers in the trace. There is also a bin statistic view that answers questions like how much time the microcontroller was in deep sleep mode, what percentage of time the WLAN module was active and more. PowerScale also provides an open API that will allow PowerScale to be integrated with source code debuggers and other software development tools and tool suites. When this occurs, it will be possible to observe changes in power consumption associated with actual code execution and will open the possibility for the developer to optimize execution for power consumption. For example, if a given segment of code does not require a given on-chip peripheral, that peripheral can be turned off and the power savings measured. While Hitex does supply compilers and a debugger, its primary expertise

The Hitex PowerScale module supports four probes in parallel capable of sampling two different power domains in any combination. The ACM probe (bottom right) is capable of measuring very low currents directly on the processor pins.

is in hardware tools such as JTAG debug tools, analyzers and in-circuit emulation. Partnerships with companies whose primary expertise lies in IDEs and software development tools would be a natural and is something that Hitex is also pursuing. Another effort in this arena is being pursued by just such a company, IAR Systems, whose Embedded Workbench and C/C++ compilers support a range of processors including ARM, Atmel, Freescale Coldfire, Microchip, ST Microelectronics, Renesas and more. IAR had launched an effort to develop a low-power debugging solution as well, which is to be added to its Embedded Workbench IDE. IAR is developing a probe technology called J-Link Ultra that will be able to perform analog power measurement to a resolution of 1 mA at a 50 kHz sampling rate. Unlike the PowerScale probe with its two probe options, J-Link Ultra is intended for connection to the board’s power supply pin, which measures the power consumption of the whole system. The probe uses JTAG or serial wire output (SWO) to the probe, which also contains a power sampling subsystem. This enables the instructions that are read by the normal debug probes to be correlated with the timing and measurement of the power consumption. Currently, the IAR effort is a work in progress on the probe side in somewhat the same way the Hitex is on the debugger side. IAR has the connections to the J-Probe Ultra and its internal power sampling as well as interfaces for debug and power to the Embedded Workbench


editor’s report

tool suite, and additional features will be added (Figure 2). Interestingly, IAR Systems also appears to have a partners program that will allow the integration of third-party probes in the future. This could conceivably include such devices as the Hitex PowerScale with its standard and ACM probes that would enable the monitoring of the actual processor power pins along with the board power supply and tight association with the display of the code in the familiar debugger environment rather than an oscilloscope-like display.

Java Improves Multicore Garbage Collection

One of the biggest problems in adapting Java for real-time perfo rmance has been adapting the garbage collector so that it does not interfere with scheduling. Garbage collection (GC) retrieves previously allocated sections of memory that are no longer needed by the code. This is a problem made more complex by multicore architectures. Now a newly formed company, Atego, has released Aonix Perc Ultra SMP 5.4 with support for concurrent multiprocessor garbage collection technology. Aonix Perc Ultra SMP responds to the need for multiprocessor and multicore solutions in complex mission-critical embedded and real-time Java applications. Aonix Perc Ultra SMP, first introduced in 2008, provided parallel GC that allowed the use of all processors/cores for faster identification and collection of unused objects. A dual quad-core Xeonbased Linux real-time system could collect discarded memory nearly eight times faster than a single-threaded garbage collector but could not run concurrent with other application threads until now. The new version of Perc Ultra further improves the efficiency of the garbage collection process by implementing concurrent GC. Compared to parallel GC, concurrent GC allows collection of unused objects by multiple processors while Java application threads continue to operate concurrently. Perc Ultra’s GC dynamically allocates available processors/cores to perform garbage collection tasks without disrupting active Java threads on other cores. This enhances the

IAR Partner Program . Allow Partners access to C-SPY . Quality Control RTOS Partners

New features in IAR Embedded Workbench

Power Partners

Expanded Trace and Power debug options

(3rd Party Probes)

PCB ARM Cortex

JTAG/ SWO Power

JTAG/ SWO

Debug API JTAG/ SWO

Power Sampling Power

Power

IAR J-Link Ultra

IAR Embedded Workbench

Power API Power on Pin19

3rd Party power probes (in the future)

Figure 2 The IAR systems J-Link Ultra samples power levels in parallel with the debug interface and presents the measurements to the debugger. This illustration shows the roadmap for the technology.

ability of the GC to pace the garbage collection rate to the application’s memory allocation rate.

SFF Starts Searchable Database, Improves USB Channel

A few developments out of the Small Form Factor SIG: The Small Form Factor SIG has set up a searchable product database that allows member companies to document their compatible products and OEMs to search online for products that meet their needs. The database provides classifications for products meeting any of the seven specifications released by the SFF-SIG, and defines eight product categories covering CPUs, I/O expansion boards, mass storage and connectors. Each product listing contains a photo, feature bullets, descriptions and a link to a data sheet in .pdf format as well as a link to the member company’s site. In addition, the Stackable Unified Module Interface Technology (SUMIT) specification has been upgraded to revision 1.5 offering two improvements. First, it describes the implementation of channel shifting in SUMIT-based systems. Channel shifting in stackable systems means that when an I/O card consumes a resource such as a USB channel or PCI Express lane, it shifts the remaining available resources of a like kind to the pins used by the consumed resource when they are passed to the next I/O card

above on the stack. Thus a card that uses USB channel 0 would shift channel 1 signals to channel 0, channel 2 to 1, channel 3 to 2 as the signals are passed up the stack. Each board is assured of a USB port being available up to the number of ports provided. No hardware or software decoding is required. In addition, SUMIT revision 1.5 describes a simple resource label that conveys the interoperability of a company’s SUMIT-compatible product since all the defined interface signals may not be supplied by a given SBC or I/O module. For SBC cards it shows the resources available and for I/O cards it shows the resources consumed. This provides a quick way for designers to match the labels between I/O cards against the SBC resource label to determine if the required interfaces and power are available. Hitex Development Tools Irvine, CA. (949) 863-0320. [www.hitex.com]. IAR Systems Foster City, CA. (650) 287-4250. [www.iar.com]. Atego San Diego, CA. (888) 824-0212. [www.atego.com]. Small Form Factor SIG [www.sff-sig.org].

RTC MAGAZINE MAY 2010

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Technology in

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Making the Most of Multicore

Multicore Software: To Gain Speed, Eliminate Resource Contention Even when applications are parallelized over multiple cores, performance can suffer from resource contention. Parallelizing the access to resources can eliminate much of the contention.

by Steve Graves, McObject

D

Table1 Table2 Table3 eployment on multicore CPUs T3 R1 T2 R1 T1 R1 T3 R2 T2 R2 T1 R2 should make software faster by enT3 R3 T2 R3 T1 R3 T3 R4 T2 R4 T1 R4 abling tasks to run in parallel rather T3 R5 T2 R5 T1 R5 than waiting for a time slice on a single core. But in practice, parallel processing on multiple cores can introduce contenT3 R3 T1 R3 T3 R1 Read Only tion for system resources, making an apT1 R5 T2 R5 T3 R3 T3 R5 T3 R2 plication slower than when it is deployed Task1 Task2 Task3 on a single core. Achieving multicoreâ&#x20AC;&#x2122;s hoped-for linear performance gains hingFigure 1 nies providing solutions now es on resolving this issue. By examining ion into products, technologies and companies. Whether your goal is to research Three the latesttasks running in parallel have resulted in two versions of a database two examples of such a conflict andofthe ation Engineer, or jump to a company's technical page, the goal Get Connected to put you row is(T3R3). proven solutions to them, we can get to the you require for whatever type of technology, and productsconceptual you are searching for. starting point for solutions to database while a single task updated it, intensive applications where data must be similar resource contention bottlenecks. thereby blocking all other tasks from writ- changed often and where many tasks are ing to the database (or portions of it) during running on multiple cores. Database Contention the modification. In contrast, MVCC is an Under MVCC, when tasks want to The first conflict is contention in up- optimistic concurrency model in which no update the same data at the same time, a dating a shared data store, and its solution task or thread is ever blocked by another conflict does arise and a retry will be reis called multi-version concurrency control because each is given its own copy (ver- quired by one or more tasks. However, an (MVCC). Until recently, nearly all data- sion) of objects in the database to work occasional retry is far better, in perforbase management solutions for embedded with during a transaction. When a transac- mance terms, than the guaranteed blocksystems used a pessimistic concurrency tion is committed, its copy of the objects it ing caused by pessimistic locking. Further, model that locked all or portions of the has modified replaces the objects in the da- in most systems conflicts under MVCC are tabase. Because no explicit locks are ever assumed to be infrequent because of the required, and no task is ever blocked by an- logically separate duties among tasks, that Get Connected with companies mentioned in this article. other task with locks, MVCC can provide is, task A tends to work with a different set www.rtcmagazine.com/getconnected significantly faster performance in write- of data than tasks B, C and D, etc.

End of Article

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Figure 1 compares MVCC to pessimistic locking, in operation. The diagram shows three tables in a database, each with five rows, and three tasks that are reading and/or modifying certain rows of certain tables. Task 1 is modifying Table 1’s row 3 (T1R3) and Table 2’s row 5 (T2R5). Task 2 is modifying T3R1, T3R3 and T3R5. Task 3 is reading T3R3 and modifying T1R5 and T3R2. Note that there are two copies (versions) of T3R3: a copy in Task 2 and Task 3. For purposes of this discussion, assume that all three tasks are started as close together in time as possible, but in the order Task 1, Task 2, Task 3. With MVCC, the three tasks run in parallel. With pessimistic locking, there are three possibilities: database locking, table locking and row locking. Each will exhibit different degrees of parallelism (but all less than MVCC). Database locking: Task 1, Task 2 and Task 3 will be serialized. In other words, Task 1 will be granted access to the database while Task 2 and Task 3 are blocked as they “wait their turn.” When Task 1 completes its transaction, Task 2 will run while Task 3 continues to wait. Finally, Task 3 will run after Task 2 completes its transaction. Table locking: Task 1 and Task 2 will run in parallel because Task 1 acquires locks on Table 1 and Table 2, while Task 2 acquires locks only on Table 3. Task 3 will block until Task 1 and Task 2 complete because it also needs a lock on Table 1 (which is locked by Task 1) and Table 3 (which is locked by Task 2). Task 3 will be blocked for the length of time required by Task 1 or Task 2, whichever is greater. Row locking: Again, Task 1 and Task 2 will run in parallel because they operate on different tables, (hence on different rows). Task 3 will again block because Task 2 has a write lock on T3R3, which Task 3 wants to read. Any serialization effectively defeats a multicore system; all but one core will be idle with respect to the utilization of the shared resource (in this instance the database). However, strategies to maximize parallelism, such as MVCC or finegrained locking, impose their own overhead. In the case of fine-grained locking (row locking) there is lock arbitration,

which can be complex. In the case of MVCC, there is version management— creating object versions, merging them and discarding them. So for MVCC to be justified, the gain in parallelism has to outweigh the additional processing overhead. To illustrate, the graphs in Figures 2, 3 and 4 show the relative performance of McObject’s eXtremeDB in-memory database system on identical multithreaded tests executed on a multicore system, using a multiple-reader, single-writer (MURSIW, or database-locking) transaction manager, and its multi-version concurrency control (MVCC) transaction manager. In all three cases, the performance gains tail off. This is due to the increasing amount of housekeeping with each new thread—which becomes a greater percentage of the total processing time—and increased contention for data structures within the DBMS runtime. Systems less complex than a DBMS would probably see linear improvement extended farther to the right (i.e. to more cores). Conversely, there is virtually no processing overhead inherent in the MURSIW (database-locking) transaction manager—it is extremely lightweight, and performance remains nearly constant regardless of the number of concurrent threads.

Memory Allocation

A second example of resource contention in multicore, multithreaded systems involves the C/C++ heap. Normally, the C runtime library provides malloc() and free() (or C++’s new and delete) functions that allow applications to allocate and release memory from/to the heap. Application developers tend to use these functions liberally, without thinking about how they actually work. What’s going on “under the hood” is that the heap is organized as a pool of contiguous memory locations (often called free holes) referenced by a singly linked chain of pointers. The allocator services a request for memory allocation by traversing the chain looking for a large enough free hole. In a multithreaded application, the allocator’s chain of pointers is a shared resource that must be protected. Chaos would ensue if a thread, while in the process of breaking the chain to insert a new link, was interrupted by a context switch


technology in context

Insert Performance 8,000,000 7,000,000

Objects per second

6,000,000 5,000,000 4,000,000 MURSIW

3,000,000

MVCC

2,000,000 1,000,000 0 1 2

3 4 5 6

7 8

9 10 11 12 13 14 15 16 17 18 19 20 Threads

Figure 2 Insert Performance

Update Performance 4,000,000 3,500,000 Objects Per Second

3,000,000 2,500,000 2,000,000 MURSIW

1,500,000

MVCC

1,000,000 500,000 0 1 2

3 4 5 6

7 8

9 10 11 12 13 14 15 16 17 18 19 20 Threads

Figure 3 Update Performance

Delete Performance 3,500,000 3,000,000 Objects Per Second

and another thread tried to walk the (now broken) chain. To prevent this sort of interruption, the chain is protected by a mutex to prevent concurrent access and preserve the allocator’s consistency. On single-core systems the latency caused by this locking is minimal, because the CPU is kept busy by processes unrelated to memory management. On a multicore system, though, a phenomenon arises that is similar to the one described above involving the shared data store: all but one core will be idle, with respect to the utilization of the shared resource. In other words, if the applications were doing nothing but allocating and freeing memory, the threads would be serialized due to the mutex. So, the extent of this problem for any particular application is directly proportional to the amount of dynamic memory management used. In the data store example discussed previously, contention is solved by giving each process a copy of the relevant object to work with. Similarly, when threads “fight” over access to the memory allocator, an effective solution is a custom memory manager that provides a separate memory allocator for each thread, so that each allocator manages memory independently of the others. This approach is called a thread-local allocator. The thread-local allocator avoids creating locking conflicts when objects are allocated and released locally, in one task/ thread. When allocating memory in one task and de-allocating the same memory in another task, a lock is, of course, required. However, this allocator takes measures to minimize those locking conflicts. To illustrate the benefit, we created a thread-local memory manager that is based on a block allocator. A block allocator imposes less metadata overhead than a standard list allocator, for the following reasons. In use, it is given a quantity of memory and divides this chunk into equal sized pieces, which it organizes in a linked list of free elements. Blocks are guaranteed to be the same size, so unlike the list allocator, the block allocator does not need to keep track of the size of each block. A block allocator also eliminates fragmentation because blocks are all of equal size, therefore when freed, they are

2,500,000 2,000,000 MURSIW

1,500,000

MVCC

1,000,000 500,000 0 1 2

3 4 5 6

7 8

9 10 11 12 13 14 15 16 17 18 19 20 Threads

Figure 4 Delete Performance

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Figure 5 A block allocator allocates and deallocates all objects locally and so needs no synchronization.

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not, and do not need to be, joined with adjacent free blocks. The allocator creates and maintains a number of linked lists (called chains) of same-size “small” blocks that are made out of “large” pages. To allocate memory, the allocator simply “unlinks” the block from the appropriate chain and returns the pointer to the application. When a new large page is necessary, the allocator uses a general-purpose memory manager (standard malloc) to allocate the page. This algorithm does not require any synchronization as long as all objects are allocated and de-allocated locally by the same thread. When objects are not de-allocated locally, the memory manager maintains a pending-free requests list (PRL) for each thread. When an object allocated in one thread is being de-allocated by another thread, the de-allocating thread simply links the object into its PRL list. Of course, PRL access is protected by a mutex. Each thread periodically de-allocates objects in its PRL. This can occur based on a timer, or when a certain number of requests are pending, or according to some other application-specific criteria. It’s important to note that regardless of those criteria, the number of synchronization requests is reduced significantly by using a thread-local allocator. First, objects are often freed by the same thread that allocated them; secondly, even when the object is de-allocated by a different thread, it does not interfere with all other threads, but only with those that need to use the same PRL. The thread-local allocator is depicted in Figure 5. McObject

performed two tests to examine the impact of the thread-local memory manager in allocating memory for 10 million objects and then freeing it. The first test compares performance of the thread-local allocator and the standard C runtime allocator (malloc) when the allocation pattern is local: all de-allocations are performed by the same thread as the original allocations. The second test compares performance when objects are allocated by a “producer” thread and freed by a “consumer” thread, using both thread-local and standard (default) allocators. Results of the first test, using 24 threads and running on a 24-core machine, are shown in Figure 6. Thread-local allocation results in a performance advantage of more than 600%. Note that the application’s 24 threads are all trying to allocate and then free 10,000,000 objects each, for a total of 240,000,000 alloc/ free pairs (480,000,000 malloc/free calls). Because of the lock conflict, they all get serialized (run one at a time) when using the standard malloc allocator, which is why it takes more than 10 minutes. In contrast, the thread-local allocator has no conflicts for “local” allocations, so all 24 threads run in parallel. Figure 7 depicts the results of the second test, in which every object is freed by a thread other than the one that allocated it. This test used just two threads, in order to isolate the performance difference to just the reduced synchronization requirements of the thread-local allocator, even when all allocations are “global.” Overall time to complete is less than in the first


technology in context

Local Allocations 10,000,000 alloc/free X24 threads, 24 cores

“local” TLA

1

Elapsed Time (seconds) “local” malloc

653

0

100

200

300

400

500

600

700

Figure 6 Performance of thread local allocator vs. standard C malloc.

Global Allocations 10,000,000 alloc/free X 2 threads, 2 cores “global” TLA

24

Elapsed Time (seconds) “global” malloc

28

22

23

24

25

26

27

28

29

Figure 7 Global allocation/deallocation performance of TLA vs. malloc.

test, because fewer threads are running (2 vs. 24). In both cases, the performance gap between thread-local and standard allocation mechanisms is smaller due to the overhead associated with the “handoff” of responsibility for de-allocation from one thread to another. But the thread-local allocator, by reducing synchronization requests via the PRL, turns in a 14% performance gain. A real-world application would have a blend of “local” and “global” allocation patterns, and would exhibit a performance difference somewhere between the two charts depicted here. The results would be more like Figure 6 if the preponderance of the pattern is “local,” and more like Figure 7 if the pattern is more “global.” Multicore CPUs add the potential for performance gains by allowing threads to execute in parallel. But software often lags in taking advantage of this capability. Even programs that use multitasking and multithreading can be hobbled when these processes are

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forced to contend for a system resource. In such situations, overall application performance can depend heavily on its efficiency in granting access to the resource. The examples above should be recognizable to programmers as involving typical shared resources: application data, and the software’s memory allocation function. In both cases, significant performance gains are obtained through a solution that makes a copy of the resource available to each task. While processing is (sometimes) required to merge or pass results, this overhead is easily outweighed by the increase in efficiency that results from elimination of resource contention. McObject Issaquah, WA. (425) 888-8505. [www.mcobject.com]


ploration your goal k directly age, the source. ology, d products

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Making the Most of Multicore

Optimizing Multicore Software for Embedded Processors Multicore technology offers new performance potential. But to take advantage of that potential, software tools must be leveraged to implement parallelism across single and multiple cores.

by Stephen Blair-Chappell and Max Domeika, Intel

T

he use of multicore processors in em__m128i Tmp1; // example of 128bit SSE2 register bedded systems is increasing. These _mm_and_si128(.., ..); // AND processors, which are two or more _mm_setzero_si128(); // init to zero processor cores on one package, enable _mm_cmpeq_epi32(.., ..); //IS EQUAL increased computation performance and _mm_storeu_si128(.., ..); // copy results to memory optimized power utilization compared to single core processors. Multicore procesFigure 1 sors are already employed in a number of embedded market segments such as teleExample of some compiler SIMD intrinsic instructions. communications and digital surveillance. nies providing now Typically, in order to fully take adUsesolutions is increasing in embedded systems cessor core is similar. This is opposed to ion into products, technologies and companies. Whether your goal is to research the latest vantage of technologies such as SMT, heterogeneous multicore processors where where low power and small form factor ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you homogeneous multicore processors and the processor cores implement different constraints are paramount. you require for whatever type of technology, SIMD instructions, software changes must instruction set architectures (ISA). MultiThere are for. many types of multicore and products you are searching be made. Employing the proper software core processors improve performance by processors. Two examples, which are the tools can go a long ways toward being efenabling the software developer to utilize focus here, are simultaneous multithreadficient in design, implementation, debug parallelism in their application. ing (SMT) and homogeneous multicore. Another form of processor technology and tuning of your application. SMT is the ability of one physical procesFirst, as an example, we share an sor core to mimic multiple logical proces- that enables developers to take advantage of parallelism in their applications is single overview of the Intel Atom processor sor cores. With SMT, as far as the operatinstruction, multiple data (SIMD) instrucwith a focus on the hardware features ing system and the applications executing on the operating system are concerned, that tions. SIMD instructions enable the same that enable developers to take advantage one processor core appears to be a multi- operation to be performed on multiple data of parallelism. Second, we discuss the core processor. A homogeneous multicore items at the same time. Another term for software tools that lend themselves to enprocessor is one where each physical pro- SIMD is vector, because these data items acting parallelism and helping developcan be logically grouped into vectors. Intelâ&#x20AC;&#x2122;s ers at all phases of the development cyGet Connected version of SIMD instructions is comprised cle. We show coding examples that help with companies mentioned in this article. by Intel Streaming SIMD Extensions. reinforce the discussion. www.rtcmagazine.com/getconnected

End of Article

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Get Connected with companies mentioned in this article.


technology in context

Intel Atom Processor Architecture

The Intel Atom processor architecture is an in-order processor capable of retiring two instructions per clock cycle. The clock speeds available in currently shipping products range from 800 MHz to 2.0 GHz. The processor supports Intel MMX, Intel SSE, Intel SSE2, Intel SSE3 and Intel SSSE3. These are all forms of SIMD instructions that enable vector computation on integers, single-precision and double-precision floating point numbers in combinations comprising a 128-bit register. Software modifications are required to take advantage of these extensions. These modifications can be in the form of direct coding or employing tools and libraries that make use of the instructions. SMT support in the Intel Atom processor is provided by Intel HyperThreading Technology. Internally, the processor enables instructions from two different threads to make use of the microarchitecture so that if one thread is stalling inside the pipeline, a second thread can take advantage of the idle process resources. Multithreading is one means of taking advantage of the additional processing power available from SMT. There are performance issues specific to SMT of which to be aware. Since processor resources are shared between processes, and threads execute concurrently, the cache available per thread is effectively halved. This consideration should be a part of any design effort to take advantage of SMT. In the worst case, it is possible for two threads to cause each other to repeatedly miss in the cache. The multicore versions of the Intel Atom processor consist of two processor cores only at this point in time. Each processor core supports SMT so a total of four threads can execute concurrently on a system based upon the processor. As with SMT, multithreading is a mechanism to take advantage of the processing power. During multithreaded application development and tuning, at-

Gap Remains Between Multicore Potential and Software Realization by Eric Heikkila, Venture Development Corporation VDCâ&#x20AC;&#x2122;s embedded hardware and systems research practice recently surveyed over 200 embedded developers who were using multicore processors. The results showed that there is still a major gap between the multicore silicon available on the market and the software solutions available to work effectively with multicore processors.

Biggest Challenges/Gaps Encountered Using Multicore Processors (Percentage of Embedded Developer Respondents Identifying)

Software Development Tools Programming Model Software Drivers and Middleware Performance Analysis Download/Connection Speed Cross Triggering System Visibility Trace Other

73.1% 64.2% 46.3% 41.8% 35.8% 29.9% 20.9% 13.4% 1.5%

The table shows that when we surveyed these embedded multicore users, the top three challenges/issues with multicore processor use encountered by the respondents were software related. In particular, there is still a dearth of software tools that are easy to use and effectively work with multicore processors to fully maximize the performance offered by multicore and to also take advantage of the existing user knowledge/experience with parallel programming. It is important to note, however, that this gap has not significantly slowed the rapid adoption of multicore processors. Instead, it has simply limited the multicore processors they are already using. Over the past two years the gap between multicore hardware and software solutions has been closed significantly by a lot of hard work on the software side and many great solutions to challenges of multicore, but there is certainly still a long ways to go to close the gap entirely. Venture Development Corporation Natick, MA. (508) 653-9000. [www.vdresearch.com].

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technology in context

tention should be paid to how threads are executing on the processor cores. Performance issues concerning thread contention, workload balance and cache behavior must be remedied. Tools support can help in this endeavor.

Strategies for Parallelization

Parallelization is a “hot topic.” Programmers are increasingly facing up to the challenge of writing parallel code.

When programming for multicore it is easy to slip into the mistaken belief that writing parallel code is the answer to improving efficiency. In many cases writing programs that take advantage of SIMD extensions can bring a performance benefit in excess of any boost that multithreading can bring. Three programming practices stand out as being hugely beneficial: • Accessing SIMD instructions using Intel SSE

• Automatic vectorization • Parallelizing code Most compilers support the use of SIMD instructions through the use of inline assembler or compiler intrinsics. Using compiler intrinsics rather than assembler is much easier because the compiler takes care of some low-level details such as register allocation. To make best use of these SIMD intrinsics, the programmer will need to think carefully about how an application algorithm can be modified to take full advantage. With a little effort it is possible to obtain some huge speedups. Figure 1 shows some intrinsics that were used in a Sudoku solver—in this case it realized a speedup of 20. Auto-vectorization is a technique where the compiler automatically replaces traditional instructions with SIMD instructions. Calculations in loops are prime candidates for auto-vec-

Analyze Code Look for Hotspots

Implement Parallelism

Validate & Check for Parallel Errors

Tune Parallel Applications Figure 2 This four stage development cycle is widely accepted as the best way to introduce parallelism into an existing program.

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technology in context

1: #pragma omp parallel for 2: for(int i = 0; i < 100000 ; i++) 3: DoWork(i); Figure 3(a) – a parallelized loop 1: #pragma omp parallel 2: { 3: #pragma omp sections 4: { 5: #pragma omp section 6: DoWork(); 7: #pragma omp section 8: DoSomeMoreWork(); 9: } 10: } Figure 3(b) - two parallel sections 1: #pragma omp parallel 2: { 3: #pragma omp single nowait 4: { 5: for(int i = 0; i< 100000 ; i++) 6: { 7: #pragma omp task firstprivate(i) 8: DoWork(); 9: } 10: } 11:} Figure 3(c) – using OpenMP tasks Figure 3

can further improve the performance of the code. Nearly all the effort in adopting parallelism focuses on how to make existing programs take best advantage of multicore. In a recent roundtable discussion between some key developers in the industry, porting of legacy code was the number one concern. Figure 2 shows one of the most common strategies employed when turning a non-parallel program into parallel. The process is incremental, the cycle being repeated many times as different parts of the application are made parallel. This same strategy can be used for embedded applications. At the analysis stage, the application is profiled to find the code that uses the most CPU time, the hotspots being potential candidates for parallelization. It is normal that code higher up in the calling hierarchy is parallelized rather than the hotspot itself. Any profiling tool such as GNU gprof, Intel VTune Analyzer, or Intel Parallel Amplifier can be used to determine the hotspots. At the implementation stage, parts of the code are made parallel. Parallelism can be implemented in the code by a variety of means including native threads, language extensions such as OpenMP, or by using threaded libraries. At the validation stage, attention is directed to detecting parallel errors such

as data races and deadlocks. These types of errors can be notoriously difficult to find. Some programmers choose not to make their code parallel because of their anxiety about detecting such paralleltype errors. To efficiently check for parallel errors it is important to use tools that are dedicated to the purpose such as Intel Thread Checker, Intel Parallel Inspector, or Valgrind. Some checks can be accomplished by a careful codereview or static analysis of the code, but it is advisable also to do some runtime checking since not all errors can be captured by simple code inspection. In the tuning stage, the application is analyzed with respect to load balancing and threading overhead. Here is where you address such questions as, “Are all the threads performing an equal amount of work?” and, “Is my program scalable?” As previously mentioned, OpenMP can be used to implement parallelism and is a favorite of many programmers. OpenMP allows C\C++ and Fortran programmers to add parallelism to their code by using a combination of compiler pragmas and calls to OpenMP library functions. Various work-sharing constructs can be used to distribute work between a pool of threads. Some programmers use OpenMP for rapid prototyping. Once satisfied that there will be a performance gain, they re-imple-

Three different ways of parallelizing code in OpenMP.

torization. By using SIMD instructions, the compiler can reduce the number of iterations such a loop needs to execute. Usually little or no intervention is needed by the programmer other than to make sure this option is enabled in the build. Not all compilers support autovectorization. While talking about producing optimized code, it is worth repeating that our example processor, the Intel Atom, has an in-order execution engine. Normally compilers rearrange instructions assuming an out-of-order execution. When generating Intel Atom processor specific code, it is better to use a compiler that can generate in-order code. Although this is not essential, it

Soft Real-time

Hard Real-time

Threading via low-level primitives

Threading via high-level constructs

Figure 4

Communication via IPC or shared memory

Some embedded designers partition their embedded applications between hard and soft real-time.

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technology in context

ment the parallelism using other means. OpenMP is a well established standard and is supported by all of the major compiler manufacturers. Figure 3 shows three different ways of parallelizing code using OpenMP. In all three examples, a pool of threads is automatically created by the #pragma omp parallel statement. The number of threads created defaults to the

number of hardware threads the platform can support. Figure 3(a) gives an example of parallelizing a loop. In this example the iterations of the loop are divided between the numbers of threads in the thread pool. So for example, on a CPU that supports two hardware threads, the first 50,000 loops will run on one thread and the remaining loops will run at the same

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Based on the Altera Alte era Stratix family of FPGAs for signal processing

For more information, visit bittware.com 26

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time on a second thread. Figure 3(b) shows how to get two functions to run in parallel. Each of the two section statements at line 5 and line 7 run in parallel. Although the code is not scalable, this particular construct can be very useful in embedded programs, where one might want to separate two distinct activities into separate threads running in parallel. Figure 3(c) gives an example of the OpenMP Task construct. This construct can be used in non-loop oriented code such as a linked list or a recursive call. For simplicity the example here uses a loop. The for loop at line 3 runs in a single thread. The loop creates a number of OpenMP tasks at line 7. OpenMP tasks are available for execution the moment they are created; the OpenMP runtime being responsible for distributing the tasks among the thread pool. Support for OpenMP tasks was introduced in OpenMP 3.0, so all compilers do not yet support this construct. Embedded developers are sometimes nervous about using high-level constructs in their real-time applications. Most of the high-level implementations rely on a runtime library that has not been designed for hard real-time requirements. Figure 4 shows one approach to solving this problem. By partitioning the application between hard and soft realtime, low-level threading primitives can be used for the hard real-time code, and high-level constructs used for the soft real-time code. Interval Zeros’s RTX is an example of exactly this approach. Another popular solution for implementing parallelism is Intel Threading Building Blocks (TBB), an open source C++ template library. Although TBB is not suitable for hard real-time code, it is worth considering for programs that have a soft real-time requirement. In the near future there will be other language options for programming in parallel. Two examples from the Intel stable include Ct and Cilk. Intel Santa Clara, CA. (408) 765-8080. [www.intel.com].


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ploration your goal k directly age, the source. ology, d products

Technology

connected Ethernet Hits 40 Gbit, Aims at 100 Gbit

High Levels of Interface Integration to Enable 10, 40 and 100 Gbit/s Ethernet over Optical Nets New devices are enabling the transport of 10 Gbit Ethernet signals from LANs and WANs over metro and long-haul optical transport networks with less overhead and lower cost. by David Yeh, AppliedMicro

I

ncreasing volumes of IP-based network traffic are driving telecommunication carriers and Internet service Equipment providers are already in production with 40 providers to demand faster transmission Gbit networks and some are in the field with 100 Gbit. speeds of 10 Gigabits per second to 100 Gbit/s and now beyond. The long-haul and nies providing solutions metro portions of wide Whether area networks ion into products, technologies and companies. your goal is to research the latest ation Engineer, or jump to a company's technical page, the goaltechof Get Connected to put you are converting from SONET/SDH requiresisinnovation at circuit, line card cal for OTN to be utilized as the common you require for whatever type of technology, protocol for network convergence. nology to Optical Transport Network and system level design. and products you are searching for. Another factor driving carrier miOTN optical services offer many (OTN) technology to send video-rich gration from SONET/SDH to OTN netof the same protection and management Ethernet traffic over the fiber-optic works is the desire to extend Ethernet, features of SONET/SDH networks, but infrastructure to meet volume, perforspecifically 10 Gbit Ethernet (10GbE), without the complexity and cost associmance and cost requirements. To make from the local area network (LAN) into ated with them. OTN optical services are this transition as cost-effective as posthe wide area network (WAN). The caralso better for transparent mapping and sible, networking system OEMs have riers are able to achieve reduced cost transport of native client traffic through to develop multi-protocol, multi-rate, and complexity by preserving the naMetro and long-haul networks. This point high-density line cards to support not tive client signal, particularly 10GbE, is extremely important for client trafonly the legacy SONET/SDH traffic, but also the surging IP/Ethernet and fic where the preservation of clock and through the metro and long-haul transOTN traffic. Accomplishing that goal management information is necessary port network. Standardization is helping to lower for sustaining end-to-end path link comGet Connected munications, without the degradation of the cost of this transition. The 10Gbit with companies mentioned in this article. performance. Of course, being able to Ethernet signal is ideally suited for www.rtcmagazine.com/getconnected maintain client transparency is also criti- transmission across metro and long-haul

End of Article

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MAY 2010 RTC MAGAZINE Get Connected with companies mentioned in this article.


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technology connected

Client XFI/SFI (Serial) (XFP,SFP+) (Shared w/ System)

and SFI4.1 (16bit)

Line

YAHARA G.709 GFEC PM

10GE 10GFC OC-192 8GFC

(MSA) (Shared w/ Line)

PCS/W-IS GFP-F GFP-T Mapper

G.709 GFEC EFEC PM

10GE 10GFC OC-192 8GFC

System

XFI/SFI (Serial) (XFP,SFP+) (Dedicated)

and SFI4.1 (16bit) (MSA) (Shared w/ Client)

10G

System Interface SFI4.2/SFI-5s/XAUI XFI (Shared w/ Client) Figure 1 System-on-chip devices like the one pictured above have multiple optical module interfaces integrated on chip to achieve the low-cost, energy efficient transmission of 10 Gbit Ethernet signals over optical transport networks.

optical transport networks when carriers map it into an optical channel data unit-2 (ODU-2) payload as defined by the International Telecommunication Union (ITU) specification, Sup. 43, Section 7.3. Using this mapping mode, the 10 Gbit Ethernet signal fits entirely into an optical transport unit-2 (OTU-2) signal while maintaining its G.709 standard transmission rate of 10.709 Gbit/s. Additionally, the OTN framing structure also supports forward error correction (FEC) that greatly extends the distances of error-free transmission links, further fueling the rate of adoption for carriers migrating to 10 Gbit services. The OTN structure also scales nicely for 40 Gbit (OTU-3) and 100 Gbit (OTU-4) signals, thus allowing the multiplexing of 10 Gbit signals into 40 Gbit and 100 Gbit signals. With Internet, voice and data traffic continuing to double every 12 to 18 months, the carri-

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ersâ&#x20AC;&#x2122; call for 40 Gbit and 100 Gbit transport networks is becoming palpable. At the device level, the transition is occurring through system-on-chip solutions that provide a rich suite of 10 Gbit client mapping and OTN framing features that enable the multiplexing and transmission of 10 Gbit services over 40 Gbit and 100 Gbit networks.

Higher Transmission Rates

When it comes to meeting the insatiable growth in metro and long-haul traffic, carriers have three basic choices to pursue. They can light more fiber, add more wavelengths to existing fibers, or increase the transmission rates on existing fibers. All have positives and negatives. Lighting up fiber can involve installing additional fiber and/ or installing new hardware, a very expensive proposition. Transmitting more wavelengths over a fiber may require

narrower channel spacing, which involves more sophisticated modulation schemes and the costly upgrade transmission equipment. In addition, the existing fiber chromatic and polarization mode dispersion characteristics may set limitations to improved channel spacing performance. Finally, the increase in transmission rates involves more sophisticated modulation and forward error correction schemes to address existing fiber dispersion characteristics. New analog-to-digital converter technology and optic modules are under development to enable this level of sophistication. All three options have drawbacks. However, the path of higher transmission rates offers the greatest advantages in terms of system performance and cost-effective migration paths. By transitioning from 10 Gbit to 40/100 Gbit transmission rates with the integra-


technology connected

tion of enhanced modulation schemes such as Dual Pole – Quadrature Phase Shifting Keying (DP-QPSK), carriers can preserve much of their existing fiber infrastructure, and base transport platforms and repeater equipment. By employing new modulation techniques like DP-QPSK, carriers anticipate transmitting up to 80 channels of 100 Gbit bandwidth over a single fiber, at 50 GHz spacing. Equipment providers are already in production with 40 Gbit networks, and some are in field trials with 100 Gbit. The ability to efficiently map and multiplex existing 10 Gbit traffic into these larger pipes is also underway. The ITU Study Group 15 has standardized on OTU-4 mapping/framing/clocking schemes, and the Optical Internetworking Forum (OIF) has also standardized on modulation technique DP-QPSK to most efficiently enable the framing, mapping, multiplexing and transmission of 10 Gbit signals into 40 Gbit and 100 Gbit pipes. A key factor in the transition is highly integrated wide area network SoCs that can provide 4x10 Gbit to 40 Gbit, and 10x10 Gbit to 100 Gbit mapping and multiplex (muxponder) solutions. Among a rich suite of features and integration, these devices should offer support for a generic mapping protocol (GMP) that enables “AnyRate” 10 Gbit client signals to be mapped into 10 Gbit ODTU-23/24 frames, and output them at a common clock rate to allow for easy multiplexing of 10x10 Gbit signals into a 100 Gbit OTU-4 frame.

tions to transport equipment providers and carriers. The devices are designed for a variety of blade applications including 10 Gbit client/line cards, 10 Gbit transponders/muxponder cards, 10 Gbit regenerator cards and even 40 Gbit/100 Gbit muxponder applications. In addition, the serial 10 Gbit interfaces on the devices support pro-

grammable pre-emphasis and electronic dispersion compensation (EDC) to interface with both XFP and SFP+ optical modules. With integrated ITU G.709 FEC and Enhanced FEC (ITU G.975.1.I4), the SoCs enable  metro and long-haul transmission of 10GbE over OTN networks in low optical signal noise ratio

Highly Integrated Framer/ Mapper PHY

To meet the challenge, silicon designers are integrating framing, mapping and physical layer onto devices for LAN/WAN/OTN solutions to meet multiple interface, low-cost and low-power requirements of multi-service transport, dense wave division multiplexing (DWDM) and metro/core switch router applications. These integrated SoCs offer the most flexible and cost-effective soluUntitled-5 1

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technology connected

p-ODTU 24 clock (used to send p-ODTU 24 to the OTU 4 device)

100G Muxponder Client Interface XFI

XFP/SFP+ XFP/SFP+ XFP/SFP+

5x Yahara 10G Client Mapper OTU 2 FEC

XFP/SFP+

OTU2 (e,f) (xFEC) 10GE LAN/WAN 10G FC 8G FC OC 192/STM 64

OTU4 clock

/10

Line Interface

Line Interface XFI

10x pseudo-ODU2h (ODTU24)

XFP/SFP+

OTU 4 FEC Encoder/ Decoder

112G Transponder 10 -Lanes of SFI-S or MLD (synchronous)

XFP/SFP+ XFP/SFP+ XFP/SFP+

5x Yahara 10G Client Mapper OTU 2 FEC

10-lanes of Synchronous XFI

OTU4

XFP/SFP+ XFP/SFP+ Demap PLL x10

p-ODTU 24 clock (used to send p-ODTU 24 back to 10G Demanppers)

OTU 4 to ODU2 Pll x 10 NOT REQUIRED Due to Yahara

10G Client Mapper: Bit-transparent (Async + Sync) w/ clientmonitoring GFP-F for 10GE GFP -T for 8G FC, 10G FC (via Transcoding) OTU2 x FEC termination ODTU 24 mapping and pseudo - ODU 2h Framer Figure 2 A highly integrated 10 Gbit Framer/Mapper/PHY SoC, seen here as the AppliedMicro Yahara, in a 10x10 Gbit to 100 Gbit muxponder board level application, helps carriers enable higher 10G Ethernet transmission speeds at lower cost and reduced power consumption.

(OSNR) environments.  Additionally, the GFEC and Enhanced FEC also compensate for nonlinear inter-channel impairments, which allows for a  narrow channel spacing of 25 GHz for DWDM systems. A series of devices that integrates 10GbE/10GFC/8Gbit Fibre Channel/ OC-192/STM-64 to OTU-2 mapping services, FracN clock synthesizing circuitry, electronic dispersion compensation (EDC), GFEC/Enhanced FEC features and 10 Gbit PHY integration, enables Telecom OEMs to reduce the cost, power and space of their current 10 Gbit LAN/WAN to OTU-2 solutions by up

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MAY 2010 RTC MAGAZINE

to 50 percent by eliminating external PHYs and interface bridge devices. Interface flexibility with specialized devices is a key attribute for 10G OTU-2 client/line tributary metro Ethernet and switch/router applications. A flexible system interface supports XAUI/SFI4.P2/SFI-5s protocols and enables the direct connection to network processors, 10Gbit Ethernet switches, 10 Gbit Framers and 10 Gbit MACs, and its 10 Gbit Line XFI Interface enables the direct connection to XFP and SFP+ optic modules. Designing an SoC with a robust set of interfaces makes it flexible and

suitable for multi-service transport and DWDM platforms. These devices need to support a system interface (XAUI/ SFI4/P2/SFI-5s) and a dedicated 10 Gbit XFI Line interface. In addition, it should also be designed to support a separate and dedicated 10 Gbit XFI Client interface as well as a 16-bit parallel SFI4.P1 interface that can be used either on the client or line side of the device. The SoC configured this way can be used for 10 Gbit OTU-2 client/line tributary cards, transponder and regenerator applications and support 10 Gbit XFP/SFP+ and 10 Gbit MSA modules. In addition, a rich set of interfaces allows for customer-specific


technology connected

side door functions, such as encryption, to be supported as well as other unique mapping and enhanced FEC modes. For 10 Gbit transponder applications, serial 10 Gbit backplane applications, and 10x10 Gbit to 100 Gbit muxponder applications, a chip should have two serial 10 Gbit interfaces that are XFP/ SFP+ module compliant. Designers in this space should aim to provide a variant of the framer/mapper/PHY SoC to be equipped for the optical networking industryâ&#x20AC;&#x2122;s continued and inexorable migration to smaller form factor serial 10 Gbit optic modules and 10 Gbit serial backplanes. To help reduce cost and complexity, silicon companies are tasked with providing OEMs with a clean, thermally efficient and easily routable interface to both the Client side XFP/SFP+ optic module and to the 100 Gbit encoder/ decoder/framer device. GMP Mapping and XFI interfaces on the chip-to-chip interface allow for a direct connection to OTU-4 Framer implementations. Also, the 10 Gbit GMP mapping mode integrated into these devices produces a common clock rate, and greatly simplifies the complexity of the OTU-4 framer function. Future incarnations of framer/ mapper/PHY SoCs with further levels of 10 Gbit port integration, and single silicon solutions for 100 Gbit (OTU4)/FEC functions, will help to provide a downward slope for cost, power and space requirements, enabling 100 Gbit to become ubiquitous in the transport networks (Figure 2). A family of SoCs with differentiated feature sets enables system OEMs to select the most appropriate set of optical interfaces for their specific applications. As a result, these device families provide system OEMs with a cost/space/power advantage over other multiport, all-encompassing single-chip solutions. With system OEMs developing metro and long-haul transport solutions utilizing interface-rich WAN SoC devices, they provide carriers and Internet service providers with highly integrated and

cost-effective 10 Gbit, 40 Gbit and even 100 Gbit OTN/WAN/LAN system solutions. A flexible architecture and a small footprint provided by high-volume silicon-tested 10 Gbit intellectual property, provides the most robust and effective 10 Gbit transmission solutions over opticalbased metro and long-haul networks.

Untitled-4 1

AppliedMicro Sunnyvale, CA. (408) 542-8600. [www.appliedmicro.com].

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ploration your goal k directly age, the source. ology, d products

technology in

systems

Facing the Challenges of Touch Screen Design Touch screen user interfaces are become increasingly popular in a wide variety of embedded applications. The big challenge is to design them to be robust and reliable under a wide range of environmental conditions.

by Arild Rødland, Atmel

C

Vdd apacitive touch has become a hot technology for various markets ranging from consumer and white goods to industrial and medical markets. As designers experiment with capacitive MCU touch solutions, they face a number of Ct challenges. When a designer works on a EARTH touch application in a well controlled lab environment, many touch designs work flawlessly. the real test comes nies providing solutions However, now Cs when placing and thecompanies. product Whether into a your harsh ion into products, technologies goalenis to research the latest vironment with changing humidity ation Engineer, or jump to a company's technical page, the goal ofand Get Connected is to put you EART H you require for whatever type In of technology, temperature. order for a design to conand productstinue you areworking searching for. in such environments, the importance of selecting a robust hardware and software implementation cannot be GND stressed enough. To get the needed robustness, the solution has to automatically Figure 1 recalibrate based on the environmental A finger will add an additional load Ct effectively increasing the sensor changes. Unfortunately, many solutions do capacitance. not offer this automatic calibration. This could be due to a small available program to make a self-calibrating system robust to chanical wear as traditional buttons. This memory or software designers who lack environmental changes. effectively eliminates performance degexperience about what needs to be added radation over time. The touch sensor is Capacitive Touch placed behind a smooth touch surface, Get Connected Unlike mechanical buttons, capaci- making up a sealed system. This makes with companies mentioned in this article. tive buttons have no moving parts, and the product robust against humidity, and www.rtcmagazine.com/getconnected as such are not subject to the same me- the smooth surface makes it much easier

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MAY 2010 RTC MAGAZINE Get Connected with companies mentioned in this article.


tech in systems

Adhesive

Front Panel

PCB

Drive Electrode (X)

Receive Electrode (Y)

Figure 2 If air bubbles are trapped in the adhesive between the sensor and the front panel, this changes the total dielectric constant. This results in reduced performance.

to keep clean. This may be of particular interest in medical appliances where it is important to keep all surfaces clean and germ free. Capacitive touch sensing relies on the fact that your finger adds a measurable capacitive change in the touch sensor (Figure 1). This change or ΔC in capacitance can then be measured. There are many ways of doing this. Some methods rely on measuring the time it takes to charge the touch sensor to a predetermined level, others look at the “frequency” change that occurs in an RC system using a known value Resistor (R) (e.g. the internal pull) and a variable “C”—the touch sensor. Many more methods exist that can also measure this capacitive change. Most methods rely in some way on the time constant change (τ=RC) occurring when adding additional capacitive loading to the touch sensor. Generally speaking all methods are capable of detecting a change in sensor capacitance. What separates them is usually referred to as “quality of touch.” This term covers a collection of measurable parameters that determine how robust and reliable the solution is in everyday use.

The challenge does not lie in making a prototype that works on your own desk Some of these factors are signal-to-noise performance, noise immunity, and also how well the application tolerates changes in temperature, humidity and voltage.

The Challenge

The challenge does not lie in making a prototype that works on your own desk. Even if your prototype seems to be working reliably, this does not guarantee good performance when you take the product outside. Weaknesses easily overlooked in a well regulated environment soon become apparent once subjected to harsh or changing environmental conditions. As electronic components tend to change value and characteristics over temperature and voltage, a touch system must therefore be regarded and treated as a dynamic system. To ensure maximum performance, the touch measuring and signal processing need to adjust to

changes in operating conditions and calibrate to fit the new conditions. This allows the application to always operate at the optimal measuring point for the sensor. So how does humidity factor into this? As mentioned, capacitive measurements are based on the fact that touching the sensor, or actually the overlaying dielectric panel on top of the sensor, adds capacitive load to the system. Ambient humidity also adds capacitive load to the system. The fact that humidity affects performance may be less obvious, but remember that the human body contains about 60% water, so taken to an extreme you might say we add “water” to the sensor when we touch it. If the humidity in the ambient air changes, this changes the capacitive load on the sensor. In real life this may cause a serious design challenge, and if ignored, you run the risk of RTC MAGAZINE MAY 2010

35


Tech In Systems

Reference

Un-touched State

Detect Threshold

Touched State

Figure 3 The untouched, touched and reference values of the capacitive sensor. The delta between these values will determine if the button is in a detect or touched state.

designing a product that fails under humid conditions. Materials have different dielectric properties. For example, if you look at the dielectric properties of glass and vacuum, you will observe that glass has better dielectric properties, which makes it a better material to use as an overlay for a capacitive touch sensor. So how does this affect the choice and build of your front panel? Real products have the capacitive sensor placed behind a front panel made of glass, plastic or another good dielectric material. Glue connects the PCB to the front panel. Typical manufacturing processes may have difficulty guaranteeing that no air bubbles exist in the adhesive layer between the sensor board and the panel. Any air bubbles cause a variance in the dielectric creating an uneven capacitive response (Figure 2). So the touch sensing system needs to be able to compensate for this to give the user a consistent response for all buttons regardless of any air bubbles added by the manufacturing process.

Unparalleled Control A&D Technologyâ&#x20AC;&#x2122;s ADX family of high-speed simulation and control platforms. Procyon (AD5445): Multi-core, multi-processor system with ultra-low latency I/O for real-time simulation and HiL applications Compact ADX (AD7011): Low-cost, high-value turnkey solution for embedded system development ADX (AD5435): General purpose platform with modular I/O and integrated touchscreen, customizable for a wide variety of applications

www.aanddtech.com

Untitled-1 1

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5/17/10 3:19:51 PM


tech in systems

The Solution

All of the above challenges can be compensated for in a properly designed system. It doesn’t even have to be difficult with a touch solution that has this kind of functionality built in. The secret is how to make a touch solution production proof. In Figure 3 we see a typical touch sensor, and the raw sensor value measured when in a touched and untouched state. Figure 3 shows three important values. The untouched state, often referred to as the “raw data,” shows the numerical representation of the touch sensor’s capacitive value. This signal increases or decreases depending on the capacitive load on the sensor. The reference holds the long-term average value measured on the sensor and as such it holds the answer to what the average value for an untouched button should be. The delta shows the difference between this reference and the actual measured signal value at any time. If the delta is big enough, i.e., larger than a predetermined threshold value,

Channel recalibrated

Recalibration threshold

Figure 4 In the event that a sensor has been calibrated with additional capacitive load, the software should detect a sudden drop in load, and automatically recalibrate if the signal value exceeds a determined recalibration threshold.

The New Standard in Low-Power Networking Engines The CSB1725, based on the Marvell MV78200 Dual Sheeva Core SoC, is a highly integrated System On a Module (SOM). The CSB1725 provides an ultra small, powerful, flexible engine for low-power 10/100/1000 Ethernet based networking systems. The main features include: 1GHz Dual Superscalar ARMv5TE Cores w/512KB L2 Cache 512MByte 64-Bit Wide DDR2-667 Memory with 8-Bit ECC 64MByte NOR with Secure ID, and 512MByte SLC NAND Two PCIe x4 Port (or one x4 and four x1's) Two 10/100/1000 ports via 88E1121R RGMII to Copper PHY Two SATA Gen 2 (1.5Gbit or 3.0Gbit/sec) Channels Two 480Mbit USB 2.0 Host Ports <6W Typical, 10W Maximum, Both Cores Enabled 70mm x 75mm x 5.2mm (on 4.3mm Low Profile MXM Socket) Uboot and Linux 2.6.x BSP

COMING SOON - Freescale P2020 Dual Core The CSB1725 is manufactured in our in-house state of the art, lead-free surface mount manufacturing line. All products carry a 1-year warranty and are offered in commercial and industrial temperature versions. Cogent also offers standard and custom carrier boards, plus royalty free licensing options for the CSB1725.

COGENT "ALWAYS COMPLETE" Untitled-9 1

Cogent Computer Systems, Inc. 17 Industrial Drive, Smithfield RI 02917 tel: 401-349-3999, fax: 401-349-3998, web: www.cogcomp.com 5/13/10 4:32:36 PM

RTC MAGAZINE MAY 2010

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Tech In Systems

we say that the button is in detect or touched state. The key challenge to designing a robust touch system is to add sufficient logic to be able to analyze the signal, reference and delta, and to determine if it is a true or a false touch once the button goes into detect. A false touch can be caused by noise or changing environmental conditions. The way to

determine this is to continuously monitor the measured signal values and then update the references if the ambient condition starts affecting the average sensor signal values. It is critical to have this kind of runtime calibration. If left uncalibrated, you run a significant risk that your system will start drifting toward or away from the threshold, making the system

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too sensitive or totally unresponsive. The software needs to adapt to longterm changes and at the same time determine if a fast change is noise or an actual touch. In the Atmel QTouch Library, for example, this is solved by passing a time stamp to the measure function when called. The library tracks all measured values for all sensors and automatically makes necessary changes to the individual reference values. Note that changes measured on one sensor should not be regarded as being valid for any other sensor as they may be subject to different environmental conditions, and may also have a different size or shape. The software needs to track each sensor individually. In the QTouch Library, the “measure sensor” function uses a millisecond resolution time stamp that tells the library how long it has been since the previous measurement. This is the only input the library needs to be able to properly compensate for all environmental changes. When you first power up the touch application the system runs through an initialization routine to establish reference values for all sensors. An error condition occurs if the user touches the sensor during initial calibration. This causes the software to calibrate for a higher capacitive load than really exists on that sensor. If this happens, this sensor goes deaf, as the detect threshold is already set below what is reachable by touching the sensor (Figure 4). For this reason, the application should be able to identify this error condition and quickly do a recalibration if it detects that the raw signal makes a big positive jump compared to the reference value. This recalibration can safely be done as this kind of positive step only occurs due to excess capacitive load being removed from the sensor. It is important to be aware of these challenges and make sure that your software compensates to make sure you have a robust touch system. Atmel San Jose, CA. (408) 441-0311. [www.atmel.com]


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PMC

XMC

Size

HXWXL 16.5mm X 74mm X 149mm

Capability

SLC: 32 GB ~ 256 GB MLC: 64 GB ~512 GB

Transfer Protocol

PCI 32 bit 33/66 MHz

Bandwidth

132 MB/s \ 264 MB/s

Sustained write speed 1

250 MB/s 100 MB/s

Sustained read speed 2 OS

PCIe1 X Gen1

100 MB/s Windows 2000 \ Windows XP \ Linux \ Vxworks \ KYLIN

Power Consumption 3

6.5 W

Operation Temperature

Industrial (﹣20˚~﹢70˚) Extended Temperature Grade (﹣40˚~﹢85˚)

Weight 4

<100g

Security Characteristic

Destruction Rate 5 GB/s

RAID

RAID0`RAID1

Reliability

MTBF >1,000,000 hours MIL﹣STD﹣810F \ GJB150 \ GJB322A﹣98

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sales @runcore.com


exploration r your goal eak directly page, the resource. hnology, nd products

technology deployed Green Engineering

Fiber Optics Is the Path to Reliability in Wind Turbine Generators and Wind Farms Major benefits, including insulation, long data transmission length, easy installation and maintenance, make fiber optics components the better choice compared to copper data links.

by Mickaël Marie, Avago Technologies

E

lectricity generation by wind turbine generators, or WTGs, is a proven green energy technology in both land and offpanies providing solutions now shore environments. However, wind farms located either ation into products, technologies and companies. Whether goal isand to research the latestaccesonshore or offshore are often in your remote not easily cation Engineer, or jump to a company's technical page, the goal of Get Connected is to putcan you sible locations. Additionally, their height above ground ce you require for whatever type of technology, pose unique maintenance, repair and lightning strike chales and products you are searching for. lenges that must be addressed to make wind power renewable energy reliable and economical. Fiber optics (FO) technology is probably best known for use in high-speed, high-bandwidth telecommunication applications. But today fiber optics data and control links have replaced copper links in wind turbines and farms making them a critical part of a wind farm operator’s solutions for minimizing costly downtime and service interruption. Fiber optic technology is the most suitable—and in some cases the only acceptable—technology in high electrical noise environments for electrical generator/turbine control, power conversion and wind farm wide-area communications. The Get Connected characteristics and reliability benefits of FO components— with companies mentioned in this article. receivers,www.rtcmagazine.com/getconnected transmitters, transceivers and cable—are applicable in wind farms and wind turbines, as well as overall wind farm and wind park operation.

End of Article

Get Connected with companies mentioned in this article. www.rtcmagazine.com/getconnected

40

MAY 2010 RTC MAGAZINE

A

Electrical Signal

Copper Jack

Wind Turbine Environment

Unlike conventional electricity generating facilities that use coal or natural gas as their energy source, wind turbines operate outdoors and in regions with temperature extremes, corrosive spray (e.g., salt), dust, lightning strikes, snow and rain. In offshore wind park installations, weather may prevent maintenance and repair for extended time periods. Offshore wind turbines are usually larger than onshore installations and also generate more power because wind speeds are generally stronger and steadier, which means the WTGs must be more powerful. Higher wind speeds, larger mechanical loads, and corrosive elements in sea-based wind parks mean even higher reliability is needed. Because wind turbines operate in rugged environments, both from a physical and electrical perspective, high levels of noise and electromagnetic interference (EMI) are generated inside the wind turbine nacelle from motors, solenoids, power

Electrical Signal

Copper

Electrical Signal

Fiber Optic

Optical Signal

Copper Jack

B

Electrical Signal

IC

A

Optical Electrical Signal Transmitter Signal

Receiver

B

Electrical Signal

Figure 1 Fiber optic data communication link with inherent voltage isolation.

lines, inverters and generators. Lightning strikes are prevalent in wind farm installations, and fiber’s inherent galvanic isolation adds to system reliability. The wind turbine itself is a complex assembly of mechanical components, including a tower, gearboxes, brake systems and blades. It also consists of electronic and other components such as motors, frequency inverters, rectifiers, isolated gate bipolar transistors (IGBTs), power converters, programmable logic controllers (PLCs), sensors, pitch and yaw systems—and all must be interconnected to generate reliable power. Inside


technology deployed

the turbine’s nacelle are the power generation electronics, generators, blade pitch control, system controllers, motor, Ethernet/Profinet protocol devices, frequency inverters, circuit breakers and more. Fiber optic links are well suited for this short reach environment and are also the best choice for sending data and control signals from an individual wind turbine to the wind farm central monitoring station. They are also the optimal choice within the wind farm thanks to fiber’s advantages of high-bandwidth, galvanic isolation, long transmission distances, high noise immunity and near-perfect EMI immunity. In comparison, traditional copper data links cannot match the overall capability of a fiber optic based system when judged on reliability and operation in rugged environments. Likewise, doubled shielded CAT5/CAT6 copper cables make the solution more expensive than using fiber optics solutions. Figure 1 shows a basic fiber optical link where photons reflected in the core of the fiber cable replace electrons moving in copper cable in the transmission path. By eliminating the conductive copper cable, very high galvanic isolation levels can be achieved. The power-generation electronics, such as the IGBT/IGCT inverter power switches, are controlled over high-noise-immune, EMI-resistant fiber optic control paths (Figure 2). Fiber data links connect the nacelle’s remote controllers to the turbine’s main controller at the base of the platform and then to the wind park over a redundant fiber data and control communication link (Figure 3). A wind farm must rely on constant, reliable data flow for peak performance, reliability and safety even in installations covering large areas that are subject to local weather variations. Sensors monitor blade operation, system variables such as vibration, and outside environmental factors such as ice—all of which can im-

Generator

Rectifier AC-DC

DC Link

Fiber Optic Wind Turbine Blade

Inverter DC-AC

3 Phase Line Filter and Transformer

Versatile Link HFBR-0500Z series POF

Versatile Link HFBR-0500Z series

C Rg

G

IGBT

B

Gate Driver

IGBT’s Gate Driver Block Diagram Figure 2 Real-time, noise and EMI-resistant fiber optic communication technology is used for wind turbine power generation, control and communications subsystems.

pact power generation and system safety. The data from system sensors can also be fed into the SCADA systems for preventive maintenance action. Communication links must often run alongside power carrying conduits, and fiber cables are immune to crosstalk from power cables. As shown in Figure 3, fiber-based communication links inside the nacelle, between wind turbines and back to the wind farm control station, all benefit from using optical fiber.

Plastic Optical Fiber

Providing isolation and reliable communications make wind farm management and operation safer and more efficient. Many different fiber cable types (POF, HCS, Multimode, Singlemode) can be used in WTGs, with plastic being the least expensive. Costeffective plastic optical fiber (POF) and glass optical fiber solutions

Data Acquisition System Controller

Fiber Optic

Control Board and Communication

Driver Logic and Protection Functions Driver

Control Board

Control Center

Utility Grade AC Power

Computer System

Server Fiber Optic Switch

Turbine Control Unit (TCU) Network Switch

Figure 3 Fiber optics are used in the turbine nacelle and wind park for real time control.

RTCRTC MAGAZINE MAGAZINEMONTH MAY 2010

41


technology deployed

Data Rate

Link Distance

DC - 1MBd

45m (POF)

DC - 5MBd

20m (POF)

DC - 10MBd

40m (POF) 200m (HCS)

20MBd

2700m (MM)

125MBd

50m (POF) 100m (HCS)

125MBd

2000m (MM)

TABLE 1 Fiber optic component selection for data rate/link distance.

are used worldwide in existing wind farm installations. Higher reliability and easier maintenance all play a role in the economics of wind power; getting a turbine online quickly and having it running reliably without interruption are critical concerns. Fiber communication links consist of short-link POF, e.g. 60 meters, in individual turbines or multimode cables coupled

to discrete transmitters/receivers or transceivers. Fiber cables are lightweight and both robust and resistant to harsh environments. One advantage of the POF is also its flexibility. For the handling of POF cables, 25 mm is the minimum bend radius (measured to the inside curvature), at which the cable can be bent safely without any damages during installation or even shortening the cable’s life. Under minimum tension, the minimum long-term bend radius is 35 mm. These are necessary characteristics for vertical cabling in towers that can be over 200 meters tall and where several hurdles in different parts of the WTG are to be bypassed. Fiber optics termination also offers safe and robust connections, either with POF, HCS or MM. It is very important to make sure that no cable will be pulled out of any equipment by mistake when technicians operate on any components of the turbine. For industrial and renewable applications, optical fiber solutions with solid connectors are preferred. In effect, a good retention is required in numerous applications as vibrations may inhibit an optimized coupling of the light to either the sourcecable or cable-receiver interfaces. A commonly used solution is a versatile link transmitter/receiver family. With this solution, a connection is made by inserting the connector into the transmitter and receiver ports. Both the transmitter and receiver have a slot on the top of the housing that enables the use of a latching system. This system allows a retention force of typically 80 newtons (80N), or approximately ten times more than a connector with no latching system.

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MAY 2010 RTC MAGAZINE

Recipient of the VDC Platinum Vendor Award for five years running!


Technology deployed

For industrial applications with very high operating temperatures, latching connectors are the preferred solution since the connector retention decreases with the temperature. The storage and operating temperature ranges for the plastic connectors are from -40째 to +85째C. Moreover, the retention force remains unchanged even after 2000 insertions of the connector into the transmitter or receiver. The force required to insert the connector varies from 30 to 51N maximum based on the type of plastic connector used. Destruction occurs typically from 178N. The connector-cable tensile force is approximately 50N for a solution without a ring and from 22 to 35N using a crimping ring. A crimpless connector is less expensive not only because it avoids the purchase of tools and reduces the time spent on the termination, but it also reduces the yield loss due to installation errors. The connectors, like the POF cable, can be simplex or duplex. The duplex connectors are keyed to prevent any bad connection to a system of duplex modules. A duplex configuration is easily achieved by snapping together two non-latching simplex connectors: the upper part of one of the simplex is inserted into the ferrule of the second. In this way, the POF are definitively connected to the connector and cannot move. From a practical point of view, the connectors used can be color coded in order to facilitate the task of technicians insofar as they can more easily identify the cable to be connected to a transmitter or a receiver. Fiber optic components can be selected to match the link length and data rates needed for each specific environment. Low-

rate, short-span applications can be served by 650 nm LED-based components where up to 1 MBaud data rates, a span out to 45 meters and cost-effective plastic fiber cable are suitable. The LEDbased components have a reach of 2,700 meters over multimode fiber (MM) and a 20 MBaud data rate, but can also operate up to 160 MBaud over 500 meters. Other rates and reaches are served by components such as those shown in Table 1. Many types of equipment in WTGs use Ethernet communications, including the control system, Ethernet-based circuit breakers and the switches used for the networking of the farm. Each control system of each individual wind turbine will be connected to a Local Area Network (LAN) operating with Ethernet that is also connected to a remote control center for monitoring purposes. Using fiber optics solutions for communication will make the wind farm even more reliable, especially in the harsh, offshore farm environment. A digital monitoring interface (DMI) and an industrial 10/100 Ethernet POF and HCS transceiver with DMI can be used. The DMI allows a full real-time monitoring of the FO link through a two-wire serial interface. In addition to the monitoring of the LED drive current and photodiode current, the interface also monitors the transmitter supply voltage and temperature. Avago Technologies San Jose, CA. (408) 435-7400. [www.avagotech.com].

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www.tripleease.com salestriplee@xtech-outside.com 1-888-444-1644 Untitled-4 1

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exploration r your goal eak directly page, the resource. hnology, nd products

technology deployed Green Engineering

Energy Harvesting and Power Balance in Wireless Sensor Networks Gathering the energy needed for operation locally rather than relying on line power or batteries, can enable the use of wireless sensor networks in more locations and reduce the cost of maintenance in such locations as older buildings where wired installations would be prohibitive. by Martin R. Johnson, Illumra and Eugene You, EnOcean

W

ireless, energy-harvesting technologies are making waves in terms of sustaining building automation panies providing solutions now and energy conservation controls. By becoming ation into products, technologies and companies. Whether your goal is to research the latest versed wireless strategies, cation Engineer, or jumpinto energy-harvesting a company's technical page,and the goal of Get Connected is toOEMs put you can quickly energy management devices (sensors, ce you require for whatever typedevelop of technology, es and products you are searching for. switches, controllers, relays, gateways) that overcome the confines of hardwired solutions and the maintenance issues inherent to battery-dependent devices. Customizable, application-specific functions (primarily for lighting and HVAC) are embedded inside radio and energy-harvesting modules. This article will discuss the science behind the wireless, energy-harvesting technology, then delve into how to budget miniscule amounts of energy sufficient for managing building energy usage. Buildings account for 40 percent of all energy (electricity and fossil fuel) consumption in the United States, and according to the AIA, approximately 50 percent of all GHG (greenhouse gas) emissions. Climate conditioning (HVAC) and lighting acGet Connected companies mentionedconsumed in this article.by buildings. A lot of that count for with most of the energy www.rtcmagazine.com/getconnected energy is routinely wasted. By automating control of lighting and HVAC energy management, OEMs can quickly develop solutions

that satisfy a historic market demand for energy-saving instruments. Older buildings are less likely to be energy efficient than current construction. Building Automation Systems (BASs) have been shown to be reliable in reducing energy consumption in buildings on average of 40%; however, most buildings in the U.S. do not integrate BASs. Upgrading energy-inefficient buildings with BASs has traditionally been hindered by many factors, primarily the following: â&#x20AC;˘ Existing buildings are expensive to retrofit (installation costs, slow payback) â&#x20AC;˘ Retrofitting existing buildings with BAS is invasive, often complicated and potentially risky (e.g., building closures, unknown variables behind walls/ceilings and exposure to asbestos)

Integrators are overcoming these traditional barriers by using battery-less, selfsustaining, wireless sensors and controls. The controls reduce the amount of energy unnecessarily wasted in our buildings and bypass many obstacles inherent in hardwired equivalents.

1 Wireless Standard 130+ Alliance Members 400+Products

End of Article

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MAY 2010 RTC MAGAZINE

100% INTEROPERABLE

Figure 1 The EnOcean Wireless Standard and Alliance.


technology deployed

Motion

Solar

Thermo

Figure 2 Radio and Energy Harvesting Modulesâ&#x20AC;&#x201D;Radio modules powered by ambient sources of energy.

Energy Harvesting & Wireless

At the center of energy harvesting and wireless is the EnOcean wireless standard. EnOcean, a spin-off of Siemens AG, invented energy-harvesting wireless sensor networks. Today, the technology has evolved and 130 member companies of the EnOcean Alliance now subscribe to the open wireless standard. The Alliance is a consortium of companies advocating the use of self-powered wireless monitoring and control systems that serve as catalysts to sustainable building energy management (Figure 1). Energy-harvesting technology stems from a simple observation. Where measurable sensor values reside, ambient energy exists sufficient to power sensor radio communications. For example, when a switch is pressed, temperature changes or luminance level varies, energy is produced. These rudimentary operations generate enough energy to transmit radio signals that are useful in terms of sustaining wireless communications between sensors, switches and controls within a building automation system. Instead of batteries, EnOcean-based controls use miniaturized energy converters and capacitors that supply power to building energy management devices. The bottomless power generation (or energy conversion, to be more precise) stems from various sources of ambient power: linear motion converters, solar cells and thermoelectric converters (Figure 2). Creating an energy-harvesting-powered device requires more than simply cutting the wire from the mains supply or replacing batteries with an energy-harvesting module. It requires a system engineering approach to make it work. Given a limited energy budget, every component in the system is critically important. A market-ready product is viable only when all aspects in the system are considered along with how they operate as a whole in the system. What does a complete solution entail? An energy-harvesting wireless sensor is comprised of building blocks, each of

which has been optimized specifically for energy harvesting and to work in harmony with each other. The balance between energy generation and energy consumption is a critical consideration in developing sustainable solutions. When factoring the amount of ambient energy available in buildings, continuous operation is only feasible when all of the building blocks are optimized for low power consumption. In order to power devices within the naturally enforced limits of energy availability, sensors must transmit infrequently, execute procedures within the shortest possible time, and be able to switch off all blocks when not required for operation (Figure 3). Different wireless energy-harvesting applications require varying amounts of energy for routine operations. For example, a magnetic contact window sensor requires less energy than an occupancy sensor. The magnetic window sensor senses and signals an isolated event while the occupancy sensor must sense continuously or at intervals and send data periodically. In addition, there may be sleep modes interspersed with periodic actions of sensing and transmitting data with corresponding different levels of energy consumption (Figure 4).

Harvester

Conversion & Storage

Microcontroller Transceiver

Management Store Threshold Sleep

Sensors

Temperature, Motion, Position... Figure 3 Energy Harvesting Building Blocks.

RTC MAGAZINE MAY 2010

45


technology deployed

Designing for Micro Energy Budget & Balance

Current

A burst of three redundant telegrams Transmission CUP + Sensor + A/D CUP + Sensor

Sleep current...IS

tm

Sleep 10ms

Short term sleep 20ms

Sleep 30ms

40ms

50ms

Time

60ms

Sensor current consumption typical pattern --Sleep, wake up, sample and Tx, sleep---

Volumetric Energy Density j/inË&#x2020;3

When moving forward with a wireless, energy-harvesting design, many variables come into play including the actual harvesting, the storage and budgeting of available energy. Careful consideration of the variables is vital to a successful design. With almost any energy-harvesting device, it is possible and probable that the source of ambient energy will not always be present. For instance, in the case of solar harvesting, light may not always available. Thus, a means of storing energy is necessary. The stored energy is used to bridge the gap during the time when the ambient energy supply fades away. There are various means of storing electrical energy: capacitors, primary (non-rechargeable) and secondary (rechargeable) batteries, supercapacitors, etc. Batteries are becoming increasingly unpopular because they must be transported, installed, replaced and properly disposed of and recycled. Because most battery chemistries contain toxic chemicals, all of these activities are unpopular, unsafe, expensive and/or environmentally unfriendly. Capacitors simply donâ&#x20AC;&#x2122;t store enough energy in a small space, so they

Volumetric Energy Density Battery

1000 1000

SuperCap

100 10

1

Capacitor

0.1

Figure 5 Volumetric Energy Density.

tude better than rechargeable batteries. They can also be charged/discharged very quickly. Their volumetric energy density is a couple of orders of magnitude less than typical primary lithium cells (Figure 5), but when combined with an energy harvester, such as a solar cell, they never have to be replaced. Another benefit is that they donâ&#x20AC;&#x2122;t contain toxic chemicals. Thus, they are quite useful in low-power wireless electronics. Special attention should be given to the selection and sizing of a supercapacitor for a given application. The performance of supercapacitors is affected by time, temperature, voltage and charge cycling. The designer should not select a capacitor whose initial capacitance and equivalent series resistance (ESR) just barely meet the requirements of the application. The capacitance and ESR degrade as time progresses. For example, a supercapacitor charged to its

Figure 4 Typical Wireless Node Operation. Cell area

are not well suited to carry the burden when ambient energy is unavailable for harvesting. An increasingly popular energy storage reservoir for energy-harvesting applications is the supercapacitor or ultracapacitor. These electrochemical capacitors have the fortunate characteristic of relatively large volumetric energy density as compared to traditional ceramic, electrolytic or tantalum capacitors, as shown in Figure 5. They are routinely used in a wide variety of applications ranging from automobiles to cameras to wireless, battery-less sensors, particularly those based on the EnOcean wireless standard. Supercapacitors possess the desirable trait of tolerating many hundreds of thousands, even millions of chargedischarge cycles, which is two to three orders of magni-

46

MAY 2010 RTC MAGAZINE

5

Chart: approx constant output current 2cm2@400 1x = 4 cm2@ 200 1x

4 3 2 1

0

200

400

600

800

Figure 6 Approximate constant output current.

1000

(lux)


Technology deployed

maximum rated voltage and held at its maximum rated temperature can lose approximately 30% of its capacitance in as little as 1000 hours; its ESR can increase over 200%. Charge/discharge cycling also affects their capacitance. A supercapacitor can lose 15% of its capacitance during the first 100,000 cycles, and worsens if it is charged up to its maximum voltage each time. After 100,000 cycles the reduction in capacitance levels off to about 20% at 1 million cycles. Lowering the temperature by 10°C tends to reduce the degradation by a factor of two. Thus, the designer should determine the minimum voltage and energy requirements of the application and then derate the initial capacitance of the supercapacitor appropriately. Each manufacturer will provide more specific information to assist the designer in sizing a supercapacitor for any given application.

Solar and Thermal Energy Harvesting

One of the most common energy harvesters today is the solar cell. Solar radiation represents the largest energy resource of the terrestrial ecosystem. Unfortunately only about 0.1% of the sunlight level is available indoors. Technologically speaking, there are two major solar cell types. One type is typically used for outdoor applications while the other is used for indoor applications. Crystalline silicon solar cells, also called “outdoor,” reach their best efficiency under sunlight (peak sensitivity at 800 nm). Amorphous (non-crystalline) silicon cells, also called “indoor,” with peak sensitivity at 500 nm, are ideally suited for poor light and fluorescent light (FL) conditions. While conventional crystalline solar cells are about two times more efficient by optimum light conditions (outdoors), amorphous cells outperform them by far under poor indoor lighting conditions and win on the 24-hour energy cycle because they can also use poor artificial light and early morning or evening light. As a rough, conservative estimation, indoors and for small area amorphous

Embedded Computing for Energy Efficiency: More Than Just Vendor Marketing Hype by Richard Dean, Venture Development Corporation According to the 2010 Annual Energy Outlook, published yearly by the U.S. Energy Information Administration (EIA), total electricity consumption, including both purchases from electric power producers and on-site generation, will increase at an average annual rate of 1% through to 2035. Further, energy-related carbon dioxide emissions will also increase proportionally over the same period. As this statistical data obviously suggests, in real terms, domestic energy production and energy imports combined are rising to meet ever-increasing energy demand. However, on a per capita basis, energy consumption is actually predicted to gradually decline through 2035. Over the next 25 years, energy efficiency gains are actually predicted to reduce total consumption by 15% (on a per capita basis) from where it would otherwise be. What’s driving this decline? According to EIA administrator Dr. Richard Newell, “Structural changes in the economy, higher energy prices, emerging standards and improved efficiency,” are all playing a part in creating economic, political and environmental change. While this somewhat conflicting data may present observers with slightly contradictory storylines, there is no doubt that technology companies—including many embedded chip, board and systems vendors—are increasingly interested in designing, developing, integrating and shipping more efficient embedded technologies. And, many customers are now requesting more intelligent embedded computing technologies, which VDC believes takes this to a level beyond mere vendor marketing hype. Chip-maker, Intel, for instance, introduced earlier this year new “smart” processors for embedded applications that offer both improved performance and better power management. The Core processors that were adopted from the desktop line-up for embedded market segments include the 32nm dual-core Core i5-660 and Core i3-540, and the 45nm quad-core Core i7-860 and Core i5-750. In addition, the shift toward multicore is becoming ever more pronounced. “In the embedded space, Intel is seeing more and more migration to multicore, a trend that started in 2008 and continues unabated,” said Frank Schapfel, product line marketing manager, Intel Performance Products Division. IBM is extending its influence in the “green IT” movement beyond just new embedded boards and systems and into the broader theme of the smart, connected planet. Based on optimization of infrastructure through an integrated service management platform (ISM), the concept, officially announced at IBM’s 2010 Pulse event, is best illustrated as an interconnected network of devices and software that brings transparency, control and automation to enterprises and consumers. Going one level higher, IBM is now asking its supply chain of 28,000 partners, to begin tracking, reporting and reducing their environmental impact, according to published reports. Without setting specific targets, the company’s global suppliers are being asked to monitor their energy use, greenhouse gas emissions, waste and recycling with data management systems. Further, they are then asked to approach their own subcontractors in order to monitor their performance, as well. While VDC believes it may be premature to forecast with any real precision the direct economic impact “intelligent” embedded computing technology will have over the next decade, we will be closely evaluating these trends around specific vertical industry applications within our forthcoming published research. Venture Development Corporation Natick, MA. (508) 653-9000. [www.vdcresearch.com]. RTC MAGAZINE MAY 2010

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technology deployed

Wake cycle [s]

Transmit interval

Current required cont. operation (µA)

1 1

1 10

130.5 40.5

Peltier

1

100

31.3

Heat

10 10 10

1 10 100

13.5 4.4 3.5

100

1

1.6

100 100

10 100

0.8 0.6

TABLE 1 STM300C average current required for continuous operation for several wake/transmit schedules.

solar panels (a few cm 2), an operating current in the range 8.5 μA/cm 2 @ 200 lx (FL) can be considered. This value can be roughly linearly extrapolated using a derating factor for lower illumination and/or smaller area. That corresponds to 4 μA/ cm 2 @ 100 lx. A similar extrapolation approach is shown in Figure 6. For best performance, the solar panel output voltage should be near the required application operating voltage. The amount of output voltage mainly depends on the number of cells connected in series. Take care to ensure that the voltage delivered by the solar cell is above the minimum required by the system (at the lowest expected light level) and that it is below the maximum the system can tolerate (at the highest expected light level). These are rough estimates that depend on many variables. First, carefully check the specific environment, define worst-case application requirements and add an additional reserve of 20% by the solar panel dimensioning. Verify your assumptions by measuring the real solar panel values in the worst case. Generally consider 25 lx as a lower brightness limit for designing ambient light powered devices. Below this limit solar cell efficiency drops dramatically. Alternative to the use of a standard solar panel (e.g., in applications with no or not enough light), a radio module can also be powered by other external power sources such as a thermo-electric generator based on a standard Peltier element as shown in Figure 7. Table 1 summarizes the amount of current required by an STM300C radio module. With a

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MONTH MAY 2010 2010RTCRTC MAGAZINE MAGAZINE

c˚ 1000µF ECT 300 DC/DC

VDDLIM VDD GND

STM 300 (c)

Figure 7 Block Diagram of radio module powered by Peltier thermal energy harvester.

wake cycle of 100 seconds, and transmitting each time it wakes, the long-term current required for continuous operation is 1.6 uA. With a 2.6V supply voltage, this works out to be about 4.4 uW of continuous energy. This amount of energy can be delivered by an ECT300 EnOcean module with as little as 2 kelvin temperature differential. A capacitor provides a reservoir for harvested energy storage and provides the short-term burst current required by the radio module. By harvesting ambient energy sources and coupling that with energy-optimized wireless technologies, it is possible to realize a wide variety of wireless lighting and HVAC sensors and controls. These devices can be easily installed in almost any building, with minimal invasiveness, to help conserve energy and save costs. ILLUMRA Orem, UT. (801) 349-1200. [www.illumra.com]. EnOcean Salt Lake City, UT. (801) 943-3215. [www.enocean.com].


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products &

TECHNOLOGY ATCA Blade with Dual 6-Core/12-Thread Xeon L5638

An AdvancedTCA (ATCA) processor blade features dual next-generation 32nm sixcore Intel Xeon processors L5638 with 2.00 GHz core speed, the Intel 5520 chipset, up to 48 Gbyte of DDR3 memory, and an optional PICMG Mid-size AMC bay for increased computing performance and flexibility. The Intel Xeon L5638 on 32nm process technology with 6-core / 12-thread capability gives the aTCA-6150 from Adlink increased processing performance with more efficient power consumption. On-card connectivity includes dual GbE or 10GbE Fabric Interfaces, dual GbE Base Interfaces, dual front panel GbE interfaces and quad SAS channels, which provide leading-edge network performance and storage capabilities. High-speed data transfer on the PICMG 3.1 fabric interface is provided by an Intel 82599EB 10 Gigabit Ethernet controller with PCI Express v2.0, and base interface connectivity is delivered through the Intel 82576EB Gigabit Ethernet controller, also supporting PCI Express 2.0. The aTCA-6150 implements two Intel Xeon processor L5638 (6-core) or two Intel Xeon processor L5618 (4-core) with integrated memory controllers supporting six sockets for DDR3-1066 VLP RDIMM memory up to a maximum of 48 Gbytes. Also supporting Intel Hyper-Threading Technology and Intel Turbo Boost Technology, the Intel Xeon processor 5600 series increases the performance of both multi-threaded and single-threaded workloads, as well as improving energy efficiency. The Intel Xeon processor 5600 series features Intel Trusted Execution Technology (TXT) for safer computing and hardware/firmware security with a higher level of trust and control over computer systems. Also featured are the Intel AES New Instructions (Intel AES-NI) that accelerate data encryption and decryption. These advanced practical security features are especially suited to datacom and telecom applications. ADLINK, San Jose, CA. (408) 966-5200. [www.adlinktech.com].

Type II Compact COM Express Module with Single/Dual Core CPUs and NAND Flash

Along with a companion PCOM-C210 developer carrier board, a new compact (95 mm x 95 mm) Type II Compact COM Express Module is targeted for low power systems and handheld mobile devices in applications such as medical healthcare, industrial control, gaming, portable devices and COTS military market. Based on Intel Atom processor N450 (single core), D410 (single core) and D510 (dual core), the PCOMB215VG from American Portwell Technology features Intel 82801HM I/O controller, up to 4 Gbyte DDR2 SDRAM, onboard 4 Gbyte NAND Flash upgradable to 8 Gbyte, one Gigabit Ethernet, dual independent display via VGA and LVDS, eight USB ports, wide input voltage support (8V to 18V) and support for EIDE and SATA. Expansion capability includes five PCI-E x1 lanes that can be configured as one PCI-E x4 and four PCI-E x1, four PCI, LPC interface and a high definition audio interface. American Portwell, Fremont, CA. (877) 278-8899. [www.portwell.com].

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MONTH MAY 2010 2010RTCRTC MAGAZINE MAGAZINE

FMC ADC Card Delivers 550 MS/s Output A high-performance FPGA ADC Mezzanine Card (FMC/VITA 57) module features two enhanced Texas Instruments ADC devices. The ADC510 from Curtiss-Wright Controls Embedded Computing delivers sampling performance of 550 MS/s with analog bandwidths >1.7 GHz and 12 bits of digital output. Available in both air-cooled and conduction-cooled rugged versions, the ADC510 is aimed at DSP applications such as signal intelligence (SIGINT), electronic counter measures (ECM) and radar, making it easier and faster for system developers to integrate FPGAs into their embedded system designs.

The ADC device interfaces are routed to the FMC connector to enable an FPGA on a baseboard to directly control and receive data. There is a choice of sample clock sources for the ADC510 including an onboard source that supports sampling rates of 300, 320, 400 and 500 MSPS as well as the ability to utilize an external sample clock. Input and output triggers are provided to enable multiple ADC510 modules to be synchronized to increase the number of input channels. HDL example code is available for the ADC510 for integration into the HDL development suite for Curtiss-Wright Controlsâ&#x20AC;&#x2122; FPGA baseboards. The ADC510 is provided with HDL example code to simplify and speed integration into the HDL development suite for integration with Curtiss-Wright Controlsâ&#x20AC;&#x2122; FPGA host boards. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (613) 254-5112. [www.cwcembedded.com].


PRODUCTS & TECHNOLOGY

OpenVPX Rugged SBC Features GPGPU Technology Taking CUDA beyond Graphics

A Rugged 6U OpenVPX Single Board Computer (SBC) features integrated general-purpose computing on a graphics processing unit (GPGPU) capability. The IPN250 from GE Intelligent Platforms features Nvidia’s CUDA technology. CUDA is becoming increasingly attractive to systems integrators since it has been demonstrated to be capable of enabling performance gains of up to 100x in a range of applications: its innovative technology and openness create the opportunity for improved productivity and sustainable competitive advantage. It is increasingly mandated by some Department of Defense (DoD) program offices because it offers increased flexibility and reduced cost of ownership when compared with previous FPGA-centric solutions. The IPN250 combines Nvidia’s latest GT240 96-core GPU with an Intel Core 2 Duo processor operating at 2.26 GHz and 8 Gbytes of DDR3 SDRAM to deliver up to 390 GFLOPS of performance per card slot, depending on the application. It is designed to be compliant with the OpenVPX standard, ensuring interoperability with a broad range of other OpenVPX boards. The IPN250 includes two primary data planes and 10 Gigabit Ethernet ports supporting multiboard switched fabric OpenVPX architectures. A 16-lane PCI Express Gen2 interface on the P2 expansion plane provides high-speed interconnect for multiboard GPGPU clusters as well as system I/O to PCI Express-enabled sensor modules such as GE’s family of Xilinx Virtex5 and Virtex6 mezzanine cards. Two 1000Base-T and two 1000Base-Bx control plane ports are available, together with additional PCI Express, USB 2.0, SATA, COM ports, GPIO , audio and TV input. Video and multimedia is supported via the dual link DVI, HDMI and VGA ports directly into the Nvidia GT240 device to cater for a wide range of interfaces. GE Intelligent Platforms’ AXISLib advanced multiprocessor software development VSIPL, DSP and math libraries for CUDA and Intel SSE4 facilitate application development and code portability for the IPN250 and future GPGPU platforms. In addition to Nvidia’s CUDA environment, supported software includes Linux, Windows, Microsoft DirectX, OpenCL, OpenGL and MATLAB, together with Nvidia’s PureVideo Technology and PhysX. GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [www.ge-ip.com/gpgpu].

Core i7-Based XMC Module with Encryption/ Decryption

Next-Generation Intel Atom Processor Featured in Fanless Box Computer

Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [www.xes-inc.com].

WIN Enterprises, North Andover, MA. (978) 688-2000. [www.win-ent.com].

A high-performance XMC module features the Intel Core i7 processor and SecureCOTS. With SecureCOTS capabilities, the XPedite7302 from Extreme Engineering solutions can provide data encryption and decryption and enable developers to address a program’s protection requirements. SecureCOTS includes functionality that developers can utilize to develop secure computing and anti-tamper capabilities for their customers. In addition to the SecureCOTS capabilities, the XPedite7302 features an Intel Core i7 processor operating at 2.00/1.06 GHz, 8 Gbyte DDR3-1066 ECC SDRAM in two channels and 8 Mbyte SPI NOR boot and 256 Mbyte parallel NOR flash. The board also supports one x4 PCI Express link and four x1 PCI Express links along with a Gigabit Ethernet port and two serial ports. Configurable as either aircooled or conduction-cooled, the XPedite7302 is designed to meet a wide range of environmental requirements. Wind River VxWorks and Linux Board Support Packages (BSPs) are available.

A fanless box computer for embedded applications supports the new generation of Intel Atom processors that includes the dual-core Intel Atom processor D510 and single-core Intel Atom processors N450 and D410. The PL-80190 from Win Enterprises can be used in a variety of embedded market segments such as print imaging, digital signage, retail and transaction solutions, thin clients, digital security, residential gateways, plus commercial and industrial control. This family of processors offers scalability to OEMs wishing to go to market with an entire product line. The rugged chassis features an integral heat sink on its top side to aid cooling. Key features include Intel Atom N450, D410 or D510 processors (all are 1.66 GHz) and fanless operation along with advanced low power consumption. The unit supports dual 10/100/1000 Ethernet LAN interfaces, two SATA interface, mounting kit for 2.5” HDD and full-featured I/O. In addition, there is one VGA connector, one RS-232, four USB 2.0 ports along with a high definition audio interface. In addition, it supports one Mini PCI & one CompactFlash. Linux (Fedora, MontaVista, SUSE), Microsoft Windows Embedded, Microsoft Windows XP and Microsoft Windows CE 6.0 are supported. The version with the Intel Atom D510 dual-core processor begins selling for $405 in OEM quantities.

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PRODUCTS & TECHNOLOGY

Rugged Ethernet Switching Solution for Increased Mission Effectiveness

Combining multi-functionality, performance and small size for deployment in the widest possible range of demanding environments, the GS12 rugged Ethernet switch from GE Intelligent Platforms improves the speed, accuracy and security with which information is distributed. The GS12 switch is a stand-alone, fully managed Layer 2/3 Gigabit unit combining a high port density of 12 Gigabit Ethernet ports with support for IPv6 switching and routing in a small, lightweight enclosure. Its combination of features allows the GS12 to be deployed in a wide array of applications in ground vehicles that need the ability to interconnect a large number of nodes. Such an interconnection requires a switch with comprehensive management and configuration features: the GS12 rises to the challenge of fitting the required high-performance functionality into a small space. The GS12 supports the latest generation of IPv6 switching and routing. IPv6 provides improved network security and reliability, while support for more network addresses allows for a greater number of interconnected devices. Additional management and configuration features include quality of service (QoS) prioritization, VLANs, LAG, SNMP, RSTP, VRRP, IGMP and traffic policing, providing customers the flexibility to meet their unique networking requirements. The GS12 measures 2.5 x 6.5 and 9.25 inches (including connectors), weighs only four pounds and is capable of withstanding temperatures between -40° and +75°C. GE Intelligent Platforms, Charlottesville, VA. (800) 368-2738. [www.ge-ip.com/gpgpu].

1U Rackmount Appliance with New Generation Atom

A 1U rackmounted hardware platform is designed for network service applications. Built with Intel Embedded IA components with long-term availability, the PL-80120 from Win Enterprises supports the Intel Atom N450, D510 and D410 low-voltage processors with CPU-integrated Northbridge chipset. The device supports a high-bandwidth DDR2 SODIMM slot with memory up to 2 Gbyte. In order to provide the best network performance and utilization the storage interfaces include one 3.5” SATA HDD and CompactFlash. PL-80120 has six GbE Copper LANs with bypass function or 5 GbE Copper LANs with bypass function and 4 10/100 switch ports, all available from the front panel. Two USB 2.0 ports, one RJ-45 console port and LED indicators for local system monitoring, management and power are also found on the front panel. The PL-80120 supports one Mini PCI socket, one PCI slot. PL80120 is RoHS, FCC and CE compliant. Linux (Fedora, MontaVista, SUSE), Microsoft Windows Embedded, Microsoft Windows XP and Microsoft Windows CE 6.0 operating systems are supported. The pricing with the Intel Atom D410 single-core CPU (1.66 GHz) begins at $380 in OEM quantities. WIN Enterprises, North Andover, MA. (978) 688-2000. [www.win-ent.com].

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MONTH MAY 2010 2010RTCRTC MAGAZINE MAGAZINE

PICMG 1.3 2U Butterfly Backplane for PCI Express Gen 2 System Designs

A 2U Butterfly Backplane for PICMG 1.3-based system designs boasts comprehensive PCI Express Gen 2 support in the smallest of spaces. Compared to competing custom solutions, the PICMG 1.3-compliant standard xPB-6E5PO from Kontron offers a more costeffective and fast system design using COTS components, ultimately helping to accelerate OEMs’ time-to-market and reducing total cost of ownership. With PCI Express Gen 2 support, the Connected xPB-6E5PO is designed forGet highest through- with tech companies providing solutions put (5.0 GT/s) with the latest frame grabbers, Connected is a new resourc graphics and network cards.Get The space-saving into products, technologies and comp butterfly backplane was developed for imis to research the latest datasheet from a age processing, with gaming and infotainment as to a compa an Application Engineer, or jump well as networking applications. Via standard goal of Get Connected is to put you in touch w Whichever level of backplane service you require graphics cards, the high-speed can for whatev Get Connected willwith help you connect with the provide, for example, 10 displays differare searching for.components, ent video signals.youWith high-end control of up to www.rtcmagazine.com/getconn 40 monitors—each with different content—is possible. In the same way, very fast image processing systems with multiple frame grabbers and graphics cards or ultra-bandwidth routers with integrated firewall and 2 x 10 Gigabit Ethernet for upstream and Get Connected with technolog downstream can be implemented. Get is a new resource for For expansion ports, Connected the new backplane datasheet from a company, speak directly offers 1 x PEG (PCIe x16), 1 x PCIe x8 and 3 in touch with the right resource. Whichever x PCIe x4 as well Get as the PICMG 1.3 slot for Connected will help you connect with the system host board (SHB). Connections www.rtcmagazine.com/getconnec for 4 x USB 2.0, 2 x SATA and 1 x LAN are included in the interface offerings of the new Kontron PICMG 1.3 backplane. To be able to support multiple PCI Express Gen 2 interfaces with any standard PICMG 1.3 module, an integrated non-blocking switch links four PCIe slots to the PCI x16 interface of the system host board.

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Products Kontron, Poway, CA. (888) 294-4558. [www.kontron.com].

Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected


PRODUCTS & TECHNOLOGY

3U CompactPCI Board Combines Atom Technology with Onboard FPGA

A 3U CompactPCI single board computer combines low-power Intel Atom XL processors with an onboard FPGA for user-defined functions. The F11S from Men Micro opens up a new range of design flexibility for not only industrial and harsh embedded computing environments, but also for a variety of embedded mobile, railway and transportation applications, including automatic train control and infotainment systems, where reliability and operation in extended temperatures are critical. Depending on the application, the board can be equipped with various 45nm-based Intel Atom XL processors, which offer a maximum power dissipation of 7W at a speed of up to 1.6 GHz. The board’s specially designed heat sink enables operation across an extended -40° to +85°C (-40° to +185°F) temperature range. The board’s standard front I/O includes a COM interface via a D-Sub connector as well as two USB 2.0 ports, graphics via VGA or UXGA and a PS/2 interface for a keyboard or a mouse. Further interfaces include a Gigabit Ethernet slot via PCI Express x1 and an FPGA-based Fast Ethernet slot on the RJ45 connectors. The onboard FPGA also allows for customer-specific interfaces, such as serial interfaces, CAN bus, binary I/O, protocol converters or touch controllers to suit a user’s specific application. The F11S can accommodate up to three SA-Adapters for additional I/O. Depending on the number of adapters, the card occupies two or three system slots. The memory configuration contributes to the board’s flexibility with the incorporation of up to 2 Gbyte soldered DDR2 SDRAM, 2 Mbyte non-volatile SRAM, a CompactFlash card and a microSD card slot in addition to the 512 Kbytes of L2 cache integrated in the processor. A board management controller supervises temperature and power, and the Phoenix Award BIOS is adapted to every application. The F11S is available as conduction- or convection-cooled and supports a Windows or Linux operating system, with VxWorks and QNX available upon request. Pricing starts at $1,443. MEN Micro, Ambler, PA. (215) 453-8700. [www.menmicro.com].

Industrial Automation Software Supports Controller Redundancy, User Interface, Reporting, Trending and Alerts

A full set of software applications and utilities for the Snap Pac System of automaton controllers from Opto22 provides control programming, HMI development, OPC connectivity, database integration, communication with Allen-Bradley Logix systems, and support for controller redundancy. Perhaps the most powerful new feature found in PAC Project 9 is its support for redundant controllers communicating over standard Ethernet. Opto 22’s SnapPac stand-alone controllers, when used with the Snap Pac Redundancy Option Kit (SNAP-PAC-ROK), can be configured for synchronous operation, with one controller executing the control program and a second essentially running in parallel, so that if the master controller fails or is knocked offline, the other controller will take command and continue to perform without interruption or restart. HMI design, alarming and configuration have been improved as well. Alarm configurations and settings can be saved for easy replication, and authenticated messages can be sent to mail servers, thereby enabling PAC Display to send SMTP-based (email) alerts whenever alarms are triggered. Alarm configurations can be imported or saved and exported as comma-separated files, thus allowing alarm settings and other tabular data to be more easily exported to databases and other PAC Display clients. PAC Display also now supports Web windows, so developers can embed Web pages in their HMI screens and subsequently collate, and reconcile data from any Web page or even view live Web cam images within their HMI environment. PID loop control tuning from within the HMI has been greatly simplified through the addition of a PID button that opens a PID tuning environment within PAC Display. Also, in response to customer requests for greater assistance in debugging, multiple instances of the runtime can now be initiated. PAC Project 9 Basic is free for download or with purchase of any Snap Pac controller. Opto22, Temecula, CA. (951) 695-3000. [www.opto22.com].

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PRODUCTS & TECHNOLOGY

MMC Management Solution Using ACTEL SmartFusion

A new module management controller (MMC) board management reference (BMR) starter kit is based on Actel’s SmartFusion intelligent mixed signal programmable/configurable application services platforms (P/C-ASPs). SmartFusion integrates an FPGA, a 40 MHz hard ARM Cortex-M3based microcontroller subsystem (MSS) and programmable analog. The new kit addresses the MMCs on AdvancedMC (AMC) modules, which are used in both AdvancedTCA (ATCA) carriers and MicroTCA (µTCA) shelves, collectively referenced as xTCA. Compared to other core silicon used for xTCA management controllers, SmartFusion extends valuable features for xTCA management controllers including customizability due to the built-in flash FPGA, which can integrate board-specific logic into the SmartFusion chip, reducing footprint and cost; in addition, relevant selections from Actel’s rich library of IP blocks can be installed in the FPGA fabric to augment the hardlogic peripherals as needed. The advanced analog processing with zero load on the ARM processor is able to do xTCA-aware analog sensor monitoring; xTCA-oriented analog sensors and other analog sensors are configured and processed in a unified way in the programmable analog subsystem. Included in the kit is a benchtop management controller development board that is implemented in an AMC form factor, which means that it can be inserted into any compliant AMC slot. In addition, the kit incorporates a complete SmartFusion FPGA design in a Libero Integrated Design Environment (IDE) project, complete firmware including full source code in C for both the management controller code and development tools, comprehensive documentation and a production license that grants designers the rights needed to design and bring to market an AMC product. There are two kit variants available: one for customers who choose to work in an ATCA-focused bench top context, and the other for companies who prefer to work in a µTCA-focused bench top context. Pigeon Point Systems, Scotts Valley, CA. (831) 438-1565. [www.pigeonpoint.com].

COM Express Module with Mobile Core i7 and QM57 Chipset

A new COM Express module is part of a portfolio of Type VI COM Express Basic (small footprint) modules from American Portwell. The Type VI COM Express Basic is becoming a new standard in 2010. At 125 mm x 95 mm (4.92˝ x 3.74˝), the compact PCOM-B216VG-VI is based on the Intel Core i7 processor and the Mobile Intel QM57 Express chipset. This dual-core platform supports error-correcting code (ECC) memory and Intel Active Management Technology (Intel AMT) 6.0 along with Intel Trusted Execution Technology for effective remote management and enhanced security. In addition, it features two SO-DIMM (non-ECC) sockets to support DDR3 SDRAM 800/1066MT/s up to 8 Gbyte; one Gigabit Ethernet; expansion (via the COM Express carrier board) of one PCI-Express x16 lane, which can be configured to two x8 lanes; one DVI-D, one HDMI and one Display Port (DP) interfaces, seven PCI-E x1, LPC interface and high definition audio interface; and a PCOM-C211 Developer COM Express Type VI carrier board. Equipped with Intel Turbo Boost technology—which automatically allows processor cores to run faster than the basic operating frequency—the PCOM-B216VG-VI addresses the market’s performance and power consumption concerns because it also supports Intel Intelligent Power Sharing Technology. This balances the load of TDP (Thermal Design Power) and temperature between the CPU and the graphics engine by enforcing power clamps to non-turbo levels. American Portwell, Fremont, CA. (510) 403-3399. [www.portwell.com].

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10GbE OEM-Ready Appliance Fueled by 12 Cores

A new dual-processor network appliance features the Intel Xeon 5600 processor series to offer enhanced computing performance for high-speed modular I/O processing of multiple GbE and 10GbE links. Purposefully built for high-end network security and packet processing applications, the FWA-6500 from Advantech takes advantage of the Intel AES New Instructions (Intel AES-NI), which frees up valuable processor cycles for more virtualization and processing. Intel AES-NI adds new instructions that provide robust encryption without the need for additional appliances or increased performance overhead. Additionally, Intel Trusted Execution Technology (Intel TXT) performs SHA-1 hash measurements for RSA decryption key exchanges as part of the code authentication process. This means greater security in network transactions without a loss in processing power. With up to 6-core operation (up to 12 threads per socket with Intel Hyper Threading Technology), 50% L3 cache increase to 12 Mbyte, and support for lower voltage DDR3L DIMMs, the capabilities of the new processors will facilitate further platform consolidation whilst decreasing power budget. Network connectivity is fast and flexible with up to 16 front accessible GbE ports supported by 4 quad Gigabit Ethernet modules, based on the Intel 82576EB Gigabit Ethernet Controller, or multiple dual 10GbE modules based on Intel’s 82599EB 10 Gigabit Ethernet Controller. The modules plug into a 32-way PCI Express (PCIe) Gen2 mid-plane, providing highspeed interconnects to the I/O controller hub, making the system fast and efficient. RJ45 and SFP/SFP+-based modules are supported and can be mixed and matched as required. Copper modules come with optional LAN bypass capabilities. Two further PCIe x4 slots are available internally for standard add-in cards for offload purposes or network processor-based coprocessing. Advantech, Irvine, CA. (800) 866-6008. [www.advantech.com].


PRODUCTS & TECHNOLOGY

FPGA-Based 6U SBC Offers Triple Redundancy for Critical Applications

A 6U FPGA-based, triple-redundant CompactPCI (cPCI) single board computer uses a lockstep architecture to keep software development costs low and to make the new board suitable for highly mission-critical applications as found in the avionics and railway markets. The lockstep architecture provides a redundant computing system that runs the same set of operations in parallel, so the programming only views hardware components once. Developed according to DO-254 as a safe computer for controlling the freight load system of the Airbus A400M, the single-slot D602 from Men Micro is now available as a COTS component The 900 MHz PowerPC 750, the 512 Mbyte main memory and the internal structure of the FPGA are triple-redundant. Critical functions, such as voters, implemented as IP cores in the FPGA ensure that at least two of the three redundant components provide the same result to guarantee safety. The system remains completely operational even if one of the three redundant components fails, providing the required availability for highly critical systems. Additional redundant components include the Flash banks, the PSUs and the clock oscillators as well as the additional ECC protection for the Flash and the FRAM. Diagnosis mechanisms (BITE, e.g. extensive self tests) help detect latent errors before they lead to a system error. For the same purpose, the design is oriented toward strictly deterministic operation avoiding interrupts and DMA. The D602 provides two PMC slots, one of which is used for an AFDX connection. Both PMC modules are accessible at the front in the standard version, but can be accessed via rear I/O when used in a conductive-cooling system. Pricing starts at $14,193. . Get Connected with technology and MEN Micro, Ambler, PA. (215) 542-9575. [www.menmicro.com]. companies providing solutions now

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nanoETXexpress Starterkit for Wind River VxWorks

A new Atom Processor-based COM Express-compatible nanoETXexpress Starterkit for the latest VxWorks platform is designed to enable easy and efficient development and validation of real-time appliances based on the smallest x86 solutions. This starter kit from Kontron is pre-configured with the Kontron nanoETXexpress-SP Computer-on-Module. The Kontron nanoETXexpress-SP Starterkit for VxWorks allows developers to address critical issues such as integration costs, time-to-market and long-term support, right from the start of platform evaluation. Developers receive the Kontron nanoETXexpress-SP Computer-onModule based on the Intel Atom Z530 processor (1.6 GHz), which has onboard 512 Mbyte system memory and a 2 Gbyte flash drive. The module is integrated with the Kontron nanoETXexpress-HMI Board plus a 7â&#x20AC;? WVGA touch panel, 12V power supply and all required cables and accessories. The onboard 2 Gbyte flash drive is pre-programmed with the latest VxWorks operating system and HMI application demonstration. The starter kit also includes a USB drive containing a fully functional 30-day trial of the Wind River LiveUSB Environment that includes Wind River Workbench 3.2, Wind River Tilcon Interface Development Tool 5.7 and VxWorks 6.8. Tutorial videos are included in the accompanying documentation to help engineers immediately begin using the platform, evaluating their own appliances, or running benchmarks Kontron, Poway, CA. (888) 294-4558. [www.kontron.com].

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly AC-DC Power Controller Family for Dimmable with an Application Engineer, or jump to a company's technical page, the LED Lighting goal of Get Connected is to put you in touch with the right resource. Whichever level servicenon-dimmable you require for whatever type of technology, A cost-effective solution forof both and dimmable Get Connected will help you connect withEnergyStar the companiesreand products LED lighting, delivers high efficiency while meeting you are searching for. quirements. The CY8CLEDAC01/02 controllers provide automatic

www.rtcmagazine.com/getconnected dimmer detection, so they work with the majority of the existing installed base of wall dimmers, providing dimming down to 2% with no flicker. The new ACDC controllers Get Connected with technology and companies provi offer primary-side Get Connected is a new sensing resource for with further exploration into pro tight datasheet from a company, speak directly with an Application Engine LED current regulain touch with the right resource. Whichever level of service you require tion, eliminating the and produc Get Connected will help you connect with the companies need for opto-isolation www.rtcmagazine.com/getconnected and other secondary-side control circuitry. This technique minimizes component count to reduce board space, power consumption and overall BOM costs compared to other isolated solutions. The new controllers also feature circuit protection not normally available with other primary-side control solutions. The built-in protection features include over-voltage protection (OVP), output short circuit protection (OSCP), peak current limit protection (PCLP), current-sense resistor short protection (CSSP) and over-temperature protection (OTP). Reference designs for both the Get Connected with companies and CY8CLEDAC01 and CY8CLEDAC02, including all schematics, BOM, products featured in this section. gerber fileswww.rtcmagazine.com/getconnected and documentation to create a power supply for a fully functional LED retrofit bulb, are available.

Products

Cypress Semiconductor, San Jose, CA. (408) 943-2600. [www.cypress.com]. Get Connected with companies and products featured in this section. www.rtcmagazine.com/getconnected

RTCRTC MAGAZINE MAGAZINEMONTH MAY 2010

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PRODUCTS & TECHNOLOGY

New Class of Designs Features Latest Expansion of SHARC DSP Portfolio

Analog Devices has unveiled the newest additions to its SHARC portfolio of 32-bit floating point digital signal processors—the SHARC 2148x and SHARC 2147x series. Delivering a balance of performance and price with up to 5 Mbyte of integrated memory, high-performance SHARC 2148x and low-power SHARC 2147x series processors extend single-chip, floating point signal processing precision to a wide range of applications. With SHARC 2148x and SHARC 2147x processors, designers can take advantage of end-to-end SHARC family code compatibility and a robust suite of ADI development tools. SHARC 2148x series processors deliver up to 33% greater performance (400 MHz) and up to 250% more on-chip memory (5 Mbyte) than competing 32-bit floating point DSPs, distinguishing the SHARC 2148x series as the processors of choice for high definition (HD) audio and home theater applications, as well as advanced industrial applications requiring single-chip, floating point precision at a low price point. For portable devices and applications that require floating point processing precision with low power consumption and high environmental tolerance, new 12x12 mm SHARC 2147x series processors consume only 363 mW power (typical use-case)—up to 20% less power than competing processors—and deliver performance up to 266 MHz with up to 5 Mbyte on-chip memory to provide more performance and memory integration per square millimeter than any other competing floating point DSP. The new SHARC 2148x and SHARC 2147x processors feature dedicated hardware accelerators with independent compute units and DMA memory mapping, enabling the ability to execute FFT/FIR/IIR signal processing operations in the background to free up MIPS for core processing. Memory usage is optimized via Variable Instruction Set Architecture (VISA) support, which can free up as much as 30% of memory space for application code through reductions in instruction opcode sizing. Analog Devices, Norwood, MA. (781) 329-4700. [www.analog.com].

MicroTCA Chassis Line for Smaller, Rugged Embedded Applications

A series of compact, rugged MicroTCA chassis models provides flexibility in a variety of industrial, commercial and military environments. The new ATR chassis from LCR Electronics employ machined box construction. This enables LCR’s enclosures to conform to rigorous, industry-leading MIL-STD specifications including 810F Methods 514.5, 513.5, 516.5, 507.4 and 509.4 for vibration, acceleration, shock, humidity and salt fog, respectively. Additional MIL-STD specifications that the new chassis meet include 167 Type 1, Para. 5.1 for vibration, 901D lightweight hammer for shock and 461D for EMI. An optional shock-isolated card cage provides additional rigidity to internal electronics. Each MicroTCA rugged enclosure can feature up to a 10-slot backplane and is configured to ARINC 404A. The chassis are air-cooled or conduction-cooled in a variety of standard and custom sizes to accommodate numerous application environments with customizable I/O also available. Operating temperature is -40° to +85°C and storage temperature is -55° to +95°C. LCR Electronics, Norristown, PA. (610) 278-0840. [www.lcr-inc.com].

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PRODUCTS & TECHNOLOGY

NEW! Larger FPGA for PCIe x8

3-Phase Models Join Line of High-Power Intelligent Power Supplies

FPGA board / ac accelerator

Giant conď&#x192;&#x17E;gurable FPGA (XC5VSX240T) PowerPC 440 processing User-available DDR2 1.2 to 1.6 GB/s DMA Standard connector for mezzanine boards â&#x20AC;˘ Windows, Linux, Solaris â&#x20AC;˘ â&#x20AC;˘ â&#x20AC;˘ â&#x20AC;˘ â&#x20AC;˘

NEW! MIL-STD-1553B for PCIe

Two new 3-phase models of digitally configurable AC-DC power supplies are rated for up to 4920W of high-density output power (12W per cubic inch). The iVS power supplies from Emerson Network Power are a suitable choice for industrial applications that require reliable high-power output and maximum flexibility. The iVS power supplies use digitally configurable single, dual and triple output power supply modules available in power ratings up to 1500W. The iVS case can support up to 24 output ratingsâ&#x20AC;&#x201D;from 2V to 60Vâ&#x20AC;&#x201D;to enable a flexible range of power configurations. All modules are interoperable with existing Emerson Network Power iVS power supplies and can be quickly configured to match exact application requirements, enabling greater precisionUntitled-7 and energy efficiency. The new iVS6 and iVS8 models each support 170 VAC to 264 VAC 3-phase inputs. iVS power supplies are pre-certified to meet a range of safety specifications, including UL, CSA, VDE, CE and CB certification. In addition, all iVS power supplies feature field-upgradable firmware to extend product lifecycles and increase flexibility. Performance temperatures range from -40° to +70°C. To maximize control flexibility, iVS power supplies are equipped with Emerson Network Powerâ&#x20AC;&#x2122;s GUI-based I2C control software. The software enables designers to configure and reconfigure voltages, current limits and inhibit/enable settings for individual power. It also enables users to export final configuration specifications for backup or mass production and offers real-time voltage, current and temperature monitoring for at-a-glance performance confirmation for the entire power supply. Pricing starts at $756. Emerson Network Power Carlsbad, CA. (760) 930-4600. [www.PowerConversion.com].

â&#x20AC;˘ â&#x20AC;˘ â&#x20AC;˘ â&#x20AC;˘

1 bus controller 1 bus monitor 31 remote terminals Windows, Linux, Solaris

www.edt.com

1

5/13/10 4:28:02 PM

Conduction Cooled VME Solid State Disk Phoenix Internationalâ&#x20AC;&#x2122;s VC1-250-SSD Conduction Cooled Serial ATA (SATA) based Solid State Disk VME blade delivers high capacity, high performance data storage for military, and y, aerospace p industrial applications requiring rugged, extreme emee envi eenvironmental i ron ronmen me tal and secure mass data storage.

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High Operational Hi Temperature +85° C

Operational Altitude to 80,000 feet

'PSPVSFOUJSFMJOFPGTUPSBHFQSPEVDUTXXXQIFOYJOUDPNt 714ď&#x161;ş283ď&#x161;ş4800 An ISO 9001: 2000 CertiďŹ ed Service Disabled Veteran Owned Small Business

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RTC MAGAZINE MAY 2010

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Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

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Themis Computer..............................................................................................................38.............................................................................................................. www.themis.com TRI-M Systems.................................................................................................................20.................................................................................................................www.tri-m.com VersaLogic Corporation.....................................................................................................42......................................................................................................... www.versalogic.com XTech...............................................................................................................................43....................................................................................................www.xtech-outside.com RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. 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MAY 2010 RTC MAGAZINE


Computing/HMI

Serial

I/O

The right connection creates incredible power. Connectivity and control. Making your interface as reliable as the tidesâ&#x20AC;&#x201D;and just as strong. Sealevel creates hardware and software solutions for both digital and serial interface requirements. We Listen. Think. And Create.

Experience exceptional low power RISC computing with SBC-R9, a CE .Net application-ready platform for your next product design.

sealevel.com > sales@sealevel.com > 864. 843. 4343

Š 1986-2010, Sealevel Systems, Inc. All rights reserved.


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