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The magazine of record for the embedded computing industry

April 2010



FeaturePak: New Modular I/O Specification Gains Ground USB and/or PCIe— Which to Use When? Small Modules Roar in Data Acquisition An RTC Group Publication



46 EPIC-Express Board Demonstrates New Cooling Concept and Mechanical Design

51 AdvancedMC Sports Quad-Core Performance


53 Rugged 3U OpenVPX Data Recorder with Eight 6 Gbit/s Links

APRIL 2010



ASPs: A New Class of Devices

Application Services Platform: A New Class of Device 6Editorial 12 The What Do We Call the Whatchamacallit? for Embedded Development and Systems Industry Insider 8Latest Developments in the Embedded Marketplace Tom Williams

Form Factor Forum 10Small A Tale of Two Embeddeds


Products & Technology Newest Embedded Technology Used by Industry Leaders



EPIC-Express Board Demonstrates New Cooling Concept and Mechanical Design

Technology in Context Advances in Small Form Factors


Introducing the FeaturePak Embedded I/O Expansion Standard


Bigger Jobs in the Same Space

Jonathan Miller and Rick Lehrbaum, Diamond Systems

Martin Mayer, Advanced Digital Logic


USB? Sorting Out Two COM / SFF Design Decisions 26 PCIe? John Hentges, ACCES I/O Products

Digital Subscriptions Avaliable at

and PCI Express: Advanced, Evolving Interconnects for 30 USB Embedded Systems Akber Kazmi, PLX Technology

TECHNOLOGY IN SYSTEMS Marrying COMs and Carriers Designing for Performance and

COMs with Carrier 34Longevity: Boards Christine Van De Graaf, Kontron

TECHNOLOGY DEPLOYED Data Acquisition with Small Modules

Digitizers Recapture 38High-Speed Innovation as ADCs Yield to FPGAs Anthony Hunt, Signatec

Industry Watch Touch Screen Technology

Your Finger to the Screen How Touch Screens Understand 42From Steve Kolokowsky and Trevor Davis, Cypress Semiconductor



APRIL 2010 Publisher PRESIDENT John Reardon,

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

Art/Production CREATIVE DIRECTOR Jason Van Dorn, ART DIRECTOR Kirsten Wyatt, GRAPHIC DESIGNER Christopher Saucier, GRAPHIC DESIGNER Maream Milik, DIRECTOR OF WEB DEVELOPMENT Marke Hallowell, WEB DEVELOPER James Wagner,

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Free Online Spotlighting the Trends and Breakthroughs in the Design, Development and Technology of Embedded Computers. Search Archived Editions along with the Latest News in the Embedded Community. An RTC Group Publication



To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, Editorial Office Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214

Published by The RTC Group Copyright 2008, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


Tom Williams Editor-in-Chief

What Do We Call the Whatchamacallit?


ow is it that very smart people seem to have similar ideas at around the same time? In our industry, when such a thing happens we tend to think of a trend, or in other cases of some form of uniquely new technology. Then we seek to give it a name, and if it really catches on, it becomes yet another industry acronym. We here at RTC are motivated to do just that with respect to an innovative combination of microprocessor and programmable logic technologies into a class of devices that hold the potential for greatly reducing the parts count, cost, power consumption and design effort for a wide range of embedded systems. Long has been the quest for that single general-purpose, highly integrated piece of silicon that could serve as the center of an embedded system. All attempts from ASIC to ASSP to FPGA to full custom silicon have been a balancing act between cost, performance, and in the case of custom devices, the projected volume needed to amortize the design and production costs—the more custom the device, the higher the volume needed to justify the cost. The class of devices we are choosing to call the Application Services Platform (ASP) represents a big step toward the center of this maelstrom. Basically, this new device class is a combination of a 32-bit microcontroller or microprocessor (some will even have multiple cores) with a set of standard peripherals such as UARTs, CAN, I2C, GPIO, USB and PCIe to different classes of memory and mass storage, etc. There is also analog I/O and a fabric of programmable logic into which can be loaded soft devices or algorithms from libraries of predesigned IP, or which can be programmed from scratch with specialized, custom devices and algorithms that can act as coprocessing routines for the main CPU. The exact combination of CPU, standard peripherals, analog circuitry and programmable fabric will vary with the kinds of target applications as the world of ASPs develops and grows. The main point, and the reason for the term “Application Services Platform” is that with the exception of main memory and mass storage (and currently graphics capability), all the hardware services needed by the application can be supplied by this single silicon chip. It almost seems as if we had taken a COM CPU module (less its system memory) along with a custom I/O carrier card and smooshed them both down onto a silicon die. The device is programmable in the sense that it has a RISC (and later maybe a CISC) von Neumann-



style processor that is programmable in C, and the programmable logic fabric is programmable with the same tools used to develop FPGAs. These include the kinds of graphics-based tools that shield the developer from having to know specialized languages like Verilog or HDL. These latter tools, rather, make the fabric more configurable than directly programmable because they enable the inclusion and connection of predefined IP. It will be up to the system architect and design team to determine what level of configuration and programming is required in the fabric by the individual application. The real advantage is that once the standard peripherals are selected and connected, and the fabric loaded with whatever combination of IP is required, the entire device can be presented to the application programmer as a known entity with digital values appearing at the interfaces that can be used by the application software. For example, even multiple analog inputs can be digitized and routed into the fabric through whatever filter or signal processing algorithms may be there and appear to the program in parallel without processing overhead from the main CPU. That beats having to add a separate DSP to the design with its specialized code—or even a separate FPGA—in order to process just a few needed inputs. The time and money spent programming those things into the fabric could be well rewarded in the long run. In this month’s “Editor’s Report,” we present implementations being carried out by three leading companies: Cypress Semiconductor, Actel and Xilinx. They are all technical advances in their own right as well as signposts pointing forward to where this combination of technologies will lead. They already point to the potential diversity of the ASP concept with the first step having been an 8-bit design followed by 32-bit incarnations with different emphasis on I/O, processing power and peripheral mix. There is room for much more diversity and innovation within the basic model of the ASP. The advantages in terms of size, power, cost, time-to-market and inventory are potentially huge. There are still challenges ahead in terms of the development of an appropriate tools environment that will not only enable the ease of programming and configuration of these devices from a system viewpoint, but will also enable software and hardware specialists to easily communicate with one another. The potential advantages of the ASP, however, seem destined to motivate intense efforts in this area as well.

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INSIDER APRIL 2010 FeaturePak Initiative to Move Spec to Standards Organization In the wake of the introduction of the FeaturePak I/O module specification, efforts are underway to establish it as a recognized standard. Currently, the FeaturePak specification is being maintained by the FeaturePak Initiative, which includes Diamond Systems Corp., originator of the standard, plus FeaturePak Initiative “Charter Members” Arbor Technology Corp., Cogent Computer Systems Inc., congatec, Connect Tech, Douglas Electronics, Hectronic and IXXAT Automation. Diamond plans to transfer ownership of the FeaturePak specification, trademark and logo to a suitable standards organization in the near future, so that all companies in the embedded market can enjoy its benefits. The selected organization will be responsible for maintaining, extending and promoting the FeaturePak standard, and will have the authority to establish rules associated with use of the FeaturePak trademark and logo. Notwithstanding the plan for this organization and the opportunity for companies to join it in order to influence the future development of the FeaturePak Specification and the collective efforts to proliferate the standard, the specification itself is available for free download (on request), and may freely be used without becoming a member of any organization. In short, the use of the FeaturePak standard itself is completely open and free. However, the use of the FeaturePak logo in connection with FeaturePak-related products is restricted to members in good standing of the FeaturePak Initiative (or eventual parent organization). To learn more about the FeaturePak Specification and FeaturePak Initiative, to obtain a copy of the FeaturePak Specification, or to find out how to join the Initiative, visit the Initiative’s Web site at

QNX and Real-Time Systems Team to Combine RTOS with Hypervisor

QNX Software Systems and Real-Time Systems have formed an alliance that will provide customers a combined solution of the RTC Hypervisor 2.2 with QNX Neutrino RTOS. This will allow developers to run Neutrino on the same hardware as Windows, Linux and other operating systems. The solution represents a hardware consolidation in that it can reduce system costs by eliminating the need for additional processors. It is also particularly useful for industrial and medical applications where many users rely on an RTOS



like Neutrino for time-critical and mission-critical functions like motion control, while using a different operating system for other functions, such as running a legacy human interface (HMI). Because the solution does not depend on a host operating system, the operating systems can reboot independently and not interfere with each other. Within the RTS Hypervisor environment, inter-system communication is simplified through a virtual TCP/IP-based network. Real-Time Systems technology also supports message-signaled interrupts (MSI) for the QNX Neutrino and other operating systems, eliminating interrupt conflicts and simplifying system configuration.

VITA Issues Call for Research into Optical Architectures

The VME Industry Trade Association (VITA) has announced the formation of the VITA Architectures for Optical (VAO) Study Group that will be researching high-density optical interconnect technology and developing a proposal for nextgeneration architectures for critical embedded systems. A call for participation in the study group goes to non-VITA members to make presentations and participate in discussions with the Study Group. A study group is the initial step in the process of developing an ANSI/VITA standard. The mission of the VITA Architectures for Optical Study Group is to research and determine the feasibility of developing a standard architecture for optical interconnects suitable for deployment in critical embedded systems. The study group will focus on high-density options for backplanes and connections between line-replaceable units, mezzanines and daughter cards. Critical embedded systems are high-performance, distributed computing systems, and they manage highbandwidth I/O; involve real-time processing; and are environmentally constrained in size, weight and power (SWaP). VITA has set up a Web page at voa to track information related to optical technology.

GoAhead Software Moves to Open Source Business Model

GoAhead Software has announced that it is shifting its business model and technology strategy from its proprietary SAFfire product to an open source software model. Simultaneous with the move to open source,

GoAhead is announcing the acquisition of Avantellis from Emerson Network Power. These two moves combine to create a new overall strategic direction for GoAhead. The decision to move to open source is being made now due to a number of market developments that indicate a significant overall shift toward adoption of OpenSAF, the open source community focused on high-availability middleware: • T he maturity and stability of the OpenSAF software distribution, especially the upcoming 4.0 release • T he continued support of the OpenSAF Foundation by key industry players such as Ericsson, Emerson, HP, Wind River and Huawei • T he inclusion of OpenSAF in commercial deployments by industry leaders such as Ericsson In conjunction with the move to open source, GoAhead is formally announcing that it is joining the OpenSAF foundation. GoAhead will be contributing key components of its SAFfire middleware to OpenSAF, and company President Asif Naseem will be joining the OpenSAF foundation as a board member.

ZigBee and Wi-Fi Alliances to Collaborate on Smart Grid Wireless Networking

The ZigBee Alliance and the Wi-Fi Alliance have announced an agreement to collaborate on wireless home area networks (HAN) for Smart Grid applications. The initial focus of the collaboration will be ZigBee Smart Energy 2.0, which is the next-generation energy management protocol for Smart Grid-enabled homes based on today’s successful ZigBee Smart Energy Profile. The ZigBee Smart

Energy 2.0 is expected to operate over Wi-Fi technology as a result of the collaboration. The two organizations will identify opportunities to use ZigBee Smart Energy 2.0, capitalizing on the unique strengths and capabilities of their respective technologies. This will expand the utility of the HAN in the management of energy consuming or producing devices, a crucial part of Smart Grid efforts now underway. ZigBee Smart Energy 2.0 was selected last year by the U.S. Department of Energy and the National Institute of Standards and Technology (NIST) as an initial interoperable standard for HAN devices.

ZigBee Smart Energy was initially developed to operate over a standard ZigBee wireless network to support the needs of Smart Metering and Advanced Metering Infrastructure (AMI). ZigBee Smart Energy 2.0 has been designed to support other network technologies within the digital home, including HomePlug and now Wi-Fi. The lowpower ZigBee standard is optimized to the needs of Wireless Sensor Networks by offering robust, self-organizing, self-healing mesh networking; scalability to very large networks; very low cost and complexity; and superlative battery life.

Kontron Enhances Global Software Services

Kontron has announced a centralized Global Software Design Center aimed at further extending Kontron’s in-house design services for customer applications by offering enhanced, complex software support, helping OEMs reduce time-to-market and improve application quality. While continuing to offer local software support, the Kontron Global Software Design Center will be the company’s central service point for the handling of the increasingly complex software functionalities of customers’ embedded computing solutions. For example,

in the future, virtualization will play a major role for customers’ applications. To fully benefit from these often multicore-based architectures, it is vital to have vast expertise in this field for all relevant operating systems. With customers continually seeking a reduced time-to-market, the team will also offer application-ready solution bundles and an extended variety of dedicated platforms for multiple vertical market segments. The Software Design Center will also provide services such as the porting of drivers and middleware, the porting, adoption and validation of target software applications and the validation of the entire hardware and software solution.

RTEC10 is an index made up of 10 public companies which have revenue that is derived primarily from sales in the embedded sector. The companies are made up of both software and hardware companies being traded on public exchanges. All numbers are reflected in U.S. Dollars. Learn more at Company


52 Week Low

52 Week High

Market Cap

Adlink Technology





Advantech Elma Electronic Enea Interphase Corporation Kontron

























Performance Technologies





PLX Technology





RadiSys Corporation





Mercury Computer Systems

Market Intelligence & Strategy Consulting for the Embedded Community Complimentary Embedded Market Data Available at: RTEC10 involves time sensitive and currency exchange to determine the current value. All values in USD. Please note that these are subject to certain delays and inaccuracies. Do not use for buying or selling of securities.



Colin McCracken & Paul Rosenfeld

A Tale of Two Embeddeds


ttending an embedded-focused trade show is always an interesting experience. For those of us who cover the broad embedded market, you’ll have to excuse us if we are unable to check our schizophrenia at the door. For the embedded market today makes the Two Faces of Eve look like a minor childhood setback. There are truly two faces of the 32bit / 64-bit embedded market, and never the twain shall meet. In one corner we have the down and dirty embedded PC market, characterized by x86 notebook /netbook processors on a broad set of off-the-shelf single board computers and computer-on-module products in a variety of industry standard form factors. In this segment, hardware design is focused on system level issues and integration of diverse components. Actual board design is limited to the specialized I/O needed to implement the application. Design of a custom CPU board, let alone a custom CPU chip, is reserved for the lunatic fringe. It’s an off-the-shelf market. Software design focuses on application development. Customization and configuration of the operating system is unnecessary because the underlying architecture is locked down to PC standards implemented religiously in processors and chipsets. Windows is king, with Linux taking a large share of the former DOS market. Software designers in this space have no use for an in-circuit emulator (ICE), much less a software simulation tool of any kind. Why do this when you can run your application full speed on your desktop PC with outstanding but cheap debug tools at your immediate disposal. This is self-hosted development. Let’s admit that this segment is not the place for applications with any kind of real-time (read “deterministic”) requirements that would be buried under an avalanche of variable clock cycle execution times, instruction pipelines and caches in that huge CISC machine. On the flip side, we have tiny, power-efficient RISC cores available in off-the-shelf chips or in the form of cores for the hearty do-it-yourselfer to roll his or her own CPU. Every implementation targets an application and is therefore different. Chip design skills, FPGA design, or at least a solid foundation in system design are a must on the hardware side. Thorough, accurate simulation is essential as the cost of error is enormous. Bus considerations focus more on the on-



chip interfaces like ARM’s AMBA than the off-chip interconnects such as PCI Express found in that “other” market. On a good day, there might be an off-chip 16-bit local bus. And the software side is as different as night and day. Even the names of the major operating systems serving this segment are Greek to the x86 designer: VxWorks, QNX, Integrity, Nucleus, Thread-X, OSe and others. The very first software step is to create a board support package (BSP) or basic driver set for that custom CPU implementation—a task that requires very different skills from application development and can only be found on BIOS developers in the x86 world. Debugging, of course, requires extremely effective simulation cross-development (host-target) and remote debugging via a JTAG ICE. Determinism, or hard real time, is the name of the game here. Over the years, there have been a few efforts at crossfertilization between these diverse segments. Even now, just a few RISC-based SFF boards are available off-the-shelf in non-standard form factors. But a veteran x86 designer would face a brave new world of simulation, cross compiling, remote debugging, and tools and operating systems with a few more digits after the dollar sign. Within the RISC world, there has been little penetration by x86 processors or look-alike cores in spite of the best efforts of the major proponents of x86 architecture. Even offthe-shelf small form factor SBCs and COMs are few and far between. Having spent time in the late 90s trying to engineer just such a crossover, we can tell you it feels like trying to fit Shaquille O’Neal with a size six pump. You can squeeze like crazy, but even if the shoe fits, you won’t be able to walk. So what conclusions can we draw from these diverse, zero overlap embedded market segments? Neither one could replace the other. Crossover is difficult, if not impossible. Even moving people from companies serving one space to the other is fraught with danger. Both serve specific applications with requirements that rarely overlap. Both are needed. Both are necessary. Both meet their respective application requirements and carry their own set of challenges for the future. And let’s leave it at that.

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ploration your goal k directly age, the source. ology, d products

editor’s report P/C-ASPs: A New Class of Devices

The Application Services Platform: A New Class of Device for Embedded Development and Systems A new class of device is appearing in the world— the Application Services Platform or ASP. With the integration of CPU, standard yet configurable peripherals and a programmable fabric, all the services needed to develop an application are available to the developer on a single chip. by Tom Williams, Editor-in-Chief

There have been many attempts over disappeared, we are now going in a posithe years to achieve a highly integrated tive direction with a class of devices that system-level device on a single piece of integrate a 32-bit CPU, a selection of comnies providing solutions nowhave been ASICs, ASSPs, silicon. There monly used peripheral interfaces such as ion into products, technologies and companies. Whether yourefforts goal is to research the latest SoCs and more. There have been UART, USB, GPIO, analog, SATA, I2C, ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you to implement entire systems as soft IP on memory interfaces and so on. In addition, you require for whatever type of technology, All offor. these have run up against they also incorporate a programmable and productsFPGAs. you are searching issues like the need for high volume to logic fabric based on FPGA technology justify costs or the need for developers to that can integrate off-the-shelf IP in the become versed in esoteric languages such form of predefined devices or algorithms as Verilog or HDL. Often special needs, and can still be custom programmed for like a certain amount of signal process- very specialized needs. ing, have required the addition of a DSP All of these common and specialized as coprocessor with attendant costs, la- interfaces can then be made available as tencies and the use of specialized coding digital services to the programmer on the knowledge. single, integrated device, the ProgrammaWhile these issues have certainly not ble/Configurable - Application Services Platform, or simply the Application Services Platform (ASP). At least three comGet Connected panies are currently implementing ASPs with companies mentioned in this article.

End of Article



Get Connected with companies mentioned in this article.

in different forms: Cypress Semiconductor with its PSoC family, Atmel with its SmartFusion devices and Xilinx with its “extensible processing platform” architecture. All three families are based on the ARM RISC architecture—the ARM Cortex-M3 for Cypress and Actel, and a dual-core ARM Cortex-A9 in the case of Xilinx. They also differ in the mix of peripherals and the emphasis on analog processing, but all three indicate a new direction for embedded development. It seems that the trend began in the 8-bit world with the Programmable System-on-Chip (PSoC)3 from Cypress. The PSoC3 is based on an 8051 core and is the answer to the drudgery of sorting through catalogs of hundreds of 8051 variants looking for the right mix of peripherals. Why not just include the most commonly used with configurable digital and analog I/O blocks on a single die and let the user configure the desired mix of peripherals using an intuitive graphical tool? Then stand back and let the software guys program it in C as they are very capable of doing. More recently, Cypress introduced the PSoC5 (Figure 1), which uses the same set of peripherals but brings in the 32-bit ARM Cortex M-3, which can run both ARM’s Thumb 2 16-bit code or 32-bit code. PSoC5 consists of three components: the processor layer includes the CPU core, memory interfaces, EPROM, DMA controller and interfaces for CAN 2.0, I2C and USB 2.0. The I/O portion is highly configurable by means of the graphical tool called PSoC Creator. One part is the digital subsystem, which consists mainly of an array of universal digital blocks of programmable logic that can be defined as UARTs, timers, multiplexers, LCD drivers and more by use of PSoC Creator. The analog subsystem similarly is built up with elements that can be programmed as DACs, ADCs, op-amps, comparators, etc. that can be set up from a library of pre-built components, which can be configured further using the tool. In addition, there is a twochannel digital filter block. Analog channels can have up to 20 bits of resolution. One other element provides a highly configurable interconnect between the elements

























IC 2

FS USB 2.0










Figure 1 The three layers of the PSoC architecture are, except for the processor core, the same for both the PSoC3 and PSoC5 devices. I/O can be routed to selected external pins on the chip and to internal elements via the programmable routing and interconnect block. Supervisor PLL




32 KHz






SysTick ENVM





ARM Cortex - M3


Microcontroller Subsystem Programmable Analog FPGA Fabric











AHB Bus Matrix UART_0




Temp. Mon.



Volt Mon. (ABPS)


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Volt Mon. (ABPS)

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Sample Sequencing Engine


Post Processing Engine


Versa Tiles



Figure 2 The SmartFusion devices from Actel are based on the ARM Cortes-M3 and include in addition to the programmable fabric, a programmable analog subsystem with an analog compute engine (ACE).

on the processor layer, the configurable block of the digital and analog subsystems, and the external pins on the chip via GPIO ports—all of which can be defined with PSoC Creator. The tool also lets you assign names to the elements that then form part of the API that is available to the programmer. The programmer simply needs to know the names and functions of the API and can proceed to start developing code.

And Now We Add the Fabrics

Taking the PSoC idea to its logical conclusions—with enormous consequences for embedded system developers—are two FPGA companies, Actel and Xilinx. Each has independently come upon the idea of taking the processor with its array of configurable peripherals and adding the programmable fabric of a field programmable gate array. This is a fundamentally different approach from the earlier method of embedding soft CPUs, or in some cases hard-wired processors, in the programmable fabric. In these designs, the programmable fabric plays the role of a programmable/configurable peripheral field. In both the SmartFusion product family from Actel and the new architecture announced by Xilinx, the fabric is configurable in the sense that the system architect can specify and bring in predefined peripheral devices as well as pre-written algorithms for custom coprocessing. It is also programmable in the sense that specialized soft devices as well as algorithms can be programmed from scratch if need be. SmartFusion uses a microcontroller subsystem based on the 32-bit ARM Cortex-M3 with a 10/100 Ethernet MAC, two each of SPI, I2C, UART and 32-bit timers. In addition there are 512 Kbyte of flash and 64 Kbyte of SRAM on-chip along with an external memory controller and a DMA controller and up to 41 MSS I/Os (Figure 2). The Xilinx “extensible processing platform” architecture has gone full bore to a dual-core microprocessor and is



editor’s report

Processor System Coresight Debug


Cortex - A9 w/NEON I/D Cache

Cortex - A9 w/NEON I/D Cache






L2 Cache DMA


Parallel CTLR



AMBA Network Interconnect


Config Security

Select I/O

Programmable Logic

SysMon ADC


Figure 3 The extensible processing platform architecture announced by Xilinx places emphasis on a high-powered dual-core ARM Cortex-A9 with a wide variety of pre-defined peripherals in addition to the programmable fabric.

based on the dual-core superscalar ARM Cortex-A9 with the NEON 128-bit SIMD engines. The microprocessor subsystem includes a large number of pre-built peripherals including GPIO, tri-mode Ethernet (10/100 Mbit and 1 Gbit), USB 2.0, UART, CAN, I2C, SDIO and SPI. In addition, there is a variety of external memory interfaces including flash and NAND controllers, parallel and DDR



controllers. Pre-implemented on the FPGA fabric are additional configuration and security interfaces, including a system monitor, 12bit ADC and Gen 1 and 2 PCIe (Figure 3). Both device families have on-chip analog interfaces, although the SmartFusion devices appear to have placed greater emphasis on the analog aspect, making it a complete analog subsystem. An analog compute en-

gine (ACE) offloads the CPU from analog tasks—it incorporates a sample sequencing engine and a post processing engine. The analog section also incorporates 12-bit DACs at up to 600K samples per second and up to ten 50ns comparators. In all, there are up to 32 analog inputs and 3 outputs depending on which version of the device is chosen. In the SmartFusion family there are currently three members with 60K, 200K and 500K gates respectively. Device configuration is stored in on-chip flash memory that can be locked against tampering and reprogramming. The SmartFusion devices have up to 128 FPGA I/Os depending on which device is chosen. Xilinx has not yet released product-specific data as to the sizes of its arrays or the number of I/Os. Programming of these ASP devices at the microcontroller/microprocessor end is straightforward with the wide variety of ARM development tools that are available. Configuration and programming on the fabric end are supported by company-specific tools. Of course, each company will supply and support a selection of ARM tools, but the developer is free to use whichever ones appear most suitable and familiar. There will, of course, be a number of tools available to shield the developer from having to deal directly with FPGA-specific programming languages such as Verilog and Hardware Description Language (HDL), which are still the realm of specialists. There are graphical UI tools for the use of pre-existing IP libraries for both environments as well as company-specific FPGA development tools for programming, timing analysis, power optimization, etc. The interesting question is how this new class of devices will affect the development culture. We are predicting that it will catch on and grow due to a number of very specific advantages. The first is inherent in the name “application services platform.” The idea is to present to the application programmer on a single chip all the services that will be needed by the application in a form that the C programmer can readily understand and incorporate into the application code. An ASP literally contains all the devices, common or custom, short of main memory, mass storage and display, that an embedded device may need. These are put together during the configuration stage when peripherals

editor’s report

are selected and configured, or in the case of the programmable fabric, downloaded, connected and/or created from scratch. Obviously, this latter part may require differing levels of specialized expertise, such as that of a DSP specialist who can create needed algorithms in the fabric. Such components would be specified by the system architect. Once they are created and incorporated however, they can be utilized by the application programmer using his or her established skills. The savings in parts and in the bill of materials have the potential to be impressive. For example, suppose a medical device requires a couple of DSP algorithms to process an ultrasound signal. Normally, this might require a DSP coprocessor and attendant software and programming, which would run up the parts costs, development time and inventory. Having a specialist create the small set of needed algorithms that could then be loaded into the FPGA fabric could represent significant savings on all these fronts and also improve performance. The result would be a number of algorithms that could process inputs without intervention of the processor,

making the digital results available to the application code. An arbitrary number of such algorithms could run in parallel on the fabric significantly reducing latencies. All this still happens on the same chip, obviating the need for a coprocessor, extra board space and power consumption. Another potentially large advantage of ASPs is their effect on bills of materials for what could be a family of devices. Simply changing the programming and configuration of the same physical device could yield radically different systems and subsystems for applications such as medical devices, transportation systems, system management applications and many, many more. What we are seeing with the advent of the Application Services Platform is the emergence of a new class of devices that will have a very big impact on the design of, especially, small, handheld, mobile and low-power systems. These first three incarnations will certainly not be the last, from these companies and from others. We already notice a difference of emphasis between the Actel SmartFusion family and the extensible processing

platform architecture being announced by Xilinx. SmartFusion places more emphasis on a programmable analog subsystem while Xilinx appears to be heading for a family based on a high-performance dual-core CPU. It is not inconceivable that there may be additional processor architectures that will find their way into an ASP architecture, perhaps with emphasis on graphics and user interface. There will no doubt be partnerships that will be formed between processor manufacturers and programmable logic vendors. By the way, there is a limited number of the latter, so dance cards may begin filling quickly. Actel Mountain View, CA. (650) 318-4200. [] Cypress Semiconductor San Jose, CA. (408) 943-2600. [] Xilinx San Jose, CA. (408) 559-7778. []

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Advances in Small Form Factors

Introducing the FeaturePak Embedded I/O Expansion Standard Tiny, low-profile I/O expansion modules target size, flexibility and space constraints of COM baseboards, SBCs and silicon vendor reference designs.

by Jonathan Miller and Rick Lehrbaum, Diamond Systems


orn in the early ’90s with the advent of PC/104, the “stackable single board computer” market rapidly evolved into a thriving global ecosystem. Two decades later, PC/104—joined by a handful of stackable descendents such as PC/104-Plus, PCI-104, PCI/104-Express and SUMIT-ISM—remains in widespread Despitenow the many successes of stacknies providing able-SBCs, theWhether cost and funcon into products, technologieshowever, and companies. your goal is to research the latest of high-volume tion Engineer,tionality or jump to constraints a company's technical page, the goalprodof Get Connected is to put you you require for whatever of technology, ucts havetype tended to dictate full-custom and productsdesigns, you are searching for. with high development complete costs and risks. In an effort to move off-the-shelf boards into high-volume opportunities, JUMPtec (now part of Kontron) in 2000 introduced a new concept, dubbed ETX. The company’s Figure 1 ETX boards integrated a full set of embedded-PC functions within a compact “comThe FeaturePak board dimensions are smaller than a credit card and use a puter-on-module” (COM), which plugged 230-pin edge connector. into a custom application baseboard through a pair of high-density connectors. This effectively transferred the bur- soon joined by ETX Express (aka COM den of I/O and power connectors—plus Express), XTX, Qseven and several other Get Connected additional, application-specific func- COM standards. The resulting COM with companies mentioned in this article. tionality—to the custom baseboard. The market’s annual revenues are projected COM approach caught on, with ETX to surpass those of the stackable-SBC

End of Article


Get Connected with companies mentioned in this article. APRIL 2010 RTC MAGAZINE

technology in context

market by the end of this year, according to a recent report from Electronic Trend Publications. Interestingly, despite the success of COMs, it took a full decade for the other shoe to drop—namely, “I/O on modules.” Although PC/104-style stackable I/O modules had evolved to encompass new buses and I/O technologies, the COM market’s emergence dictated the need for a smaller, lower-profile, mezzanine-style I/O expansion format more suitable to the needs COM-based systems. It was this unfulfilled need that led to the development of the proposed FeaturePak embedded I/O modules standard.



Low-cost MXM connector

Introducing the FeaturePak Standard

In March 2010, a group of eight companies debuted an innovative new I/O-on-module concept at the Embedded World 2010 trade show. The FeaturePak standard defines a highly compact, low-profile and inexpensive I/O-on-module format measuring 1.70 x 2.55 inches (43 x 65 mm)—about three-fifths the size of a credit card (Figure 1). FeaturePak modules can be used for providing snap-in options or upgrades to both SBCs and COM baseboards. They can also provide building blocks for simplifying the development of custom embedded electronics. The FeaturePak form-factor might also catch on as a consistent format for silicon vendors’ I/O controller evaluation boards and reference designs, instead of today’s hodgepodge of I/O controller evaluation boards. The mezzanine-style FeaturePak standard is highly synergistic with existing and emerging bus, I/O, chip and board-level technologies. It leverages the latest high-speed serial expansion standards—such as PCI Express and USB— and is compatible with a wide range of current and future processors, including both x86 and RISC architectures. A summary of features and benefits is shown in Table 1.

PCI-104 Connector

Low-cost MXM connector

PCIe/104 Connector

Figure 2 FeaturePak on stackable SUMIT-ISM and PCI/104-Express modules.



technology in context

module formats • Stackable expansion modules such as the PCI/104-Express and SUMITISM • Backplane expansion boards such as standard PCI Express cards • Industrial slot-boards such as PICMG’s CompactPCI Express • Silicon vendor reference designs and evaluation boards • Set-top boxes, intelligent transportation systems, medical devices, test equipment, etc.

COM Express Module

FeaturePak Module

Low-cost MXM connector






Figure 3

FeaturePak Connector Signals

FeaturePak on a COM Express baseboard.

Qseven Module

FeaturePak Module

Low-cost MXM connector

Low-cost MXM connector





Figure 4 FeaturePak on a Qseven COM baseboard.

How FeaturePak Modules Can Be Used

With their compact size and standardized connector, FeaturePak modules are easy-to-use macrocomponents that target a wide range of embedded applications. Embedded computer design can be greatly simplified by treating complex I/O subsystems as components, just as various types of COMs allow designers to treat the core embedded computing functions as a



Figures 2 through 5 suggest a few anticipated FeaturePak applications. The red lines indicate the host interface connections.

plug-in building block. This macrocomponent approach greatly accelerates design cycles, and also enables the creation of reconfigurable and upgradable products. A few places where FeaturePak expansion would be beneficial include: • Single board computer form factors such as EBX, EPIC, 3.5-inch, MiniITX, Nano-ITX, etc. • Application baseboards for COM Express, Qseven and other computer-on-

All of the FeaturePak module’s bus and I/O signals appear on a single, highdensity, 230-pin card-edge connector. The module inserts into the connector at an angle and then swings down to lie parallel to the host PCB, after which it’s secured with two screws. The use of a single low-cost connector plus gold fingers on the FeaturePak module results in the lowest possible cost for a mezzanine board interconnect solution. The socket’s MXM connector is rated for 2.5 Gbit/s operation, fast enough for PCI Express and various high-speed I/O interfaces, including USB 2.0 and Gigabit Ethernet. In comparison with the venerable stackable PC/104 module and socket, the FeaturePak module is about 1/3rd the size of a PC/104 module, and its socket provides 220% of the signal density in 85% of the board space. Additionally, the FeaturePak socket is lower profile, at 0.31 inch (7.8 mm) vs. 0.43 inch (11 mm) for PC/104’s. All connections—including power, host interface and external I/O—are carried by the single low-cost, high-density, 230-pin MXM connector, originally designed for use with notebook computer graphics modules. Incidentally, the FeaturePak standard utilizes the 230-pin MXM connector differently from the way it is used by the MXM graphics standard, as well as from

technology in context

other standards that employ MXM connectors, such as Qseven COMs.

Height Considerations

Although MXM connectors are available with several board-to-board heights, FeaturePak sockets use the MXM connector options that provide 0.2 inch (5.0 mm) spacing between the bottom of the FeaturePak module and the top surface of the baseboard. Allowed component thicknesses on the top and bottom of FeaturePak modules vary according to two types of modules—“Standard” and “Tall”—as well as by regions on the top and bottom surfaces. The maximum topside component thickness on a Standard FeaturePak module is 0.19 inch (4.8 mm), while that on a Tall module is 0.4 inch (10 mm). The Standard height module in a FeaturePak socket on a baseboard can have a PC/104 or similar stacking board with 0.6 inch board-to-board spacing installed above it. Many FeaturePak applications will not require this restriction. The bottom surface of either type FeaturePak module supports maximum component heights of 2 mm or 3 mm, depending on location. Details are provided in the FeaturePak Specification and Design Guide.

The FeaturePak connector interface signals are illustrated in Figure 6. Two frequently asked questions regarding the FeaturePak connector’s signal

PCI-104 Connector FeaturePak Module



Low-cost MXM connector IDE


PCIe-104 Connector






Figure 5 FeaturePak on an EPIC Express SBC.

FeaturePak Signal Groups

All of the FeaturePak module’s host and external I/O interface and power connections are carried by a single low-cost, high-density, 230-pin connector. These signals consist of the following: • Host interface – includes 2 PCI Express x1 links, 2 USB (1.1 or 2.0) channels, 1 serial port (TX, RX, RTS, CTS), SMBus, reset, JTAG, auxiliary signals, a slot ID, +3.3V, +12V and ground. • Primary I/O signal group – includes 50 I/O signals, +5V and ground. Within this group, 34 signal pairs are implemented with enhanced isolation for use in applications such as highprecision analog, Ethernet and optically isolated I/O. • Secondary I/O signal group – includes 50 general-purpose I/O signals, +5V and ground.

assignment are: How are the two groups of 50 I/O signals intended to be used? And why are power and ground pins not included in the two 50-line I/O signal groups?


Host Interface

User Interface


I/O Connector 50 pins

I/O Connector 50 pins

(2) PCIe x1 (2) USB (1) Serial SMBus Reset, Misc. JTAG +5V +3.3V Ground Reserved

N/C for I/O signal isolation

13 5 4 3 7 4 5 8 21 26

MXM Connector 230 Pins

50 34


Figure 6 All connections, including host interface, user I/O ground and power, are carried by the 230-pin MXM connector. The user I/O is organized in two 50-pin groups.



technology in context

Vibration Profile Random Vibration Spectrum Frequency (Hz) Amplitude 20

0.01 g2/Hz

20 to 80

+3 dB/Octave

80 to 350 350 to 2000 2000

0.01 g2/Hz

FeaturePak Features • Compact, low-profile form factor — three-fifths the size of a credit card and one-third the size of a PC/104 module! • Single low-cost connector integrates all host and external I/O interfaces • Provides up to 100 I/O points per module • Leverages industry-standard buses such as PCIe, USB and I2C • Host processor and form factor agnostic • Coexists with PC/104, SUMIT, Qseven, ETX, XTX, COM Express, etc. • Multiple FeaturePak modules may be present within one system • Open industry standard • Rugged and reliable

+3 dB/Octave 0.007 g2/Hz

Overall acceleration = 6.07 GRMS Vibration duration = 10 minutes Note: This Random Vibration Profile conforms to MIL-STD-78ID Task 401 Figure 401-1 PM426-48

FeaturePak Benefits



92/Hz 10-1


6 18


24 30


36 42

10-4 10-5






Vibration Profile A. Random Vibration Spectrum TEST TOLERANCES The test tolerances shall be as follows: Frequency Greater of +2% or +1Hz Equalization and analysis bandwidth ≤25 Hz Acceleration spectral density +3 dB Overall acceleration +10% Duration +10, -0% Figure 7 Results of shock and vibration testing of FastPak module.

The answer to both these questions is that these two 50-line groups on the FeaturePak’s MXM connector were intentionally left unspecified in order to maximize FeaturePak flexibility. Letting each FeaturePak define its 100 external interface lines broadens the range of applications that can be supported. Power and ground can be assigned to as many lines as required, in a card-specific manner. This lack of specificity in the initial FeaturePak standard does not preclude



the possibility of developing multiple market- or application-specific external interface “profiles” in the future, however. FeaturePak modules operate on 3.3V, although they may optionally use 5V power for auxiliary functions (depending on the specific FeaturePak module). All logic levels are implemented with standard 3.3V signaling. Based on the MXM connector’s maximum per-pin current rating of 0.5A and the number of defined power pins on the

• Shortens time-to-market • Reduces board-level development costs and risks • Simplifies system design • Eliminates cables, resulting in higher reliability, lower cost and faster assembly • Enables scalable and reconfigurable system design • Enables easy product upgrades • Protects from component obsolescence • Encapsulates intellectual property • Suitable for SBCs, baseboards and proprietary allin-one hardware designs • Ideal for rapid-prototyping through high-volume applications • Ideal format for silicon vendor reference designs • Open standard increases market acceptance

TABLE 1 Key features and benefits of FeaturePak.

FeaturePak interface, maximum FeaturePak module power consumption is 12W from its 3.3V inputs. Additionally, up to 15W of power can be supplied to a FeaturePak via its optional 5V inputs. The connector’s +12V interface pin is not intended for powering the module.

FeaturePak vs. FeaturePak USB Sockets

The FeaturePak standard defines two types of FeaturePak sockets: “FeaturePak” and “FeaturePak USB.” Each requires a minimum set of functions to be implemented, in order to ensure interchangeability with the open market of FeaturePak modules. The only difference between the two is the minimum number of PCI Express and USB links. The minimum set of functions that must be provided by each type of FeaturePak socket appears in Table 2.

technology in context

FeaturePak modules, on the other hand, are allowed to implement subsets of the host interface signals, although a future release of the FeaturePak Specification may define certain minimum requirements. Thus, a FeaturePak module may communicate with the host board via any combination of PCI Express, USB and serial interfaces. All subsets of these interfaces are permitted—resulting, for example, in possibilities such as a USBinterfaced serial expansion module, a serial-interfaced GPS module, or a PCI Express-interfaced Ethernet switch or video frame grabber.

How Rugged Is It?

Another question often asked is: “How rugged is this standard?” or “Aren’t miniature card-edge finger contacts (230 contacts on 0.5 mm pitch) unreliable?” With questions like this in mind, Diamond subjected the FeaturePak card and connector design to shock/vibration testing. The company reports that the form factor and its connector successfully passed random vibration testing up to 6.07 Grms over 20 Hz through 2000 Hz in 3 axes, according to MIL-STD781D Task 401. Refer to Figure 7 for the test profile used. After more than two decades, stackable single board computers (SBCs)

Untitled-3 1

Function supplied to FeaturePak Socket

Must be provided by “FeaturePak” compliant host sockets

Must be provided by “FeaturePak USB” compliant host sockets

+3.3 VDC power

2A, minimum

2A, minimum

+5 VDC power

1A, minimum

1A, minimum

PCI Express x1 lanes



USB 1.1 or 2.0 ports



Serial port



PCI Express reset



Slot ID



TABLE 2 Comparison between “FeaturePak” and “FeaturePak USB.”

are firmly established as a cornerstone of embedded system design. However, SBCs often are left out of high-volume opportunities due to cost, feature, or spatial constraints. A more recent approach—the boardlevel computer-on-module (COM)— appears to be making better headway in high-volume applications, evidenced by projections that COM market sales are likely to overtake those of stackable-SBCs this year. With the success of COMs has come an opportunity for similarly packaged I/O function blocks—what might be termed “I/O-onmodules.” The proposed FeaturePak embedded I/O expansion standard, introduced in March 2010 at the Embedded World trade show in Nuremberg, introduces a

compact, low-cost and flexible I/O-onmodule format that’s well suited to a wide range of embedded applications, including applications based on stackableSBCs, COM baseboards and full-custom electronic designs. Diamond Systems Mountain View, CA. (408) 810-2500. []. [].


3:45:15 PM RTC MAGAZINE 11/11/09 APRIL 2010

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Advances in Small Form Factors

Bigger Jobs in the Same Space The increase in CPU power, memory and interconnect bandwidth in step with Moore’s Law and implemented as PCIe/104, continues to multiply the computing power within the PC/104 form factor. And this one still has room to grow. by Martin Mayer, Advanced Digital Logic


he PC/104 envelope continues to benefit from Moore’s Law, as CPU performance has reached a new plateau of 20 GIPS starting with Intel’s T7400 CPU and continued with the SP9300. Feeding such a powerhouse requires fast memory, and with DDR3, over 5.7 Gbyte/s of memory bandwidth is available to support compute-intensive floating-point and integer tasks while simultaneously pumping 180 Mbyte/s out the video port. While such an arrangement may be ideal for parallel computation on large arrayssolutions of numbers, nies providing now ray tracing, animation, Figure 1 gaming and fractal generation, none of ion into products, technologies and companies. Whether your goal is to research the latest these tasks are coretechnical to embedded ation Engineer, or jump to a company's page, the applicagoal of Get Connected is tocubes put you offer a visual These you require for whatever typethrive of technology, tions, which on data collection and impression of the data in and productsprocessing. you are searching for. Networks of sensors or direct Table 1 as a function of CPU performance, bus bandwidth and image processing of digital camera feeds memory. are but two bandwidth-intensive applications that are served by the introduction of PCI Express into the PC/104 embedded in the PC/104 embedded space increases space. These limited physical-volume sys- I/O bandwidth and throughput, expandtems may now address the challenges of ing the realm of applications that may be sipping gently from a fire hose. addressed by modular PC/104-based sysPCIe provides the local data highway tems. Modularity permits the PC/104 emnecessary to connect high-bandwidth pe- bedded space to morph and tailor the peripherals to multicore CPU systems. PCIe ripheral mix to suit the application, while providing the infrastructure necessary to sustain multiple product offerings and exGet Connected with companies mentioned in this article. panded performance levels in the future. As more processing power is brought to

ploration your goal k directly age, the source. ology, d products

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APRIL 2010 RTC MAGAZINE Get Connected with companies mentioned in this article.

bear on the flood of I/O data delivered via PCI Express, new embedded applications in high-definition video, signal processing, high-volume upper tier data communications, management and encryption are beginning to emerge. The serialization of the PCI bus into the Express variant changes the fundamental topology from a multipoint simplex bus to a dedicated star, which permits simultaneous full-duplex communication to each endpoint. Capable of driving up to six endpoint peripherals, PCIe/104 is composed of four x1 lanes at 250 Mbyte/s, and a multi-lane portion that typically drives a single x16 endpoint at 4 Gbyte/s, two x8 endpoints at 2 Gbyte/s or two x4 endpoints at 1 Gbyte/s. Using dedicated transmit and receive signal paths, PCI Express leaps forward as a communications bus. Bandwidth capabilities suggest that a single PCIe/104 CPU could handle the task of inserting selective security into a full speed OC-192 data link. Similarly, a suitably fast CPU and memory could multiplex and demultiplex eight Gigabit Ethernet links into an OC-192 data link, again, adding value within the stream. The x16 Express interface offered by PCIe/104 was originally devised as a highbandwidth interconnect for an external

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technology in context


































TABLE 1 Numerical representation of Figure 1. Note that the cube root column for the PCIe system shows there is still room to grow to a potential of around 6200 before the PCIe interconnect fabric is saturated. Synergistic Frequency Reduction Cores


32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 -0

Core Frequency (MHz)

2250 2000 1750 1500 1250 1000 750 500 250 0 18









2Y Cores



Moore Cycle

Figure 2 The synergistic effect on clock frequency caused by adding CPU cores while continuing to advance through future Moore cycles.

graphics processor. Emergence of the Compute Unified Device Architecture (CUDA) has tasked graphics processors with alternate roles as vector processors and physics engines. Market requests indicate some desire to exploit this functionality, which waits only for the development of silicon capable of meeting the rigorous environmental characteristics of the PC/104 embedded space. Adaptation of existing x4, x8 and x16 PCI Express designs are currently being driven by new market demand. Ultra definition and high-speed image capture are two applications that can leverage 4 Gbyte/s x16 interface, as inputs to the system rather than outputs. The increased signal processing power of the SSE4 instruction set makes compression and signal processing tasks much easier to handle “in-core” as opposed to designing specialized hardware specifically for these tasks. When coupled with sufficient processor and memory resources, sometimes referred to as the processing footprint, the I/O bus can be graphed in a third dimension to express the computational volume



of a system. With memory represented in the diagonal Z-dimension, Figure 1 compares current bus champions, for ISA, PCI and PCIe. I/O bus bandwidth is vertical and processor speed is horizontal. The smallest shape represents a 133 MHz Elan SC520, 128 Mbyte SDRAM, PC/104 CPU. The medium is a 1.8 GHz Pentium-M, 1 Gbyte DDR, PCI/104 CPU. The large cube represents a 2.26 GHz Intel SP9300 Core 2 Duo, 4 Gbyte DDR-3, PCIe/104 CPU. All of the CPUs chosen have the ability to execute one or more instructions per clock cycle, making their integer performance meet or exceed the CPU clock frequency. Note that the shape of the PCI Express computational volume is more cubic than flat, wide and deep like the other two volumes. This is the first indication that the combination of bus, CPU and memory has not reached the bus maximum. With PCI Express, total memory bandwidth must exceed four times the total bus bandwidth before full-duplex store-and-forward operation can maximize bus utilization. Increasing the

memory bandwidth may require a wider and faster channel, and this is one of the fundamental architectural challenges that must be addressed before PCI Express, in even its basic form, is challenged to the fullest extent. The PCI Express bus is likely to remain useful for several Moore Cycles past saturation. Technical limitations of the PCIe/104 implementation will hold the current perlane data rate at its current level, as the increased bandwidth of second-generation PCI signaling will cross the boundaries of reliability on some systems. Knowing when the next I/O interconnect solution must be deployed becomes critical to the continued longevity of the physical PC/104 envelope. The cubes in Figure 1 represent Moore Volumes, which are the product of CPU Frequency (MHz), memory size (Mbyte) and bus bandwidth (Mbyte/s-1). One MMv has the implicit units of MHzB2s-1. It should be noted that a system of 1 MHz by 1 Mbyte/s by 1 Mbyte, such as the IBM PC/XT would have a rating of 1 MMv. It is worth noting that the base10 bus speeds were converted to MiB, so that a correct Moore Volume is computed. This preserves the scale implied by the fundamental HzB2s-1 unit. Table 1 reveals the dimensions of the three cubes. The first two rows are for the saturated volumes, and we see that there is a rough factor of 10 in the cube-root of the Moore Volumes, and an increase of 10 in the base-2 logarithm of the Moore Volume. For the cube root column, we would expect the PCIe generation to have a number on the order of 6200, revealing that this number can grow. Likewise, the log2 column seems to suggest that 1.5 more cycles remain before saturation. While the length of a Moore Cycle is no longer fixed at 18 months, the log2 column still shows that ten doublings of Moore Volume occur between new bus saturations in PC/104. Considering that there were many Moore cycles that occurred before the PC/XT, it is reasonable to class these shifts in I/O paradigm as occurring every Moore Decade. There is considerable overlap from one bus to the next, as two stackable buses at most are currently supported on a PC/104 CPU. This says nothing of other ubiqui-

technology in context

tous I/O offerings that bristle on various connectors. With Mega-Moore generations 18 and 28 completed, we are currently racing toward the completion of generation 38, which is witnessing the vast deployment of multicore CPUs. Many studies have been performed on twin-core units, showing that many applications can be unrolled and paralleled to nearly double the performance. Of course, we know that there are limits to synergistic processing, rendering the simple product of cores and clock frequency less than useful for more than about 4 cores. It can be predicted that a quad core system operating at a nominal 2.5 GHz with 8 Gbytes of system memory will be able to saturate the existing PCIe/104 deployment, perhaps in the form of a realtime mobile Doppler weather-radar system with >12 km radius and a 3D display running at 1600x1200 resolution. Once memory bandwidth exceeds 16 Gbytes-1, the market will begin clamoring for a faster embedded bus and more cores. What will it take to satisfy such a voracious appetite? Imagining the 48th Moore Cycle and beyond, there is limited usefulness in expecting processes to be continuously splittable. However, this is not out of the question as the complexity of the tasks to be accomplished will continue to increase in response to available embedded system processing power. At the 48th Moore Cycle we may see full advance weather prediction, with HD-3D display, running an advanced WRF 24 km weather model, fed by the previous generation’s radar unit hanging off of a USB-3 port. To apply continued downward pressure on core clock rates, the number of processor cores per CPU must increase 16-fold every 10 Moore Cycles in order to saturate the next-generation interconnect fabric. Given this explosive rate, one might be inclined to look at each process as a vector that is at a right-angle to another vector, with the result being a mutual vector with a magnitude of √2 , representing an average synergistic effect of each new processor core added to the CPU. Figure 2 expresses this possible future. Note that the secondary Y-axis is logarithmic, with the maximum value

representing 230 cores in a single processing unit. Memory and bus bandwidth must grow to feed a billion core unit. Table 2 lists upper bound values for each decade in Figure 2. While only time will answer the precise I/O bandwidth beyond the 38th Moore Cycle, the expectation that bus speed continues to advance 10x for each new bus may prove different than what is predicted. Many other I/O solutions may

as to when, if ever, it may achieve a density that permits it to serve in the confines of the PC/104 embedded space. As we focus on the tasks necessary to finalize the transition into the age of the Giga-Moore, and wonder what innovations will bring the 48th Moore Cycle to fruition, there is certainly no schedule implied in this application of Moore’s Law and the concept of the computational volume. Rather, milestones are indicated,

Historical Comparisons for Perspective 1) The Cray-3, which was implemented to ¼ of its designed capacity before being abandoned, was rumored to have run as a dual-core vector processor for some time after being decommissioned. The theoretical throughput of a 16-core Cray-3 was 15.17 GFLOPS. The Intel SP9300 CPU has been clocked in excess of 16 GFLOPS using SSE3 instructions and SiSandra 2007 and Windows XP-SP3. The Cray-3 consumed 88 kW in 1995 and was bath cooled in Freon. The 2010 PCI/104-Express SP9300 needs less than 30W and can be cooled radiatively, with no moving parts, at an ambient temperature of +85°C. 2) In a tight loop, the 6502 CPU could execute 250,000 instructions per second, with a more typical performance of 125,000 IPS. With an installed memory of 64 kB and a 1.023 MHz 2-phase clock, the I/O expansion bus would move 0.975 Mbytes-1. The computed Moore Volume for an Apple ][ with these specifications is 0.00762 MMv typical and 0.0152 MMv peak. Compared to the IBM PC/XT’s rating of 1MMv, the Apple ][ appears at -6.0356 to -7.0356 Moore Cycles. No. Cores

Moore cycle

No. Cores (Log2)

ƒ(Core) (MHz)

RAM Size

I/O Bandwidth





128 MB

12.7 MBs-1





1 GB

127 MBs-1





8 GB

4.66 GBs-1





64 GB

46.6 GBs-1





512 GB

466 GBs-1





4 TB

4.55 TBs-1





32 TB

45.5 TBs-1





256 TB

455 TBs-1





2 PB

4.44 PBs-1





16 PB

44.4 PBs-1

Moore Unit MMv




TABLE 2 Moore Volume Parameters: M, G, T and P correspond to 220, 230, 240 and 250 respectively.

be invented between now and then, yet the factor expressed in the table represents the minimum payload that must be delivered before a new I/O interconnect is considered for incorporation into the PC/104 embedded space. Equally tenuous is the rate of memory expansion. While it is certainly reasonable to expect that memory density will continue to increase, the question remains

and when, not if, they are reached, we will know that it is time to explore all that technology has to offer, selecting the best of breed to keep the PC/104 embedded space a growing and thriving ecosystem. Advanced Digital Logic San Diego, CA. (858) 490-0597. [].




connected USB and/or PCI Express?

PCIe? USB? Sorting Out Two COM / SFF Design Decisions Modern Computer-on-Module (COM) standards include multiple buses, either in a single connector or among several. Given these COMs’ plethora of bus interfacing options, which should your next design use? by John Hentges, ACCES I/O Products


mong all the bus types available in most COM specifications, only USB and PCI Express (PCIe) are well supported, high-level buses, with plug-and-play and excellent interoperability. A PCIe or USB design guarantees it will work with any vendor’s COM solution. Additionally, all of the current and up-and-coming COMs support both of these buses, letting you reuse your schematic and produce the same device for complementary—or competing— COM standards. Having the facts will make it easier to choose which bus to use in your next embedded peripheral design. PCIe and USB are each fully supplied with operating system level interfaces, both built into the OS and available from a variety of third parties. The buses are mature and well documented, down to the nitty gritty details of implementation for new peripherals. However, there remain real differences between them that will help you choose which bus is right for your new embedded peripheral.

Latency Provides the Most Contrast between USB and PCI Express

A single USB transaction takes at least 125 microseconds, and empiri-



USB vs PCI Express (PCIe)








Relative Cost, Effort, Bandwidth, and Latency







Figure 1 USB vs. PCI Express design variants.

cally usually consumes 250 microseconds, even in Linux. 125 microseconds is significant in computer-based systems, especially in the embedded

world where human input is often a smaller portion of the system’s total operation. This means USB takes longer to issue control events, like setting

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up a mode of operation, or polling for a status change. PCIe, on the other hand, can complete a single transaction in anywhere from a fraction of a microsecond to around two microseconds, depending on the system architecture. This low latency

Why Not LPC, SPI, or I2C? LPC, SPI and I2C are very low level and require customizing the COM unit or its BIOS to properly implement. This limitation is primarily due to these buses having been designed without “plug-and-play” in mind—all three were originally designed to connect various chips on a single PCB. As a result they are not very effective when designing an I/O module you intend on using with a variety of vendors’ COMs. For example, although COM-Express provides five I2C buses on its connector, the first four are dedicated to specific functions, and the fifth doesn’t have a common software interface standard, effectively negating vendor interoperability. Also, the LPC and I2C buses are very low bandwidth, further limiting their utility. These buses should be ruled out of consideration for most projects.

allows more control requests to be issued, or better timing to be achieved even when using relatively few requests. The difference in latency effectively means USB is less “real-time” than PCI Express. Many applications don’t need microsecond latencies, but only PCIe can deliver it when necessary. Do not confuse latency with bandwidth however. Both buses have real-world data rates in excess of 40 Mbyte/s. PCIe, however, can achieve speeds at least an order of magnitude greater than USB, theoretically as much as 250 Mbyte/s for a single PCIe lane. PCIe lanes can also be grouped (used in parallel.) You’re probably familiar with the 16x PCIe slots normally used for video cards. Grouping PCIe lanes can achieve a near linear increase in bandwidth while retaining the same low latency. PCIe, then, is both less latent and higher-bandwidth than USB even can be. So why should you even consider USB?



USB is easy and inexpensive to design. USB Bus interface chips are simple, relatively low pin-count devices, allowing fewer layers to be used in the design. USB 1.1 even supports two-layer boards! With only one signal pair to route, the designs are truly simple. Many USB Bus peripheral interface chips include a microcontroller. These chips provide sub-processors to handle the overhead of USB communication, and the busywork associated with things like streaming to an IDE device, or any FIFO you attach. This microcontroller implements the relatively high-level communication protocol you design. This lets you create designs quickly, at a low cost, and achieve incredible flexibility by modifying firmware instead of hardware. This firmware can be updated over the USB connection “insystem,” usually without the customers even noticing. Additionally, the USB interface chips are very low cost and have relatively few support chips required. This keeps the unit bill of materials (BoM) costs low, which keeps production costs down. PCI Express, on the other hand, is an expensive, involved, very high pin-count design. Dozens of high-speed differential signals may need to be routed, compared to a single pair for USB. PCIe designs also require more support components: often 3.3, 2.5 and 1.8 volt references are needed. Also, active PCIe signals are so fast (up to 8 GHz) that most silicon can’t accept the serial stream directly, and it must be processed by a special chip such as a PHY. The output of this device must be fed to an FPGA or other silicon to interpret. The PHY, the FPGA and the nonvolatile storage used to load the program for all the devices on board are often only available as BGA packaged devices. BGA requires advanced solder facilities, reduces serviceability, and usually requires at least six-layer designs, greatly increasing cost across the entire design and production cycle. A single FPGA-based PCI Express design may have three to five times the parts cost for the bus interface alone— completely excluding your circuitry!

When you factor in the increased PCB, assembly, and test costs, PCIe is truly an expensive proposition compared to USB. Even if you use a COTS PCIe-to-local bus bridge chip instead of FPGAs (greatly reducing your device’s flexibility), design and parts costs exceeds USB by a significant margin. Score one for USB for being easier and less expensive to design, and for its lower parts cost throughout. PCIe does bring some more ammunition to the battle: backward compatibility. PCIe devices can be compatible with existing “old-school” PCI or PCI-X devices. This compatibility is obviously not in the bus connector; they are radically different. Rather, the lowest level software that communicates with memory and registers on the peripheral is easy to make 99% compatible with any existing PCI device. You can usually reach 100% compatibility if you stretch a little. This low-level software communicates with the hardware through the “register map” and plug-and-play subsystems, and very few PCI designs are cross-compatible at this level. By designing your new peripheral to use the same register map as an existing PCI board, you can offer a low-cost migration path for customers dealing with the PCI end-of-life cycle; only the peripheral need change, the mission-critical software can remain identical despite the hardware upgrade. Your customers moving from a PC-104+-based embedded system can upgrade to a Pico-ITXe system using PicoIO peripherals—with radically different size and bus connectors—and neither you nor they should need to modify the application or driver software they are using. USB also provides some compatibility, but of a very different nature. USB devices have high-level interfaces; unlike PCI and PCIe devices with complex register maps and memory locations, USB is treated more as a collection of control functionality combined with a few highbandwidth streaming pipes. Instead of issuing a dozen or more assembly language OUT DX,AX instructions, you might issue a single usb_control_request(). This means USB is definitely not low-level compatible with any existing PCI device.

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Additionally, USB was—and is— designed with forward compatibility in mind: USB 2.0 controllers support USB 1.1 peripherals, and USB 1.1 hubs support USB 2.0 devices. You can even plug a USB 2.0 device into a USB 3.0 hub without losing any functionality! You certainly can’t plug a PCI device into a PCIe slot— if you could there wouldn’t be an end-oflife problem in the first place—which is really a great selling point for USB: USB devices aren’t likely to become obsolete simply due to bus changes. USB is very easy to future-proof; by designing a useful and flexible set of interface functions, all of your I/O designs can reuse the same high-level application or API, regardless of how many times you redesign the peripheral, or how many bits it handles. The high level application talks to a fairly high level control-request interface, and this control-request interface is shared among all of your USB devices. Whether the forward-looking compatibility of USB or the backward compatibility of PCIe is more important for your design depends on the nature of your requirement. You should consider PCIe as your first choice if you are replacing a PCI device your customers use, especially if you don’t have the resources to modify your software. USB, though, will prevent this compatibility cycle from being an issue the next time you upgrade your system, and allows much greater compatibility within a product generation due to the higher-level nature of the interface. So, the verdict is PCIe for compatibility with existing PCI products as summarized in Figure 1; USB for compatibility with multiple products in a single generation, and with products going forward. This multitude of pros and cons sums into several easy choices: 1) If you must have the speed of PCIe, your decision is easy, choose PCIe. 2) If you cannot modify the source code for an existing PCI-based embedded system or the customer’s software applications, or the expense of doing so is prohibitive, choose PCIe. 3) If cost of design and production is a primary concern, USB rules the day.

4) If your embedded device needs to support flexible peripheral options, USB virtually eliminates costs associated with swapping out I/O devices. Designers must understand and weigh the benefits of each bus type. Cost, effort, bandwidth, latency and compatibility are different factors to consider, and depend on specific application needs.

Untitled-1 1

New form factors are constantly being created, and ACCES will continue to develop products across the many bus types to target virtually every application. Explore the possibilities! ACCES I/O Products San Diego, CA. (858) 550-9559. [].


2:54:26 PM RTC MAGAZINE 3/19/10 APRIL 2010

ploration your goal k directly age, the source. ology, d products


connected USB and/or PCI Express?

USB and PCI Express: Advanced, Evolving Interconnects for Embedded Systems What are the attributes of PCIe and USB that should be considered by designers in selecting an optimal interconnect in embedded designs for the applications they support? An overview of the technologies and their key features can help as a guide. by Akber Kazmi, PLX Technology


SB and PCI Express are two interconnect technologies that have created industry-wide appeal and a Volt reg strong presence in computer and consumer DAS electronics over the last two decades. During that time these technologies evolved Serial Fan XTAL in speed and functions to meet the needs Flash of the market, while maintaining backward compatibility with the previous generations in hardware and software. The nies providing solutions now evolving robustness of these technologies ion into products, technologies and companies. Whether your goal is to research Figure the latest1 isorattracting other industry segments, ation Engineer, jump to a company's technical page, the goal such of Get Connected is to put you USB in a DAS application. as whatever embedded systems, you require for type of technology,to utilize them and and productstake you are searching for. advantage of the their broad availability and lower cost due to economies port higher speeds of 480 Mbit/s that enof scale. abled a plethora of applications for fast data transfer and storage. Today, you see USB 3.0 – SuperSpeed USB USB 2.0 camcorders, external disk drives, USB technology has made significant SSD thumb drives, digital cameras, printprogress since its introduction back in ers, network adapters, and a wide range 1995 as a simple plug-and-play mouse and of other consumer-focused applications. keyboard interface. Commonly known USB is a key enabler of the digital revoluas USB 1.0, it runs at 1.2-12 Mbit/s. In tion in consumer electronics. early 2000, USB 2.0 was defined to supAs new bandwidth-demanding applications such as video players and highspeed disk drives started using USB 2.0, Get Connected with companies mentioned in this article. I/O became a bottleneck, so a new sion, USB 3.0, was developed. Also known

End of Article


APRIL 2010 RTC MAGAZINE Get Connected with companies mentioned in this article.

RAID 0 RAID 1 Spanned JBOD

as SuperSpeed USB and introduced in 2008, it enables a whopping tenfold improvement over USB 2.0, while running at 5 Gbit/s. In addition to the 10x speed over the previous version, USB 3.0 offers additional capabilities such as increased bus power, power management and explicit packet routing. Table 1 highlights the key differences. Delivering on its plug-and-play and ease-of-use promises, the connectors for USB 3.0 are backward compatible with USB 2.0. Although the connectors are compatible, in actuality they differ, as

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Flash (8 or 16-bit) (1MB)


Print Server PCIe

SATA Ethernet PHY


Memory DDR2 x16




Figure 2 USB in a NAS application. CPU Camera Camera




Camera CPU

PEX 8505

Control Processor

Camera Camera




PEX 8311

Camera Figure 3 PCIe in a video surveillance application.

USB 3.0 requires additional signals to support duplex high-speed communication and power. There are some limitations on USB 3.0 cable length compared to previous versions, as signaling rates are much higher. Although x86 CPU makers have yet to introduce chips that support USB 3.0, several other vendors have introduced products and are shipping them in large volumes. With its speed, new features and availability of silicon, USB 3.0 will



deliver unprecedented I/O speed to applications such as embedded systems, hard drives, high-definition video, high-resolution cameras and multi-channel audio. Additionally, advanced storage applications such as DAS and NAS (Figures 1 and 2) are emerging that maximize USB 3.0’s performance.

PCI Express

PCI Express (PCIe) was introduced when the performance and capabilities of

the parallel PCI bus peaked at 64-bit, 133 MHz. PCIe represents a dramatic extension of the PCI bus. It is a serial, pointto-point interconnect technology. PCIe has gone through its evolution from 2.5 Gbit/s to 8 Gbit/s signaling rates and to advanced features to meet the needs of embedded, graphics, storage and communication applications. While evolving in speeds and features as USB has, PCIe also maintained backward compatibility with earlier generations in three areas key to embedded designs: software stack, form factor and protocol. Table 2 highlights the differences between PCIe 2.0 and 3.0. Devices based on PCIe 3.0, at 8 Gbit/s, are expected to release later this year. Like USB, PCIe is addressing the needs of an ever-increasing number of industry segments—some highly anticipated, others less so. In these applications, it provides scalable bandwidth between the CPU and I/Os in servers; matches the SAS/SATA and Fibre Channel (FC) data rates in storage; provides high-speed links to control or packet processors in communication; links real-time audio/video processors in consumer applications; and facilitates high-bandwidth serial links in many embedded applications. Rackmount and blade servers: These high-end applications would fall in one of two classes—rackmount server or blade server. Graphics: This application is the key driver of PCIe technology, as it has brought economies of scale to reduce the cost of components. Video gaming, for one, has been growing by leaps and bounds, and graphics chip vendors are providing cutting-edge performance through high-resolution graphics-processing units (GPUs). Video distribution: Multiple-monitor computing enabled by PCIe is a major trend that increases productivity and enhances capability in desktop publishing, CAD, CAM, CAID, financial analysis, stock trading, software development, simulation and animation. Storage systems: PCIe provides the connectivity between the storage interfaces, such as FC, SCSI and SATA, and the processors that control or manage the storage system. Industrial/embedded: PCIe technology is being adopted by many standards

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bodies in the industrial and embedded spaces, such as the advanced telecom, MicroTCA systems and AMC specifications. PCIe switches from companies such as PLX Technology are being used to connect embedded and network processors, as most of them are designed with PCIe interfaces integrated. Security systems: With numerous high-resolution cameras comes an extensive need for increased bandwidth and throughput in the systems. For example, a frame-grabber board takes video images from the cameras, processes them locally and feeds them info to the host for analysis and action (Figure 3). DVR cards and TV tuners: Digital video recorder (DVR) cards ship with a conventional PCI interface. However, because PCI slots are being eliminated and replaced with PCIe, next-generation DVR cards will be available with the PCIe interface.

How Do They Compare?

A quick comparison of PCIe 2.0 and USB 3.0 shows an array of similarities that impact embedded systems and other applications. Peer-to-peer communication: USB hubs will support multiple end-devices, but these end-devices will not be able to send traffic directly to each other. PCIe switches support peer-to-peer communication. Once configured by the host, enddevices can directly communicate with each other. However, one must be careful when choosing the switch vendor, as some vendors require CPU support in peer-topeer communication. Cable: Cables and connectors for USB have provided an excellent migration path from one generation to the other. USB’s high volume due to the heavy use in consumer electronics has yielded very low cost for the connectors and cables for all USB generations. In the case of PCIe, cable and connector development has been slow due to various non-technology reasons. As a result, the PCIe Gen 1 cable spec took too long to develop and the spec is so complex that after several years the cost of the cable and connectors is prohibitively high. Although PCI Gen 2 has been around since early 2007, the cable


USB 2.0

USB 3.0

Data Rate

12 Mb/s & 480 Mb/s

5.0 Mb/s

Data Interface

Half duplex, diff-pair

Dual-Simplex, 2 diff-pairs


Host directed, Packet broadcast

Host directed, Packets routed

Bus power

Low/high bus power

50-80% increase from 2.0

TABLE 1 USB 2.0 compared to USB 3.0


PCIe Gen 2

PCIe Gen 3

Signaling Rate

5 Gb/s

8 Gb/s

Data Rate

4 Gb/s

7.9 Gb/s

Data Interface

Full duplex, diff-pair

Full duplex, diff-pair


Host directed, peer-to-peer

Same as Gen 2

Bus power

Over 100 watts

Over 100 watts

Protocol enhancements

r2.1 extension


TABLE 2 PCIe Gen 2 compared to PCIe Gen 3.

specification for this generation is not complete yet. This has caused vendors to either stay away from PCIe or design proprietary connectors and cables to serve their needs. Bandwidth: USB 3.0 runs at 5 Gbit/s and provides 4.8 Gbit/s data bandwidth simultaneously in both directions, which makes it very attractive for a lot of consumer and embedded applications. PCIe Gen 3 runs at 8 Gbit/s effectively providing 7.9 Gbit/s after encoding, and PCIe Gen 2 runs at 5 Gbit/s, providing 4 Gbit/s data bandwidth after encoding overhead. PCIe not only has raw bandwidth advantage over USB, but it also allows scaling of this bandwidth up to 16-fold by combining sixteen PCIe lanes into one data pipe (port). These increments could be x2, x4, x8 and x16. Quality of service: USB does not offer any quality of service and it is not needed in most applications that it serves. PCIe supports quality of service through multiple virtual channels, port arbitration and traffic classes. Embedded applications can take advantage of this feature. Error recovery: USB does not offer any error recovery mechanism from link failures. PCIe supports positive acknowledgement of data packets moving between devices and retransmits in case of errors. PCIe also supports reducing the port

width and/or speed of the link if too many line errors are observed. Power management: USB supports some level of power management. PCIe supports exhaustive device, link and system-level power management features. Protocol enhancements: Some protocol enhancements have been made in USB 3.0 to support address-based routing of packets instead of broadcasting through USB hubs. The PCI-SIG has developed an exhaustive list of protocol enhancements (as discussed above) to enable system designers to enhance performance and manage power consumption. Both PCIe and USB are highly valuable technologies for embedded-system developers. USB is very useful in connecting to peripherals over a low-cost cable and connector combo and is available everywhere. Unfortunately, it does not scale beyond a 4.8 Gbit/s data pipe. PCIe offers a low-cost connectivity alternative in many embedded applications. PCIe scales well to support high-bandwidth applications and offers various enhancements compared to a simple data pipe like Ethernet. PLX Technology Sunnyvale, CA. (408) 774-9060. [].



technology in


Marrying COMs and Carriers

Designing for Performance and Longevity: COMs with Carrier Boards COMs help forward-thinking designers prepare for longevity and increased performance through module upgrades. Planning ahead to accommodate increased performance, reduction of device size and added features means designers will avoid design surprises in leveraging the long-term advantages of COM-based design. by Christine Van De Graaf, Kontron


omputer-on-Modules (COMs) are uniquely positioned for scalable, space-constrained designs—particularly those that benefit both economically and competitively from customization that can last for multiple generations of a given application. Since COMs integrate the complex CPU architecture and circuitry onto a single small form factor module—some as small as 84 mm x 55 mm—designers can focus on using their skills and experience in the development of the application itself. A primary advantage of COMs-based design is that all the application-specific hardware customization is designed into the module’s carrier board rather than the module. So when additional computing power or improved energy efficiency is required by the application, the COM can be quickly and easily replaced with one that meets the appropriate performance and power requirements. The standards-based module, which works in conjunction with the customized carrier board, connects all the peripherals and I/O in a consistent manner and can be switched out for any number of performance enhancements. The result is a nearly complete computer mounted on a carrier board, a design concept being implemented into a vast array of embedded



applications such as POS systems, industrial equipment, medical devices, rail and transportation systems. Customization and the transition from generation to generation are simplified with this platform. However, designers need to be aware of pitfalls or design gaps that must be addressed as they port software from one COM to another, or shift from legacy to next-generation COM product families. With some forward thinking and planning for future generations of the device or application, designers can avoid any surprises or “gotchas” that go along with upgrading designs for added features or increased performance.

Avoiding the Gotchas

Planning for scalability across the full range of the COM Express specification may require attention in first-generation designs, including anticipating the need for smaller device size, improved thermal characteristics and increased performance. Overall, important design elements such as pin-out types, module size, software and interface compatibility, and which designs require a new carrier board or updated processor, become critical considerations. To add new functionality to a COMsbased design, implemented controls may

be required for native support of specific features such as new display integration, higher performance graphics capabilities and increased security (Table 1). Cores can be upgraded within a product family (e.g., COM Express module to COM Express module), or the design can be upgraded within the COM specification. Moving from legacy technology such as ETX into more current I/Os and interfaces found in COM Express does not require a core CPU module change, but an actual swap of the COMs technology implemented. These designs do require a new carrier board, although similarities to the ETX layout allow designers to incorporate existing compatible software technology. Pin-out types must be considered; currently there are five pin-outs defined under the COM Express specification. To maintain the same carrier board with an upgraded COM module, designers must work with the same pin-out with any new module as well. For example, an ETX carrier board is not compatible with XTX modules because of its alternate pin-out definition. Module size may also be an important consideration, particularly with a first-generation design. If the earliest design allows only enough room for a carrier compatible to the nanoETXexpress (the

tech in systems

Figure 1

Figure 2

The Kontron microETXexpress-PV module accelerates the development of ultra-low-power embedded applications. The microETXexpress-PV also is a drop-in replacement for Intel Pentium M-based designs.

Designed today for use in extreme conditions, COMs offer industrial temperature ranges of -40° to +85°C as well as the necessary tolerances for high reliability in terms of shock and vibration resistance.

smallest “ultra” form factor), the application may not be scalable across the specification or able to take advantage of any modules in the compact or basic sizes. Features such as native support for VGA or SATA/PATA may require control implemented on either the module or the carrier board if the processor does not offer that feature (i.e., eMenlow). Depending on the processor/chipset, PCIe may even be required to bring out Ethernet or other features, ultimately reducing the number of available PCIe slots for the carrier board to use with add-ons such as PCIe graphics cards. Second-generation Atom technology has impact here as well, with COMs such as the microETXexpress-PV (Figure 1) incorporating the dual-core Intel Atom D510 processor (2x 1.66 GHz). This represents a performance jump (and an upgrade path) from the microETXexpress-SP based on the first-generation, single-core Intel Atom Z5XX series delivering from 1.1 GHz to 1.6 GHZ performance. The microETXexpress-PV also delivers native LVDS and VGA simultaneous graphics support as compared to its predecessor, which requires implementation of a VGA controller on the application-specific carrier board if the feature was needed.

Intel’s 32nm processor technology also has designers looking for upgrade paths. For example, the ETXexpress-AI offers designers greater flexibility due to its 32nm Intel Core i7/Core i5 processor technology, high energy efficiency, wide graphics support, customizable PCI Express configuration and ECC dual-channel RAM to ensure data accuracy. Both computing and high-end graphics performance are improved, enabling a performance jump from the ETXexpress-MC, designed for fourth-generation graphics architectures used in advanced video applications.

The COMs Revolution

In areas where reduction of device size is a key driver, for instance medical embedded design, COMs are leading significant growth as a design platform. Perhaps a diagnostic device once built onto a cart needs to be made even smaller and more portable, such as a battery-powered fist-held device that can be kept with the medical staff moving from patient to patient. COMs are wellsuited to evolve designs not only from medium-sized desktop or stationary devices to tablet-size applications and on toward smaller and smaller palm-sized ones—but also provide upgradability within a single product generation. Compute-intensive

imaging that previously required a much larger single board computer can now be managed effectively by a high-performance COM such as the ETXexpress-PC. With planning, even smaller footprints can be achieved using microETXexpress-PC modules based on the same chipset and CPU. Performance options are scalable, and designers can anticipate that future COMs, such as the recently introduced microETXexpress-XL (Figure 2), will provide even more options for sister devices that demand high resistance to shock and vibration while operating in extreme temperature conditions. Markets such as industrial control and transportation are likely to benefit from these advances, with robust COM Express-compatible modules offering a suitable match for designs that span an incredible range of varied end-use applications and the likelihood of multiple device generations. Train management and wayside systems, automatic piloting, interlocking and control center systems, as well as passenger information, onboard infotainment, tunnel safety and automated digital video surveillance are just some of the compute-intensive, high-availability technologies characterized by extreme conditions, round-the-clock performance and high-speed processing requirements. Overall, COMs show continued promise in low-power, ultra-mobile applications that require energy-saving x86 processor perfor-

COM Express Extension The Computer-on-Modules – Industrial Group (COM-IG) is working to improve the PICMG COM Express specification with the COM Express Extension. The extension will overcome gaps identified over the last ten years, including the addition of hardware and software definitions and interchangeability at the software level. Important extensions for hardware: • Form factor size ultra • Wide range of input power • SDIO usage of GPIO ports • Thermal control Important extensions for software: • TPM support and TCG 1.2 compliance • Smart Battery support • Legacy Super I/O support via LPC in BIOS For more, visit



Tech In Systems

MEN Micro’s Rugged COMs for Harsh Environments


ETX (95 mm x 114 mm); COM Express (125 mm x 95 mm, 95 mm x 95 mm, 84 mm x 55 mm)

Pin-Out Types

Types 1 through 5; applies only to COM Express compatible modules

Module Family

ETX with four connectors; COM Express with two connectors

Interface Compatibility

SATA, PATA. USB 2.0/3.0, etc. - same or different from generation to generation

Feature Support

Native vs. implemented controls

TABLE 1 Designers must consider several key areas to avoid surprises when upgrading a COMs-based design. Pin-out, module size and module family are crucial considerations, as well as software compatibility, evolving thermal characteristics and overall power and performance.

mance, high-end graphics, PCI Express and Serial ATA combined with longer battery life. This represents a broad slate of embedded design areas, including handheld devices for medical or multimedia applications, transportation infotainment systems, small mobile data systems and even new applications previously limited by size or power consumption.

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Untitled-1 1


3/31/10 11:02:09 AM

The COMs Evolution

A fixture on the embedded landscape for more than ten years now, COMs have come quite a long way in what they bring to the table. The COM Express standard has been critical to the evolution of smaller and smaller modules, at the same time offering the assurance of consistent physical layout, pin assignment and carrier board mounting holes. Currently the standard specifies module sizes in basic ETXexpress (125 mm x 95 mm), extended (155 mm x 110 mm) and compact microETXexpress (95 mm x 95 mm). The compact microETXexpress was driven by more recent 45nm chip technology, along with the newer ultra nanoETXexpress (84 mm x 55 mm), which is expected to be integrated in the PICMG standard shortly (see sidebar “COM Express Extension,” p. 35). Further, advanced processing technologies continue to change the game— offering breakthrough improvements in performance delivered and power saved. For instance, the 45nm Intel Atom processor architecture achieves fast performance (with clock speeds between 1.1 GHz and 1.6 GHz) in a sub 5-watt thermal power envelope. It features a power-optimized front side bus (of up to 533 MHz) for faster data transfer, in turn enabling development of

energy-saving, high-end graphics devices based on the Intel Atom processor and the Intel System Controller Hub US15W. Modules that integrate Intel Core i7 and 32nm processing advancements deliver even greater design flexibility, using an efficient two-chip solution for better signal integrity and minimized board space, in turn enabling higher performance for smaller, power-constrained portable designs. Intel Core i7 benefits such as new display integration, higher performance graphics capabilities and increased security features will continue to drive the COMs development path. Additional “by design” features are available today, such as high reliability in terms of shock and vibration tolerance, and performance in industrial temperature ranges of -40° to +85°C. As a result, designers are achieving greater performance in their designs, without leaving the safe and proven development path of COMs as an established and future-proof industry standard. The COM Express specification means design security, guaranteeing manufacturerindependent continuity and consistent availability across the larger range of manufacturing sources. With broad industry adoption among both suppliers and users, COMs enable faster time-to-market, reduced development cost and minimized design risk. The benefits reach into future generations as well—with simplified upgrade paths, scalability and increased application longevity. Kontron Poway, CA. (888) 294-4558. [].


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technology deployed

handle the raw data rates of the leading ADCs for various onboard data routing and handling requirements, but they also are providing ever increasing processing resources (above and beyond ADC data loads) for real-time data processing applications. Given the meteoric rise of FPGA processing resources in a relatively short period of time, the future answer to the question concerning the whereabouts of digitizer innovation or invention will likely come from the creative hands of FPGA logic designers. Table 1 shows the trend for 14-bit ADC sampling rate increases over the past decade. The devices selected were among the leading sampling rates for 14-bit ADCs at the time of their release. Notice that ADC sample data Incremental advances in electronic components no longer rate loads increased by about a factor of 4:1 over the course of seven to eight years. limit the potential for wideband data acquisition systems. Compare the ADC performance growth rate over this same period with the FPGA processing performance growth rate in Table 2, and it becomes quite evident that there is a large disparity in the rate of FPGA processby Anthony Hunt, Signatec ing resource growth versus the leading high dynamic range ADC data loads. Figure 1 is a graph that plots the performance factor values rior to the new millennium, skilled hardware engineers from the two tables relative to each other. pushed the technology envelope with inventive wideband digitizer designs leveraging an assortment of discrete logic FPGA Performance integrated circuits (ICs): counters, registers and simple programXilinx FPGAs were selected for the relative ADC performable logic devices. This environment led to unique products mance comparison to minimize difficulties in comparisons driven by hardware engineers where one manufacturer’s digitizer across manufacturer components and also because Xilinx is the could have significant fundamental differences in design layout FPGA sales leader. The components selected were an attempt to and capability versus other digitizer products. However, around find components of similar class across the Virtex II to Virtex-6 the turn of the century, high-speed digitizers became increas- generations of FPGA components. The component selection proingly difficult to develop due to the compounding effect of IC cess for finding these similar components across generations is tolerance errors, which resulted in design timing issues. not so black and white, which admittedly leaves room for some Fortunately, as ICs began to fail to meet the needs of ris- error, but the overall general trend is undeniable. ing analog-to-digital converter (ADC) sampling rates, early field programmable gate array (FPGA) devices were just beginning 70 to enter the market. Though these early FPGA devices were not 60 the data processing juggernauts they are today, they did allow for digitizer designs to consolidate what once spanned about 50 to 50 100 ICs to a single FPGA package. The result was much tighter 40 timing and truly synchronous designs that no longer suffered ADC compounding time deviations from IC to IC. 30 FPGA Utilizing FPGA components clearly solved an important in20 dustry problem that was in dire need of a solution, but it also 10 created an interesting side effect. Digitizer products began to homogenize across all designers and manufacturers, where new 0 digitizers seemed to be little more than the latest ADC connected 2002 2003 2004 2005 2006 2007 2008 2009 to the latest FPGA, which begged the question, “Where is the inFigure 1 novation or invention?� The last couple FPGA component generations have elevated 14-bit ADC data load increases versus FPGA processing performance increases since 2002. their processing capabilities to the extent that not only can they

Data Acquisition with Small Modules

High-Speed Digitizers Recapture Innovation as ADCs Yield to FPGAs




Technology deployed

ADC Device

ADC Manufacturer

ADC Sample Rate

ADC Performance Factor


AD6645-105 (estimated)

Analog Devices

105 MHz





105 MHz





105 MHz





190 MHz





210 MHz





400 MHz





400 MHz





400 MHz


TABLE 1 ADC sampling performance factor increases since 2002

Since 2004 and the release of the Virtex-4 FPGA, the primary processing elements within Xilinx FPGAs are the logic cells and the DSP48 slices (PowerPC processors are also available in some models, but are not a focus in this article). While difficult to directly quantify performance capabilities of one versus the other (since they tend to specialize in different operations), industry experience and component history indicate that the logic cells and DSP48 slices deliver comparable processing magnitudes when considering all logic cells versus all DSP48 slices for a particular FGPA package. Again, similar to the FPGA component comparison selection process, equating the relative capabilities of all the DSP48 slices in a package relative to all the logic cells is not so black and white, but it is clear that both resources can deliver significant processing capabilities to realtime applications, and neither resource has significant capabilities over the other. The graphs in Figure 2 show the FPGA performance factor increases—derived from data in Table 2—and the relationship between different FPGA component generations of Xilinx FPGA devices. This progression comparison provides a sense of relative capability between the FPGA devices as well as data for how the “Estimated FPGA Performance Factor” numbers were established. Based upon these numbers, both resources appear to approximately triple for each new component generation. It should also be noted that the clock rates increase by about 10-20% for each generation, resulting in an effective performance growth rate slightly greater than the resource counts alone would indicate. However, is such an exponential performance factor path sustainable? To answer this question, initial analysis of the increased next-generation FPGA resources relative to the Virtex-2 shows a general x3 increase across all FPGA resources (Figure 3). So far, the exponential theory holds. However, analysis of the performance factor increase of all FPGA resources relative to the predecessor FPGA model reveals a different story. Figure 4 shows an interesting trend regarding the exponential growth factor of the DSP slices. From the Virtex-4 to the Virtex-5 to the Virtex-6, the exponential performance factor slows linearly, from x4 to x3 to x2, as new FPGA generations are released. In contrast, the logic cells growth shows little variation, hovering between 2.7 and 3.3 for each FPGA generation.

FPGAs 70 60 Performance Factor


50 40 30 20 10 0






1600 1400 1200 1000 800 600 400 200 0





FPGA Logic Cells

350,000.00 300,000.00 250,000.00 200,000.00 150,000.00 100,000.00 50,000.00 0 XC2V1000




Figure 2 With each next-generation FPGA, processing performance triples about every two years.

The DSP slice performance factor decrease isn’t unexpected. Great advances are often followed by a gradual normalization process. Yet, despite the slowdown witnessed with the DSP slice, the x3 logic cell growth trend continues for a few FPGA generations, where an incredible amount of logic resources will be available even if the DSP slice growth were to slow down and stay under x1.5 per generation. To highlight the exponential processing capacity in a practical sense, consider that in 2004, digitizer cards could acquire 160 MSPS of 16-bit data for a single analog channel and select up to 10 DDC channels containing 3 MHz of narrowband data with a logic package running on an embedded Xilinx Virtex-4 FX60. This process consumed nearly all DSP resources within the Virtex-4 FX60 FPGA. Just two years later, when Xilinx released the Virtex-5 SX95 in 2006, digitizer cards could acquire two analog channels at a full rate of 400 MHz at 14 bits, where the FPGA not only handled the same DDC capability, but also allowed the addition of realtime FFT processing and data averaging modules.



technology deployed


Current Capabilities of Embedded Logic

30 25 20

Block RAM


DSP48 Logic Cells

10 5 0 2V1000




Figure 3 Relative increment of different FPGA resources for different FPGA generations using Virtex- II as a basis. 6 5 4 Block RAM




Logic Cells

1 0 2V1000




Figure 4 Relative increment of different FPGA resources for different FPGA generations using the previous generation as basis.

In 2009, Signatec, Inc., a manufacturer of high-speed data acquisition, real-time processing and arbitrary waveform generation systems for advanced radar, signals intelligence (SIGINT), ultrasound, medical imaging and other high-speed communications applications, released a PCI Express-based, high-speed digitizer leveraging the Virtex-5 SX50 and SX95 FPGAs with embedded fixed signal processing packages (Figure 5). The left side of Figure 5 exemplifies a common wideband capture scenario, where the PX14400 digitizes 14-bit data at 400 MHz for a total capture band from near DC to 200 MHz. Inside this greater 200 MHz bandwidth is an intermediate and smaller band of interest positioned at the center frequency (Fc). The ADC digitizes the input signal and passes data to the “Standard Signatec Logic” (SSL) module, which contains all PX14400 generalpurpose product services. The SSL, contained entirely within the first V5 LX50T FPGA, connects directly to the ADCs, PCIe host bus and to a second V5 SX95 FPGA. This second FPGA is dedicated to real-time data processing and incorporates all remaining diagram elements. In this fixed capability logic kit (FLK), the first element in the processing chain is the numerically controlled oscillator (NCO), which allows for modulating the signal band of interest to another center frequency, usually baseband. FIR filter stages follow the NCO and allow data decimation in steps of x2 from 23 up to 212. The output of the filters can be either real or I&Q format. Figure 6 shows the characteristics of the x2 decimation filters, where the stop band is sufficiently attenuated by 90 dB or better, which exceeds the dynamic range for a 14-bit signal digitizer. Data decimation occurs in x2 increments repeatedly until achieving the desired decimation rate. Windowing and FFT processing stages immediately follow the filters. The FFT window is fully programmable with variable FPGA



Standard Custom/FLK Signatec Logic FPGA Processing (Raw Data) In Switch Out Data Path 1:3 Out Out

In Switch Out In 2:2 Out

Filter with x2 Data Decimation1 x2


IF Band of Interest

FFT Window In In Switch Out Programmable Windows and 2:2 Out


FFT Windows Bypass

Figure 5


Mixer/NCO Bypass PCIe/

200 MHz

Instantaneous BW up to 200 MHz Captured Frequencies up to 400 MHz

Mixer/ NCO

FFT In Switch Out In 2:2 Out FFT Bypass

Programmable Real In Switch Out Size FFT2 I & Q In 2:2



Data Averager Programmable Size and Accumulations

Data Averaging Bypass

1.) Filter has Customer Programmable Filter Coefficients and Data Decimation in Factors of 2 up to 2ˆ12 2.) FFT Size up to 4096 Points with x2 Size Decimation to 64 Points; Output Format can be Real only or I & Q Note: Switch Elements can only Connect a Single Input to a Single Output

PX14400-SP95 and Signatec’s V5 SX95T-based Processing Elements (at 400 MSPS, 2 Chs, 14 bits)



Out SAB In Switch Bus In 2:2 Out

PCIe Bus

Technology deployed

Figure 6 Frequency response of the x2 decimation filters.


FPGA Device

FPGA Manufacturer

Logic Cells

DSP48 Slices

Estimated FPGA Performance Factor



































established), but they can also effectively handle the increased data sampling rate demands of the highest sample performance 12-bit ADCs when implementing the same DDC, FIR filter, FFT and data averaging example program for the 400 MHz digitizer. When compared to the advances in FPGA processing capabilities of the same time period, ADC sampling rates are increasing at a slower rate than FPGA processing resources. Given that FPGAs triple processing elements about every two years and ADCs double sampling rates every 2.5 to 3 years, by 2016, FPGA processing capabilities will outpace the ADC data supply load by about 6:1. Should this trend continue, in 10-12 years, the ratio could be over 30:1. Such large ratios of increased embedded processing performance above and beyond the real-time processing capabilities possible today positions the high-speed data acquisition and signal recording industry upon the precipice of a design revolution, where a wave of innovation and invention will birth creative new paradigms. The driver of digitizer technology, which to date has mostly been ADC driven, will likely transition to an FPGAcentric model where product capabilities will be increasingly defined by the embedded processing. Signatec Newport Beach, CA. (949) 729-1084. []

1 192


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TABLE 2 FPGA processing performance factor increases since 2002.

FFT sizes from 64 to 4096 points supported. The output from the FFT is either magnitude squared or complex, which then passes into a programmable data averager with up to 216 accumulations possible to complete the processing elements. Any processing element in the FLK can process data in-line, as shown in the diagram, or be bypassed.

Next-Generation ADCs

The previous section detailed the type of real-time processing capabilities that are currently in the digitizer market and running on the Virtex-5 SX50T/SX95T devices. Using the recently released state-of-the art 1 GHz, 12-bit ADC as an example, today’s 28nm Virtex-6 FPGA family equivalent of the Virtex-5 SX95T will possess the capabilities to handle the x2.5 jump from the previous 400 MHz, 14-bit ADC digitizer processing example (and likely with some additional resources to spare). This result indicates that not only can the next-generation FPGA components more than handle the state of the art for 14-bit ADCs (as

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Untitled-6 1



11:43:57 AM



Touch Screen Technology

From Your Finger to the Screen – How Touch Screens Understand From a touch on the touch screen through system hardware and software stacks and several complex steps, capacitive touch screen technology is becoming a more vital part of handheld and mobile user interfaces. by Steve Kolokowsky and Trevor Davis, Cypress Semiconductor


hile touch screens have become more prevalent in everyday electronics, few people understand how they really work. From the capacitive change from a human finger to the final motion on screen, the technical aspects of touch screens remain a mystery to most users. In fact, most users understanding of a touch screen consists of either “it works well” or “it doesn’t work well.” The question is how to understand the system well enough to determine what makes a touch screen work well or poorly. In order to understand this better, we would like to de-mystify how a touch screen registers the human touch, expose critical aspects of touch screen construction, and to show how touch motions on the touch screen are interpreted and result in screen action.

What’s Inside the Touch Screen?

A capacitive touch screen is commonly constructed of several layers, called the “stackup.” The top layer is a protective layer composed of glass, or PMMA (commonly called Plexiglas or acrylic) with an anti-scratch coating. This layer is often shaped and printed with the company logo, button indicators, and is the outward most facing material of the phone or



Glass/ Film/ PMMA - overlay for protection Adhesive or isolation layer Indium Tin Oxide (ITO) - a transparent metal deposit Glass/Film Second Layer of ITO - for touch sense or noise isolation LCD

Figure 1 Cross-sectional view of capacitive touch screen “stackup”.

touch product. Directly underneath this top layer is a thin layer of optically clear adhesive and then the exciting part—the touch-sensing layers. The primary technical “secret” of the touch sensor layers is that they are constructed of indium-tin-oxide (ITO). The ITO is optically transparent, even though it is a ceramic. Typical capacitive ITO touch screens are ~92% transparent, which is a very large selling feature. Below the ITO sensing layers is an air gap or spacing that helps separate these touch sensing layers of ITO from the electrical

noise of the bottom most layer—the LCD electronics. In Figure 1, there are two layers of ITO shown. Touchpanel vendors will use one, two, or even three layers of ITO depending on the specific product design considerations. Ultimately, however, the ITO layering is chosen depending on the touchpanel supplier’s technical capabilities as well as technical requirements from the customer. If you examine a touch screen device from the right angle (with the LCD turned “off”), you may even be able to see the ITO pattern in the glass. Today, typical touch

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X Sensor Data


Y Sensor Data

Figure 2 ITO patterning on a typical touch device provides X & Y touch information

CSD Block Diagram VDD

16-bit PRS





Inside Cypress TrueTouch Controller ADCPWM EN


Data Processing



Figure 3 Capacitive charge circuit for sensing capacitive change and finger detection

screens use a diamond pattern as shown in Figure 2. Diamonds have been chosen as a “best practice” for design because the ITO patterning must meet several requirements. First, the ITO layer must cover the whole screen, so that there is no visible variation in optical clarity. Second, it is easiest for system designers if the pattern corresponds to an X/Y grid—writing software that comprehends X and Y locations is simpler and more logical when making LCD update decisions. Finally, the pattern must provide continuity across the entire electrode. Diamonds with small bridges between them meet all of these needs.

The Physics of Touch

The key to making a capacitive touch screen work is that the system is designed to detect minute changes in capacitance introduced by a human finger. In fact, as a finger or other conductive object ap-



proaches the screen, it creates a parallelplate capacitor between the sensors and the finger. This capacitor is small relative to the others in the system (about 0.5 pF out of 20 pF), but it is measurable with the right technology and filtering. A parallel-plate capacitor is composed of two conductive surfaces with an insulator between them. The ITO layer is a conductor, a user’s body is a conductor, and the glass or PMMA is an insulator. When a user touches the screen, they’ve become part of a capacitor. This same phenomenon is used in Cypress’s CapSense devices, which provide buttons and sliders in products from cell phones to washing machines. One mechanism used to sense capacitance is Cypress’s CSD (CapSense with Sigma Delta). In this method, the capacitor is measured by a mechanism similar to a Sigma Delta ADC. The capacitor is connected to a bleed resistor (RBleed). If

the voltage across the capacitor is above a threshold, a fixed charge is added to the cap. The circuit then measures the amount of time (counts) required to discharge the cap before the threshold is hit again. These counts are averaged over time to obtain an accurate capacitance measurement. The CSD block diagram in Figure 3 appears complex at first, but it can be understood. Let’s start on the left hand side. The PRS (Pseudo-Random Source) causes Switch 1 (SW1) and Switch 2 (SW2) to alternate connections in a break-beforemake pattern. This means that CSENSOR will be connected to VDD, then connected to CEXT over and over again. CEXT is an external capacitor used to integrate charge from CSENSOR. Every time CSENSOR is connected to VDD, it fills with charge. When CSENSOR is connected to CEXT , it charges CEXT. Note that CSENSOR is much smaller than CEXT. Imagine a bicycle pump and a tire. Each time SW1 is closed, the handle is pulled up and the air cylinder is filled. Every time SW2 is closed, the pump handle is pushed down and the air moves from the pump to the tire. The circuit elements in the middle portion of Figure 3 discharge CEXT and measure CSENSOR. When the voltage at CEXT is above VREF, SW3 is closed, which discharges CEXT. Think of this discharge as a safety valve on the bicycle tire. One important feature of this safety valve is that it discharges at a known rate. Once we measure the discharge time, we know CSENSOR. The right-hand portion of the diagram is simply measuring the amount of time that SW3 is closed. The PWM provides a pause between scans to allow the processor to read samples. The counter measures time whenever SW3 is closed. As the capacitance increases at CSENSOR the charge sent to CEXT increases, so the amount of time that SW3 is closed must also increase. It is this capacitive change that allows the touch screen controller to recognize that a touch (resulting in an increase in sensed capacitance) has occurred. The problem, of course, (and one of the key contributors to a “good” or “bad” touch screen), is the ability to tell a true finger


1. Device collects X/Y data from the panel 2. Device processes data

3. Device asserts line to host and passes X/Y data

4. Host reads data from I2C 5. (optional) Host changes parameters on the device

Figure 4 Data processing flow from touch screen to host processor.

touch from environmental noise. Noise in the system can really cause problems. If the touch controller is not able to distinguish an actual finger touch from just a capacitive noise spike, the touch screen will not react properly.

Finger Location Determination

Once the system can properly recognize a change in charge due to a finger touch, the exact location and motion path can be determined. Measuring the capacitance of all sensors in the touch screen produces information on exactly which sensors are active and the magnitude of capacitance change. Even though the screen may only contain an X/Y grid of 10x15 sensors, users want the system to report touch location accurately even within a millimeter. A simple interpolation technique can be used to determine finger position to a very fine degree. For example, if sensors 1, 2 and 3 see signals of 3, 10 and 7, the center of the finger is at (1*3+2*10+7*3) / (3+10+7) = 2.2. This value is normally scaled to match the pixel resolution of the LCD before it’s reported to the host CPU. In a real design, there are several factors that complicate matters. When the finger reaches the edge of the panel, the interpolation breaks down because there is no “next sensor” to average into the computation. One method used to mitigate this effect is to assume that all finger touches produce the same total capacitance change. In the example used above,

the finger created a capacitance change of 20 units. If a touch near the edge is measured with a capacitance change of only 15 units, it can be presumed that the remaining 5 units are over the edge. Additionally, customers may have unique industrial design requirements that dictate that a touch screen does not detect a touch when finger capacitance is witnessed on the touch screen edge (perhaps from holding the phone edges). In designs such as this, the touch screen controller must be flexible enough to be programmed to recognize these types of touches and to ignore them.

the raw data through a low-level driver to the host operating system for interpretation and action—and the rest is up to the user interface designers. Creating unique human interaction and exciting features that rely on touch will be an exciting place to watch for new development ideas in the near future. The fact that touch screens are becoming more and more popular is not a mystery. Consumers continue to call for cell phone, notebook, PC monitor, netbook, MP3 player and IP phone manufacturers to produce more versions of touch screen-based devices. With a more clear understanding of how capacitance change is sensed, how a finger location is determined and refined, and how the finger location data is passed up through the host system for operation, developers will be more able to supply innovative touch screen technology to meet the ever-increasing demand from users for this compelling interface. Cypress Semiconductor San Jose, CA. (408) 943-2600. [].

Communication to the User

Now that a valid touch signal is present and the X/Y coordinates of the touch are known, it’s time to get the data to the host CPU for processing. Most touch screen devices communicate using the venerable I2C interface. The touch screen controller IC uses I2C (or SPI if desired) to pass X/Y or gesturing data to the product’s host processor where the command of product operation takes place. An example flow of this data transfer is shown in Figure 4. In a real system, most of these touch detection and feedback operations take place in parallel because the touch screen is in constant detection mode when being operated by a user. As the touch data is collected, the touch controller device can either process the data to interpret a finger motion (or gesture) itself, or it can pass RTC MAGAZINE APRIL 2010



PRODUCT EPIC-Express Board Demonstrates New Cooling Concept and Mechanical Design

A new product family targets strategic mission-critical systems and enables easy and reliable development of applications that require non-stop operation reliability (24/7), within wide ambient temperature ranges and temperature variations, as well as extreme shock and vibration durability. With the Hurricane-QM57 from Lippert Embedded Computers, the innovative mechanical concept provides for a passive cooling mechanism and a robust mechanical construction. The rugged DDR3 SODIMM memory modules provide error correcting code (ECC). They surpass conventional SODIMM construction to withstand more rugged environmental requirements. Two memory channels access up to 8 Gbytes system memory for better system data throughput. One memory bank soldered directly to the board provides basic memory capacity. The second bank features sockets for expansion with Rugged SODIMM modules. The RAM clock runs at up to 1066 MHz. The Core i7 processor features an integrated graphics controller, which manages and controls two independent highresolution displays. Additionally, a dual channel 24-bit LVDS connects to flat screens. Other key features include two Gigabit Ethernet channels, four SATA interfaces at 3 Gbit/s with RAID support and ten USB 2.0 ports. There is a mini-PCIe slot for WLAN and other accessory cards as well as a PCI/104-Express extension slot. The extended temperature range covers -40° to +85°C. With the cooling concept of the Hurricane-QM57, all components requiring cooling reside on the board’s bottom side, where they have direct thermal contact to a specially designed heat spreader. This also serves as a mechanically stable mounting platform preventing torsion and providing mechanical strength when mounting or removing extension boards on the top side. Extension boards in PC/104-Express as well as EPIC-Express formats can be mounted without obstruction on the top side. The heat spreader also provides the mounting holes required by heat pipes. This enables the fast and easy integration of customized heat pipe solutions. This design of the Hurricane-QM57 became possible through the use of a compatible, but higher, PCI Express connector to gain the height (22 mm) required for the Ethernet and serial interface connectors. PCI Express boards from other vendors with connectors of 15.24 mm height can be used without modification. Pin assignments are unchanged from the standard. Using the EPIC-Express form factor has several advantages for the user. It is an Industry standard by the PC/104 Industry Consortium and offers easy functional extension using PC/104 and PC/104-Express peripheral boards. It is a compact and rugged format (165 mm by 115 mm) with all connectors for external peripherals on one board edge. No cable sets are required. In additions, it accepts plug-on extension boards in EPIC-Express format with more room for special functions. First introduced with Intel Atom designs, Lipppert Enhanced Management Technology (LEMT) provides additional valuable features for condition monitoring, such as:



• Operation hours counter (in minutes) • On-time counter since last power on in seconds • Power cycle counter • Reason for system restart (normal shut-down, watchdog, power loss, system crash) • Long-term watchdog • 1024 bytes flash memory for customer’s information • 128-bit encryption key (write once, read many) • Board identity (Vendor ID, board ID, serial number) • Storing lowest, highest and current environmental temperatures Lippert offers software APIs for the LEMT functions for various operating systems. Two peripheral EPIC-Express extension boards for the HurricaneQM57 have already been designed. One board features 8 serial COM ports with up to 1000V potential separation between the individual ports and the base board interface. Four COM ports interface to DSUB9 connectors; the other 4 require flat foil cables with DSUB9 connectors. All COM ports support software-configurable signal levels for RS-232C, RS-422 or RS-485 protocols. The other board provides eight Gigabit Ethernet channels with an individual MAC-ID on each channel. Many security applications require such configurations. LiPPERT Embedded Computers, Mannheim, Germany. +49 (0) 621 43214 12. [].

products &

TECHNOLOGY Series of Ten Multifunction USB Analog Output Modules Starts at under $300

A line of 12- and 16-bit USB I/O modules for use in data acquisition and control—the USB-AO series from Acces I/O Products, includes 10 models with list prices ranging from $299 to $699. The flagship model is the USB-AO16-16A, a high-speed USB 2.0, multifunction board that features 16 channels of 16-bit resolution analog outputs along with two 16-bit analog inputs and 16 digital I/O lines— all packaged in a small, rugged, industrial enclosure. This module can be used in any PC or embedded system with a USB port and is a suitable choice for embedded system and test designers. The USB-AO16-16A can be used in an assortment of USBbased embedded applications that require stable and accurate output signals. A micro-fit USB header connector is provided in parallel with the high retention type B connector and can be used for stacking and embedded applications. Available accessories include a wide variety of cables and screw terminal boards for quick and easy connectivity. A DIN rail mounting provision is available for installation in industrial environments. The OEM version (board only) features PC/104 module size and mounting compatibility. The USB-AO Series can be integrated into any PC/104-based stack by simply connecting it to a USB port included on board with embedded CPU form factors such as EBX, EPIC and PC/104. The USB-AO Series utilizes a high-speed custom function driver optimized for a maximum data throughput that is 50-100 times faster than the USB human interface device (HID) driver used by many competing products. The USB-AO Series is supported for use in most operating systems and includes a free Linux (including Mac OS X) and Windows 2000/XP/2003/Vista/7 compatible software package. This package contains sample programs and source code in Visual Basic, Delphi and Visual C++ for Windows. Also provided is a graphical setup program in Windows. Third-party support includes a Windows standard DLL interface usable from the most popular application programs, and includes LabVIEW VIs. Embedded OS support includes Windows XPe ACCES I/O Products, San Diego, CA. (858) 550-9559. []

High-Speed Solid-State Drives for Embedded Systems

A new family of solid-state drives (SSDs) features fast read/write speeds in high capacities and is designed for embedded system OEM applications that require superior performance, high reliability and long product life. The single-level cell (SLC)-based SiliconDrive N1x SSDs from Western Digital are an ideal storage solution for a wide range of embedded system OEM applications in growing markets such as automotive and transportation, data center, communications infrastructure, video surveillance and industrial automation. WD SiliconDrive N1x SSD products feature a native SATA 3.0 Gbits/s interface with target read speeds up to 240 Mbytes/s and write transfer rates up to 140 Mbytes/s in capacities up to 128 Gbytes/s. WD SiliconDrive N1x SSDs deliver maximum drive endurance and high sustained sequential write speeds to satisfy the 24/7 operational requirements in critical OEM applications. The WD SiliconDrive N1x products also feature WD’s innovative Speed Assurance technology for consistent read/write performance. Western Digital, Lake Forest, CA. (949) 672-7000. [].



New RISC Embedded Computer Offers Rich I/O and Windows CE 6.0

RISC computing power is delivered in a compact, rugged package and packed with a wealth of I/O features and using the latest embedded software environment. The Relio R9 from Sealevel Systems is based on the Atmel AT91SAM9263 processor boasting a 32-bit ARM instruction set. The Relio R9 is an attractive platform for embedded applications requiring small size, wide operating temperature range and flexible I/O connectivity.

Available with up to 256 Mbyte RAM and 256 Mbyte flash memory, the I/O features of the Relio R9 extend the possible uses beyond traditional ARM applications. Standard I/O includes Ethernet, serial, USB, CAN Bus, digital and analog interface. For local or remote I/O expansion, the Relio R9 connects to Sealevel SeaI/O modules via the dedicated RS-485 expansion port and communicates via RS-485 Modbus RTU. The Windows CE 6.0 BSP binary and low-level drivers for system I/O are included. Additionally, the R9 software package is equipped with the Sealevel Talos I/O Framework, which offers a high-level object-oriented .NET Compact Framework (CF) device interface. This interface provides an I/O point abstraction layer with built-in support for the specific needs of analog and digital I/O such as gain control and debouncing. The Relio R9 is housed in a rugged, small enclosure suitable for mounting almost anywhere and is rated for a full -40° to +85°C temperature range. The Relio R9 is priced from $599, and a QuickStart Development Kit is available. Sealevel Systems, Liberty, SC. (864) 843-4343. [].

PC/104, PC/104 Express and ISM Showcase USB-AO Series: Multifunction USB/104 modules provide up to 16 Analog Outputs and 2 Analog Inputs

Featuring the latest in PC/104, PC/104 Express and ISM technologies ACCES I/O Products, Inc. Phone: (858) 550-9559 Fax: (858) 550-7322

P104-WDG-CSMA: PC/104Plus Watchdog Timer Status Monitor

ACCES I/O Products, Inc. Phone: (858) 550-9559 Fax: (858) 550-7322

PC/104-Plus watchdog timer Watchdog open collector reset outputs Temperature sensor with calibration pot Temperature monitor / alarm Temperature measurement with 8-bit A/D Fan status and speed control PCI/104 power monitor / limit alarm Opto-isolated input to trigger reset General purpose opto-isolated input Two isolated outputs, current limited TTL reset pushbutton input Two general purpose 8-bit A/D inputs Light sensor for enclosure security E-mail: Web:

Fastwel Phone: (718) 554-3686 Fax: (718) 797-0600

E-mail: Web:

E-mail: Web:

PC/104Plus to PCI Interface The BX-DE-104+-465 board connects up to four PCI Boards directly to PC/104Plus system. This is one of many interface boards from Douglas Electronics for connecting PC/104, PC/104Plus, ISA, PCI, PMC and CompactPCI products.

Douglas Electronics, Inc. Phone: (510) 483-8770 Fax: (510) 483-6453

PC/104 Plus –CPC306 DM&P Vortex86DX (800 MHz) processor 128 MB DDR2 SDRAM Two Xilinx FPGAs Flash disk 128 MB Ethernet controller 10/100 Mb/s PC/104 slot (32-bit PCI, 16-bit ISA) USB 1.1, USB 2.0 support, up to four devices connection Four COM ports Isolated analog input – 8 channels Isolated analog output – 2 channels ADC, DAC 100G/10G – shock/vibration Industrial operating temperature range: –40°C to +85°C Protective coating (optional)

4, 8, or 16 analog outputs with 12 or 16-bit resolution USB/104 form-factor for OEM embedded applications PC/104 module size and mounting compatibility Two 16-bit analog inputs and 16 lines of digital I/O Connections made via industrystandard 37-pin D-Sub connectors Alternate micro-fit embedded USB header connector Type B USB connector features industrial strength and high-retention design Extended temperature

E-mail: Web:

USB Embedded Modem Modules

Radicom Research, Inc. Phone: (408) 383-9006 Fax: (408) 383-9007

USB modems, in module or standalone form factor Linux, Windows and Mac O/S support -40C to +85C operating temperature (Module) Compact size: 1” x 1” x 0.2” (Module) USB 2.0 compatible up to 56K bps data rate, fax and voice AT command Transferable FCC68, CS03, CTR21 telecom certifications Global safety: IEC60950-1, IEC606011 (Medical) approved CE marking E-mail: Web:


Embedded Application Lifecycle Management Solution Targets 50% Cost Reduction

A new end-to-end application lifecycle management (ALM) system for the embedded space merges product requirements, business objectives and metrics in a uniform actionable perspective. Embed-X, jointly released by LDRA and Visure Solutions, also delivers these ALM objectives with full certification support for critical development standards in the avionics, defence, automotive and medical markets. To enable companies to cope with the exorbitant costs systemic in current development processes, LDRA and Visure have designed Embed-X to streamline software development with the goal of delivering 50% cost savings. This embedded application lifecycle management for critical systems coordinates software engineering by integrating project management, requirements management, architecture, coding, software configuration management and testing. ALM solutions automate and enforce processes between the stages of development, manage relationships between assets used or produced by the software, and offer transparency and metrics through reports on development as it progresses. Building on LDRA’s experience in the critical software marketplace and Visure’s experience delivering requirements solutions, Embed-X is geared to meet the demands of safety-critical development standards. Incorporating LDRA’s patent-pending verification management technology, Embed-X will help system engineering, development and production organizations by coherently tracing requirements through static and dynamic analysis to unit testing and system verification to achieve a fully certified application. Embed-X offers compliance with DO-178B, MISRA and security standards, such as CERT C and the Homeland Security Agency’s Common Weakness Enumerations (CWE). Knowing the cost-sensitivity of the embedded market, LDRA and Visure have eased adoption by providing a target license package that incorporates customization and training. LDRA, San Bruno, CA. (650) 583-8880. []. Visure Solutions, Madrid, Spain. +34 91 806 17 13. [].

Embedded Virtualization Manager Pairs Windows with RTOSs

A new embedded virtualization manager software product enables different real-time operating systems (RTOSs) to run alongside Windows on the same multicore processor platform without sacrificing determinism, performance or features. Using eVM for Windows from TenAsys, applications that have been developed for stand-alone RTOSs such as QNX, VxWorks, Windows CE and numerous others, can now be run on multicore Windows platforms with full native performance. Unlike other virtualization schemes, which can fail in time-critical applications, eVM for Windows’ embedded virtualization technology utilizes hardware-assisted features built into Intel processors to allocate hardware resources and ensure that time-critical I/O processes aren’t interrupted, thereby ensuring that systems provide deterministic response to real-time events. eVM for Windows enables cost savings by allowing systems that previouslyrequired multiple platforms in order to guarantee determinism to be implemented on a single multicore platform. In addition to saving hardware costs by eliminating redundant memories, power supplies, circuit boards and interconnects, this approach also cuts the cost of system design and maintenance. Investments in legacy software are protected by enabling the hosting of legacy RTOSs and application software on their own cores while new features are implemented on other OS environments on other cores. eVM for Windows is priced a $995 in a starter kit at the TenAsys Web site. TenAsys, Beaverton, OR. (503) 748-4740. [].



Atom XL-based ESMexpress COM Module with Extended Temperature Operation

An upgraded ESMexpress Computer-onModule (COM) incorporates the Intel Atom XL processor to provide tested, qualified operation in the extended temperature range of -40° to +85°C (-40° to +185°F) in both conduction and convection-cooled environments. It also features an increased memory capacity of 2 Gbytes, double its predecessor. Because the enhanced XM1L from Men Micro conforms to the ANSI-VITA 59 RSE standard currently in development, it provides a cost-effective and easily upgradeable means of employing advanced embedded technology in highly rugged applications as found in industrial, harsh, mobile and mission-critical environments.

The low-power XM1L uses the Intel Atom XL processor family operating at up to 1.6 GHz in combination with an IA-32 core based on 45nm process technology, while drawing a maximum of 7W. In addition to the upgraded 2 Gbytes of soldered DDR2 SDRAM system memory, the XM1L supports other memory, including USB flash on the carrier board and 512 Kbytes of L2 cache integrated into the processor. All interfaces from the Intel System Controller Hub US15W are routed from the XM1L for use on any ESMexpress carrier board. Interfaces can include a combination of PCI Express links, LVDS, SDVO, high-definition audio, SATA, Ethernet with Wake-on-LAN functionality and USB, depending on application requirements. Additional COM interfaces are available on the carrier board via a USB to COM conversion. A board management controller monitors all board functions to complete the functionality of the XM1L. For testing of the XM1L and for developing the application, the universal carrier board XC1 in ATX format can be used. The XM1L can also be plugged onto COM Express carrier boards (basic form factor type 2) via the adapter board AE12. Pricing starts at $497. MEN Micro, Ambler, PA. (215) 542-9575. [].


AdvancedMC Sports Quad-Core Performance

A double-wide, full-size AMC module features the new Intel Xeon processor LC5518, which is based on the latest Intel microarchitecture and delivers with its 45nm process technology even lower power consumption and higher integration. This makes the AM5030 from Kontron an attractive solution for MicroTCA platforms designed for dense server environments deployed in storage, military/aerospace and communications networks such as IPTV, VoIP, NAS, SAN and wireless radio network controllers. The 45nm Intel Xeon processor LC5518 with integrated I/O Hub features a 4-to-1 consolidation of workload functions for greater real estate and power savings. This includes, for the first time, the integration of PCIe Gen 2.0 I/O within the processor. In addition, the new processor offers up to 8 Mbytes shared Last Level Cache, Intel Hyper-Threading technology support and Intel Turbo Boost technology. Thanks to the accompanying Intel 3420 platform controller hub (PCH) and Direct Media Interface (DMI), the Kontron AM5030 takes full advantage of reduced component count and streamlined data-paths between CPU, PCH and peripherals for overall greater performance. Furthermore, an integrated Redundant Array of Independent Disks (RAID) acceleration, which is advantageous for storage customers migrating to Intel architecture or transitioning RAID for core optimization, complements the unique technical feature set. The AM5030 hosts up to 24 Gbyte ECC memory (DDR3) at 1066 MHz implemented as a 3-channel interface for the highest memory access, and is built with two 10GbE (XAUI) interfaces in accordance with AMC.2 for comprehensive networking capabilities. Four GbE interfaces, two available on the front panel, two in accordance with AMC.2, provide additional networking capabilities. The AMC.1/.2/.3-compliant Kontron AM5030 module has full hot-swap capabilities for replacing, monitoring and controlling the module without the need to shut down the MicroTCA system. A dedicated Module Management Controller (MMC) is used to manage the board and to support a defined subset of Intelligent Platform Management Interface (IPMI) commands. The new Kontron AM5030 supports RedHat Linux, Windows 7, Windows XP and Windows 2008 Server. Kontron, Poway, CA. (888) 294-4558. [].

$149 Evaluation Kit Invites Energy Harvesting and Wireless Exploration

For only $149, an evaluation kit enables integrators and OEMs to explore the breadth and performance of EnOcean wireless energy harvesting technologies within the context of their own buildings. Encapsulated in the kit are the building blocks critical to fully integrated systems: energy generation, energy conditioning and storage, sensor power balance, lowpower timers and also a microprocessor for OEM custom development. These are the same components that have enabled automated energy management in more than 100,000 buildings worldwide. System integrators can simulate sensor applications in any environment without any programming or configuration. The Evaluation Kit from Echoflex contains a solar-powered temperature sensor, set point adjustment and reed switch (magnet contact). The radio modules are powered by two ambient sources—infinite wells of solar and motion energy. Integrated energy harvesting ensures full functionality of the solar-powered STM sensor modules even after days in complete darkness. The motion-powered PTM module is optimal for ON/OFF/DIM controls such as lighting, blinds and master ON/OFF switching. The bi-directional transceiver (TCM 200C) communicates directly with associated lighting/temperature plug-ins and software. Key Features of the evaluation kit include the ability to explore the range and reliability of the EnOcean wireless standard in any environment. It highlights the demonstrated capabilities of EnOcean PTM, TCM and STM radio modules and includes a bi-directional transceiver for communicating with remote sensors and feeding data into a PC. A USB connection and software are provided for monitoring radio packets, and the kit offers interoperability with other EnOcean-based products. Echoflex, Squamish, BC. (888) 324-6359. []. EnOcean, Boston, MA. (801) 943-3215. [].

VPX Test Backplane Eases Access to Signals

A 2-slot test backplane for VPX board developers and integrators is designed to the latest VITA 46 specifications. The backplane from Elma Bustronic allows the user to power up and test J1 fabric connections as they would be interconnected in the target application. Signals can be passed from one slot to the next via high-speed interconnecting cables, via signals introduced through the J1 fabric connector, or accessed on the J1 fabric connector using the test backplane’s SMA and SATA cable headers. The test backplane accepts 6U cards with the 3U size supported by use of a shelf divider. For convenience in attaching probes, the slot pitch is an extra wide 1.6”.

VPX cards are usually developed together with a rear transition module that does not access the J1 fabric signals. In conventional designs, an engineer cannot probe these J1 fabric signals while using the device under test’s (DUT) rear transition module (RTM) to access other I/O signals. The Bustronic solution allows the primary J1 fabric signals to be accessed/connected without interfering with the use of an existing RTM designed for J2-J6 I/O connector signals. Further, custom backplanes are often required to interconnect the primary fabric signals between multiple VPX blades for a specific application. The VPX Test Backplane allows the user to interconnect two or more such blades before investing the time or expense of a custom VPX backplane. Additional 2-slot Test Backplanes can be used in a larger chassis to interconnect the J1 primary fabric in any serial topology desired. The A channel input using SMA cables accepts up to 10 Gbit/s and the B, C, and D channel inputs using the SATA II connectors accept up to 3.125 Gbit/s. There are 8 power studs for VS1, VS2_A, VS2_B, VS3 and 4 GND as well as fastons for 3.3V, +/- 12V and VBAT. There are also two 5-pin IPMB headers for SMB-0 and SMB-1 Pricing starts under $1,500.. Elma Bustronic, Fremont, CA. (510) 490-7388. [].




High-Speed, Real-Time Recording for Extremely Wide Bandwidth Signals

A ready-to-run, PC-based recorder includes a complete PC workstation running Windows XP, housed in a rackmount 4U chassis. The Model RTS 2711 Real-Time Data Recording Instrument from Pentek incorporates an extremely high-speed architecture that allows simultaneous digitizing and recording of two signals at sampling rates of 500 Megasamples/sec. Since the system handles input signal frequencies up to 750 MHz, it is well suited for development and field testing in a broad range of wideband signal applications including UAVs, telemetry, communication and radar. In addition to its unusually high data rates, the Model RTS 2711 has a total of 4 terabytes of RAID storage to record arriving signals. The storage is actually configured as two 2-terabyte arrays with each of the arrays assigned to one of the A/D channels. With each of the two channels running at its full rate of 500 Megasamples/sec, users can record signals continuously for an hour. And because the Model 2711 is a complete turn-key instrument, they don’t need to do any programming or write any software—they can start recording immediately. The RTS 2711 records data directly in NTFS (new technology file system) format. This means that as soon as recordings are laid down on the RAID array hard disks, they are immediately available to any Windows application for analysis or post-processing. A number of competing instruments use a proprietary file system for recording. In order to open these files in Windows applications, such as signal analysis tools like MATLAB and others, the files must first be converted to a Windows-compatible file format. This conversion can often take many times longer than the actual duration of the recording. The RTS 2711 is easy to use due to its SystemFlow software package based on a client/ server architecture and delivered with every RTS instrument. SystemFlow includes several key components. The Graphical User Interface (GUI) provides the user with a control interface for the recording instrument and an intuitive means for setting up system parameters. The Signal Viewer includes two companion analysis tools: a virtual oscilloscope and a virtual spectrum analyzer so users can monitor the signal prior to, during and after a recording session. Together, these elements of SystemFlow greatly simplify operation. In addition, SystemFlow includes an Applications Programming Interface (API), which allows users to integrate control of the RTS instrument into a larger system application. Pricing starts at $58,995.

Board Set Merges COM Express Cores with Triple-Play I/O

A board-level “embedded-ready subsystem” (ERS) combines the benefits of computer-on-modules (COMs) with those of stackable single-board computers (SBCs). This announcement means system manufacturers no longer need to design a custom carrier to deploy COM Express modules. Called Magellan from Diamond Systems, the CPU core consists of a COM Express CPU module and heat spreader mounted on its bottom side, resulting in optimal thermal management and increased space for I/O functions and connectors.

Solid-State Power Controller Sports 8 KW over 16 channels

This design makes it possible for Magellan to integrate dual gigabit Ethernet LAN ports, a 7-30V DC/DC power supply, a full set of peripheral interface header connectors, stackable PCI104 or SUMIT expansion, and a FeaturePak I/O module socket, in addition to a complete embedded-PC core—all within the 95 x 125 mm COM Express footprint. Stacking boards in one direction greatly simplifies the thermal design of embedded systems based on high-end CPUs, avoiding costly custom heat pipes and milled aluminum thermal-transfer blocks. Magellan is offered in a range of models that vary according to the choice of COM Express CPU module and SDRAM capacity (socketed or soldered-on). It can be used either as a highly integrated embedded component, or as a platform for application development and reference designs. The Magellan baseboard includes connectors and interfaces for USB, serial, Gigabit Ethernet, audio and SATA mass storage devices. It also supports the connection of a wide variety of displays, including CRTs, LVDS-interfaced flat panels and televisions. Small quantities of the Magellan embedded-ready subsystem are available in 30 days in several models, priced as indicated in the table. Development kits that include the Magellan models plus a cable kit and utility software are also available.

Data Device Corporation, Bohemia, NY. (631) 567-5600. [].

Diamond Systems, Mountain View, CA. (800) 367-2104. [].

Pentek, Upper Saddle River, NJ. (201) 818-5900. [].

A third-generation solid-state power controller provides reliable solid-state protection and control for sixteen independent 28 Vdc channels, with a total power output of more than 8 KW. Programmable trip points, channel paralleling and power-on defaults support maximum power distribution system flexibility. The RP-26200 embedded controller and network interface from Data Device Corporations (DDC) enable real-time load monitoring, which can be used for efficient load management and preventative maintenance. The RP-26200 is based upon field-proven technology, with more than 500,000 nodes installed since 1988 on vehicles including the M1A2 Abrams tank and the Bradley fighting vehicle, and recently on upcoming unmanned ground vehicles and tactical wheeled vehicles. The RP-26200’s complement of high power density, programmability and cost-effective architecture makes it suitable for tactical wheeled vehicles where weight, size and flexibility are at a premium, and where reliability under harsh operation is vital to mission success.




FeaturePak DAQ Module with 2 MHz A/D, D/A, Autocalibration and Digital I/O

A new data acquisition model for a new standard is designed for the FeaturePak embedded I/O expansion module specification. The FeaturePakDAQ1616 from Diamond Systems is a data acquisition I/O card integrating Diamond’s newest and fastest analog I/O technology and a PCI Express host interface.

This board measures 1.7 in. x 2.55 in. and offers 16-bit A/D sampling at 2 MHz, supported with an expanded 16K-sample FIFO for reliable data collection in any operating system. Analog output capability is sixteen 16-bit channels with programmable output ranges. All analog I/O features are enhanced with our industry-leading autocalibration technology, featuring independent calibration factors for each input and output range to guarantee maximum accuracy across all operating modes and the entire operating temperature range. Digital I/O features include seven 8-bit ports with both bit-wide and byte-wide direction control, two 32-bit up/down counter/timers with programmable input source and gate, four 24-bit pulse-width modulation circuits with 0-100% duty cycle and a watchdog timer. The board is available in analog I/O and analog out-only configurations. The included driver software includes a high-level programming library for all of Diamond’s I/O boards, as well as for the data acquisition circuitry on the SBCs and EmbeddedReady Subsystems. All data acquisition features are supported by easy-to-use function calls, resulting in a reduced learning curve and shortened application development time. The Universal Driver works with Linux, Windows XP, Windows CE and DOS. Application examples and projects are included for each function, each board and each operating system, in order to provide a quick starting point for learning and development. Diamond Systems, Mountain View, CA. (800) 367-2104. [].

Core i7 COM Module with Improved Graphics and Performance Plus ECC RAM

A COM Express Computer-on-Module offers 32nm Intel Core i7 / Core i5 processor technology, high energy efficiency, wide graphics support, customizable PCI Express configuration and ECC dual channel RAM to ensure data accuracy. The ETXexpress-AI from Kontron comes in the COM Express Basic form factor and features the processor-integrated HD graphics with DisplayPort support. For safety-critical applications, the Kontron ETXexpress-AI integrates up to 8 Gbytes of ECC system memory and an optional Trusted Platform Module (TPM). The performance of the new Computer-on-Modules is scalable from the start with a choice of four different Intel Core i7 or Core i5 processors. By integrating the latest 32nm processor technology for power use efficiency, higher bandwidth and greater integration, the Kontron ETXexpress-AI COM raises the performance bar again. The new module not only speeds up multiprocessing tasks via hyper-threading technology (HTT), but also processes single-threaded tasks much faster thanks to the new Intel Turbo Boost technology. Depending on the processor, this allows individual cores to operate between 25% and 100% above the nominal clock speed without exceeding the defined TDP. The Kontron ETXexpress-AI is available with the 1.06 GHz Intel Core i7 620UE, the 2.00 GHz Intel Core i7-620LE, the 2.40 GHz Intel Core i5-520E, and up to the 2.53 GHz Intel Core i7-610E Processor. All versions support up to 2 x 4 Gbytes of dual channel DDR3 SO-DIMM modules with ECC and offer a comprehensive range of interfaces via the COM Express COM.0 Type 2 connector: 1x PCI Express Gen 2 graphics (PEG) (also configurable as 2x PCIe x8), 6x PCI Express x1, 4x Serial ATA, 1x PATA, 8x USB 2.0, Gigabit Ethernet, dual-channel LVDS, VGA and Intel High Definition Audio. Additionally, older non-PCI Express-compliant components can be incorporated via the integrated PCI 2.3 interfaces. The integrated Intel AMT 6.0 Active Management Technology enables out-of-band remote management. An 8V-18V universal power supply for simplified power distribution rounds out the feature set. Operating system support is offered for Windows 7, Windows XP, Linux (including Red Hat Enterprise, SuSE, Red Flag and Wind River Linux) and VxWorks. Kontron, Poway, CA. (888) 294-4558. [].

Rugged 3U OpenVPX Data Recorder with Eight 6 Gbit/s Links

A small form factor data recorder board enables system designers to quickly and easily integrate highvolume, continuous (streaming) data recording in a small compact package. The VR-7310 from Curtiss-Wright Controls Electronic Systems is designed for use in a broad range of space, weight and power (SWaP)-constrained critical applications in both manned and unmanned ground, air, and sea vehicles, including signal intelligence, image processing, FLIR radar, sonar, RF tuners, MRI and cameras. The VR-7310 storage includes eight external 6 Gbit/s SAS/SATA links that enable direct attachment to eight 1.8” or 2.5” drives deployed on disk carrier cards or VPX3-FSM Flash Storage Devices. The 3U VPX recording engine features an onboard XMC/ expansion site, supporting a wide variety of I/O such as Serial Front Panel Data Port (sFPDP), Gigabit Ethernet (GbE), 10GbE and analog I/O, as well as FPGA processing. The board’s AMCC 460SX CPU is supported with 2 Gbytes of DDR2 SDRAM memory for recording buffers. The Vortex software provides full access to a well-defined and fully documented interface to the data before it is written to or read from disk. Curtiss-Wright Controls also provides the XMLRPC API, which enables the customer’s application to control system operations including the number of channels to acquire, disk grouping, playback from offsets in the recording, disk group management. For custom applications, the Vortex software provides users with an easy to use API for creating high-speed recording systems with a wide range of I/O options. Curtiss-Wright Controls Electronic Systems, Dayton, OH. (937) 252-5601. []. RTC MAGAZINE APRIL 2010


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ACCES I/O Advantech Technologies, Arbor Solutions..................................................................................................................4........................................................................................................... End of Article Products

ATX Automation Technology Expo......................................................................................43...........................................................................................................


Get Connected with companies and Get Connected Extreme Engineering Solutions, Inc....................................................................................11............................................................................................................. products featured in this section. with companies mentioned in this article. Lippert Embedded Computers............................................................................................31......................................................................................................... MEN Micro, Inc.................................................................................................................36........................................................................................................ Microsoft Windows Get Connected with companies mentioned in this article. One Stop Get Connected with companies and products featured in this section. PC/104, PC/104 Express and ISM Showcase.....................................................................49

Pentek, Phoenix International.........................................................................................................41........................................................................................................... PLD Red Rapids, VDC VersaLogic Corporation.....................................................................................................15......................................................................................................... WDL XTech...............................................................................................................................55..................................................................................................

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RTC magazine  

April 2010

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