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The magazine of record for the embedded computing industry

March 2010



LightPeak—A First Peek at Intel’s Optical Interconnect Advances Multiply Embedded Memory Options New Designs Keep Cool in Smaller Spaces An RTC Group Publication




45 Fibre Channel XMC Interface for Embedded Hits 8 Gbit/s

46 6U VME Single Board Computer with Dual-Core Freescale Processor


48 PCI/104-Express SBC with Core2 Duo/Celeron M Processors

MARCH 2010


Editor’s Report

technology in systems

Optical Interconnects

Mechanical Design for Cooling


Editorial Software Quality a Matter of Life or Death—and Not Just for the User


Industry Insider Latest Developments in the Embedded Marketplace

technology in context

technology deployed


Small Form Factor Forum If You Can’t Take the Heat... Get out of the Stack

Embedded Memory Options


M2M Systems in Transportation

Phase Change Memory Will Change Memory System Design


Improving RAID Storage Systems with Nonvolatile Write Journals


Products & Technology Newest Embedded Technology Used by Industry Leaders

featured product

Enables MSI Support for all Operating Systems 44Hypervisor


Low-Cost Optical Interconnect Points the Way to Major System Developments Tom Williams

Jim Hardy, Objective Analysis

Ravi Prakash and Shivendra Singh, Cypress Semiconductor

technology connected Supervisory Systems


Autonomous UIs—A New Path for Customizing Application Look, Feel and Function Robi Karp, Fluffy Spider Technologies

Analysis and Heat Sink 28Thermal Design Optimize Cooling of HighPerformance Modules Michael Haskell, Advanced Thermal Solutions

Data in Real Time: Machine to Machine Systems 32Providing Smooth Transportation Kurt Hochanadel, Eurotech, Inc.

the Railway with Technology and Keeping Both 36Monitoring Running Dana Earl, Salient Systems and Russ Nieves, Xembedded

industry watch Advances in Processor Technology

Core i7: What It Means to the Embedded Market 40Intel’s Richard Kirk, GE Intelligent Platforms

Digital Subscriptions Avaliable at RTC MAGAZINE MARCH 2010


MARCH 2010 Publisher PRESIDENT John Reardon,

;HYNL[LKMVY! • Embedded


• Communication

EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

• Enterprise


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The magazine of record for the embedded computing industry

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Free Online Spotlighting the Trends and Breakthroughs in the Design, Development and Technology of Embedded Computers. Search Archived Editions along with the Latest News in the Embedded Community. An RTC Group Publication



To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, EASTERN SALES OFFICE The RTC Group, 3310 Twin Ridge Drive, Charlotte, NC 28210 Phone: (949) 573-7660 Editorial Office Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214 Published by The RTC Group Copyright 2008, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


Tom Williams Editor-in-Chief

Software Quality a Matter of Life or Death—and Not Just for the User


think it started with that little “check engine” light. I had for some years been blissfully driving a number of cars that were equipped with the enigmatic little light but had managed to avoid any concern because none of them had ever lit up. But now... The first thing I did was open the hood to check and yes, the engine was still there—but now what? A warning light like that is disconcerting because unless you have invested in one of those do-it-yourself scan tools, you don’t know if you’ve got a minor intermittent problem or some potential costly major failure staring at you. The only thing to do is to take the car in and trust the tender mercies of the repair shop or dealer. And I have a hard time trusting any of them, and the little light, now whether off or on, is a constant source of unease. It turns out that the little “check engine” light mostly monitors mechanical conditions, primarily those that might affect emission system compliance as mandated by federal regulations. In my case, a squirrel had started to build a nest in the duct leading to my air filter, but the service guy said, “The average ‘check engine’ costs around $350.” I got off for considerably less. Still, the light can also come on for much more serious problems. You can’t tell by just looking at it. More recently, however, we are facing cars with ever greater software content that affects not only the peripheral functions but also the vital operation and safety features of the vehicles. And when I refer to cars here, I’m also talking about the entire world of devices and systems that surround us all in our daily lives. Cars just happen to be the most familiar of such situations and the ones with the most immediate user interface that can directly affect our well being. As Toyota executives sit squirming before Congressional committees wishing they could just be waterboarded and have done with it, the suspicion is starting to turn toward “electronics”—read software—as possibly being behind a lot of the recent problems and is something that they really don’t want to talk about. And this does not just apply to Toyota. The software content of automobiles in general is on a rapid growth curve in engine control, braking systems, steering and more. In some cases, such as the systems that are designed to prevent rear-end collisions, it can actually make decisions for the driver.

Add to this the recent demonstration in which the police were able to contact OnStar and have a car-jacked vehicle remotely disabled, and we must realize that automotive software can also be susceptible to remote hacking. So like every other connected system on the planet, cars are also vulnerable to internal software bugs as well as to outside unauthorized access. What if some hacker got into OnStar and was able to send some global command that caused all OnStar-equipped vehicles to be disabled? There is, of course, a huge motivation on the part of developers to produce bug-free secure code for use in mission- and life-critical systems. In addition, there have been major advances in tools and methodologies to analyze code for correctness; there are seminars and courses devoted to bug-free software development and all of these are hugely positive advances. They are battling the twin dragons of increasing complexity and time-to-market (read $$$). The recent fiasco involving Toyota has shown us where concessions to the twin dragons can lead, especially when coupled with corporate arrogance. This can easily apply to vital systems outside the automotive arena as well. First, no amount of testing and verification can give 100 percent assurance that code will be correct under all circumstances. Why? Because the lab is not the real world. Because the time it would take to rigorously test and verify several million lines of C code to the point of 100 percent assurance would have to deal with the sun becoming a red giant. So we reach a level of comfort, or an estimate of liabilities. What you don’t do is what Toyota has done and try to convince yourself that everything is just fine. That is going to cost them billions. Far better to assume from the outset that there will be problems, however seldom or seemingly minor, but perhaps life-threatening. Having a staff and a protocol in place to examine, deal with and correct such things immediately does two things. For one thing, it avoids disaster of the scale we have witnessed with Toyota. Second, even if problems remain minor, it impresses customers in ways that will bear fruit well into the future by positioning the company as responsive, focused on quality and the customer. You can’t enter numbers for this into a spreadsheet, but the potential losses that can be suffered by not doing it should now be clear to all. RTC MAGAZINE MARCH 2010



INSIDER MARCH 2010 OpenVPX System Specification Ratified by VSO VITA has announced that the VITA Standards Organization (VSO) working group responsible for the VITA 65 OpenVPX System Specification has ratified the specification. The specification now meets the final criteria enabling balloting to proceed for ANSI ratification. The VITA 65 working group received the original body of work from the OpenVPX Industry Working Group in October of 2009. Since then, the VITA 65 working group has been resolving the last outstanding comments received during the balloting process. At the January VSO meeting, the required number of approvals was achieved, officially recognizing the specification as ratified by the VSO. Special acknowledgement should be made to Curtiss-Wright Controls Embedded Computing’s Pete Jha, chairperson of the VITA 65 working group, and Mercury Computer Systems’ Greg Rocco, lead editor of the VITA 65 working group, for their tireless contribution to the timely ratification process, and congratulations to the rest of the working group members. VPX is a broadly defined technology utilizing the latest in a variety of switched fabric technologies in 3U and 6U format modules. OpenVPX is the architecture framework that defines system-level VPX interoperability for multivendor, multimodule, integrated system environments. The OpenVPX framework delineates clear interoperability points necessary for integrating module to module, module to backplane, and chassis. OpenVPX recommends but does not specify development systems to assist in VPX system evaluation, prototyping and development. OpenVPX will evolve and incorporate new fabric, connector and system technology as new standards are defined. The working group will now submit the specification to a larger body of interested parties for balloting as part of the process to gain ANSI ratification. This process is expected to take 2-3 months, after which time the specification will be available to designers in the industry.

Xilinx Picks 28nm Process to Accelerate Platforms

Xilinx has announced the foundation for a next generation of programmable platforms to address what it calls the “Programmable Imperative.” That refers to today’s numerous trends—the exorbitant cost of designing and manufacturing ASICs, rapidly evolving standards, the need to reduce bill of materials, and the need for both hardware and software programmability, all in the face of rough economic times and reduced staffing. These, Xilinx maintains, are converging to create an environment where electronics product designers are increasingly looking to FPGAs as alternatives to ASICs and ASSPs. Xilinx has chosen to maximize the value of the 28nm technology node by choosing a highperformance, low-power process technology, a common scalable architecture across product ranges, and tool innovations so customers will have FPGAs that de-



liver the ASIC-class capabilities they need to meet their cost and power budgets, while improving their productivity through easy design migration and IP reuse. At the same time, power management and the impact it has on system costs and performance is a paramount concern to today’s electrical system designers and manufacturers. Compared to the standard high-performance process, the high-performance, lowpower process delivers FPGAs that are 50% lower in static power. Meanwhile, next-generation development tools reduce dynamic power as much as 20% through innovative clock management. Enhancements made to Xilinx’s partial reconfiguration technology will enable designers to further drive down power consumption and lower system costs by 33%. To address system performance bottlenecks caused at the interconnect level, Xilinx will provide the industry’s highest performance interfaces to support cus-

tomers who need high-bandwidth chip-to-chip, board-to-board and box-to-box connections. This is of critical importance as customers increasingly look to FPGAs to become a major, if not central, component of their systems, and helps define how the next generation of FPGAs will enable customers to build their systems when ASIC and ASSP options are unavailable.

SFF-SIG Adopts CoreExpress Spec to Strengthen PCIe 2.0-Ready COM Portfolio

The Small Form Factor Special Interest Group (SFF-SIG), a collaboration of suppliers of embedded component, board and system technologies, today announced the adoption and release of the CoreExpress Specification revision 2.1. CoreExpress was originally developed as a proprietary standard by Lippert Embedded Computers GmbH. Under the terms of an agreement between SFF-SIG and Lippert, the entire

embedded community will now be able to develop CoreExpress modules and applications without regard to confidentiality and without royalties of any kind. Use of the CoreExpress logo will require membership in SFF-SIG. The newly released version of the specification contains a number of enhancements proposed by SFF-SIG members during the evaluation process. These include the support of the emerging DisplayPort interface and the addition of sufficient reserve pins to enable upward compatible support for USB 3.0 in the future. The new version is upward compatible from the current CoreExpress 2.0 version previously published by Lippert. CoreExpress uses a single connector baseboard interface, eliminating the registration problems frequently found with twoconnector Computer-on-Module products. Fully digital to reduce system noise and EMI, CoreExpress is the smallest x86 computer-on-module in the market, measuring a mere 58 x 65 mm. With dedicated interface pins for optional CAN bus support, CoreExpress ushers in a new era of “application COMs” tailored for vertical markets. Three characteristics establish the CoreExpress Specification as the first of a new generation of Computer-on-Modules. First, the connector used by CoreExpress modules has been confirmed to operate at the speeds required for PCI Express Generation 2. Secondly, the specification contains an option to configure the SDVO interface pins for the new DisplayPort interface. Third, sufficient reserved pins are included in the definition to enable inclusion of at least two USB 3.0 ports in a future release of the specification. The CoreExpress baseboard interface includes PCI Express

(configured as one x4 lane or four x1 lanes), RGMII Ethernet, 2 SATA ports, 1 CAN port, 8 USB 2.0 ports (one of which may be configured as a client), LPC bus, SM bus, High Definition Audio, SDVO (multiplexed with Display Port), 24-bit LVDS flat panel interface, backlight control and an SD/SDIO/MMC 8-bit interface. The CoreExpress Specification is available for download from the SFF-SIG Web site at www. CoreExpress modules are available today from Lippert Embedded Computers.

OpenSAF in Commercial Deployment

The OpenSAF Foundation, the not-for-profit organization supporting the Open Service Availability Forum (OpenSAF) open source high-availability middleware projects, has announced that Ericsson has deployed the OpenSAF technology in carrier networks. This represents the first public statement by a major equipment manufacturer on commercial adoption, development and deployment of OpenSAF. Since its launch in January 2008, the OpenSAF community has released two major versions of the code base, incorporating over 200 significant contributions, with hundreds of downloads of the releases. The number of developers and users is growing continuously and the high-availability software and systems expertise within the project is extremely high, resulting in a level of quality required to deploy in carrier networks. “Ericsson’s commitment to OpenSAF in their commercial products is significant” said Alan Meyer, president of the OpenSAF Foundation. “Multiple other companies are also contributing to the OpenSAF code base as well as using OpenSAF for commercial developments. Like Ericsson,

many of these applications are in communication networks, and we anticipate further public success stories in the future.”

Open-Silicon and Virage Logic Partner for Low-Power SoC Design

Open-Silicon and Virage Logic have announced a partnership agreement to provide customers with comprehensive design solutions including access to Virage Logic’s extensive Physical and advanced Interface intellectual property (IP) portfolio. In particular, as more and more customers develop energy-efficient devices, Virage Logic’s low-power IP combined with Open-Silicon’s lower-power design technology enable the development of significantly lower power silicon. The partnership presents a well-aligned technology offering. Virage Logic, a leader in lowpower semiconductor IP technology, uses several advanced power management features within the SiWare Memory compilers and SiWare Logic libraries that enable customers to dramatically reduce leakage current while maximizing performance. Open-Silicon’s VariMAX back biasing technology similarly works with Virage Logic’s tapless SiWare Logic standard cell libraries to reduce leakage for the IC’s logic. By changing the amount of bias used on individual chips, VariMAX effectively tunes the silicon for optimum power and thereby boosts production yields. This latest collaboration builds on a recently announced co-developed test chip with working silicon running at 1.1 GHz that was achieved using Open-Silicon’s patented CoreMAX performance enhancement technology and Virage Logic’s advanced SiWare Memory compilers. “As power management and efficiency are becoming increas-

ingly critical in a multiplicity of products and technologies, our collaboration with Open-Silicon underscores how we are working with our design ecosystem partners to help SoC designers address these challenges,” said Dr. Alex Shubat, president and CEO of Virage Logic. “Open-Silicon’s MAX Technologies working in conjunction with Virage Logic’s extensive semiconductor IP portfolio enables our mutual customers to address a broad range of SoC design requirements.”

Mentor Graphics Acquires Virtual Garage from Freescale

Mentor Graphics Corporation has announced the acquisition of the Virtual Garage product line from Freescale. Virtual Garage is a software suite that addresses two important topics within the design and management of automotive electrical and electronic systems: the trade-off between value-ofvariety and cost-of-complexity caused by optional electronic content; and provision of vehicle-specific design data, such as dynamic electrical schematics, on demand to service networks. Both topics carry significant profitability implications. Virtual Garage is seen as highly complementary to Mentor’s CHS software for electrical systems design and wire harness engineering. Virtual Garage expands Mentor’s scope both upstream into product planning, where decisions about product configuration complexity significantly impact long-term costs, and downstream into the key area of online service documentation for dealer networks. The Virtual Garage products add significant value across the supply chain. Mentor has acquired the relevant intellectual assets and the key architects of the solutions. Mentor also acquired

one key commercial contract under the acquisition. Following this technology acquisition, Virtual Garage will be incorporated into Mentor’s automotive industry product portfolio. Virtual Garage will also be featured in several sessions at the upcoming IESF conference in Detroit on March 18, 2010.

ZigBee Alliance Begins Certification for Sub-1 GHz Platforms

The ZigBee Alliance has announced it is now offering certification for ZigBee platforms designed to operate in the regional sub-1 GHz unlicensed frequencies. More semiconductor manufacturers and Alliance members are seeing a growing market for a range of ZigBee device options using the ZigBee specification. The Alliance recently completed its first series of multi-vendor interoperability tests for sub-1 GHz platforms. These platforms will become the Golden Units against which all other platforms seeking certification will be compared. They offer the same underlying functions and robust capabilities as existing ZigBee-compliant platforms operating at 2.4 GHz. Atmel Corporation, Exegin Technologies and ZMDI are leading this effort in conjunction with ZigBee Alliance’s accredited test houses, National Technical Systems, TRaC Global and TÜV Rheinland. The ZigBee specification has always supported sub-1 GHz platforms, but offering certification of platforms built to the specification requires at least three independent implementations for initial testing and validation. This rigorous certification requirement ensures that Alliance members only deliver interoperable solutions to the marketplace. RTC MAGAZINE MARCH 2010




Colin McCracken & Paul Rosenfeld

If You Can’t Take the Heat… Get out of the Stack


n spite of the new ultra-low-power silicon on the market, it’s tempting to bite off more than you can cool. If you ‘duo’ (do), you can blow your diet threefold—first, you can kill your expensive CPU; second, you add the cost of the 500W power plant required to boot it; and finally, you lower reliability with the CPU cooler and system fans (including the fans to cool the power supply). It’s even worse if your system requires a high-end graphics card that also requires cooling. And don’t forget to budget for the inefficient / unconverted power of the supplies themselves—ten watts or more—since that heat also must be removed. Job security for your thermal engineer. Full-size ATX motherboards spread out the hot CPU and graphics cards longitudinally, and Rambo fans provide forced-air cooling to the tune of hundreds of linear feet per minute. If the fans fail, the system overheats and shuts down, with no damage other than user inconvenience and a service call. The situation is complicated when re-purposing this desktop technology for the small form factor world. Move from an indoor to an outdoor environment, such as a vehicle, and the ambient temperature baseline can jump up dramatically. Low-voltage (LV) and ultra-lowvoltage (ULV) processor SKUs suddenly become well worth the price premium. But first download the processor datasheet to see whether the Tj max—the on-die transistor junction temperature maximum specification—is 100°C or only 90°C. Industrial and military systems are often specified up to 85°C. Forced-air cooling is typically not allowed. When fan bearings go, blue screens and smoke screens can cause collateral damage. Alternatives to heat sinks and fans are needed. The lower the temperature to which the electronics are subjected, the better the reliability / MTBF will be. PC/104 stacks have been popular in tight spaces such as military, vehicle and aircraft applications. Unlike the motherboard example above where the heat is spread out, the heat generated by the CPU, graphics and power supply are combined into the same vertical stacking chimney. Without adequate cooling, the best-case scenario is reduced operating lifetime (shortened MTBF). The worst-case scenario is thermal runaway, where heat generated exceeds heat removed, and the tem-



perature keeps rising… a ‘smoke stack’ reminiscent of Three Mile Island. Heat pipes can solve this dilemma. With heat pipes, the heat is neither created nor destroyed, just moved to a location far away from sensitive electronics where it can be safely absorbed and dissipated, such as the system enclosure or a large heat sink. However, these solutions are expensive for this low-volume, highmix market because they are custom-fitted to each unique board/ stack/enclosure. And the need to increase the board-to-board stack height from 0.6” to 0.9” to make room for the heat pipe and aluminum block adds more cost and might mean that the proposed next-generation board set won’t fit in the space allotted. Enter computer-on-modules (COMs) to the rescue. Rather than insisting on stacking up and down, COMs make an important simplifying assumption, which has a side benefit for thermal designers—they only stack downward. As a result of the strict top side height limit, heat spreaders can be installed on the top surface to bring the same low-cost thermal relief to the x86 community that analog designers have used for many decades. The ultimate thermal solution consists of directly coupling multicore processor and chipset heat to the flat metal heat spreader plate, which is then attached to the outside cabinet or system enclosure. Recall that thermal rise equals the power dissipation in watts times the ‘thermal resistance’ in degrees C per watt. Aluminum and copper have low thermal resistance making them ideal for a heat spreader. The weakest link is usually the thermal grease or gap filler pad in the case of a heat spreader plate, or a heat sink in a low airflow environment. Expect a 10 to 15 degree rise from ambient to thermal junction depending upon the processor’s thermal design power (TDP) rating and the resistance of the thermal solution. This means that the processor die could still be running at 90°C if the air outside the thermal solution is 75°C. Be especially careful of Atom SBCs that claim to support 85°C because only very few Atom processor models have a high enough junction temperature rating to support +85°C correctly. More efficient processors and chipsets coming down the road will re-invent this market. Until then, thermal analysis remains a critical part of your design.


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editor’s report Optical Interconnects

Low-Cost Optical Interconnect Points the Way to Major System Developments The soon to be deployed LightPeak serial interconnect is an optical link that may be the herald of a new age of data transfer between systems, peripherals and even between components within a system.

by Tom Williams, Editor-in-Chief


iber optics is certainly not new to computer systems. Fibre Channel, for example, has been around for years and we are starting to see Ethernet over fiber links; telecom has used it for quite a long time. The list goes on. Still, a development coming out of Intel may push fiber optical links to an almost ubiquitous presence first in PCs and consumer products and then, inevitably, in embedded systems. Called LightPeak, it is being readied as a two-port optical module with each port having a transmit and a receive fiber cable. The initial offering is expected to have a data rate of 10 Gbit/s with the potential to increase the speed to 100 Gbit/s. It will leapfrog the speed of copper wire serial interfaces such as USB 3.0 and bring some of the inherent advantages of optical data communication along, includ-



ing immunity from EMI, a much longer data path and less weight—a prime consideration in areas like aerospace. The big difference that LightPeak makes is that up until now, optical technology has been in use in the data center and in telecom transceivers but is now being tailored to the size, ease of use and cost requirements of consumer electronics and PCs. This presages the next stage of the familiar pattern that when a technology achieves widespread deployment in those areas, economies of scale will make it attractive to the embedded market where size, power consumption and, above all, cost are the most significant factors determining acceptance. The technology that is currently under development expects to have components ready to ship to manufacturers a little later this year and to see first deployments of

products sometime next year. The current module design is implemented on a 12 mm x 12 mm platform that includes an optical module with an optical IC to which are connected the lasers, the photo detectors and the optical cables. In addition, there is a controller IC to which a connector on the module plugs into the port on the system or the peripheral (Figure 1). The lasers and photo detectors in the initial version are off-the-shelf components that also exist for other applications, but Intel is doing research on integrating both onto a silicon chip. It might be tempting to think of LightPeak, as some have done, as a leap beyond some mythical USB 4.0, but its potential is far greater than just a quantum leap in data rates. Intel has expressed its vision as providing a standard, low-cost, optical-based interconnect that can serve as a common optical I/O infrastructure “for the next decade and more.” That is, providing a single, flexible cable that will be able to carry any platform I/O. This would seem to imply that LightPeak would serve not only as an interconnect between systems and between systems and external peripherals, but also as an inter-component/peripheral interconnect within a system. To make this possible, Intel is developing a common transport protocol for LightPeak that can encapsulate other mature I/O protocols—such as USB, HDMI, Display Port, PCIe, SATA, etc.—and interleave them in a single 10 Gbit/s (later 100 Gbit/s) data stream and deliver them to their appropriate end points over a single optical fiber (or fiber pair in the case of two-way communications). While the architecture supports encapsulating a comparatively large number of I/O protocols, the specific product implementation would have some subset of these that would support PCIe, SATA, etc., while a video port might carry HDMI, VGA, Display Port, or other video protocols. A hypothetical system bus fiber link might support another selection or combination of protocols. Exactly which protocols these are to be and how they are to be combined would depend on a combination of driver soft-

editor’s report

ware and modifications to the design of the controller IC. According to Jason Ziller, who heads Intel’s Optical I/O Project Office, “Our initial focus is on external cable I/O because that’s in the shorter term the greater need. But our expectation is that down the road optics will be used even inside the platform as the speeds you require between two points on the platform get so high that you really can’t do it any other way.” Another aspect of the LightPeak specification is the issue of providing power to peripherals. We have gotten used to this little convenience from USB, where it is not universally available but can be offered on certain ports that are optionally designed to provide from 100 mA to 500 mA at 5V. On the one hand, LightPeak will be capable of supplying more power over an optional copper wire since the electrical current can’t interfere with the light signals. On the other hand, there will be a constraint on the distance that power can be delivered for a given gauge of wire. These constraints will have to be spelled out in detail in any specification or standards document. The speed of adoption of a technology like LightPeak is a bit of a “chickenand-egg” situation in that it will depend on the growth of an ecosystem of not only systems, but also peripherals that incorporate the interconnect. This in turn will depend on adherence to a specification and eventually to a standard. Intel is also, wisely, in contact with other major companies about what their ideas might be in this area while at the same time continuing to refine its own specification. Components will be available this year and some system solutions next year. However, it is reasonable to expect it to take somewhat longer for an actual standard to evolve and get into place. In the meantime, it is a good idea for the major players to collaborate ahead of that.

Beyond LightPeak

As noted, the current implementation of LightPeak uses discrete lasers and photo detectors electrically connected to a silicon chip in what is known as silicon pho-

1x2 Arrays


2 Link IC PCB

4 Fibers Tx1 Tx2 Clk Rx1 Rx2

Optical IC


Alignment hole

Controller Chip


12mm x 11mm

Light Peak Optical Module

Figure 1 The LightPeak optical module is a 12 mm x 12 mm device that includes the optical IC, two lasers and two photo detectors, each of which is connected to a transmit or receive fiber cable respectively.

tonics. However, research is moving rapidly forward toward integrating both lasers and photo detectors directly on the silicon. The very promising photo detector side of this is a silicon-based avalanche photo detector (APD). In the APD, incoming photons strike a germanium layer where they create an electron-hole pair. The electron continues through the germanium into a silicon multiplication region, while the hole is collected by the germanium layer. In the silicon region, the electron collides with silicon atoms creating more electronhole pairs with each collision. The holes continue to move up toward the germanium layer. A series of collisions can result in as many as 20 electrons from the initial collision—hence the term avalanche photo detector. These become an electrical signal, which is passed over a conductor and detected as an electrical pulse. Intel says that the APD has the highest gain-bandwidth product ever seen (340 GHz). Gain-bandwidth multiplies the de-

vice’s amplification capability by the highest speed signal that can be detected. The results are that the current state of the art can be used for APDs for optical links of up to 40 GHz. The research is a joint effort by Intel and DARPA. The other recent breakthrough is the hybrid silicon laser, which involves the direct implementation of a low-cost light source on silicon rather than an attached pre-fabricated laser. The term “hybrid” refers to the use of silicon and an indium phosphide-based material bonded to a silicon waveguide that forms the laser cavity (Figure 3). The promise is that hybrid silicon lasers could be built using lowcost, high-volume silicon manufacturing techniques because bonding the indium phosphide to the silicon does not require precise alignment. Performance and routing of the light signal is determined by the silicon waveguide. We’re not there yet, but the implications of silicon photonics could be huge RTC MAGAZINE MARCH 2010


editor’s report

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Untitled-4 1


1/21/10 3:11:55 PM

Figure 3 When voltage is applied to the electrodes of the silicon and indium phospide hybrid laser, current flows with the electrons (-) and holes (+) combining in the center to generate light.

with the interfaces to silicon logic devices—imagine CPUs, memory devices, peripheral chips and even FPGAs—consisting of integrated lasers and photo detectors that could transport data via whatever communication protocol seemed appropriate to an application over a single optical pathway within a system. This could greatly simplify system design by reducing or eliminating all the electri-

cal noise and interference problems connected with designing high-speed copper traces on circuit boards as well as reducing the number of such paths needed to implement a system. Intel. Santa Clara, CA. (408) 765-8080. [].

Technology in


Embedded Memory Options

Phase Change Memory Will Change Memory System Design Dramatic changes are coming to the way nonvolatile and volatile memories are used, and with these changes firmware will evolve to take advantage of the new memory topology, making systems less complex, more reliable and lower in cost. by Jim Handy, Objective Analysis





NAND NOR 103 Electrons per Gate

hase Change Memory or PCM is a new memory technology being explored by several companies. This technology fits between today’s volatile and nonvolatile memory technologies to provide features that appeal to system designers who have had to work around the idiosyncrasies of existing memory technologies for the last several years. PCM is simple enough to use so designers can begin to forget all the strange work-arounds they must use now to design NOR or NAND flash into their systems. PCM also helps realize some significant improvements in time-to-market as well as related improvements in performance, cost and code density. In certain cases, designers will find it worthwhile to rework existing designs to convert them from flash to PCM. Many designs should also be able to reduce or even eliminate a RAM chip that was once required to compensate for flash’s slow and messy programming protocol. To help illustrate the strengths and weaknesses of today’s dominant memory technologies against PCM, Table 1 presents the performance of seven key metrics for each of three technologies: DRAM, NAND flash and phase change memory (PCM). Relative performance for each technology is given for sequential and random read and write, power consumption, volatility and cost per bit.


10 1000mm

100mm Process Geometry


Figure 1 In both NAND and NOR flash, the electrons per bit are rapidly declining with reduction in process geometry to the point of unreliability.

Why PCM? Why Now?

Why is PCM interesting and why is it now reaching production? There are several reasons for both. The biggest reason that PCM has been unable to make its mark in the market today is that existing memories have proven to be far more eco-

nomical than any new alternatives. This has been the case for quite a long time, shutting any newcomers out of the market. On any given process, these alternative memories have either suffered from having a larger die size than their entrenched competition, or the wafer processing costs

technology in context

prototype in 2004 that is a precursor to impending production. Shortly afterward Numonyx announced a prototype PCM device that started shipping in limited pro-

duction toward the end of 2008. One other company—BAE Systems—has been shipping its C-RAM chips into the aerospace market since 2006. This market is inter-

Reset Pulse: Causes Region to Become Amorphous

Set Pulse: Causes Region to Crystallize



Figure 2 Heat pulse level and duration required to set and reset the chalcogenide material in a phase change memory.

PCM Cross-Section Metal Interconnect

Polycrystalline Chalcogenide


have been significantly higher. Cost is everything in the memory market, so any chip with a higher manufacturing cost doesn’t stand a chance of displacing any existing technology. This will change soon, as PCM costs close the gap with DRAM over the next few years. On the positive side, there are a few reasons why PCM has recently become attractive. For one, materials have progressed significantly over the past decade and it is now much more feasible to produce the high-purity thin films that are required by the phase change material. Also, there have been numerous breakthroughs with the chalcogenide materials used in PCM because they have been used in high volume to manufacture both CD-R and CD-RW disks. Along with this has been a vast increase in the understanding of the physics of these materials. Process shrinks have played their part: In the past, the amount of material to be heated was relatively large, requiring significant energy to achieve a phase change. As processes have shrunk, what once seemed like an ocean of material to heat has now plummeted to something more akin to a bathtub. Finally, a general acknowledgement that flash memory will soon reach its scaling limit has added impetus to develop follow-on technologies that will continue to scale past this limit. Although flash’s scaling limit has been postponed for a number of years, all flash makers agree that there will soon come a time when flash can no longer be shrunk to the next process node and the industry will have to change technologies. Figure 1 illustrates the phenomenon behind this scaling limit: the number of electrons stored in a flash bit is on a steady decline. The graph indicates that both NAND and NOR flash could store fewer than 10 electrons per bit before either of these technologies reaches the 10nm process node in about eight years. Ten electrons is far too few to store multiple bits in MLC in a noisy environment, so the minimum required number of electrons is significantly higher than 10, closer to 100 per bit. Even at this level the low number of electrons makes it difficult to meet the reliability requirements of existing applications. Phase Change Memory is already available. Samsung announced a PRAM

Programmable Volume

CMOS Logic

Figure 3 In PCM, intense localized Joule heating induces a shift in the chalcogenide material from amorphous to polycrystalline and back with differences in electrical resistance that correspond to 1s and 0s.



technology in context



PCM Fast

Sequential Read



Random Read




Sequential Write




Random Write














Nonvolatile Cost

TABLE 1 Comparing DRAM, NAND and PCM

ested in PCM since it is immune to bit errors caused by alpha particle radiation. Those designers who have been able to try out these parts report to us that they are pleased to find that the technology removes a number of obstacles they have had to work around when using older, more conventional memory technologies. To understand the enthusiasm designers have for PCM we must consider how memory is used in the system. A typical system will use both some type of nonvolatile memory for code storage and some type of RAM as a scratchpad and sometimes to store other code. In order to keep the programmer from having to work around the different memory types, operating systems hide the differences between each type of memory and perform the task of managing the volatile and nonvolatile memories in a way that is transparent to the other programs. This adds a considerable amount of complexity to the system. Even with this help, the programmer is under some constraint to fit the code into the read-only code space and the data into the read-write data space. If either code or data grows larger than the size of its memory, even by a single byte, the size of that portion of memory must be doubled at a significant price increase. In some cases this can be avoided in a PCMbased system. Phase Change Memory has changed the rules of the game. No longer must code and data be split between two fixed-size banks of NVM and RAM. Code and data may be contained within a single component. For small system designers this reduces chip count and power consumption. Designers of both large and small systems



will appreciate the fact that there is no longer a fixed delineation between read/ write and read-only memory.

Intricacies of Flash

Flash memory is difficult to manage. One designer we interviewed referred to the process of managing flash as a “very involved dance.” Those who have designed with either NAND or NOR flash will attest to this. Flash management involves a number of considerations like wear leveling, read-while-write and bad block management that make this task extraordinarily complex. Phase Change Memories present considerably fewer problems than do flash designs. PCM is byte-alterable so there are no erase blocks as there are in both NAND and NOR flash. This vastly simplifies writes. Writes do not need to be preceded by an erase cycle—in PCM ones can be changed to zeros and zeros can be changed to ones. A PCM’s write is more like a write to a RAM than to either NAND or NOR flash. PCM has fast write cycles with no need for the erase required by NAND and NOR. This removes the need for a concurrent read/write capability, and programmers will rarely, if ever, need to write code to prevent reads from occurring near a recent write. PCM has random NOR-like or SRAM-like addressing that perfectly matches what the processor wants to see. Furthermore, PCM does not require the error correction used with NAND flash since all bits are guaranteed to contain the same data that was written into them. All the algorithms that are required to manage flash with wear leveling and

bad block management are quite simply unnecessary in a PCM environment. Some call PCM: “A firmware/software engineer’s perfect nonvolatile memory.” There is also a benefit to the programmer, since the boundary between code and data space is more flexible than it has been. In today’s designs each memory application requires its own unique memory topology, commonly: • NOR and SRAM • NOR plus NAND and SRAM or PSRAM • NOR or NAND plus DRAM or mobile SDRAM These systems rarely use the nonvolatile memory to store temporary data, and can never use the RAM to store code, since the contents of the RAM disappear upon power loss. PCM helps to simplify these configurations. A single PCM chip or a PCM-only array will store both code and data, often removing the need to pair a RAM chip with a nonvolatile chip. As an added bonus, the programmer need now worry only about the size of the code plus data, rather than about the code space and the data space as two separate areas. If the data space increases by a couple of bytes, perhaps there will be room that can be “borrowed” from the code space. This luxury is simply unavailable in a non-PCM topology.

How PCM Works

Phase Change Memory uses the changing state of a special material to determine whether a bit is a 1 or a 0. The phase change memory’s two states are “crystallized” and “amorphous.” Like a liquid crystal display blocks light or allows it to pass through, depending on a crystal’s orientation, the chalcogenide glass that is used for bit storage in a PCM either allows current to pass (when crystallized) or impedes its flow (when amorphous). Bits are changed from a crystalline state to an amorphous one via a tiny heater at each bit location that melts the glass then cools it in either a way to allow crystals to grow or to keep crystals from growing. A set pulse,raises the temperature to melt the glass and holds the temperature at that level for a time, ramping it down once crystallization has begun. A reset pulse

technology in context

quickly raises then lowers the temperature before the melted material can form any crystals. This results in an amorphous, or nonconducting, organization of the material at that location (Figure 2). Since very small heaters are used, they can heat the material very rapidly for a tiny location—on the order of nanoseconds. This allows fast writes to be performed and prevents adjacent bits from being disturbed. Furthermore, these heaters shrink along with process geometry shrinks, which will make parts produced with a smaller process easier to program than their large-geometry predecessors. This technology is expected to shrink well beyond the limits of NAND and NOR flash (Figure 3). Speeds are comparable with flash today and will later approach the speeds of DRAM. From a system architecture viewpoint, one beauty of PCM is that there is no block erase—each bit can be set or reset at any time independently of all the other bits. This gets past the limitations that block erase imposes on both NAND and NOR flash. Memory chip prices are highly dependent on production costs, and Objective Analysis projects that PCM makers will take steps to bring their costs down to those of competing technologies. Today PCM sells for roughly 25 times as much per gigabyte as does DRAM, but PCM uses smaller cells than do leadingedge DRAMs, so PCM manufacturing costs should be able to fall below those of DRAM, once wafer and process equality is reached. As the technology gains parity with DRAM in process geometry and wafer diameter, and as unit volume grows large enough to impact economies of scale, PCM will cross below DRAM’s average price per gigabyte, a situation the market should expect in 2015-16. Further cost reductions will become possible as PCM migrates to multi-level cells, when the technology’s cost can be expected to fall to less than half that of DRAM, making it the second least expensive technology after NAND. It is not too early to start paying attention to phase change memory. We know that flash is approaching its inevitable scaling limit, and that some other technology

like PCM will eventually take the place of flash. PCM makers indicate that this technology will reach price parity with DRAM in the middle of the decade, a change that will start a whole new way of thinking about memory system design. Objective Analysis. Los Gatos, CA. (408) 356-2549. [].

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Numonyx. Folsom, CA. (888) 466-8666. []. Samsung Semiconductor. San Jose, CA. (408) 544-4000. [].


1/20/10 9:38:50 AM RTC MAGAZINE MARCH 2010

Technology in


Embedded Memory Options

Improving RAID Storage Systems with Nonvolatile Write Journals Write journaling is essential to the reliability of RAID systems. The performance and efficiency can be greatly improved by combining write journaling techniques with nonvolatile memory technology that can respond to and recover more quickly and reliably from power failures. by Ravi Prakash and Shivendra Singh, Cypress Semiconductor


hen RAID was first introduced, the term was defined as “Redundant Array of Inexpensive Disks.” It has now become a blanket term for data storage schemes with better fault tolerance and input/output (I/O) performance than a single disk drive or “Just a Bunch of Disks” (JBOD). RAID commonly represents a system consisting of many storage disks that are accessed by servers through high-speed communication channels. The I/O performance of disk drives has always been the major bottleneck for any system requiring access to huge amounts of storage, and there were several efforts being made at that time to increase the throughput of disks through mechanical means. Such efforts, however, led to cost increases of these high-density, high-speed disks, making them unaffordable for small businesses. RAID was developed to address all the above shortcomings and has became a popularly accepted approach based purely on principles of redundancy and parallelism, which allows the use of inexpensive storage media to achieve very high performance and safety from disk



Storage Box Ethernet / FC Switch


RAID Controller Network

Flash nvSRAM


Battery SATA / SAS Expander

Figure 1 RAID Storage System Architecture

failures. The popularity of RAID was further boosted by the success of the Internet, which generated huge demand for high-performance data storage and management systems. Over time, the definition of RAID has changed to “Redundant Array of Independent Disks,” making the term more generic and applicable to

higher cost disk drives like SAS, solidstate drives and others. There are different implementations of RAID systems suitable for different applications. Most of these implementations were suggested in the original Berkeley RAID paper and some were invented based on industry needs. These

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technology in context

Journal Log entry 1.1 NV RAM

HOST Data1 RAID Controller (SAS, SATA Controller)

(Journaling & Configuration)

FLASH (Firmware)

Journal Log entry 1.2



Data1 Cache

(Journaling & Configuration)


FLASH (Firmware)

Battery Backup


(Journaling & Configuration)

FLASH (Firmware)


Cache (DDR) Battery Backup

RAID Controller (SAS, SATA Controller)


Cache (DDR) Battery Backup

1. RAID Controller acknowledges write completion to the host 2. Internally moves the data from Cache to disk drives 3. Logs entry 1.2 “Data 1 moved to the disk drives” to journal

HOST RAID Controller (SAS, SATA Controller)

Write Complete Notification: Data1


1. Host send data to write onto disk 2. RAID Controller sends Data 1 to the Cache 3. Logs entry 1.1 “Data 1 stored in the cache” to journal

Read Journal Back


HOST Journal Log entry 1.3 & 2.1 Data 2 NV RAM RAID Controller

(Journaling & Configuration)

FLASH (Firmware)

Recovery from power or disk failure done by running through journal log to identify all steps completed up to failure point.


Data 2

(SAS, SATA Controller)



Cache (DDR) Battery Backup

1. Host is free to send next data block to RAID controller 2. Drive acknowledge completion of write operation 3. RAID controller logs journal entries 1.3 (Data 1 write completed–Disk2 write failed) and entry 2.1 (Data 2 stored in Cache”)

Figure 2 RAID Controller: Data flow showing the sequence taken when there is a power failure.

different implementations are referred to as RAID “Levels,” which are differentiated based on parallelism, redundancy and duplication.

RAID Controller Architecture

Figure 1 shows a generic RAID storage system architecture. The data from the servers connected on the network is received by a switch, which directs this data to different storage boxes. The processor in the storage box also interacts with multiple storage boxes through the switch to enable virtualization. The data received by the processor is sent to the RAID controller. The RAID controller may be implemented in software or in hardware as a RAID on Chip (RoC). A software implementation of RAID is typically done on the motherboard chipset. The RAID controller has direct access to the cache memory that enables fast read/write access to the storage system. The cache is used to write the data in transition. The RAID system uses a cache to speed up the apparent I/O performance of the storage system so that


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the host processor is available for other tasks. In modern RAID systems, the size of these cache memories is very large and typically use high-speeds SDRAMs. A read cache memory is used to speed up the read process by predictive caching of expected reads. This cache memory helps reduce disk drive seek latency for read accesses by the processor. The write cache is one of the most important components of a high-performance RAID system. A RAID write may operate in two different modes. In write-through mode, the data sent by the host is directly written to the disks by the RAID system and the cache is bypassed. The host waits for the RAID controller to signal completion of data write before sending the next data. Though the write throughput in this mode is significantly lower, it ensures integrity of the data as the host is only acknowledged when the data is committed to the disk In write-back mode, the RAID controller writes data from the host to the cache memory and acknowledges write completion to the host. The host is free

technology in context

NV Array (SONOS) SRAM Reliable NV (20yrs) AutoStore Software Store 200,000 STORE

High Speed Infinite Writes

Figure 3 RAID Controller: Data flow showing the sequence taken when there is a power failure.

to perform other tasks while the RAID controller transfers the data from the write cache to the disk drives. Although this approach significantly increases write performance, the actual transfer of data to the disks is transparent to the host. This raises a potential risk to data integrity in case of power failure after the host has acknowledged the write but before the data is committed to disk. There are several ways to improve data integrity while using a write-back cache, with the most important method having a reliable power backup for the cache.

failure, disk failure, or any other failure that inhibits the completion of data movement from the cache to disk drives may lead to system failure. Consider a situation where the storage system acknowledges the host after writing data into the cache, but the power goes off before the system transfers the data from cache to the physical drives as shown in Figure 2. The data stored is usually secured using a battery backup that retains the contents of the cache even during power failure. On the next power up, the storage system has to track back each transaction to find which blocks of data were not written onto physical drives. Therefore, even with battery-backed cache, system recovery time may be significant as the system needs to be checked for the exact point of failure before recovery can begin. To avoid such recovery delays, many storage systems log each transaction of data from the host to the cache and from cache to the disk in a nonvolatile circular buffer. During the next power-up, this log can be retrieved to identify the state

of the storage system before failure and substantially speed recovery. This method is called write-in-progress record or write journaling.

Choice of Memory Device for Write Journaling

Choosing the right nonvolatile memory type for write journaling is important for performance and reliability of a RAID system. While a RAID system can use battery-backed DDR cache for data caching, its use for write journaling is not appropriate for several reasons. In practice, large blocks of data are being written to the DDR cache continuously at very high speed. However, only small blocks of data are being written to the journal memory. Using a part of DDR cache as a write journal requires the system to stall to complete writing journaling data. This, in effect, leads to inefficient usage of cache bandwidth and adversely impacts regular RAID performance. In addition, placing the journal memory in the write cache creates a single point of failure, because if the write cache is com-

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The Write Journal

A write journal or write-in-progress record is used in “cache write-back” mode to keep track of all ongoing write transactions. A write-back cache improves performance significantly but comes with an increased risk to the data integrity of the system. In write-back cache mode, the RAID controller does not wait for the data to be committed to disk before acknowledging the host about completion of the write. The data is transferred from the cache to disk internally and this movement of data is transparent to the host. After it receives acknowledgement from the RAID controller, the host assumes that the data sent has been securely stored to the physical disk drives. However, power

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11:53:54 AM RTC MAGAZINE 11/17/09 MARCH 2010

technology in context

promised, both cache data and the write journal will be lost. Another issue is durability. Cache memories are typically battery-backed SDRAMs. Usually, these have a limited power down lifetime of 72 hours. A dedicated nonvolatile memory for write journaling ensures that even if the cache data is lost, the system can identify the status of operations before the power failure occurred. Another factor of prime importance to any storage system is availability. Independent access to the write journal allows the system to accept new data to be written from the host even when it is reading the write journal. This helps to identify completed and pending writes to the disk while at the same time increasing system availability, Choosing an appropriate nonvolatile memory for write journaling is critical to system performance and reliability. Engineers should consider the following critical parameters: Fast Read/Write Access: The NVRAM should be able to handle fast read and write accesses. A slow journal can potentially slow down the whole storage system. High Reliability: Data reliability of journal entries is important if the system is to meet RAID atomicity, consistency, and more importantly, durability goals. This memory space is also used to store some configuration details and failure logs with time stamping. Therefore, high


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reliability and data integrity are essential for RAID application. High Endurance: Data needs to be written in a circular buffer fashion at a very high speed. Given the volume of data passing through RAIDs, the journal memory must have a very high endurance (i.e., support a large number of write/erase cycles). The standard asynchronous SRAM interface on an nvSRAM enables highspeed read and write access (up to 20 ns) while allowing the nvSRAM to be written or read effectively indefinitely. This is possible because the nonvolatile elements of nvSRAM provide reliable data storage without the need of a battery to protect data during power down. In addition, the endurance of nvSRAM is counted in terms of the number of times power is lost, for it is only when the system power goes down that a store operation to NV elements takes place. Specifically, data backup to nonvolatile memory is done automatically on power failure using stored energy on a small capacitor connected to the VCAP pin of the nvSRAM chip. nvSRAM is the fastest nonvolatile RAM in the industry with 20 ns read and writes access time. This enhances system performance by reducing access time. The use of Silicon-Oxide-Nitride-OxideSilicon (SONOS) technology as a form of backup flash memory array provides nvSRAM with unmatched reliability. Data retention of 20 years at industrial tem-

perature range is the highest among any nonvolatile RAM technologies available today (Figure 3). The SRAM interface of nvSRAM also allows the write journal to be written infinitely without the worry of running out of endurance or wear leveling. This takes away all the effort required for implementing wear leveling or monitoring endurance cycles in software. Unlike a battery-backed SRAM, nvSRAM is a green technology with no battery involved. A small capacitor is used to store power and utilized for the AutoStore operation during power fail conditions. Many RAID systems time stamp write journal data. This typically requires an additional real-time clock (RTC) device, thus increasing the total BOM cost and board area. With an integrated RTC function, nvSRAM frees up resources on RAID systems such as communication channels and reduces software development. Write journaling using nvSRAM is an effective and reliable way to implement a nonvolatile cache for RAID systems. With highspeed read and write operations, infinite write endurance, battery-less operation, scalability and reliable SONOS technology, nvSRAMbased designs provide a robust foundation for nonvolatile cache in RAID systems. Cypress Semiconductor. San Jose, CA. (408) 943-2600. []

11/11/09 3:45:15 PM


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connected Supervisory Systems

Autonomous UIs—A New Path for Customizing Application Look, Feel and Function The concept of Autonomous UIs lets application developers specify generic or abstract presentation of controls, widgets and even content, giving downstream developers the freedom to brand and customize without altering the underlying application code. Robi Karp, CEO, Fluffy Spider Technologies


mbedded computing has its roots in industrial automation and instrumentation. The vast majority of traditional systems was headless, or communicated with operators and other users through dedicated physical means—knobs, dials, gauges, indicator lights, etc. Today’s intelligent devices, by contrast, boast greater sophistication of operator interaction with user interfaces (UIs) comparable in scope and capability to desktop applications. Leading this trend are mobile computing devices like smart phones, in-vehicle (IVI) systems and home entertainment (media players, HDTV, DVRs and STBs). However, nearly every design domain, from factory automation to medical devices to aerospace systems and from networking equipment to Point-of-Sale, demands increasingly engaging user interfaces. With traditional design methodologies, application code “owns” the particulars of UI implementation, determining the type, orientation, placement and other attributes of objects on the display (button, widgets, etc.). This includes the flow of their use and the callback code that





Not all input/output passed to/from application




Figure 1 Different Presentations of the same applications are made possible by decoupling the UI from the application code.

technology connected

powers those elements. The attributes of a UI design are thereby set in the original design and are only minimally mutable downstream, by channel partners, thirdparties and end users. Some UI and application frameworks support theming— customization of color schemes, menu text styles, window frames, widget sets, etc. However, the fundamental structure and flow of an application UI remains set in stone—a closed box as imagined by the original design team.

Decoupling the UI from the Application

The concept of Autonomous UI design and implementation goes beyond custom themes, icon sets and color schemes common on many mobile phones and other intelligent devices. It entails letting developers bind custom functionality to individual UI elements via runtime scripting. It supports the addition and/ or removal any item from an application UI, including images, videos and widgets without changing any application code, i.e., with binary images. An autonomous UI further enables existing applications to integrate reaction with new device events and capabilities, like shaking and orientation by adding an accelerometer, location and movement (GPS), and definable data and network events such as calendars, stock quotes, sports scores, wireless traffic, etc. It also lets integrators, operators and end users easily add new UI personalities at runtime without changing shrink-wrap application code (Figure 1).

Autonomous UI Architecture

Breaking out application and presentation code doesn’t require radical rethinking of the core application design. Application code can still solicit input and generate output. It is still up to the application design team to determine how much control resides inside the application itself vs. the amount exposed to subsequent modification. But decoupling does require specific support from the underlying graphical and multimedia framework. Key enablers of an autonomous UI include providing safe binding between

underlying graphical system APIs and an external, open programming environment. One very good tool for accomplishing this is the Lua scripting language (see sidebar “Lua Scripting Language” p. 26). In addition, there must be a way to expose inventories of (public) application objects that implement UI functions. The decoupling mechanism must also support a protocol between presentation code and the application for information exchange. It is also important to provide an open high-level API for developer use. It is of course the main point of entry for developers, and also simplifies translation of information between the language bindings using the protocol. At Fluffy Spider Technologies, we chose C in building FancyPants itself, and for underlying libraries. For building Autonomous UI code, we bind to the Lua scripting language at a high level, taking advantage of Lua features and rapid prototyping capabilities.

Real-World Examples

SMS Client – On a mobile handset, the device manufacturer will typically include a short messaging system (SMS) application, sourced from the mobile OS supplier, a third-party (ISV) or created in-house. This “preload” SMS application likely includes a traditional, straightforward display of messages and addressees. A mobile network operator (MNO) or other channel partner has few options for customizing or branding this kind of application, and is often forced to pass uninspired software through to end users “as is” or invest in replacing preload applications at considerable effort and expense. An SMS client, or comparable application, designed to leverage Autonomous User Interface design, would offer MNOs and other channel participants numerous options for customization and differentiation. For example, developers at the MNO could enhance addressee information with status and location-based data supplied from the operator’s network. Similarly, a third-party ISV could offer an alternate look and feel to that same SMS client, using previously unavailable functions like accelerometer input or GPS coordinates—all without modifying any

original application code. An example of such different look and feel designs is shown in Figure 2. Universal Access UIs – Many operating systems, devices and even individual applications offer some degree of support for disabled users, ranging from alternate input methods to zoomed/large typeface output to spoken and Braille-based UIs. While surely helpful, most attempts at adaptive UI customization merely aug-

Figure 2 Two presentations of a single SMS application are obviously targeted at different classes of users.

ment one or two attributes of existing interface design without really accommodating actual user needs. Building on the foundation of Autonomous UI, applications could easily be augmented to support alternate input methods by supporting aftermarket integration of voice-input engines, iconic input schemes like Minspeak and Bliss Symbols, and accommodating the particulars of adaptive communication equipment. Similarly, application output could be conditioned for user visual acuity, limited field of vision, etc. Ruggedized Instrumentation UIs – Most instrumentation systems are designed for nominal viewing and input conditions, targeting stable, well-lit workbench, laboratory and clinical environments. Using the same device in more challenging environments—in moving vehicles, high-noise environments, in bright sunlight, etc.—presents challenges to offthe-shelf UIs and can render a device almost completely ineffective. OEMs can’t begin to predict the ways and locales in which their wares will be deployed. By employing Autonomous UI design, both RTC MAGAZINE MARCH 2010


technology connected

The Lua Scripting Language Lua is a powerful, fast, lightweight, embeddable scripting language. Lua combines simple procedural syntax with powerful data description constructs based on associative arrays and extensible semantics. Lua is dynamically typed, runs by interpreting bytecode for a register-based virtual machine, and has automatic memory management with incremental garbage collection, making it ideal for configuration, scripting, and rapid prototyping. Learn more about Lua at

OEMs and integrators can facilitate missionspecific customization to accommodate vibration, the need for ad hoc mixtures of audio and visual output, and “off book� ad hoc integration with other types of equipment. Manufacturers Producing Multiple Product Families – Depending on the industry, a new product—not just a new product version—can require between 2 to 10 or more man-years of engineering effort to reach the market. For point-of-sale terminals, with stringent security requirements,

development time can stretch longer, while mobile phones, with quicker sales cycles have a much shorter market window time but usually involve an even greater engineering investment. A significant part of the engineering effort lies in the creation of a compelling, differentiated user interface. For OEMs creating families of products with multiple members, being able to deploy the same application code base with different user interfaces saves time, money and can also help focus development ef-

fort on truly differentiating features. For subsequent iterations of the same product line, an Autonomous UI helps new products in the family arrive to market more quickly and with confidence. The arena where this phenomenon is most evident is in common operating platforms. OEMs choose a common, interoperable COTS OS like Android or WinCE to save on non-differentiating engineering, and to leverage existing or evolving ecosystems that revolve around those platforms. However, these platforms typically leave little room for OEM branding and customization. Unless OEMs invest in significant incremental engineering, as Motorola did with Blur UI, users will be greeted with the same UI as on every other Android gadget, relegating the new device to the status of commodity as in the PC market. And if OEMs do make the required investment, they will likely need to repeat that effort with each new platform release. Figure 3 shows two home screens for an application based on the Android operating system but enabled by an autonomous user interface.


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technology connected

retention. A manufacturer can create a recognizable user experience that will come to be identified with that brand. The concept of decoupling UI and application design principles embodies core principles that can be applied to using other frameworks and toolkits—abstraction and limiting application dependency on platform particulars. In today’s dynamic landscape of multiple applications OSs

(especially in mobile), and of burgeoning device SKU counts, it’s especially important to build a strong base product that can be easily tailored for different packages, channels and markets. Fluffy Spider Technologies. Aptos, CA. (408) 916-1191. [].

Figure 3 Two Android home screens can offer a widely different look and feel for the same application while delivering the same functional value to different classes of users.

Autonomous UI design is not just another way to subdivide application functionality. It actually offers developers benefits that emerge directly from decoupling UI and application code. It offers shorter development time to create brand new, unique user interfaces without modifying application code. At the same time it adds the ability to add intelligence to existing UI code, it can, in fact, make decisions and process events unforeseen in the original design. An autonomous UI results in shorter time devoted to quality assurance because the application code has already been quality assured and only the different versions of the user interface need to go through the process. The ability to create a family of products based on a single application code base means that high-end devices can have different user interface presentation and reactions than the low-end products. Product iterations can also take advantage of the shorter Q/A time and reduction in software development time. The ability to build devices with a unique look and feel, even on commodity software and hardware platforms, leads to enhanced brand Untitled-3 1


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technology in


Mechanical Design for Cooling

Thermal Analysis and Heat Sink Design Optimize Cooling of HighPerformance Modules Computer-driven simulation and analysis of thermal characteristics can develop optimal cooling solutions for high-performance board designs that can be verified by real-world testing to improve MTBF and shorten time-tomarket. by Michael Haskell, Advanced Thermal Solutions


leading provider of embedded computing solutions needed to determine the thermal characteristics of its new packet processor. Such devices often entail complex heat transfer and other thermal characteristics. Comprehensive thermal management analysis and design services can be tailored to help bring telecommunications, networking, embedded computing and other high-performance electronic products to market faster, ensure their reliability and reduce development costs. The packet processor was a high-performance 4-port Gigabit Ethernet PCI-X card that provides secure, high-speed connectivity and complex security processing with wire speed performance. It features a 16 core 500 MHz processor, which must be kept at a junction temperature below 110°C to maintain reliable operation. A previous card model employed an active heat sink for cooling the processor. However, the card makerâ&#x20AC;&#x2122;s design team wanted a complete and thorough thermal examination of this component so that a passive cooling solution could be used. Passing cooling would pro-



Figure 1 SolidWorks model of the PCI-X card.

vide higher reliability and save on both cost and implementation time. Several thermal management analysis and design services were used in developing such a solution. The process starts with a detailed thermal analysis of the PCI board design, which leads to CAD and computational fluid dynamics (CFD) simulation and analysis. The results of the analysis and simulation are used to implement the rapid design of the proto-

type heat sink. The design is then tested and verified using wind tunnel and chassis testing. Advanced Thermal Solutionsâ&#x20AC;&#x2122; engineers studied several key factors including volumetric flow rate, pressure drop and component temperature. They started by researching and simulating the thermal characteristics of the memory DIMM and other critical components. Using this approach they produced analytical junction

tech in systems

Figure 2 From left to right, SolidWorks images of the maxiFLOW heat sink, along with its CFD simulation and prototype.

temperatures for each device as well as an estimate of the airflow necessary to ensure proper cooling of the PCI-X card. It also reduced the number of CFD (computational fluid dynamics) iterations that needed to be performed, and validated those CFD findings. Based on the results of the thermal analysis, engineers used SolidWorks 3D CAD software to produce a detailed model of the board assembly (Figure 1). Then they ran multiple airflow simulations, at various flow rates, using CFD software from CFDesign. The result was a detailed set of CFD images showing the airflow patterns and providing a temperature profile of the card. Using the data from the initial analytical and CFD studies enabled the design of a high-performance heat sink based on ATS’ maxiFLOW flared fin architecture that, when installed, would adequately cool the package and ensure proper performance of the PCI-X card. maxiFLOW heat sinks feature a low-profile, spread fin array to maximize their surface area for more effective convection (air) cooling (Figure 2). In the case of the PCI-X card, the heat sink was found to keep the junction temperature of the processor at or below acceptable levels with an airflow of 200-275 LFM or greater within a PCI card slot, at an ambient air temperature of 55°C. Engineers then had two heat sink samples precision-machined at their in-house prototype and volume manufacturing facility. As part of the design process, all heat sinks are tested in a thermal fluids laboratory, using a CWT-100 series open-loop wind tunnel, to verify any analytical or

Figure 3 An Intel SR2400 server chassis (left) and an ATS ATVS-2020 automatic temperature and velocity scanner (right) were used to test the ATS heat sink performance on a PCI-X Card.

Figure 4 CFD Simulation of the Packet Processor PCI-X Card with the ATS maxiFLOW Heat Sink Installed, alongside a sample card.

computational simulation results. When the heat sink was tested, elements in the open-loop wind tunnel were arranged to simulate the PCI slot conditions, thus validating CFD testing. Test findings also produced the heat sink’s thermal resistance and pressure drop characteristics. The analytical design of the passive heat sink for cooling the proces-

sor was the initial phase of the PCI-X card thermal characterization. Because the heat transfer from the component to the ambient was so complex, further testing of the maxiFLOW heat sink was performed with it installed on the card, and inside an Intel SR2400 Server Chassis, under several different test conditions. RTC MAGAZINE MARCH 2010


Tech In Systems

2 1.8 Thermal Resistance (˚C/W

1.6 1.4 1.2 1 0.8 0.6 0.4

PC Cards Feel the Heat

0.2 0







Air Velocity (LFM) Chassis Testing

Figure 5

CFD Simulation

The results of CFD simulations and chassis testing of the ATS maxiFLOW Heat Sink. The PCI-X Card manufacturer recommends an airflow of at least 275 LFM if a passive heat sink is used.


800,000 700,000 (Hours)

Mean Time Between Failure


600,000 500,000 400,000


300,000 200,000 100,000 0

Cooling Solutions With 12V Fan

With ATS-725 maxiFLOW Heat Sink

Figure 6 Comparison of cooling solutions for the PCI-X Card in terms of mean time between failures.

Thermocouples and ATS’ ATVS2020 Automatic Temperature and Velocity Scanner, multi-channel, hot-wire anemometer system were used to measure case temperature as well as approach air velocity (Figure 3). For one validation test, a sample PCI-X card was installed in the chassis and subjected to variable airflow. Component temperatures were recorded over a range of airflow levels to produce a thermal resistance graph. In a separate test, the PCI-X card was modeled in CAD and simulated with CFD. The PCB was modeled as a standard 12-layer board with bulk thermal proper-


CFD simulation of airflow across a PCI card: A passive heat sink covers multiple components. The blue lines represent cooler air. Yellow lines are warm air removing heat from the sink. PCI cards at one time required 5-10 watts to power their components. Today, a typical card may require 60W. More effective thermal analysis and heat sink designs are necessary to keep component junction temperatures within safe operating limits.


ties as follows: a thermal conductivity of 85.6575 W/m-K in the X and Y directions, thermal conductivity of 0.333705 W/m-K in the Z direction, 432.54 kg/m3 density, and 837.002 J/kg-K specific heat. The card and the CFD simulation are shown in Figure 4. The results of these two testing methods showed close agreement, with an error of 2-13% from 100-600 LFM velocity. The final test stage included CFD simulation of the complete PCI card with the heat sink attached. This simulation also showed close agreement with the chassis testing. CFD results showed a

consistently higher thermal resistance of 2-13%, and this was mainly due to a lack of radiation heat transfer in the simulation (Figure 5). Once the base simulation was correlated with experimental results, future scenarios could be investigated within CFD to predict processor upgrade thermal performance. Effective thermal management study and design produced valuable analytical, computational and experimental data that allowed for a high-performance, optimized passive heat sink solution to be designed for the PCI-X card’s ideal operating conditions. Not only did the heat sink solution offer significant cost savings, but it also provided 27 times the reliability of the active solution (Figure 6). As a result of the collaboration between the card manufacturer’s design team and ATS thermal management experts, the company was able to quickly introduce the new card to the market with cost savings and increased reliability. Advanced Thermal Solutions. Norwood, MA. (781) 769-2800. [].




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technology deployed M2M Systems in Transportation

Providing Data in Real Time: Machine to Machine Systems Smooth Transportation M2M systems in transportation consist of a variety of very different devices that must all communicate their data to a central monitoring system as well as to each other. Making them modular, reliable and flexible is essential to smooth fleet operations and scheduling. by Kurt Hochanadel, Wireless Product Manager for Eurotech, Inc.


n machine-to-machine (M2M) communications, a field-deployed wireless device gathers data and sends it to a back-end server through a wireless network. M2M is particularly useful in the transportation industry, where valuable data provided in real time can ensure a smooth transition for goods or passengers. The goal of any passenger train service, trucking company or bus service is to move goods or passengers from point A to point B Connected Train Mobile Access Router for the train to ground link

Safety camera

Ethernet switch

Digital Video Recorder Passenger Counter Control System

Ethernet switch

Passenger Information System Ticketing & Passenger Services Control Console

Figure 1 A connected train uses M2M communication to track passenger and security data in real time. The result is a smoother ride for passengers, and easier operation for transit companies who can update departure and arrival times and make adjustments based on accurate data.



in a pleasant and efficient manner. M2M has emerged as the next-generation technology that can smooth transportation by allowing for real-time data analysis. For instance, M2M communication allows a bus station to update arrival and departure times based on data provided directly from the bus fleet. M2M communication also allows a grocery supplier to monitor the temperature for frozen foods on a semi-trailer truck. Mobile computing platforms have become smarter and the number of applications requiring complex, real-time data is growing. There is a wide range of unique transportation markets including rail, commuter bus, fleet and air, and several key factors come into play when considering the product development lifecycle for M2M devices in transportation (Figure 1). Regardless of the end application, product designers must carefully consider similar basic requirements: communications, I/O, packaging, operating system and networking.


The most important aspect of the M2M system for smooth transportation is connectivity for reliable communications. It is critical to identify the wireless capabilities of the M2M device, including: cellular (GSM/GPRS & CDMA), 802.11 (access point, client only), satellite, GPS, Bluetooth (class 1 or 2), mesh networking (ZigBee, 802.15.4, 6Lopan), RFID and others. Each wireless interface has several specifications to consider in choosing the correct hardware path. Cellular is the most prevalent and essential hurdle to overcome to successfully deploy a new product with an M2M application. The correct cellular design leads to long product life cycles and improved sales. Making a mistake leads to redesigns and expensive certifications that delay time-to-market. Consider the following options for cellular communication: • Technology - High Speed – 3G, 4G (EvDO, HSDPA/UMTS) - Low Speed – GPRS, iDEN, 1xRTT CDMA - Market/Carriers – Verizon, AT&T, Sprint, Global, others • Interface - Standard – Pluggable Module (USB, Cardbus, Serial), Mini PCI, Mini PCI Express - Custom – Typically a 40+ size pin header • Certifications - Carrier Certification - CE, FCC - PCTRB - CTIA

Technology deployed

Matching the right technology speed and cellular carrier enables a transportation company to take a focused approach to going to market with their M2M application. For example, if the application is GPS tracking and engine diagnostics with simple I/O, high-speed network connectivity might not be necessary. A lower-priced GPRS device should do the trick. However, if the application will use Wi-Fi, digital signage and Internet access for peripheral devices such as a PDA, it is critical to achieve the highest possible speed and 3G technology is the best avenue. Choosing the right interface for communications support depends on the carrier and technology speed. For the 3G network, a modular approach with a Mini PCI Express card typically allows for the most flexibility, highest speeds and works on almost all carriers. As new technologies are offered with higher connectivity speeds, these modules can be updated fairly quickly and allow for short implementation cycles to get to market. Planners must keep industrial temperatures in mind. High-speed modules do not usually have a -40° to +85°C temperature range, but they are generally rugged enough for most situations. For a lower speed product, use a module provider that offers long-term product lifecycle support. The technology is already outdated, so make sure you have at least 5 years of support for any given device architecture. System designers should consider the certification process at the beginning of the product development lifecycle, since it is sometimes the limiting factor to putting a product on the market. In the United States and some other countries, cellular carriers require certification for each cellular product on their network prior to deployment. Therefore, after all of the hardware and software development, RF tests, packaging and documentation, each product must go to each carrier for certification. The certification process can be expensive and can delay deployment by as many as nine months. If there are issues that require a redesign, the added delay could kill the product. Planners do well to work with carriers early in the development process to receive guidance and eliminate problems before they occur.

I/O & Packaging

The M2M market for transportation is applied widely and has varied requirements. There are two common approaches to hardware design: fit-for-purpose or a modular platform. Fit-forpurpose systems are designed to meet an application’s requirements with little change, such as asset tracking requiring power, GPS and cellular connectivity. A modular platform is designed to meet the requirements of many applications across different segments within the transportation industry. For either choice, there are several components worth exploring during planning and development. Power consumption is relevant for applications requiring continual connectivity, even when the vehicle is not running. If the embedded device will always be on, the power consumption needs to be 20 mA or less. Low power is achieved by processor choice and the ability to put hardware components into a sleep mode. For

Bus Management System Cellular Network

GPS Passenger Counter Wireless hot spot and GPS receiver Video surveillance

Driver’s Console

Fare collection

Passenger Information

Control Computer

Ticketing & Passenger Services Bus Stop Passenger Information

Figure 2 Machine to machine communication is taking bus transit to a new level, facilitating updated arrival and departure times based on data provided directly from the bus fleet. Wireless communication can allow the data to be gathered in real time, or when the bus enters the hub.

applications that operate only when the vehicle is running, low power consumption is not as critical. Some devices will need to be powered for a fixed amount of time after the vehicle shuts down to upload data at a hotspot requiring additional hardware. There are many types of vehicles that service the M2M transportation market, and there are just as many ways to provide power. While there are no set standards for input voltage, there are some similarities in each segment. Most designers target a wide range encompassing the maximum number of applications such as those typically seen in Fleet platforms with an 8-36 VDC input. The examples below detail the typical requirements recommended for design: • Fleet – 12 or 24 VDC • Rail – 12, 24, 48, 72, 120 VDC • Air – 12, 14, 24, 28 VDC There is need of new technology in terms of the ability to survive the commonly encountered transients or surge voltages in the automotive environment. The platform designer must ensure reliable circuit operation in this severe transient environment. The transients range from the severe, high-energy transients generated by the alternator/regulator system to the low-level “noise” generated by the ignition system and various accessories, which can be detrimental to poorly designed products. It is critical to provide transient surge protection for the hardware based upon the application. For most vehicle applications the transient protection needs to be from 100 to 150V to shield the hardware from failure. The protection enables the device to connect directly to the vehicle bus for ease of installation and provides longevity to the hardware design. RTC MAGAZINE MARCH 2010


technology deployed

Not all applications for transportation devices will require isolation and it can be an expensive capability to add. However, it is a must in most rail applications. There is no ground available in rail applications due to the fact that the device is running on rail, which is commonly known as a floating ground. In this environment it is possible to encounter large differentials in power and the device must act in complete isolation as an autonomous system protecting the hardware inputs, chassis and antenna connections. The typical range of isolation is 1000 to 2500V on the various I/O. Antennas are significant for a well connected device and smooth customer experience. Antennas are either integrated or external to the product. Radio frequency experts should handle integrating the antenna into the device as the composite of the enclosure and placement needs to be carefully engineered. For all external antennas, less engineering is required but planners must be aware of the type of connector required and the specific needs of the radio frequency device. For example, the 3G network modules are typically enabled with two antenna connections, one for main and the other for diversity. It is not a requirement to have both, but may be necessary for certain applications. The transportation market requires a rugged design for the vertical markets such as rail, air and military projects since they require certification. The packaging should not be an afterthought but rather considered throughout the lifecycle of the design. Each application can have unique standards though it is typical just to meet SAE J1455 or MIL-810-F shock and vibrations standards for most fleet applications. Wide temperature ranges, fan-less requirements and compact size constraints are also common considerations during package design.

Operating System & Networking

M2M systems in transportation are continually dropping on and off the network, requiring belts and suspenders in the code and operating system to maintain the connectivity and reliability. Running several wired and wireless networks in a mobile platform is not easy and requires complete control of the interface, which also includes the application being able to support the interrupts. Designing the application in a clean environment and expecting it to run on a mobile platform ignorant of communications is not likely to be successful or sustainable over time. Also, keep in mind that planners must focus on driver support for the peripherals and internal modules since they are major contributors to the success of the project. One of the most important aspects of a platform is its routing capabilities to connect multiple network interfaces from backend applications. To connect to peripherals through serial ports, mesh networking, Ethernet or USB interfaces requires tooling that is easily enabled and controlled. The routing functionalities that are important include Mobile IP, network address translation (NAT), port-forwarding or masquerading, terminal server and clients, DHCP client and server, and static routing. Since most of the devices are connected to the Internet, data security is a must. Operating and connecting secure devices in mobile applications includes understanding the following topologies/technologies:



• VPN – IPSec, OpenVPN... • SHH, SLL • Routing, Port-forwarding and Network Address Translation (NAT) • Encryption – AES, Blowfish, 3DES... • WEP, TKIP, WPA… Technology and firewalling are essential for device connectivity of data between backend applications and other data consumers. Protecting the device from malicious hacking and securing the network connectivity is always a concern. Managing the mobile computing platform with firmware updates and programs additions on a moving asset is part of M2M. These updates can be difficult if the OS and application do not have the correct tooling. An OSGi application framework is ideal, allowing for bundles of Java code to be deployed, stopped, started and rolled back with version control. Providing diagnostic tools for logging and debugging allows bug fixes and application issues to be handled remotely and not through costly removal of the hardware, inherently saving time and money.

Providing Accurate Passenger Data

Integrated into the other functions of an M2M transportation system is the collection of passenger data, which can be used separately or correlated with other data in the control center. Transportation agencies need to count passengers for three reasons. First, they need to report passenger counts for government subsidies and budgeting. Second, they want to know how many people are riding compared to how many fares they are collecting. Third, they want to know how many people are riding to monitor and smooth schedules and service offerings Prior to the latest embedded systems and M2M technology, drivers counted passengers with a clicker. Drivers have to focus on safety and driving, of course, and counting passengers is last on their list of responsibilities. Counting by hand is only about 70 percent accurate. Now, a remotely fielded embedded device automatically counts the number of passengers and reports the count in real time to a server. The data is collected and agencies use the information to better manage fleet operations and scheduling. The analysis of the data provides a better overall customer experience and increases fleet utilization managing costs while increasing profits. Successful machine-to-machine hardware design smoothes transportation for both users and operators. Data is moving quickly on rail, ground and air fleets, and embedded systems allow operators and backend applications to pull data off these moving parts and synthesize the information in real time. With the right design and focus on communications, successful delivery of data into M2M applications is possible.

Eurotech. Columbia, MD. (301) 490-4007. [].








technology deployed M2M Systems in Transportation

Monitoring the Railway with Technology and Keeping Both Running

One hazard is caused by “hunting trucks,” which refers to a mismatch between the shape of the wheel tread and the shape of the rail. Normally, these are shaped like a matching cone (wheel) and rise (rail) such that they fit together and keep the wheels centered on the rail and the car riding straight. Wear can flatten out these shapes and when they are mismatched, the set of wheels, called a truck, oscillates back and forth “hunting” for a stable match position on the rail. When hunting trucks underneath rail cars violently oscillate from one rail to the Sophisticated sensors in remote areas combined with other as they traverse along tangent track, rugged, specialized processor modules, software and they induce excessive lateral forces that significantly contribute to the rapid wear of communication systems work together to keep trains on rail and rail cars in a relatively short time. the rails, saving billions of dollars. In addition to protecting This particular type of degraded vehicle performance is a leading cause of damage such systems from the weather, protecting them from to delicate lading. At a minimum, hunting end-of-life is vital to transportation systems. trucks cause increased fuel consumption. Unchecked, severe damage to truck components and derailment can result. More than 10% of the equipment-related derailments each year could be avoided through by Dana Earl, Salient Systems and Russ Nieves, Xembedded greater Hunting Truck Detector (HTD) network coverage (Figure 1). Similar in design to the wayside Wheel Impact Load Detector (WILD), this add-on capability measures the array of lateral forces n the railroad industry, management by prevention is im- exerted by a hunting truck on a passing train. What’s unique perative. Faulty track and equipment causes half of all about the Salient design is that it takes into account the dynamic train derailments. The resulting cost to the global rail relationship between vertical and lateral loads; that is, the system industry in materials alone exceeds billions of dollars, not compares simultaneous readings from a WILD and an HTD to including costs for personal injury, hazardous material clean identify critical instances where the wheel flange and rail gage up, litigation and lost productivity. Real-time monitoring of face geometry may promote flange-climb derailments. These the health of rails and the performance of trains helps to low- measurements are processed through a highly sophisticated er the risk of catastrophic derailments and promotes timely, proprietary algorithm and transformed into a Hunting Index to cost-effective preventative maintenance. The most dangerous identify and sound alarms on vehicles that exhibit excessive sidedefects in rail infrastructures are the ones that are invisible to-side motion. If the forces exceed an acceptable threshold, an to the human eye. intellitrack solutions by Salient Systems, automatic report notifies the customer which truck requires acInc., integrates advanced failure detection technologies with tion based on their tailored alarming requirements and long-term sophisticated decision-making software tools to help detect analytical needs. these defects with a range of monitoring systems including Salient System’s MARK III (Mk III) Wheel Impact Load Wheel Impact Load Detectors (WILD), Hunting Truck De- Detector (WILD) is a system of strain gages coordinated by a tectors (HTD), Weigh-in Motion (WIM) and Truck Perfor- central processing unit (CPU). CPUs send reports to servers mance Detectors (TPD). under the Wheel Management and Detection System (WDMS) Salient Systems, part of the Portec Rail Group (NASDAQ: or customer maintained servers to track vehicle health history PRPX), invested many years developing the intellitrack system, and dispatch alerts. Customers can establish a network of WILD getting the physics and math right, and then developing the sen- systems using TCP/IP links, modem communications, or similar sors and monitoring technology. methods that allow network or serial ports to communicate over




Technology deployed

Figure 1 Hunting Truck Monitoring Station

Figure 2 Wheel Impact Load Detector Installation

distance. These WILD systems then create a complete picture of vehicle health within a customer’s rail network, protecting from derailments and damaged track infrastructure (Figure 2). The primary measurement tool of the Mk III WILD is strain gages. Vertical strain gages measure the force wheels passing over the rail head exert on the top of the rail. Lateral strain gages measure the force wheels exert on the side of the rail as they travel down the track. Secondly, the Mk III WILD employs tag readers to identify the cars passing over the site. The software can determine the car type from strain gage measurements, but to track the history of a car and easily identify defective cars, tag readers supply an individual name to the vehicles. Thirdly, the WILD system can gather weather conditions from a weather sta-

tion attached to a serial port. Weather data is useful to determine cross winds, temperature and rainfall that can create unsafe conditions and influence wheel data. The system CPU employs an Intel processor running a Linux operating system. SiteMaster is the software program that coordinates all of the measurements by strain gages and tag readers (Figure 3). Once SiteMaster calculates the measurements made by the WILD system, it dispatches reports to talkers, printers, computers and servers so that customers get alerted to dangerous conditions, allowing them to track the health of vehicles that cross WILD sites. For over 20 years, Salient Systems monitoring systems have been a tool that rail operators have counted on to help identify conditions conducive for derailment. Many of these systems are found in extreme, remote locations—some so remote that it takes two days of hiking along the track to reach them. Because of these extreme environmental conditions, when we looked into deploying the system, we decided that VME bus was the best solution, providing a system more robust, efficient and easier for local support and maintenance. We originally started with a standard VME chassis and backplane, but as the system was fielded, we settled on a custom enclosure and chassis. These two pieces were designed around the pin-out of the host processor board, which made the system more robust and easier to service. About three years ago, the company that made the system host processor was bought by a competitor. Shortly after that, we received an end-of-life notice for the processor we had built the system around. After discussions with the new manufacturer of the EOL board, we were told our volume was too small to support with the existing board. That gave us two options: buy ALL the EOL boards we needed in a last build, or migrate to a new processor board. We were assured the new processor would be “supported longer,” but it had a different pin-out, I/O complement and BSP (board support program). Since neither option was acceptable, we decided the best way to proceed was to find a new board, with long-term support, that would plug directly into the existing custom backplane and have a BSP that was compatible with the present one. After researching the options, we looked at Xembedded’s Legacy Product Support program and selected them for the project. Xembedded worked closely with us to create a board specification, including the pin-out to match the custom backplane, compute power and I/O needed to support the project, plus a compatible BSP API. The 100% identical pin-out of the VME J2 and P0 was crucial for us. This allowed use of the new board in existing and future systems, with no changes to the other system components. Because Xembedded started with one of their standard COTS design, that kept the cost low compared to a custom board and reduced design risk. Since 90% of the parts are also used across other products, our board quantities could be lower yet still be cost competitive. RTC MAGAZINE MARCH 2010


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16-channel TTL/LVTTL digital I/O Pico-I/O™ module size (60mm x 72mm) & mounting capability All 16 I/O lines buffered with 32mA sink/source current capabilities 8 Form C electromechanical relays switch 1A Custom high-speed function driver Alternate embedded USB connector All required power drawn from USB port, no external power adapter required

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E-mail: Web:

1.1GHz (Z510) & 1.6GHz (Z530) Up to 2GB memory Up to 8GB on board flash 10/100/1000 LAN Up to 8 USB ports, 2 or 4 COM ports, 7.1HD Audio CRT/LVDS 1x PCI Express Minicard for WLAN/GSM PATA or SATA, Optional GPS PC/104+ or PCI/104-Express Bus Above Features are Dependent Upon Product and Options…

Advanced Digital Logic (ADL) E-mail: Web:

Phone: (858) 490-0597 Fax: (858) 490-0599


E-mail: Web:

Kontron COM Express Modules

COM Express Modules Type 2 COM Express® module provides easy-to-use embedded PC functionality Intel® Atom™ processor N450 @ 1.66 GHz for low power consumption Up to 2GB DDR2 memory, optional eUSB flash Gigabit Ethernet, SATA and PCI Express LVDS graphics for flat panel displays 8x USB 2.0 interfaces Target applications include industrial control, kiosks, clinical display systems, panel PCs, diagnostic and test equipment and more

Kontron modules range in performance and power consumption from the ultra-small, extremely power efficient nanoETXexpress-SP with the Intel Atom Z5xx processor series all the way up to the top-performing ETXexpress-AI featuring Intel Core i7 processors. For more information, visit

Emerson Network Power


Phone: (800) 759-1107 or E-mail: (602) 438-5720 Web:

Phone: (888) 294-4558 Fax: (858) 677-0898

E-mail: Web:

Technology deployed

Salient’s MK Wheel Impact Load Detector Future Detectors

Salient’s Overload Car Detector

Small Form Factor SIG & PC/104 Showcase Kontron Embedded SBCs Kontron’s pITX-SP delivers significant power efficiency utilizing the Atom Z5xx processor series and the US15W System Controller Hub. The JREXplus-DC, with the Intel Atom N270 processor and the 945GSE chipset, delivers the best performance per dollar ratio and integrated support for a rich classic I/O set.

Salient’s Skew/Hunting Bogie Detector SALIENT’S SITE MASTER

Outside World

Tag Reader


Weather Station

Figure 3

Kontron Phone: (888) 294-4558 Fax: (858) 677-0898

The SiteMaster software system coordinates the input data from different sensors as well aa external data such as weather to determine the conditions that could lead to derailments.

Xembedded also worked closely with us to add some system improvements including improved processing speed, upgraded memory, higher speed Ethernet ports and the custom BIOS settings that we had wanted. Other enhancements that made the system more robust included an enlarged custom heat sink (the system has no fans) and removing unused serial and IDE ports to help eliminate field service errors. Once finalized, our product was assigned a unique product modification (PM) number. That feature saves us time in manufacturing and configuration management. By documenting all of our modifications to a standard board and assigning a part number specific to us, every time we place an order, we can be assured that we get the same board. If in the future we have a board ECO, Xembedded will incorporate it into the PM number and incorporate it into future builds. Xembedded’s Legacy Product program saved us time and money. They made the process easy, and with their support, we got the new board integrated with little disruptions to our production schedule. We don’t have to worry about the processor now, we can focus on doing what we do best—helping the railroad industry.

USB Embedded Modem Modules

Radicom Research, Inc. Phone: (408) 383-9006 Fax: (408) 383-9007

USB modems, in module or standalone form factor Linux, Windows and Mac O/S support -40C to +85C operating temperature (Module) Compact size: 1” x 1” x 0.2” (Module) USB 2.0 compatible up to 56K bps data rate, fax and voice AT command Transferable FCC68, CS03, CTR21 telecom certifications Global safety: IEC60950-1, IEC606011 (Medical) approved CE marking E-mail: Web:

Intel® Atom™ Powered PC/104+ Module Embedded Intel® Atom™ processor Z5xx series Ultra-low power consumption Dual 10/100Mbps PCI bus Ethernet One DDR2 SO-DIMM sockets supports 533/400MHz up to 2GB memory Supports CRT, 18/24-bit interface Two serial ports & four USB 2.0 ports Two SATA II interfaces & one CompactFlash™ type I/II socket Optional High Definition audio interface

Salient Systems. Dublin, OH. (614) 792-5800. []. Xembedded. Ann Arbor, MI. (734) 975-0577. [].

E-mail: Web:

WIN Enterprises Phone: (978) 688-2000 Fax: (978) 688-4884

E-mail: Web:



Advances in Processor Technology

Intel’s Core i7: What It Means to the Embedded Market Intel’s new processor family offers a range of power/performance options, models with ECC, and high levels of integration that are making them very attractive to embedded developers.

by Richard Kirk, GE Intelligent Platforms


n Thursday, January 7 of this year, according to one editor in the embedded computing space, it “rained” Intel Core i7 press releases. According to another editor, the military/ embedded market seemed to be “turning backflips” on that day, forecasting what he described as a “tectonic shift” in the industry. January 7 was the date Intel announced no fewer than 27 new Core i3, Core i5 and Core i7 processors— originally codenamed Arrandale—and what followed was a veritable deluge of announcements of products based on those processors. According to one commentator, by the time of Intel’s CES press conference, no fewer than 400 PC designs and, more importantly, at least 200 embedded devices based on the Core i7 were ready for launch. GE Intelligent Platforms was one of the companies responsible for that deluge with the announcement of five new single board computers based on Intel’s Core i7 technology (Figure 1). Why the excitement? For many years, embedded systems designers have been caught between two attractions in terms of choosing a proces-



Figure 1 The rugged VR12 6U VMEbus single board computer was one of five products announced by GE Intelligent Platforms concurrent with Intel’s announcement.

sor architecture. On the one hand, Intel’s raw performance has always been compelling—but this often came at the cost of a hard-to-manage power envelope. Then there was the growing PCI/PCI Express infrastructure, and the opportunities it offered to create more cost-effective solutions. Add to that the fact that the Intel architecture supported not only Windows, but also, for example, Linux and VxWorks, and its attractions were undeniable.

On the other hand, Freescale offered what seemed to be a better understanding of the need to offer solutions that made a trade-off between processor performance and power consumption/heat dissipation. The PowerPC architecture also offered access to AltiVec, the floatingpoint processing capability that is invaluable in sophisticated applications such as digital signal processing. And there was no questioning Frescale’s understanding


of the need to ensure extended product lifecycles in line with the needs of the embedded industry. The world, however, has changed. The single-minded zeal with which every processor manufacturer relentlessly pursued increases in clock speed and throughput has been tempered by a realization that those are no longer the be-all and end-all of processor design. Why? Simply because the unarguable trend—whether in the PC market with laptops, followed by netbooks, followed by tablets and slates, or in the embedded market with military applications such as unmanned vehicles and man-wearable computing—is to put more and more processing capability into smaller and smaller environments where power usage needs to be conserved and heat dissipation minimized. Now, the discussion is routinely not about clock speeds, but about performance/watt, about the size, weight and power (SWaP) characteristics of a solution. The kinds of products Intel was designing for the mobile PC market were the kinds of products that the embedded market needed. When the company announced 12 new products specifically for the embedded market at CES— products that would have the seven-year lifecycle necessary for the embedded market—pieces of the jigsaw started to fall into place. But extended availability wasn’t the only good news Intel brought to the embedded computing table at CES. Also announced was the fact that these new processors would include, among many other desirable features, ECC memory and a floating-point processing capability. Floating-point processing capability is a fundamental requirement for many of the most sophisticated embedded computing applications, such as radar, sonar and sensor processing or in any commercial environment where digital signal processing is a substantial

element, such as the growing interest in facial recognition for ATMs. In fact, the Core i7’s floating-point processing capability was not new, as such. GE Intelligent Platforms had benchmarked Intel’s earlier Penryn family of processors, which also featured floating-point capability, and found that it compared favorably with the embedded market’s incumbent supplier, Freescale, and its AltiVec processor. A significant attraction of the Core i7’s inclusion of an even more capable floating-point processor is that Freescale no longer supports the AltiVec processor. Beyond this, the Core i7’s HyperThreading Technology promises to substantially improve the performance of single precision FFT operations. HyperThreading Technology allows each execution core to function as two logical processors. Coupled with the ability to execute multiple instructions across the floating Arithmetic Logical Unit (ALU), each of the logical processors can execute multiple single-precision floating-point instructions per clock cycle—which has the potential to deliver a quite compelling boost in performance. The provision of ECC memory is equally significant. Embedded computing applications typically rely on the very highest levels of data integrity in what are often mission-critical and even lifeor-death environments. The majority of military/aerospace requests for tender, for example, specify it as a requirement—a requirement that boards based on the Core i7 can satisfy. As with the floating-point processing capability, integration of ECC memory is not new for Intel—but it is new in a chipset designed with the performance/watt characteristics required by the mobile computing market. Previously, designers had to choose between higher power consumption/heat dissipation and ECC memory—or lower power consumption/ heat dissipation without ECC memory.

Also integrated within the Core i7 chipset (Figure 2) is a powerful graphics capability which, according to Intel, will obviate the need for a separate graphics processor in an increased number of applications. Early GE Intelligent Platforms benchmarks, using the 3D Mark suite of tests, show a level of performance comparable with previous platforms that employed a discrete graphics processor. For example, ATI’s Radeon E2400 discrete GPU scores around 16,000 in the 3DMark tests—while the Core i7’s integrated graphics comes very close with a score of 12,000. That level of performance has made the provision of two DVI ports (rather than the previous single port) appropriate for GE Intelligent Platforms’ new family of Core i7-based products. Of course, graphics processing is also about number, variety and bandwidth of graphics I/O that can be supported, so the requirement for discrete graphics capability will still exist—but for many applications, the capability provided by a single board computer based on the Core i7 will suffice. In its announcement, Intel has loudly trumpeted the 32 nanometer manufacturing process used to fabricate the Core i7 chip set. This shrinking has contributed significantly to the higher degree of integration that means that three devices have been replaced with two. The front side bus (FSB), for example, is no longer a connection across the printed circuit board—it is integrated into the chipset. Not only does this integration result in higher speed performance and/or lower power consumption, but it also frees up valuable board real estate—a precious commodity to single board computer manufacturers looking to add the maximum possible amount of functionality. In the case of the VR12, for example, it has allowed the provision of two XMC sites, where otherwise only a single site would have been possible. This provides significantly more flexibility to users in configuring the capabilities of the RTC MAGAZINE MARCH 2010



board and minimizing overall slot occupancy. The additional real estate has also enabled the VR12 to feature onboard flash memory, as well as a plethora of connectivity options. Another important benefit of the Core i7 family of processors is just that—that it is a family. Intel has recognized the importance of being able to trade process-

i7 will offer either more processing performance per watt compared with earlier products (estimated at around 20%), or will offer lower power consumption per unit of processing performance than its predecessors. Much of the coverage of the Intel Core i7 announcement has focused on those features to which Intel has given

Figure 2 Intel’s Core i7 features a powerful inbuilt graphics capability

ing performance against power consumption/heat dissipation: the Core i7 is offered at power consumption (TDP) levels of 35 watts, 25 watts and 17 watts—with clock speeds of 2.53 GHz, 2.0 GHz and 1.06 GHz respectively - enabling customers to choose the performance/watt ratio most appropriate for the planned application. Early indications are that the Core



interesting names, such as Turbo Boost and Hyper Threading. Intel Turbo Boost Technology is said to automatically accelerate performance, temporarily increasing clock speed depending on workload, while Intel Hyper-Threading Technology is claimed to enable smart multi-tasking by allowing each processing core to run multiple “threads.”These

are, unquestionably, some pretty cool technologies—especially for students of microprocessor design—but, for the embedded market, they all merely contribute to the higher levels of performance/ watt that the Core i7 is expected to deliver. They are all also illustrative of the fact that companies like Intel are looking far beyond simply ramping clock speeds and reducing die sizes in order to achieve worthwhile performance gains. Intel’s Core i7 announcement is therefore significant to the embedded market for a host of reasons. It confirms Intel’s renewed commitment to a market that the company says is now worth a billion dollars a year to it. That commitment is illustrated by its continuing focus on performance/watt rather than pure performance, and the range of performance/watt options it offers; by its inclusion of the error correcting memory capability that means little to PC users but everything to many embedded users; by the inclusion of a highly capable floating-point capability at a time when the embedded market’s historically most significant supplier of processor technology no longer does so; by its inclusion of a superior graphics facility; and by the degree of integration, which has made board space available for manufacturers to increase the functional density of their offerings. Freescale is, and is likely to continue to be, a significant supplier to the embedded computing market. However, with its Core i7 announcement, Intel has clearly placed an important marker in the sand—and that can only be of enormous significance to vendors like GE Intelligent Platforms and to users of embedded computing worldwide. GE Intelligent Platforms. Charlottesville, VA. (780) 401-7700. [].

products &

TECHNOLOGY FEATURED PRODUCT Hypervisor Enables MSI Support for all Operating Systems

A bare metal (Type 1) hypervisor allows the execution of realtime operating systems (RTOSs) in parallel to operating systems like Linux or Microsoft Windows XP without adding any latencies to their native real-time performance. Deterministic behavior remains fully intact. Because embedded Hypervisors and real-time extensions for Linux or Windows typically require interrupts to be assigned exclusively to the different operating systems, system configuration can be very difficult and sometimes even impossible. To avoid conflicts due to shared interrupts, Version 2.2 of the RTS Hypervisor from Real-Time Systems now allows the use of message signaled interrupts (MSI) for all operating systems, even if these operating systems inherently do not provide support for MSI. In Version 2.2 it is now possible with the RTS Hypervisor to automatically analyze the CPU and cache topology of processor architectures such as the Intel Atom, Core, Xeon or Nehalem and intelligently assign CPUs to individual operating systems like Windows or an RTOS. This feature ensures that operating systems running in parallel cannot negatively affect each other due to a shared cache topology. Furthermore, in order to expand support for deterministic operating systems, Version 2.2 now features an open control module that provides a high-performance virtual network interface, shared memory and other virtualization components. Customers or operating system vendors can use this control moduleâ&#x20AC;&#x2122;s straightforward paravirtualization interface to integrate their own operating system or any other real-time code into their RTS Hypervisor-based system. By partitioning processor cores, memory and I/O devices into individual, independent computers, the RTS Hypervisor facilitates hardware consolidation and fosters an uncompromised reduction in overall system costs. Devices or machines that currently use an embedded hardware board in parallel to a computer executing Windows XP can now safely be merged onto a single Intel multicore hardware platform, thus greatly reducing design, manufacturing and maintenance costs. With just one dual core CPU, any RTOS can now execute in parallel to and completely independent of Microsoft Windows, for example. Using the RTS Hypervisor, the number of operating systems that can execute simultaneously is limited only by the number of available CPU cores. There is no requirement that supported operating systems be identical or dissimilar. For example, using the RTS Hypervisor, it is just as easy to run four instances of the same RTOS on a Quad-Core processor as to execute four different operating systems. The RTS Hypervisor technology does not restrict the many possibilities.



Thanks to strict separation of individual operating systems, any OS in the system can be independently booted in a user-defined order. The RTS Hypervisor even makes it possible to reboot one operating system while the others continue to run. Using a shared memory mechanism as well as a TCP/IP virtual network, communication between operating systems is straightforward. Out of the box, the RTS Hypervisor currently supports Windows XP, Windows CE, VxWorks, QNX, Microware OS-9, On Time RTOS-32, Linux and preemptive Linux in any combination. Real-Time Systems, Ravensburg, Germany. +49 (0) 751 359 558 â&#x20AC;&#x201C; 0. [].


Multiple Graphics Expansion Modules Support up to Six Displays per System

Adding multiple displays to systems is becoming increasingly popular for high-end and complex applications. Matrox Graphics has announced multiple DualHead2Go and TripleHead2Go Graphics eXpansion Module (GXM) support to drive up to four or six monitors, respectively, from a single system. A second GXM can now be connected to the secondary output of a supported dual-monitor graphics card so two DualHead2Go GXMs can power up to four outputs in 2x2 or 4x1 modes, while two TripleHead2Go units can be combined to connect six displays to produce either a 3x2 or 6x1 setup. Matrox currently offers multi-GXM support with the 2.06 (or above) GXM software suite. A maximum of two GXMs—of the same make and model—can be connected to a supported graphics card with two available outputs of the required type. Multi-GXM stretched desktop mode is available with Matrox M-Series cards, while independent desktop support is available with supported M-Series, ATI and NVIDIA graphics cards. Pricing ranges from $169 to $329 depending on version (analog, digital or Display Port) and model.

Ad Index

Matrox, Montreal, Canada. (514) 822-6366. [].

Fibre Channel XMC Interface for Embedded Hits 8 Gbit/s

Get Connected with technology and

10 Gbit Ethernet PCI Express FPGA Accelerator Card companies providing solutions now

Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

An 8 Gbit/s Fibre Channel XMC interface product allows embedded system applications to leverage ultra-high-speed Fibre Channel technology for performance networking and storage applications. The silicon-based architecture and extensive software support of the Model FCA2540 XMC from Critical I/O achieves sustained data rates as high as 1600 Mbyte/s (1.6 Gbyte/s), 15 µsec RDMA data transfers, and up to 300,000 IOPS (IO operations per second). These performance characteristics and RDMA & SCSI protocol support make the 8 Gbit Fibre Channel suitable for performance networking applications and an attractive choice for performance storage applications. However, integrating this technology into real-time and embedded systems can be quite challenging due to the importance of mature drivers and libraries. The hardware is relatively straightforward but the supporting software is very difficult. Critical I/O’s investment in more than 50 man-years of development in Fibre Channel software is one of the key features that more embedded systems designers can leverage for their products. The mature software offers customers the ability to integrate Fibre Channel products without wasting time debugging poorly written and inadequate drivers, or worse, having to attempt development of drivers from scratch. The FCA2540 XMC is part of Critical I/O’s 7th generation of Fibre Channel interfaces. This hardware interface dissipates only six watts but provides two independent 8 Gbit Fibre Channel ports, 8 lane PCI Express host interface and extensive integrated hardware BIT. It is supported by a full complement of library and drivers for VxWorks, Linux and Windows. It is compatible with X86, PPC and DSP-based embedded processor boards. Critical I/O, Irvine, CA. (949) 553-2200. [].

A low-profile PCI Express FPGA accelerator card features a 10 Gbit Ethernet interface directly coupled to a Xilinx FPGA. The Get Connected with technology andPCIecompanies prov 180 from Nallatech is targeted at Signal Intelligence, Network Security Get Connected is a new resource for further exploration into pro and Algorithm Acceleration applications. The PCIe-180 features anApplication ondatasheet from a company, speak directly with an Engine board Xilinx Virtex-5 user FPGA directly a high-bandwidth, in touch with the rightcoupled Whichever level of service you requir Get Connected will help you connect with the companies and produc flexible memory configuration that includes ECC and parity protection. Five banks of DDR-II SRAM provide up to 10 Gbyte/s of sustained, random access memory bandwidth. A single bank of DDR2 SDRAM memory provides 4 Gbyte/s of deep storage local to the user FPGA. The PCIe-180 is tightly integrated to the Host platform via a x8 PCI Express connection supporting sustained bandwidths of up to 2.2 Gbyte/s. Optimized VHDL memory controller IP cores and reference designs are included as part of the standard product deliverables along with driver and API source code for 64-bit Linux operating systems. The PCIe-180 complies with the “low-profile” half-height, halflength PCI Express mechanical specification. This enables compatibility with almost all high-density server and blade center platforms from leading OEMs such as HP, IBM, DELL, CRAY and SGI. Depending Get Connected withthe companies andstarts at $2,995 in volume upon configuration, pricing for PCIe-180 production.products featured in this section.


Nallatech, Camarillo, CA. (805) 383-8997. [].

Get Connected with companies and products featured in this section.




AdvancedMC Processor Board with Core i7 and Integrated Graphics

A single-width AdvancedMC processor module, designed with the new Intel Mobile Core i7 processor, offers a high-end combination of computing power and integrated graphics when utilized in MicroTCA and AdvancedTCA integrated platforms. The AM4020 AdvancedMC processor board from Kontron integrates the memory controller, PCI Express and the graphics processor within the multicore processor. Equipped with the highly integrated Intel QM 57 Platform Controller Hub, it offers high power density and performance on an extremely compact footprint. Its overall performance makes it suitable for MicroTCA and AdvancedTCA telecommunications applications such as IPTV, media servers and media gateways, conference systems, and test systems for wireline networks. The Kontron AM4020 is also an attractive fit for the medical, automation, aerospace, military and security markets, which require fast data processing. With MicroTCA.1 support for a robust system design and an optional temperature range of -25° to +70°C, it withstands the toughest mechanical and thermal environmental conditions. The AM4020 AdvancedMC CPU board features the new Intel Core i7 processors with 2.0 (25W TDP) or 2.53 GHz (35W TDP) and 4 Mbyte L3 cache. The integrated memory controller enables direct access to up to 8 Gbytes of dual channel DDR ECC RAM at 1066 MHz. Compared to the previously available AdvancedMC CPU boards with Intel Core 2 Duo processors, customers can expect to experience up to 100% higher overall performance. In addition, the AMC.1/.2/.3-compliant AM4020 CPU board offers eight PCI Express lanes to the backplane, configurable as 2 x PCIe x 4 or 8 x PCIe x 1. There are also four GbE ports; two on the front and two on the backplane (AMC.2) as well as 4 x SATA. For systems without separate hard drives, up to 32 Gbytes of flash memory can be implemented via a SATA flash module, which is securely screwed to the PCB. The board features a DisplayPort output on the front panel making additional graphics modules unnecessary. Alternatively, a COM port for external management access is available. A USB 2.0 port with mini USB jack on the front panel rounds out the feature set. The AM4020 has full hot-swap capabilities for monitoring, controlling and replacing the module. The Intelligent Platform Management Interface (IPMI) enhances the board’s availability while reducing the overall operating costs and mean-time-to-repair. For board management and basic IPMI commands, it features a dedicated Module Management Controller (MMC). The highly integrated Kontron AM4020 AdvancedMC processor board is available in both mid- and full-size formats. It supports Windows XP, Windows 7, as well as VxWorks 6.8.and various Linux distributions such as RedHat 5.3, SUSE 11.2 and Wind River Linux PNE 3.X. Kontron, Poway, CA. (888) 294-4558. [].



6U VME Single Board Computer with Dual-Core Freescale Processor

A new 6U VME SBC is equipped with Freescale Semiconductor’s dual-core MPC8572E PowerQUICC III processor. The XCalibur1531 from Extreme Engineering Solutions is a high-performance 6U VME single-board multiprocessing computer that is suitable for ruggedized systems requiring high bandwidth processing and low power consumption. With dual PowerPC e500 cores running at up to 1.5 GHz, the MPC8572E delivers enhanced performance and efficiency for today’s embedded computing applications. The XCalibur1531 provides two separate channels of up to 4 Gbytes (2 Gbytes each) DDR2-800 ECC SDRAM and two PrPMC/PrXMC slots, as well as 256 Mbytes of NOR flash (with redundancy). It also supports four Gigabit Ethernet ports, PMC I/O, XMC I/O and RS-232/422/485 serial ports out the front panel and/or P2/P0 backplane connectors. The XCalibur1531 is a powerful, feature-rich solution for the next generation of computationally intensive embedded applications. Additional features include up to 16 Gbytes of NAND flash and 256 Mbytes of NOR flash, one SATA 3.0 Gbit/s port and three USB 2.0 ports. In-house operating system support includes board support packages for Green Hills’ Integrity, Wind River VxWorks, ONX Neutrino and Linux. Pricing starts at $7,985 and varies based on processor speed, memory configuration and ruggedization level. Volume discounts are available. Extreme Engineering Solutions, Middleton, WI. (608) 833-1155. [].

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Compact Form Factor Computer-on-Module for Industrial Temperatures

A compact form factor COM Express Type 2 Computer-on-Module is specifically designed for use in the industrial temperature E2 range from -40° to +85°C. The new microETXexpress-XL from Kontron features the Intel Atom processor Z520PT and Intel System Controller Hub US15WPT. The microETXexpress-XL with the robust COM Express Type 2 connector is specifically designed for applications under extreme environmental conditions ranging from very high to very low temperatures, and especially stressful cycling thermal conditions such as in UAVs, which experience high temperatures on the ground and extremely low temperatures at their operational altitude. All components of the microETXexpress-XL are fully industrial temperature rated and are vendor-confirmed to withstand temperatures from -40° to +85°C. Within the dimensions of its compact footprint (95 mm x 95 mm), the Kontron microETXexpress-XL offers a comprehensive feature set. Based on the Intel Atom processor Z520PT, it supports up to 2 Gbytes of soldered DDR2 system memory and even offers room for an optional onboard 2 Gbyte Solid-State Drive (SSD) on the module. Furthermore, taking advantage of the full bandwidth of the COM Express Type 2 connector, it offers 1x Gigabit Ethernet, 1x Serial ATA, 1x PATA and 8x USB 2.0, as well as 2 PCI Express x1 Lanes and PCI for customer-specific extensions. With the SDVO port for DVI, SDTV and HDTV along with 24-bit single channel LVDS, the Kontron microETXexpress-XL offers extensive connectivity options for various displays and monitors. Intel High Definition audio rounds out the feature set. These extensive features make the Kontron microETXexpress-XL one of the most I/O-rich compact FF Computer-on-Modules available for extreme environments. The Kontron microETXexpress-XL supports Linux, QNX, VxWorks as well as Windows XP, XPe and CE. Kontron, Poway, CA. (888) 294-4558. [].

PCI/104-Express SBC with Core2 Duo/Celeron M Processors

High-Density 16-bit D/A PMC Module with Software-Selectable Output Ranges

Advanced Digital Logic, San Diego, CA. (858) 490-0597. [].

Tews Technologies, Halstenbek, Germany. +49 (0) 4104 4058-0. [].

A PCI/104-Express single board computer is based on the Intel Core 2 Duo / Celeron M Small Form Factor (SFF) processors and the Intel GS45 Express (Cantiga) chipset. Based on the 45nm process, the ADLGS45PC from Advanced Digital Logic sets a new standard with managed thermals, combined with superior performance in an embedded PCI/104-Express form factor. The Intel Core 2 Duo SFF and Celeron M SFF processors guarantee genuine Intel architecture to small form factor and thermally constrained markets. The Intel GS45 Express GMCH coupled with the Intel ICH9M-E I/O controller hub offers an impressive list of high-performance features that make full-size board makers nervous. The ADLGS45PC takes advantage of these features by delivering high performance and managed thermals in a compact form factor. The Intel graphics controller drives a CRT to 2048x1536 and/ or 18/24/36/48-bit LVDS LCD to 1600x1200 resolution. Memory is added via an SODIMM204 socket that will accept up to 2 Gbytes of DDR3-1066 DRAM. In addition to ACPI/APM functions, the ADLGS45PC has the following features: 8x USB 2.0, 2x RS232/422/485 COM ports, PS/2 Keyboard and Mouse, LPT, AC97 Sound / 7.1 HDA and 2x 10/100/1000MBit LAN. The ADLGS45PC also includes four onboard SATA 3 Gbyte ports with RAID 0/1/5/10 support.



A standard single-wide 32-bit PMC module provides 32 or 16 channels of 16-bit analog outputs. The TPMC554 is ideal for applications in industrial, transportation and COTS aerospace/defense. The TPMC554 from Tews Technologies features software selectable output voltage ranges of 0-5V, 0-10V, 0-10.8V, ±5V, ±10V or ±10.8V, which can be individually set per channel. The conversion time is typically 10 µs and the DAC outputs are capable to drive a load of 2 kΩ, with a capacitance up to 4000 pF. The double-buffered DACs allow simultaneous update of all channels for simulation applications. A sequencer on the TPMC554 supports the periodic updating of enabled channels with a sequence timer range from 10μs to 11.93h. In addition to the double-buffered distributed RAM inside the FPGA, the TPMC554 provides 2M x 16-bit external SRAM to store values that are known in advance. This feature can also be used to periodically output any kind of waveform or bit pattern. The size of the FIFO for each DAC channel is adjustable. Physical connectivity is achieved through a HD68 SCSI 3 type front I/O connector. Each TPMC554 is factory calibrated. The calibration information is stored in an onboard serial EEPROM unique to each PMC module. The TPMC554 operates in extended temperature range (-40° to +85°C) standard. All Tews Technologies products feature a five-year warranty. Driver software is provided for operating systems including VxWorks, Windows, Linux, LynxOS, Integrity and QNX6.


Diagnostic Tool for Long-Term Monitoring of CAN Bus Systems

The new CANobserver from IXXAT enables the physical and logical long-term monitoring of CAN, CANopen and DeviceNet systems. For this, the device is permanently integrated into the network and continuously monitors and records the data transfer for up to several years. Sporadic negative impacts, such as external EMC interferences or a slowly deteriorating signal quality caused by worn plug connections, can be detected by the physical layer diagnosis and logical frame monitoring in a timely manner. Thus, the CANobserver is able to inform the system operator before any communication error occurs. The CANobserver comes with LEDs to display bus load and error status and optionally the power supply status. In addition, free programmable error outputs can be used to trigger external devices and signalers. An Ethernet interface is used to connect the CANobserver to the PC, which also enables the operation of the device by an easy-to-use Web interface. Recorded messages can be stored using the universal XML format. The connection of the device with a control center can be made via SNMP. The CANobserver comes in an IP20 aluminum housing for DIN rail mounting. The power can be supplied within a wide range between 9-36V DC.

Ad Index

IXXAT, Bedford, NH. (603) 471-0800. [].

Capacitive Touch Switches Improve Transparency with Less Reflectivity

An advanced capacitive touch switch technology detects variations in position and command, eliminates air gaps and reduces the number of layers required. This technology from Optrex America offers the highest standards of optical performance with exceptional ease of design for human machine interfaces, handheld terminals, gaming, medical equipment, and point-of-sale and mobile applications. The capacitive touch screens respond to fingertip input control without requiring application of any pressure. The structures are very robust and the sensor elements will not wear out. Lifetimes are approximately 100 million touches. Optrex’s new capacitive touch switch solutions provide clarity and ease of design. Improved visibility results from less reflectivity and higher transparency of the image displayed through the touch panel and allows for a thinner touch screen in front of the LCD (up to 0.5 mm - 0.7 mm thick in the viewing area). Transparency is a minimum of 95% and reflection is less than 15%. The capacitive touch screens also have a wide operating temperature range, -20° to +70°C. Touch screens utilizing Optrex’s technology are more compact, lighter in weight, more durable (including better resistance to liquids) and easier to clean. Display solutions incorporating Optrex’s capacitive touch technology are currently available for demonstration and new product designs. Sample pricing is $50.00 for T-55343 (3.5" transmissive); $66.00 for T-55149 (3.0" transflective); and $70.00 for T-51963 (3.5" transflective). Optrex America, Plymouth, MI. (734) 416-8500. [].

Get Connected with technology and companies providing solutions now

Get Connected Data Loggers for FlexRay and CANis a new resource for further exploration

into products, technologies and companies. Whether your goal A new data logger for automotive comis to research the latest datasheet from a company, speak directly munication systemswith is available as a Baan Application Engineer, or jump to a company's technical page, the sic or Plus version. The CARcorder goal of Get Connected is to put you in touch with the right resource. from IXXAT Basic versionlevel of service you require for whatever type of technology, Whichever Get Connected will help you connect with the companies and products provides fully six CAN interfaces ( ISO you are searching for. 11898-2 / 11898-3), two LIN and two RS-232 interfaces and a USB host/device interface as well as an interface switchable between Connected with technology and companies prov SAE J1850 and K/L-line. Get In addition, the device comes Get withConnected digiis a new resource for further exploration into pro a company, speak directly with an Application Engine tal and analog inputs anddatasheet outputsfrom each in touch with the right providing eight channels. In addition, theresource. Whichever level of service you requir Get Connected will Plus version offers a FlexRay interface help withyou connect with the companies and produc two channels. The two-processor architecture of the CARcorder enables the fanless device to record all data synchronously and without any losses in real time and with a time stamp accuracy of 1 µs. The device is delivered with a rugged aluminum case, an integrated UPS for up to 10 seconds of power cut and it has a power consumption of less than 10 mW in deep sleep mode. The wake-up is initiated with the first valid message, which is automatically recorded. The power supply can be made in a wide range between 6.5 and 40V DC. With the PC-based software tool, the device can be configured via Ethernet, a direct USB connection or a USB stick. The software also enables the user to define trigger conditions and to set up diagGet Connected with companies and nostic tasks. The bus configuration is done by importing the related products featured in this section. bus description files (CANdB, FIBEX, A2L, ODX, open XML).


IXXAT, Bedford, NH. (603) 471-0800. [].

Get Connected with companies and products featured in this section.




Tablet-Sized Capacitive Touch Screen with Multi-Touch All-Point Capability

A tablet-sized capacitive touch screen technology with unlimited finger tracking capability enables, among other things, a user to manipulate multiple pictures on the screen simultaneously. The technology, based on Cypress Semiconductor’s TrueTouch touch screen solution for smaller-size portable electronics, will power touch screens between 7 and 17 inches with full multi-touch support. The inclusion of multi-touch support in the Windows 7 operating system has opened up the large laptop, netbook and tablet PC market to touch screen interfaces. Multi-touch capability is a key requirement for enabling designers to develop innovative applications and ways for the user to interact with his or her PC. Cypress’s TrueTouch family of devices enables designers to create new usage models for products such as tablet PCs, notebooks, netbooks, mobile handsets, portable media players (PMPs), GPS systems and other products. TrueTouch technology provides the industry’s most flexible touch screen architecture, allowing designers to implement differentiated features with Cypress’s legendary noise immunity based on patented capacitive sensing technology for flawless operation in noisy RF and LCD environments. Cypress Semiconductor, San Jose, CA. (408) 943-2600. [].

3U CompactPCI Board Combines Intel Atom with Onboard FPGA

A 3U CompactPCI (cPCI) single board computer (SBC) now combines low-power Intel Atom XL processors with an onboard FPGA for user-defined functions to offer enhanced embedded computing and I/O solutions for mission-critical industrial, mobile and harsh environment applications. The new F11S from MEN Micro opens up a new range of design flexibility for not only industrial and harsh embedded computing environments, but also for a variety of embedded mobile, railway and transportation applications, including automatic train control and infotainment systems, where reliability and operation in extended temperatures are critical. Depending on the application, the board can be equipped with various 45nm-based Intel Atom XL processors, which offer a maximum power dissipation of 7W at a speed of up to 1.6 GHz. The board’s specially designed heat sink enables operation across an extended -40° to +85°C (-40° to +185°F) temperature range. The board’s standard front I/O includes a COM interface via a D-Sub connector as well as two USB 2.0 ports, graphics via VGA or UXGA and a PS/2 interface for a keyboard or a mouse. Further interfaces include a Gigabit Ethernet slot via PCI Express x1 and an FPGA-based Fast Ethernet slot on the RJ45 connectors. The onboard FPGA also allows for customer-specific interfaces, such as serial interfaces, CAN bus, binary I/O, protocol converters or touch controllers to suit a user’s specific application. The F11S can accommodate up to three SA-Adapters for additional I/O. Depending on the number of adapters, the card occupies two or three system slots. The memory configuration contributes to the board’s flexibility with the incorporation of up to 2 Gbyte soldered DDR2 SDRAM, 2 Mbyte non-volatile SRAM, a CompactFlash card and a microSD card slot in addition to the 512 Kbyte of L2 cache integrated in the processor. A board management controller supervises temperature and power, and the Phoenix Award BIOS is adapted to every application. The F11S is available as conduction- or convection-cooled and supports a Windows or Linux operating system, with VxWorks and QNX available upon request. Pricing for the F11S starts at $1,443. MEN Micro, Ambler, PA. (215) 542-9577. [].



Attend one of our complimentary, technical and educationally-focused seminars, workshops, keynotes and exhibits. The events focus on the latest technologies from industry leaders and are demonstrated in breakout sessions and in the exhibition hall. RTECC is coming to an area near you... we invite you to attend ~ and be our guest for a complimentary lunch and parking, as well!

Melbourne, FL 04/13/10

Fort Walton Beach, FL 04/15/10

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Pico-ITXe Module Creates Platform for NextGeneration Fleet Management

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3/4/10 12:01:49 PM

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VIA Technologies, Fremont, CA. (510) 683-3300. [].

Rugged Transit Rack Cases in 4U and 12U

Transit rack cases for safe and reliable transport of electronic systems in rugged environments come in 4U and 12U heights. The cases feature superior shock/ vibration and extreme environment protection. Compliant to MIL-STD 810F and rated to IP65, the cases from Optima EPS are stable in temperatures from -40° to +158°F. They combine the resilience of a rotomolded case with a stainless steel 19â&#x20AC;? rack frame supported on anti-vibration mounts. The transit cases have an enhanced sway space between the inner frame and outer case to prevent contact with container shell. The inner frame is adjustable allowing for increased depth from both the front and/or the rear side for front panel, rear wiring or connector spacing needs. The racks have positive stacking, aligning flush at the front face regardless of the rack depth. Other features include ergonomic injection-molded carrying handles, optional cooling units and a wide range of accessories. Pricing for the cases is under $1,500 each depending on size, volume and configuration. Optima EPS, Lawrenceville, GA. (770) 496-4000. [].

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A new technology platform is initially targeted for fleet management device designs. The EPIA-P710-D from Via Technologies is a Pico-ITXe expansion module that allows system integrators to easily create cuttingedge fleet management devices that incorporate a range of the latest communication and intelligent management technologies. Measuring only 10 cm x 7.2 cm for easy integration into the dashboard of any vehicle, the Via EPIA-P710-D is designed to accurately suit any device that is fitted directly to the dashboard, occupying one DIN unit. The Via EPIA-P710 board is connected using SUMIT connectors, positioning the Via Eden processor downward allowing simple passive cooling designs that can incorporate the chassis of the device. The Via EPIA P710-D works in tandem with the Pico-ITXebased Via EPIA-P710 board, adding an I/O feature set tailor-made for fleet management device design. Front side I/O includes a SIM slot and SD card reader for easy access to GSM services and local data storage, as well as access for two USB 2.0 ports, audio jacks and HDD activity and power LEDs. Internal storage needs are provided by both IDE and SATA ports with rear I/O providing access to VGA, COM, UART and GPIO technologies.

10/16/09 11:43:57 AM

with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




Actel ADLINK Technology America, Inc........................................................................................2................................................................................................ AMD.................................................................................................................................26................................................................................................ End of Article Products American Portwell Technology, Inc.....................................................................................13............................................................................................................. Apacer..............................................................................................................................52.............................................................................................................. Get Connected with companies and Get Connected products featured in this section. with companies mentioned in this article. ATX Automation Technology Expo......................................................................................47............................................................................................................ Avalue ELMA Electronic

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Get Connected with companies and products featured in this section. Interface ISI Nallatech Microsoft Windows National Instruments..........................................................................................................9...................................................................................................................... One Stop Pentair Electronic Phoenix International.........................................................................................................52........................................................................................................... Real-Time & Embedded Computing Conference . ...............................................................51................................................................................................................. Red Rapids, Sealevel Systems..............................................................................................................31............................................................................................................ Small Form Factor SIG & PC/104 Showcase...................................................................38,39...................................................................................................................................... TRI-M Viking Modular Solutions Sanmina-SCI

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