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The magazine of record for the embedded computing industry

August 2009

Serial Interconnects: The

Next Generations

ATCA Advances in Telecom and Beyond Mobile Robotics Combine Sensing, Decision Making and Action 802.11n Brings Seamless IP to Wireless Industrial Networks An RTC Group Publication

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Serial Interconnects: The

44 AIM-USA Announces First Commercial HS1760 Test Product

Next Generations

45 6U VME Multi-Processor for Air-Cooled and Rugged Conduction-Cooled Apps


46 SATA/PATA SSDs Feature Higher Speeds and Capacities, Reliability Technologies



Technology in Context

Industry Insight

ATCA: Telecom and Beyond

Mobile Robots

Line Rate and Security: Mobile Robotics: Moving Robots 5Editorial 10 Balancing Isn’t it a Wonder that Anything Works? FPGA-based MicroTCAs Enable Forward 36 10 Gbit/s Network Traffic Insider 6Industry Latest Developments in the Embedded An Architect’s Checklist: Designing System Integration Marketplace a Carrier-Grade, Application-Ready Industrial Networks 16 ATCA Platform Small Form Factor Forum 802.11n Wireless Connectivity 8Small Form Factor: More than Boards Supports Seamless Industrial 40 Networks Products & Technology Embedded Technology Used by Solutions Engineering 44Newest Industry Leaders Rob Kraft, AdvancedIO Systems

Meghan Meckstroth, National Instruments

Dr. Asif Naseem, GoAhead Software and Simon Stanley, Heavy Reading

N. Venkatesh, Redpine Signals

Serial Interconnects Move to the Next Generations

Express Gen 3: Twice as Nice — and Then Some 24 PCI Steve Moore, PLX Technology

RapidIO 2.0 Moves into the Wireless Infrastructure 30 Serial Stephen M. Nolan and Devashish Paul, IDT

Digital Subscriptions Available at RTC MAGAZINE AUGUST 2009


AUGUST 2009 Publisher

Embedded Super Power #103:


Super Cool

Editorial EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

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Published by The RTC Group Copyright 2009, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.



Tom Williams Editor-in-Chief


Isn’t it a Wonder that Anything Works?

e who are so used to blithely discussing mission-critical systems, five nines reliability and all manner of security issues often forget—or suppress the uncomfortable awareness of—the vast complexity we have built into the world. It is relatively common to hear about viruses and cyber attacks, many of which appear to be coming from China. And we do know that things are constantly going wrong in various places and many people make very good livings finding and fixing the problems that constantly crop up. So far, there has been no vast, worldwide breakdown in the cyber world we have woven around ourselves, and the Internet was specifically designed to prevent that. Still, late at night when the moon is full I wonder. And recently, we here at RTC saw an incident that adds another dimension of worry—that completely competent systems may just fail to work together due to miscommunication or misunderstanding. We have a number of people who, thanks to the Internet, are able to work off-site around the country. I, for example, am able to work on a 32-acre piece in the Santa Cruz Mountains surrounded by trees, wildlife and clean air. We use a virtual private network (VPN) to let us have all the advantages of an office except for the fridge in the break room with interesting things growing in the back. One day, nobody could get their email and our IT consultant got about six frantic phone calls in 30 minutes. While we still don’t know exactly what happened, we suspect that an upgrade to Windows touched what turned out to be a hidden bug in the firewall’s operating system. They are still working on this and I’m making no accusations. But it brought home to me that even systems that have been long installed and thought stable can be brought down by what seem to be purely routine matters Extrapolate this relatively trivial example to the vast and ever growing dependence we have on embedded and connected devices, and one gets a mixture of terror and wonder. We can wring our hands over the problems we encounter; we can paint dark scenarios of what could happen if a truly determined attack took place (actually many reports of serious attacks are either not reported, suppressed or ignored), or if some unintentional megaflaw caused a worldwide collapse.

On the other hand, as the poet Rainer Maria Rilke once said, “. . . beauty is naught but the onset of terror that we just barely endure.” We can stand in awe and take pride in the fact that these things actually do appear to work. It is a thing of wonder that semiconductor fabs turn out millions of tiny dies on which electrons course through delicately treated silicon and ultimately keep planes in the air, patients alive, communications flowing and machines producing goods. That, considered against the latent fear of what could happen if it were all to break down, does make it a thing of beauty. That is also a source of optimism regarding the economy— namely that failure is not an option. We are beginning to see upticks in activity even during the summer, which is traditionally a somewhat lax season in our industry. Now that may have a number of causes, but I can’t help but suspect that among them is the realization that we cannot stand still—we have to keep peddling faster. We have set in motion a process that not only requires constant maintenance but also constant refinement and expansion. You can look at it as an organic construct that needs continuing care and feeding, or as some kind of Moloch that demands repeated human sacrifice, but it does appear to have a life of its own. For my part, I am inclined to look at the embedded connected world we are building as a natural stage in evolution— possibly partly because it may be the only way to mitigate the environmental and energy issues that have arisen as a result of the earlier stages of humanity’s industrial development. In the sense of the old saying that “the only way out of it is through it,” we are committed to the scientific and technical solution to our problems and to the problems created by science and technology. And as in every stage of the process of evolution, there will be starts and setbacks—just like in the economy—but the overall movement is forward. That’s why it is sometimes instructive to look up from our detailed day-to-day tasks and take in some of the scope of what is continuing to develop based on these amazing technologies— and just because we are the ones building them and who (mostly) understand them, does not make them any less amazing, or sometimes scary. RTC MAGAZINE AUGUST 2009




Wireless Sensor Network Recognized for IPv6 Compliance Arch Rock Corporation’s wireless sensor network has achieved the IPv6 Forum’s highest level of compliance with IPv6, the latest, most scalable version of the ubiquitous Internet Protocol. The Arch Rock PhyNet platform’s 6LoWPAN protocol stack implementation earned the Forum’s “IPv6 Ready-Phase 2 (Gold)” designation June 30 after passing a comprehensive set of more than 450 tests for conformance and interoperability. In March 2007, Arch Rock’s Primer Pack/IP WSN solution incorporated the first commercial implementation of IETF 6LoWPAN, an industry standard for IP communication over low-power wireless personal-area networks. In gaining the IPv6 Ready-Phase 2 designation, Arch Rock joins the ranks of major vendors in routing and switching (Cisco, Nortel, Huawei), PC hardware and software (Dell, IBM, HP, Microsoft) and consumer electronics (Motorola, Panasonic, Sharp). However, the list has previously included no companies in the area of “IP for Smart Objects”—embedded devices that gather information from the physical world. “The IPv6 Ready Logo Program Committee and the IPv6 community are delighted to see Arch Rock’s groundbreaking achievement with IPv6 Phase 2 readiness in this new tier of embedded smart objects and devices,” said Professor Hiroshi Esaki of the University of Tokyo and one of the world’s foremost pioneers in IPv6 protocol development and deployment. “It is even more exciting that embedded IPv6 and 6LoWPAN protocols are being applied to some of the most critical issues of our time, such as energy and environmental monitoring, through commercial solutions such as Arch Rock’s recently introduced Energy Optimizer.” The IPv6 Forum’s ( IPv6 Ready Logo Program is a conformance and interoperability testing program intended to increase user confidence by demonstrating that IPv6 is available now and is ready to be used. The program’s key objectives and benefits are to verify protocol implementation and validate interoperability of IPv6 products, provide access to free self-testing tools, and provide IPv6 Ready Logo testing laboratories across the globe dedicated to providing testing assistance or services.

Call for Apollo 11-Class National Effort to Deliver the Electric Car to Market

On the occasion of the 40th anniversary of the Apollo 11 moon landing, XP Vehicles, a nationwide electric vehicle company comprised of contractors and partners from across the nation and from across the auto and



aerospace industries, announced phase two of its “Giant Leap Program,” inspired by Apollo 11’s massive national program to put a man on the moon. The “Giant Leap Program” brings together companies, schools, associations and the public to educate, promote and deliver electric vehicles, along with green jobs, to market in retail volumes and prices.

XP Vehicles is developing technologies that have been tested on Mars, the Moon and across the Earth for the production of a new type of paradigmshifting ultra-safe, low-cost, electric automobile. Their effort is an example of space technologies coming back to serve fundamental service on Earth in the hands of mainstream consumers. XP Vehicles is one of the first U.S. Department of Energy, Section 136, AVTM loan applicants to receive notification that their application has been considered substantially complete. The company applied for a commercial $40M Department of Energy “ATVM” loan at the beginning of November 2008, and has been in extensive due diligence review by the U.S Government for the last seven months. Energy Secretary Chu has ordered funds from the program to be dispersed “as fast as possible.” XP Vehicles expects finalization soon and has also applied for additional loan and grant opportunities and is currently negotiating with investor opportunities.

Acromag Announces 7-Year Extended Warranty Program

Acromag has implemented a 7-year extended warranty program. All Acromag products now carry a base 1-year warranty, but qualify for up to six years of additional warranty protection when registered on Acromag’s Web site, Most products, including PMC I/O modules, Industry Pack products, PCI cards and CompactPCI, are eligible for a 6-year warranty extension.

PMC FPGA modules, specialty instruments and accessories, can double the warranty period to two years. Acromag’s quality management system has been certified for compliance with AS9100 quality standards. AS9100 is a widely adopted and standardized quality management system for the aerospace industry. AS9100 fully incorporates the entirety of the current version of ISO 9001:2000 quality management standard, while adding additional requirements relating to quality and safety. Many other practices have also led to significant advances in quality control. Acromag takes every measure to guarantee dependable operation and products that perform at or beyond their rated specifications. State-of-the-art manufacturing and military-grade components add an extra degree of ruggedness. All products are built to comply with IPC-A-610 Class II standards by IPC-A-610 certified assemblers, inspectors, technicians and supervisors. Printed circuit boards are purchased to IPC-6012 Class III standards and receive 100% inhouse inspection. An advanced water purification and board cleaning system prevents the introduction of contaminants in the manufacturing process. Plus, a strict static control program adopts the ANSI/ESD S20.20 standard as a guide for controlling static discharge.

CANopen via Bluetooth— May Add More Wireless Protocols

The CAN in Automation (CiA) international users’ and manufacturers’ group has established the Special Interest Group “CANopen via Bluetooth.” In the inaugural meeting the experts agreed to map the CANopen communication services such as service data objects (SDO) and process data objects (PDO) to the Bluetooth lower layers. The group will also specify CANopen-toBluetooth routers, in order to provide connectivity in heterogeneous network architectures. “The scope of the group is not limited to Bluetooth, other wireless communication technologies are welcome, too,” said Reiner Zitzmann (CAN in Automation). The chairman of the SIG, Harm-Peter Krause (ESD), invites all interested parties to join the standardization activities regarding CANopen via Bluetooth.

Excellence Center for Parallel Processing on GPUs.

Visual computing specialist Nvidia, and NeST, a provider of specialized multicore software services, have announced that NeST will be providing CUDA Professional Services and GPGPU Multicore services to their joint customers worldwide. CUDA is a general-purpose parallel computing architecture that leverages the parallel compute engine in Nvidia graphics processing units (GPUs) to solve complex computational problems. It includes the CUDA instruction set architecture and the parallel compute engine in

the GPU. Developers are able to program the architecture in C and run applications at the vastly increased performance offered by the parallel machine. NeST also will be setting up a CUDA Center of Excellence with the latest products from Nvidia to develop solutions for their customers. Nvidia’s CUDA parallel computing architecture, accessible through an industry standard C language programming environment, has already delivered cost-effective multi giga-flop performance, and has revolutionized visual computing across industry domains. NeST’s Multicore Services Group will help harness the new-generation GPUs from Nvidia, to deliver low-cost, fast-to-market products for their customers in the healthcare, security and consumer electronics domain. “This CUDA Centre of Excellence is the latest sign that GPU computing has established itself as a key technology for the future of high-performance computing,” said Daniel Saison, Nvidia sales director Middle East, Africa and India. “Working with NeST on this initiative will help us to bring our technology to an even wider range of companies and institutions, as well as focusing CUDA expertise in the field of imaging in the region.”

European Brands Push Ahead in Chinese Motor Drive Market

Chinese users of motor drives tend to favor brands of European origin according to the results of a user survey compiled and analyzed by IMS Research. One question in the survey asked users to name the

brand of drive that they had used in 2007. Of the top five most popular answers, three were the well-known European manufacturers ABB, Siemens and Schneider, which together accounted for some 45% of all responses. Mitsubishi and Fuji of Japan completed the top five with a combined 15%. The remaining 40% was split between a further 22 companies, indicating the fragmented nature of the market beyond the major players. The dominance of the European brands can perhaps be best explained by users’ perceptions of both the products and the suppliers themselves, revealed by additional questioning in the survey. While products manufactured by Asian firms tended to be thought of as less expensive solutions, their European counterparts were generally perceived to be industry experts offering premium quality products. Quality and industry expertise, or rather the perception of them, therefore play a seemingly fundamental part in the brand selection process, which is the harvest of long European presence in the Chinese motor drive market.

RTI Gears up New Field Operations Organization

Rea l-Ti me I n n ov a t i o n s (RTI) has announced strategic steps to capitalize on growth for its Data Distribution Service (DDS)-compliant middleware. RTI has established a Field Operations organization, which brings together all customerfacing functions: worldwide sales, professional services and customer support. Each team will be under the leadership of industry veteran, Curt Schacker.

This organization will put increased emphasis on leveraging RTI’s technology and expertise to deliver tailored solutions that minimize the time, cost and risk of DDS adoption. In conjunction with this move, RTI is also adding top talent to its sales team. Two seasoned sales managers have joined the company: Lee Cresswell, as director of International Sales, and Dave Scheibenhoffer, as director of Services Sales. This new organization positions RTI to capitalize on the significant momentum experienced by its services business and international sales; both are benefiting from a 30 percent annual growth rate in the DDS market. RTI’s services revenue doubled year-over-year in the first quarter of 2009, a trend expected to continue through the year. RTI has also built significant growth in international sales, with design wins increasing over 80 percent from 2007 to 2008. Schacker, who will be heading RTI’s Field Operations organization, joined RTI as vice president of Professional Services in January 2009. He has more than 20 years of experience in the real-time software industry, spanning engineering, sales, marketing and corporate management roles. He co-founded Embedded Solution Partners, which was named Silicon Valley’s 20th fastest growing company in 2006. He also served as vice president of Worldwide Marketing and Corporate Development for Wind River Systems.





Colin McCracken & Paul Rosenfeld

Small Form Factor: More than Boards


hen people write or talk about small form factors, almost everyone is thinking about small circuit boards, either single board computers or I/O modules or computer-onmodule CPUs. This perception has been furthered by the recent explosive growth in the small form factor board market. Yet, putting a smaller board in a big system is not what has everyone excited. The small form factor promise is to reduce overall system size and footprint and reduce power consumption and heat dissipation—the so-called “green initiative.” This size reduction enables a new class of embedded applications, from smaller medical devices to additional sophistication in field-deployable military technology—even truly wearable computers. But to construct a small form factor system, much is needed beyond a small CPU board and I/O modules. And progress to shrink these other areas has not kept up with the reductions in CPU size. One of our favorite axes to grind is system memory. For years, embedded CPU designers have had the choice of soldering memory directly to the CPU card or supporting a standard memory interface such as DIMM or small outline dual in-line memory module (SODIMM). Soldering memory tended to yield smaller, more rugged CPU boards, but it increases the number of SKU units the manufacturer needs to provide, increasing inventory cost and complicating the ability to forecast demand. While the traditional DIMM quickly became too large for all but the largest CPU boards, the SODIMM (the memory technology used on laptops) became the staple memory device for small form factor CPUs. The SODIMM mounts parallel to the CPU board, and the height of the socket allows passive components to be placed underneath. But the 30.00 mm x 67.6 mm SODIMM form factor is rapidly approaching the size of new CPU boards (the Pico-ITX form factor is 72 mm x 100 mm) and COM solutions (the 70 mm x 70 mm Q7). CPU and COM form factors will continue to shrink. The SODIMM system memory form factor is inadequate to support the continued evolution of this segment. Soldered memory is not an acceptable solution for many applications. Supporting a 64-bit data path requires multiple x16 or x8 devices, chewing up board space. A new small form factor embedded memory interface standard is badly needed. And it must be a standard with widespread acceptance to ensure support from memory module



manufacturers that require high volume to achieve the low memory costs required. But memory is not the only area requiring a shove to get small form factor support in gear. One of the biggest challenges in building a small form factor system is heat dissipation. The processors and chip sets used to build small form factor CPUs are much more efficient than those of even a few years ago. These systems can almost always be built without cooling fans, the nemesis of many embedded applications. However, to replace a fan with a humongous heat sink within a properly designed enclosure that facilitates convective cooling may solve the fanreliability problem, but it does little to ensure the small size of the resulting system. Creative thermal solutions to channel heat away from key heat producing components (read: processor and chipset) are required. Heat fundamentally looks for surface area to dissipate from—and surface area is one thing small form factor systems don’t have. Our last, but certainly not the only other area to highlight is the area of I/O connectors for externally interfaced devices. Standard connectors for items such as a video monitor, serial ports, USB and Firewire ports, and audio are all gigantic by small form factor standards. For example, the simple choice to put a DB15 VGA connector on a small form factor board occupies significant board space and destroys the ability to stack a same-sized I/O module on top of the CPU. Many small form factor board manufacturers use transition cables to get to bulkhead-mounted industry standard connectors at the other end. Transition cables are the items we love to hate. They enable small form factors, but they complicate the assembly process, increasing cost. They create a potential rat’s nest within a small enclosure. Repair and maintenance become a nightmare. And they are frequently not cheap. It’s time for new, small industry standard connectors for all these devices, similar to the mini-USB connectors used on cell phones and cameras. Small form factor boards, powered by efficient new processors and chipsets have enabled a new range of embedded applications. For this growth to continue, it’s time to start shrinking other areas of the systems to keep pace. –Paul Rosenfeld

Technology in


ATCA: Telecom and Beyond

Balancing Line Rate and Security: FPGA-based MicroTCAs Enable 10 Gbit/s Network Traffic The flexibility and scalability of MicroTCA and FPGAs keep traffic flowing quickly, smoothly and securely in 10GbE networks. by Rob Kraft, AdvancedIO Systems


he advance of 10 Gbit Ethernet networks and the increased data rates have provided both opportunities and challenges for developers of highperformance, real-time applications. The number of Internet subscribers and their use of bandwidth continues to rise in response to richer video and image content. Consequently, service providers need a bigger, 10 Gbit/s pipe, which 10GbE can provide. This means aggregating 1 Gbit links into 10 Gbit links, and replacing single 10 Gbit links with multiple 10 Gbit links. Although users expect consistent, smooth access to content, higher bandwidths lead to a greater likelihood of performance bottlenecks. Therefore, network performance must be monitored and optimized. Meanwhile, since security attacks have become more sophisticated, more bandwidth must be monitored and deeper analysis of packets is required. Because the processors they’ve been using in network performance monitoring/ optimization and security systems can’t keep up with the data streaming from a 10GbE pipe, service providers’ applications won’t function with existing systems. There-



fore, they must scale the internal bandwidth of these systems in step with these changes. The scaling they need cannot be done using either the current 1GbE hardware employed for security, packet inspection and load balancing functions, or by adding more of the general-purpose processors often used in that hardware, since the congestion problems don’t scale in a linear fashion. MicroTCA provides a platform that can accommodate this scaling for performance monitoring and security applications. With their switched fat-pipe backplanes and ability to add in more AMC cards as required, MicroTCA architectures have the flexibility and capability to scale when the processing and data bandwidth exceeds the capacity of traditional server/line-card solutions. Although the MicroTCA switched backplane architecture can provide what may be thought of as the expandable highway infrastructure to accommodate more traffic, there remains the problem of building new equipment with sufficient capacity to service that mass of traffic without simultaneously clogging it and creating a bottleneck during servicing. FPGA-based

AMC cards are a key enabling technology for this equipment. FPGAs, when programmed with suitable algorithms, can perform the myriad inspecting, filtering and manipulation tasks on packets flowing by at 10 Gbits/s, a rate that would overwhelm general-purpose processors. The FPGAs may be thought of as “service stations” that “service” the packets and keep them moving along at these high rates.

Application Needs

Network performance monitoring/ optimization applications investigate network performance patterns and identify potential architecture bottlenecks and equipment problems. These applications need wire-speed packet inspection and manipulation to identify usage trends and measure traffic flows to plan architecture upgrades and build-outs—for example, observing how new services are being handled by existing equipment. They also need rapid, real-time identification of not only major performance problems, but also more subtle ones that might otherwise go undetected, leading to frustrated customers who take their business elsewhere.

technology in context

Security applications protect the network and its subscribers from the everincreasing number and sophistication of cyber threats and attacks that consume network bandwidth and jeopardize personal information and transaction security. In order to detect such threats, the content of all data packets must be inspected. This is a computationally intensive task at 1 Gbit/s, let alone at 10 Gbits/s. Even the act of offloading processing of the 10GbE transport protocol, which could be provided by a commercial network interface card (NIC), is not enough to help the CPU keep up with the application. After the incoming data leaves the 10GbE interface and arrives on the local fabric or CPU, it is already overwhelming that fabric or CPU (Figure 1). The alternative is to send out the incoming data to large processing farms, but the space and power required, as well as the cost of these, are prohibitive. Furthermore, this alternative is not even available if the data rate already would overwhelm the fabric used for distribution to and communication within the farm. Instead, the solution lies in doing more at the pipe itself—including load balancing, time stamping and packet inspection— before the incoming data ever leaves the 10GbE interface. This can be achieved by replacing the NIC with an FPGA-based 10GbE interface that supplies both NIC and packet processing offload functionality. For higher-bandwidth networks, a MicroTCA 10GbE interface appliance powered by FPGAs can be placed between the 10 Gbit pipe and the existing 1GbE hardware. The appliance provides offload and load balancing functionality to leverage existing hardware. In the highest-bandwidth networks, including future 40 Gbit/s and 100 Gbit/s systems, the same appliance can perform NIC and packet processing functions, as well as performance monitoring, by the addition of more cards. The appliance thus can be scaled with increasing bandwidth demands (Figure 2).

The FPGA Advantage

There are several main advantages to using FPGAs as “service stations” in this new class of compute-intensive equipment, the MicroTCA appliance. These advan-




Figure 1 Intrusion protection systems that guard a network from cyber threats require inspection of the content of data packets, a computationally intensive task.

tages include the tasks they can perform before incoming data leaves the 10GbE interface, the optimized performance FPGAs can bring to these tasks, and the fact that FPGAs can be reprogrammed for new tasks as traffic evolves. Examples of some of the tasks themselves are load balancing, line-rate packet inspection, packet slicing and filtering, and the creation of multiple DMA queues. Load balancing is done whenever the data rate exceeds the sustained capability of any one CPU, and the processing that occurs in each of several CPUs may require different amounts of time to complete. In load balancing, a single 10GbE interface absorbs the data that must be distributed among CPUs in a box—such as a MicroTCA box made up of AMC modules—to perform the processing. The FPGA-based 10GbE interface can function in a control loop where feedback from the CPUs is used to determine where to send the data next in order to balance the load. An open-loop scheme may also be used, in which packets are inspected and the packet type or content determines the destination CPU. Load balancing is used in both network performance monitoring and security applications. One of the challenges in fully utilizing multicore Pentium processors is the fact

that a typical NIC will dump data from multiple sockets into a single queue. This means that one core on the CPU needs to be the interface to the NIC and distribute data to the others, which can lead to the single-core interface getting swamped. One way to do load balancing that solves this problem is to create multiple DMA queues with an FPGA-based solution— for example, one that is based on the particular socket or socket type—so that individual cores can access the data independently, and the first core is freed up from the interfacing task. This technique is common to virtually any multiprocessor telco application or system. Emerging, increasingly sophisticated attacks and threats require correspondingly sophisticated security measures. Statistics obtained by merely sampling packets in flows are insufficient to detect the more insidious modern threats. Instead, the content of every single packet must be inspected, and at line rates. This compute-intensive task, known as deep packet inspection, requires hardware acceleration. Although deep packet inspection cannot be done on a GPP, packets can be inspected at 10 Gbit/s line rates in an FPGA. The detection of anomalies can be flagged for more intense analysis, sending only the ones that really need further RTC MAGAZINE AUGUST 2009


technology in context


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analysis by GPPs, so that the output data rate flowing into the GPP is much lower than the 10 Gbit/s incoming data rate. Both packet slicing and packet filtering can achieve data rate reductions for network performance monitoring/optimization systems and security systems, such as those that provide intrusion protection. In packet slicing, the headers are kept but varying amounts of payload are sliced off. In packet filtering, only packets matching certain criteria—such as a particular IP address, size, or protocol— are passed through to subsequent processing elements. FPGAs can bring optimized performance to these tasks. They bring massive amounts of configured logic gates operating in parallel to bear on incoming data, giving them the ability to process packets on the fly at line rates. In contrast to other programmable devices like multicore CPUs and specialized ASICs, FPGAs provide unmatched, extremely tight control over all aspects of processing operations. They can therefore be programmed as hardware processors optimized for the performance of challenging tasks. Furthermore, FPGA-based appliances can easily be reprogrammed for new tasks as traffic evolves. Such new tasks may consist of either new functionality added to existing tasks—such as load balancing based on an emerging traffic protocol—or additional functionality in the form of entirely new tasks, such as redeploying a network security appliance as a performance

monitoring device for network optimization, or as a multi-protocol gateway.

The MicroTCA Advantage

The growth of MicroTCA in telco and other high-performance real-time applications has been propelled by the same types of advantages that FPGAs bring to box-level designs: small size, scalability, the flexibility to easily add new or different functions by changing or replacing up to 12 cards on a single backplane, and the ease of customization via changing the mix of cards in the chassis. The MicroTCA architecture facilitates the design of smaller, lower-power, yet highly scalable plug-in appliances that provide the hot-swap and shelf management capabilities found in their larger ATCA cousins. MicroTCA’s high-speed, protocol-agnostic, switched backplane meshes well with the needs of packet-switched communications. It has built-in hot-swap and redundancy via the backplane, which can run two fabrics to each card so that each one forms a separate multi-hub controller. This provides the high reliability needed in security systems. These characteristics, when combined with its small 2U form factor and high communication bandwidth (from 40 Gbits/s to 1 Terabit/s or more), make MicroTCA an excellent design platform for building the FPGA-based 10GbE interface appliance described above. A MicroTCAbased appliance can start relatively small, with empty slots that can be filled with

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technology in context

additional cards of the required type as needed. This architecture meshes well with the need to deploy these appliances in a variety of places in the network, at the edge as well as in the core. For example, the appliance can be placed at connections between wireless and wired networks, at various points within a wired network, and wherever enterprise networks interface with service provider networks. A single appliance architecture can be used

in all of these locations, but scaled by the capacity needed. For example, in locations where small systems are required, only a few slots can be filled, and in locations that need higher bandwidth capacity, more slots in the box can be filled with the appropriate cards. The V3021 from AdvancedIO Systems is an AMC module suited to network security and performance monitoring applications requiring wire-speed packet in-

Figure 3 An FPGA-based AMC module such as AdvancedIO Systems’ V3021 can perform the highspeed packet capture, filtering and processing needed in network security and performance monitoring applications.

spection and manipulation (Figure 3). The V3021 is equipped with two optical 10GbE interfaces, a Xilinx Virtex-5 FPGA, and multiple, large, independent, high-speed memory buffers to handle high-speed packet capture, filtering and processing. The module runs AdvancedIO’s expressXG framework that accelerates the development of high-bandwidth telecom applications. The framework, consisting of FPGA firmware and host software, abstracts the underlying FPGA hardware interfaces, board-level details, and control and set-up functionality, and provides key packet processing building blocks for high-bandwidth application development. The higher bandwidth of 10GbE networks brings challenges such as performance bottlenecks, which require service providers to monitor and optimize network performance. At the same time, the increasing sophistication of security attacks demands the monitoring of even more bandwidth and requires deeper analysis of packets. But existing equipment cannot run these applications at higher network speeds, or provide the scaling that service providers need. The flexibility and architectural scalability of the MicroTCA architecture, combined with the flexibility and performance scalability of FPGAs, make possible a 10GbE interface appliance that performs the line-rate monitoring or security functions. AdvancedIO Systems Vancouver, BC. (604) 331-1600. [].


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Technology in


ATCA: Telecom and Beyond

An Architect’s Checklist: Designing a Carrier-Grade, Application-Ready ATCA Platform A network element constructed with COTS components can save development effort upfront, as well as reduce maintenance and upgrade headaches downstream. Here is a checklist of considerations for creating a carrier-grade, network-ready system. by Dr. Asif Naseem, GoAhead Software and Simon Stanley, Heavy Reading


n this day of service-oriented architec30-48 Months Development Cycle tures that offer converged data, voice, video and mobile services on the same System Platform Revenue Integration Design & Generating Field Trials IP-based network, continuous service is & QA Development Services an increasingly important requirement. However, designing a network element for deployment in a network expected to pro18-24 Months 6-12 Months 6-12 Months vide uninterrupted service is a complex task. Such a task requires specialized exImpact of Pre-Integration pertise, and significant resource and time nies providing solutions nowWhile the availability of commitment. 19-30 Months Development Cycle ion into products, technologies and companies. Whether your buildgoal is to research the latest commercial-off-the-shelf (COTS) ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ing blocks makes it easier, designers must you require for whatever type of technology, Revenue System General a disciplined approach to ensure and productsfollow you are searching for. Field Trials Generating Integration Commercial the resulting system meets the most critiServices & QA Availability cal requirements.

#1: COTS or Not?

The first decision to make is determining where to leverage COTS components throughout the system. A vibrant COTS ecosystem including standardsbased hardware—shelves, blades, components, etc.—and high-availability

End of Article Get Connected

with companies mentioned in this article.


9-12 Months

4-6 Months

General Commercial Availability

6-12 Months

Figure 1 Use of COTS can significantly improve velocity to revenue.

middleware makes it very compelling to put together a system that accelerates time-to-market and revenue for even the most complex telecommunications applications. Empirical data in the industry is emerging that reinforces this assertion


Get Connected with companies mentioned in this article.

(Figure 1). This data shows that in-house development of a network element takes anywhere from two and one-half years to four years from concept to commercial deployment. Before revenue-generating applications are developed, significant


technology in context

HA Middleware


Application Specific Subsystem


Base Platform

CG Linux

Dual/Quad CPU

10GE Switch

AMC Carrier

ATCA Chassis, Backplane, PSU, Cooling, ShMM

Figure 2 Second-generation ATCA platforms offer faster speeds and higher functional density.

R&D time and effort goes into designing the platform. Cost and effort can be saved if such a platform is acquired from the ecosystem, and resources quickly applied to the development of applications and services. A side benefit of such an approach is that since the platform has already been put together with pre-tested and pre-integrated COTS components, the overall testing and quality assurance effort is also reduced. Choosing a standard platform like ATCA does not however mandate the use of COTS components throughout. Equipment providers can opt to use in-house solutions for any or all of the system, taking advantage of the standard platform with custom or cost-optimized components as required. Many companies use a mix of COTS and in-house design, working with suppliers to integrate and test a common platform for multiple products.

#2: Choosing a Platform

Once the COTS question has been answered, it’s time to choose a hardware platform. While the market offers many compelling choices, traction around ATCA is rapidly increasing. According to a recent survey conducted by Light


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Reading, 50 percent of the NEPs reported that they are developing systems using ATCA hardware. Furthermore, the survey data shows that an increasing number of telecommunications applications are beginning to use the ATCA systems. When choosing ATCA hardware, careful consideration must be given to several factors; key among them are switching options, fabric capacity, configurability, and thermal and NEBS validation. The ATCA specifications provide many options for configuration of interfaces and switching across the backplane. Options for the fabric interface include Gigabit Ethernet, Gigabit Fibre Channel, 10 Gigabit Ethernet and RapidIO. The designer must keep in mind future upgradability when choosing a particular switching option. Over the past five years the performance of Ethernet-based ATCA systems has grown dramatically. In 2004, the first ATCA systems with a single gigabit Ethernet interface per blade had a total chassis capacity of less than 70 Gbits/s. With 10 Gigabit Ethernet switching, the capacity of second-generation ATCA systems has grown to almost 160 Gbits/s, and will

technology in context

grow further to 600 Gbits/s for thirdgeneration systems with 40 Gigabit Ethernet (Figure 1). ATCA systems not only offer many different options for ATCA blades but also enable the use of advanced mezzanine cards (AMCs). AMCs are hot swappable and have integrated system management functions. AMCs can be used in ATCA, MicroTCA and other platforms. There are multiple configurations for AMCs including single or double width, and full, mid or half-size modules. Thermal and NEBS validation are a key part of ATCA-based system development. Quad core CPUs, 16 core NPUs and multicore DSPs are pushing the limits on power delivery and cooling. Chassis airflow varies from slot to slot, cooling efficiency depends on the airflow direction and distribution, airflow depends on board topology, and theoretical airflow data is typically based on unrealistic lamina flow tests. To ensure compliance, operating limits should be verified over the entire large range of target conditions and environments. Finally, NEBS compliance is usually a key requirement for carrier-grade systems. Systems integrators and blade suppliers have already completed significant testing of components as well as application-ready platforms. Designers can take advantage of this fact and plan accordingly.

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Applications AIS (SA Forum)

Other Middleware & Application Services

Service Availability Middleware

Operating System (CGL) Virtualization Hardware Platform Interface(HPI) (SA Forum)

Hardware Platform A

Hardware Platform B

Hardware Platform C

Hardware Platform D

Figure 3 Use of standard interfaces facilitates portable middleware and applications.

#3: Platform Independence and Portability

The next step is to ensure changes can be made down the road. Designing this flexibility into the system is important not only at the hardware layer, but at the middleware and application layers as well. A key advantage of using accepted industry

standards is that various functional layers can be abstracted from one another, making it possible to create and/or modify one layer without impacting others. The commercial acceptance of ATCA, CGL and service availability middleware based on the SA Forum open interfaces has enabled a system design where the hardware, the


8/11/09 2:29:04 PM RTC MAGAZINE AUGUST 2009

technology in context

operating system and the middleware can each be acquired from different suppliers. NEPs no longer have to be locked into a vertically integrated, proprietary architecture from a single vendor. Furthermore, since the layers are based on open standards, each can be replaced should the NEP decide to switch a particular supplier with another. A high level reference architecture enabled by the industry standards is depicted in Figure 3. While choosing a suitable hardware platform, the designer should consider if it offers the libraries specified by the Hardware Platform Interface (HPI) specification. This specification gives the designer the flexibility to design overlaying functional layers in a way that is platform-agnostic, preserving the ability to replace, change or add hardware platforms without having to modify other system components. Similarly, the SA Forum Application Interface Specification (AIS) offers a designer the ability to author applications that are abstracted from the underlying layers, making them portable across other platforms that are based on the AIS standard.

#4: Performance

Performance is the next key factor. In telecom devices, the performance requirements—especially failover times—depend on whether the processing is in management, control or user plane. In terms of high-availability (HA) requirements for a device at the edge of the network (e.g., a home router), there are no failover requirements since the significance of an outage is of little or no consequence. Only a single user (or an end-point) is affected and a simple reset resolves the issue. However, at the core of the network an outage affects many more users and has a much greater impact. As the functional density in a device or a system increases, the HA requirements can emerge where they did not exist before. For example, in an integrated security solution for telecom, significant HA requirements emerge when the various stand-alone devices that previously performed that function are consolidated into a large system. A cable TV universal edge device is another such example where the number of subscribers supported by one

of these devices increases to the point where the impact of an outage would affect a large number of customers. Allowable recovery times—specifically failover performance time—in general, are budgeted to best fit the needs of the appropriate level. Management plane recovery times (e.g., for SNMP) are relatively generous, often in seconds, since the device’s functional performance typically can continue even if management actions are not available. On the other hand, control plane recovery times (e.g., for signaling protocols), are more demanding and can range between seconds and milliseconds, since the device must pick up and connect and tear down incoming connection requests within strict timeframes. Even more demanding, user or data plane recovery times for real-time data, for example in the case of an in-phone call, must be extremely fast to ensure no perceivable interruption to the service. This requires failover times in the millisecond to microsecond range. Upfront allocation of failover time budgets during the design phase is critical to ensure desired HA performance of the deployed system.

#5: No Single Point of Failure

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The most critical requirement of a system expected to provide uninterrupted service is the elimination of all single points of failure (SPF). It is a fact that some hardware or software components will fail at some point in time. The designer must identify possible failures and ensure they aren’t realized. Redundancy is a popular scheme employed to achieve continuous service availability even in the presence of failures. Using a reference architecture can help a designer identify and address possible points of failure within a system. Consider a reference design created around an ATCA chassis, multiple operating systems and the SA Forum framework (Figure 4). The five-blade system provides redundancy including the following: • Redundant base and fabric backplane interfaces • Redundant platform support including power, cooling and shelf manager • Redundant HPI interface available to the service availability middleware • Redundant service availability middleware managers and client processes

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technology in context

System Mgmt Blade

System Mgmt Blade

General Processor

General Processor

Data Plane Blade



















Distributed MW Services


Redundant Applications

SA Middleware Cooling

Shelf Mgr




Redundant SA Forum HPI Heterogeneous OS & CPU architectures Redundant Backplane

Figure 4 Redundancy is the most important element of ensuring no single point of failure.

In this example, for each active component there is a standby that is ready to take over the processing on a redundant physical resource, should something happen to the active resource. A 1+1 redundancy model is employed for resources such as the management capabilities, HPI, operating systems

and various platform support resources. Both 1+1 and 2+1 redundancy models are applied to multiple applications.

#6. Upgradability

Last but not least, a design that considers upgradability ensures an op-

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erational system can be upgraded as new versions of software or hardware become available, without impact on service. The system designer must be clear about the properties that today’s code base must exhibit in order to successfully participate in an in-service upgrade in the future. For example, the designer must consider the impact of future potential changes in messaging, protocols, APIs, checkpoints of configuration data layouts, etc. The most common in-service upgrade is the rolling upgrade where all active processes migrate elsewhere as a node comes down, this node is upgraded with the new version of the software, and the node is rebooted and brought back into the system as the standby node. This process is repeated until all other nodes in the system are upgraded. Several key issues must be thought through in the design phase to ensure upgradability. First, it is important to determine the nature of the intended upgrade. Upgrading for functional improvements is relatively straightforward, whereas upgrading for structural changes can be challenging. Designing for upgradability means that the service must be maintained throughout the upgrade process. Most systems have one or more single points of failure that should be identified and addressed so that their impact is eliminated or minimized during an upgrade. Downgrade requirements must also be considered. Upgrades do go wrong, and the design must account for a plan to roll back to the previously known operational versions. Although the availability of COTS building blocks helps aid the designer of a highly available network element to get solutions to market more quickly, it also poses additional considerations that must be thought through during the design phases. GoAhead Software Bellevue, WA. (425) 453-1900. [].


© 2009 Pentair Electronic Packaging. All Rights Reserved.


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engineering Serial Interconnects Move to the Next Generations

PCI Express Gen 3: Twice as Nice— and Then Some System designers will soon be able to take advantage of the improved performance and robustness of PCIe Gen 3 technology with new Gen 3 switches that will help them overcome the challenges inherent in multigigabit system design. by Steve Moore, PLX Technology




80 70 PCIe Gen3 x8 - 64Gb/s

60 Bandwidth (Gb/s)

ith each successive generation of the industry standard PCI Express (PCIe) interconnect, the technology has been able to double its bandwidth, while at the same time adding features to improve system robustness. Designers now using PCIe Gen 1 and Gen 2 technology can look forward to another significant performance jump—to an incredibly fast eight gigabits per second (Gbits/s) per lane and 128 Gbit/s in designs using x16 port widths—along with a number of optimizations for enhanced signaling and data integrity, while maintaining full compatibility with the PCIe protocol stack and interoperability with components that support only the lower speed. As with PCIe Gen 2, the earliest adopters of Gen 3 technology will be in the graphics space, where there is an insatiable demand for speed. Additionally, we expect to see this type of bandwidth used in fabrics for high-performance compute platforms and RAID storage systems, video capture and broadcast distribution systems where the additional bandwidth will allow the interconnect to outpace the existing interconnect technologies (Figure 1). Additionally, the improvements in link integrity and equalization will extend the adoption of PCIe in cabling and backplanes, with significant opportunities for both reducing cost and power while increasing performance.

50 40

PCIe Gen2 x8 - 32Gb/s

40G Ethernet

30 20

PCIe Gen2 x4 - 16Gb/s


10G Ethernet




Figure 1 PCI Express bandwidth projections

PCIe Gen 3 Doubles Bandwidth

PCIe Gen 3 doubles the bandwidth of the interconnect without doubling the encoded bit rate. By comparison, the PCIe Gen 2 bit rate is 5 GigaTransitions per second (GT/s), and its 8b/10b encoding scheme provides an interconnect bandwidth of 4 Gbit/s per lane. A simple approach to doubling the PCIe interconnect bandwidth would have been to maintain the 8b/10b coding and then double the bit

rate to 10GT/s, providing Gen 3 with an 8 Gbit/s per lane interconnect bandwidth. However, after extensive analysis, the PCI SIG determined that the overhead associated with the 8b/10b code could be eliminated by using scrambling to obtain DC balance, together with a 128,130 encoding scheme. This results in a useful bandwidth per lane of 8Gbits/s, less ~1.5% due to coding, with an encoded bit rate of only 8 GT/s. This lower bit rate results in lower

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solutions engineering power consumption, less silicon area and better signal integrity than a standard that would require a full 10 GT/s rate. This of course translates into reduced cost and improved efficiency. Table 1 shows the migration of PCIe bandwidth performance from Gen 1 through Gen 3. What’s the trade-off? Since there’s no such thing as a free lunch, there must be some impact to the move from 8b/10b to a scrambling coding scheme. The 8b/10b encoding maps each byte of data into

one 10-bit character. While using 8b/10b encoding does increase the bit rate, the benefit is that it guarantees a deterministic DC wander. This allows for the ACcoupling of the physical lane signals, and thereby relaxes the requirements for data recovery, simplifying the receiver design of the PHY. The Gen 3 coding uses scrambling, rather than 8b/10b encoding. Scrambling is a technique by which a known polynomial is applied to the data stream in a

feedback topology. Since the polynomial is known, the data is recovered by applying the inverse polynomial. The drawback at the PHY layer is that DC wander can be introduced, requiring the receiver to either correct for DC wander or be able to tolerate the accompanying margin degradation associated with DC wander. There is also a drawback at the protocol layer: whereas the 8b/10b scheme provides out-of-band control characters that can identify the beginning and the end of a packet; with scrambling these characters do not exist. This will require additional circuitry in the transmitters and receivers, such as packet length counters, to delineate the beginning and ending of each packet. This additional circuitry has the potential to increase cost, power and complexity, but again, there’s no free lunch. Studies show that the trade-offs are worth it, since the reduced bit rate of the scrambling technique allows for the entire PHY to operate at a 20 percent lower frequency and still achieve the same link bandwidth.

PCIe Gen 3 New Features

In addition to providing twice the interconnect bandwidth, the PCI SIG is adding a handful of new transaction layer features to the Gen 3 standard. Transaction layer enhancements focus on two areas: host-intelligent device interactions to support the accelerator model (atomic operations, ID-based ordering, TLP processing hints) and means to better manage and reduce system power consumption (latency tolerance reporting, optimized buffer flush/fill, and dynamic power allocation). These transaction layer protocol options are also being released in PCIe 2.1 since their use doesn’t depend on operation at Gen 3 speeds. The physical layer interface (PHY) sections of the Gen 3 switches coming from PLX will include several enhancements aimed at improving signal integrity—particularly in long signal traces and the presence of discontinuities that arise from vias and other layout artifacts. Transmit pre-emphasis circuitry allows the transmitter to shift energy into the precursor or post-cursor portions of the signal without changing the overall power consumption of the PHY. A Finite Impulse Response (FIR) filter is employed in the transmitter to pre-distort the chan-


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solutions engineering nel to inversely match the channel loss. This allows for optimized signal integrity by matching the impulse response of the driver to the channel. A five-tap decision feedback equalizer (DFE) block is included in the receiver section. While other filter topologies tend to amplify the channel noise, the five-tap DFE operates by, in effect, canceling inter-symbol interference and reflections. The DFE is especially well suited to overcoming the effect of discrete discontinuities in the channel, such as sharp directional changes found in vias and backplanes. The DFE section can be switched into a pass-through mode for reduced power consumption. The receiver section also features a continuous time linear equalizer (CTLE). A CTLE is effective at optimizing the receiver for long continuous channels, as encountered when driving cables. Auto-calibration routines are used both to compensate for PVT changes in analog circuit parameters and to adapt equalizer settings. This allows the system design to use longer trace lengths on the circuit board, providing layout flexibility, and enhancing system robustness. Additionally, an advanced receiver detection section is included that prevents the linkdown that is often observed in long (lossy) links due to low amplitude Advanced debug and test features include jitter injection for system margining, and automatic eye-diagram generation. These permit signal integrity testing without use of external test equipment. The Gen 3 PHY can measure both eye height and width, an improvement over Gen 2 Serdes, which could measure only eye width. Additional enhancements and features are likely to be added as the specification is developed, but not necessarily tied to Gen 3 deployment.

Gen 3 Interconnect Targets Graphics Cards

Graphical displays continue to increase in resolution and complexity. This has continued to drive up the bandwidth requirements for the I/O interconnect for graphic cards, and has also driven up the demands for GPU power. With twice the bandwidth of Gen 2, Gen 3 allows for clearer images and more realistic motion, as Gen 3 bandwidth allows the time required to paint an image at a given reso-

PCIe Architecture

Signaling Rate (GT/s)

BW (Gb/s) per Lane X16 Link minus encoding Bandwidth (Gb/s) overhead

Gen 1




Gen 2




Gen 3




TABLE 1 PCIe Bandwidth Migration. CPU

Root Complex

Graphics Card

PEX 8748 48-Lane Gen3 Switch

X16 Gen3 PCIe

X16 Gen3 PCIe GPU1



Figure 2 Multicast supports dual-GPU graphics.

lution to be cut in half. Additionally, the PCIe multi-cast (MC) feature is very well suited to enhance the performance of multi-GPU systems. As Figure 2 shows, two GPUs are used to paint a single screen. Because graphics processing has a predefined set of steps running in parallel and in processing order, the CPU can simultaneously cast drawing commands to both GPUs for processing using a PCIe Gen 3 switch with multicast-enabled. Each GPU then renders its specified portion of the screen. As shown in Figure 2, GPU2 then transfers its image to GPU1 via the peer-to-peer communication feature already built into the PCIe switch. GPU1 updates the screen with both images, providing more realistic, high-bandwidth video. Using MC reduces CPU utilization, providing more cycles for general-purpose processing of other activities. Gen 3 technology will also be utilized in the high-performance world of video capture and broadcast distribution. The next-generation video processors will

require I/O interconnects that consume less power and provide higher bandwidth. Current video capture systems use PCI and PCIe Gen1 I/O for the connection of the video codecs into the CPU. As the demand for higher resolution and higher video channel aggregation continues, the bandwidth of PCI and Gen1 PCIe links has become insufficient. Deploying PCIe Gen 3 links will allow immediate relief in the I/O congestion caused by these high-speed streams. PCIe Gen 3 is on the horizon, and like the previous transitions in the PCIe standard, will bring doubled bandwidth along with significantly enhanced features. This will make the PCIe interconnect an even more compelling solution for high-speed graphics, in addition to all other application markets that thrive on speed and demand reduced power and cost. PLX Technology Sunnyvale, CA. (408) 774-9060. [].



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engineering Serial Interconnects Move to the Next Generations

Serial RapidIO 2.0 Moves into the Wireless Infrastructure The rapid growth of mobile wireless users—and their incessant demand for more and greater applications—continues to put bandwidth per user and overall processing capacity within the wireless infrastructure at a premium. This, in turn, has a dramatic impact on interconnect performance between processing elements in the base station. by Stephen M. Nolan and Devashish Paul, IDT


he wireless industry continues to look to Serial RapidIO to address the needs of mobile users and increase the quality of service. The latest version, Serial RapidIO 2.0, addresses all of these needs and maintains backward compatibility with the previous versions of the specification—helping the installed infrastructure base to be easily upgraded for the addition of new subscriber services. Clusters of processors—be they digital signal processors (DSPs), field programmable gate arrays (FPGAs) or applicationspecific integrated circuits (ASICs)—process large amounts of data within wireless infrastructure equipment such as cellular base stations. Moving the large volume of data to, from and in between these processors is no small challenge given the constraints of real-time applications, such as voice and video. Entire traffic flows must be received, processed and transmitted in microseconds. This means the end-to-end latency between switching elements needs to occur in the sub-200-nanosecond range. The required bandwidth in the wireless infrastructure continues to multiply as mobile traffic increases and as subscribers



demand more bandwidth-intensive services on their handsets, such as video on demand. Moreover, in dense urban environments, there is a desire to support the maximum number of subscribers off one base station by adding advanced 4G modulation schemes, for example Orthogonal Frequency Division Multiple Access (OFDMA) PHY processing, supporting more antennae per base station and more processing cards per chassis. With the increasing subscriber service needs of 4G and subscriber density, there is a need to distribute the processing over multiple processors and over multiple boards and chassis. Wireless base stations can be best viewed as a peer-to-peer network of processing elements doing a pipeline of tasks replicated multiple times over numerous subscribers. Given that wireless base stations are implemented with a peer-to-peer network of processing elements, it is important to introduce how RapidIO enables this topology with a simplified approach vs. PCI Express (PCIe)-based options. In PCIe, there is the complex of a host processor. Other processing elements are part of this root complex-based network. In complex mul-

tiprocessor systems, the address spaces of multiple roots need to be separated by non-transparent bridges, which can be embedded in PCIe switches, but is nevertheless complex to manage in wireless base stations. RapidIO has been universally accepted for this application because it does not use a root complex-based architecture and supports true peer-to-peer networking. It is based on simple lookup tables with packets forwarded to destination IDs (Figure 1). RapidIO supports messaging, with the receiver deciding what to do with it once it receives it, managing its own memory system, as shown in Figure 2. The history of RapidIO goes back to 1997 when work began to create a standardized interface that could be implemented on processors and peripherals. In 1999, an open standard, RapidIO, was published that addressed the needs of reliability, increased bandwidth, low latency and other key needs in intrasystem interconnect. The specification gained rapid and widespread acceptance. The RapidIO Trade Association (RTA) was formed in 2000 and continues to provide updated standards that address the needs of the industry.

solutions engineering

and microprocessor providers for DSP clusters in cellular base stations, backplanes, military, imaging and industrial control applications. Due to the interoperability ensured by the standard, a robust ecosystem of devices, software and development tools is based on Serial RapidIO. Because of the multiplicity of Serial RapidIO endpoint devices available, the need for bridging to other interconnects is minimized. Today, Serial RapidIO is the key data plane interconnect in 3.5 and 4G base stations. Virtually all new base station designs are incorporating Serial RapidIO architectures. The typical base station architecture partitions the baseband processing onto one or multiple baseband cards. These cards utilize multiple DSPs and possibly

Migration to Serial

The migration to 2G and 3G cellular base station architectures, along with the expected services, required even larger clusters of processors in base station architectures. The original RapidIO interface, however, was a parallel architecture and did not easily support the required numbers of DSPs. Because of the number of interconnects required, the limitations of board space for traces and chip pin-count restrictions, migration to a serial interface was necessary. The Serial RapidIO standard version 1.2 was released in 2002 and subsequently upgraded to version 1.3 in 2005. This has become the embedded interconnect of choice, adopted by major DSP, FPGA, switch-fabric Host Subsystem

I/O Subsystem






RapidIO Switch


Serial Switch






To Switch Fabric


DSP Farm

Comms Subsystem

• Routing is easy: Target ID based • Every endpoint has a separate memory system















8 or 16

8 or 16



Target Address

Source Address





32 or 48 or 64



Source TID

Device Offset Address

8 to 256 Bytes


Optional Data Payload




Next Packet


Figure 1 RapidIO featuring target ID-based routing in a peer-to-peer network.



other elements, such as control plane microprocessors, “Chip Rate ASICs” and FPGAs on a single board. A Serial RapidIO switch device acts as the switch fabric and aggregation point on the card. Integrated Device Technology (IDT) even offers a pre-processing switch (PPS) family of devices that, in addition to standard switching functions, can offload some of the simple data pre-processing activities of the DSP, ASIC or FPGA to allow those devices to function more efficiently. If multiple baseband cards are used in a system, typically, they are interconnected across a backplane using Serial RapidIO to a control/switch card that would also use RapidIO devices. A standard implementation of a base station architecture uses the Common Public Radio Interface (CPRI) serial interface for the link between the baseband cards and the radio cards. IDT also offers a stand-alone Fabric Inter-Connect (FIC) device that bridges from the Serial RapidIO interface on the baseband card to a CPRI interface. Another FIC bridges from the CPRI interface to the TDM interface on the RF card side (Figure 3). The Serial RapidIO 1.3 standard has many attributes that make it optimal for chip-to-chip communication in wireless infrastructure applications. It is a reliable, low-latency transport that supports 1x and 4x lane configurations per port at 1.25 Gbit/s, 2.5 Gbit/s and 3.125 Gbit/s lane rates, allowing up to 10 Gbit/s on a single 4x port. Combinations of 1x and 4x lane ports at different lane rates vary widely, depending on the system targets for bandwidth and user capacity for any given base station architecture. The Serial RapidIO 1.3 standard requires lower header overhead than similar serial data communication standards, such as Ethernet and PCI Express. RapidIO switches offer lower power per payload gigabit than PCIe because less power is effectively consumed by the smaller percentage of header bits, before getting to user data contained in the payload. Serial RapidIO also allows processorto-processor communication (peer to peer) without a root complex, which is a key to the architectural topology of wireless baseband systems with multiple distributed processors. There is no need to manage a complex memory map over multiple

solutions engineering

processing elements, making processing much more efficient than a corresponding PCIe solution.

Next-Generation—Serial RapidIO 2.0

During the past few years, Internet traffic has shown tremendous, rapid growth in mobile access markets. The recent increased demand for 3G smart phones and wireless-enabled PDA-type devices will continue to drive the increase of mobile data traffic in the enterprise market space. On the general consumer side, the biggest driver for increased data traffic for the foreseeable future will be uploads and downloads of photos and video for watching and sharing. Resulting user demand for faster access and shorter download times—while looking for a richer multimedia experience—will encourage service providers to add higher capacity 3.5G and 4G base stations to their existing wireless infrastructure mix, be they WiMAX or 3G LTE. In 3.5G and 4G base station architectures, increasing data rate capability and the push for a higher capacity of users per base station led to increasing backplane speeds between radio and baseband cards. This overall bandwidth increase, in turn, requires more multicore DSPs interconnected in a standard cluster configuration on the baseband card. The multicore DSPs now offer architectures with three to six cores, each operating in the Gigahertz range. Moving forward, the industry migration to 45nm and lower fabrication processes will allow even higher operating frequencies and possibly the incorporation of more processing cores on-chip. Despite all of the benefits that Serial RapidIO 1.3 brings to wireless applications, continued demands for greater bandwidth motivated the RapidIO Trade Association to publish the Serial RapidIO 2.0 standard in 2007. All leading wireless infrastructure equipment providers are adopting this technology in their nextgeneration platform designs to increase overall system performance, support more subscribers per base station with more revenue-generating real-time multimedia features. But Serial RapidIO 2.0 is not limited to the rollout of new platforms or upgrades of base stations to 4G standards.

In some cases, Serial RapidIO 2.0 is ideal for cost reduction and power-saving measures in legacy platform updates. Why? Simply because Serial RapidIO 2.0 can support more bandwidth per serial link, doubling the baud rate on a link from 3.125 Gbaud in Serial RapidIO 1.3 to 6.25 Gbaud in Serial RapidIO 2.0. Moreover, it can be transmitted up to 100 cm over two connectors, making it ideal for cascading multiple chassis, co-located in one physi-

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cal rack, immediately expanding the processing capacity of a base station. Two of the key benefits that Serial RapidIO 2.0 provides over its predecessor are bandwidth and port flexibility, while still maintaining backward compatibility with the Serial RapidIO 1.3 standard. The addition of 2x lane per-port configurations allows the same port rates as Serial RapidIO 1.3, with half the lane count for easy trace routing and increased trace utilization.


8/11/09 3:58:38 PM RTC MAGAZINE AUGUST 2009

solutions engineering

RapidIO Endpoint Local Memory Queue 0

Outbound Message Transmitter

Queue 1

send traffic to uncongested destinations. This feature enables distributed decision making, ensuring that available switching bandwidth is optimally used. The latency of decision making is low, as congestion information is exchanged using control symbols that are embedded within Serial RapidIO packets. There are also improvements to Quality of Service (QoS) that will appeal to carrier-grade communications applications. Within the physical layer, the new standard additions receive equalization capabilities that will allow it to support extended longreach (100 cm) traces at the full data rate. This can even be done with conventional FR4-based PC board materials. The continuous advances in the wireless infrastructure to meet the growing demands of mobile users create the need for significant increases in system compute capability and bandwidth. The industry has responded with the evolution of its most successful interface standard to meet the needs for more bandwidth, more flexibility and better quality of service. The Serial RapidIO 2.0 standard addresses all of these needs and maintains backward compatibility with the previous versions of the specification—helping to keep the installed infrastructure base from becoming obsolete. The device provider community is developing devices to support the new interface, including DSPs, CPUs, FPGAs and switch fabrics.

RapidIO Endpoint Local Memory RapidIO

Inbound Message Receiver

Queue 0 Queue 1

Queue 2

Queue 2

Queue 3

Queue 3

• Messaging uses a push architecture • Receiver is respnsible for storing the message in its memory system • Overall system latency per message transfer is reduced significantly

Figure 2 RapidIO endpoints manage their own memory system.

video can be allocated a larger bandwidth and a higher priority, and be transmitted on one VC while traffic that is less sensitive to real-time constraints might be transmitted on other channels on the same physical link. This is well summarized by the RapidIO Trade Association, which describes it as follows:

Serial RapidIO 2.0 also adds support for Virtual Channels (VCs) and Virtual Output Queuing (VOQs), improving overall traffic management and allowing more efficient use of the switch fabric. The concept of VCs is to take one physical “pipe” and subdivide this into multiple smaller pipes. For example, take a busy highway, such as Highway 101 through Silicon Valley. This highway has the capacity to support a large number of cars (packets) travelling at 60 miles per hour. One can consider the entire highway as a single pipe, or we can introduce the concept of multiple pipes that make up the highway. For example, a commuter lane can be considered as one of the smaller pipes supporting cars (packets) of a given priority. While this is a physical division, in a Serial RapidIO link, it is managed logically. Packets of different priorities are transmitted on different VCs, and each VC can be allocated a certain amount of bandwidth of the actual physical link. What this means is that, using the commuter lane analogy, latency-sensitive

“The last piece of the performance engineering story for RapidIO Specification 2.0 is the virtual channel. Virtual channels (VCs) provide the ability to aggregate traffic flows with similar characteristics, while segregating them from flows with different characteristics, and guaranteeing bandwidth to each flow. The comprehensive flow control mechanisms in RapidIO Specification 2.0 can be used to ensure that the traffic in each virtual channel meets its quality of service (QoS) requirements, without interfering with any other traffic type.”

The Serial RapidIO 2.0 virtual output queue-based backpressure mechanism allows switches and endpoints to learn which destinations are congested, and to DSP


RF Downconverter RF SAW





Sample base station architecture.





sRIO Switch PPS or CPS


Figure 3




Serial Buffer



RF Upconverter


Modulator Timing Interface

SAW Duplexer


Integrated Device Technology San Jose, CA. (408) 284-8200. [].

ully eautif and b e h t t Stay aated Riviera000! renov ould win $1 you c

October 26-29, 2009

Riviera Hotel & Convent ion Center | L a s Veg a s , N V | U S A

> Short courses on telemetry topics and technical sessions on the latest solutions and technologies > Exhibits from over 100 of the industry’s traditional and newest suppliers > Keynote speaker and panel discussions > Special events and drawings

You are invited to attend the 45th International Telemetering Conference in Las Vegas, NV. This year’s program is focused on disruptive technologies, or disruptive innovations, and their impact on telemetry. A few examples of past disruptive technologies would include digital media, digital synthesizers, light-emitting diodes, and voice over mobile IP. The opening session features a Blue Ribbon Panel presentation/discussion on disruptive technologies in the functional areas of Science and Technology, Research and Development, and Test and Evaluation. The panel will be moderated by the Honorable Dr. Charles E. McQueary, former Director of Operational Test and Evaluation, Office of the Secretary of Defense. Panel members’ backgrounds include expertise in Department of Defense (DoD) and Department of Homeland Security (DHS) technology developments, weapon systems testing and executive leadership.


insight Mobile Robots

Mobile Robotics: Moving Robots Forward Mobile robots require a number of different subsystems for sensing, making decisions and acting that must all work in concert. Some of these computational tasks must also meet real-time requirements. by Meghan Meckstroth, National Instruments


obile robotics is one of the fastest growing fields of engineering. By 2015, the Department of Defense has mandated that one third of all military vehicles must be autonomous. The International Federation of Robotics predicts that by 2011, over 12 million service robots will be sold for personal use. Cutting-edge sensor technologies such as high-definition LIDAR and stereo vision, in addition to the evolution of robotics architectures and development tools, are allowing these complex devices to become increasingly common. Mobile robots are most commonly found performing tasks that are dull, dirty or dangerous. The U.S. military uses robotic systems for dangerous tasks, such as walking through minefields, deactivating bombs or clearing out hostile buildings. Farmers use mobile robots to perform dirty tasks, including harvesting, collecting crop data, weeding and micro spraying. Hospitals use mobile robots to deliver specimens to laboratories and for assistive care. Mobile robots are even used to perform routine chores around the house, such as vacuuming and cleaning pools and gutters. Almost every type of mobile robot operates in a different environment, has different behavior, and connects to different sensors and actuators. Therefore, they are



often developed on different hardware platforms with different software development tools. Consequently, when an engineer develops a proven control system for one robot, it is difficult to transfer it to another robot because the APIs for sensing, steering and motor control are different in syntax and semantics on different robot hardware. When designing, prototyping and deploying mobile robotics applications, the following aspects of development can be a challenge: • Combining deterministic control and high level intelligence • Integration with sensors and actuators • Translating high-level algorithms to embedded hardware • Displaying a custom user interface with large amounts of data • Utilizing multicore hardware By understanding basic components of mobile robot control systems and investing in a robotics development platform that addresses common challenges, engineers and scientists can quickly move forward with the development of their mobile robots.

Embedded Control Systems

Mobile robots come in many shapes and sizes, and although there isn’t really any single definition of a mobile robot, they

all contain three main components. First, there is some combination of sensors that are used for understanding the environment. Then, of course, there is the onboard computer for planning and decision making. Finally, for it to be a mobile robot there must be some form of locomotion allowing the robot to act on its environment. The centerpiece of every robotic control system is an onboard controller. The controller makes decisions based on the available sensor data and sends instructions to its motors to control the robot’s movement. Robotic control systems require the following subsystems: An interface to I/O - Robotic control systems have to communicate with a wide variety of sensors and actuators. Key sensors such as LIDAR and GPS commonly use a USB or serial interface, while motors might require a digital port or CAN interface. Low-level control - PID loops or state-space equations are implemented to perform processing based on sensor feedback. For example, a PID loop is used to process the encoder feedback and navigate the robot in a straight line. This type of control requires deterministic response and tight integration with I/O. Autonomous navigation system - A mobile robot has subsystems for percep-

industry insight tion and planning. Once a robot perceives, or understands its sensor data, the data is passed to a higher-level planning module. The planning module can be broken down even further; low-level planning, such as stopping when an obstacle is present, or high-level planning, such as making decisions regarding the mission of the robot. User interface - User interfaces are often used to display information regarding a robot’s health, such as power consumption levels, and a notification of hardware failures. This includes both remote and local APIs. Finding an embedded hardware platform that combines the deterministic control and the high-level intelligence required for mobile robotic applications can be challenging. Microprocessors are often considered due to their low cost and small form factor. A processor is ideal for running a user interface and autonomous navigation system, but using a processor to control hardware interfaces and signalprocessing systems while executing the higher-level tasks, can be computationally intensive. Field Programmable Gate Arrays (FPGAs) are ideal for controlling hardware interfaces and signal processing. However, high-level tasks such as navigation can be very complicated to implement on an FPGA. An ideal embedded solution for a mobile robot control system is a pairing of an FPGA and a processor, with communication to a remote HMI for displaying data to a user. This architecture enables robot designers to implement the hardware interfaces and signal processing in logic, and frees up the processor to handle high-level tasks such as navigation. This architecture also allows time-critical control algorithms to be completely implemented in hardware using the FPGA. Figure 1 shows an example of how robot architecture could be implemented on an embedded system with an integrated FPGA and processor. An example of a complex robotic control system requiring both high-level modules for complex algorithms and low-level control is Alliance Spacesystems’s Aerospace Robotics Testbed (ART). Alliance Spacesystems has been providing solutions for robotics, mechatronics and embedded systems for the past 12 years. ART is used for prototyping robotic arms that will be used on future planetary rovers.

The biggest challenge that Alliance Spacesystems faced during development was finding a system that allowed them to analyze the robotic arm system (including hardware and controller), visualize the arm motion within the workspace, compute the inverse kinematics and dynamics, and at the same time provide an in-

tuitive user interface and deal with a large amount of telemetry from the arm. It also required the ability to rapidly prototype a system with numerous, custom interfaces. Because it was such a customized system, Alliance Spacesystems initially had several processors and various boards to accomplish each task. It was very much a sys-

THINK Real-Time Module Planning Path Planner, Behaviors, Motion Planner

SENSE AND ACT Sensors LIDAR, Camera, Range Finder Actuators Motors, Relays

Perception Object Classification, Localization

User Interface Health Monitor, Optional Control


FPGA Module Safety, Filtering, PID Motion Control I/O

Figure 1 A possible software architecture when developing robotics applications on NI embedded platform.

Figure 2 Alliance Spacesystems used an integrated real-time processor and FPGA for their Aerospace Robotics Testbed (ART).



industry insight

Figure 3 Nicholas is an autonomous mobile robot that navigates an environment using an embedded NI Single-Board RIO and NI LabView.

tems engineering problem and became very challenging to support all the different interfaces and features. ART required hardware that was capable of executing high-level inverse kinematics algorithms, and low-level control algorithms for the robotic arms. Alliance Spacesystems moved to an NI Compact RIO, which uses a RIO (reconfigurable I/O) architecture consisting of an integrated embedded real-time processer and FPGA. The FPGA was used for the low-level control algorithms for the robotics arms, and the embedded processor was used for the inverse kinematics. Alliance Spacesystems expanded their platform by plugging in several I/O modules including a CAN card to interface to the intelligent motor controller, an RS-232 interface, and SD memory module for storing data (Figure 2). In addition to off-loading low-level control to an FPGA, mobile robots also require multiple tasks to execute in parallel on a single processor. Tasks such as perception and planning vary in complexity, priority and


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11/10/08 10:01:37 AM

computation time. It can be challenging to execute all of these tasks while still achieving high performance and deterministic response. Multicore embedded devices can significantly improve system performance by managing tasks such as perception and planning on multiple cores. Additional cores provide expanded resources for real-time processing of more complex algorithms. For critical applications, multicore embedded processers can enable the user to reserve an entire core for a high-priority task.

Software Development Tools

Software developers have to bridge a difficult gap between the design of algorithms for use in a robot and the actual implementation in hardware. The expanding use-cases for modern robots require increasingly complex algorithms that have highly responsive control for tasks like navigation and localization. Many designers use high-level mathematical software for testing and modeling algorithms before migrating to embedded

industry insight C and assembly programming for low-cost, low profile hardware. This poses a significant challenge as these environments often have different programming syntaxes and often do not provide access to the same analysis and mathematics libraries. This means that control algorithms often have to be re-implemented and re-tested using the embedded hardware. The task of prototyping robots is expedited if designers have access to real-world data, such as sensor input, as well as the ability to control actuators such as motors. This is made possible by high-level languages that abstract the communication with hardware and provide access to the same analysis and mathematics libraries on the desktop, as well as an embedded target. Tool chains that are ideal for robotics provide the ability to migrate code that was developed using modeling and simulation to an actual realtime environment or an FPGA. An example of a software development platform that abstracts the communication with embedded hardware is NI LabView. NI LabView is a high-level graphical programming and textual language that can enable domain experts to rapidly design and develop complex robots. NI LabView is easily deployed to embedded targets ranging from integrated real-time processor and FPGA solutions, to custom 32-bit microcontrollers. NI LabView has been used in a variety of robotic applications, including Victor Tango, Virginia Tech’s autonomous vehicle that placed third in the DARPA Urban challenge, and the VECNA Bear, a robot used for battle extraction and retrieval. A simpler application, for the sake of example, is Nicholas, shown in Figure 3. Nicholas is a demonstration platform that navigates an environment while avoiding obstacles. This small-scale unmanned ground vehicle uses an NI Single-Board RIO as the control system, and a Hokuyo LIDAR sensor for visualization. The motor control is being executed on the built-in FPGA using pulsewidth modulation (PWM), and the obstacle avoidance algorithm is being executed on the deterministic real-time processor. The Hokuyo LIDAR driver, which can be downloaded from, plugged into the existing application without requiring additional modifications. By forming partnerships with leading vendors such as Hokuyo, Velodyne, Garmin, Lynxmotion

and Maxon Motors, National Instruments is working toward the development of an integrated, open robotics development platform. This allows robotics engineers to spend less time re-implementing an interface to external hardware so they can focus on the high-level mission. Mobile robots are complex systems that are used in many different applications and industries. These devices utilize advanced control systems that require deterministic control, high-level intelligence

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and tight integration with I/O. In addition, increasingly complex algorithms for tasks such as navigation require high-level tools and reusable code. Robotics engineers can decrease development time by investing in an open platform and understanding basic mobile robot architectures. National Instruments Austin, TX. (512) 794-0100. [].


8/19/09 4:48:41 PM RTC MAGAZINE AUGUST 2009

exploration r your goal eak directly page, the resource. hnology, nd products

System Integration Industrial Networks

802.11n Wireless Connectivity Supports Seamless Industrial Networks The 802.11 WLAN standard, and in particular 802.11n, helps provide seamless connectivity and a means of achieving universal IP-based networking in industrial environments.

service at rigidly periodic intervals, demanding a transport mechanism that provides guaranteed timely delivery of information. Other devices may communicate in bursts, sending out unsolicited data at irregular intervals, and without needing a deterministic latency bound. Some devices may communicate to a multitude of other devices on the network, while others may only communicate with one other. These requirements translate to specifications on the physical layer, data link layer, network layer and the application layer, usually skipping the other layers in between. Figure 1 illustrates this diversity. The physical layer in these connections could be RS-232, RS-485, Ethernet or Wireless, among others. Popular protocols include Fieldbus variants, Controller Area Networks or CAN, ModBus and DeviceNet, among a host of others.

IP – the solution for LAN as well as WAN

by N.Venkatesh, Redpine Signals

panies providing solutions now

ation into products, technologies and companies. Whether your goal is to research the latest cation Engineer, or jump to a company's technicalhave page,long the goal of Get Connected is to put you ndustrial environments been extensively networked. ce you require for whatever type of technology, The objective has primarily been automation—the need to es and products you are searching for.


control and monitor complex manufacturing processes that bring together machines, actuators, controllers, data acquisition systems, supervisory systems and communication infrastructure, among others. These individual entities communicate among themselves, following somewhat rigid hierarchies of communication links. Networks have traditionally been designed through a layered approach, with the ISO seven-layer protocol being a well-known and standardized hierarchy, albeit rarely followed in toto. Various segments of an industrial network use their own methods of communicating, often resulting in a complex structure of data links. There are almost as many types of networks as there are applicationsGet thatConnected use them. The attributes of the network are split with companies mentioned in this article. into the attributes of each of the layers that comprise them—and they derive from the requirements of the application under consideration. For example, some devices on a network may require

End of Article

Get Connected with companies mentioned in this article.



If there is one network type that can be called near-universal, it is the IP-based network. From within a home or an office to the whole world via the Internet, the TCP/IP protocol suite is omnipresent. The connectionless, packet-switched transport mechanism it provides is ideal for exchange of data; and it also helps that computing platforms everywhere have shed their diversity and adopted one of a few common architectures. Commonality helps reduce cost, and reduced cost in turn enables faster adoption of a technology—but apart from this, the TCP/IP suite also provides for the robustness required by industrial networks. The use of IP by itself does not make a network universal, for there can still be differences in the physical link and the applications that make use of the transport layer. The RS-232 serial link can carry IP packets, and so can Ethernet and optical links, among others (Figure 2). The focus here is on the use of a common wireless link in these networks.

The Wireless Network

While networks may still be universally connected without having a common physical layer, there is sound motivation for using wireless as a standard physical medium in industrial or enterprise environments. The number of devices that are connected is increasing rapidly—in fact, there is today an explosion in the deployment of “connected” devices in a whole variety of environments, giving rise to the term “M2M” or machine-tomachine communication, where a plethora of equipment, sensors, actuators, monitors and other devices are connected to

system integration

each other—something like an Internet of things. The merging of sensors—by definition small, inexpensive, easily deployable and with miniscule energy consumption—into the industrial network has accelerated the adoption of wireless transport mechanisms. In planning to connect a large number of devices within the premises of an organization, it is evident that extensive cabling would have to be introduced. Routing increasing numbers of cables is expensive and difficult—and the setting up of a new production line or reorganization of a laboratory would see considerable time and resources spent in the installation of cables. In many cases, the cost of the cabling can equal or exceed the cost of the device being networked, and may even prove to be a deterrent to increased automation in the enterprise. The nature of the devices themselves may dictate the use of wireless as the connecting medium. For example, wireless sensor networks require a few important features to be successfully deployed, and these include the ability to be deployed flexibly in large numbers, work in a “mesh,” offer a long battery life, and the ability to transport data in a standard format. These requirements are met only with a wireless transport mechanism, as illustrated in Figure 3.

DeviceNet Profibus CAN

ControlNet Modbus Diagnostics and Profinet Controllers/ Supervisory PLC Systems

The Internet


Sensors and Actuators


Figure 1 Communication between various entities of an industrial environment is often via disparate protocols, each handling a segment of the overall network, and resulting in an obfuscation of the network itself. Diagnostics and Supervisory Systems


The Advantages of WLAN

Three of the most popular wireless standards in this area are the IEEE 802.15.4 “‘ZigBee,” Bluetooth and IEEE 802.11 Wireless LAN (or WLAN). The focus today is increasingly on WLAN due to its many distinct advantages. The IEEE 802.11 family of wireless LAN standards was created as descriptions of a system that would be an equivalent of the wired Ethernet infrastructure. Data throughputs, however, were originally very low—1 Mbit/s to start with—but over the years the standard has been evolving to eventually include, as of early 2009, data rates up to 600 Mbits/s. The 802.11n addition to the standard (presently still in draft form) was proposed as a means of bringing in high user level throughput to WLANs—and therefore has addressed both the PHY and the MAC layers. Apart from addressing high throughput, the WLAN standard has also evolved to support a variety of applications with different needs— ,for instance those that require high reliability and timeliness of data transfer, and those that require mobility and roaming. At the physical layer, 802.11 defines operation in both 2.4 and 5 GHz bands. The 802.11b standard specifies digital sequence spread spectrum (DSSS) and complementary code keying (CCK) modulation schemes with data rates up to 11 Mbits/s. 802.11a, 11g and 11n specify the Orthogonal Frequency Division Modulation (OFDM) modulation scheme along with error correction coding, which has since become the dominant modulation method for high-speed wireless data transport. OFDM is inherently multipath tolerant and provides for relatively simple and inexpensive implementations. At the MAC layer, 802.11 addresses medium-sharing through a CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) mechanism. Collisions can and do occur, and

AS-i Zigbee Profibus

Ethernet - TCP/IP






Controllers/ PLC

Sensors and Actuators

The Internet

Figure 2 The Industrial Network based on IP transport protocol. Note that the physical links may still be different.

cannot be detected as such. A transmitter deduces that a collision has occurred or a packet has not reached the receiver without error by noting the absence of a return acknowledgement. Before attempting to transmit again, the source node would wait for a random back-off interval (Figure 4). This mechanism does not totally eliminate the possibility of lost packets, since the transmitter would only attempt a finite number of retries before abandoning the packet. However, under good link conditions, the probability of lost packets can be very small. The random backoff mechanism creates another problem: packet transfer latency cannot be guaranteed. This affects time-sensitive traffic like control packets for critical process control and voice calls. The IEEE 802.11e standard addresses this issue and provides for prioritizing certain categories of traffic over others. One of the main reasons why 802.11 finds itself as the wireless of choice in emerging networks is its ability to scale up and RTC MAGAZINE AUGUST 2009


system integration


settings, and this greatly eases the deployment of WLAN-enabled equipment and sensors in those environments. The planning of the network—involving decisions on frequency reuse, coverage of cells and security settings among others—would have been done, paving the way for quick and flexible installation and commissioning of equipment and devices. This is a second significant reason behind the adoption of 802.11 as the choice of wireless technology in industrial networks.

Layer-3 Processor



802.11n Controller or Coordinator Sensor Node

Figure 3 A Wireless Sensor Network shown connected in a mesh formation, with the inset showing constituents of a wireless sensor node Contention Preamble Header



Data MAC Header




Preamble Header Data Data Tx Opportunity Prioritized based on QoS Class


Figure 4 802.11 frames are acknowledged by the receiver, following which the medium is thrown open for further traffic. While contending for the medium, devices use a random back-off count with a provision for varying priority based on the QoS class of the data to be transmitted.

cater to increasing densities in wireless node deployment. The commonly used 802.11g defines “on-air” data rates of up to 54 Mbits/s. It can therefore cater to dozens of nodes each communicating at a few tens or hundreds of Kbits/s, as is common in industrial scenarios. At the same time, a wireless node that has only a limited quantity of data to send at infrequent intervals can put itself into an 802.11 power-save or sleep mode and achieve significant savings in battery drain. However, it must be noted that transmitting small packets is wasteful of bandwidth, since the 802.11 overhead is constant. WLAN nodes can connect to each other in a standards-defined ad hoc mode, but more commonly, the network would be configured in an infrastructure mode, with all data transfers being routed through an access point (AP). Now, APs are routinely deployed for handling data traffic in most enterprise and factory



The IEEE 802.11n standard primarily provides for high throughput, high efficiency and long-range data connectivity, and includes the use of multiple antennas and transmit-receive chains. Higher throughput is achieved through both PHY and MAC level enhancements. At the PHY level, the standard enables the use of 52 OFDM subcarriers for the carriage of data in every symbol, against the 48 that were used according to 802.11g or 802.11a. A new coding rate of 5/6 is also defined, up ¾ from the rate in the previous versions. The Guard Interval—the period of silence between two symbols—is also halved from 0.8 us to 0.4 us. A symbol is 3.2 us in duration, excluding the guard interval. Occupied bandwidth is increased from 20 MHz to 40 MHz, doubling data rates, with the caveat that the 40 MHz bandwidth mode be used only when an adjacent band is free of traffic. The revolutionary concept of MIMO, or multiple-input multiple-output, is introduced, which makes use of multiple antennas at the transmitter and at the receiver to enable the separation of two or more streams of data sent on the same channel at the same time. At the MAC level, the 802.11n standard improves efficiency by defining modes where longer packets can be transmitted with a single set of header bytes, or where a return acknowledgement packet contains reception information on a burst of packets previously sent. It also defines other methods like reduced inter-frame spacing (RIFS). The 802.11n standard primarily addresses the needs of hightraffic nodes, but it also includes a single-stream mode that is intended to provide the benefits of 11n to low-power small form factor devices including sensor nodes. The use of single-stream 802.11n WLAN in these client devices provides the following benefits, while retaining the size, cost and power consumption benefits of legacy devices: • Higher throughput and lower transmit times—achieved through better efficiency in PHY and MAC. • Longer range—through use of multiple antennas at the access point. • Preservation of 802.11n network capacity—the presence of legacy 802.11a/b/g clients forces the 11n nodes to use protection mechanisms and results in overall drop in network capacity. 802.11n helps avoid this.

The Integrated Industrial Network

Devices based on the 802.11 or 802.11n standard can be engineered to provide for the requirements of industrial networks (Figure 5). WLAN devices can offer the wireless replacement of a serial cable, or construct a flexible and configurable sensor network, or help integrate every piece of equipment into the

system integration

Enterprise LAN Portable Analyzer


Process Monitor

Wi-Fi RTLS Tag


RS-232 Serial-to-wi-fi Device Server

Wireless Access Point

Sensor Node with WLAN


3U CompactPCI Showcase Featuring the latest in 3U CompactPCI technology 3U Compact PCI/PXI Pentium® M SBC- CPC502

Serial-to-wi-fi RS-435 Subsystem Assembly Device Server Equipment

Intel® Pentium® M up to 1.8 GHz 1GB SDRAM w/ECC and 32MB SSD soldered onboard Two Gigabit Ethernet ports on internal 64-bit PCI-X bus Upto 6 USB 2.0 ports *, Two SATA interfaces , Two EIDE*, LVDS* Operates at 0°C to +70°C and -40°C to +85°C 3 Year Warranty *Comes with Rear I/O card and Mezzanine Interface Card

Figure 5 A WLAN network in an industrial environment, supported by available 802.11 products.

overall enterprise network. Controllers and supervisory systems built upon standard computing platforms can easily be provided WLAN connectivity through devices that connect via a standard host bus like SDIO, PCI or USB. Monitoring equipment that previously used the serial interface can be provided with external serial-to-Wi-Fi device servers that bring in wireless connectivity without actually requiring the equipment to be redesigned or upgraded. Sensors are available with different forms of wireless connectivity, but those that provide it via WLAN can be chosen for fresh installations. Even RFID tags, which help track assets, can be WLAN-enabled. With the availability of appropriate wireless devices and systems, industrial environments can easily be universally networked based on wireless transport.

FASTWEL Phone: (877) RURugged Fax: (718) 797-0600

E-mail: Web:

F19P 3U CompactPCI Plus (PICMG 2.30) SBC MEN Micro’s F19P is the first 3U Intel-based SBC that conforms to the new PICMG 2.30 CompactPCI PlusIO standard. Serial functions have been added on the J2 rear I/O connector in CompactPCI systems for flexibility, versatility and easier system upgrades.

Redpine Signals San Jose, CA. (408) 748-3385. [].

MEN Micro Phone: (215) 542-9575 Fax: (215) 542-9577

E-mail: Web:

F50 3U CompactPCI SBC MEN Micro’s F50C conductioncooled 3U SBC offers the MPC8548 or MPC8543 PowerPC processor running at speeds up to 1.5 GHz, 2 MB of SDRAM, 2 MB of non-volatile SRAM, 128 K non-volatile FRAM and up to 16 GB of Flash disk storage.

MEN Micro Phone: (215) 542-9575 Fax: (215) 542-9577

E-mail: Web:

products &

TECHNOLOGY AIM-USA Announces First Commercial HS1760 Test Product

A test product for AS5653 (aka HS1760) applications is designed to fully test the hardware interface and protocol compliance to FC-AE-1553 as profiled by SAE AS5653. The product is capable of testing and emulating the functions of the network terminal, the network controller and the network monitor. The HS1760 test product from AIM-USA combines the AIM-USA APG-FC4-2GB Simulyzer hardware with developed HS1760 protocol software. The HS1760 Test Product includes an Analyzer display that decodes the HS1760 protocol. It also includes a fully documented Windows-based API for integration into a larger test system. AS5653 (High Speed 1760) is a recently published SAE International standard that defines communications between aircraft and weapons systems. AS5653 defines a digital data command and control interface similar to MIL-STD-1553 based on Fibre Channel protocol but operating at a 1-gigabaud data rate. The AIM-USA HS1760 Test Product is aimed at defining a baseline platform for companies developing aircraft/platforms and weapons stores to test compliance with the AS5653 high-speed Fibre Channel network. The product has been delivered to several companies so they can perform compliance testing of AS5653 data to weapon systems through new platforms.

110 kHz TDI Camera Targeted for Solar Cell, FPD and PCB Inspection Applications

The Piranha HS 4k 110 kHz camera from Dalsa offers high responsivity, low noise and high dynamic range, with Camera Link interface and programmable features including Dalsa’s time-delay-integration (TDI) technology. The Piranha HS 4K 110 kHz camera has response of 11,800DN/njcm2 at 0dB 12 bit with 100x anti-blooming capability. This provides an increased line rate over existing Piranha HS camera models at 4k resolution with a 14x14um pixel size.

AIM-USA, Omaha, NB. (402) 763-9644. [].

FMC Mezzanine ADC Cards Support Xilinx Virtex-6 FPGAs

A family of high sampling rate, high bandwidth FPGA mezzanine card (FMC/VITA 57) modules supports the new Xilinx Virtex-6 FPGAs. The new FMC cards from Curtiss-Wright Controls Embedded Computing eliminate data bottlenecks with direct low latency connections to host FPGAs such as a Virtex-6. This helps system designers optimize and increase DSP subsystem performance. They include the ADC512, a 3 GS/s 8-bit, dual channel analog-to-digital converter (ADC) card, and the quad channel ADC513, a 1.5 GS/s 8-bit, analog-to-digital converter (ADC) card, which are able to support up to 1,500 MS/s data throughput per channel. The Curtiss-Wright Controls FMC cards enable system designers to optimize the performance of Virtex-6-based digital signal processing (DSP) subsystems. The high-speed ADC I/O are routed directly to the Virtex-6 FPGAs on the host board via the FMC connector to eliminate data bottlenecks and increase performance. FMC modules enable I/O devices that reside on an industry standard VITA 57 mezzanine card to be attached to, and directly controlled by FPGAs that reside on a host board. About half the size of a PMC module, FMCs provide a small footprint, reduced I/O bottleneck, increased flexibility, and reduced cost through the elimination of redundant interfaces. To maximize data throughput and minimize latency, the FMC connector provides numerous I/O pins that support high-speed signals for moving data between the FMC and the FPGA. Available in both air-cooled and conduction-cooled rugged versions, the ADC512 and ADC513 are designed for use in demanding reconfigurable computing applications, such as direct RF down-conversion, SigInt/Surveillance, Satellite communications and SDR. They speed and simplify the integration of FPGAs into rugged deployed embedded system designs. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (613) 254-5112 [].



Camera configuration is extremely flexible and the throughput and line rate are all software controllable. All cameras are capable of bi-directionality with up to 48 selectable stages, while preventing over-exposure with anti-blooming. The HS 4k is available in two speed grades, ensuring that the best camera throughput can be selected according to the application. It is suited for: solar cell inspection, flat-panel display, electronics manufacturing, document scanning, high-performance web inspection and general machine vision applications. Key features include high response that enables high speed in low light applications and TDI technology enabling high throughput for high volume production at lower costs. Cost reduction includes lower operational costs for lighting as a result of lower energy consumption. Camera configuration parameters are all software controllable. DALSA, Waterloo, Ontario. (519) 886-6000. [].


Qseven-Based Carrier/SBC Duo Rolls 6U VME Multi-Processor for Air-Cooled and Rugged Conduction-Cooled Apps

A 6U VME multi-processor board with Freescale MPC8640/8641 single- or dual-core processors and Altivec engine offers scalable processor performance, high-data throughput, low-power dissipation and extensibility via XMCs, PMCs and FMCs (FPGA mezzanine cards). According to the VITA 57 specification, the VM6250 from Kontron upgrades VME-based air or conduction-cooled applications with processing performance and innovative features.

The Qseven connector scheme leads the way on the notion of combining a variety of I/O technologies onto one connection. Supporting that standard, American Portwell Technology has announced the PQ7M102XL module board and its companion PQ7-C100XL 3.5-inch ESB developer carrier board, which supports an industrial temperature range of -40 to 85 degrees C. At a mere 70 mm x 70 mm (2.75 x 2.75 inches), the ultra compact PQ7-M102XL module board supports the Intel Atom processor Z510PT (1.1 GHz) or Z520PT (1.33 GHz) series and the Intel System Controller Hub US15WPT. The PQ7-M102XL module board features 512 Mbytes system memory; dual independent display by LVDS/SDVO; one Gbit Ethernet; eight USB ports; expansion of two SATA, one SDVO, one PCI-E x1, LPC interface and high definition audio interface. The PQ7-C100XL developer carrier board is based on Portwell’s popular 3.5-inch ESB form factor and features one VGA port and one LVDS port for dual independent one Gigabit Ethernet port; Getdisplay; Connected with technology and companies providing nowvia one seven USB ports; two SATA ports; one SDIO socket;solutions expansion mini PCI-E; plus an onboard 12V to DC circuit DC-inforapplicaGet DC Connected is a newfor resource further exploration intoPQ7-M102XL products, technologies and board companies. tions. Available now, Portwell’s module withWhether com- your goal is to research the board latest datasheet from speak directly panion PQ7-C100XL developer carrier is suited fora company, low-power, withfanless an Application Engineer, or jumpapplications. to a company's technical page, the wide-temperature and devices in military

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With a choice of Freescale MPC8640 single- or dual-core processors at 1.00 or 1.25 GHz and Freescale MPC8641 single- or dual-core processors with 1.33 GHz, the VM6250 combines high processing power and memory bandwidth. With a 64-bit MPX bus running up to 667 MHz, the Kontron VM6250 boosts memory bandwidth up to 4.3 Gbits/s, which makes it 3 times faster than boards based on legacy G4 PowerPC processors. In the rugged conduction-cooled version (-45° to + 85°C), the board is targeted for applications in harsh environments. The VM6250 features soldered DDR2 SDRAM with Error Correcting Code (ECC) and onboard USB Flash support for software storage without rotating nonvolatile memory. Data security is additionally ensured by 128 Kbyte NOVRAM for back up of critical data in case of power failure. One of the two mezzanine extension slots for Macs and PMCs additionally supports FMCs. An optional dual PMC carrier allows up to 4 PMCs. The new FMC standard allows users to easily change the I/O configuration of an FPGA design without having to redesign the core FPGA functionality. Thus a single FPGA design can be utilized in multiple applications by simply using a different FMC. The Kontron VM6250 provides on the front panel 2x Gigabit Ethernet, 1x USB 2.0 and 1 x serial port (EIA-232). Via the P0 connector (VITA 31.1) Gigabit Ethernet, SATA II, USB 2.0, PCI Express 1.0, SRIO, GPIO and 32 I/Os for PMC 1 are connected to the backplane. Besides the 64-bit VME bus (VME64x), Kontron’s VM6250 provides support 2eSST, which enables data throughput speeds of up to 320 Mbytes/s on P1. P2 connects 64 I/Os from the FMC and PMC 2 slot and 32 I/Os from the PMC 1 slot to the backplane. Kontron’s new 6U VME CPU board comes with the Open Source U-Boot firmware and supports VxWorks 6.6 and Fedora 9 Linux. Furthermore, it is covered by Kontron’s long-term supply program. This guarantees customers a multi-year supply of the product beyond its active life. Kontron, Poway, CA. (858) 677-0898. [].

goal of Get Connected is to put you in touch with the right resource.

American Portwell, Fremont, CA. (510) 403-3399. []. Whichever level of service you require for whatever type of technology,

Get Connected will help you connect with the companies and products you are searching for.

Low-Power Core2 Duo Processor in 3U CompactPCI

A new 3U CompactPCI single board computer based on the Intel Core2 Duo SL9380 processor offers a full range of convection- or Get Connected with technology and companies prov conduction-cooled con- Get Connected is a new resource for further exploration into pro datasheet from a company, speak directly with an Application Engine figurations to satisfy a wide in touch with the right resource. Whichever level of service you requir range of telecommunications to Get Connected will help you connect with the companies and produc military applications. XPedite7130 from Extreme Engineering Solutions also provides a PMC/XMC site with Ethernet and the traditional PCI bus (PMC) or PCI Express (XMC) support, suitable for high-bandwidth data-processing applications, storage or additional I/O. XPedite7130 features include up to 4 Gbytes of DDR2-400 ECC SDRAM and 2 Mbyte firmware hub flash (or 1 Mbyte with redundancy) along with 4 Gbytes of NAND flash. The J2 connector I/O includes GPIO, two SATA ports, two USB ports and PMC/XMC I/O. There are also two RS-232/RS-422/RS-485 serial ports. In-house X-ES operating system support includes board support packages for Green Hills Integrity, Wind River VxWorks, QNX Neutrino and Linux LSP as well with as Windows XPedite7130 is shipGet Connected companies drivers. and ping in commercial (0 to +55ºC), industrial and military (-40° to +85ºC) products featured in this section. configurations. Pricing starts at $4,995.


Extreme Engineering Solutions, Middleton, WI. (760) 632-9415. [].

Get Connected with companies and products featured in this section.




Linux-Based I/O Controller Available for PPC, GigE Cubes and RACKtangle Chassis

A new Version 2.0 of the UEIPAC Programmable Automation Controller from United Electronic Industries is now available for the company’s GigE Cubes and RACKtangle platforms in addition to the standard PPCx cubes. The new controller features a Linux OS (2.6.x Kernel), Xenomai Real-Time OS and Eclipse IDE support as well independent 1G Ethernet and USB 2.0 ports for communication and diagnostics. These new features extend the capabilities of this open-source high-speed controller for embedded control system and Hardware-in-the-loop applications. Suitable for highspeed PID loops (8 channels > 20 kHz), you can program it in C in either Linux or Windows environments. The UEIPAC 2.0, Linux applications written on a PC can run fully standalone on any of several UEI platforms—without a dedicated host PC. The controller is compatible with any of the 30+ I/O boards available from UEI, now and in the future. Each Cube consists of a core module (that holds the processor and network interface) along with three or six open I/O slots. Users select the deployment option that meets their requirements, and then match the Cube’s I/O configuration to their application by selecting the appropriate boards. The six-slot Cube provides up to: 150 analog inputs, 192 analog outputs, 288 digital I/O, 48 counter or quadrature channels, 72 ARINC-429 channels, 24 Serial or CAN-bus ports, or 12 1553 communication channels.

Compact Modules Simplify Implementing GPS in Systems

Two easily applied GPS modules blend high performance, low power and cost effectiveness into a single, compact, SMD package. The modules from Linx Technologies use a SiRF StarIII low-power chipset to minimize power consumption and provide high sensitivity, even in dense foliage and urban canyons. The receivers feature an onboard LNA and SAW filter, as well as an integrated antenna in the SR Version or an external antenna for the SG Version, which further lowers cost and reduces complexity. No other RF components are needed and the modules’ standard NMEA data output makes them easy to integrate, even by engineers without previous RF or GPS experience. Both versions are immediately available.

United Electronic Industries, Walpole, MA. (508) 921-4557. [].

SATA/PATA SSDs Feature Higher Speeds and Capacities, Reliability Technologies

Western Digital has announced that it has begun shipping its new SiliconDrive III solidstate drive (SSD) product family based on technology from its March 2009 acquisition of SiliconSystems. The new SiliconDrive III products feature faster read/write speeds and increased capacities, and offer mechanical scalability, making them a suitable storage solution for embedded system and data streaming applications such as multimedia content delivery systems and data center media appliances. The product line includes 2.5-inch Serial ATA (SATA) and Parallel ATA (PATA) and 1.8inch Micro SATA products featuring native SATA 3.0 Gbit/s or ATA-7 interfaces with target read speeds up to 100 Mbytes/s and write speeds to 80 Mbytes/s in capacities up to 120 Gbytes. Performance and reliability are achieved through the integration of the company’s patented and patent-pending advanced storage technologies that include PowerArmor, SiSMART and SolidStor technologies. These are targeted to address critical OEM design considerations such as the elimination of drive corruption due to power anomalies, the ability to monitor a SiliconDrive’s useable life in real-time, and integrated advanced storage technologies that ensure data integrity and SSD life for multi-year product deployments. Western Digital, Lake Forest, CA. (949) 672-7000. [].

In addition to the SiRF Star III chipset, the GPS modules feature 20 channels, 200,000+ correlators, a power consumption of only 46 mW and a sensitivity of -159 dBm. They include battery-backed SRAM and need no programming and no production tuning. The modules use a direct serial interface, include a power-down feature and are RoHScompliant. For getting designs up and running, the Linx MDEV-GPS Master Development System contains everything needed to evaluate the SG or SR Series GPS modules and implement them. The Master Development System features a preassembled development board with an onboard OLED display for stand-alone testing. The system can also be attached to a PC via USB and operated using the supplied software. The software shows satellite positions, SNR, satellites in use, NMEA data, coordinates, and even the module’s position on Google Maps. For development, a prototyping area with breakout headers and regulated power supply allows for rapid testing and interface. Direct technical support for the system and all onboard Linx products is also included. MDEVGPS Master Development Systems are immediately available and are priced at $249 for the SG version and $289 for the SR version. Linx Technologies, Merlin, OR. (541) 471-6256. [].




Tool Suite Supports Integration with the Analog Devices VisualDSP++ Environment

The LDRA tool suite, which provides automated software testing and verification across all stages of software development, has now integrated the Analog Devices VisualDSP++ (VDSP++) software development environment. VDSP++ creates a software development environment for engineers working with Analog’s embedded processors. This offering enables seamless testing of user code at both the unit and system levels, coupled with enhanced error detection to speed up the overall software development process. Integration of the LDRA tool suite and the Analog Devices VDSP++ software combines their respective strengths. The LDRA tool suite supports the instrumentation of user code, test harness creation and processes target responses, and VDSP++ compiles and captures target results. The method of results capture is defined early in the process and is implemented in the instrumentation technique and harness code to accommodate the requirements and limitations of the target whether it is actual hardware or the VDSP++ simulator. Compatibility with the ADI Integrated Development and Debugging Environment enables remote access with the VDSP++ environment. Using this integration method, the LDRA tool suite is able to capture and use the specific environment settings defined within VDSP++ project files (*.dpj and *.dpg) in the creation of source code analysis sets. In doing so, the tool suite is able to ensure that the analysis, build and execution settings that are applied match the project settings, which in turn enables the use of the original project files to build the code as tested. The LDRA tool suite is able to distinguish between the differing files that form a VDSP++ project, ignoring the source files that do not need to be analyzed. When the program executes, the LDRA tool suite can drill down to the captured results and then use these results for unit tests and structural coverage analysis. In this manner the LDRA tool is able to support the analysis needed to demonstrate structural coverage analysis up to and including DO-178B Level A. This integration covers all devices supported by VDSP++. LDRA, Wirral, UK. +44 (0)151 649 9300. [].

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8/11/09 4:25:10 PM RTC MAGAZINE AUGUST 2009


Vision System with Multicore Processing for Multiple Cameras

A new embedded vision system gives manufacturing engineers and system integrators the ability to build high-speed real-time machine vision systems for applications such as sorting products, verifying assembly and inspecting packaging. The NI EVS-1464RT Embedded Vision System from National Instruments is a high-performance, multicore controller capable of processing images from multiple IEEE 1394 and GigE Vision cameras. Additionally, the system features an extended temperature range, a real-time operating system, a solid-state hard drive and a fanless design, making it suitable for use in harsh industrial environments. The EVS-1464RT features a variety of camera connectivity options so engineers can use many different types of cameras to perform simultaneous inspections ranging from high-resolution area scan to high-speed line scan and from color to infrared. The EVS1464RT also includes a wide range of digital I/O and industrial communication options that make it possible for the system to communicate and integrate with automation devices such as programmable automation controllers, programmable logic controllers, human machine interfaces, sensors and actuators to perform faster inspections. The EVS-1464RT can be configured with NI Vision Builder for Automated Inspection (AI), an interactive software environment for building, benchmarking and deploying machine vision applications without programming. With this intuitive, menu-driven software, engineers can build complex machine vision applications that not only incorporate image processing algorithms but also advanced decision making with looping and branching using the built-in state diagram editor. For more advanced applications, the EVS-1464RT also can integrate with NI LabView graphical system design software and the NI Vision Development Module, which is the comprehensive library of image processing functions. Because both software packages work with all NI vision hardware, engineers easily can manage and maintain multiple hardware systems, choose the appropriate hardware for new applications and switch between both software options with minimal effort.

Industrial CompactFlash Card with SMART Option

A new CompactFlash (CF) card from Swissbit—the new C-300 Series—includes the latest enhanced firmware as well as the option to support the Self-Monitoring, Analysis and Reporting Technology (SMART) standard. Using this technology, the C-300 CF card can report its detailed lifetime status, which allows users to predict imminent failure to avoid data loss. Various lifetime relevant statistics are available for analysis, such as the usable Flash spare blocks and remaining guaranteed Flash write life. The lifetime statistics information is collected online while operating, and the SMART status will change to warn when critical values are reached.

National Instruments, Austin, TX. (888) 280-7645. [].

Atom-Based Qseven Module Gains SATA Interface and up to 1 Gbyte Memory

An upgraded Intel Atom-based Qseven module offers more integrated features such as a SATA interface and up to 1 Gbyte system memory. At a mere 70 mm x 70 mm (2.75˝ x 2.75˝), the ultra compact PQ7-M101G is the ideal solution for a range of low-power systems and handheld mobile devices in applications such as medical healthcare, industrial control, gaming, portable device and COTS military markets. The new PQ7-M101G continues to use Intel Atom processor Z510/Z530 and System Controller Hub (SCH) US15W. It includes the same feature set of dual independent display by LVDS/SDVO; one Gigabit Ethernet; eight USB ports; and expansion of one SDVO, one PCI-E x1, LPC interface and high-definition audio interface. Not only does it include enriched features such as a SATA interface and the upgrade option of system memory of up to 1 Gbyte, but its functions can also be further expanded with Portwell’s PQ7C200 developer Mini-ITX form factor carrier board. American Portwell, Fremont, CA. 510-403-3399. [].



Swissbit has also developed an easy to use Windows (Win2000, XP & Vista) or Linux application to interpret the lifetime statistical data. The applications also allow users to collect data in the background and display historical charts of all relevant values. This allows for detailed control over the lifetime statistics and aids in early failure prediction. It is also possible for the customer to seamlessly integrate the lifetime monitoring in a custom application. Swissbit has available Windows and Linux software libraries along with an easy to use application programming interface (API). Swissbit, Bronschofen, Switzerland, +41 71 913 03 03. [].


Hypervisor Adds Virtualization to Multicore Software Solution

A new Type-1 hypervisor from Wind River supports virtualization on single and multicore processors and provides integration with Wind River’s operating systems (VxWorks and Wind River Linux) and supports other operating systems. The Wind River Workbench development tools suite has been extended to support developing software that runs on the Wind River Hypervisor.

Ideal for extreme temperature, shock and vibration environments


3.5" SCSI VME SATA VME SCSI Ultra3 The new hypervisor enables virtualization for devices across a broad range of market segments, including aerospace and defense, Call Toll-Free in the USA: 1-800-808-7837 or 480-483-3777 automotive, consumer devices, industrial and networking. Integration 206 West Julie Drive, Suite 2, Tempe, Arizona 85283 into the Wind River Workbench tools makes it easier for customers to consolidate their systems and adopt multicore technology in devices by using key features in Wind River Hypervisor, including support for A Leader in Mass Storage Solutions since 1993 single and multicore processors and focus on real-time aspects such as performance, latency, determinism and minimal footprint. It enables protection between operating systems and cores, including starting, 6/17/09 9:20:33 AM stopping, reloading operating systems to increase reliability; and highly Untitled-1 1 optimized silicon-specific hardware support. The introduction of Wind River Hypervisor enhances Wind River’s Multicore Software Solution, which consists of three elements: • Operating system choice including a high-performance integration with the industry’s leading real-time operating system VxWorks and commercial-grade Linux platform Wind River Linux, and the ability to integrate other operating systems into the same system; • A broad and flexible set of multi-core software configurations with support for Symmetric Multiprocessing (SMP), Asymmetric Multiprocessing (AMP) and supervised AMP, and virtualization; and • A unified development environment based on Wind River Workbench for configuring, building, diagnosing and analyzing the software for hypervisor-based systems, including the VxWorks and Wind River Linux operating systems and the applications running on these operating systems. Earlier this year, Wind River introduced VxWorks 6.7, which allows system designers to select the optimal multicore design configuration, AMP or SMP, to deliver next-generation devices with higher performance while maintaining or reducing power consumption. Now, Wind River Hypervisor enables systems designers to use a supervised AMP configuration that makes an AMP system easier to configure. Wind River Systems, Alameda, CA. (510) 748-4100. [].

RTC MAGAZINE AUGUST 2009 Untitled-1 1


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Phoenix International designs and builds rugged COTS Data Storage Systems that plug and play in any application -- from Multi-Terabyte Fibre Channel RAID and Storage Area Network configurations to plug-in Solid State Disk Drive VME/cPCI Storage Modules.

4FFVTBUXXXQIFOYJOUDPNPSDPOUBDUVTBUtJOGP!QIFOYJOUDPN An AS 9100 / ISO 9001: 2000 CertiďŹ ed Service Disabled Veteran Owned Small Business

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Development System for CompactPCI Handles Both 3U and 6U

A compact and portable development system designed for CompactPCI backplane architecture offers a modular test and development platform that supports both 3U and 6U CompactPCI cards. The 522 Development System from SIE Computing Solutions is suitable for lab and desktop use, but also rugged enough to withstand transporting to and from the field. The 522 Development System features a versatile design for CompactPCI hardware and software developers. The system provides unobstructed access to both system and rear transition boards for device monitoring. It is available with CompactPCI backplanes that meet the CompactPCI Specification PICMG 2.0 Rev. 3.0, Hot Swap Specification PICMG 2.1 Rev. 1.0 and Telephony Specification PICMG 2.5 Rev. 1.0 The 522 Development System is designed with features like highperformance cooling with speed-controlled fans that provide distributed cooling to both the front and rear card modules. The system is available with front mounted test points and LEDs for all DC voltages, as well as an optional LCD for displaying system voltages and both fan and temperature monitoring functions. The 522 Development System can also accommodate VME64x, VXS and VPX boards, both in 6U and 3U form factors. Modular in design, the system is available in both standard and custom configurations. SIE Computing Solutions, Brockton, MA. (800) 926-8722. [].

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Two new solid-state drives clock in with read speeds of up to 220 Mbyte/s and write speeds of up to 120 Mbytes/s. The Corsair P128 from Corsair memory delivers the same 220 Mbyte/s read speeds and 200 Mbyte/s write speeds as its higher capacity cousin the P256, at a lower cost. The P64 is one of the highest-performing, lowerdensity SSDs available. Both drives utilize the same technology including a Samsung controller IC with 128 Mbytes of cache memory and NCQ support to deliver stutter-free performance. The Corsair P128 solid-state drive is available immediately from Corsair’s authorized distributors and resellers worldwide, and is backed by a two-year limited warranty. Complete customer support via telephone, email, forum and Tech Support Express is also available. Corsair Memory, Fremont, CA. (510) 657-8747. [].


Core 2 Duo ETX Module with CRT/LVDS, LAN, SATA & Audio

A new ETX form factor system on module provides support for Intel Core 2 Duo and Celeron M processors to give customers a substantial choice in power and price. The MB-80050 from Win Enterprises supports SO-DIMM memory slot for DDR2 SDRAM up to 2 Gbytes, and comes with 2 x SATA connectors on-module. The graphic media accelerator X3100 provides both fast video response time and high-quality images via the two-channel memory architecture. Combined with the MB-73210 carrier board, MB-80050 supports dual display via VGA, LVDS, TV-Out (S-Video or Composite Video). With its display-enriched interface, MB-80050 can support various multimedia devices and is appropriate for portable medical, kiosk and other multiple display applications. It features a Compact Flash Socket for embedded application usage. The MB-80050 can also support legacy devices via ISA expansion slots to help maximize their investment. The MB-80050 has been tested with and supports Windows XP Professional. Pricing for the unit begins at $206. A COM Express evaluation base board, the MB-80050, is also available with prices beginning at $102. WIN Enterprises, North Andover, MA. (978) 688-2000. [].

COM Express Module Includes GM45 Express Chipset

The latest in a portfolio of Type II COM Express Basic (small footprint) modules from American Portwell has a footprint of 125 mm x 95 mm (4.92˝ x 3.74˝). The compact PCOM-B213VG includes the GM45 and ICH9M-E chipset; integrated GMA 4500HMD graphic engine that supplies extreme 3D performance for media applications such as highdefinition 1080p imaging. Active Management Technology (AMT) 4.0 and Trusted Platform Module (TPM) support effective remote management and enhanced security. Two SO-DIMM sockets support DDR3 SDRAM up to 8 Gbytes and the board has both EIDE and SATA as well as one Gigabit Ethernet. I/O expansion (via the Com Express carrier board) includes one PCI-E x16 multiplexed with SDVO interface, five PCI-E x1, four PCI, LPC interface and high-definition audio interface, and a PCOM-C210 Developer COM Express Type II carrier board. Portwell’s PCOM-B213VG is targeted for solutions in applications such as medical devices, test equipment, industrial controls, gaming machines, portable devices and COTS military. In each of these market segments, COM Express safeguards development investments and lowers total cost of ownership by enabling designers to partition commodity host-processor COM Express modules from proprietary, value-added platform building blocks, including FPGAs and specialty I/Os on custom baseboards. American Portwell, Fremont, CA. 510-403-3399. [].

INDUSTRIAL I/O via Ethernet Monitor position & speed | Regulate fluid levels Measure temperature | Control motors & solenoids

SENSORAY’s data acquisition applications range from controlling cranes at shipping ports to controlling water pressure at laser jet cutting factories. We specialize in the development of devices for industrial sdioincluding nelos & srotEthernet, om lortnoC PC/104, deeps &PCI, noitiand sop roPCMCIA. tinoM applications on several buses, We support operating slevel diuPocket lf etalugPC/Windows eR erutarepmCE, et eReal-Time rusaeM systems which include Windows, Linux, OSs and QNX. We offer off-the-shelf, custom or modified solutions, live technical support and evaluations.

To learn more visit:, email: or call: 503.684.8005 Model 2426 | Industrial I/O via Ethernet

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AUGUST 2009 RTC MAGAZINE 6/12/09 10:11:16 AM

Microscale Heat Pump Enables Pinpoint Thermal Management

A high-voltage, low-current thin-film thermoelectric cooler (TEC) targeted at laser diode cooling for the telecommunications market achieves a 60°C temperature difference between its cold and hot sides. This temperature difference, known as the deltaT, reflects the ability of the device to pump heat efficiently. For customers in the optoelectronics and telecommunications industries, this translates to improved cooling performance, lower input power requirements and greater efficiencies for solving thermal management issues in electronic packages. The OptoCooler HV14 thermoelectric cooler from Nextreme Thermal Solutions is the first module in a new class of high-voltage and high heat pumping thermoelectric coolers that operate at low currents and are optimized for standard circuitry and power requirements. The device can pump up to 1.5W of heat at 85°C and operates at a maximum voltage of 2.7V with a maximum current of around 1A; with a footprint of only 2.8 mm2. The module is suited for the cooling and temperature control of optoelectronic devices such as laser diodes for transmission modules and photodiodes for sensing. Bulk TEC devices have been used to provide temperature control of laser diodes and other optoelectronic devices. However, a major trend in photonics today has been the move to smaller form factor, higher power, and more integrated, cost-effective packaging in order to enable a lower cost structure while concurrently opening the door for higher volume manufacturing. In the course of this transition, conventional thermoelectric solutions have not kept pace with these needs due to their size and power density limitations. Due to the micro-size and power-pumping capabilities of the HV14 module, manufacturers of LEDs and other semiconductor chips can now integrate cooling and temperature control functionality directly into the package during assembly, resulting in a high-volume, lower cost thermal management solution. Nextreme Thermal Solutions, Durham, NC. (919) 597-7300. [].

Image Acquisition Board for General Purpose Machine Vision Applications

An entry-level Camera Link image acquisition board, which is easy to set up and use, delivers highly reliable image acquisition and offers extensive software support. The Xcelera-CL LX1 Base image acquisition board from Dalsa is designed for Camera Link Base cameras. Designed for the PCI Express x1 interface (V. 1.20), the Xcelera-CL LX1 Base can acquire images from a variety of multi-tap area and line scan, color and monochrome cameras. Camera Link operations are supported up to 85 MHz. The Xcelera-CL LX1 Base has also been engineered within Dalsa’s Trigger-to-Image Reliability technology framework to more reliably and efficiently control and monitor the entire image acquisition sequence. This frame grabber is designed for ease of implementation in a wide range of OEM imaging applications including electronics and semiconductor inspection, as well as generalpurpose machine vision applications. All Xcelera series frame grabbers are supported by Dalsa’s Sapera Essential software package. Sapera Essential is a machine vision software toolkit that bundles board level acquisition and control with advanced image processing capability, featuring 1D/2D barcodes, OCR, pattern finding, color analysis, blob analysis and lens correction tools. Sapera Essential is designed to deliver the critical functionality needed to design, develop and deploy high-performance machine vision applications while at the same time significantly lowering the deployment costs. The software run-time license, included at no additional charge, offers access to over 400 image processing functions, area-based (normalized correlation-based) template matching tool, blob analysis and lens correction tool. List price is $495. DALSA, Waterloo, Ontario. (519) 886-6000. [].





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RTC Magazine August 2009  

Serial Interconnects: The Next Generations

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