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The magazine of record for the embedded computing industry

July 2009



Processor Architectures Cut Power Usage Pick the Right Model for Data Acquisition Wearable Computers: More Personal than PCs An RTC Group Publication

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Mike Deliman Here’s a guy who appreciates the view from above. When he’s not trekking the high plains and mountain passes of Tibet, Mike Deliman is working on aerospace and defense projects for Wind River. He’s fond of Mars rovers, solar panels, and astronauts; and his real-life heroes are Albert Einstein and the Dalai Lama. He’s aiming high.

Aerospace and Defense Regional Developer Conference, Framingham, MA Register now to join Wind River and our keynote speaker, Ken Krieg, Former Under Secretary of Defense for Acquisition, Technology, and Logistics, and our key partners at our conference dedicated to Wind River’s aerospace and defense solutions. Get the latest information on Wind River’s industry-leading multicore solutions, Wind River Hypervisor, VxWorks MILS, VxWorks 653, VxWorks AMP/SMP, Wind River Linux, and our Common Criteria/DO-178B security and safety solutions.

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WIRELESS NETWORKS Pose a Challenge to Security

46 Quad Channel ADC FMC Card for Rugged DSP Applications

49 MicroTCA Carrier Management Controller Reference Kit Uses Mixed-Signal FPGA


50 USB Serial Converter for Immediate Updates to Legacy RS-232 without Layout Changes

JULY 2009


5Editorial WSNs Look Like a Foundation for Building Energy Efficiency

Technology in Context


Low-Power Processors

Human/Machine Interfaces

Key to Really Low Power: 10 The Fewer Interrupts Kristian Saether, Atmel


Industry Insider Latest Developments in the Embedded Marketplace

Solutions Engineering


Small Form Factor Forum Netbooks Provide Easy Entry to Small Form Factor World



Products & Technology Newest Embedded Technology Used by Industry Leaders

Data Acquisition Maximizing Resources in Data Acquisition Systems with a Network Data Model John Pai, Birdstep Technology

Cost, Better Results with Wearable Computers in the 38Lower Enterprise Larry Ricci, Eurotech

Industry Watch Multicore Processing

Good News and the Bad News: Your New Chip Has Multiple Cores 42The Arun Subbarao, LynuxWorks

Industry Insight Security for Wireless Networks

in Wireless Sensor Networks 24 Security Kurt Stammberger, Mocana

30 Wireless Security and CERT C Chris Tapp and Paul Humphreys, LDRA

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JULY 2009 Publisher

Embedded Super Power #103:

PRESIDENT John Reardon,


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EDITOR-IN-CHIEF Tom Williams, CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, COPY EDITOR Rochelle Cohn

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JULY 2009

Tom Williams Editor-in-Chief

WSNs Look Like a Foundation for Building Energy Efficiency


hile wireless sensor networks have been around for a while, their applications have been pretty diverse—including such things as military and security sensing, environmental monitoring, monitoring road conditions, controlling crop irrigation—the list goes on. Recently, however, in addition to all the diverse applications, there seems to be a focusing of attention on one area with a huge potential, and that is energy conservation. In fact a number of companies including Arch Rock and Digi, which started as suppliers of general-purpose wireless sensor network technology, are now beginning to offer a range of products and software designed for the sensing, analysis and control of energy usage in commercial and industrial environments to the home with smart appliances, thermostats and water/electric meters. The ZigBee Alliance has defined a Smart Energy public profile against which OEMs can design compatible devices for use in eventually building out the Smart Grid. The main thing about what we call a wireless sensor network is that it is far more than a communicating mesh of little intelligent sensors. To do real work, it forms a full hierarchical machine-tomachine system of cooperating sensors, actuators and devices that deliver information from the lowly hair dryer to the utility generating plant. That means that the sensors connect with each other and through gateways ultimately to the Internet and/or the power grid. Among the most obvious advantages is automated meter reading, which eliminates the guy in the truck with the clipboard. But the data from these automated meters comes in at something close to real time—at most hourly—which enables utilities to adjust power sources around the grid as well as to communicate back to users. For example, a smart appliance can be set to react to a drop in rates to run at night or some other convenient time. As homes become equipped with advanced metering and demand response programs, and when commercial and industrial facilities can actually analyze and understand their energy usage, everybody from the housewife to the power company will be able to better manage, control and conserve energy usage. That will, in turn, make the use of renewable sources more adaptable to widespread usage because fluctuating conditions of

things like wind and sunlight can be compensated for by real-time monitoring and load adjustment. Needless to say, the advocacy in this space is self-centered in that such a prospect of an intelligent grid with wireless intelligent meters, sensors and controllers along with all the ancillary applications means a huge opportunity for the developers and vendors of all kinds of embedded devices. Products are just starting to roll out in the form of smart meters, programmable thermostats that support things like standard HVAC systems and heat pumps, and that can at the same time supply data over the wireless connection for monitoring and analysis. Gas and water meters are also included as well as wireless monitors for individual electrical outlets. These are just some of the end-user devices that are beginning to appear. Of course, at the OEM and service provider level as well as for the industrial and power utility user, there are larger systems in the offing that pull together the data from a building, a facility and even from sections of the overall grid to show points of usage that will draw attention for optimization of loads and usage. All this is enabled by the advances in silicon technology, and that will drive the development and deployment of ever more smart devices to the commodity level because what they represent happens to be something of real value—a way to bring down energy costs. But let us be clear about which energy we are talking about. It’s mainly coal and not oil. Over fifty percent of electricity in the U.S. is still generated by burning coal. To bring down the use of oil, there will have to be a similar infusion of intelligence into the transportation arena because that is what powers some ninety-five percent of our transportation systems. Here, of course, there are also huge opportunities for embedded intelligence that are only tentatively being tapped. Hybrid and electric vehicles are just getting a serious look in this country after the disasters of the U.S. auto industry. Tesla Motors just got a big stimulus package and will be building a plant in the San Francisco Bay Area. M2M applications make routing trucks and delivery vehicles more efficient. Opportunities are screaming for attention in all these energy efficiency application areas. The companies that are quick to respond have every chance of doing extremely well in the future. RTC MAGAZINE JULY 2009



INSIDER JULY 2009 Android Platform on MIPS Architecture Aims to Drive Beyond Mobile Handsets MIPS Technologies has announced availability of the Android platform on the MIPS architecture. The company also announced it will make the MIPSoptimized source code publicly available within 60 days. This move, backed by several ecosystem partners—with more to come—brings Android to the MIPS development community across the world, which can now begin using this revolutionary platform for consumer devices such as DTVs, mobile internet devices (MIDs), digital picture frames (DPFs) and set-top boxes. Separately, MIPS announced that it has joined the Open Embedded Software Foundation (OESF), an organization focused on standardization and development of Android platforms for embedded devices beyond mobile handsets. Android provides a common framework across devices to leverage the large number of software application developers that are writing applications for the Android market. Initially finding success in the mobile phone market, Android is now set to move into other digital consumer devices. Android’s ready-to-use software stack provides a device-agnostic application development platform, and a common framework for the industry. With Android and the dynamic open source development community around it, developers can easily and quickly create new applications, and OEMs can leverage the growing set of applications for their devices. With the MIPS ecosystem around Android, OEMs will be able to quickly optimize Android for their specific platforms. Embedded Alley, a provider of embedded Linux solutions, is offering support for SoC implementations from MIPS Technologies’ licensees. The Embedded Alley Development System for Android-based Devices includes processor and board support as well as a version of the Android Dalvik virtual machine (VM) optimized for the MIPS instruction set and CPU cores. This includes extending the Android bionic library, linker and other software infrastructure for the MIPS architecture; and providing integration and testing board support for industry-specific device drivers, CODECs and other middleware. Viosoft Corporation, a pioneer of fully integrated embedded Linux software solutions, is a key partner for MIPS-based software development tools. Viosoft’s Arriba tools deliver comprehensive support for single and multicore platforms. The tools support Android, and are available today.

Zigbee Alliance Certifies First Golden Units for Zigbee RF4CE

The ZigBee Alliance, a global ecosystem of companies creating wireless solutions for use in energy management, commercial and consumer applications, has announced the availability of ZigBee Golden Unit platforms that implement the ZigBee RF4CE specification. ZigBee RF4CE was designed to replace infrared (IR) remote controls with radio



frequency (RF) and thereby offer non-line-of-sight operation, longer range and battery life for consumer electronic devices like HDTV, home theater equipment, set-top boxes and other audio equipment. Freescale Semiconductor and Texas Instruments are the first members to have successfully implemented the new ZigBee RF4CE specification and pass independent testing conducted by NTS Corporation, TRaC Telecoms & Radio and TUV Rheinland to achieve Golden

Unit status. This milestone enables original equipment manufacturers (OEMs) to create ZigBee RF4CEcertified products that allow for advanced interoperable communications between components and remote controls while providing interoperability between OEMs. Other platform suppliers are now able to seek ZigBee RF4CE platform certification and further broaden the already strong ZigBee supply chain. To maintain quality, the ZigBee Alliance requires Golden Units for all new specifications. This process ensures all platforms demonstrate full interoperability for future ZigBee RF4CE products. Golden Units also prove that all technical aspects of the specification can be implemented and perform as intended using multiple independent implementations. Announced in March 2009, ZigBee RF4CE is a standardized specification for RF remote controls that will enable faster, more reliable and greater flexibility for devices to operate from larger distances, effectively removing the line-of-sight and field-of-vision barriers in today’s IR remotes. The ZigBee RF4CE specification is designed for a wide range of products, including home entertainment devices, lighting control, security monitoring, keyless entry systems and many more.

National Instruments and MobileRobots Collaborate on Foundation Technologies

National Instruments has announced a collaboration that combines the ease of use and flexibility of its LabView graphical system design software and MobileRobots Indoors autonomous mobile platforms to help engineers rapidly deploy service robot applications. Engineers working on robotics applications often are challenged to assemble a solution from the myriad of software and hardware tools that offer niche functionality and limited or no integration with other platforms. The collaboration between National In-

struments and MobileRobots gives engineers a seamlessly integrated robotics development platform based on proven and robust technologies. MobileRobots Indoors is a general-purpose platform that helps non-programmers quickly customize and install autonomous robots for applications such as couriers, guides, kiosks and inspectors. The robots also offer easy interoperability with third-party vendor solutions. MobileRobots Indoors technology is the basis for numerous robotics companies’ autonomous robotics solutions, and robots using this technology drive millions of kilometers each year in factories, hospitals and offices in the United States, Europe and Asia. LabView delivers a sophisticated and robust graphical programming environment that makes it easy to add accessories, including manipulators, sensors and other taskspecific components, to robots with MobileRobots Indoors technology, and to rapidly integrate these robots or robot fleets into an automation environment such as factories, clinical labs or facility security systems. LabView simplifies application development by abstracting the underlying code, making it ideal for robotics engineers, who often have experience with mechanical or electrical engineering but limited or no software programming knowledge. The seamless integration between LabView and MobileRobots Indoors is made possible by a set of LabView virtual instruments (VIs). Using MobileRobots’ TCP/ IP-based protocol, engineers can connect to MobileRobots platforms and program them with LabView to add custom capabilities such as speed and directional changes. Engineers also can use the VIs to take advantage of the Mobile SimBank at the MobileRobots headquarters, to remotely test their simulations for both single robot designs and more complex fleet applications to reduce disruption when the robots are installed in a factory or other location.

Kontron Calls for PICMG Spec for Smaller COMs

Kontron has issued a statement welcoming the publication of the COM Express carrier board design guide 1.0 by the PCI Industrial Computer Manufacturers Group (PICMG). As a next step, the statement calls for a PICMG specification for smaller Computer-on-Modules as essential, because demands in the market for smaller Computeron-Modules are increasing. “For COM Express, it’s an important milestone that the COM Express carrier design guide has been published by PICMG. It guarantees that modules from different manufacturers that conform with the COM Express specification are interchangeable on the carrier boards based on the design guide 1.0,” explains Norbert Hauser, vice president marketing at Kontron. “We will not, however, be resting on any laurels, as the market demands an official standard for smaller modules.” The introduction by Kontron—and already supported by several other embedded vendors— of the compact microETXexpress (95 mm x 95 mm) and ultra small nanoETXexpress (55 mm x 84 mm) modules, offers up two COM Express compatible footprints (following pin-outs Type 2 and 1 respectively) that it says represent a logical advancement of the existing COM Express specification to “basic” and “extended” footprints already noted under the standard. An official PICMG specification for these smaller Computer-onModules would make COM Express a universal specification for all module sizes and guarantee compatibility of carrier boards. The 160-page publication of the carrier board design guide provides complete vendor-independent standardization, which is required for scalable Computeron-Module designs. The PICMG Carrier Design Guide 1.0 offers comprehensive information for developers of custom-designed

carrier boards for COM Express modules. In combination with the latest COM Express specification and the module vendors’ product manuals, the design guide will greatly simplify design efforts and guarantee optimal interchangability of Computer-on-Modules from different manufacturers. For reference, it includes numerous connection diagrams and external switching circuits plus descriptions of ideal implementation solutions for all COM Express interfaces.

EcoCAR Competition Announces Winners from University Engineering Schools

Six North American university student engineering teams were recognized with top honors for their green-vehicle architec¬ture designs at the EcoCAR: The NeXt Chal¬lenge Year-One Competition Finals June 7-12 in Toronto, Canada. The EcoCAR Challenge is a three-year con¬test—with annual progress competitions—that challenges university engineering students across North America to re-engineer a 2009 Saturn VUE to improve fuel efficiency and reduce emissions, while maintaining the vehicle’s performance and consumer appeal. All participating teams apply real-world automotive engineering practices through the use of model-based design techniques including hardware-in-the-loop (HIL) and software-in-the-loop (SIL) simulation to bring their vehicle control designs from concept to the road. Of the six highest placing teams, four—the Ohio State University (First Place), the University of Victoria (Second Place), Mississippi State University (Third Place) and the University of Waterloo (Fifth Place)—all developed their vehicle control strategies using dSPACE HIL simulators and rapid control prototyping (RCP) systems. Ohio State prevailed over 16 other North American universi-

ties, partly by demonstrating the most effective use of modeling and simulation to develop their vehicle architecture. The team’s EREV (Extended Range Electric Vehicle) architecture design is powered by a 1 .8-liter engine and fueled by E85 ethanol. This design is predicted to increase the vehicle’s overall fuel economy by 300%.

Cavium, Atheros Team to Enable Wireless HD Video to Flat Panel Displays

Cavium has announced a collaboration with Atheros Communications to offer an integrated platform that enables wireless HD 1080p60 video transmission to flat panel displays. Wireless video distribution is increasingly used by consumer electronic manufacturers, service providers, gaming console vendors, and aftermarket gateway and HDMI cable replacement vendors to connect multiple video sources to flat panel displays without wires. Cavium Networks’ netHD technology, paired with Atheros’ 802.11n XSPAN MIMO-based, dual-band solution, uses standard H.264 video encoding, IP networking and quality of service techniques to provide 1080p60 high-quality wireless video. Atheros’ XSPAN family of solutions provides up to 300 Mbit/s data rates with a range of more than 100 feet through multiple walls. Additionally, Atheros XSPAN solutions provide multiple Quality of Service parameters that are dynamically tuned on-the-fly by Cavium’s netHD technology to provide a smooth and high-quality HD video experience to the flat panel end user. The netHD evaluation platform provides a development platform to build next-generation in-home wireless distribution systems called netHD gateways. netHD integrates the Cavium Networks’ PureVu CNW3602, OCTEON CN50XX processor

and Atheros’ widely adopted XSPAN 802.11n chipset. The platform offers 2x HDMI interfaces, 1x VGA input, 1x SPDIF audio output, 1x GE port and 1x USB 2.0 host. The HDMI interfaces can input 1080p60 HD video and send a secure compressed video stream via 802.11n WLAN to a receiving flat panel. The netHD evaluation platform ships with ready-to-use software called the netHD application suite.

Digi-Key and IAR Systems in Global Distribution Deal

Electronic components distributor Digi-Key Corporation and IAR Systems announced today that the companies have entered into an agreement for the distribution of IAR Systems development tools for embedded systems. IAR Systems products stocked by Digi-Key include IAR Embedded Workbench, a set of development tools for embedded applications. It integrates the IAR C/C++ Compiler, assembler, linker, librarian, text editor, project manager and C-SPY Debugger into an integrated development environment. Additionally, DigiKey will be stocking IAR PowerPac, an integrated middleware toolset for designing embedded applications. This toolset contains a fully featured, real-time operating (RTOS) and a highperformance file system, which is highly optimized for minimum memory consumption in both RAM and ROM. IAR PowerPac is the perfect complement to IAR Embedded Workshop. Other tools in the offering include IAR KickStart Kit for STM32 and IAR KickStart Kit for LPC2478, which have the hardware and software needed to design, develop, integrate and test applications and IAR J-Link—a small USB-JTAG/SWD debug probe. These products are featured in Digi-Key’s print and online catalogs. RTC MAGAZINE JULY 2009



FORUM Paul Rosenfeld

Netbooks Provide Easy Entry to Small Form Factor World


y wife says I shouldn’t be allowed to go to Fry’s Electronics without adult supervision. Hence it was with great trepidation that I wandered alone into Fry’s Palo Alto store a couple of weeks ago to buy a memory upgrade for my decidedly un-small form factor 130W dual core Pentium D CPU desktop. The great risk is that I will be unable to just head straight for the memory counter, make my purchase and immediately check out and leave. True to form, after making the memory purchase, I sneaked over to the computer section to check out the latest in laptop technology. I found a row of “netbooks,” the new Intel terminology for ultra small laptops, from half a dozen suppliers including Acer, Asus and HP. Fifteen minutes later, I left Fry’s with two 1 Gbyte DIMMs and a new Acer Aspire One Netbook. Now I need another computer like a cow needs a fifth leg, having three desktops and a laptop that are still functioning. But it was cute, I hate carrying my 10-pound, 15” Toshiba (with its 45-minute battery life) around, and it seemed like a good opportunity to evaluate the impact that new small form factor technologies are having in the commercial (e.g., not embedded) world. Maybe some lessons would emerge. The first thing that grabs you is the size: 9.75” x 6.5”. Just slightly bigger than an EBX SBC (originally Ampro’s Little Board that is now the biggest of the small form factor SBCs, making it a big Little Board, but let’s not go there). Packed into this space is a 1.6 GHz Intel Atom CPU, 1 Gbyte memory, 160 Gbyte HDD, 802.11 alphabet soup, Ethernet, 3 USB ports, an SD memory card reader, a full-sized qwerty keyboard and 8.9” LCD. It’s also available with a 10.1” LCD in the same package, which must utilize a smaller bezel. It runs Windows XP (not enough memory for Vista, thank you). What really got me was the $250 price tag ($227 with a 120 Gbyte HDD), in your choice of colors. It looks, smells and feels pretty much like any small system using any of the dozens of small form factor SBCs or COM modules on the market today. And the little gotchas that come while using it are probably not too far from what you will experience building a small form factor solution for your application. First,



the display is 1200 x 600, not too tiny for my aging eyes, but the missing pixels from the bottom are noticeable in some software. And my Yahoo! email provided a sweet little note to tell me that the resolution was too low and I should switch to Yahoo! Mail Classic. I declined and it worked just fine. The keyboard is not bad for its size, but I’ve yet to touch type with much accuracy. I’m just not used to where some of the keys are located. The Atom processor really does make a difference in battery life. I’m averaging between 2.5 and 3.0 hours per charge off the standard 3-cell battery, and can run all day with judicious use of standby and hibernation. Recharging is fast. Performance is reasonable—certainly the match of my four-year-old Toshiba with a 1.5 GHz Celeron M and a similar feature set. The big surprise was holding this thing on my lap for a while. While I didn’t get third degree burns, it gets pretty hot. I don’t think there is a fan inside—unless it is totally quiet. I don’t feel any airflow. This is just another reminder that perhaps the biggest single problem with any small form factor system is heat dissipation, and this netbook confirms for me that we have a long way to go. If you are evaluating the new low-power processor technology (Intel Atom or VIA Nano) for a small form factor system, it may be easier (and certainly cheaper) for you to do at least some of your evaluation with one of these netbook solutions. It’s the first time in quite a while that off-the-shelf commercial laptops are available with the same technology being widely designed into embedded applications. Save yourself some grief. The take-away message might be that small form factor solutions require some compromise. If you understand in advance what the compromise entails, and find that your application does not suffer, you are an ideal candidate for this technology as it matures and goes mainstream. Now, about your legacy serial ports… –Paul Rosenfeld

We’ve Hatched the Next Generation of Software Radio Solutions

Pentek delivers board and system-level SDR products that include digital downconverters, upconverters and transceivers. Since all of these products are FPGA-based, Pentek offers powerful factory-installed IP cores plus the GateFlow FPGA Design Kit for custom development. These software radio solutions are perfect for applications in communications, SIGINT, radar, direction finding and many more.

s 8-#0-# 0#) 0#)E 6-%683 C0#) Let Pentek help you get your software radio systems out of the nest on time! Call 201-818-5900 or go to for your FREE Software Defined Radio Handbook, technical datasheets and to request pricing.


Pentek, Inc., One Park Way, Upper Saddle River, NJ 07458 Phone: 201.818.5900 Fax: 201.818.5904 Worldwide Distribution & Support, Copyright Š 2009, Pentek, Inc. Pentek and GateFlow are registered trademarks of Pentek, Inc., Other trademarks are properties of their respective owners.

ploration your goal k directly age, the source. ology, d products

Technology in



The Key to Really Low Power: Fewer Interrupts Controlling communication between peripherals and moving data can be cycle- and interrupt-intensive if handled by the CPU. Adding an event handler and DMA can greatly reduce the cycles used and the power consumed. by Kristian Saether, Atmel


s embedded applications become CPU clock may have to be increased, with more responsive to their environ- a linear increase in power consumption. ments, the number of peripherals In extreme cases, the design must be mineeded to capture and process data is grated from an 8-/16-bit to a 32-bit device, exploding. It is commonplace for micro- just to keep up. Frequently, a signal on a peripheral controllers to have ADCs, DACs, PWMs, does not in itself require the CPU to do multiple timer/counters and numerous anything except let another peripheral TWI, SPI, CAN, USB and USART interknow it needs to do something. Unfortufaces for communications. More periphernately, liaising between two peripherals als mean more cycle-intensive interrupts, nies providing solutions now requires cycle-intensive interrupt processand the amount of data that must be moved ion into products, technologies and companies. Whether your goal is to research the latest ing. For example, in a motor control apbetween the memories and the peripherals ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you plication, overheating is prevented by congrows exponentially. you require for whatever type of technology, stantly measuring the current on the motor Generally, the CPU is in charge of and products you are searching for. and toggling an analog comparator when processing interrupts and moving data. an over-current situation signals that the In some applications the CPU may spend motor has stalled. The CPU is interrupted most of its cycles on these activities. For example, managing two simultaneous and shuts down the pulse width modulator inter-peripheral communications and a (PWM) output for the motor driver. This single 64 Mbit/s data transfer would re- process can require tens of cycles plus anquire 200 CPU MIPS and consume 240 other 20-100 cycles to restore the context. mA due to the extensive context switch- The microcontroller is not really doing ing and interrupt usage involved. In order anything that requires its processing capato meet the extra computational load, the bilities. It is basically just passing a message from an analog comparator to a PWM output. The cycles are basically wasted. Get Connected Other cycle wasters include the use of with companies mentioned in this article. timer/counters to time other peripherals

End of Article



Get Connected with companies mentioned in this article.

such as ADCs and DACs. In these situations, an interrupt is generated to start every conversion. At a sample rate of just a few kHz, these timer/counter interrupts consume over 1 MIPS—about 8% of a 12 MIPS MCU’s capacity. If these peripherals could communicate with each other directly without interrupting the CPU, millions of cycles could easily be saved each second. One reason why 8-bit applications outgrow 8-bit microcontrollers is that, as applications become more data-intensive and interrupt-driven, most of the MCU’s MIPS are wasted on these activities. Transferring data between the peripherals and memories further increases the load on the MCU. A 350 Kbit/s data transfer requires between 22 and 25 CPU MIPS. One solution to this problem is to use a low-power 8/16-bit single-cycle RISC MCU with an 8-channel event system and DMAs that off-load these functions from the CPU. This microcontroller architecture allows the simultaneous execution of up to 8 inter-peripheral events, plus up to four 64 Mbit/s data transfers, while consuming a total of less than 10 mA. Since

technology in context

0.6 mA/MHz, the microcontroller would consume 8.6 mA for this task alone. A comparable MCU with an event handler would require zero MIPS and no incremental power consumption (Figure 2). By eliminating the interrupt, processing response latency can be reduced to a guaranteed maximum of two clock cycles—or 62.5 nS with a 32 MHz clock. The fastest possible response time is 31.2 nS. In fact, using an event system on an 8-/16-bit MCU can achieve event response times that are 37 times faster than that available from a conventional 32-bit MCU without an event system (Table 1).

Souping up Data Transfer

Transferring data is another cycle-intensive contributor to power consumption. Since an 8-bit CPU, on its own, can transfer only one byte of data at a time, there is a lot of processing overhead involved. An 8-bit microcontroller must execute 22 MIPS and consume 14 mA to effect a 350 Kbyte/s data transfer. SPI and USART transfers can have data rates as fast as 25 Mbit/s, making it virtually impossible for a typical 8-bit MCU to support the maximum rate. Adding a peripheral DMA controller to the device offloads essentially all these




Power Control











Reset Control




External Bus Interface



Interrupt Controller Watchdog


Event System


Data Bus



T/C F0:1




T/C E0:1




T/C D0:1




T/C C0:1

Event Routing Network USART C0:1

the event system and DMA allow the peripherals to communicate with each other autonomously, no CPU clock cycles or interrupts are required. The CPU can be put into sleep mode. The event system routes peripheral signals through a dedicated network outside the CPU data bus and DMA controller. The benefit of this is predictable and latency-free inter-peripheral signal communication that reduces CPU time and frees up interrupt resources. The event system enables a change of state in one peripheral to automatically trigger actions in other peripherals. In the motor control example cited earlier, an analog comparator, timer/counter, I/O pin or ADC in the microcontroller can directly shut off the PWM for the motor drive within two cycles of an over-current situation, offering better protection for the motor, while using zero interrupts and zero CPU cycles (Figure 1). Peripheral events that can trigger the event system include timer/counter compare match or overflow, analog comparator toggle, pin change, ADC complete or compare and real-time counter overflow. Events that can be triggered in other peripherals include ADC or DAC conversion, input capture to time stamp communication or ADC measurements, external frequency or pulse-width measurements, clocking of timer/counters, starting a DMA transaction or changing a pin output. Deciding which events should trigger which actions on which peripherals is fully configurable and completely up to the designer. Event system configurations can be kept static and locked, or can change dynamically during various stages of the application execution. The event channels operate in parallel and up to 8 pairs of peripherals can be interconnected simultaneously at any time. Using an event system removes the bottlenecks associated with multiple and/ or frequently triggering interrupts. There is no software overhead and critical tasks can be performed independently of the CPU. The implications for power consumption are significant. A conventional 8-bit MCU, without an event system, requires about 16 MIPS to shut off a PWM in response to an over-current condition on a motor. At 16 MHz, 1 MIPS/MHz, and

Figure 1 MCU with Event System Bus - An MCU with an event system and DMAs routes peripherals signals through a dedicated network outside the CPU data bus and DMA controller, providing predictable and latency-free inter-peripheral signal communication that reduces CPU time and frees up interrupt resources. MIPS


8-16-bit MCU with Event System



Conventional 8-bit MCU



88 X longer

Conventional 16-bit MCU



48 X longer

Conventional 32-bit MCU



- 37 X longer

TABLE 1 Event Processing Cycles and Response Time with and without Event System.



technology in context

Event Generator

Event Channel [7:0] 8x T/C


2x ADC


2x DAC


4x AC


1x RTC




Event User



Compare Match

MUX [7:0]


Event Routing Network


Channel Sweep Single Conversion Event Action Selection

Figure 2

Figure 3

The event system enables a change of state in one peripheral to automatically trigger actions in other peripherals, without any interrupt processing or CPU clock cycles. Up to eight inter-peripheral events, plus up to four 64 Mbit/s data transfers, can be executed simultaneously with CPU in sleep mode and 10 mA power consumption.

Using the event system in conjunction with the DMA controller, an analogto-digital and digital-to analog conversion can be achieved as follows: A pin-change on any I/O pin or an overflow on any timer/counter triggers the ADC conversion without any CPU cycles. The ADC conversion result is transferred over a DMA channel to the SRAM.

cycles from the CPU. When the CPU data bus is free, the DMA controller uses it to transfer data between the memories and peripherals without using CPU resources.

The internal buses to the peripheral registers including I/O pins, memory mapped EEPROM, internal SRAM and the External Bus Interface are split to enable simultaneous bus access from the DMA controller and the CPU. Hence there is always a communication channel available for the DMA. Transferring 350 Kbyte/s of data with a DMA controller requires 99% fewer MIPS and consumes less than 1 mA,

compared with 22 MIPS and 11 mA for an 8-bit MCU without DMA (Table 2). The DMA controller can move data from a peripheral register to internal or external SRAM, between SRAM locations, and even between peripheral registers directly. The four DMA channels have individual priority, source, destination, triggers, addressing modes and transfer block sizes. The DMA can transmit from 1 to

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technology in context



8-/16- bit with DMA



8-bit without DMA



16-bit without DMA



32-bit without DMA



TABLE 2 Typical MIPS and Power Consumption with/without DMA at 350 Kbyte/s.

16 Mbytes in a single transfer, due to the simple linear data memory address space in the RISC CPU and to the auto increment/decrement and reload features in the DMA controller. Using the event system in conjunction with the DMA controller, an analogto-digital and digital-to analog conversion can be achieved as follows: A pin-change on any I/O pin or an overflow on any timer/ counter triggers the ADC conversion without any CPU cycles. The ADC conversion result is transferred over a DMA channel to the SRAM. At the same time, a second timer/counter can trigger a high-speed DAC conversion using a second DMA channel for the data. The event system can make the analog comparator trigger input capture for 100 percent accurate time stamps, automatic capture to time stamp the beginning of communication transactions, or ADC conversion scans on the second ADC. Four event channels are still available that can be used for fault protection of a PWM output controlling a highvoltage driver stage, cascading of timer/ counters, and a couple of communication channels—all at the same time, while the CPU is sleeping (Figure 3). Adding an event system and DMA to a microcontroller can have an enormous impact on power consumption. In some applications, the MCU can spend most of its time in sleep mode, consuming as little as 80 uA/MHz while all peripherals can continue to operate. In a hypothetical application with eight simultaneous events and four 350 Kbyte/s data transfers, an 8-/16-bit MCU with an event handler and DMA would be able to spend 31.6 million cycles per second in sleep mode and would consume a total of just 4 mA. Any traditional 8- or 16-bit MCU without an event handler and DMA would consume 52 to 60 mA. A 32-bit MCU would consume 34.8 mA—almost 10 times more power. In an application with extensive interrupts and data, a microcontroller with an event handler and DMA would consume 90% less power. Atmel San Jose, CA. (408) 441-0311. [].


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Maximizing Resources in Data Acquisition Systems with a Network Data Model When deciding on a data management solution for a data acquisition device, there are several different solutions available depending on needs. Selecting the appropriate data model can significantly impact cost, quality, end-user experience and ultimately customer success. by John Pai, Birdstep Technology


Guy Bob

Artist Table ata acquisition devices have come Primary Key a long way, but since the first defirst_name last_name vices were created, one thing has Bob Dylan remained the same: they have limited reTownes Van Zandt Arlo Guthrie sources. In such embedded devices high Steve Earl performance is paramount, and small ABBA data acquisition platforms need to handle Guy Clark the data throughput at high rates, manage data relationships and process the information withnow minimal processing power nies providing solutions so that more and is companies. availableWhether for the ion into products, technologies youractual goal is to research the latest acquisition application. ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you you require for whatever type of technology, A common misconception when and products you are searching for. hearing the term “database” is the idea that the database is synonymous with enterprise-wise relational databases or inefficient and slow personal databases. Managing data in embedded devices is a different matter than managing data on PCs and servers. Enterprise databases are not designed for embedded devices, and their subsequent adaptations result in large memory footprints, often entirely too large to fit

with companies mentioned in this article.




Get Connected

Townes Steve



End of Article

Album Table Foreign Key first_name Bob Townes Arlo Steve Bob ABBA Guy Townes Arlo

album Modern Times Poncho & Lilly Alice’s Restaurant Guitar Town The FreeWheelin’ Arrival Dublin Blues Legend Hobo’s Lullaby

Figure 1 A relational model database with a relationship between an artist and an album.

JULY 2009 RTC MAGAZINE Get Connected with companies mentioned in this article.

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solutions engineering

into the target device. Enterprise databases do not translate well into embedded devices, and attempting to adapt open source implementations presents its own special set of headaches. The embedded database is another type of database that is dramatically different from the well-known enterprise databases. When it comes to choosing the right embedded database for data acquisition Artist Table Primary Key first_name last_name Bob Dylan Townes Van Zandt Arlo Guthrie Steve Earl ABBA Guy Clark

devices, there are three main types: flat-file, relational and network models. Which is the best one to use for a particular job will depend on factors such as type and amount of data to be processed, as well as how frequently it will be used.

Flat-File and Relational Models

Essentially, the flat-file model is a set of strings in one or more files that

member Owner

Album Table album Modern Times Poncho & Lilly Alice’s Restaurant Guitar Town The FreeWheelin’ Arrival Dublin Blues Legend Hobo’s Lullaby

Figure 2 The same database as the one in Figure 1, but streamlined into a network model.

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The Network Model

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can be parsed to get at the information they store. It is decent in storing simple lists and data values, and can get more complicated when trying to model more complex data. Modeling complex data creates a new set of headaches. One of the main issues with using flat files for even a semi-active database is the tendency to corruption. Generally, a flatfile database does not have a locking mechanism, which prevents data from being corrupted when multiple threads may simultaneously try to write to the database. Even when the device is designed for multiple threads, it is possible for two or more threads to cause a “race condition,” which could be prevented with a locking mechanism. A race condition may force the device to stall indefinitely, which is detrimental especially in an embedded device that normally does not reset easily. In a data acquisition device where reliability of data is also a priority, flat-file databases may not be the best choice. The relational model stores data in tables composed of columns and rows. When data from more than one table is needed, a joint operation relates these different data using a duplicate column from each table (Figure 1). While the relational model is flexible, performance is limited by the need to create new tables to hold results from relational operations, and storing redundant columns. Even when designed efficiently, there are several sources of overhead. The overhead comes in duplication of data, in helping maintain database integrity, and a need for a foreign key to help maintain relationships in the relational database. The overhead results in excess in file size and extra I/O needed to perform basic database operation. Such overhead is especially expensive in resource-constrained devices. Most developers are familiar with the relational database model, such as those from Oracle, Informix, Sybase, etc. Alternative data model architecture is more appropriate for resource-constrained devices such as data acquisition devices.

7/21/09 12:39:27 PM

solutions engineering

The network model is conceived as a flexible way of representing objects and their relationships. The network model predates the relational model and can be viewed as a superset. This implies that anything expressed in the relational model can be expressed in the network model, even SQL support. The main advantage is the way the relationships are modeled.

A primary distinction to the relational data model is that the network model allows designers to describe relationships between records using “sets,� where pointers are used to relate objects directly and navigate between them (Figure 2). When compared to the relational model, the network model is faster, more reliable, uses disk space more efficiently and is better at expressing complex data-

base designs. Consider an instance when traversing from one table to another using a relational link. After locating a key value in the first table, the database engine seeks out the value in an index file; this contains a reference to the second table. Searching the index file costs the system several disk accesses for each record accessed. In the network model, this process is accessed through sets. A set is a linked list representing a oneto-many relationship, which contains pointers to the next and previous member link of the set. Traversing from one member to another member and from member to owner requires only one disk access.

Cost Implications

Consider reading records through the sets. When performing the same task with a database using a relational model, a B-Tree would need to be traversed first, prior to locating the actual record. It is also important to note, not only will there be disk access overhead, but also memory overhead. Any database cache will store the recently visited data, even B-Tree data. Since the BTree search ends up in cache, the cache must be sufficiently large to reduce the chances of additional disk access to update the data. A write operation also involves heavy costs in a relational model. After a record is inserted into the table in a write operation, the database inspects the B-Tree to locate the record’s index position. If there is no room available in the B-Tree, the tree needs to be reorganized to maintain efficiency. This reorganization process is unpredictable because it depends on the fullness of the tree and where in the tree the change must be made. The more nodes a tree contains, the greater the chance of a larger reorganization, which may be time-consuming and unpredictable. The reorganization process may also require the operating system to devote all computing resources into reorganizing in order to meet the time constraints. After the reorganization pro-


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6/19/09 2:45:52 PM



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solutions engineering


x86 Desktop (34,000 records)

ARM7 consumer device (1,776 records)





Records Inserted

81.62 sec

29.07 sec

193.88 sec

33.6 sec

Records Updated

103.28 sec

15.28 sec

Not Available

Not Available

Records Deleted

88.16 sec

17.03 sec

Not Available

Not Available

Records Selected

15.81 sec

.28 sec

1.25 sec

0.0012 sec

TABLE 1 Bench results for relational and network models on x86 and Arm7 devices.

cess is performed, the database can write a reference to the new record in the B-Tree. In a network model, adding a record is relatively simple, less taxing and predictable. The process involves adding a new record and setting pointers to owner, previous and next record. Then, setting the owner’s last pointer to the new record. This process is fast, predictable and does not require reorganization of a B-Tree. Another cost implication involves the features of a database that may help to reduce development time and minimize a measuring device’s time-to-market. Some features can reduce development costs and exploit hardware such as circular tables and hybrid in-memory databases. Birdstep Technology also offers a database that may allow an embedded client to replicate the embedded database into a central aggregate point, a server database.

An MP3 Player Benchmark

So how much in the way of hardware resources can a developer save using the network model? In one example, a threeway relationship, artist->album->song, allowed a commercial MP3 player manufacturer to get some hard facts on resource savings. Developers carefully compared the relational and network models using both desktop hardware and consumer hardware. Table 1 illustrates a correlation between the lack of resources and a difference in savings. On both of these hardware solutions, the network model used 27 percent less disk space to store the same amount of records and


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JULY 2009 RTC MAGAZINE 7/21/09 12:46:17 PM

relationships. All the storage savings can be attributed to replacing the artist>album and the album-> song foreign key index with pointers. Removing these data structures had a huge effect on the storage requirements. A B-Tree index typically requires 1.3 times the space of what it’s indexing. Birdstep Technology Seattle, WA. (206) 748-5353. [].

industry insight



Security in Wireless Sensor Networks Despite their ubiquity, security and networking technologies for sensors and other smart objects are still very much in their infancy, and there is tremendous technical and market opportunity in this arena. by Kurt Stammberger, Mocana



industry insight


evices and “smart objects” like industrial sensors are rapidly outnumbering workstations on networks worldwide, with some experts projecting that within 5 years there will be over 100 non-PC devices for every workstation on a network. Some devices, like sophisticated printers or routers, are relatively “intelligent” and have comparatively ample memory, processing and bandwidth resources at their disposal. As such, we can usually apply some of the security techniques originally developed for networks of PCs directly to the new “citizens” on the network. But at the very low end, devices like environmental sensors often present a unique challenge because of the extreme resource constraints they impose on security architects. Industrial control systems have relied on smart objects like sensors and actuators for years to interact with and oversee factory processes. A typical system consists of battery-powered sensors that send information to a smarter, wired control device. Today’s sensors are tiny, inexpensive to manufacture, and don’t need a lot of power—an essential characteristic, since many sensors are expected to operate long-term without access to line power. Most wireless objects get their power from batteries, but interesting new classes of devices are emerging that scavenge electricity directly from the environment. Computational and communication resources in sensors can be quite limited; just a few megahertz of CPU power paired with several hundred Kbytes of RAM and EEPROM are typical. Most modern sensors utilize radio frequencies to communicate, though optical and infrared communications are also sometimes used, but are less common because of the line-of-sight requirement. Bluetooth might seem like a natural for these networks, but is rarely used because of its relatively greedy power requirements.

and storage resources, and are often used to stage and transmit information to larger IPbased networks, including the Internet. There are a few important factors we always need to keep in mind when working with these networks. First, global addressing systems usually aren’t possible— so we need to be data-centric. Second, power is very scarce, and we often can’t get more if we need it. Transmitting data can consume 1000x more power than processing it, on a per-bit basis. Furthermore, we can’t assume that we know exactly where any given node is at any given time, and sensor networks are often “infrastructureless” which means they need to work in a distributed manner, or not at all. Finally, we certainly can’t depend on any of our objects to be tamper-proof or use any kind of “trusted” computing platform since these characteristics often make the individual nodes prohibitively expensive.

Wireless Networks of Sensors

Sensor Network Security

Some smart objects, like sensors, are typically scattered to cover a specific area of interest. While the range of each object, or node, is limited by its radio transmitter, we generally assume that each node can contact any other, though they may have to rely on nearby nodes to relay their communications to the target. The nodes send data to a “sink” or base station. These centralized stations are systems comparatively rich in CPU

Figure 1 Factory automation increasingly relies on networks of sensors and actuators that must be dynamically reconfigurable and which communicate over a wireless network.

Security requirements often vary with application and context, but in general, security for wireless sensor networks should focus on the protection of the data itself and the network connections between the nodes. Confidentiality, integrity and authentication are the most important data security concerns. When considering the network itself, we need to protect fair access to communications channels (or media access control) and we often

need to conceal the physical location of our nodes. We must defend against malicious resource consumption, denial of service, node capturing and node injection. Sometimes our applications require secure routing to guard the network from the effects of nodes “gone bad.” Finally, we need some mechanism for protecting the mobile code itself. Because distributed control networks like these tend to be extremely vulnerable to simple node attacks, weaknesses in a subsystem can easily be exploited to mount attacks on the whole network, even beyond the “sink.” So it is crucial to design sensor networks with security in mind from the very beginning, not as an add-on feature of the system. That’s largely because security will almost always add some overhead, which means increased power requirements— something that’s difficult to shoehorn in to an already-designed system. Tight integration of security techniques in processing and communications simply allows for more efficient use of scarce resources.

Key Management in Sensor Networks

Key management is usually named as the primary obstacle to true security for sensor networks. In other words, the defining characteristics of wireless sensor networks conspire to make it difficult for two nodes to securely share a secret key, a basic requirement of encrypted communications. RTC MAGAZINE JULY 2009


industry insight

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IP-Enabled Wireless Sensor Nodes

IP Router

IP-Enabled Wireless Sensor Nodes

Figure 2 A network of end-to-end IP-enabled, small footprint wireless network nodes, IP routers and Internet applications. Not all wireless sensor networks support IP throughout. There is a variety of other mesh network protocols by which the sensors communicate. Illustration courtesy Arch Rock.

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JULY 2009 RTC MAGAZINE 9/8/08 11:02:27 AM

The nodes in these networks can’t rely on a central security infrastructure like a Kerberos server. The best-practices method for key management on the Internet—RSA, or Diffie-Hellman-based public key cryptography—is often prohibitively expensive for sensor networks, at least in terms of processing, storage and communications requirements. Key management based on elliptic curve cryptography may offer a solution, but as of yet there is no consensus on standards for its use in sensors. What are our other options? Well, we could preload a single secret key onto all of the nodes…but the capture of a single node would then compromise the entire network. Another approach is to preload that single key, then establish “link keys” unique to every pair of nodes based on the original secret key. Then destroy that original secret key. Unfortunately, this scheme gets unwieldy for even mediumsized networks, and rules out the addition of new nodes after the initial network

setup—usually a deal-breaker. We could leverage a trusted base station to establish link keys with each node, but this is difficult to implement in many sensor networks because it requires time synchronization across nodes. Then, of course, the trusted base station becomes a single point of failure for the entire network—a definite no-no in security architecture. Random key predistribution protocols show some promise in the literature. In these schemes, a random subset of a large pool of keys is preinstalled in each object. If the key set is large enough, then every node can establish connections with at least a few others and thereby patch together a secure network containing all objects. The downsides to this approach include a requirement for a trusted base station, and tamper-resistant hardware in each node to conceal the keys—usually another deal-breaker. The fact is: there’s no easy answer for key management in sensor networks. Sensors are always getting smarter and more

industry insight

capable, and companies like Mocana work hard to super-optimize cryptographic implementations so that device designers can leverage public key techniques for key management. On the other hand though, “there’s always room at the bottom” and someone will always need a device that’s smaller and less power-hungry than the last-best design. For those cases, some additional security risk will have to be incurred using one of the compromise key management techniques listed above.

Sensor Hardware and Software

Sensors have a triple role in most networks; they act as data collectors, processors and as traffic forwarders for other objects in the network. When public key management isn’t an option, the most common approach is to periodically disseminate fresh keys to

routing functions) but at significant added expense. For these reasons, many security functions on sensors are relegated to software. Consider too that tamper-resistant devices can’t be updated or patched dynamically. On the other hand, dynamic software update capability comes at a security cost. A hacker could inject code into the network and initiate a denial-of-service attack, or force a sensor to exhaust its battery by tricking it into performing useless computations or radio transmissions. Given the homogeneity of code across many sensor networks—for example, among clouds of thousands of tiny sensor nodes—such attacks can be disastrous. Protecting code update dissemination is therefore essential. Again, if capabilities permit, public key mechanisms provide best-practices protections (e.g., code sign-

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nodes, and accept the risk that those keys might be intercepted during dissemination. But there are still environments where persistent keys need to be present in the objects to decide whether or not a node can “play” on the network. Unfortunately, a malicious user could paralyze these networks by either capturing a single object (node) and extracting the secret keys or by modifying the networking code of a captured object. Tamper-resistant hardware could mitigate these concerns (to protect keys and

ing). But other options exist. An encryption mechanism with locally shared secret keys (group keys) can ensure that a particular code update originates from an alreadytrusted set of objects. Code distribution algorithms can themselves be hijacked for malicious purposes, but new techniques like CPA and DPA can mitigate these concerns. However, the same mechanisms can be used to propagate a new, malicious code distribution technique as well. Device-based “micro intrusion detec-

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7/7/09 3:47:19 PM

industry insight

tion systems” could be one answer. Under Mocana’s NanoDefender system, when a new application is compiled, NanoDefender performs a static analysis of the code to determine the call flow of the executable. The system determines which functions call which functions, and which functions make which system calls. Later, at link time, the executable is instrumented to track function calls. Finally, at runtime, the code and the modified OS together enforce the proper


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call flow. Such a system (if the sensor has sufficient resources to run it) can virtually eliminate the threats of arbitrary code execution and malware injection.

Routing Security in Sensor Networks

The biggest problem for wireless networks of sensors is that of network operational security. In other words, the problem involves a hierarchical organiza-

7/13/09 3:14:25 PM

tion of nodes in networks and the secure connectivity between sensor nodes and base stations. The functions that we’re looking for include confidentiality, secure routing, detection of bad behavior among nodes, and the ability to “excommunicate” naughty nodes from the network. On the Internet and other infrastructure networks, there is a clear separation of roles: there are end systems (nodes) and intermediate systems (routers, switches and the like). But in sensor networks each node is potentially a router for some other nodes. This creates an entirely new set of vulnerabilities in the network layer. For example, routers can become “neglectful,” in that they selectively do not forward packets from other nodes, or they can become “selfish,” in the sense that they prefer to give preference to their own packets. Such behaviors are often the result of denial-of-service attacks. Wireless sensor networks have a lot in common with wireless ad hoc networks, but many of the security mechanisms designed for ad hoc networks simply won’t fly on networks of sensors. Unlike in ad hoc networks, not every pair of nodes in a sensor network needs to communicate. Also, in ad hoc networks many security mechanisms usually rely on public key algorithms, which are sometimes too expensive in terms of resources for sensor networks. We could attempt to adapt a secure routing protocol based on secret-key cryptography, but it would impose non-trivial packet overheads in addition to necessitating the gathering of node state information. Routing misdirection is an attack whereby malicious nodes advertise false routes to either inject artificial traffic into the channel, direct traffic to a fraudulent base station or node, eliminate part of the network by overtaxing its resources or avoid forwarding packets entirely. Such an attack can be foiled using authentication, network monitoring and redundancy techniques. Authentication mechanisms based on distributed certification authorities have been proposed, but these have been shown to be tough to implement in real-world environments. Some network monitor applications can have neighbor nodes listen to both the sender and forwarder of a message, and notify the sender if the exact packet is not forwarded to the next hop of the route within a specific time limit. Unfortunately, packet

industry insight

comparison is not enough, since aggregation points may delay transmissions until enough information has been collected. Even if the time threshold is long enough, aggregated data will probably not match transmitted data. This will result in mischaracterizing the aggregation node as a “bad actor.”

Battery Attacks

Attacks targeting the battery exhaustion of nodes are termed attacks on “system lifetime.” Why would an attacker bother? Suppose, for example, a sensor network is deployed as an early-warning system for biological or chemical attacks. Because of the widely distributed nature of the sensor network, it would be almost impossible for a terrorist to physically destroy it. An easier option would perhaps be to insert a few misbehaving nodes that force the legitimate sensors to work continuously until their batteries are totally exhausted. Then the terrorist could proceed with his real-world attack, undetected. There is a difficult trade-off in the case of sensor networks. These devices have a triple role: as data collectors, processors and forwarders. The goal of the network is to be working as long as possible, in order to transfer information from the objects to the sinks. But the objects “want” to participate in the network as little as possible, in order to stay active for a longer lifetime. This creates conflict for the node, and sets the stage for battery attacks. Selfish behavior and “unfairness” in cooperative protocols can be considered weak forms of denial-of-service attacks, and there are many others more advanced such as sleep deprivation attacks. Link layer protocols for channel arbitration can even be manipulated to exhaust batteries or simply degrade network performance. For example, channel jamming results in transmission errors, which make nodes retransmit data and increase transmission power to overcome noise. Another form of attack is interrogation. A selfish node may continuously request channel reservation. In cooperative MAC protocols, like those based on IEEE 802.11, neighbor nodes are forced to reply to those requests and thus eventually consume all their energy reserves. Most, if not all of the problems in current approaches to securing networks of smart objects arise from the fact that security has been designed as an add-on,

not as an integral part of the network architecture. The resource constraints common to wireless sensor networks often deprive the security architect of one of our favorite tools: public key cryptography. Fortunately, even the “lowest” modern sensors are getting better processors and more memory, enabling them to “speak IP” and participate in the global public key infrastructure. Good work, too, has been done on optimizing and miniaturizing public key algo-

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rithms, and elliptic curve approaches can sometimes work well. When memory is just too tight, or processors just too weak, however, clever work-arounds and hard compromises are needed. Mocana San Francisco. CA. (415) 617-0055. [].


4:47:07 PM RTC MAGAZINE 2/17/09 JULY 2009

industry insight



Wireless Security and CERT C A set of programming standards is designed to prevent the kinds of errors that can result in security breaches. When combined with automatic tools that can test code for compliance, firmware in wireless networked devices can be made more secure. by Chris Tapp and Paul Humphreys, LDRA


he widespread adoption of wireless technology in embedded systems, such as wireless DSL routers, printers, streaming audio devices, PDAs and smart phones, over the past decade has led to a significant increase in the numbers and types of wireless systems that are in use. These include Bluetooth, Wi-Fi, ZigBee, Wireless USB, 3G and other telecoms. These technologies allow for the easy connection of mobile platforms to peripherals, local networks and the Internet. However, since these connections are over-the-air, they can be intercepted and altered by third parties making them a potential source of security breaches. Wireless security is therefore a major concern, and there are two main aspects that need to be considered when implementing wireless systems. First, the network needs to be secure. Since network security is a “standard” infrastructure issue, it will not be considered further here. However, let’s focus on the second concern—the security of the firmware within the wireless devices. The security of such firmware can be enhanced by applying the guidelines contained within the “CERT C Secure Coding Standard.” During 2008 there was a great deal of positive talk about the emergence of a new breed of programming guidelines from the U.S. federally funded organization, CERT. Languages such as C, C++ and Java are being tackled, with the goal of producing safe, secure and reliable systems. Currently, though, it is CERT C that has made a splash. In October 2008, version 1.0 of the standard made its debut at the Software Development Best



Practices exhibition in Boston. Both C++ and Java secure coding standards are works in progress at present, so for this discussion we focus entirely on the CERT C Secure Coding Standard.

What Is CERT C?

CERT was created by Defense Advanced Resource Projects Agency (DARPA) in November 1988 to deal with Internet security problems after the Morris Worm struck. Its coordination center (CERT/CC) is located at Carnegie Mellon University’s Software Engineering Institute (SEI). Although intended purely as an academic exercise to gauge the size of the Internet, the effect of the Morris Worm had repercussions throughout the worldwide Internet community and infected thousands of machines. Many organizations with systems attached to the Internet suffered damaging denial of service attacks. Consequently, software vulnerabilities came under the microscope of various bodies, including the U.S. government. The SEI CERT/CC was primarily established to deal with Internet security problems in response to the poor perception of its security and reliability attributes. Over a period of 12-15 years, the CERT/CC studied cases of software vulnerabilities and compiled a database of them. The Secure Coding Initiative, launched in 2005, used this database to help develop secure coding practices in C. The CERT C Secure Coding Standard provides guidelines for secure coding in the C programming language. Following these guidelines eliminates insecure coding practices and

undefined behaviors that can lead to exploitable software vulnerabilities. Developing code in compliance with the CERT C Secure Coding Standard leads to higher quality systems that are robust and more resistant to attack. Internet connectivity is clearly a primary source of malicious attacks on software systems. These attacks are now focusing on the components integral to wireless connections. A dependency on connected software systems is not just relevant to corporations or individuals, but also to government and civil infrastructure such as industrial plants, power generation and transmission. More and wider connectivity is becoming integral to the way people work and live. There is a need, therefore, for systems to be impenetrable whether from IT-based hackers or from devices and equipment under the control of those with malicious intent. On this basis, CERT C considers the overall and far-reaching need for secure coding practices. The primary aim of CERT C is to enumerate the common errors in C language programming that lead to software defects, security flaws and software vulnerabilities. The standard then provides recommendations about how to produce secure code. Although the CERT guidelines share traits with other coding standards, such as identifying non-portable coding practices, the primary objective is to eliminate vulnerabilities. And so, what is software vulnerability? The CERT/CC describes a “vulnerability” as a software defect that affects security when it is present in information systems. The defect may be minor, in that it does not affect the performance or results produced by the

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software, but nevertheless may be exploited by an attack from an intruder that results in a significant breach of security. CERT/CC estimates that up to ninety percent of reported security incidents result from the exploitation of defects in software code or design.

nizations such as CERT, SANS, etc. have many reports of wireless system vulnerabilities that could have permitted such attacks. These include integer overflows leading to arbitrary code execution and denial of service, and specially crafted

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LDRA Testbed detection of EXP33-C violation.

What Security Issues Are There with Wireless?

There are two classes of wireless interface that will be considered. First, there are embedded interfaces contained within a ‘box” that provide some functionality (e.g. a wireless access point or DSL modem/ router) and which cannot easily be replaced, upgraded or modified by the user. Second, there are peripheral interfaces like PCI cards and USB devices that can easily be replaced, upgraded or modified by the user. Both device classes contain firmware that is responsible for ensuring that authorized systems are allowed to connect to each other and for routing information between such connected systems. This software generally runs within the kernel of an operating system and has privileged access (akin to “superuser” or “admin” rights) to the system that hosts it, meaning that it has the potential to access all data and/or hardware regardless of whether or not that data and hardware are related to wireless communications. From this, it is obvious that any vulnerabilities in the firmware may lead to the exposure of sensitive data or allow the execution of arbitrary code at an escalated privilege level. It is possible for an external agent to exploit vulnerabilities within a wireless system. This could allow eavesdropping of sensitive data, denial of service attacks, redirection of communications to locations containing malware and/or viruses, man-in-the-middle attacks, etc. In fact, a quick Internet search will show that orga-

network packets allowing remote code execution with kernel privileges and local information disclosure. While many, if not all, of the identified vulnerabilities may be eliminated from future code releases, it is common that many of the deployed systems do not benefit from this work via updates. PC drivers are generally updated as part of the rollout of routine security updates, at least within the corporate environment. However, embedded devices are often ignored as the updates are often more difficult to apply, and some devices are simply forgotten about.

How Does CERT C Help?

The CERT C guidelines define rules that must be followed to ensure that code does not contain defects that may be indicative of errors and that may in turn give rise to exploitable vulnerabilities. For example, guideline EXP33-C says “Do not reference uninitialized memory,” giving protection against a common programming error often associated with the maintenance of complex code. Consider the following example: int SignOf ( int value ) { int sign; if ( value > 0 ) { sign = 1; } else if ( value < 0 ) { sign = -1; } }

return sign;

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The SignOf() function has a UR dataflow anomaly associated with sign. This means that, under certain conditions (i.e. if value has a value of ‘0’), sign is Undefined before it is Referenced in the return statement. This defect may or may not lead to an error. For example: int MyABS ( int value ) { return ( value * SignOf ( value ) ); }

MyABS() will work exactly as ex-

pected during testing, even though the return value of SignOf() will contain whatever value was in the storage location allocated to sign when it is called (zero multiplied by any integer value is zero). The code is said to be “coincidentally correct” as it works, even though it contains a defect. However, all uses may not be so fortunate:

void Action ( int value ) { if ( -1 == SignOf ( value ) ) { NegativeAction ( ); } else { PostiveAction ( ); } }

The code in Action() is most likely to call PositiveAction() when it is called with a value of ‘0’ (which is likely to be correct), as only a return value of (exactly) ‘-1’ will cause it to do otherwise. It is likely that a latent defect will be present in released code as there is little chance of it causing an error during testing, even if that testing is robust. While compliance with the CERT C guidelines can, in theory, be demonstrated by manual checking, this is not practical for large or complex systems. To that end, tools are available to automate the compliance checking process. Figure 1 shows an example of how the LDRA tool suite reports the dataflow anomaly in the SignOf() function. Automated tool checking for compliance is a cost-effective and efficient method to demonstrate compliance with the requirements of CERT C. Such a demonstration provides evidence to support any claims that are made with respect to the inherent security of a wireless product. Adoption of the guidelines contained within CERT C will significantly reduce the number of vulnerabilities within wireless interfaces. However, these benefits will only be realized if tools that automatically check code for compliance with the standard are available to the developers. CERT launched the Vulnerability Discovery Project, which promotes the use of test tools and techniques, to help ensure that suitable tools are available. The aim is to develop a process that may be used systematically by developers and testers to discover and eliminate all vulnerabilities in software. LDRA. Wirral, UK. + 44 0151 649 9300. [].


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System Integration

for enterprise use, almost always with some enterprise application on a server, and usually as part of a fleet of devices. It is purchased to do a job and is loaded with just that software. Often its power must last from four to twelve hours. For a wearable, battery life is everything. Unlike a laptop that might be used for a few minutes on the go, a wearable is on full time, for a shift, even for a day or more. The situational awareness of the device needs to be exploited to extend battery life. Clearly there is no reason to run a LCD backlight unless someone is looking at it, and it should not be brighter than the ambient conditions warrant. Not only the backlight, but Wi-Fi and WWAN networks are significant power consumers and can be enabled based on the situation—for example when the device location is known based on GPS readings. To get the most out of wearable computers in the enterprise, All versions of a useful wearable computer should make the most of power manenable the mobile worker with applications based on the to extend battery life. Some of these Service Oriented Architecture, and back up those applications agement devices are configured with inertial sensors with device features and an application framework. that will put the device into sleep mode when the arm is down, and will wake it up when it is raised to reading position. A civilian verby Larry Ricci, Eurotech sion of a wearable should be good for a full shift; a mission-specific version might have special batteries for even longer use. earable computers are becoming part of the fabric of enterPersonalization is not just about hardware and hygiene. The device prise application deployment. Today, a large portion of the software must be personalized at the start of use by the application eninformation workforce is “deskless” yet still needs data inter- vironment. There are many personal aspects to a wearable application. change with the enterprise. Such information workers include police, These include allowed access to on-premises systems as well as to celfire, utility linemen, soldiers, medical personnel and construction su- lular networks, which may follow the person, not the device. Wearables pervisors. Separating out the workday into information capture (typi- can be personalized for left or right handedness, language and speech cally pen and ink to paper) and information data entry (key stroking recognition libraries in addition to more familiar things like phone and it into a PC at the office), is monstrously inefficient and prone to error. email directories, contact lists, calendars and the like. This and other As we deploy more and more applications to the deskless worker, information would typically be provided from “the cloud.” we are beginning to see how very different wearable computers are from Security is a related issue. A wearable can be lost or stolen, portable computers like laptops, and we are learning the techniques to and with it confidential data. Biometrics can be built in to enforce deploy these wearables into a robust, Service Oriented Architecture. only authorized access. Also, it should be possible to remotely wipe the memory of any device that has gone unaccounted for. Start with the Device The final and perhaps ultimately most important aspect of wearMobile and wearable devices are very different from laptops. able device personalization is its ability to identify the wearer within soEven a subnotebook or netbook should be best considered a small ciety. Any tool we bring to our person, like a watch, a clipboard or hard desktop PC. Obviously, a wearable device is very different (Figure hat, serves to identify the user as a certain type of individual, a member 1). Even if running similar or the same OS as a laptop, a wearable of certain group. In the future, this will be even truer for a wearable device requires different assumptions at the start. The primary in- computer, and the applications architect needs to be aware of this. put is no longer a keyboard or mouse. The primary input may be a touch screen, but voice, on-screen keyboards, functions buttons and Moving Up the Stack – from Hardware to OS keypads are also used. It is often sensor-based with GPS, ambient There was a time when mobile and wearable devices were based light and inertial sensors as well as biometric and process sensors. on hard-coded, proprietary operating systems, but those days are gone. In the role of host or client, the wearable computer is often a “host” Now devices based on the Microsoft or Linux platform are the norm. in the field, but a “client” back in the office. It may even be part of a But don’t expect full compatibility with existing enterprise applica“mesh” network such as Wi-Fi or Zigbee. It is often location- and situa- tions. On the Microsoft front, XP, Vista, Embedded XP, Windows tion-aware using GPS and the ability to sense movement, lighting levels Embedded Standard, Windows Mobile and Windows CE all present and arm position. It must often be designed for use in hostile locations a different API, and some adaptations and recompiling of existing like a construction site, mine or the battlefield. It is usually purchased applications should be expected. Similarly, as is central to the open

Human/Machine Interfaces

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system integration

Reaching for the Clouds

Wearable computers are the natural partner for cloud computing. As the server room vanishes to the cloud, the desktop can become an appliance, a wearable tool. This is the perfect environment for a Service Oriented Architecture. While this may superficially look like an embedded client/remote server architecture, the fundamentals are different. It is the difference between Embedded and Pervasive computing. A smart embedded computer system is any microprocessorbased device encapsulating basic process knowledge. The consequence of this is IT integration is at best an effort in hindsight and at worst ignored altogether. On the other hand, pervasive computing provides technology and infrastructure enabling the distribution within the enterprise of process knowledge and associated parameters. As a consequence, IT integration becomes a native capability of the system.

Have a Drink of SODA

SODA for Devices is a breakthrough. In the client/server model, devices are slaves displaying and querying data that only a single hosting program controls. Thin client interaction is even more limited: Displays and controls developed for a desktop system are presented, awkwardly, to a mobile worker with a wearable device and no keyboard. However, in the SODA model each device can not only consume data, but it can also source data. For example, consider the

Figure 1 The Zypad Wearable Computer by Eurotech is not a PDA strapped to the wrist; it is a ground-up, location-aware, situation-aware design focused on enterprise applications. ESB or Other SOA Mechanism Services: Industry Standards

Generic Device Service Device Service

OSGi Framework

SOA Binding Framework Enterprise Adapter Service

Application Code Agents: Device and Scenario Specific Logic Device Interface and Protocol Adapters

ECLIPSE - Based Tooling with OSGI Programming Model Support

source business model, virtually all Linux platforms are different. Since enterprise scale applications need lifetimes of a decade or more, the best approach to reduce maintenance may be to code applications in a high-level language like Java or C#. This abstracts the business logic from the hardware. Updates to hardware, device drivers and OS are handled by the JVM (Java) or JIT interpreter (Windows/C#). Of course, if the user of the device plans to migrate his applications, he needs to be sure that his device supplier offers the Java or C# interface to all the I/O on the device that he needs. Various application frameworks are available, from Microsoft and from third parties. For practical applications the question is simpleâ&#x20AC;&#x201D; â&#x20AC;&#x153;What I/O is visible from the application logic?â&#x20AC;? A big part of the Eurotech value-add is that we can include, and maintain, the branded EveryWare Software Framework (ESF) inside any of our products, with all I/O and network features visible to the application environment. Again, OS fragmentations driven by device variation have, in the past, required developers to work with hard-edge tools like compliers, text editors and specialized debuggers. For comprehensive enterprise applications, the trend is to mandate powerful development tools, from the mobile/wearable device up to the cloud. More and more, these tools tend to be Eclipse for the Java/Linux users and Visual Studio of the Microsoft camp. Both are excellent platforms, with plug-in tools and rich third-party support to manage development and maintenance of any scale of enterprise application. The Eclipse foundation offers the Service Oriented Device Architecture (SODA), which defines the key set of architectural constraints for SOA architectures (Figure 2). The Microsoft approach with .NET and the Windows Communication Framework (WCF) is similar and embraces many emerging industry specifications like universal plug and play and wireless plug and play. Most commodity devices today, for example printers, GPS units and so forth, are incorporating into their firmware elements of the industry specifications embraced by .NET.

Device Interfaces: Proprietary and Industry Standards Device

Figure 2 The SODA Stack: This diagram, supplied by IBM under the Creative Commons license, indicates the components needed to achieve SODA in the Eclipse, OSGI environment.

evolution of personal GPS systems. Before the turn of the century, GPS devices were not too smart. They had 8- or 16-bit processors and were hard-coded to give basic latitude and longitude information. Currently, all GPS personal navigators are smart 32-bit systems and can provide graphics and turn-by-turn directions. Development time for these was a fraction of the time required for the hard-coded 16-bit predecessors. Increasingly, more of these personal navigation devices are networked, to get traffic and weather reports, for example. Networks are wide area cellular or FM data sideband, or they may be local Bluetooth for cell phones and car infotainment. Recently, service-oriented devices are appearing for GPS applications. One GPS now provides, as well as consumes, traffic data. It publishes its current location and speed to all users of the same GPS so best routes can be plotted. This demonstrates how perfectly a pervasive computing device can distribute process knowledge (for example traffic reports), within an enterprise as loosely defined as the owners of a specific brand of navigation device. To make SODA work, every connection on the network needs to be able to publish and subscribe to events throughout the system. RTC MAGAZINE JULY 2009


system integration

Figure 3 Ring-mounted barcode scanners and other instruments can connect to, and receive power from, the wearable through a USB cable.

Framework software will provide mechanisms for this via an object broker or enterprise bus. Using a mechanism like this, any device or application anywhere in the network can be messaged with a change that it is interested in. Since the industry is migrating to XML, SOAP, DPWS and other industry standards, networks can be transparent across platform and vendor, subject to security provisions. In an ideal world, users of any smart navigation device would be able to publish their traffic data as a service in exchange for getting other peopleâ&#x20AC;&#x2122;s traffic data to consume as a client or, more likely, to get better routing information published by a powerful computer on the Net and consumed by the personal networked device as a service. This service might or might not be offered by the device supplier.

The Wearable Is the Ultimate Service Provider

Because a wearable computer is in full-time physical contact with the user, and in personal area network (PAN) range of the userâ&#x20AC;&#x2122;s other tools and devices, it can publish extraordinary levels of data as a service. For example, one OEM offers a wearable biomedical sensor shrunk to a patch. Connected by Bluetooth to a wearable computer, the patch can report the state of health of the wearer to anyone on the Net. The patch might be on a patient and a wearable computer by


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Eurotech, called the Zypad, might be on a nurse, or might be on the EMT working in an ambulance. Or, alternately, such a patch might be on the same soldier or fireman who is wearing the Zypad. Collecting and publishing the vital signs without intervention and with no data collection/transcription errors could be important to many parties, including the attending physician, the health insurance company or the trauma center where the ambulance is headed. Collecting and publishing vital sign data of a soldier in combat or a fireman in a burning building could direct life or death actions of their brigade or platoon. The wearable often becomes a hub for other devices in the PAN space. Typically these devices are basic tools. Devices with their own power, like a belt-worn printer, tend to use Bluetooth for the PAN. Devices that need power, like an RFID reader or the Eurotech barcode Ring scanner, tend to use a USB connect for both data and power (Figure 3). The networks for these connections can be power-aware, faulttolerant and ubiquitous. Wi-Fi, 3G, Bluetooth and Zigbee all have different profiles of energy use and should be selectively used by the application according to availability and task. In some situations, such as the deployed military platoon, an access point on a vehicle might be eliminated by hostile action, and the units might have to reconfigure to a mesh network. Ideally, all of this logic should be supported by the application framework, between the business logic of the application and the hardware/OS level. Service Oriented Device Architecture is coming for wearable and most other forms of embedded computing. Hard-coded 16-bit solutions are just too costly to implement and maintain. The detailed plumbing of the user interface and sensor data is all local to the device, and does not need to be known by remote information providers and information consumers. With modern, 32-bit software frameworks, wearable computers can achieve this open-ended application extendibility at low development and low maintenance cost, and do it in perfect synchronization to the emergence of cloud-based application architectures. Eurotech. Columbia, MD. (301) 490-4007. [].

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Multicore Processing

The Good News and the Bad News: Your New Chip Has Multiple Cores The embedded software engineer faces some major issues when trying to move to a multicore device, and fortunately some new RTOS technologies are available to help. by Arun Subbarao, LynuxWorks


or the embedded software devel- of threads, and communication between oper, the traditional world has used threads running on the different cores. In a single processor core for the main addition to looking at the issues faced in an control software and a real-time operat- SMP system, it is worth looking at some of ing system (RTOS) to separate the con- the benefits in system design when using trol functions. As more software has been a multicore system. Some of these benefits added, and more performance is required, can be realized by using software virtuala faster processor has been used, with the ization and embedded hypervisors. This, increase in processor speed typically be- then, introduces the new concept of runing able to match the increase in software. ning not just multiple applications, but mulnies providing solutionsworld, now more performance often tiple (possibly different) operating systems In today’s ion into products, technologies and companies. Whether your goal is to research thesame latest hardware, allowing for potenequates to more cores, and so the embed- on the ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you tial consolidation of traditionally separate ded software developer now has to figure you require for whatever type of technology, systems onto a single multicore platform. to take and productsout you how are searching for. his uniprocessor system and spread it across multiple cores to get his performance gains. SMP in the RTOS For multicore devices that offer the In multicore computing, the funcsame CPU architectures for each core, a tions performed by the operating system symmetric multi-processing (SMP) RTOS become layered and more complex. The can be used to spread applications and operating system design must be capable processes across the cores. However, there of handling the complex concurrency isare still issues that need to be considered, sues that arise with multicore architecsuch as system initialization, concurrency tures. Some of the generic areas of OS in both the cache and memory, scheduling design that are affected by the presence of multiple cores are concurrency control, interrupt handling and scheduling. Get Connected Concurrency in a multicore environwith companies mentioned in this article. ment is a key enabler of better

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mance. The RTOS provides primitives that allow multiple threads of execution to protect shared data while executing on multicore processors. Depending on the extent of concurrency control, the RTOS can provide better or worse utilization of multiple cores. The scheduling algorithms play a key part in harnessing the power of multiple cores. Typical scheduling algorithms maintain a per-CPU queue of threads that are ready to run and allocate CPU time based on this queue. However, in a real-time system it is critical to preserve real-time determinism so the scheduling approach is different. The scheduling happens on a global basis where the highest priority thread runs on the first available CPU. However, this may lead to higher levels of cache misses. This can be addressed by using design optimizations in real-time thread scheduling. One such design optimization, known as processor affinity, may allow applications to request an “affinity” to a processor core. In this case, the operating system schedules the applications on the preferred processor core, as long as it does

Create Your Own PMCs Custom I/O as Easy as 1, 2, 3!

Thee Te Th Tech Technobox chno ch nobo no boxx Mi bo Micr Micro cro cr o Me Mezz Mezzanine zzan zz anin an ine in e Sy Syst System stem st emTM iiss based base ba sedd on a simple se ssim impl im plee idea pl idea – provide ppro rovi ro vide vi de embedded emb emb mbed edde ed dedd systems de syst sy stem st emss designers em desi de sign si gner gn erss with er with a foundation for innovation and flexibility. Provide a highly-granular, modular architecture featuring a range of configurable FPGA-based FPGA based carrier boards and an extensive variety of micro mezzanine Electrical Conversion Modules (ECMs) that can be assembled in thousands of combinations. Provide an environment in which a designer can create an array of unique, future-proofed, board-level solutions. But without the costs normally associated with custom board development and manufacture, while speeding development and reducing time to market. It’s the logical next step in mezzanine systems.


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JULY 2009 RTC MAGAZINE 6/12/09 10:11:16 AM

Hardware (multicore CPU)

Figure 1 An embedded hypervisor presents virtualized hardware to different guest operating systems on a multicore CPU.

not affect overall system scheduling. A more rigid form of processor affinity is processor binding, where the task is always scheduled on the same processor core. However, this approach in RTOSs may lead to priority inversions. Operating system design should accommodate considerations such as processor affinity without degrading real-time determinism and responsiveness. In the context of a real-time operating system, other key factors such as priority scheduling and interrupt latency should be preserved in multicore architectures as well. An SMP-enabled real-time operating system must schedule tasks dynamically and transparently between processors to efficiently balance workloads using available processors. It optimizes the support of load-balancing on multiple cores along with preserving the key elements of realtime latency and determinism.

Optimizing Applications for Multicore

Applications written for uniprocessor execution are not necessarily optimized for multicore architectures. Any inherent contention for resources that prevents execution parallelism may result in performance bottlenecks in multicore environments. Application parallelism is dependent on the ratio of computation to communi-

cation overhead. The computation is the amount of time the CPU spends executing application code. The communication overhead is the amount of time that the OS spends in communicating between cores. In a typical multicore architecture, the communication overhead indicates how often messages are sent between different cores. The more threads an application has, the higher the chances that they are scheduled on different cores, which in turn increases the communication overhead. There are two types of application parallelism that can be identified. Coarsegrained parallelism is characterized by large tasks, single threading and low communication overhead. In this case, the ratio of computation to communication overhead is high. This indicates that the communication overhead is lower than computation time, thereby yielding better multicore performance. Fine-grained parallelism is characterized by small tasks, multithreading and high communication overhead. In this case, the ratio of computation to communication overhead is low, which indicates that the communication overhead is higher than computation time, thereby yielding lower multicore performance. In addition, applications that are CPUbound can exploit the full power of multicore architectures since they are coarse-grained, while memory-bound or I/O-bound fine


grained applications may need to be optimized to avoid the bottlenecks that arise due to the communication overhead in symmetric multiprocessing architectures. When looking at applications on multicore solutions, embedded developers must determine the allocation of functions within applications and redesign their applications to exploit parallelism. Developers must consider the design trade-offs of using multithreading versus non-multithreading to harness the power of multiple processor cores. In some instances, applications may perform better on a single core system.

Hardware Virtualization and Hypervisors

Hardware virtualization involves the emulation of the underlying hardware capabilities to allow operating systems themselves to run in a hardware environment different from their original environment. The software programs that emulate the underlying hardware capabilities are called hypervisors. A hypervisor abstracts the capabilities of hardware and allows multiple heterogeneous operating system instances to run on a single hardware platform. There are two main types of hypervisors. The Type 1, or native hypervisor runs directly on the hardware and has complete control of the platform. This type of hypervisor is more prevalent in embedded systems. The Type 2, or hosted hypervisor runs on a host operating system and is dependent on the host operating system for control of the hardware. Virtualizing multiple instances of an operating system can be done using either full virtualization or partial virtualization. In either case, the virtual machine virtualizes the hardware to provide the illusion of real hardware for the operating systems executing on this virtual machine. However, both full and partial virtualizations have some key differences in their overall architecture, leading to a different set of trade-offs. Full virtualization of the underlying hardware requires virtualizing all the capabilities of the processor and board. This involves complex manipulations of memory management and privilege levels that are computation-intensive on commodity processors. This leads to performance

overheads that are much higher than the non-virtualized versions of the OS. The biggest benefit of full virtualization is that it allows operating systems to run unmodified, although at the cost of a significant performance overhead. Partial or para-virtualization is usually a technique where the underlying hardware is not completely simulated in software. This architecture allows commodity operating systems to be easily virtualized on commodity processors, with the requirement that the virtualized operating system have code modifications to adhere to the partially virtualized architecture. The advantage is that the performance of partially virtualized architectures is much better than the fully virtualized machines, usually within a few percent of the non-virtualized versions The emergence of the Type 1embedded hypervisor brings an exciting new dimension to the world of multicore processors, and the promise of superior utilization of processor resources. The ability of the embedded hypervisor to completely control the platform resources allows symmetric and asymmetric multiprocessing to be supported by the hypervisor. In the SMP-enabled hypervisor, a single copy of the hypervisor can allow a single guest operating system to utilize multiple cores. The same hypervisor can enable AMP by allocating a single guest operating system to a unique core. This can be extended to allow AMP and SMP on the same platform through judicious allocation of guest operating systems on single or multiple cores, thereby increasing processor utilization significantly (Figure 1). The migration of software from single core to a multicore system is not straightforward, as there are no automated processes to help configure and partition the applications across cores. However, using SMP operating systems can help not only smooth this transition, but actually offer some real benefits when combined with embedded hypervisor technology, giving opportunities to run multiple guest operating systems and applications across the multiple cores. LynuxWorks. San Jose, CA. (408) 979-3900. [].

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products &

TECHNOLOGY High-Speed PCI Express Digital I/O Board with Flexible Features

A new PCI Express high-speed digital I/O card offers 32 channels of bi-directional parallel I/O lines with a data throughput of up to 200 Mbytes/s and a clock rate up to 50 MHz from an internal timer or 100 MHz from an external clock. The PCIe-7350 from Adlink Technology offers a high-throughput architecture with very flexible acquisition/generation timing and triggering features—making it an ideal solution for high-speed digital pattern acquisition and generation for use in ATE, IC testing, image sensor testing and video image recording/playback. The PCIe-7350 is based on the PCI Express interface (x1 lane), supports a selectable input/output direction per group of eight bits, and provides eight channels of auxiliary programmable I/O. An onboard FPGA provides additional I/O features such as triggers, clock signals, handshaking lines, and I2C and SPI control interfaces. These onboard interfaces enable the PCIe-7350 to communicate with external image sensors via I2C and SPI, without the need for an external control interface. The PCIe-7350 supports selectable software voltage levels of 1.8, 2.5 and 3.3V (5V compatible), which provides the flexibility of interfacing with a variety of ASICs or external devices. The PCIe-7350 also supports a 16-step phase shift feature to ensure accurate sampling timing and prevent invalid timing issues during data transition. The PCIe-7350 is priced at $1,699.

Modular Rackmount/Desktop Enclosure in 51 Different Sizes

The new Type 15 StyleBox enclosure from Elma Electronic offers more colors, a new handle assembly, 51 different sizes, and a flexible design allowing it to convert to a portable tower. The new handle design comes in three parts—a top and bottom that attach to the enclosure, and a centerpiece. The centerpiece is offered in any heights from 1U to 7U, providing flexibility without special tooling. The handle pieces are also available in white, silver, or custom colors, and they can be mixed-and-matched to provide even more color combinations.

ADLINK Technology, San Jose, CA. (408) 360-0200. [].

Quad Channel ADC FMC Card for Rugged DSP Applications

A new quad channel 1.5 GSample/s 8-bit, analog-todigital converter (ADC) card is able to support up to 1,500 MSample/s data throughput per channel. Designed for use in demanding direct RF down-conversion, SigInt/Surveillance, Satellite communications and SDR applications, the ADC513 from Curtiss-Wright Controls Embedded Computing speeds and simplifies the integration of FPGAs into embedded system design by providing highbandwidth I/O direct to the host card’s FPGAs. The module eliminates data bottlenecks to increase DSP subsystem performance by routing high-speed ADC I/O directly to the host board’s FPGAs via the FMC connector. Available in both air-cooled and conduction-cooled rugged versions, the ADC513 has two onboard National Semiconductor ADC08D1520 ADC devices. Each of the module’s four ADC channels supports a sampling rate up 1500 MSample/s. By routing the ADC device interfaces directly to the FMC connector, the ADC513 enables an FPGA on the host board to directly control and receive data. The ADC513 supports an external sample clock input for all ADC channels. Input and output triggers are provided, enabling the number of input channels to be increased by synchronizing multiple ADC513 modules. Curtiss-Wright Controls provides HDL example code for the ADC513 to simplify and speed integration into the HDL development suite for Curtiss-Wright FPGA host boards, such as the FPE650 (Quad FPGA VPX), HPE720 (MPC8641D/dual FPGA VPX) and FPE320 (3U FPGA VPX). Pricing starts at $8,300. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (613) 254-5112. [].



The standard sizes of the new Type 15 enclosure range from 2U to 7U high and widths of 42 HP, 63 HP and 84 HP. With depths in 245 mm, 305 mm, 395 mm, or 500 mm, there is a large range of possible size configurations. Customization is also available. The front of the enclosures can also optionally be recessed by 60 mm with reduction kits. This provides space for protecting electrical or optical connectors and can be provided with or without a perforated air-intake panel or a solid panel. Other features of the Type 15 include a push-on extrusion that saves manufacturing and assembly steps, and hole locations allowing the unit to have mounting feet and a top handle installed. Rotated by 90 degrees and with feet/handle installed, the enclosure becomes a portable tower. The enclosure configurations include 19” rackmount with/without handles, desktop with/without handles, portable case (horizontal orientation) and portable tower (vertical orientation). Pricing is under $200 in volume depending on size and configuration. Elma Electronic, (510) 683-8427. [].


High-Speed, High-Density, Battery-Free Non-Volatile RAM System

A high-speed, high-density non-volatile RAM system delivers densities between 4 megabytes (32 megabits) and 2 gigabytes (16 gigabits) and peak transfer rates equivalent to DRAMs. The AgigaRAM from AgigA Tech is suitable for a wide range of systems, including storage, networking, communications, industrial computing and controls, medical equipment, gaming systems, ATMs and point-of-sale terminals, printers, scanners, copiers, automotive and military systems. Complementing the nvSRAM offerings from parent company Cypress, the AgigaRAM system scales and extends non-volatile solutions to much higher densities. The next best high-density alternative, battery-backed memories, can offer high speeds but are subject to numerous problems, such as hazardous material issues, increased design complexity, long charge times, limited operating life and a high total cost of ownership. The AgigaRAM system solves these problems with use of a battery-free power subsystem teamed with high-speed synchronous DRAM, NAND Flash, intelligent power management and a proprietary system controller. During normal operation the AgigaRAM functions exactly like a synchronous DRAM (SDRAM). When power is lost, however, it automatically saves the data to NAND Flash using the energy stored in the power subsystem. When power is restored, the data is transferred back into the SDRAM. This functionality can be used for power interruption/loss immunity, instant-on recovery, write caching and posting, data logging and journaling, and service and maintenance processing. AgigA Tech announced two product families: Bali and Capri. The Bali product, targeted at general-purpose, embedded and industrial applications, features 4 Mbyte to 64 Mbyte densities and high-speed 100 MHz SDRAM with 200 Mbyte/s peak transfers. It includes an I2C command/control bus and uses 3.3V VCC for 4 Mbytes to 32 Mbytes, 5.0V VCC for 64 Mbyte capacities. The Capri Product is targeted at higher-end storage, industrial, networking and communications applications. This product comes in sizes ranging from 256 Mbytes to 2 Gbytes and uses a much higher speed DDR-800 interface. It also integrates a battery-free power pack. Future versions will extend these sizes even further. AgigA Tech, Poway, CA. (858) 375-4530. [].

Embeddable Antenna Now Available for MICS Band

A compact, embeddable antenna is now available in the Medical Implant Communication Service (MICS) frequency band. The antenna from Antenna Factor is centered at 403 MHz and designed to cover from 402-405 MHz, making it well suited for MICS as well as a wide variety of general RF applications. By utilizing a proprietary grounded-line technique, the “Splatch” achieves excellent performance in a compact surface mount package. Unlike many compact antennas, the Splatch exhibits good stability in proximity to objects and persons. The antenna is RoHS-compliant and designed for hand or automated assembly. It measures 1.1”L x 0.5”W x 0.062”H, exhibits a 50-ohm characteristic impedance, and has a typical VSWR of less than 1.9. The antenna costs less than $1.00 in Get Connected with technology and volume. companies providing solutions now

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Antenna Factor, Merlin, OR (541)Get 471-6256. []. Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Multifunction Boards Offer Options Get Connected will help you connect with the companies and products on Resolution and you areSpeed searching for.

A series of PCI Express-compliant multifunction boards features 16 single-ended or 8 differential channels of analog input, 1 analog output and 4 TTL-level channels of both digital input and output. An 8/16 channel multiplexer Get Connected with technology and companies prov is available to double the GetavailConnected is a new resource for further exploration into pro able analog inputs. The “E” Series from datasheet from a company, speak directly with an Application Engine Contec offers 16M data input memory in touchbuffer with the right resource. Whichever level of service you requir Get Connected will helpindeyou connect with the companies and produc allowing background sampling—conducted pendently from the operation status of the Host PC or its software—to be performed for a variety of trigger conditions. There are four different models, providing a choice of resolution (12 or 16 bit) and conversion speed (10 µsec/ch or 1 µsec/ch). In addition, Contec offers a variety of optional signal conditioners that allow for the expansion of the boards’ functions. Available options include simultaneous sample and hold, cold-junction compensation, gain and low pass filtering. All boards in the Intelligent “E” Series ship with Contec’s data logging software “C-Logger,” which allows the end-user to display recorded data in graphs, save files and to easily import data files into Excel. A driver library is also included, which can be used to create Windows Get Connected within companies and can be used with National /Linux applications. All boards this series products featured in this section. Instruments’ LabView and MatLab by The MathWorks (corresponding driver libraries are available for free download at


CONTEC, Sunnyvale, CA. (408) 400-8700. [].

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5.7-inch Touch Panel Computer Is Fanless

The combination of touch panel technology and the ability of processors to handle sophisticated touch screen graphic interfaces has transformed the notion of what a touch-screen computer terminal can do. Feeding that trend, the Industrial Automation Group of Advantech introduces a lower cost version of their current TPC-66T 5.7-inch QVGA TFT LCD touch panel computer. The TPC-66T-E2BE version comes with 64 colors, 320 x 240 resolution and an Intel low-power-consuming CPU and heat sink to achieve a unique fanless design. The low-voltage processor (Intel XScale PXA270 312 MHz) with an LED backlight is very power efficient, and with its 320 x 240 resolution, it provides a clear display for its compact size. Furthermore, the TPC-66T-E2BE provides multiple standard communication ports (2 x RS-232, 1 x RS-485, 1 x Ethernet, 1 x USB) allowing connectivity with a variety of peripherals. The TPC-66T-E2BE supports Microsoft Windows CE and comes with an NEMA4/IP65 front panel resilient enough to withstand the harsh conditions of any industrial environment.

Compact 5.7” Touch Panel PC for 19” Control Cabinets

A compact touch panel PC is targeted for HMI applications where small mounting space is a challenge. The OTP/57V from SSV Software Systems is supported by a main processor that is fanless and is based on the Vortex86DX SoC by DMP. The processor unites CPU core, North and South Bridge as well as numerous peripheral functions in one single IC. The memory complement consists of 1 Gbyte NAND flash and 128 Mbyte DDR2 DRAM. Available interfaces 1x 10/100 Mbit/s Ethernet, 2x USB host with 480 Mbit/s, 2x RS232, 1x RS-485 as well as 1x CAN.

Advantech, Irvine, CA. (949) 789-7178. [].

Modules Add Wi-Fi and LAN Capability to Embedded Devices

A family of embedded LAN and Wi-Fi modules targets machine-to-machine (M2M) solutions. The Nano Socket iWiFi/LAN modules from Connect One are based on the company’s CO2144 Internet Controller. Nano Socket iWiFi is an 802.11b/g embedded WiFi module with an integrated Wi-Fi antenna. Nano Socket LAN is a 10/100BaseT LAN module with an integrated RJ45 connector. With the Nano Socket family, only a few hours are required to add full-featured Internet access functionality over LAN or Wi-Fi to an embedded device. The logical interface between the host application and the modules is Connect One’s AT+i protocol, a simple text-based API that enables fast and easy implementation of Internet networking and security protocols. The Nano Socket family includes a variety of security features. The modules serve as a communications offload engine and inherent firewall, protecting the embedded device from the Internet attacks. Both modules boast a high level of Internet security and encryption algorithms (AES-128/256, SHA-128/192/256, 3DES, SSL3/TLS1 protocol for a secure client socket session), for complete, end-to-end encryption support. The Nano Socket iWiFi also includes the latest WLAN encryption schemes (64/128-bit WEP, WPA/WPA2 enterprise). Both modules share the same simple header-based pinout, allowing customers reduced assembly costs and increased flexibility when designing solutions. A single product design can easily accommodate both LAN and Wi-Fi. The Nano Socket family eases development by including USB, SPI, USART and RMII interfaces. The Nano Socket LAN operates at an industrial temperature range of -40° to 85°C (-40° to 185°F) and is RoHS-compliant. Nano SocketLAN is available now and is priced at under $25 for large volume customers. Evaluation can be done using an II-EVB-363MS evaluation board ($160). Connect One, San Jose, CA. (408) 572-5675. [].



The OTP/57V is equipped with a 5.7” TFT color screen with touch function. The integrated XGI VOLARI-Z9s LCD controller with 64 Mbyte DDR2 video DRAM in addition with a display resolution of 640 x 480 pixels and a brilliance of 400 cd/m2 ensure brilliant data visualization and a very high image quality. The rugged front (IP65) facilitates a quick mounting in 19” control cabinets with three height units (3 HE). The preinstalled Embedded Linux, X-Server as well as the original Sun Java runtime Environment (J2SE JRT) with Swing support make the system an open and high-performance HMI platform, which enables you to respond flexibly to changing requirements anytime. SSV Software Systems, Hanover, Germany. +49 (511) 40 00 042. [].


ESMini Minimizes Space and Power Demands for Compact and Mobile Systems

The smallest available form factor ESMexpress modules are the new ultra-compact MM1 ESMini boards from Men Micro. Only 95 mm x 55 mm, they integrate first-generation Intel Atom processors based on 45nm technology with processor frequencies of 1.1 GHz (Z510) or 1.6 GHz (Z530). Housed in rugged packages, the boards are suitable for use in aggressive designs found in commercial vehicles, railway, avionics, medical engineering and industrial automation applications. The MM1 models consume a maximum of 7 watts for longlasting mobile applications, and feature an operating temperature range of -40° to +85°C in an enclosed housing that provides shock-resistant, vibration-resistant performance and EMC protection. Each module also includes a real-time clock and board management controller with watchdog.

Rugged Triple Gigabit Ethernet Cards

A rugged family of PC/104-Plus Gigabit Ethernet modules is specially designed for the industrial market. Extended temperature versions for -40° up to +75°C are available as well. The Triget Family from MPL consists of highly integrated, flexible and robust PC/104-Plus-compliant Ethernet modules for industrial use. With a single PC/104-Plus module a system can be expanded with up to three Gigabit Ethernet interfaces! By using a PCI-to-PCI Bridge on the module, the Triget requires only one slot on a PC/104-Plus stack. Therefore, the stack still can be expanded with up to three additional PC/104-Plus cards. To match different system requirements, two interface options and two mechanical versions are offered. Choose between RJ45 or 2 mm lockable headers as well as different mechanical sizes. Features include up to three Gigabit LAN controllers while using only one PC/104-Plus slot. Included onboard are status LEDs and RJ45 or 2 mm lockable headers. The boards are capable of 33 MHz /66 MHz PCI operation and support a 5V tolerant 3.3V PCI bus. Versions are optionally available that are rated at -40° up to +75° C MPL-AG, Dättwil, Switzerland. +41 56 483 34 34. [].

MicroTCA Carrier Management Controller Reference Kit Uses Mixed-Signal FPGA If additional cooling beyond the screened operating temperature is needed, the housing can be connected to an external heat dissipation system (conduction) or combined with a heat sink on the top cover for heat dissipation (convection). In moderate application temperatures, the low-power version may also be operated without the frame and cover. Every MM1 ESMini incorporates 512 Kbytes of L2 cache integrated into the Intel Atom processor, complemented by up to 1 Gbyte of directly soldered DDR2 SDRAM main memory for significantly lower power dissipation, reduction in design costs and space-saving design flexibility. Each also supports additional memory, including USB flash memory, on the carrier board to which the module is mounted. Versatile I/O options cover a wide range of capabilities implemented through customized carrier boards to meet specific end-user requirements. These include modern serial I/O connection options such as a PCI Express x1 link, LVDS, SDVO, highdefinition audio, SATA and USB as well as legacy I/O interfaces, including CAN, COM, Fast Ethernet and I2C, and up to 120 general-purpose I/Os (GPIO). All MM1 modules are equipped with rugged industry-proven connectors supporting high frequency and differential signal connections. All components are soldered in place to withstand shock up to 15g/11 ms and vibration up to 1g/10 Hz to 150 Hz (sinusoidal). The boards are also optimized for conformal coating. A compatible carrier board is available for application development and thorough testing of all module functions. Single quantity pricing starts at $497. MEN Micro, Ambler, PA. (215) 542-9575. [].

A new MicroTCA Carrier Management Controller (MCMC) Board Management Reference (BMR) Starter Kit is based on Actel’s Fusion mixed-signal FPGA. The starter kit from Actel subsidiary Pigeon Point Systems delivers a solution for the mandatory management controllers used in MicroTCACarrier Hub (MCH) modules, including the Carrier Manager and Shelf Manager functions. The kit accelerates a customer’s design cycle and enables designers to concentrate on differentiating their MCH products instead of using internal effort to meet management requirements for specification compliance and interoperability. In addition to the MCMC functionality, the ARM Cortex-M1 processor in the Fusion mixed-signal FPGA hosts the Pigeon Point µCarrier Manager and µShelf Manager components to enable cost-effective and compact management of an entire MicroTCA shelf. The Fusion FPGA-based MCMC integrates significant functionality that would need to be implemented as external devices in an MCMC based on a traditional microcontroller, saving substantial billof-materials (BOM) cost and reducing footprint. The kit includes schematics for a complete MCMC subsystem ready for integration into an MCH design along with a customer-adaptable design for the Fusion FPGA that serves as the core of that subsystem. Bench top MCMC and supporting hardware enables an immediate ramp up on MicroTCA’s IPMI-based management framework, without waiting for custom hardware. In addition, corresponding firmware is delivered in source code form. Pigeon Point Systems, Scotts Valley, CA. (831) 438-1565. []. RTC MAGAZINE JULY 2009



AdvancedMC Board Offers 64 Core TILEPro64 Processor

An AdvancedMC platform based on the Tilera TILEPro64 processor offers 64 cores of generalpurpose and signal processing compute power coupled with over 20 Gbits/s of full-duplex I/O. The TPM-100 PrAMC from JumpGen offers new levels of performance enabled by the new TILEPro64 processor design features and the Tilera Multicore Development Environment (MDE) version 2.0. The single-wide TPM-100 is the latest JumpGen PrAMC platform that supports 10 Gbit/s Ethernet interfaces to address growing market requirements for IP networks. The TPM-100 and T6M-100 AMCs provide equipment manufacturers with options to dramatically reduce time-to-market and fulfill the growing demand for packet processing in converged, content-aware IP networks that process data, voice and video. The board’s dual 10 Gbit/s Ethernet interfaces and 64 processor cores make it ideal for hosting high-bandwidth embedded communication applications such as wireless radio network controllers (RNCs), multimedia gateways, media transcoders/transraters, session border controllers, modular servers, firewalls and deep-packet inspection appliances. Application development on the TPM-100 is supported by the Tilera Multicore Development Environment (MDE) version 2.0. MDE 2.0 includes new features like Zero Overhead Linux (ZOL), which enables dataplane applications to run on Linux while avoiding all of Linux’s overhead; and Bare Metal Environment (BME), which is suitable for RTOS porting and low-level dataplane applications. The MDE also offers an integrated set of tools and libraries that brings simplicity to multicore programming and helps programmers harness the full potential of their processors. It also provides full support for C/C++, standard programming paradigms, and the most advanced multicore debugging and optimization tools. TPM-100 features include the TILEPro64 processor with 64 cores running at 700 MHz, 2 Gbytes of ECC DDR2 memory running at 800 MHz, and up to 8 Gbytes of persistent memory in the form of a solid-state drive. The front panel offers dual 10GigE interfaces (AMC.2 Type 6 or AMC.2 Type 5 with 10 Gbit/s SFP+) as well as an RS-232 Serial and an optional SFP+ for 10 Gbit/s fiber connection. The board is available in both full and mid-size AMC configurations for AdvancedTCA (ATCA), MicroTCA and proprietary architecture systems, and is RoHS-compliant. In addition, a complete set of tools and runtime software stack is provided by the Tilera Multicore Development Environment version 2.0. JumpGen Systems, Carlsbad, CA. 760-931-7800. [].

2-Channel, MIL-STD-1553, Bus Interface Boards for UEI’s Cube and RACKtangle Family

A set of DNA/DNR-1553-553 two-channel, dual redundant, 1553 bus interface boards provides two independent, dual redundant bus interfaces for 1553 communication. The DNA version is compatible with UEI PowerDNA and UEIPAC “Cubes” while the DNR version is designed for use in UEI’s twelve and six slot RACKtangle chassis. Each port may be independently configured as a Bus Controller (BC), Remote Terminal (RT), or Bus Monitor (BM). Designed to function in harsh environments, the DNA/DNR-1553-553 is fully tested for operation from -40° to +85°C, 0 to 70,000 ft. and can withstand 5g vibration and up to 50g shock. Pricing for the DNA-1553-553 is $5,500 and for the DNR-1553-553 it is $5,650. United Electronic Industries, Walpole, MA. (508) 921-4557. [].



USB Serial Converter for Immediate Updates to Legacy RS-232 without Layout Changes

A fully integrated, USB-powered, USB2.0-to-RS-232 adapter, packaged in a DB-9 form factor shell, is designed to add a USB interface to legacy serial products without hardware or software redesign requirements. The CE-USB from Saelig is suitable for use in embedded devices and systems, security systems, cable boxes, test equipment and other electronics applications where use of an RS232 device is specified or in use.

The CE-USB simplifies legacy updates by replacing an industry-standard right-angle PCB-mount DB9 connector with a near-identical part, with the mechanical specifications of an AMP 745131-1. It uses the DB-9’s same PCB pad pinout to allow immediate updates to older serial products without layout changes, while drawing no additional power from the embedded system, and just 35 mA from the USB port. Drivers are supplied for all major operating systems, including Windows, MacIntosh and Linux. CE-USB’s device drivers allow it to appear to an operating system as an additional COM port and send 8-bit asynchronous serial data at selectable speeds between 300 and 921.6 Kbits/s. PC application software accesses the device as it would a physical COM port. Existing COM port applications can thus be used to transfer data via a PC’s USB port, with zero software changes. Pricing starts at just $25.99. Saelig, Pittsford, NY. (585) 385-1750. [].


Interoperable 3U VPX FPGA and SBC Modules Boast Rugged Platform

A flexible, multi-card 3U VPX solution for rugged deployed embedded FPGA processing applications delivers a high level of flexibility for addressing high-performance 3U VPX systems applications. CurtissWright Controls Embedded Computing is announcing the interoperability of its 3U VPX FPE320 FPGA processor card, 3U VPX VPX3-450 FPGA processor and 3U VPX VPX3-127 single board computer (SBC) running Wind River’s VxWorks.

Using this solution, system integrators can now utilize the largest Xilinx Virtex-5 FPGAs currently available in a small form factor embedded system powered with a Power Architecture general-purpose processor. The FPE320 supports Virtex-5 LXT, SXT, or FXT devices. With its onboard FMC expansion site (FPGA Mezzanine Card: ANSI/VITA 57), the FPE320 supports optimized FPGA I/O using Curtiss-Wright’s broad range of FMC ADC51x series cards to bring in high-speed I/O such as analog to digital converters (ADCs). The VPX3-450 FPGA processor combines the computing power of a Xilinx Virtex-5 FPGA with the high-performance floating-point capabilities of the Freescale 8640D dual-core Power Architecture processor. The VPX3-127 features a Freescale MPD8640D processor and can be expanded via its onboard PMC/XMC expansion site. The VPX3-127 uses PCI Express to connect to the FPE320 and/or to the VX. All three boards are available in a combined development chassis that includes FPE320 and/or VPX3-450 cards and a VPX3-127 card. Systems designers can use the platform for prototyping before addressing extended temperature convection- and conductioncooled systems. The FPE320 is a 3U VPX FPGA processor board that incorporates the largest Xilinx Virtex-5 FPGAs available with an FMC mezzanine site. Providing a large amount of resources in a small, rugged form factor, the FPE320 is a suitable FPGA platform for 3U systems that need to acquire analog and other high-speed I/O or need a large FPGA processor. The VPX3-450 is a 3U VPX FPGA processor board that also incorporates Xilinx Virtex-5 FPGAs with an onboard PMC/XMC mezzanine site. With large DDR2 SDRAM and fast QDR-II+ SRAM blocks, and several onboard and off-board high-speed serial links, the VXP3-450 FPGA node provides a balanced mix of processing capabilities with memory, interFPGA and off-board bandwidths. The 3U VPX VPX3-127 single board computer combines the performance and the advanced I/O capabilities of Freescale’s MPD8640D Power Architecture processor with an extensive I/O complement to provide a highly capable processing platform for a wide range of embedded military/ aerospace applications. Designed for space, weight and power-constrained applications, the VPX3-127 represents the latest step in the evolution of rugged, high-performance, highly integrated small form factor single board computers. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (613) 254-5112. [ ].

RTC MAGAZINE JULY 2009 Untitled-2 1


7/13/09 11:43:31 AM


Rugged Direct-Spray Enclosure Supports 3U Boards



Phoenix International designs and builds rugged COTS Data Storage Systems that plug and play in any application -- from Multi-Terabyte Fibre Channel RAID and Storage Area Network configurations to plug-in Solid State Disk Drive VME/cPCI Storage Modules.

4FFVTBUXXXQIFOYJOUDPNPSDPOUBDUVTBUtJOGP!QIFOYJOUDPN An AS 9100 / ISO 9001: 2000 CertiďŹ ed Service Disabled Veteran Owned Small Business

As embedded control goes into ever smaller and more mobile applications, designs are sensitive to size, weight, power and cost. With that in mind, SprayCool offers MPE-3U, a 3U form factor of its scalable MPE line of direct-spray rugged enclosures. The MPE-3U weighs in at only 18 lbs, but is rugged enough to provide environmental isolation to both commercial-grade and rugged 3U cards. Building on the legacy of flexibility inherent in all SprayCool enclosures, the MPE-3U allows customers to deploy commercial-grade or legacy electronics in the same enclosure. In the case of electronics cards designed for air or conduction cooling, this translates directly into lower costs and faster development cycles for integrators and their military customers. The MPE-3U enclosure can scale above 7 slots and is designed to meet industry standard designs for 3U VPX, cPCI/cPCIe and VME-64X and proprietary electronics boards, offering significantly more cooling capability per slot (up to 100W) than enclosures using lower capacity cooling technologies such as air or conduction cooling. The operating environment can range from temperatures of -55° to +71°C, and altitudes of up to 55,000 ft, even in unpressurized compartments. SprayCool, Liberty Lake, WA. (509) 232-2600. [].

2U Platform Powered by Intel Core 2 Duo Has Highly Expandable I/O Untitled-2 1

1/21/09 8:35:49 AM

A 2U rackmount platform designed for IDS/IPS, firewall, VPN gateway, load balancing, UTM applications and other network services features modular I/O capabilities and can expand from a basic level of 8 x GbE to 26 x GbE. With the PL-10450 from WIN Enterprises, customers can configure the I/O they require with copper and fiber LAN expansion modules.

Ideal for extreme temperature, shock and vibration environments



Call Toll-Free in the USA: 1-800-808-7837 or 480-483-3777 206 West Julie Drive, Suite 2, Tempe, Arizona 85283

A Leader in Mass Storage Solutions since 1993


Untitled-1 1


6/17/09 9:20:33 AM

The unit features the Intel 3010 express chipset and ICH7R I/O controller, which support an Intel Core 2 Duo/ Pentium Dual CoreLGA775 processor with 533/800/1066 MHz FSB. Support is provided for ECC and non-ECC high-speed DDRII memory with up to 8 Gbytes. One removable 3.5â&#x20AC;? SATA HDD bay and CompactFlash socket are available for system storage. The PL-10450 supports both ECC and none-ECC high-speed DDR2 memory. The networking I/O architecture is based on extensive scalable I/O from todayâ&#x20AC;&#x2122;s mainstream I/O technology: PCI-E x8/x4/x1. The unit supports a maximum of 26 x GbE in both copper or SFP, has a redundant power supply and is RoHS-compliant. The PL-10450 supports DOS 6.22, Windows XP SP2 and Linux Fedora Core 6, 7 and 8. Pricing begins at $1,209. Price includes CPU. Memory and storage are extra. WIN Enterprises, North Andover, MA. (978) 688-2000. [].

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Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.




ACCES I/O Products.................................................................................. 29..................................................................................... ACT/Technico............................................................................................ 20............................................................................... ADLINK Technology America, Inc...............................................................

End of Article Advantech Technologies, Inc...................................................................... 14................................................................................. Products Alphi Technology Corporation..................................................................... 51................................................................................... American Portwell Technology, Inc.............................................................

Get Connected with3.......................................................................................... companies and ARM Techon Get Connected

products featured in this section. with companies mentioned in this article. Birdstep Technology.................................................................................. Elma Bustronic Corp.................................................................................. ELMA Systems Div....................................................................................

Extreme Engineering Solutions, Inc............................................................ Get Connected with companies mentioned in this article. Interface Concept...................................................................................... Get Connected with companies and products featured in this section. Lippert Embedded Computers.................................................................... 31................................................................................... MEN Micro, Inc......................................................................................... Mentor Graphics........................................................................................ 21...................................................................................... Micro/sys, Inc............................................................................................ Moxa Technologies.................................................................................... National Instruments................................................................................. 26.............................................................................................. One Stop Systems..................................................................................... 41........................................................................ Pentair Electronic Packaging...................................................................... 18................................................................................. Pentek, Inc................................................................................................. 9....................................................................................... Phoenix International................................................................................. Pioneer Magnetics...................................................................................12, Red Rapids, Inc......................................................................................... 40........................................................................................... Red Rock Technologies, Inc....................................................................... Rugged SBCs Showcase..........................................................................36,37.............................................................................................................. Technobox................................................................................................ 43................................................................................. TRI-M Systems......................................................................................... 22......................................................................................... Twin Oaks Computing................................................................................ Vector Electronics & Technology, Inc.......................................................... 23................................................................................ VersaLogic Corporation............................................................................. Wind River Systems, Inc............................................................................. 2.................................................................................... WinSystems.............................................................................................. 17............................................................................... Xilinx, Inc.................................................................................................. 13.........................................................................................

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.




Built Tough for Broader Embedded Applications




Intel ® Atom™ processor (Z510P, Z510PT, Z520PT or Z530P) with industrial temperature range Intel ® Embedded Compact Extended Form Factor Intel ®ECX Form Factor


Dual display (LVDS and SDVO)


Multiple USB ports


Low power, fanless & small footprint

Portwell ruggedizes its new PEB-2738 ECX board with the new Intel® Atom™ processors Z510P, Z510PT, Z520PT and Z530P. The power optimized micro-architecture consumes very low power and operates at a wider temperature range. As a result, it creates an even more robust system with fanless configuration. Portwell’s PEB-2738 ECX solutions can be employed in far more embedded applications than those of other suppliers. Applications for the new PEB-2738 include military-grade computers, in-vehicle infotainment systems, outdoor computing systems, industrial automation and control applications and many more.





Intel ® Atom™ processor Z510 or Z530


Intel® Atom™ processor Z510 or Z530


Intel ® ECX form factor


Dual display (VGA and LVDS)


Dual display (VGA and LVDS)


Multiple USB ports


IDE and SD interface for storage

4.02” „

Multiple USB ports



Gigabit Ethernet


Gigabit Ethernet


Low power, fanless and small footprint


PCIe x1 for expansion


Low power, fanless and small footprint





COM Express



Intel ® Atom™ processor Z510 or Z530



Dual display (LVDS and SDVO)



Multiple USB ports SDIO interface for storage Gigabit Ethernet PCIe x1 for expansion


Low power, fanless and ultra compact

„ 2.75”

„ „ 2.75”


„ 3.7” „


Portwell’s extensive product portfolio includes single-board computers, embedded computers, specialty computer platforms, rackmount computers, communication appliances, and human-machine interfaces. We provides both off-the-shelf and versatile custom solutions for applications in the medical equipment, factory automation, retail automation, semiconductor equipment, financial automation, mission critical and network security markets. American Portwell is both an ISO 9001:2000 and ISO 13485:2003 certified company.

Intel® Atom™ processor N270 Mobile Intel® 945GSE express chipset & ICH7-M Multiple USB ports IDE and SATA


Gigabit Ethernet


PCIe x1 and PCI for expansion


Low power, fanless and compact

Portwell 1-877-278-8899

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