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The magazine of record for the embedded computing industry

June 2009

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COMBINING

VISION MOTION SAFETY

Toward a Unified Embedded Module Framework Managing Processor Power with an RTOS Shelf Management in Depth An RTC Group Publication


Embedded Prototyping. SimpliďŹ ed.

Traditional Prototyping Tools

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Get to market faster and reduce development costs with graphical system design, an approach that combines open, graphical software and off-the-shelf hardware to help you quickly iterate on designs and easily implement them on an NI embedded platform. The NI CompactRIO system offers an ideal embedded prototyping platform with a built-in microcontroller, RTOS, programmable FPGA, integrated signal conditioning, and modular I/O, as well as tight integration with intuitive NI LabVIEW software.

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SERVER BLADES: Many Choices for the Right Slot

Cover Photo: Bob Anderson demonstrates the capabilities of the robot affectionately known as the M2, for Mighty Mouse. (Photo by Randy Montoya)

42 10 GigE Switches Provide IP Carrier Class Routing on 6U cPCI, VME and VPX

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44

COM Express Reference Carrier Board is Compatible with New PICMG Design Guide

TABLEOF CONTENTS

RISC Embedded Computing with Rich I/O and Windows CE 6.0

JUNE 2009

Departments

5Editorial COM, Meet Carrier — Not a Speed Dating Scene Insider 6Industry Latest Developments in the Embedded Marketplace

10 42

Small Form Factor Forum Software and I/O Make the Application (or... It’s the I/O Dummy!) Products & Technology Newest Embedded Technology Used by Industry Leaders

Technology in Context

System Integration

COM Modules

Motion Control and Safety

a Unified Framework for 12 Toward Embedded Modules Jonathan Miller and Rick Lehrbaum, Diamond Systems

Framework for Safe Motion Firmware 30AControl Michael Wilk and Michael Barr, Netrino

Solutions Engineering

34Machine Vision Passes the Bucket

Intelligent Power Management

Industry Watch

18

RTOS–The Heart of Good Power Management Lotta Frimanson, IAR Systems

Industry Insight

Ben Dawson, Dalsa

Embedded Data Integrity

Fault Tolerance into Embedded Data Management 40Building Duncan Bates, Birdstep Technology

Managing Small Modules

I C for “Behind-the-Scenes” 24 Using Management 2

Michael Thompson, Pentair/Schroff Serge Zhukov, Pigeon Point Systems

Digital Subscriptions Avaliable at http://rtcmagazine.com/home/subscribe.php RTC MAGAZINE JUNE 2009

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JUNE 2009 Publisher

Embedded Super Power #103:

PRESIDENT John Reardon, johnr@rtcgroup.com EDITORIAL DIRECTOR/ASSOCIATE PUBLISHER Warren Andrews, warrena@rtcgroup.com

Super Cool

Editorial EDITOR-IN-CHIEF Tom Williams, tomw@rtcgroup.com CONTRIBUTING EDITORS Colin McCracken and Paul Rosenfeld MANAGING EDITOR Marina Tringali, marinat@rtcgroup.com COPY EDITOR Rochelle Cohn

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Published by The RTC Group Copyright 2008, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.


EDITORIAL

JUNE 2009

Tom Williams Editor-in-Chief

COM, Meet Carrier —Not a Speed Dating Scene

W

e in the press make a constant practice of covering the newest developments in processor technology and the newest modules that incorporate their functionality, while often neglecting some of the other issues important to successful system design. Now, it is certainly of central importance to follow the advances in processor technology such as the recent developments in low-power 32-bit devices like the Intel Atom and the VIA Nano. These processors have enabled the creation of extremely small processor modules that make possible the extension of very powerful embedded intelligence into ever smaller and more specialized application areas. Among the Atom-based modules that have recently appeared on the market, for example, there appear to be more similarities than differences. True, they are available on different form factors such as COM Express, Pico-ITX, ISM and more. The modules offer alternatives in terms of additional connectivity—that is, in addition to what is provided by the main connectors. They offer such things as onboard solid-state storage options, graphics capabilities and the like. But solving the system design issue of the main processor is mostly a process of window shopping, feature selection and price comparison. The hard part comes after that. As we all know, the job of the CPU is to handle the I/O data by running software. No duh. In the case of ever more diverse embedded applications, that I/O “thingie” can get pretty complicated. It can often involve analog-to-digital and digital-toanalog conversion. It can be targeted toward a host of real-world phenomena such as temperature, rotation speed, acceleration, lumens, color grades, vibration, pH, chemical and gaseous composition, spectral data, volume, and flow rates of liquids. The list goes on. The nature and variety of sensors is growing. Each of these real-world phenomena must be translated into an electronic digital format the processor and software can deal with. Not only that, it must be done efficiently, at low cost, and, in the case of COM modules, in a form that can be sent over the signals supported by the connector. What we seem to have

at present in the COM arena are a lot of processor modules and relatively few carrier I/O modules on the market. That means that the major time and expense in putting together a specialized embedded application needs to focus on getting the I/O right so that it works with the COM module. Oh, yeah—and that little matter of the software. One of the big selling points of COM modules is that they allow an OEM to concentrate on getting the I/O portion of the design right, and when it comes time to upgrade performance or functionality, to simply plug in a more powerful CPU. My spies tell me this is by far not that straightforward. One issue—certainly to be expected—is engineering a specialized I/O module to input data from sensors that is accurate in terms of the CPU. This has been greatly aided by a generation of intelligent sensors that often convert the units they are measuring to standard electrical signals that can be dealt with on the I/O board and by the processor. A somewhat trickier issue is presented by the subtle variations between designs of COM modules—even those that incorporate different versions of the same CPU architecture from the same manufacturer. Matching the electrical characteristics of the COM module and the carrier in terms of power-up times and other variables is something that is apparently more difficult than has been assumed. A connector standard between CPU and carrier card does not always completely isolate either from some of these difficulties, particularly when the CPU is powered by connections coming off the carrier card, which is actually connected to the power supply. Having heard some of these comments from knowledgeable engineers, we at RTC are very interested in finding out more about them and what can be done in design practice to smooth the hoped-for path to easier integration. Are there guidelines that can be established? Are there some additional specifications and/or standards needed? Or does it really just come down to detailed, precise plain old work? You know—engineering. RTC MAGAZINE JUNE 2009

5


INDUSTRY

INSIDER

JUNE 2009

Intel to Acquire Wind River Systems

I

ntel has entered into a definitive agreement to acquire Wind River Systems, under which Intel will acquire all outstanding Wind River common stock for $11.50 per share in cash, or approximately $884 million in the aggregate. As a leading embedded software vendor, Wind River will become part of Intel’s strategy to grow its processor and software presence outside the traditional PC and server market segments into embedded systems and mobile handheld devices. Wind River will become a wholly owned subsidiary of Intel and continue with its current business model. The acquisition will deliver to Intel software capabilities in embedded systems and mobile devices, both important growth areas for the company. “This acquisition will bring us complementary, market-leading software assets and an incredibly talented group of people to help us continue to grow our embedded systems and mobile device capabilities,” said Renee James, Intel vice president and general manager of the company’s Software and Services Group. “Wind River has thousands of customers in a wide range of markets, and now both companies will be better positioned to meet growth opportunities in these areas.” “Our combination of strengths will be of great benefit to Wind River’s existing and future customers,” said Ken Klein, Wind River chairman, president and CEO. “As a wholly owned subsidiary, Wind River will more tightly align its software expertise to Intel’s platforms to speed the pace of progress and software innovation. We remain committed to continuing to provide leading solutions across multiple hardware architectures and delivering the same world-class support to which our customers have grown accustomed.” The implications of the acquisition can be many. The companies state that the new subsidiary will continue to support other architectures, but it would be difficult to imagine that Intel’s mission, which is to sell silicon—namely its own silicon—has changed. The acquisition of Wind River should be regarded in that light. The acquisition brings not only the VxWorks RTOS and a real-time version of Linux under Intel’s roof, but also development tools like the Eclipse-based Workbench tool suite, test management tools and the Tilcon graphics suite. While there have been no indications from Intel, the opportunity certainly exists to gradually move this software arsenal to more Intel-specific purposes such as pricing strategies, support programs and performance-enhancing modifications that can be tied directly to the chip architectures and kept proprietary. This type of move would definitely give Intel an advantage over its x86 competitors AMD and VIA Technologies as well as a weapon to use more generally in competition with other embedded rivals like ARM and Freescale. There have been remarks already that this shows that Intel has “finally discovered the embedded market.” These people have not been paying attention. Intel has for some time had an embedded roadmap with devices specifically aimed at the needs of embedded developers, including guaranteed life cycles. The advent of the low-power Atom family along with 45nm Core Duo processors is targeted at embedded systems and is expected to be followed later this year by a new generation of 32nm devices. Intel didn’t just discover the embedded marked; it has been ruthlessly pursuing it for some time. At the same time, the acquisition of Wind River puts Intel into direct competition with other embedded software vendors, many of whom offer prod-

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ucts targeted at the x86 architecture. One of the more intriguing of these is, of course, Microsoft, which also long ago “discovered” the embedded market. Intel is reportedly making a push into (among other things) the market for Mobile Internet Devices (MIDs), small, handheld multimedia devices with wireless Internet connectivity. There, it apparently wants to dominate with its Atom and follow-on processor families, but now also with the embedded Linux acquired with Wind River. There it runs smack into Microsoft with its Windows Mobile, CE and/or XP Embedded. Since Microsoft doesn’t make silicon, the availability of an integrated mobile hardware/software platform could be a distinct advantage. The same goes for automotive applications, medical devices and a whole range of small applications. Reaction from embedded software vendors has been generally optimistic. John Carbone, VP of marketing for Express Logic said, “I see this as a good deal for just about everyone. It’s good for software vendors in general because it shows that a mega-company like Intel recognized the value of software as a necessary solution to offer customers, and the valuation ($885M) is a good one, given the current state of the market. It benefits Wind River by giving them an inside track to the Intel customer base and Intel sales channels. It benefits Wind River’s competitors by moving Wind River to a perceived Intel-centric role, making them less attractive to companies using Freescale, MIPS, ARM and others. Finally, it’s good for Intel because it gives them a one-stop-shop solution that’s appealing to customers, and positions them ahead of Freescale and their other competitors [e.g.: AMD, as you observed] in this area.” QNX Software was also upbeat. According to CEO Dan Dodge, “Intel’s acquisition of Wind River presents a significant opportunity for QNX Software Systems, as we remain committed to an architecture-agnostic strategy that provides tools, middleware and RTOS technology for ARM, MIPS, Power, SH-4 and x86 platforms.” He went on to note, “Intel and QNX have worked together for more than 20 years, and we will continue to work with them and other silicon vendors to support our multi-platform approach. In fact, QNX fastboot technology for the Intel Atom processor recently won an innovation award from Intel Embedded and Communications Alliance.” Green Hills Software, one of the largest RTOS vendors, appears to be quite optimistic about the acquisition as well. President and CEO Dan O’Dowd stated, “In a few years Green Hills Software will be the only vendor supplying tools and OSs for multiple processor families. Intel has removed a competitor from the board. Its aim is not to provide a convenient way to write software that can be easily migrated to another vendor’s chips. Our business model is to be the vendor you go to when you don’t want to be locked in.” The potential rivalry between Intel and Microsoft for the more consumer end of the market served by OSs like CE and Linux is of less interest to Green Hills. “What we want is the traditional embedded market of industrial control, automation, instrumentation, etc. It’s really hard to imagine a better scenario. Intel will begin to take them (Wind River) out of the ARM, PowerPC, MIPS, etc.” O’Dowd let it be known that he sees an additional advantage. “I bought a million shares of Wind River over the years,” he says, “Every time it went below seven dollars.” by Tom Williams Editor-in-Chief


ZigBee Smart Energy Proposed as Basis for an IEC Standard

In an effort at helping speed the development of the Smart Grid, the ZigBee Alliance, a global ecosystem of companies creating wireless solutions for use in energy management, commercial and consumer applications, has announced it is proposing use of the ZigBee Smart Energy public application profile to the International Electrotechnical Commission (IEC) as a basis for an IEC standard. ZigBee Smart Energy is a standardized home area network solution that meets the requirements of leading utilities worldwide.  The deployment of an estimated 30 million ZigBeeequipped smart meters is underway in North America.  Working with the IEC on an even broader global standardization is expected to benefit the energy sector and public by placing more emphasis on energy management and smart grid development. “The ZigBee Alliance is doing heavy lifting in the industry, offering new possibilities for seamlessly integrating the home area network with the electric system to deliver long-awaited value and functionality as part of a larger smart grid,” said Richard Schomberg, convener of the IEC Smart Grid Strategic Group. Greg Robinson, convener of IEC TC57 Working Group 14, added, “Basing and harmonizing the ZigBee Smart Energy profile on the IEC Common Information Model (CIM) would improve data fidelity and minimize overall life cycle costs for exchanging information among home area networks, metering systems and utility back office systems.” “ZigBee Smart Energy is in wide use today,” said Bob Heile,

chairman of the ZigBee Alliance. “Our goal will be to ensure the highest level of compatibility with all ongoing, and soon to begin, deployments of ZigBee Smart Energy. With its inherent Internet connectivity, use of global wireless frequencies and robust security, ZigBee Smart Energy is in deployment around the world.”

Semiconductors Are Now the Driving Force behind U.S. Energy Efficiency Gains

Semiconductor technologies are so essential to advances in energy efficiency gains that the U.S. economy could expand by more than 70 percent through 2030 and still use 11 percent less electricity than it did in 2008, according to a new study by the nonprofit and independent American Council for an Energy-Efficient Economy (ACEEE). Titled Semiconductor Technologies: The Potential to Revolutionize U.S. Energy Productivity, the new ACEEE report concludes that semiconductors already are the leading factor behind energy efficiency gains. The report states: “Compared to the technologies available in 1976, we estimate that the entire family of semiconductor-enabled technologies generated a net savings of about 775 billion kilowatthours (kWh) of electricity in the year 2006 alone.” Energy solutions that are described as “smart”—from smart buildings to smart appliances to the Smart Grid—have semiconductor sensors to measure temperature or other variables; communications chips to receive and transmit data; memory chips to store the information; and microcontrollers, microprocessors and power management chips to adjust energy loads.  Smart grid technologies also enable a more

cost-effective deployment of decentralized but cleaner renewable energy resources such as solar panels and wind turbines, which are also enabled by semiconductors. Smart grids may also enable plug-in hybrid cars to stretch gasoline dollars, and provide battery storage units for the nation’s electric generation system.  U.S. energy intensity (energy per constant dollar of GDP) declined an average of 1.2 percent annually between 1950 and 1995.  The level of U.S. energy intensity further declined 2.1 percent between 1995 and 2008. A significant portion of these gains appears to be the result of the explosive growth in technologies supported and the related shift in the predominant technological paradigm.   Additionally, huge additional energy efficiency gains will be seen over the next 20 years. The cumulative net electricity bill savings enabled by semiconductors might exceed $1.3 trillion through 2030.  Perhaps not surprising, a more productive economy might also support some 935,000 more jobs while substantially reducing environmental impacts—notably a reduction in energy-related carbon dioxide emissions that would exceed 700 million metric tons, also by 2030.”   The need for 300 more power plants could be eliminated. Smart investments “can facilitate productivity gains that reduce electricity use to only 3,364 billion kWh by 2030. The resulting savings of 1,242 billion kWh in 2030 means that the economy may actually consume 11 percent less electricity than it did in 2008. In other words, semiconductor-related technologies may support an economy in 2020 that is 35 percent larger than today, but one that uses 7 percent less electricity

Fibre Channel over Ethernet (FCoE) Interoperability Validated

The Fibre Channel Industry Association (FCIA), a non-profit international organization of manufacturers, systems integrators and vendors, has announced that it successfully completed its second FCoE Plugfest the week of May 12th at the University of New Hampshire Interoperability Lab (UNH-IOL). Sponsored by the FCIA, leading Fibre Channel vendors worked together to ensure interoperability for the stable FCoE standard. This year’s Plugfest provided a forum for testing the interaction of FCoE end devices with data center bridge exchange (DCBx) switches. Participating companies in the Plugfest included Amphenol, Brocade, Cisco Systems, Finisar, HewlettPackard, Intel, IXIA, Mellanox, Microsoft, NetApp, QLogic, Tyco Electronics and UNH-IOL. Bill Martin, FCoE Plugfest chair and engineer consultant for the Office of Technology at Emulex, volunteered to execute the successful Plugfest event. “Adding Converged Enhanced Ethernet-capable switches in this Plugfest allowed vendors to validate discovery over an FCoE fabric, priority flow control, separation of Ethernet traffic based on priority, and interoperability with other Ethernet traffic in the same environment. This added testing has allowed the industry to move forward toward quick implementation of an interoperable converged network environment,” said Martin. Member companies have already delivered or are in product development and gearing to deliver FCoE solutions over the coming months.

RTC MAGAZINE JUNE 2009

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INDUSTRY INSIDER

Hybrid Locomotives: GE Partners with NY in Facility for New Battery Technology

General Electric has announced that it will open a new, state-of-the-art battery manufacturing plant in upstate New York that will serve as the main manufacturing facility for GE’s newly formed battery business. The initial investment in the factory will be $100 million. It will be located in the Capital Region and will create 350 new manufacturing jobs at GE and thousands more in the supply chain. The announcement coincides with GE’s submission for federal stimulus dollars from the U.S. Department of Energy. GE has invested more than $150 million to develop advanced battery technologies, including a high energy density, sodium-based chemistry battery that will provide energy storage for several future product applications. The first application will be GE’s hybrid locomotive, which will be commercialized in 2010. In addition, GE has launch customers in several industries, including mining, telecommunications and utility, with key applications for heavy service vehicles, backup storage and load leveling for the smart grid. This investment in sodium battery technology complements GE’s investment in A123, a leading supplier of lithium batteries for plug-in electric passenger cars. With these two technologies, GE now leads the world in applications for high power and high energy density storage systems. GE’s planned facility will employ a high wage “green collar” workforce that will produce approximately 10 million cells each year when the facility is at full capacity. That translates to 900 megawatt hours of energy storage, or enough energy storage to power 1,000 U.S. homes for a month, or enough energy to support 1,000 GE hybrid locomotives. The new battery business will be a part of GE Transportation and will serve customers in the rail, marine, mining, telecommunications and utility sectors.

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This battery technology will allow GE to be the first manufacturer to introduce a hybrid, heavy-haul freight locomotive that reduces emissions while improving fuel efficiency, putting GE well ahead of its competition. GE hopes to secure additional federal funding for the new facility later this summer. Applications for Department of Energy funding are due next week. The goal is to have the new manufacturing operation producing batteries by mid-2011

PICMG Forms Technical Committee Focused on Large-Scale Physics Applications

A new PICMG subcommittee has been initiated by an international group of physics labs that are using or actively exploring usage of both AdvancedTCA and MicroTCA platforms in experimental research machines and detectors. These include applications in such diverse fields as high energy, photon, astro, fusion and medical physics. The Committee will tackle AdvancedMC channel usage models, rear transition module definitions, timing synchronization, and the generic design of AdvancedTCA and AdvancedMC modules needed to allow PICMG’s xTCA family of products to be used in the broad physics community. The main goal of the subcommittee is to develop a set of xTCA specifications, sub-specifications, design guides, requirements documents, and other documents while maintaining maximum compatibility with existing xTCA specifications. This subcommittee will serve as a coordinating committee for study of solutions, specific tasks, resources and timelines for a number of closely coupled working groups. “PICMG is very excited about the formation of this subcommittee,” stated Doug Sandy, PICMG vice president of technology. “It proves PICMG’s xTCA family of specifications, including AdvancedTCA, MicroTCA and AdvancedMC, has

application beyond their telecommunications focus. It also shows how open specifications can be enhanced within the PICMG organization to permit broader use of the technologies.” “The physics scientific community was among the first to pioneer interoperable modular instrument standards beginning in the 1960s,” said Ray Larsen of the SLAC National Accelerator Laboratory, chair of the Coordinating Committee. “This special relationship of physics with PICMG aims to create xTCA features to serve the new generation of intelligent, highly available largescale physics systems, along with strong industrial support.”

ZigBee Alliance Plans Further Integration of IP Standards

The ZigBee Alliance has announced it will incorporate global IT standards from the Internet Engineering Task Force (IETF) into its specification portfolio of low-power wireless networking standards. This move will expand the growing portfolio of successful ZigBee specifications and should further advance the rapid growth of Smart Grid applications that have widely adopted the proven ZigBee Smart Energy public application profile. By incorporating IETF standards, ZigBee Smart Energy products will enhance their application capabilities with native IP support, allowing seamless integration of Internet connectivity into each product. ZigBee members will also benefit from the knowledge and experience contained in IETF standards for large-scale network addressability, security and IT integration, further building on existing expertise from developing the world’s leading technologies in the area of reliable, low-cost wireless sensor and control networks. Through cooperative efforts with IETF, ZigBee members will create additional solutions for wireless sensor and control networks as part of the new specification. Internet connectivity is

currently provided by existing ZigBee specifications; however, the addition of native IP support will offer tighter integration from wireless devices all the way to large-scale utility IT networks. The resulting specification will further broaden ZigBee’s suite of low-power wireless network solutions to meet the diversified needs of companies in the home, automation, healthcare, commercial building automation, telecommunications and consumer markets.

IDT to Acquire Tundra Semiconductor

Integrated Device Technology and Tundra Semiconductor have announced the two companies have entered into a definitive acquisition agreement pursuant to which IDT will acquire Tundra for CDN$6.25 per share, for an aggregate purchase price of approximately CDN$120.8 million. “IDT is excited about the proposed acquisition of Tundra. We look forward to better serving our customers by utilizing the Tundra core strengths in serial switching and bridging using PCI Express, RapidIO and VME, with the existing IDT mixed signal product portfolio,” said Dr. Ted Tewksbury, president and CEO at IDT. “We believe the result of this transaction will provide our customers with a broader product offering as well as improved service, support and future roadmap of serial connectivity innovations. This transaction reflects our commitment to extending our technology leadership in the communications end market, which is particularly critical in the current challenging economic environment.” Tundra announced earlier that Gennum notified Tundra that it would not exercise its right under the amended arrangement agreement between Tundra and Gennum to match the IDT offer. As a result, Tundra has paid the CDN$5.0 million termination fee to Gennum and has terminated the Gennum Agreement in accordance with its terms.


SMALL FORM FACTOR

FORUM

Colin McCracken & Paul Rosenfeld

Software and I/O Make the Application (or… It’s the I/O, Dummy!)

T

he pointy-haired boss says the latest multicore CPU is required for the next project, providing you with a reason to come to work tomorrow. Good thing the boss knows how to keep abreast of technology, or where would we be? Now that the CPU choice is settled, the task becomes how to fit that square peg into your application’s round hole. No problem, just start with a 5-vendor COM Express RFQ, and may the cheapest CPU win. 16-bit A/D, kilosamples per second, CAN bus, PoE, ACPI, QVGA, etc. Or ARINC, SSD, DO-160, COM ports, legacy BIOS, … uh oh. Bus, what bus? So begins another round of trying to educate the pointy-haired boss. The fundamental problem here is selecting the CPU first. Conventional wisdom tells us to proceed this way, as does the unwise conventional boss. The ensuing struggle to force-fit the I/O against the grain is our job security. Everybody and their brother makes a CPU, but, even with a schematic, you probably can’t tell them apart. The CPU information needs to be filed away into a project-oriented decision framework. It is critical to understand the I/O requirements, software interactions, latencies, determinism and data bandwidth needs first. Then interconnects and bus structures can be determined. This holds whether designing at the chip level or board level. For example, it’s not wise to triple the gigahertz to solve the determinism problem unless you have a budget that can handle tripling the CPU and thermal solution cost as well. Finally, the CPU and chipset (or all-in-one SoC) can be selected after all the other considerations are put to rest. This, then, is the appropriate time to reach into the archives of the brain and play eenie, meenie, miney, mo with the processor choices. Since each embedded application is unique, and you are the master of your domain, let’s fast forward past your analysis of I/O and interconnect requirements to the last step, the small form factor CPU selection. There are three major classes of processors suitable for embedded developers—desktop/notebook class (32/64-bit), RISC-based and microcontroller (4/8/16-bit). Each occupies its own market space without much overlap in terms of performance, power, cost and real-time response. And usage is driven by the application. Automotive infotainment (telematics) has very different requirements than the 50 or so microcontrollers in the vehicle. Even the

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pointy-haired boss might understand that distinction. Microcontrollers are well suited for white goods like microwaves and dishwashers, car and TV remote controls, sensor networks, alarms, access control, and distributed decentralized dedicated controllers such as automotive applications. In most cases, the firmware and application-specific I/O is all included in a single chip. Typical unit volumes are in the millions, and prices are several dollars. There is nothing inherently difficult about designing custom boards with these devices; even hobbyists and college students can lay out simple boards and compile interesting application code. Microcontroller Linux versions exist. However, trying to extend these processors to applications outside of their comfort zone may mean expensive custom device drivers, and spending more money on connectors than on the processors themselves. RISC processors have moved beyond cell phones and cable modems to digital TV, DVRs, network routers and other headless fixed-purpose devices. The 32-bit processors run TCP/IP network stacks, middleware and larger operating systems like QNX, VxWorks, Nucleus, Integrity and many others. Volumes are typically in the tens and hundreds of thousands, costs are tens of dollars, and like microcontrollers, the ROI for custom designed boards instead of off-the-shelf boards is well established due to the uniqueness of every application and the processor-specific local buses. Intel Architecture and other x86 processors, ColdFire, and some of the high-end almost-CISC-like PowerPC variants comprise the high end. The x86 space in particular has such a standardized architecture that an ecosystem has blossomed. Motherboard form factors like Mini-ITX and modules like COM Express cover the tens- to thousands-per-year volumes with tens to hundreds of dollars for the processor alone. Many of these are 2-chip or 3-chip solutions with 10-100W power dissipation and rich PC-style buses and I/O. Because of their rich graphics support, these processors find themselves in many GUI- and HMI-oriented applications like kiosks, signage, medical instruments and imaging, military, avionics, trains, traffic management, automation and others. Remember, despite the grandstanding, the CPU is only there to run the software and serve the I/O. If this material is beyond your grasp, there may be a management opening nearby. Let us know your pointy-haired boss stories by e-mailing us at sf3@rtcgroup.com.


Technology in

context COM MODULES

Toward a Unified Framework for Embedded Modules Some rather minor modifications to the original PC/104 form factor may not only smooth the path from legacy ISA through PCI to PCI Express data paths in the same system, but also provide a way forward when future interconnect technologies appear. by Jonathan Miller and Rick Lehrbaum, Diamond Systems

I

n April of 2008, the Small Form Factor Special Interest Group (SFF-SIG) unveiled a new modular standard for stackable expansion of single board computers. The SFF-SIG’s new standard, known as the Stackable Unified Module Interconnect Technology (SUMIT), implements a PC/104-like self-stacking bus based on the latest serial bus and interface technologies. SUMIT defines the electrical and mechanical characteristics of a stackable expansion bus for single board computers and expansion modules. SUMIT defines two identical 52-pin connectors (“A” and “B”), which together carry up to 6 lanes of PCI Express, four USB 2.0 ports, ExpressCard support, a low pin count (LPC) parallel bus, SPI.uWire and SMBUS/I2C serial buses, and various power and ground lines. The signals carried on SUMIT’s A and B connectors, according to the soonto-be-released SUMIT Version 1.3 specification, appear in Table 1. The SUMIT specification defines three configuration alternatives based on having one (connector A), the other (connector B), or both the A and B SUMIT connectors present on the host single board computer (SBC). They are designated as follows: • Configuration A — consisting of the SUMIT A connector, only

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• Configuration B — consisting of both the SUMIT A and B connectors • Configuration C — consisting of the SUMIT B connector, only

SUMIT B and A

Combining SUMIT with PC/104

It should be emphasized that the SUMIT specification is independent of any particular form factor. That noted, a separate SFF-SIG draft specification defines a SUMIT-based stackable module format that offers backward compatibility with the PC/104 Consortium’s PC/104 module standard. Initially dubbed “Express104,” the standard

SUMIT-ISM Type 1

104-pin PC/104 (ISA) Bus

Figure 1 SUM IT-ISM Type 1 layout.

SUMIT B and A

120-pin PCI-104 (PCI) Bus

SUMIT-ISM Type 1

SUMIT-ISM Type 2

104-pin PC/104 (ISA) Bus

SUMIT A and B

Figure 2 Comparison of SUMIT-ISM Type 1 and Type 2 footprints, assuming a normal, PC/104-compatible mounting hole pattern.


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technology in context 3.350 3.250

0.200 0.350

0.650

SUMIT Type 2 implemented on the UEMF.

is currently known as “SUMIT-ISM” where “ISM” standards for ”industry standard module.” Basically, SUMIT-ISM features a PC/104-compatible board outline and mounting hole pattern along with SUMIT’s pair of 52-pin connectors (A and B) near the top edge. In addition, the PC/104’s 104-pin connector array is near the bottom edge just as it is in legacy PC/104 modules. The result is a compact, self-stacking, embedded computer module format that supports expansion via SUMIT’s PCI Express and other bus signals, along with PC/104’s ISA bus. SUMIT-ISM thus enables the use

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0.200 0.385

Figure 3

3.575

3.775

Slots .125” diameter hole .250” diameter pod 4 places

0.950

1.993

0.300 0.200

Figure 4

3.200 3.350 3.550

SUMIT Type 2 form factor dimensions.

of “legacy” PC/104 (ISA) expansion modules within SUMIT-based module stacks—a convenient way to include both PCI Express and ISA in a compact, rugged module stack. Additionally, SBCs can

be designed with SUMIT-ISM bus connectors, allowing expansion with a choice of modules based on either the SUMIT bus configurations, a PC/104 (ISA) bus, or a combination of both.

5/7/09 10:31:33 AM


technology in context Figure 1 shows the basic connector, board outline and mounting hole layout of the SFF-SIG’s preliminary SUMIT-ISM module format. For the purposes of this discussion, this version will be designated “SUMIT-ISM Type 1.” While SUMIT-ISM builds a bridge from yesterday’s PC/104 module standard to tomorrow’s PCI Express requirements, it does not directly support modules that interface via the PC/104 Consortium’s 120-pin stackable PCI bus (also known as “PCI-104”). Use of PCI-104 modules in a SUMIT-ISM stack is possible, but it requires the addition of a dedicated PCIeto-PCI adapter card to create the necessary 120-pin PCI bus. Under the assumption that many system developers may prefer to incorporate today’s widely available, high-performance PCI-104 modules and PC/104-Plus modules (with their 104-pin ISA stackthrough connectors removed) in new designs that utilize SUMIT, we are proposing a SUMIT-ISM Type 2 module, which substitutes a PCI-104 (PCI) bus option for SUMIT-ISM’s PC/104 (ISA) bus option. Put simply, SUMIT-ISM Type 2 builds a bridge from today’s PCI-104 (PCI) module standard to tomorrow’s PCI Express requirements. PC/104-sized (or larger) single board computers built with SUMIT-ISM Type 2 can thus be expanded via SUMIT (PCIe etc.) modules, legacy PCI-104 (PCI) modules, or both. Additionally, an adapter module could provide compatibility with legacy PC/104 (ISA) modules.

ISA and PCI-104 PCI, respectively) are located as defined by the PC/104-Plus specification. From the pair of drawings in Figure 2, it can be seen that modules built with only SUMIT A and/or B connectors of these two types could not be combined in a stack, because when either module is rotated by 180 degrees, the mounting holes will not align. To alleviate this incompatibility, and thereby allow SUMIT-ISM Type 1 and

SUMIT A Connector

SUMIT B Connector

One PCIe x1 lane Four USB 2.0

One PCIe x1 lane

ExpressCard

four PCIe x1 lanes

One PCIe x4 or

LPC S PI. uWi re SMB us/I2C

table 1 SUMIT A and B connector utilization.

Introducing the “UEMF”

One interesting “feature” of the original PC/104 specification is its nonsymmetrical mounting hole pattern. Consequently, SUMIT-ISM’s mounting hole pattern (as currently defined) would not be compatible with a version that simply substitutes PCI-104’s 120-pin PCI bus connector for PC/104’s 104-pin ISA bus connector, since on a PC/104-Plus module footprint—which defines the location of these two connectors—the PCI connector is located at the top, while the ISA is located at the bottom. Figure 2 provides a comparison of the mounting hole locations on SUMIT-ISM Type 1 and SUMIT-ISM Type 2 modules, assuming the legacy buses (PC/104 Untitled-7 1

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technology in context Type 2 modules built with only SUMIT A and/or B connectors to be used interchangeably and combined together, a universal hole pattern is proposed for both versions—or at least for Type 2, so that it can accommodate Type 1 modules. This hole pattern, along with the 3.775 x 3.550 inch module footprint, are collectively dubbed the “Unified Embedded Module Framework” (UEMF). SUMIT-ISM Type 2 implemented on the UEMF is illustrated in Figure 3. A dimensioned mechanical drawing appears in Figure 4.

Implications of the UEMF

By virtue of its symmetrical mounting capability, the UEMF provides much more flexibility than the original, nonsymmetrical PC/104 form factor. For example, a SUMIT-ESM Type 1 module could stack atop a SUMIT-ESM Type 2 module (illustrated in Figure 3), providing the Type 1 module’s 104-pin ISA bus pass-through connector is removed.

It is now possible to envision an extremely long lifecycle and broad range of applications extending well beyond the current transition from parallel to serial buses and interfaces. As already demonstrated in this proposal, the UEMF potentially enables SUMIT to team up with a choice of 104pin ISA bus (SUMIT-ISM Type 1) or 120-pin PCI (SUMIT-ISM Type 2), for maximum flexibility of legacy support. Similarly, UEMF could provide this same flexibility to the PC/104 Consortium’s new stackable PCIe bus (PCIe/104) standard. More importantly, UEMF enables a technology roadmap beyond the current transition, for there will surely come a time—perhaps five years from now— when today’s next- generation bus (PCIe) will have become tomorrow’s legacy bus, and the stackable SBC market will once again be wondering which of several legacy buses is the most important to retain. Who knows—in two years we

PCI-104 PCI Connector

PCI-104 PCI Connector

PC/104 ISA Connector

PCIe/104 PCIe Connector

PC/104-Plus on UEMF 1

B

SUMIT Connectors

PCI-104 Express on UEMF 1

A

PCI-104 PCI Connector

PC/104 ISA Connectors A

SUMIT Connectors

1

SUMIT-ESM Type 1 on UEMF

Possible connector configurations enabled by the UEMF.

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1

SUMIT-ESM Type 2 on UEMF

Figure 5

Untitled-1 1

B


technology in context

1 B

SUMIT Connectors

1 A

PCIe/104 PCIe Connector

Figure 6 SUMIT A/B along with PCIe/104 PCIe.

may use the UEMF to add PCIe/104 to SUMIT A/B, to keep up with the latest Intel embedded processor’s increased number of available PCI Express lanes. Or, perhaps UEMF will be harnessed to introduce some sort of fiber-optic system expansion bus. The drawings in Figure 5 illustrate the flexibility of the UEMF and suggest some possibilities. And last, but not least, the SFF-SIG’s SUMIT A/B bus combined with the PC/104 Consortium’s PCIe/104 PCI Express bus is shown in Figure 6.

ted holes in order to accommodate both buses’ reference hole patterns. Enclosure mounting holes can— and probably should—retain the original asymmetrical PC/104 hole pattern, at least for now. However, it may be desirable to migrate all UEMF modules to the slotted pattern over the next five years, and after ten years to the symmetrical hole pattern that corresponds to the outer foci of the currently proposed slotted pattern. There have been some concerns and suggestions that the slotted mounting holes may compromise resistance to shock and vibration. We believe that the four corner-mounting screws will be fully capable of holding stacked boards rigidly in place. We plan to perform a number of tests to verify that the approach is sufficiently robust to survive the environments where PC/104-style modules are typically used. It should be noted that the four 0.125 diameter mounting holes on PC/104-style modules are already larger than the diameter of the screws, so transverse forces, which are already present in PC/104based systems, have not been an issue to

date. PC/104-style modules are typically secured via 4-40 mounting hardware with 0.112 diameter threads. Regarding the requirement for the slotted holes, SUMITESM Type 2 could be usable with PCI-104 modules regardless of whether the Type 2 modules’ holes are slotted or normal. The advantage of the UEMF is that it lets PC/104-sized modules with a wide variety of buses be combined together in stacks, without forcing module vendors to modify legacy modules or build each module two ways (other than leaving off unused bus connectors). Thanks to the UEMF approach, stackable ISA, PCI and PCI Express buses (from the PC/104 Consortium), the stackable SUMIT PCI Express bus (from the SFF-SIG), the stackable USB bus (from the StackableUSB association), and future stackable buses yet to be defined can all coexist synergistically. Diamond Systems Mountain View, CA. (650) 810-2500. [www.diamondsystems.com].

Issues Concerning Slotted Mounting Holes

Must all UEMF module formats adopt the UEMF’s slotted mounting hole pattern? The short answer is no, although it makes sense for newly designed modules of all types. Each bus used on PC/104-style modules was originally situated at either the “top” or “bottom” edge of the original PC/104 footprint, thus associating it with a specific mounting hole pattern. With that in mind, here is a simple rule: Each bus on a UEMF module or UEMF stack host board must be accompanied by its originally defined reference hole pattern (all four corners). Thus, dual-bus UEMF modules, having both buses in their “standard” locations, are free to use legacy PC/104-style (round) mounting holes. Modules such as the SUMIT-ISM Type 2 format proposed in this document, with SUMIT at the “bottom” instead of at the “top” (as defined by SUMIT-ISM Type 1), would require slot-

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solutions

engineering INTELLIGENT POWER MANAGEMENT

RTOS – The Heart of Good Power Management The basic mechanisms for power management are already in the RTOS. The lowest-priority task can put the CPU into a selected sleep mode to be reawakened by any interrupt in the role of Prince Charming. by Lotta Frimanson, IAR Systems

L

ow power consumption is an essential requirement in many embedded applications. The growing importance of battery-powered applications for portable electronics, home automation and wireless communications—for example, in medical devices, personal navigation devices, sports watches and portable game consoles—means that the demand for improved battery life is growing dramatically. The number of low-power versions of microprocessors and other silicon devices that have power management capabilities is increasing steadily. Many embedded applications spend most of their time waiting for something to happen: receiving data on a serial port, watching an I/O pin change state, or waiting for a time delay to expire. If the processor is still running at full speed when it is idle, battery life is being consumed while very little is being accomplished. So in many applications the microprocessor is only active during a very small amount of the total time, and by placing it in a low-power mode during the idle time, the battery life can be extended by orders of magnitude. However, incorporating power management and using an RTOS may be just as important a way to save power as the

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/********************************************************************** * * OS_InitHW() * * Initialize the hardware (timer) required for the RTOS to run. * May be modified, if another timer should be used */ void OS_InitHW(void) { OS_IncDI(); /* Ensure, interrups are diabled TA0CTL = 0 /* Reset Timer_A5, division 1 | (1 << 2) /* Clear timer | (2 << 8) /* Use SMCLK as timer clock ; TA0CCR0 = (OS_PCLK_TIMER / 1000) - 1; /* Set to 1ms TA0CCTL0 = 0 /* Initialize capture control | (1 << 4); /* Enable compare interrupt TA0CTL |= (1 << 4); /* Start timer in UP-Mode OS_POWER_UsageInc(OS_POWER_USE_SMCLK); /* Mark SMCLK as used OS_COM_Init(); /* Initialize UART OS_DecRI(); /* Restore interrupt context }

*/ */ */ */ */ */ */ */ */ */ */

Figure 1 Example of a task indicating usage of the SMCLK clock via OS_POWER_ UsageInc.

silicon design itself. Test examples have shown that some microprocessors may be in idle mode for 60 - 80% of their operating time. Using an RTOS in combination with idle tasks may significantly reduce power consumption and the CPU overhead by ensuring that the CPU is in its lowest possible power mode whenever it is idle.

Reducing Power Consumption in an Embedded System

The key is to minimize the active time and therefore maximize the time when the processor can go to sleep. The active time can be reduced by using a compiler that is efficient at optimizing for speed. The faster a specific task can be executed, the less time the processor needs to run.


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solutions engineering

A further important consideration is to structure the code in a way that identifies when the system is not performing any tasks. A good approach is to have a taskoriented design and to use an RTOS: In a task-oriented design, a task can be defined with the lowest priority, and will then only run when there is no other task needing to run. We call this task the idle task, and it is the perfect place to implement power management. In practice, every time the idle task is activated, it puts the processor into a low-power mode. An RTOS provides the developer with a framework on which to build and organize the features of the system. The toolbox that accompanies the RTOS should also provide services such as intertask communication and time management. Even for systems that have no need of the real-time capability, the code can be cleaner and better organized if based on an RTOS, partly because it promotes code reuse. The integration of an RTOS solves

a variety of problems that can occur in application code, since it provides multitasking capability and allows the application to be broken down into smaller pieces. Each task is assigned its own priority based on its importance, and preemptive scheduling ensures that the microcontroller (MCU) runs the task that has the highest priority among those that are ready to run. In most cases, adding a lower-priority task will not affect the responsiveness of the system to high-priority tasks. There are many advantages to implementing power management within the OS, as it allows developers to concentrate purely on application development. The application developers can then easily use this object-oriented approach to make the embedded system more power efficient and easier to maintain, and development times become faster.

Using Low-Power Modes

The use of low-power modes is also very beneficial. A low-power mode is simply

/********************************************************************** * * Idle loop (OS_Idle) * * Please note: * This is basically the â&#x20AC;&#x153;coreâ&#x20AC;? of the idle loop. * This core loop can be changed, but: * The idle loop does not have a stack of its own, therefore no * functionality should be implemented that relies on the stack * to be preserved. However, a simple program loop can be programmed * (like toggling an output or incrementing a counter) * * We just enter low power 0 mode here. */ void OS_Idle(void) { /*Idle loop: No task is ready to exec */ OS_UINT PowerMask; OS_U16 ClkControl; OS_DI(); // // Examine which peripherals may be switched off */ // PowerMask = OS_POWER_GetMask(); // // Switch off peripherals which are not needed // ClkControl = UCSCTL8 & ~OS_POWER_USE_ALL; PowerMask &= OS_POWER_USE_ALL; UCSCTL8 = ClkControl | PowerMask; // // Nothing to do ... enter low power mode, with interrupts enabled // BIS_SR(GIE+CPUOFF+OSCOFF+SCG1+SCG0); for (;;); /* Alternative endless loop, required */ /* when simulator is used ! */ }

Figure 2 Example of an idle task that is using OS_POWER_GetMask to get information about peripheral usage.

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solutions engineering

a state that a microprocessor can be switched to in order to save power. Many microprocessors and other silicon devices have a number of different low-power modes, in which different parts of the processor can be turned off when they are not needed. The oscillator can be either turned off or switched to a lower frequency, peripheral units and timers can be turned off, and the CPU stops executing instructions. Several processors have different levels of low-power modes, each with a different power consumption based on which peripherals are left on. The wake-up time from a low-power mode does of course differ depending on which microprocessor it is, and it also depends also on which parts of the processor have been turned off. For example, the MSP430 device in the 5xx family has a wakeup time from standby mode of less than 5 µs. MSP430X5xx devices support several power modes, so instead of all clocks being active the following modes may be applied:

the saved SR value on the stack within the interrupt service routine, and the modecontrol bits and the stack can be accessed within any instruction. When setting any of the mode-control bits, the selected operating mode takes effect immediately. Peripherals operating with any disabled clock are themselves disabled until the clock becomes active again. The peripherals may also be disabled by means of their individual control register settings.

Example of Implementing Power Save

The perfect place to implement power management is in the idle task, since this is the code that will be executed as soon as there are no other tasks to perform. Depending on which resources are used, the idle task is an ideal means to trigger the CPU to enter the lowest possible power mode. Figures 1 and 2 show an example of implementing the power save

Low-power mode 1 (LPM1) • CPU is disabled. • ACLK and SMCLK remain active. MCLK is disabled. • DCO’s dc-generator is disabled if DCO not used in active mode. Low-power mode 2 (LPM2) • CPU is disabled. • MCLK and SMCLK are disabled. • DCO’s dc-generator remains enabled. • ACLK remains active. Low-power mode 3 (LPM3) • CPU is disabled. • MCLK and SMCLK are disabled. • DCO’s dc-generator is disabled. • ACLK remains active. The low-power modes shown above are configured by means of the CPUOFF, OSCOFF, SCG0 and SCG1 bits in the status register. The advantage of including these particular mode-control bits in the status register is that the current operating mode is saved onto the stack during an interrupt service routine. The program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine. Program flow can be returned to a different operating mode by manipulating Untitled-4 1

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solutions engineering

functionality in the idle function, where we switch off the peripherals that are not used and then enter one of the low-power modes. It is noted that the RTOS always brings the CPU into lowest power mode possible whenever the CPU is idle and peripheral clock requirements are taken into account. IAR PowerPac for MSP430 provides support for power management; its RTOS uses power management

counters to keep track of the usage of shared resourced within the system. The following power management functions are provided: OS_POWER_GetMask — Returns a mask that shows which power management counters are set. OS_POWER_UsageDec — Decrements power management counters. OS_POWER_UsageInc—- Increments power management counters.

All tasks that are using shared hardware resources need to make operating systems calls to let the system know when shared resources are or are not in use. In the hardware initialization example in Figure 1, the function needs to use OS_POWER_UsageInc to indicate that the Sub-System Master Clock (SMCLK) is used by the system. The idle task will use the function OS_POWER_GetMask to get information about which power management counters are set, as shown in Figure 2. This will make it possible for the idle task to find out which low-power mode it can enter. All peripheral units with a counter value of zero can be switched off. On an MSP430 processor, entering a low-power mode is done by a simple write to the status register. The processor will now stay in the lowpower mode until one of the tasks is ready to execute. Whenever there is a task that needs to be done, or the application needs to respond to an event, the system will be woken up through any enabled interrupt. With only a very small amount of additional code, it is possible for an application to make significant improvements when it comes to saving power. Additionally, there is no need to increase the complexity of the system to implement power management, since the RTOS manages it with virtually no overhead. Using the RTOS to manage power in this way will ensure that the processor spends as much time as possible in the lowest possible low-power mode. So what exactly do you as a developer need to consider in order to minimize the power consumption? Firstly, you need to select a microprocessor that can run at a low-power level, and which supports lowpower modes. And you should select a professional build chain with a highly optimized compiler. Then it is necessary to use an efficient RTOS with a small footprint and optimized task switching. And finally, you should implement the power management functionality, and thus make the idle task responsible for bringing the processor into a low-power mode. IAR Systems Foster City, CA. (650) 287-4250. [www.iar.com].

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ploration your goal k directly age, the source. ology, d products

Industry

insight MANAGING SMALL MODULES

Using I2C for “Behind-the-Scenes” Management Hardware platform management implementations must interface with a variety of components with different characteristics. The Inter-Integrated Circuit Bus provides a straightforward and extensible basis for building powerful management into complex systems. by Michael Thompson, Pentair/Schroff and Serge Zhukov, Pigeon Point Systems

T

he Advanced Telecommunications ATCA/AMC Specification Elements Potential Pigeon Point Product Sites Architecture (ATCA) and MicroTShelf Manager System Manager Shelf-Specific 1. Shelf Managers CA specifications include hardware Shelf Management Controller (ShMC) ShMM Carrier Running Pigeon Point IPM Controllers - Several Variants Shelf Manager platform management capabilities because ShMM-500R AdvancedTCA Board the target markets demand high reliability Other Field Replaceable Unit (FRU) and maintainability. The specifications 2. IPM Controllers — AMC Module intentionally omit the implementation deShelf Shelf BMR Controller Variants for Distrinct Types of Boards and FRUs Manager Manager Reference tails of the hardware and firmware for the (Active) (backup) Design Fan Tray Power Entry Running Pigeon Point [1...N] Module management devices. This allows the deBMR Firmware [1...N] signer to consider all of the trade-offs and Optionally Implemented in Fusion Mixed-Signal FPGA ShMC ShMC nies providing solutions IPMC IPMC decide whatnow is best. ion into products, technologies and companies. Whether your goal is to research the latest From the external, management-ori2x Redundant, Bused or Radial, IPMB-0 ation Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ented view (Figure 1), a shelf is a collecyou require for whatever type of technology, Carrier of searching field replaceable units (FRUs) and IPMC IPMC IPMC AMC MMC and productstion you are for. IPMC their associated sensors. When you look IPMB-L at the actual FRU designs you will find ATCA ATCA ATCA ATCA AMC MMC that they are often intelligent, incorporatBoard Board Board Board ing a microprocessor or an FPGA with a 2x Redundant Radial Internet-Protocol-Capable Transport microprocessor core running shelf manFigure 1 ager or Intelligent Platform Management Controller (IPMC) firmware. An FRU can Overall ATCAN FRU Management Architecture. also be non-intelligent, but managed by an intelligent FRU. In either case, the ex- non-intelligent FRUs and their sensors is dardized method of interacting with the ternal representation of the intelligent and the same. FRUs. This architecture defines messages The Intelligent Platform Manage- that travel on the Intelligent Platform ment Interface (IPMI) architecture, sub- Management Bus (IPMB), an I2C bus that Get Connected stantially enhanced by the ATCA and Mi- interconnects the FRUs inside the shelf. with companies mentioned in this article. croTCA specifications, is used as a stan- Using IPMI abstracts the physical implewww.rtcmagazine.com/getconnected

End of Article

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industry insight

mentation of the FRU. The only requirement is that the FRU implementation must comply with the IPMI behavioral and I2C electrical specifications.

Approaches to Management Solution

ATCA supports both intelligent and non-intelligent FRUs. Non-intelligent FRUs are usually managed by an IPMC on another intelligent FRU or by the shelf manager (the managing controller). The managing controller represents itself and its own sensors (such as temperature or voltage sensors) to the shelf manager, as well as representing its managed FRUs and their sensors. A managing IPMC can represent AdvancedMC (AMC) modules to the shelf manager, using an architecture defined by the AdvancedMC specification. An IPMC uses IPMI/I2C to communicate with the shelf manager over the IPMB, but the communication interface between the IPMC, its sensors and its managed FRUs is not defined. Each IPMC needs to implement I2C for the IPMB so it is natural to also use I2C-based voltage, current, temperature or presence sensor devices and I2C-based nonvolatile FRU data storage. The I2C sensor devices that are on an FRU controlled by the IPMC are not directly connected to anything outside of that FRU. The I2C devices on the FRU are accessed in a standardized way via IPMI commands. For the purposes of hardware platform management, the devices in the IPMC are usually exposed as collections of sensors and FRU inventory devices. For each supported sensor, the IPMC has an associated Sensor Data Record (SDR). IPMI commands are defined to read the contents of the SDR. The SDR contains all information about the sensor: its type, format of the analog reading, measurement units and parameters for conversion from the single-byte “raw” reading to the numeric “processed” reading. The processed reading is expressed in measurement units that make sense to the user like the number of RPMs for a fan tachometer sensor or the number of volts for a voltage sensor. The SDR also contains the human-readable name of the sensor, initial values of thresholds and hysteresis,

ATCA/AMC Specification Elements Shelf Manager

System Manager

Shelf Management Controller (ShMC) IPM Controllers - Several Variants AdvancedTCA Board Other Field Replaceable Unit (FRU)

Shelf Manager (Active)

Shelf Manager (backup)

ShMC

ShMC

AMC Module Fan Tray 1 ... 3 I2C Devices

PEM 1 ... 2

SAP

I2C Devices

I2C Devices

I2C Bus

IPMC

Carrier IPMC

2x Redundant, Bused or Radial, IPMB-0

AMC MMC

IPMC

IPMC

AMC MMC

ATCA Board

ATCA Board

IPMB-L ATCA Board

Figure 2

ATCA Board

2x Redundant Radial Internet-Protocol-Capable Transport

ATCAN FRU Management Architecture with Non-intelligent Auxiliary FRUs.

and, for discrete sensors, the mask of supported states and assertion and deassertion state masks. So, the IPMC normally represents I2C sensor devices as IPMI sensors, mapping the corresponding I2C device register value to the IPMI analog reading and describing the attributes of the device in the corresponding SDR. I2C devices and signals used as control inputs and outputs are represented as settable sensors. I2C-based EEPROMs are often used to store “FRU information.” The FRU information is a collection of structured records defined by the IPMI or PICMG specifications that describe an FRU and its properties (such as inventory information like serial and model numbers). A key question for ATCA shelf developers is how to manage the auxiliary FRUs that make up the shelf infrastructure, such as fan trays, power entry modules and alarm panels. In one approach, as shown in Figure 1, each of these FRUs is represented by an IPMC. Some shelf vendors and their customers prefer that approach. The IPMC-based auxiliary FRU architecture can make shelf maintenance a headache because there can be more than six IPMCs on those FRUs (in a shelf that has two power modules, three fan trays and an alarm panel, for instance). The different types of FRUs in the shelf usually have their own specific firmware versions,

adding to the maintenance complexity. Different revisions of the IPMC firmware may behave differently so you need to be careful about mixing FRU revision levels. You may also find that newer revisions of the IPMC firmware may not run on older FRU hardware revisions. An alternative shelf management architecture has a single microprocessor, usually on the shelf manager (or perhaps a redundant pair of microprocessors, normally running the same firmware), managing multiple non-intelligent chassis FRUs. This dramatically reduces the number of microprocessors and the amount of independently managed firmware in the shelf. Since there is only a single copy of management firmware this also makes system maintenance much easer. When the firmware in the single microprocessor is upgraded, the behavior of all of the FRUs is upgraded at the same time. In the example that follows, the shelf manager manages six non-intelligent FRUs in the shelf. The shelf manager has I2C interconnects for management links and also uses I2C to connect to the devices on the FRUs. Just as on an IPMC, the microprocessor on the shelf manager manages the non-intelligent FRUs in the shelf and makes the sensor devices on managed FRUs in the shelf appear to be intelligent. Figure 2 shows a shelf management architecture in this second model, where the auxiliary FRUs are non-intelligent and RTC MAGAZINE JUNE 2009

25


industry insight

SAP

PEM A -LM75 -SEEPROM -PCA9555

- LM75 (Exhaust left) - LM75 (Exhaust center) - LM75 (Exhaust right) - LM75 (Board) - SEEPROM - PCA9555

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agement architecture you need a generic method that describes a specific shelf design and lets the shelf manager interpret this description dynamically. Compared to a regular IPMC, the shelf manager can utilize a more powerful processor, so this approach becomes practical. The Pigeon Point shelf manager uses this approach to provide generic support for different types of shelves, shelf manager carriers and non-intelligent FRUs. These are described in a textual format in a special language designed by Pigeon Point Systems, called Hardware Platform Definition Language (HPDL). An HPDL description of a shelf includes the list of

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are â&#x20AC;&#x153;ownedâ&#x20AC;? by the shelf manager, rather than having local IPMCs. Compared with a regular IPMC, the shelf manager has more challenges and possibilities in managing these auxiliary FRUs. The main challenge is that a shelf manager should ideally support ATCA shelves of different types, each of which may have a different population of nonintelligent FRUs, sensors and control devices. It is good to avoid the need to add new firmware to support each new shelf design. This will also prevent the shelf manager firmware implementation from expanding in size and complexity over time. To implement this flexible man-

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26

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Au1550 Processor

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industry insight

non-intelligent FRUs with their properties, describes the I2C devices and the corresponding signals that exist on the FRUs, describes mapping between the I2C devices and IPMI sensors, and also includes the SDRs for these sensors. The shelf description in HPDL is created by the shelf manufacturer, possibly in collaboration with Pigeon Point engineers. The HPDL description is then compiled into a binary format, compressed and stored in the Shelf FRU information device. The Shelf FRU information device is a redundant (typically an EEPROMbased) storage device that contains, according to the ATCA specification, important information about the shelf. Shelf FRU Information is mandatory for any ATCA-compliant shelf, and its format, based on variable-sized records, allows vendor-specific extensions. This is a good location for storing the HPDL description of the shelf. The shelf manager reads the Shelf FRU Information at initialization. When the shelf manager firmware encounters HPDL description records in the Shelf FRU Information, it reads and interprets them. Based on that information, the shelf manager firmware creates corresponding managed FRUs and sensors, and maps subsequent operations on managed FRUs and sensors to reads and writes on the corresponding I2C devices.

A Management Architecture

Designing a shelf that utilizes HPDL with just I2C devices on the FRUs can present some challenges. I2C devices like temperature sensors and EEPROMs have a limited number of possible bus addresses. Fortunately, I2C bus switches are available so that the I2C devices can be arranged in a hierarchy that eliminates the address conflicts. Also, there are limitations on the total capacitance that the I2C devices can put on the I2C bus. An I2C switch alleviates this restriction because it reduces the total number of devices that are connected to a single I2C bus at the same time. Figure 3 shows the overall I2Cbased FRU management architecture of a Schroff ATCA shelf. The Schroff shelf manager incorporates a Pigeon Point ShMM-500R Shelf Management Mezzanine. The RMI Alchemy Au1550 proces-

sor on the ShMM-500R has two I2C buses that implement the IPMB-0 management links. It also has a master-only I2C bus that is used to connect to the I2C devices on the shelf manager and auxiliary shelf FRUs. The shelf manager includes an On Semiconductor I2C ADM1026 that provides FRU data storage, fan speed monitoring, fan speed control, temperature sensing, voltage measurement and GPIO—

nearly all of the sensors on the shelf manager. HPDL records describe the I2C devices on the shelf manager, and how the shelf manager’s sensors are mapped to the I2C devices or the pins on the I2C devices. The shelf manager’s master-only I2C bus needs to be connected to the I2C devices on the shelf’s non-intelligent FRUs. As stated earlier, a hierarchy of I2C buses is necessary because of address limitations and to limit capacitance on the I2C bus.

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FAN _ TRAY FanTray0 { SITE 4, 1; PRESENCE Master _ ADM1026.FanTray0 _ Presence; HOT _ SWAP BUTTON, FT _ IO.FT _ IO _ Pushbutton; HOT _ SWAP _ LED FT _ IO.FT _ Blue _ Led; LEDS { LedFail: 1: OFF, ON, SHORT _ BLINK, RED, , , FT _ IO.FT _ Red _ Led; LedStatus: 2: ON, ON, SHORT _ BLINK, GREEN, , , FT _ IO.FT _ Green _ Led; }; POWER _ LEVELS { 100 }; FRU _ INFORMATION “FT _ EEPROM”, 2048; DEVICES { DEVICE FT _ LM75 { LM75:3:0x4c; }; DEVICE FT _ EEPROM { AT24LC256:3:0x54; }; DEVICE FT _ IO { PCA9555:3:0x24; SIGNALS { FT _ 48A: IO _ 0 _ 0, in, low; FT _ 48A _ AF: IO _ 0 _ 1, in, low; FT _ 48B: IO _ 0 _ 2, in, low; FT _ 48B _ AF: IO _ 0 _ 3, in, low; FT _ 24V: IO _ 0 _ 4, in, low; FT _ Fan _ Off: IO _ 0 _ 5, out, low; FT _ Green _ Led: IO _ 1 _ 3, out, high; FT _ IO _ Pushbutton: IO _ 1 _ 4, in, low; FT _ Red _ Led : IO _ 1 _ 5, out, high; FT _ Blue _ Led: IO _ 1 _ 7, out, high; }; }; }; SENSORS { 0x20,0,124: 3000: FT _ LM75; 0x20,0,208: FT _ IO.FT _ 24V INITIAL _ STATE 1; 0x20,0,209: FT _ IO.FT _ 48A INITIAL _ STATE 1; 0x20,0,210: FT _ IO.FT _ 48A _ AF INITIAL _ STATE 1; 0x20,0,211: FT _ IO.FT _ 48B INITIAL _ STATE 1; 0x20,0,212: FT _ IO.FT _ 48B _ AF INITIAL _ STATE 1; 0x20,0,213: FT _ IO.FT _ 48A && FT _ IO.FT _ 48A _ AF, FT _ IO.FT _ 48A && !FT _ IO.FT _ 48A _ AF, !FT _ IO.FT _ 48A && !FT _ IO.FT _ 48A _ AF INITIAL _ STATE 1; 0x20,0,214: FT _ IO.FT _ 48B && FT _ IO.FT _ 48B _ AF, FT _ IO.FT _ 48B && !FT _ IO.FT _ 48B _ AF, !FT _ IO.FT _ 48B && !FT _ IO.FT _ 48B _ AF INITIAL _ STATE 1; 0x20,0,240: Tachometer0; 0x20,0,241: Tachometer1; }; MIN _ LEVEL 1; MAX _ LEVEL 15; NORMAL _ LEVEL 8; LEVEL _ EXPRESSION Master _ ADM1026.FanControl; LEVELS { 1: Master _ ADM1026.FanControl = 0x1, UC 255; 2: Master _ ADM1026.FanControl = 0x2, UC 255; 3: Master _ ADM1026.FanControl = 0x3, UC 255; 4: Master _ ADM1026.FanControl = 0x4, UC 255; 5: Master _ ADM1026.FanControl = 0x5, UC 199; 6: Master _ ADM1026.FanControl = 0x6, UC 159; 7: Master _ ADM1026.FanControl = 0x7, UC 132; 8: Master _ ADM1026.FanControl = 0x8, UC 115; 9: Master _ ADM1026.FanControl = 0x9, UC 99; 10: Master _ ADM1026.FanControl = 0xA, UC 88; 11: Master _ ADM1026.FanControl = 0xB, UC 79; 12: Master _ ADM1026.FanControl = 0xC, UC 71; 13: Master _ ADM1026.FanControl = 0xD, UC 66; 14: Master _ ADM1026.FanControl = 0xE, UC 61; 15: Master _ ADM1026.FanControl = 0xF, UC 56; }; EMERGENCY _ SHUTDOWN FT _ IO.FT _ Fan _ Off; LOCAL _ CONTROL Master _ ADM1026.FanLocalControl; TACHOMETERS { 0 : 0x20,0,240; 1 : 0x20,0,241; }; };

Figure 4 HPDL records for a non-intelligent ATCA Fan Tray.


industry insight

An NXP PCA9545 1x4 I2C switch and an LTC4300-controllable I2C buffer expand the single master-only I2C bus to five I2C bus segments that connect to the off-board I2C devices. HPDL records describe the I2C switch and the I2C bus hierarchy so the shelf manager firmware knows where to find all of the devices on the non-intelligent FRUs. The shelf alarm panel (SAP) has an onboard I2C temperature sensor, three exhaust air temperature sensors, a SEEPROM for FRU data storage and PCA9555 GPIO devices. Since the SAP is a separate FRU from the shelf manager, these I2C devices are described in the HPDL records, but they are associated with the SAP FRU. The power entry modules (PEMs) and fan trays use the same LM75 I2C temperature sensor, SEEPROM and GPIO devices as the SAP. There are not enough I2C addresses available for all of the devices to be connected to the shelf manager at the same time. The I2C switch on the shelf manager allows us to only connect to a few of the devices at a time, so the hierarchical design works. Additional HPDL records describe all of these I2C devices and associate them with their corresponding FRUs. The shelf requires FRU data storage for board and product data, for power management and interconnect information, and for the HPDL data. This shelf includes SEEPROMs on chassis data modules (CDMs) on individual I2C buses for redundancy. The Shelf FRU Information SEEPROMs are described in HPDL records that are stored in the SEEPROMs on the shelf manager. The shelf supports redundant shelf managers. Because of the possibility of a hardware or software failure, only a healthy and active shelf manager can enable its off-board I2C buses and utilize the I2C devices on the Shelf FRUs. A watchdog timer on the shelf manager will disable off-board access to the I2C devices if there is a hardware or software failure on the shelf manager. There are a small number of I2C devices on the shelf manager that measure the local air temperature, control and monitor the cooling fans, store FRU data, and control and monitor digital I/O. The shelf manager firmware running on the

Au1550 makes its onboard I2C devices appear as intelligent sensors that are associated with the shelf manager FRU. The HPDL records that describe the fan tray of the shelf architecture described above, are shown in Figure 4. From the implementation examples above, we can see that I2C has proven to be an excellent choice for both the TCAspecified in-shelf management links and for the behind-the-scenes connections

Untitled-7 1

to the sensor and storage devices on the FRUs in a shelf. Pentair/Schroff Warwick, RI. (401) 732-3770. [www.schroff.us]. Pigeon Point Systems Scotts Valley, CA. (831) 438-1565. [www.pigeonpoint.com].

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6/1/09 3:31:58 PM RTC MAGAZINE JUNE 2009


System Integration MOTION CONTROL AND SAFETY

A Framework for Safe Motion Control Firmware by Michael Wilk and Michael Barr, Netrino

30

JUNE 2009 RTC MAGAZINE


system integration

Writing the software to handle motion control is a critical job on any real-time system design project. Safety is of the utmost importance. And, of course, it is also important that the code work precisely and allow for testing and performance tuning. An object-oriented framework can be used to create safe, testable and tunable motion control systems.

D Ad Index

<< abstract>> CSensorBase 1...*

CRelativeSensor

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eveloping firmware for motion control systems can be a Sensor and motor class diagram. tricky business. Strict accuracy and repeatability combine with user safety to present a challenging set of requirements. How do you go about designing motion control firmware CDataComm CDataLogger CDataLoggerItem to meet these requirements properly? And how can you ensure 0...* the resulting implementation is tunable with andtechnology testable and from the Get Connected companies providing solutions now start? In using what are some key design methodologies and the Get Connected a new resource for furthermotion exploration beginnings of a framework for safe, istestable and tunable into products, technologies and companies. Whether your goal CMotorBase control firmware, it is important to consider the design goals. is to research the latest datasheet from a company, speak directly CBLDCMotor 0...* CBLDCMotorDataItem Safety concerns vary Engineer, by the orindustry for which you write with an Application jump to a company's technical page, the firmware. In goal such application areas andresource. aeroof Get Connected is toas putmedical you in touchdevices with the right Figure 2 Whichever of service youpriority. require forHow whatever type of technology, space systems, safetylevel is the critical a system handles Data logging class diagram. Connected will help you connect with the companies and products failures fromGet a safety perspective might vary. For example, in a you are searching for. medical device that uses motion control, if there is a systematic www.rtcmagazine.com/getconnected failure, the system must fail in a manner that will keep the patient use to get the job done. Before getting into the always-interesting or user safe. This may simply be to invoke an electromechanical specific motion control algorithms and low-level hardware coninterlock and alert the operator. In other cases, a failure in the trols, we should first consider the software framework. system may not be as simple as shutting down, and so the events Infrastructure planning starts by thinking and using objectthat take place following a failure must be well defined. oriented analysis and design techniques. We have a great modelwith system technology and with companies solutions The testabilityGet of aConnected motion control starts goodproviding ing tool at ournow disposal in Universal Modeling Language (UML) Get firmware Connectedplays is a new for further into products, Whether yourwe goalcan is to begin, researchwith the latest architecture, and the a resource key role. Test exploration engineers class technologies diagrams and andcompanies. state charts. But or withdatasheet from a company, speak directly with an to Application jump to by a company's technical page,objects the goal of Get limited Connected to put you must have the ability to verify all software modules ensureEngineer, outorUML, identifying a few with andis discrete in touch with the right resource. Whichever level of service you require for whatever type of technology, correct behavior. One of the most common mistakes is testing sets of responsibilities. Used properly, objects also help avoid Get Connected will help you connect with the companies and products you are searching for. with only www.rtcmagazine.com/getconnected valid (i.e., in range) inputs. The real key to testing is coupling between subsystems through encapsulation and good subjecting the system and/or its various modules to invalid inputs interface design. and ensuring the system behaves correctly and safely under all To make our discussion concrete, consider the UML class possible conditions. diagram in Figure 1, which shows how to represent sensor and If a bug causes the software to request motion that requires motor objects in an abstract way. We know there are many differinfinite acceleration, does the firmware respond safely or does it ent types of sensors and motors. However, these objects do have instead try to perform the erroneous operation and hope for the common sets of features. In addition, there is a relationship bebest? For a safety-critical system, this can have devastating re- tween motors and their associated sensors. In the model shown, sults, for example if a surgical robot receives an invalid position we do not directly incorporate sensor functionality with our motor implementation, but rather associate sensors with a motor or velocity command. Testable motion control systems should also provide means instance. This object model immediately shows us extensibility for tuning the motion control parameters. Tuning is necessary to and reuse using abstraction and class inheritance. The sensor and Get Connected with companies and Get Connected model also sets us up for maintainability because ensure bothfeatured precision repeatability in movement outcomes, motor object products in thisand section. with companies mentioned in this article. we are avoiding putting all our functionality into a single object. with www.rtcmagazine.com/getconnected such calibration generally motor-specific. www.rtcmagazine.com/getconnected To reach our testability goals, we need to go a step further than this model by defining the public interface to each object. Infrastructure Planning Reaching all of our design goals properly in the first implementation requires time to think and plan prior to the start of Get Connected with companies mentioned in this article. coding. At the samewith time, we also tofeatured consider the tools weâ&#x20AC;&#x2122;ll www.rtcmagazine.com/getconnected Get Connected companies and need products in this section.

Products

End of Article

www.rtcmagazine.com/getconnected

RTC MAGAZINE JUNE 2009

31


system integration

Once the interface is in place, white box tests can be developed to ensure proper functionality and the ability to handle invalid inputs. We now have a set of objects in our framework for managing the motion control itself, but I mentioned earlier that infrastructure was one of the keys to success. Let’s assume that our motors and sensors have the data we need, but how can we make it available, especially if we’re running in an embedded system? This is where the classes in Figure 2 become part of our infrastructure.

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ning in its own task) that maintains a list of CDataLoggerItem derived objects. CDataLoggerItem provides an interface for common methods but does not actually contain any real data. The derived class, in this case CBLDCMotorDataItem, contains the specific data we care about. Using polymorphism, the data is formatted and obtained over our communication channel. As we manage/control the motor, we set and add CBLDCMotorDataItem data to our running list that is managed by the CDataLogger instance. As a side note, we would want to allocate our CBLDCMotorDataItem objects ahead of time and keep them in a memory pool to avoid dynamic memory allocation at runtime. From the outside world, we access the list of data through our communication evUnInit interface. This data becomes available for performing offline or near real-time analyevInitialize sis and/or display of data. The data could include position, velocity, current, or other data. It is completely up to the developer to Error evError define what data to provide. Of course, we enter/TurnOffMotor(); TurnOnBrake(); can also imagine a lot of possibilities for other objects like CBLDCMotorDataItem that could be used for various purposes. So what do we do with the data now that we have it available? That’s really up to you, but I have used this data, combined with a small custom application, to provide live data displays or perform calculations. You could also do runtime calculations and graph the results to monitor your motion control behavior at runtime. The available tools for developing such test applications are varied, but could include Java, .NET, or LabVIEW, all of which have extensive evError support for communicating with your firmware. You could even go so far as to develop an entire testing infrastructure that matches your firmware infrastructure that would allow your testers to write a variety of test applications.

Figure 3 Example motion control state diagram.

Figure 2 presents a few different ideas. The first is the CDataComm class, which is a singleton object that provides a gateway to the outside world. The actual communication channel might be RS-232, USB, or Ethernet; it really doesn’t matter from the system perspective. The CDataComm object manages requests for data and sends responses. There are more efficient mechanisms, but I am assuming a query/response communication model. The next thing to notice is the CDataLogger object. CDataLogger is an instance of an active object (perhaps run-

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JUNE 2009 RTC MAGAZINE

Event-Driven Software

The next level of design for the framework provides a means to ensure efficient and deterministic behavior. We recommend taking advantage of an event-driven, message-based framework to communicate among your objects. An event-driven software architecture works well with an object-oriented design such as that above. It also helps to ensure efficient use of the CPU and ties into another valuable design methodology: state machines. Using an event-driven architecture combined with state machines utilizes run-to-completion semantics, which eliminate race conditions, and can ensure deterministic response times for critical system event handling. You can do


system integration

this using RTOS mailboxes or message queues, or with a statemachine framework. The use of state machines ensures predictable and discrete behavior based on a given system event. With UML state charts, you can provide industry standard diagrams that clearly define system behavior. Figure 3 shows an example of a simplified motion control state machine. The advantage of implementing our behavior using the state machine versus a flowchart approach is that we don’t need to check a bunch of flags using convoluted if/then/else spaghetti code. Additionally, the system only reacts to system events that matter based on the current system state. In this simplified example, there are only 11 possible states in which the axis can be at any given time. However, if we tried to manage the system with as few as, for example, 4 Boolean flags, then there are 16 possible system states. Each additional flag used to manage the state doubles the number of possible states, making unit and system maintainability, extensibility and testing difficult.

Verification

As mentioned, testing is critical when developing motion control firmware. In safety-critical systems, this is more formally referred to as verification. The verification process requires written detail and proof that the system has passed testing. The verification process usually involves formal test plans and procedures to be written, reviewed and approved.

During the development of the test plans and procedures, engineers need to devise tests that ensure their device meets the requirements. For the motion control case, this is usually done using an external measurement device. I’m not suggesting we could eliminate external measurement, but our framework gives us another avenue for test. By using the internally measured data provided through the communication interface, we have an additional means to test and troubleshoot the system. If internally measured data can be verified, the motion control system can be considered self-validating once you take into account the need for system calibration. This is a valuable outcome. The foregoing is presented as a basis for developing a framework when designing motion control firmware. With a little forethought, planning and good design practices combined with realizing the need for development and test tools, an extensible code base can be developed for creating safe motion control firmware. This firmware will not only be reused for varying needs, but it can be properly tested and maintained into the future. Netrino Columbia, MD. (866) 783-6233. [www.netrino.com].

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Untitled-1 1

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System Integration MOTION CONTROL AND SAFETY

Machine Vision Passes the Bucket Coordinating motion with machine vision presents a number of unique challenges. A real-world example shows some of the expected and unexpected considerations that must be built into a system for even a very specific set of actions. by Ben Dawson, Dalsa

U

nloading empty paint buckets from a pallet and placing them on a conveyer line for filling is fast-paced, stressful and tedious work. One worker moves pallets from a truck, clips retaining straps, and rolls pallets into reach of the other worker. The other worker sweeps or grabs buckets and puts them onto the conveyer to the fill stations. This de-palletizing process was a “pinch point” in a paint manufacturer’s production line—if the workers could not keep pace the line stopped. So the paint manufacturer asked Faber Industrial Technologies to design and build an automated de-palletizing system using Dalsa’s machine vision components. As before, pallets are prepared and rolled into a safety cage by one worker, but the eyes and hands of the other worker are replaced by a machine vision system

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and a robot with custom “end effectors”— the robot’s “hands”—to unpack and pass buckets to production. In comparison to our human abilities, this task seems easy to do, but is really quite challenging. A pallet of cans is a stack of materials. The top layer is a “picture frame” of wood that, when bound with retaining straps, holds the layers of cans in place without damaging them. Each layer of cans starts with a protective sheet of cardboard. There are 56 cans in each layer and up to 6 layers of cans on a pallet. The bottom of the stack is the pallet itself. Each of these layers needs to be “seen” by the vision system in order to be picked up by the robot’s end effectors. To do this, the camera is mounted so it is looking down on the stack. The robot puts cans on the production line conveyer, and packing material in piles to be recycled (Figure 1).

When a new pallet is brought in, the vision system finds the position of the “picture frame” and directs the robot to remove it. Then the robot removes a layer of protective cardboard and the vision system finds the position of each can. Individual cans that are more than a few inches out of packed, hexagonal grid position are a problem, as we shall see. Once all the cans in a layer are found, the robot arm’s end effectors pick up half the cans in that layer at a time and place them on the conveyer for filling. The stack of cans is about 6 feet high when first seen, but shrinks to about 8 inches high when all the cans are removed. Thus the vision system camera must adjust to focus on the current layer of cans. When the pallet itself is finally exposed, the robot uses another of its end effectors to pick up and remove the pallet. The first step in any machine vision solution is to select lighting that emphasizes important part features and suppresses unwanted details. In this application the vision system is in an open-mesh safety cage and is therefore subject to uncontrolled, ambient illumination. Bright lights were positioned at an angle to the can tops to “wash out” most of the influence of ambient illumination. This results in images with bright ovals where the can rims reflect the light and dark centers for the insides of the cans. The lens is specified by the field of view (FOV), the working distances and the camera specifications. The pallet stack is 48 x 40 inches (width x height), but a slightly larger field of view, 58 x 44 inches, is used to allow for skew in a layer of cans and variations in the location of the pallet. Optical magnification, M, is the camera’s sensor size (SS) divided by the FOV, so M = SS / FOV = 0.00429. The lens must reduce the FOV by about 233 times to fit into the sensor size. The working distance (WD) is the distance from the camera to the top of the pallet stack. If the camera looks straight down on the pallet stack, the WD is about


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48 inches. The lens focal length = WD * M / (M + 1), where M is the magnification computed above. This gives a lens focal length of 5.2 mm.

the can rims) and image contrast as layers of cans are removed. Optical distortions due to the lens and perspective distortion are corrected by

3

2

4

1 ROBOT

Figure 1 Pallets of cans roll into the safety enclosure (1). The pallet position and can positions are determined by the camera (2) and vision system. The robot arm’s end effectors (3) pick up half the cans in a layer of 56 cans and put them onto the conveyer (4) to the fill line.

PC Interfaces Supporting all PC interface standards For demanding control applications as well as for mobile analyzing and maintenance tasks Windows 2000/XP/Vista drivers included (Linux/RTOS on request)

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IXXAT Inc. 120 Bedford Center Road · Bedford, NH 03110 Phone: 603-471–0800 · Fax: 603-471–0880 www.ixxat.com

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5.2 mm is a very short focal length so the lens is a “wide angle” lens, and wide angle lenses distort the image. You might have seen images taken with a “fish eye” lens, which is an extreme example of a wide angle lens. If you are trying to visually guide a robot’s “hands” into cans to pick them up, this optical distortion is a problem. As mentioned, the camera focus must change as layers of the pallet stack are removed. This application also had to contend with perspective distortion, the apparent decrease in object size as a function of 1 / WD. Longer focal length lenses greatly reduce these problems. To use a 25 mm focal length lens the working distance must be about 20 feet; however, this would not work due to the plant ceiling height. Therefore, to increase the working distance and to get the camera out of the reach of the moving robot arm, the camera and lens were mounted on the ceiling to one side of the pallet stack. This introduced more perspective distortion. The lens used is designed for surveillance and has motorized settings of focal length (zoom), focus and iris so that the vision system can adjust the field of view, focus (on

building calibration tables for each layer of cans and for each can in a layer. The rims or interiors of the cans are used to find the center position of each can in a layer, and then the calibration tables are applied to correct the center position for the optical and perspective distortion (Figure 2). Dalsa’s Sherlock machine vision software finds the can rims or the dark “blobs” that indicate can interiors. Because of the somewhat uncontrolled lighting, both methods are used at different pallet stack levels. The vision system then reports the location of can centers to the robot and the robot end effectors are positioned so they insert into the cans. The end effectors expand to grasp the cans from the inside, and the cans are lifted by the robot arm and placed on the fill line conveyer. To find the rims of the cans an “edge detector” is applied to produce an image that only shows the edges of objects. Then a circle Hough transform is applied to accumulate edges that could be part of a circular can rim. The Hough transform is a voting scheme. Each edge pixel “votes” as to what circles it could be a part of and the votes are tallied in an “accumulator space.” Peaks in this ac-


system integration

cumulator space indicate circles with a “winning” number of votes. The Hough transform is robust to image noise but requires significant computation time. The center of the can opening is returned by the Hough transform. The radius is also returned but not used. When the lighting gives dark interiors for the cans, these dark areas are detected using connectivity analysis, often called “blob analysis.” An intensity threshold is applied to the image so that the interior of the cans is mapped to 1 (or some non-zero value) and the rest of the image is set to 0. Then areas of connected (“touching”), non-zero pixel values are found. The center of gravity of a “blob” of connected pixels is the center of a can’s opening (Figure 3). The end effectors on the robot arm are mechanically complex and constitute a large part of the design effort. The can pick-up end effectors are on a fixed, hex-

Industrial Ethernet Module

agonal grid to match the pattern of cans on the pallet. This means that if a can is more than a few inches off of this hexagonal grid, it might be hit when the robot is trying to insert the pick-up end effectors into the cans. The assumption here was that delivered cans could have layers skewed with respect to other layers, but would have no cans more than an inch or two off of the hexagonal grid alignment. The failure of this assumption was shown when the end effectors came down on the grid of cans and crushed cans or sent cans that were off the grid flying. No one was eager to redesign the end effectors to allow more can position tolerance, and having the robot pick up one can at a time would have been too slow. Three measures were taken to reduce the “bucket kicking” problem. First, the remaining worker had to push wayward cans into a tight packing after he

Complete real-time communication solution based on a FPGA module Available as module ready for operation, Design-In or universal IP-Core and protocol software solution For the quick and costeffective connection of devices to EtherNet/IP, PROFINET I/O, Powerlink, EtherCAT and SERCOS III networks Generic Host-API enables communication via shared memory or serial interface

Figure 2 In this image of a layer of cans, the vision system has marked can rims with green circles and the center of can openings with red crosses. The radius of the circles is not used.

IXXAT Inc. 120 Bedford Center Road · Bedford, NH 03110 Phone: 603-471–0800 · Fax: 603-471–0880 www.ixxat.com

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Industrial Box PC Showcase Featuring the latest in Industrial Box PC technology

Integrated Custom Systems

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Front panel filter door option, NEBS particulate filter media 3RU (or 2RU height) / 20 inch deep chassis One or two Quad-Core Intel® Xeon® CPUs Up to 96GB memory Up to eight removable 2.5” SAS or six SATA drives Dual redundant, hot-swappable power supplies Operational range: 0° to 55° C Shock - up to 25G @ 20ms Linux®, Sun® Solaris™ and Windows® OS support E-mail: info@themis.com Web: www.themis.com

Intel Pentium M 1.8 GHz-RAM1024 400 MHz processor system bus, conduction cooled Up to 1 GB DDR SDRAM with ECC Two Gigabit Ethernet ports via RJ-45 PC/104-Plus Expansion (PCI 32 bit, ISA 16 bit) Four USB 2.0 ports, Two RS-232 ports Power: 6...40 V DC, max 168W Windows XP E, Pro, CE 5.0, VxWorks, Linux, QNX IP52 Standard Conformance Operating temperature: –40°C to +70 °C ( to + 85 °C with 1.4 GHz ) E-mail: saugust@fastwel.com Web: www.fastwel.com

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Front panel filter door option, NEBS particulate filter media 1RU / 20 inch deep chassis One or two Quad-Core Intel® Xeon® CPUs Up to 32GB memory Up to three removable 2.5” SAS or SATA drives Dual redundant, hot-swappable PSUs Operational range: 0° to 50° C Shock - up to 20G @ 20ms Linux®, Sun® Solaris™ and Windows® OS support E-mail: info@themis.com Web: www.themis.com

CoolShell CS-3U Server Front-only cable and FRU access Total modular maintainability Two quad-core Xeon sockets Up to 64GB memory DVD, 2 x 2.5” HDD’s SSD option Seven independent 1Gb/s Enet NIC’s Copper or Fibre interface to NICs Twelve independent USB ports Up to three Graphics or DSP GPU’s Two hot swap 850W PSU’s

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system integration

CANopen Products and Services

Figure 3

CANopen Master/Slave protocol software for the development of embedded applications

Robot arm lifting 28 cans from a pallet (half the number in a layer) and onto the conveyer line. The green and yellow suction cups are used to remove the “picture frame” and the protective cardboard layers. “Claw” end effectors, not visible in this image, pick up and stack the pallet.

or she removed the retaining straps. Second, the vision system was improved to detect cans more than a few inches off the hexagonal grid and stop the robot from trying to pick up these cans. Then the worker goes into the safety cage to straighten out the cans, which halts the robot. These two measures reduced can alignment problems, but the robot still occasionally stops, and this can stop the filling line. The last measure was to require the producer of the empty cans to be more careful about the packaging and shipping of the cans so that off-the-grid experiences were reduced. One suggestion, yet to be implemented, was to add horizontal strapping on each can layer in addition to the vertical strapping between the “picture frame” and the bottom pallet. As engineers, we enjoy solving the hard problems while not paying attention to assumptions that seem “obvious” and so are less interesting. As we have

seen here, these unexamined assumptions are often the ones that come back to bite you.

Windows driver API and PC interfaces for PC based CANopen Master applications

DALSA Corporation Billerica, MA. (978) 670-2002. [www.DALSA.com].

Tools for configuration, testing and analyzing Consultation, implementation and development services

IXXAT Inc. 120 Bedford Center Road · Bedford, NH 03110 Phone: 603-471–0800 · Fax: 603-471–0880 www.ixxat.com

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ploration your goal k directly age, the source. ology, d products

INDUSTRY

WATCH

EMBEDDED DATA INTEGRITY

Building Fault Tolerance into Embedded Data Management Maintaining data integrity in embedded applications while also ensuring 24/7 operation is a complex challenge, especially when the constraints of real-time performance are added.

by Duncan Bates, Birdstep Technology

S

mall resource-constrained applicaTransaction Journal tions are getting so complex that we BEGIN can’t even start comparing the re... quirements from 10 years back with what COMMIT Consistent BEGIN Database we see today. Nonetheless there has been Deduct from checking Image Add to savings a trend of implementing homegrown data COMMIT managing solutions for both volatile and persistent storage media. Building fault tolerance into these devices was not much Figure 1 of asolutions requirement nies providing now back then, but it is now The complete database image. increasingly demanded byyour thegoalend ion into products, technologiesbeing and companies. Whether is to research the latest ation Engineer, or jump to a company's page, the goal of Get Connected is to put you customers. Today technical we expect embedded you require for whatever type of technology, applications to recover from any power your data on disk and other parts in memand products you are searching for. failure in addition to operating 24/7 with- ory, add an efficient data indexing subsystem, manage concurrent access to the data out system downtime. No matter the fault tolerance require- across multiple threads and applications, ment, building transactional or replication and implement an elaborate data caching capabilities into the data management so- system to avoid I/O overhead and increase lution is a complex task and should only performance—to mention a few. By now be attempted if you have time to spare, this amounts to a sophisticated piece of money to waste, and can live with an in- software if you need to cope with the fault ferior application. The fact of the matter tolerance scenarios for the embedded apis that data management can get compli- plications in addition to the other data recated. You may want to manage parts of quirements. The first piece of the fault tolerance Get Connected puzzle is the ability to recover from any with companies mentioned in this article. application or power failure. Making sure www.rtcmagazine.com/getconnected that the data is not corrupt or that the loss

End of Article

40

JUNE 2009 RTC MAGAZINE Get Connected with companies mentioned in this article.

of data hasn’t been too great is usually the first requirement. Data management solutions implement this by supporting the Atomic, Consistent, Isolated and Durable (ACID) transaction model. As a familiar example of the “Atomic” concept, consider what happens when you enter the bank and instruct the teller to move money from your checking account to savings. The money transaction breaks down into two operations, deduction from one account and addition to another, and it’s important to both parties that both happen or that neither happens. This is what’s meant by Atomic and is normally implemented through a data journaling system. Figure 1 shows the current state of the database. Some of the information is in the consistent database image and the rest is in the transactional journal. But also note that the atomic operations are wrapped in Begin and Commit marks. “A” in ACID is ensured by having flushed the Commit mark to persistent storage. The property of consistency is ensured by the data engine aborting transactions that break with any defined rules. Say you define a rule that the checking ac-


INDUSTRY WATCH

count can’t drop below $0. If the money transaction above violates this rule the system would automatically invalidate the transaction and revert back to the previous state of the database through the journal. Now let’s add your spouse to the equation, who is tapping into an ATM to view the balance of your accounts just as you’ve instructed the teller to move the money. We will need to make sure that only the state of the two accounts prior to your request or the states after are visible. This is called transaction isolation and is also achieved by only offering the state of the database based on the image and the committed transactions. Lastly, the durability property means we can’t accept the money transfer if power was lost or an application crash happened at an inconvenient time. There are different ways to accomplish this but simply put, we must at all times ensure that we have the information to either replay transactions or reinstate the old state of the database image. This process relies on quite a bit of disk I/O and disk cache flushing to guarantee crash recovery. Implementing the four properties becomes quite complex and you will additionally want to have the flexibility of relaxing some of these properties for some operations in order to trade off safety with speed, etc., adding even more complexity to the transaction system that needs to be in play to build fault tolerance into your application.

No Errors from Downtime

The second piece to the puzzle is 24/7 operations. An identical secondary copy of the system, including the data, needs to be available to be able to hand over operation to a failover card in case of unplanned or planned downtime of the primary system. From a data management standpoint there are a few tricky functions that need to be available. First we need to have the ability to move the transactions over to the secondary system in real time in case of downtime. Second, when a planned upgrade is made, the system will

need to deal with migrating transactions between two different versions of the database image. The latter is referred to as a hitless upgrade and is important to ensure 24/7 operations even if the system is not encountering a fault but rather a controlled system upgrade.

Consistent Database Image

the system handover will hit a system with transactions lacking. This rather high-level discussion should trigger thinking about all the details of fault tolerance and what they mean to your data management. It rapidly becomes apparent that this is a complex

Transaction Journal

Transaction Journal

BEGIN ... COMMIT BEGIN

BEGIN ... COMMIT

Consistent Database Image

Deduct from checking Add to savings

COMMIT MASTER SYSTEM

SLAVE SYSTEM BEGIN

Deduct from checking Add to savings

COMMIT

Figure 2 Data replication.

Figure 2 illustrates a real-time replication of an ACID transaction. Implementing real-time transactional replication can be done in two ways, asynchronously and synchronously. If the application needs to guarantee that both database copies are in sync you’ll need a synchronous replication solution. The effect of this is that the time to commit a transaction is the time it takes to get it into the master and the time it takes to move it over to the slave plus the time it takes to update the slave. In a synchronous replication environment the application will not regain control until both systems have been updated, which in most cases is not acceptable due to other performance requirements. An asynchronous model, which is the most common model, will queue the transaction up at the master when it’s committed and then return control to the application. The queued transactions will later get moved over to the slave followed by a slave update. The drawback is obvious. In an asynchronous model the slave may be delayed by a number of transactions, and in case of failure

task, especially if you combine it with other data management abilities required by the application. The solution is of course to start looking at third-party data management solutions. Solutions for these problems have been around for the last three decades, with a few recent startups that offer data management systems and libraries to handle the problems outlined. Basing your application on an established third-party product will increase the overall quality, at a fraction of the cost compared to in-house development. And of course it will get you to the market in a much shorter time than if you implement the solution yourself. Obviously we highly recommended that you consult with the embedded database specialists when faced with the challenges described in this article. Birdstep Technology Seattle, WA. (206) 748-5353. [www.birdstep.com].

RTC MAGAZINE JUNE 2009

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products &

TECHNOLOGY 10 GigE Switches Provide IP Carrier Class Routing on 6U cPCI, VME and VPX

A family of switches supports jumbo frames, full-wire speed Layer 2 bridging as well as Layer 3 Unicast and Multicast engine forwarding, all running at full data rate. In addition, the fully managed IPv4/IPv6 ComEth4300a 10 Gigabit Ethernet (GigE) switches support Layer 2 through Layer 4 advanced traffic classification, filtering and prioritization. This makes them suitable for data security services that require strict priority data trafficking as found in time-sensitive or critical applications. Designed for demanding networking applications and built on the latest generation of Marvell’s Prestera GigE packet processors, the new family of Gigabit Ethernet switches ranges from 24 to 28 ports, up to four of which can be 10 Gigabit. The automatic MAC address management, auto-negotiation, auto-polarity and auto-crossover on each port make the ComEth4300 family truly plug-and-play. The ComEth4300 family provides a routing capacity of 125 million packets per second. The switches easily fit in standard 6U CompactPCI systems, comply with the PICMG 2.16 standard and come in standard, extended and conduction-cooled grades. VME and VPX versions, compliant with VITA standards 31.1 and 46.20 respectively, of the ComEth4300 switches will also be available. An onboard PowerQUICCIII processor handles all the management functions and the protocol processing, including L3 routing and setup, and additional L4 services. Interface Concept’s onboard Switchware software manages all the traffic routing and packet processing. The entire system can be monitored from a browser, SNMP or CLI. Some additional functions are provided including configuration of all PHY and switch parameters, port monitoring, static MAC addresses, VLAN control and statistical counter. The switches are fully compatible with other Interface Concept ComEth switches, including the 4000a, 4020a, 4030a, 4050a versions. Pricing starts at $8,995 at quantity 1 for a standard-grade board. ACT/Technico, Warminster, PA. (215) 956-1200. [www.acttechnico.com].

High-Resolution DualChannel ADC FMC Card for Rugged DSP Apps

Designed for use in demanding DSP applications such as signal intelligence (SIGINT), electronic counter measures (ECM) and radar, a high-resolution FPGA Mezzanine Card speeds and simplifies the integration of FPGAs into embedded system design by providing high-bandwidth I/O direct to the host card’s FPGAs. The ADC511 from Curtiss-Wright Controls Embedded Computing is an FMC/VITA57 dual-channel analog-to-digital converter card designed to eliminate data bottlenecks and increase DSP subsystem performance by routing high-speed ADC I/O directly to the host board. Available in both air-cooled and conduction-cooled rugged versions, the ADC511 has two onboard 14-bit 400 MHz Texas Instruments ADS5474 ADC devices. Each of the module’s ADCs supports a sampling rate up to 400 MS/s, within an analog bandwidth of >1.7 GHz, and provides 14-bits of digital output. By routing the ADC device interfaces directly to the FMC connector, the ADC511 enables an FPGA on the host board to directly control and receive data. A choice of sample clock sources is provided, including an onboard source that supports sampling rates of 300, 320 and 400 MS/s, as well as the ability to utilize an external sample clock. Input and output triggers are provided enabling the number of input channels to be increased by synchronizing multiple ADC511 modules. Curtiss-Wright Controls provides HDL design reference code for the ADC511 to simplify and speed integration into the HDL development suite for Curtiss-Wright FPGA host boards. Pricing for ADC511 starts at $5,000. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (613) 254-5112. [www.cwcembedded.com].

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MONTH JUNE 2009 2009RTC RTC MAGAZINE MAGAZINE

Low-Cost, LowPower Processor AMC Boosts Embedded Communications

A processor AdvancedMC (PrAMC) features the Intel EP80579 Integrated Processor with Intel QuickAssist Technology and up to 4 Gbytes of ECC DDR2 memory and is targeted for use as coprocessor or host processor for embedded communication applications. The PRM-110 from JumpGen Systems supports up to 5 GigE links including 2 Front Panel and 3 routed to the AMC connector. It may be deployed with 600 MHz, 1.066 GHz, or 1.2 GHz processors to serve and is available with integrated accelerators that support Intel QuickAssist Technology through software packages provided by Intel. The software drivers enable acceleration of cryptographic and packet processing for VPN/firewall and unified threat management, wireless and WiMAX access applications, and SMB and home network attached storage applications. Additional features include a PCI Express x4 Interface to Fat Pipes Lanes 4-7 (AMC.1, Type 4), dual GigE interfaces to Common Options Lanes 0 and 1 (AMC.2 Type E2) and a single GigE interface to Fat Pipes, Lane 8 (AMC.2, Type 1). Dual SATA interfaces to Common Options Lanes 2 and 3 (AMC.3) are also provided. The front panel I/O includes Dual 10/100/1000BaseT Ethernet, RS-232 Serial and USB. The PRM110 is available in both full and mid-size AMC configurations for AdvancedTCA (ATCA), MicroTCA and proprietary architecture systems. Unit pricing for a range of configurations is expected to be under $1,000. JumpGen Systems, Carlsbad, CA. (760) 931-7800. [www.JumpGen.com].


PRODUCTS & TECHNOLOGY

Switching Power Manager with USB On-The-Go & Overvoltage Protection

A family of power manager ICs for single-cell Li-Ion/Polymer battery-based applications features a bidirectional switching power manager that can power an application and charge the battery from USB. Operating in reverse, the same switching regulator can take power from the battery to generate 5V and deliver up to 500mA for USB On-The-Go (OTG) applications without any additional components. Targeted at applications such as media players, personal navigation devices, digital cameras, PDAs and smart phones, the LTC4160/-1 from Linear Technology includes automatic load prioritization when powered from USB, input overvoltage protection, a stand-alone battery charger, and an ideal diode, all in a compact, ultra-low profile (0.55 mm) 3 mm x 4 mm UTQFN package. The LTC4160-1 offers a 4.1V battery float voltage allowing high temperature safety margin, while other family member, the LTC4160, features a 4.2V final charge voltage for optimized battery run time. The on-chip switching regulator also features programmable input current limits of 100 mA and 500 mA for enhanced USB compatibility, as well as a wall adapter input current limit setting up to 1.2A. For fast charging, the LTC4160/-1 converts nearly all of the 2.5W available from the USB port to charging current, enabling up to 600mA of charge current from a 500 mA limited USB supply and up to 1.2A of charge current from a wall adapter. The device provides an overvoltage protection (OVP) control circuit that prevents damage to its input from the accidental application of high transient voltages. The OVP circuit can protect the USB port even when the IC is providing power for USB. Pricing starts at $2.85 each for 1,000-piece quantities. Linear Technology, Milpitas, CA. (408) 432-1900. [www.linear.com].

COM Express Reference Carrier Board Is Compatible with New PICMG Design Guide

1U Accelerator Expansion System Supercharges Performance

Following closely on the heels of the release of the PICMG COM Express Carrier Design Guide, a new version of the Express-BASE Reference Carrier Board for Basic Form Factor Type 2 COM Express modules has been announced by Adlink Technology. The reference board, in standard ATX size, allows system designers to emulate the functionality of a desired end product with their chosen COM Express module and add on cards to get a head start on software development and hardware verification. The PICMG COM Express Carrier Design Guide is a 150-page document that provides information for designing a custom carrier board for COM Express modules. The design guide includes reference schematics for the external circuitry required to implement the various COM Express peripheral functions, explains how to extend the supported buses, and how to add additional peripherals and expansion slots to a COM Express-based system. The Adlink Express-BASE is a reference carrier board for Basic Form Factor Type 2 COM Express modules in standard ATX size that allows system designers to emulate the functionality of the desired end product with their chosen COM Express module and get a head start on software development and hardware verification. The latest version of the Adlink Express-BASE is fully compatible with the design practices described in the PICMG COM Express Carrier Design Guide and provides a full complement of I/O interfaces, debugging tools and peripheral devices (such as Super I/O and an audio codec) that may be required on the custom carrier board. The full schematics and mechanical drawings of the Express-BASE are available for download from the ADLINK website (as well as the PICMG COM Express Carrier Design Guide), to allow customers to immediately begin their own carrier board design effort.

A new 1U accelerator expansion system employs either the AMD FireStream 9270 or 9250 graphics processor-based accelerator boards to provide a system tailor-made for high-end computational applications. The 1U 9270 from One Stop Systems contains one or two AMD 9270 boards while the 1U 9250 system employs up to four AMD 9250 boards. The 1U accelerator expansion system is equipped with a PCIe x16 Gen 2 host cable adapter that installs in a host computerâ&#x20AC;&#x2122;s PCIe x16 expansion slot, delivering data transfers of up to 80 Gbits/s to the host system. A 1-meter standardized PCIe x16 cable is included. The GPU expansion system offloads the host CPU engines and will be used by research laboratories, video imaging systems and gaming applications. The new product family supports maximum compute density in the datacenter, allowing users to deploy up to 4 single-precision TFLOPS and 800 double-precision GFLOPS of compute performance. The 1U rack-mountable system can be installed within up to 10 meters of its host system using the standard PCIe cable. Greater distances from the host system can be accommodated using a fiber optic version, to be released by OSS later this year. Vital system functions like fan rotation, power voltages and temperature can be remotely monitored through Ethernet, making the solution easy to manage in large datacenter environments. The AMD FireStream provides up to 1.2 TFLOPS raw single precision performance and up to 240 GFLOPS raw double precision performance. That amounts to over 8 GFLOPS per watt of single precision performance potential. AMD FireStream 9270 is a dual-slot solution with 2 Gbyte GDDR5 memory and up to 1.2 TFLOPS single precision and 240 GFLOPS double precision floating point performance. AMD FireStream 9250 is a single-slot, lower power solution with 1 Gbyte GDDR3 memory and up to 1 TFLOPS single precision and 200 GFLOPS double precision floating point performance. The 1U 9250-4 Accelerator Expansion System with four FireStream 9250s lists for $7,495. OEM quantities can be quoted on request.

ADLINK Technology, San Jose, CA. (408) 360-0200. [www.adlinktech.com].

One Stop Systems, Escondido, CA. (760) 745-9883. [www.onestopsystems.com].

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PRODUCTS & TECHNOLOGY

RISC Embedded Computing with Rich I/O and Windows CE 6.0

A system based on the Atmel AT91SAM9263 processor delivers RISC computing power in a compact, rugged package that is packed with a wealth of I/O features and uses the latest embedded software environment. Boasting a 32-bit ARM instruction set for maximum performance, the Relio R9 from Sealevel Systems is a suitable platform for embedded applications requiring small size, wide operating temperature range and flexible I/O connectivity. Available with up to 256 Mbyte RAM and 256 Mbyte flash memory, the I/O features of the Relio R9 extend the possible uses beyond traditional ARM applications. Standard I/O includes Ethernet, serial, USB, CAN Bus, digital and analog interface. For local or remote I/O expansion, the Relio R9 connects to Sealevel SeaI/O modules via the dedicated RS-485 expansion port and communicates via RS-485 Modbus RTU. To provide a fast time-to-market, the Windows CE 6.0 BSP binary and low-level drivers for system I/O are included. Additionally, the R9 software package is equipped with the Sealevel Talos I/O Framework, which offers a high-level object-oriented .NET Compact Framework (CF) device interface. This interface provides an I/O point abstraction layer with built-in support for the specific needs of analog and digital I/O such as gain control and debouncing. The Relio R9 is housed in a rugged, small enclosure suitable for mounting almost anywhere and is rated for a full -40°C to +85°C operating temperature range. The Relio R9 is priced from $599, and a QuickStart Development Kit is available. For applications with specialized hardware requirements, system designers can use the Relio R9 as a platform for application development while a customized target system is designed for specific application requirements. Sealevel Systems, Liberty, SC. (864) 843-4343. [www.sealevel.com]

Compact, Rugged PC/104-Plus SBC Rolls

Fans are frowned on in harsh environment applications. They represent a single point of failure that’s not worth the risk. Offering its latest fanless SBC solution, VersaLogic began shipping a new PC/104-Plus SBC called the “Manx”—a mid-range SBC featuring a highly efficient AMD Geode LX 800 processor. The product is function and pin-out compatible with VersaLogic’s older Puma SBC, offering customers a higher performance migration path from that popular product. The new Manx incorporates mid-range processing speed (500 MHz) with very low power consumption (less than 5W). The ACPI suspend-toRAM state feature reduces power draw to an incredible 0.2W between active sessions. This high-reliability fanless design is available in both standard (0° to +60°C) and extended (-40° to +85°C) temperature versions. The Manx has standard onboard features that include 256 Mbytes of soldered-on DRAM, 10/100 Ethernet, four USB 2.0 ports, LPT port, IDE interface, three COM ports and analog audio. A CompactFlash socket provides reliable, high-capacity onboard storage with no moving parts. The PC/104-Plus expansion interface supports both ISA and PCI add-on modules. The Manx will be available in production quantities in June. Pricing is about $550 in OEM quantities. VersaLogic, Eugene, OR. (541) 485-8575. [www.versalogic.com].

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Network Appliance Utilizes Latest Intel Xeon 5500

A new server-grade network appliance features a 2U rackmount chassis, dual sockets for the Intel Xeon processors E5540 or E5504 with an integrated memory controller, highspeed Intel QuickPath Technology link connections between the two processors as well as Intel Turbo Boost, Virtualization and HyperThreading Technologies. The NAR-7100 from American Portwell also features the associated Intel 5520 I/O Hub to meet high-performance computing requirement with up to 36 PCI Express Gen2 lanes. Ten DDR3 memory DIMMs support up to 80 Gbytes system memory. The new NAR-7100 not only provides high CPU computing performance, but also supplies high Ethernet performance using PCI Express Gen2 solution.

The NAR-7100 2-socket, 2U rack network appliance provides maximum performance while supplying a variety of Ethernet interfaces and Ethernet ports, helping reduce energy and deployment costs. The high concentration of computing power and redundancy makes the NAR-7100 an appropriate choice for high-performance networking applications. The appliance supplies the necessary computing power for UTM, IPS, IDS, Anti-virus, Firewall, VPN, Content Filtering and much more to enhance our customers’ applications. Customers using traditional Copper or Fiber modules can now choose the NAR-7100’s programmable bypass module. In practice, the programmable bypass mode allows network packets to flow in and out unattended when the appliance is shutting down. The programmable next bootup status means that the Bypass or Open mode can be determined in advance before a system shuts down. This means that the system can be predetermined to reboot to the preferred status and is immediately ready to serve. Bypass mode status can be changed instantly by software commands. Each Bypass segment has its own WatchDog Timer (WDT), therefore bypass behaviors can operate independently. American Portwell, Fremont, CA. (510) 403-3399. [www.portwell.com].


PRODUCTS & TECHNOLOGY

USB 3.0 Automated Compliance Test Package

An automated compliance test package for USB 3.0 (SuperSpeed USB) is available for use on the recently released WaveMaster 8 Zi Oscilloscope platform from LeCroy. QualiPHY USB3 provides SuperSpeed USB physical layer compliance testing according to the USB-IF Electrical Test Specification, and more importantly, enables rapid debugging of compliance failures to identify the root cause of serial data problems. QualiPHY USB3 features automated oscilloscope control for accurate measurements, connection diagrams showing the proper setup for each test, and report generation available in HTML, XML or PDF formats. In addition, integration with LeCroy SDA II and Eye Doctor II analysis software ensures that the challenges that come with the faster data rate and unique capabilities of SuperSpeed USB are addressed easily and accurately. QualiPHY USB3 uses LeCroy SDA II analysis software to display eye diagrams and jitter decomposition 50 times faster than other solutions, and contains integrated jitter and timing analysis for clock and data signals. It allows analysis of data up to the memory limit of the oscilloscope. LeCroy Eye Doctor II analysis software allows the user to view his signal after Continuous Time Linear Equalization (CTLE) and Channel Emulation. QualiPHY USB3 uses this functionality to create the eye diagram and measure the jitter after CTLE as required for SuperSpeed USB compliance. The Price for the QPHY USB3 Software Option is $1,500.

PC/104-Plus SBC Sports 1.60 GHz Atom CPU

The Atom processor is quickly pushing aside the idea that PC compatibly means suffering with high power consumption. Advanced Digital Logic has released its ADLS15PC, which is based on the Intel Atom (Z510, Z530) and the IntelUS15W (Poulsbo) chipset. The Intel Atom is a single core processor built on a 45nm process that boasts an impressive 2.0 watts TDP (Intel) for the CPU. This processor delivers the benefits of genuine Intel architecture to a small form factor for low-power, thermally and space-constrained markets. The ADLS15PC takes advantage of these features by delivering high performance and low thermals in a compact, single board PC/104-Plus form factor. Memory is added via an SODIMM200 socket that will accept up to 2 Gbytes of DDR2-400/533 DRAM. In addition to ACPI/APM functions, the ADLS15PC provides EIDE, 8xUSB 2.0, 2xRS232 COM ports, PS/2 keyboard and mouse, LPT, 7.1 HDA Audio, 10/100/1000 Mbit LAN and more. The ADLS15PC can also come equipped with an onboard Solid State Disk (SSD) of 2 or 4 Gbytes. With the use of ADLâ&#x20AC;&#x2122;s advanced conductive and convective thermal solutions engineered for the Atom design, the boards can be placed in nearly any application under environmentally demanding conditions. Advanced Digital Logic, San Diego, CA. (858) 490-0597. [www.adl-usa.com].

LeCroy, Chestnut Ridge, NY. (800) 553-2769. [www.lecroy.com].

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PRODUCTS & TECHNOLOGY

Data Translation Announces New Technology in Precision Measurement

Extremely high accuracy in analog voltage readings regardless of the environmental conditions is possible with instrumentation using proprietary ISO-Channel technology. The VOLTpoint and TEMPpoint instruments from Data Translation use galvanic isolation to guarantee 1000V isolation between each sensor input. The result is that accuracy is preserved on all input channels. ISO-Channel technology offers increased reliability over older relay front-end designs prone to system failure, by implementing a separate DC/DC Converter on each 24-bit A/D converter for all 48 channels. Common mode noise and ground loop problems are eliminated with ISO-Channel design. Sensors at varying ground reference are individually referenced to their own level even at vastly differing voltages, including transients to thousands of volts. The all solid-state design provides digital transfer of valuable sensor data with optical and transformer isolation. The result to the user is preserved accuracy on all sensor inputs without regard to grounding conditions. VOLTpoint is a precision measurement instrument designed and newly enhanced for measuring a wide range of voltage inputs of ±10V, ±100V and ±400V. Applications include HybridElectric Vehicle (HEV) battery performance, Li-ion Cell measurements, High voltage, precision battery stack, or cell balance measurements and battery back-up monitoring among others. TEMPpoint is a series of temperature measurement instruments designed for high accuracy and industrial robustness. These instruments allow direct thermocouple, RTD and precision voltage or resistance measurements with a PC. Temperature and voltage values can be viewed, graphed, or exported to Excel, and allow limit checking for control or monitoring of a manufacturing process. Pricing for VOLTpoint and TEMPpoint begins at $3,195 and both are available immediately in USB and Ethernet versions. Data Translation, Marlboro, MA. (508) 481-8620. [www.datatranslation.com].

PCIe-to-CompactPCI/PXI Expansion Kit in a 6U Chassis

A new PCIe-to-6U CompactPCI/PXI expansion kit from Adlink Technology includes the company’s PCIe-8560 PCI Express host board, the PXI-8656/6U remote system controller and an expansion cable. Adlink’s family of bus expansion products includes PCIe-to-PCI, ExpressCard-to-PXI/PCI, PCI-to-PCI/PXI, PXI-to-PXI, and now PCIe-to-6U CompactPCI/ PXI systems and kits for use in a wide range of applications. The PCIe-to-6U CompactPCI/PXI expansion kit is specifically designed for applications with high-density I/O requirements such as telecommunication systems, mass production testing and military/aerospace by providing direct control of 6U CompactPCI/ PXI modules via the high-bandwidth, low-latency PCI Express interface. The PCIe-to-6U CompactPCI/PXI expansion kit supports up to 7 devices in a remote 6U CompactPCI/PXI chassis. The control of the 6U CompactPCI/PXI chassis through the PCIe8560 PCI Express host board is transparent to software applications and drivers. All CompactPCI and PXI modules installed in the remote chassis will operate as if they are directly installed in the host system. Adlink’s 15-slot 6U CompactPCI/PXI chassis, the PXIS-3320, is also available for use as a remote chassis. The PCIe-to-6U CompactPCI/PXI expansion kit is currently available with a list price of $1,155. ADLINK Technology, San Jose, CA. (408) 360-0200. [www.adlinktech.com].

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HighDefinition XMC Video Interface Sports JPEG2000 Compression

A new interface for high-definition video with JPEG2000 compression provides an open standards-based high-performance solution for capturing, compressing, decompressing and displaying two channels of video at up to 1080p and 1920x1200 resolutions. Designed for demanding military video applications, the XMC-280 from Curtiss-Wright Controls Embedded Computing facilitates the design of systems that require the distribution or recording of video such as those in situational awareness applications. In real-time embedded systems JPEG2000 offers better quality than MPEG at higher compression ratios, and because each frame is compressed individually, there is no dependence on preceding or subsequent frames. This frame-byframe compression results in lower latency and greater resistance to errors in transmission. The JPEG2000 ISO/IEC15444-1 image compression standard (9/7 irreversible wavelet compression) provides visually lossless compression at ratios in excess of 10:1. Using the XMC-280, multiple channels of high-definition video can be distributed over standard Gigabit Ethernet networks in excellent quality and with minimal latency. Details are retained at 50:1 compression at which eight 1080p60 channels could be transmitted over a single Gigabit Ethernet. The XMC-280 is supported on Intel x86 and Power PC hosts under Windows, Linux and VxWorks, and as an industry-standard XMC-format module, it can be deployed in a variety of system types such as PCs and embedded rackmount displays. The XMC-280 includes two video inputs (each can be Digital DVI, Analog RGB or PAL/ NTSC composite) with up to 1920x1200 resolution at 60 Hz, and two DVI-D digital outputs. Captured video is compressed using a high-performance FPGA-based JPEG2000 algorithm or transmitted over PCIe interface uncompressed. In addition, there are two stereo channels (or four mono channels) of audio input/output that support 6-bit 48 kHz, WAV and PCM encoding. A Four-lane PCIe 1.1 interface is optimized to provide in excess of 500 Mbytes/s in each direction. Pricing for the XMC-280 starts at $5,000. Availability is Q3 2009. Curtiss-Wright Controls Embedded Computing Leesburg, VA. (613) 254-5112. [www.cwcembedded.com].


PRODUCTS & TECHNOLOGY

VXS Computing Module for Radar, SIGINT/EW and Industrial Apps

A platform for high-performance computing solutions in image, sensor and signal processing applications is being offered with the availability of the Ensemble 5000 Series VXS HCD5220 Dual 8641D Dual-Core Processing Module from Mercury Computer. The HCD5220 is the first of several new products from the VXS Ensemble 5000 Series product family designed to extend embedded, high-performance computing to a sensor-networked environment, enabling rapid access to critical information from distributed sensors via the Converged Sensor Network (CSN) Architecture. The HCD5220 combines two Freescale 8641D PowerPC processors with dual PMC/XMC mezzanine sites. For example, signals intelligence/electronic warfare (SIGINT/EW) applications are typically optimized for size, weight and power (SWaP) constraints. The HCD5220, when configured with Echotek Series Digital Receiver modules, allows up to eight channels of processing per HCD5220, doubling the channel count per slot compared to previously available systems. Additionally, the thermal design of the HCD5220 supports the faster 1.33 GHz 8641D processor in a standard 0.8"-inch VXS slot. These improvements result in an overall 2x increase in performance relative to currently available SIGINT/EW processor-digital receiver subsystems. For synthetic aperture radar/moving target indicator (SAR/ MTI) radar applications, the HCD5220 brings new heights to system-level processing performance while simultaneously simplifying application development. Scaling a chassis to 18 HCD5220 modules and two Serial RapidIO switch modules, the system offers two to three times more bisection bandwidth than mesh topologies of similar sizes, such as Mercury's previous generation of VPX products. For large systems, this increase in bisection bandwidth enables new and faster radar algorithm processing, as well as reduced system size, weight and cost. Ensemble Series software enables rapid deployment of customer applications across 3U VPX, 6U VPX and VXS form factors. Moreover, with identical hardware building blocks, the Ensemble products share identical Linux and VxWorks development and runtime environments. Customer applications for the HDC5220 can be easily retargeted for other Ensemble products. This allows users to have a single software code base, a protected investment in software algorithms, code portability, performance predictability and rapid deployment across multiple form factors. Entry-level versions in volume start at under $10,000.

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6/1/09 3:27:16 PM

CO C COT OTS OT OTS TS

RAID/SAN/NAS/VME

Phoenix International designs and builds rugged COTS Data Storage Systems that plug and play in any application -- from Multi-Terabyte Fibre Channel RAID and Storage Area Network configurations to plug-in Solid State Disk Drive VME/cPCI Storage Modules.

Mercury Computer, Chelmsford, MA. (866) 627-6951. [www.mc.com]. 4FFVTBUXXXQIFOYJOUDPNPSDPOUBDUVTBUtJOGP!QIFOYJOUDPN An AS 9100 / ISO 9001: 2000 CertiďŹ ed Service Disabled Veteran Owned Small Business

RTC MAGAZINE JUNE 2009 Untitled-2 1

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1/21/09 8:35:49 AM


PRODUCTS & TECHNOLOGY

3U CompactPCI Boards and Rack Family for Thermal Needs of Extreme Environments

Untitled-1 1

4/13/08 3:57:12 PM

Ideal for extreme temperature, shock and vibration environments

New!!

3.5" SCSI VME SATA VME SCSI Ultra3

MEN Micro, Ambler, PA. (215) 542-9575. [www.menmicro.com].

www.redrocktech.com

Call Toll-Free in the USA: 1-800-808-7837 or 480-483-3777 206 West Julie Drive, Suite 2, Tempe, Arizona 85283

A Leader in Mass Storage Solutions since 1993

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JUNE 2009 RTC MAGAZINE

A new, rugged 3U CompactPCI (cPCI) family consists of two single board computers (SBCs) and a rack that provide reliable performance in temperatures as extreme as -40°C and +85°C. In addition to the standard, convection-cooled F50P SBC, the new line from Men Micro includes the conduction-cooled F50C that easily fits into the new conduction-cooled rack. The new rack accommodates readily available, less costly 3U cards designed for ventilated systems, when mounted within conduction-cooled adapter frames and is designed for use in environments from -40°C to +85°C (-40°F to +185°F). Both the F50P and F50C SBCs offer the choice of either MPC8548 and MPC8543 PowerPC processors running at speeds up to 1.5 GHz as well as up to 2 Mbytes of SDRAM, 2 Mbytes nonvolatile SRAM, 128K nonvolatile FRAM and up to 16 Gbytes of flash solid state disk storage. Each board provides front- and rear-connection I/O options including a minimum of four USB ports, up to three 10/100/1000Base-T Ethernet channels and up to two SATA ports. Additional FPGA-controlled I/O, a standard on conduction-cooled models and optional on convection-cooled models, provides the extreme flexibility of up to 62 additional I/O lines for user-defined functions in application-specific needs such as graphics, touch screens, serial interfaces, fieldbus controllers and binary I/O. Both SBC styles, which feature soldered components to withstand shock and vibration, are designed for the added protection of an optional conformal coating. Each offers reliable system expansion using the full cPCI interface, or can be used as a busless stand-alone board with power supplied from the backplane. All versions run popular Linux, VxWorks, QNX, INTEGRITY and OS-9 operating system software. Convection-cooled SBCs are fitted with tailor-made heat sinks necessary for their environmental requirements—up to +85°C. When integrated into dedicated CCA (circuit card assembly) frames, they become conduction-cooled (F50C series) boards, available for stand-alone use up to +85°C or for installation in the new conduction-cooled rack. This frame design maintains 20% to 30% more usable card space than more costly card designs conforming to VITA 30.1. The 200 mm x 350 mm x 145 mm unit is equipped with three 3U cPCI slots for one CPU board with a side card and one I/O board, as well as a PSU slot with an H15 connector. It accommodates both front and rear I/O wiring of boards installed within the enclosure. Pricing starts at $1,637 for the F50C and $2,322 for the F50P. The conduction-cooled rack is $5,473.

6/17/09 9:20:33 AM


PRODUCTS & TECHNOLOGY

Controller Adds Graphics to StackableUSB

Using USB as a link for stacked embedded boards is the whole idea behind StackableUSB. Micro/sys satisfies the demand for graphical user interfaces in low-power, spaceconstrained embedded applications with the introduction of its new USB3201, a graphics controller and a compact 2.8-inch (320x240 pixel) color LCD, which comes with a highly modular, easy-to-use software package. Using StackableUSB, the USB3201 easily mates with small, energy-efficient microcontrollers operating off a 9V battery, as well as x86 and ARM SBCs, to provide OEMs complex 2D and simple 3D graphics within the popular 104 form factor. The USB3201 exemplifies USB’s ability to enable sophisticated, low-power systems across all CPU platforms. Powered by the Microchip PIC32 and the Microchip Graphics Library, the USB3201 can support multiple input devices. The user-friendly software package has an open documented interface for LCD driver support making it easy to interface to any LCD with the creation of a single low-level C file. With both a CPU and RGB interface, it is easy to accommodate an LCD with a maximum 480x272 WQVGA resolution. The USB3201 set including the controller and LCD touch screen starts at $265 in single quantity. Micro/sys, Montrose, CA. (818) 244-4600. [www.embeddedsys.com].

Open Frame TFT Displays Target CostSensitive Markets

Designed with advanced image inversion electronics, the new series of display products allows customers to use lower-cost twisted nematic (TN) TFT-LCDs for many applications that currently use more expensive, wide-viewing-angle TFT panels. The new I Series TouchScape displays from Smart Modular Technologies provide customers with more options to address cost pressures in kiosk, gaming, ATM and digital signage deployments. When a traditional TN TFT display is viewed from below, light areas become dark and dark areas become light. Known as “grey scale inversion,” this type of distortion effectively renders traditional TN TFT displays unsuitable for many applications that would be viewed from below, forcing OEMs to use high-cost, wide-viewing-angle TFT LCDs. With the I Series displays, OEMs can realize cost savings while still achieving the image quality required by their application. Available in 19” and 22” sizes, the TouchScape I series displays are available with impact-resistant glass, surface acoustic wave (SAW) and capacitive touchscreen options. Supporting USB 2.0 and RS-232 touchscreen controller interfaces, the new displays are IP65 capable, so they offer resistance to dust and water damage. SMART Modular Technologies, Newark, CA. (510) 623-1231. [www.smartm.com].

INDUSTRIAL I/O via Ethernet Monitor position & speed | Regulate fluid levels Measure temperature | Control motors & solenoids

SENSORAY’s data acquisition applications range from controlling cranes at shipping ports to controlling water pressure at laser jet cutting factories. We specialize in the development of devices for industrial sdioincluding nelos & srotEthernet, om lortnoC PC/104, deeps &PCI, noitiand sop roPCMCIA. tinoM applications on several buses, We support operating slevel diuPocket lf etalugPC/Windows eR erutarepmCE, et eReal-Time rusaeM systems which include Windows, Linux, OSs and QNX. We offer off-the-shelf, custom or modified solutions, live technical support and evaluations.

To learn more visit: SENSORAY.com, email: info@sensoray.com or call: 503.684.8005 Model 2426 | Industrial I/O via Ethernet

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10:51:05 AM RTC MAGAZINE 3/20/09 JUNE 2009


with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

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Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

www.rtcmagazine.com/getconnected

Company

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ACT/Technico

21

Website www.acttechnico.com

Advanced Micro Peripherals

17

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Advantech Technologies, Inc.

29

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Aitech Defense Systems, Inc. Products Apacer

33 47

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ARM Techon 3

35 45

Calculex

52

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Extreme Engineering Solutions, Inc.

13

www.xes-inc.com

General Micro Systems, Inc.

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Industrial Box PC Showcase www.rtcmagazine.com/getconnected Interconnect Systems Inc

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Discover these and other industry whitepapers at: www.rtcmagazine.com/whitepapers

www.avalue-tech.com Get Connected with companies mentioned in this article. www.birdstep.com www.rtcmagazine.com/getconnected www.bittware.com

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GetTechnology Connected with companies and Avalue products featured in this section. Birdstep Technology www.rtcmagazine.com/getconnected BittWare

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Vendor Whitepapers

www.ixxat.com

Linx Technologies, Inc

48

www.linxtechnologies.com

Micro/sys, Inc.

4

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National Instruments

2

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One Stop Systems

23

www.onestopsystems.com

Phoenix International

47

www.phenxint.com

Red Rapids, Inc.

14

redrapids.com

Red Rock Technologies, Inc.

48

www.redrocktech.com

Sensoray Company

49

www.sensoray.com

Technobox

16

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Themis Computer

27

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Twin Oaks Computing

26

www.twinoakscomputing.com

Vector Electronics & Technology, Inc.

11

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VersaLogic Corporation

51

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WinSystems

19

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“Switched Ethernet Latency Analysis” by GE Fanuc.

“Embedded Computers for Substation Automation” by Moxa

RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.

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JUNE 2009 RTC MAGAZINE


When You Design for the Extreme, Choose Your Partner Wisely. Did we mention “Reliability” is our middle name?

I

ndustrial equipment needs to perform awlessly, night and day, under even the most extreme conditions. Whether designing for the manufacturing oor, clean n room or the eld, you can depend on VersaLogic to deliver the highest quality embedded computer products, from prototyping and design-in, through years of product production. We design our boards for high reliability and long-term availability, then run them through exhaustive quality tests, ensuring that we deliver only the best. And with our world class service and ve year availability guarantee, we’ll always be there when you need us. Whether you need one of our standard products or a version customized to your needs, our skilled technical staff will work with t th you to meet your exact specications. Contact us to nd out how for more than 30 years we’ve been perfecting rfecting the ne art of extra-ordinary support and on-time delivery: One customer at a time.

1.800.824.3163 1.541.485.8575 www.VersaLogic.com/RTC


RTC Magazine - June 2009  

A Framework for Safe Motion Control Firmware

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