Page 1


in this issue

The magazine of record for the embedded computing industry

January 2007

CompactPCI Gr o w t h Tackles





Jeff Milrod:

"The Future Is in Small Form-Factors & Switched Fabrics"

An RTC Group Publication

Hybrid Backplanes •

Unite High-Speed Boards with Legacy Systems



Opens the Door to a World of Applications



• Brings out the Power of Multicore

GE Fanuc Embedded Systems

Add more security to your network applications. Control your network traffic with our Cavium-based packet processor. Administrators are increasingly turning to deep packet inspection at full Gigabit Ethernet line rates to control their network traffic. This level of control is necessary for managing traffic flows and security, and the Cavium Octeon™ is the chip of choice for these demanding high speed applications, including network address translation. With our single width AdvancedMC™ module, you can now create content-aware applications in one MicroTCA™ slot or AdvancedTCA® bay. This allows you to quickly build devices such as Session Border

Controllers, Media Gateways, Edge Routers, Firewalls and Video Services Switches to name a few. GE Fanuc Embedded Systems is a leader in AdvancedMC™ design with more than a dozen modules in production, including this Caviumbased packet processor which is already deployed in customer applications. So we can offer you the security you need to make your wired or wireless networks more secure.

Telum™ NPA-38x4 High-performance AdvancedMC packet processor

© 2007 GE Fanuc Embedded Systems, Inc. All rights reserved.

Departments 7

Editorial: EPCs on Our Foreheads? Where Will RFID Take Us?


Industry Insider

58 Products & Technology

Dual GB fabric switches w/10Gb uplinks

Up to 19 cluster processing and-or I/O blades

70 Publisher’s Letter

Features 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 a

Technology in Context

CompactPCI Growth

12 C  ompactPCI Thrives in Military and Aerospace Applications David Pursley, Kontron

18 C  ompactPCI − A Growing Alternative to COTS VMEbus Systems


Highly scalable embedded Ethernet network

PICMG 2.16 Chassis with I/O cluster processing and embedded Ethernet network. • Pg. 18

Reeves Mollman, Performance Technologies

22 C  ompactPCI / PICMG Standards on the Move: A Look at CPCI Express Valerie Andrew, ACT/Technico

Solutions Engineering

High-Speed and Hybrid Backplanes

Partition 1

Partition 2

Partition 3

Multiple address spaces

Multiple address spaces

Multiple address spaces

26 T rends in High-Speed Backplane Design David Helster, Tyco Electronics

30 D  esigning High-Speed Backplanes with PCI Express

Process A

Process 1 GUI

Process B

Process 2

100% binary compatible

100% binary compatible

100% binary compatible

Linux (MP aware)

RTOS (MP aware)

Windows (MP aware)

Industry Insight RFID Infrastructure




Steve Cooper, One Stop Systems User Mode Supervisor Mode

Separation Kernel (VMM)

34 S  upply Chain Management Challenges RFID Technology Ann R. Thryft, Senior Editor

36 R  FID Tag Data Security Infrastructure Strengthens Pharmaceutical Supply Chain

Hardware (Multicore CPU)

Virtualized OS architecture on a Multicore processor • Pg. 52

Joseph Pearson, Texas Instruments Radio Frequency Identification Systems

42 S  DR-Based Readers Keep Pace With Changing RFID Technology Margaret Wasserman, ThingMagic

Executive Interview 46 Never Underestimate the Ability of Good Engineers to Overcome Problems RTC Interviews Jerry Milrod, President & CEO of BittWare

Software & Development Tools Software for Multicore 52 S  oftware for Multicore Processors Arun Subbarao, LynuxWorks

Industry Watch 64 S  erial Attached SCSI Explodes into the Embedded Arena Matthew Knowles, PhD, Intel

Mid-Size AMC Card Enhances AdvancedTCA and MicroTCA systems • Pg. 58 January 2007

January 2007 Publisher PRESIDENT John Reardon, johnr@r VICE PRESIDENT, European Operations Zoltan Hunor, zoltanh@r EDITORIAL DIRECTOR/ASSOCIATE PUBLISHER Warren Andrews, warrena@r


EDITOR-IN - CHIEF Tom Williams, tomw@r SENIOR EDITOR Ann Thr y f t, annt@r MANAGING EDITOR Marina Tringali, marinat@r COPY EDITOR Rochelle Cohn


CREATIVE DIRECTOR Jason Van Dorn, jasonv@r PRODUCTION DESIGNER Kirsten Wyatt, kirstenw@r GRAPHIC DESIGNER Barr y Karsh, barr yk@r DIRECTOR OF WEB DEVELOPMENT Marke Hallowell, markeh@r WEB DEVELOPER Brian Hubbell, brianh@r

Advertising/Web Advertising

CALIFORNIA COASTAL ADVERTISING MANAGER Diana Duke, dianad@r (949) 226 -2011 WESTERN REGIONAL ADVERTISING MANAGER Lea Ramirez, lear@r (949) 226 -2026 EASTERN REGIONAL ADVERTISING MANAGER Nancy Vanderslice, nancy v@r (978) 443 -2402 EMEA SALES MANAGER Marina Tringali, marinat@r (949) 226 -2020 BUSINESS DEVELOPMENT MANAGER Jessica Grindle, jessicag@r (949) 226 -2012


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To Contact RTC magazine: HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, EASTERN SALES OFFICE The RTC Group, 96 Dudley Road, Sudbury, MA 01776 Phone: (978) 443-2402 Fax: (978) 443-4844 Editorial Office Warren Andrews, Editorial Director/Associate Publisher 39 Southport Cove, Bonita, FL 34134 Phone: (239) 992-4537 Fax: (239) 992-2396 Tom Williams, Editor-in-Chief 245-M Mt. Hermon Rd., PMB#F, Scotts Valley, CA 95066 Phone: (831) 335-1509 Fax: (408) 904-7214 Ann Thryft, Senior Editor 15520 Big Basin Way, Boulder Creek, CA 95006 Phone: (831) 338-8228

January 2007

Published by The RTC Group Copyright 2007, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

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Editorial January 2007

EPCs on Our Foreheads? Where Will RFID Take Us? by Tom Williams, Editor-in-Chief


he potential for radio frequency identification (RFID) is truly breathtaking. It will be possible to identify and track products not only by their lot numbers but also as individual items. That can potentially give industry and government agencies the ability to track, for example, contaminated medicines or food stuffs and prevent major health problems such as the recent E. coli scares we have read about. It will give manufacturers better control over inventories and their supply chains. It has already reunited pet owners with lost dogs and cats. It can help livestock ranchers track their herds and be used to potentially short circuit outbreaks of devastating sicknesses such as mad cow disease. But RFID is more than just a chip that can be read by a stationary sensor or a handheld reader. It involves infrastructures such as enormous databases that can contain any amount or form of information about whatever person or thing is identified by an RFID chip. In addition, the technology of RFID chips is closely related to that of the electronics in smart cards, which are in much more widespread use in Europe than here in the U.S. One application many of us are familiar with is the bridge toll card such as FastPass and others that let drivers quickly past toll gates on bridges and turnpikes. They either identify the driver and charge an account, or, as in many European subway systems, deduct a fee or toll from a preloaded amount that can be renewed by the user. Both RFID chips and such smart charge cards work with a technology that uses the RF field produced by the reader to inductively produce enough current in the chip to transmit the ID code. The person or thing carrying the chip need do nothing. Proximity to the reader is sufficient to transmit the ID. That’s quick, convenient and easy. But now let’s take this a step further. The Department of Homeland Security is looking into placing RFID chips in passports. That seems like a prudent and useful idea for helping secure airports and travelers. But some companies have also created “no swipe” credit cards containing the chips, and this has produced some pushback from the public. The first concern is, of course, that people could unwittingly incur charges without their knowledge or a viable way of disputing them. In addition, such cards can theoretically be read any place

there is a compatible reader. This leads to a Big Brother scenario of tracking people wherever they go, and many completely innocent people are very uncomfortable with that. Such a strategy could be used not only by government agencies but also by any company or group with sufficient resources or motivation to establish a tracking system. There have already been some demonstrations of a person walking into a store, having his or her card read and then automatically being steered close to highlighted products that have been identified by their buying history as being of interest. But the line between the seemingly innocuous and the truly insidious is a blurred one. The technology itself is neutral and can have many beneficial as well as very harmful applications. As a dog owner, I am very grateful for the ability to track a potentially lost friend with this technology. As a livestock rancher (alpacas) I am vastly annoyed by a potential source of massive government interference. That is a proposed system called the National Animal Identification System (NAIS). This is a proposal by the Department of Agriculture that originated from a good idea, the desire to quickly track and deal with outbreaks of disease in livestock, and quickly degenerated to a government bureaucratic nightmare. It would have been mandatory for every animal owner—down to the grandmother with a couple of chickens in her back yard—to register their premises, have ID chips implanted in all their animals and be tracked by a huge national data base. Fortunately, there was enough outrage against this Orwellian plan that the government has made it voluntary “at the Federal level,” whatever that means. Still, voluntary participation is a very good way for large agricultural operations and even smaller farmers to keep track of their animals and be alerted about potential outbreaks—a system that could potentially prevent the mass slaughter of animals such as we have seen in the UK. We are all aware of the ways technology can and does affect our daily lives. In the vast majority of cases, it is for the better. Every now and then there comes a development with implications and applications so vast and diverse that it pays to take a close look at the practices and policies that might arise from it and ask ourselves which paths we really want to follow and which we want to exercise some control over for the sake of our privacy and freedom. January 2007

Slow Motion?

FAST-FORWARD YOUR PROJECT WITH WINDOWS® EMBEDDED. Change happens. Don’t let it slow you down. Get to market faster with end-to-end development toolkits, building blocks to create tailored solutions, and the support of a highly qualified partner community. See how Magellan cut six months from development of its devices at © 2006 Microsoft Corporation. All rights reserved. Microsoft, Windows, the Windows logo, and “Your potential. Our passion.” are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. The names of actual companies and products mentioned herein may be the trademarks of their respective owners.

Fast Finish.

Industry Insider

January 2007

New Joint Standard for Embedded Flash Memory The MultiMediaCard Association (MMCA) and the JEDEC Solid State Technology Association (JEDEC) today announced their joint adoption of eMMC as the trademark and product category of a class of embedded memory module products built on the joint MMCA/JEDEC MMC Standard specification. The MMCA and JEDEC had entered into a joint standard-setting agreement earlier this year. eMMC is the first product standard from the partnership. eMMC describes an architecture comprised of an embedded storage solution with MMC interface, flash memory and controller, all in a small BGA package. It is based upon the industry standard MMC System Specification v 4.1/4.2 and JEDEC BGA packaging standards. With interface speeds of up to 52 Mbytes/s, eMMC provides fast, scalable performance. It also allows for an interface voltage of either 1.8V or 3.3V. Accordingly, eMMC supports a wide range of applications in consumer electronics, wireless, navigation, industrial uses, and other areas. With the eMMC solution, a host system can now gain access to all major classes of mass storage memory subsystems, including embedded memory (eMMC), memory cards, or even hard disk drives (via ATA-on-MMC specification) with one common MMC Interface Protocol Bus. This system architecture is far more flexible than that based upon other memory cardonly standards. The design complexity is magnified by generational process geometry shrinks and MultiLevel Cell (MLC) technology. The benefit of eMMC to the host manufacturers is a simpler product design and qualification process and an overall shorter time-to-market.

Motorola Announces Orders Worth $1 Million for MicroTCA Products

Motorola has announced orders worth $1 million for its MicroTCA system products that will enable off-the-shelf access to this open, standards-based technology. The companies will integrate Motorola’s MicroTCA core communications server technology into development systems to serve markets such as telecom access, military communications and diagnostic equipment for the healthcare industry. Early access to development systems such as this can help original equipment manufacturers gain rapid technology discovery and vital timeto-market advantage. Simon Stanley, analyst-at-large at Heavy Reading and principal consultant for Earlswood Marketing said, “Motorola’s numbers are by far the largest amount of revenue that I’ve seen for MicroTCA development systems and show that after only a few months since its ratification, MicroTCA adoption is well underway. The interest

in MicroTCA across a range of markets encompassing telecom, military, medical and industrial computing applications indicates that MicroTCA has the potential to achieve significant economies of scale. With development budgets cut to the bone, standardized platforms such as MicroTCA will be crucial to the future success of many OEMs.” “The availability of communications servers based on open standards such as MicroTCA is accelerating the shift from the old supply chain model—where OEMs supplied everything from boards to fully integrated applications—to a model with systems integrators taking on much of the development previously kept in-house,” said Paul Virgo, director of MicroTCA marketing, Embedded Communications Computing, Motorola. “In fact, for the first time since Motorola introduced the VMEbus 25 years ago, we believe that another standard has emerged that could change the landscape of embedded computing across all industry segments.”

Communications Platforms Trade Association Adds Three Members

The Communications Platforms Trade Association (CPTA) today announced that Degree Controls, Inc. has joined as a Sponsor Member, and Interphase Corporation and ZNYX Networks have joined as Contributor Members. These companies intend to contribute technical and marketing resources to CP-TA’s working groups in order to help drive a mainstream market for open industry specifications-based communications platforms through interoperability certification. CP-TA is currently defining interoperability test requirements and procedures for PICMG’s AdvancedTCA specification aligned to the SCOPE AdvancedTCA profile. At ITU Telecom World, CPTA is demonstrating its test tools, including thermal testing, for the first time. In the future, CP-TA will address PICMG’s AdvancedMC and MicroTCA as well as specifications from OSDL and the SA Forum. Member companies participate

in the creation of interoperability test documents and will be able to promote their products meeting the requirements as CP-TA-certified. The Communications Platforms Trade Association is a global organization of 25 communications platform and building block providers whose mission is to accelerate the adoption of SIG-governed, open-specificationbased communication platforms by certifying interoperable building blocks. For more information about CP-TA, visit

Curtiss-Wright and EdenTree Partner on Network Lab Automation

Curtiss-Wright Controls Embedded Computing and EdenTree Technologies have announced an expansion of their partnership to provide integrated solutions for network lab automation. EdenTree’s Lab Manager software, the Lab Operating System and leading software platform for managing, scheduling, configuring and tracking lab resources, provides a graphical user interface (GUI) and API for controlling CurtissWright’s GLX4000 series, its fourthgeneration non-blocking, multiprotocol physical layer switches. The products have been integrated since early 2005. Lab Manager’s drag-anddrop GUI allows test engineers, developers, customer support personnel, and other lab users to design and schedule test topologies consisting of devices that are interconnected by GLX4000 switches. The solution transparently and dynamically builds the topologies, eliminating manual recabling and providing automated and remote control of test topologies, easier sharing of equipment, and a dramatic increase in test velocity. The GLX4000 series is a nonblocking, multi-protocol physical layer switch that allows any input to connect to any output. The GLX4000 January 2007

Industry Insider

cPCI SHOWCASE Featuring the latest in cPCI technology

Event Calendar 01/31-2/02/07 AFCEA West 2007 San Diego, CA

02/13-15/07 Embedded World 2007 Nuremberg, Germany

02/21-22/07 5th Annual Software Radio Summit



Altera Stratix II GX FPGA featuring BittWare’s ATLANTiS framework for I/O interfacing, routing, and coprocessing Eight link ports @ up to 1 GByte/s each 36 LVDS pairs comprised of 16 inputs and 20 outputs Four channels of high-speed SerDes transceivers Four Analog Devices ADSP-TS201 DSPs @ up to 600 MHz

Real-Time & Embedded Computing Conference Melbourne, FL

02/28-3/01/07 MVA Communications Ecosystem Conference San Diego, CA



Phone: (603) 226-0404 Fax: (603) 226-6667 E-mail: Web:

Real-Time & Embedded Computing Conference Huntsville, AL

03/03-10/07 IEEE Aerospace Conf. Big Sky, MT

03/06/07 Real-Time & Embedded Computing Conference Atlanta, GA


GPS / IRIG time & frequency reference GPS & timecode synchronized reader/generator Autodetects IRIG-A, IRIG-B, NASA36 High-performance oscillator to freewheel Event capture/interrupt input Programmable alarm/interrupt output Programmable 1, 5, 10MHz frequency output IRIG-B output Windows, Linux, Solaris drivers Comparable PMC/PCI form factors

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can support up to 288 ports and up to 2.5 Tbits/s in switching capacity. The company offers SFP- and XFPbased interface cards for flexibility and support of protocols up to 10 Gbits/s, and fixed-interface cards supporting digital signals up to 4.25 Gbits/s, including Firewire (IEEE 1394B).

LabView Extended to QNX Neutrino RTOS

National Instruments and QNX Software Systems have teamed up to extend the LabView graphical dataflow environment to the QNX Neutrino real-time operating system. Engineers now can use the NI LabView Embedded Development Module with the QNX Neutrino RTOS to add comprehensive support for multicore processors and target any hardware platform supported by QNX Neutrino. Engineers using LabView to design, prototype and deploy their embedded designs with QNX Neutrino now can develop programs known as VIs in LabView with multiple simultaneous execution paths and instantly see increased processing power with no special coding or configuration required. LabView engineers do not have to worry about additional thread management and multitasking coding because QNX Neutrino handles this automatically. Additionally, engineers using the LabView Embedded Development Module with the QNX Neutrino RTOS are not required to choose a target CPU until much later in the project design. Instead, the engineer can complete the design and prototype stages using commercial off-the-shelf hardware such as National Instruments CompactRIO or PXI without addressing the final target configuration. After measuring the required CPU performance, the engineer can choose a single core or multicore target based on the specific application needs. Recently, QNX Software Systems announced that the QNX Neutrino RTOS now works with the National Instruments Measurement Hardware Driver Development Kit andPCImultifunctiondataacquisition (DAQ) boards. This announcement means design engineers now can

Industry Insider choose from a wide range of National Instruments DAQ products—from low-cost single-function units to high-speed multifunction devices— while experiencing the benefits of the proven fault tolerance and real-time performance of QNX Neutrino.

this data transport and allows manufacturers of these two types of subsystems to utilize a common data transport protocol; thereby simplifying integration and facilitating interoperability. The SDR Forum’s System Interface Working Group (SIWG) is also looking at DigitalIF, with a VITA Standards goal of defining the requirements Organization, SDR Forum for a common set of application Announce Alliance programming interfaces (APIs) The VITA Standards that can later be standardized. Organization (VSO) and the Collaboration between the Software Defined Radio Forum SDR Forum and VITA ensures that (SDR Forum) have announced that the APIs (a set of routines, protocols they will collaborate on software and tools for building software defined radio specification activities applications) developed will fully underway at each organization. support the VITA 49 standard, and The initial focus of the relationship provides a venue for VITA members will be in the area of Digital to influence the API requirements. Intermediate Frequency (DigitalIF) The SDR Forum is also examining data transport. DigitalIF defines the the DigitalIF standards utilized by signal and control data that is passed other industry associations operating between the radio frequency (RF) in adjacent markets. This will ensure subsystem and the baseband signal a robust API that fully addresses the processing subsystem of a software needs of both VITA and SDR Forum defined radio. members. Software defined radios VITA is developing the currently Page used in1defense, public PentXM2_187x121_GB 18/10/06are 11:52 VITA 49 standard, which defines

safety and security, and commercial applications such as RFID readers.

Samsung Unveils Fusion Memory Solution – OneDRAM

Samsung Electronics has announced that it has developed a prototype fusion memory chip that can significantly increase the data processing speed between processors in mobile applications. The new fusion solution, OneDRAM, is expected to be specified in the design of handsets, game consoles and in other digital applications, especially those that use three-dimensional graphics. The 133 MHz 512 Mbit device incorporates a dual-port approach to sharply increase the time that it takes to transfer data between processors. Data managed by the processors is housed in a shared bank where the space for storing the data can be adjusted accordingly. This meets the JEDEC, low power, double-datarate (LPDDR) memory standard. Due to rapidly increasing

demand for multimedia features in mobile applications, designers have been specifying the use of two separate processors—a communication processor and a media processor. The new OneDRAM will channel data between the processors through a single chip eliminating the need to also specify DRAM and SRAM chips for buffer memory. Along with the faster data processing speeds between the processors, the OneDRAM reduces power consumption by 30 percent, lessens the number of chips needed and minimizes area coverage by 50 percent, resulting in a fivefold increase in the speed of cell phone and gaming console operations, longer battery life and slimmer handset designs. A single OneDRAM can replace at least two mobile memories in high-end smart phones and other multimedia-rich handsets. In addition, by adjusting the hardware in the chipset, OneDRAM can cost-effectively reduce system circuitry, while maximizing overall operational efficiency.

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TechnologyInContext CompactPCI Growth

CompactPCI Thrives in Military and Aerospace Applications Designers are constantly challenged to find the best system architecture to meet the demands of their applications. With the unique challenges in these markets, designers continue to move toward CompactPCI architectures to handle their demanding needs. by D  avid Pursley Kontron


hen designing new systems, deRS-232 to other boards Standard backplane signers must start by determining what architecture best supRTM USB ports the overall goals of the system. In Device the past, VME-based architectures were the favored choice for military applicaPS/2 tions, and they continue to remain in fa3U J2 Mouse vor with many users. However, with the cPCI increased demands of modern defense J1 Board panies providing solutions now and aerospace applications such as Future ration into products, technologies and companies. Whether your goal is to research the latest Combat Systems (FCS) and Joint Tactiication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you calwhatever RadiotypeSystem (JTRS), VME-based ce you require for of technology, are often es and productssolutions you are searching for. no longer able to meet these needs. In many cases, the limitations of the VME bus preclude it from being considCustom backplane MIL 38999 ered at all. This is especially true for small I/O footprint applications requiring the 3U Rugged chassis form-factor. Limitations of 3U VME in terms of bus width, bandwidth and rear I/O pins make it impossible to use for many Figure 1 Rear I/O provides different capabilities for different applications. In non-rugged applications, rear I/O signals pass through the standard applications. Instead, designers choose backplane to a board-specific rear transition module (RTM) that provides 3U CompactPCI for these applications, as

End of Article Get Connected

with companies mentioned in this article.


January 2007 Get Connected with companies mentioned in this article.

I/O connectors, such as the RS-232, USB and PS/2 connectors shown here. In rugged applications, rear I/O pins connect to a custom backplane that provides rugged connectivity between boards and to ruggedized connectors.


it supports a much higher bandwidth with plenty of rear I/O. Similarly, for high-performance applications that require multiple CPUs processing data across a single backplane, 6U CompactPCI’s derivative PICMG 2.16 is a logical choice, as it is more reliable and supports more rear I/O than VITA 31 or VITA 41. CompactPCI’s roots in PCI also make it more desirable than VME for many design groups. For example, new software designers already know and understand the challenges of developing PCI applications, while developing VME applications provides some unique challenges. Also, there are literally millions of software applications that are compatible with CompactPCI. These “comfort zone” factors that made CompactPCI quite successful in non-defense embedded applications are now helping to make it prevalent in defense applications as well.

Importance of Rear I/O

Rear I/O simply means the routing of board I/O signals to the backplane instead of, or in addition to, routing them to the front panel. Adding I/O to pins on the rear of the board provides more flexibility to the designer. Beyond the obvious value of adding more I/O pins, rear I/O improves serviceability of the system. As shown in Figure 1, with all I/O wiring at the back of the system via a rear transition module (RTM), a failing board can be simply unplugged from the backplane and replaced. No other re-connections are necessary, making replacement faster and less error-prone. Hot-swap capabilities improve on this further, allowing the board to be replaced without powering down the system. The value of serviceability is important to defense applications, although rear I/O has another use in systems to be deployed in harsh environments. Rugged systems use the rear I/O pins to communicate via a custom backplane to minimize the number of connectors. Interboard communication is done directly over the custom backplane to minimize

CompactPCI (3U)

VME (3U)

Data Bus Width





Theoretical BW (MB/S)





Rear I/O

75 or 105




Table 1

CompactPCI can be used to overcome many of the limitations of 3U VME, including the low bandwidth and lack of rear I/O. Also note that a 64-bit bus is not possible with the 3U VME form-factor.

PICMG 2.16 (6U)

VITA 31 (6U)

VITA 41 (6U)

Gigabit Ethernet

Gigabit Ethernet

PCI Express, InfiniBand, StarFabric, Serial RapidIO

Rear I/O




System management





No (cPCI)

Yes (VME64x)

Yes (VME64x)

System protected from single board failures




Backplane fabric

Table 2

VITA 31 and VITA 41 offer backward compatibility with legacy VMEbus boards. PICMG 2.16 trades off compatibility with IPMI-based system management preventing a single board from bringing down the entire system.

components and connectors. Furthermore, these systems require rugged MIL-style connectors to the outside world, which are typically connected directly to the custom backplane. As detailed in Table 1, when a system requires both rear I/O and a 3U formfactor, CompactPCI is the only available option. If a larger form-factor (6U) is sufficient, CompactPCI, VME, and their derivatives (PICMG 2.16, VITA 31 and VITA 41) all allow for rear I/O. PICMG 2.16 provides the most rear I/O functionality, with 295 connector pins available.

Multiprocessing in Rugged Environments

Small form-factor, while always desirable, is not always the most important design constraint. For example, unmanned ground vehicles (UGV) require real-time

feedback based on the concurrent processing of dozens of sensor streams. Similarly, during the early stages of large-scale defense programs, emulators simulate entire networks of deployed systems. Each of these applications requires multiple processor blades to be operating independently, while at the same time communicating heavily with the rest of the system. Currently, these types of systems require a 6U form-factor with PICMG 2.16, VITA 31 and VITA 41 all meeting the multiprocessing requirement. Since each of these specifications places a switched or mesh fabric on the backplane, the designer must look more closely at other system requirements, such as rear I/O, in order to determine the best architecture for the application. PICMG 2.16 offers more rear I/O pins than its VITA counterparts, but designs with modest rear I/O requireJanuary 2007



Figure 2

MicroTCA will compete with CompactPCI and PICMG EXP.0 as leading architectural choices for years to come. The smaller form-factor EXP.0 and MicroTCA solutions provide higher bandwidth than previous architectures. Pictured is the Kontron AM4001.

ments will find that any of these architectures will meet their rear I/O needs. In such a case, the designer has to look more carefully at other system considerations. Table 2 shows that the fundamental trade-off when evaluating these architecRTC?FREEADPDF0tures is one of backward compatibility vs.










January 2007

reliability. If a system requires legacy VME boards to be on the same backplane as the boards running the new application, then the system designer must choose VITA 31 or VITA 41. However, if that is not the case, then the designer may select PICMG 2.16 because of its improved reliability.

PICMG 2.16 improves reliability in two ways over VITA 31 or VITA 41. First, the PICMG 2.16 architecture requires IPMI (Intelligent Platform Management Interface) on the boards and backplane via an I2C bus. This allows the system to be monitored so that failing boards can be identified and hot-swapped with replacement boards. Depending on the system configuration, IPMI can improve availability to “five nines� (99.999%). Second, since PICMG 2.16 does not maintain backward compatibility with CompactPCI, there is no data bus shared among the cards. Therefore, no single card can go haywire and completely prevent all communication in the system. On the other hand, VITA 31 and VITA 41 include legacy VME64x support, which means that a single bus is shared among the boards, giving the opportunity for a single board to fail the system. In the most pathological case, an electronic failure on a single board could damage all cards in the system. On a less technical note, it is worth mentioning that while PICMG 2.16 has all

JhoekhNC8 The XMB is a part of Octagon’s line of Core Systems™ that offer fanless solutions for transportation, military and security applications.The XMB is a “no compromise” design that optimizes the electrical, thermal and mechanical components for maximum reliability.The result is a powerful, yet fanless system in a rugged extrusion that provides 24/7 service even in harsh environments. The basic unit includes the processing power, power supply, memory and I/O for most applications.Yet, it can be easily expanded using PC/104 I/O function blocks or Octagon’s XBLOK™ half–size PC/104 expansion modules. Generated heat is efficiently channeled directly to the case to help prevent internal hot spots.

D[[ZYkijec?%E5 JhoekhNC8 The XMB Core System simplifies custom I/O expansion.You can prototype your system in less than a day. The option panel is removable for easy punching and machining.Add digital, serial, analog, GPS, GSM, Firewire or dozens of other functions.




Then, attach the cable for a PC/104, mini–PC or other expansion device and install the drivers. Once your system checks out, Octagon can supply a finished turnkey version, loaded with Windows XPe® or Linux, plus your application software.

šO  ekhioij[c_i\kbboj[ij[ZWdZh[WZo jei^_fjeoekhYkijec[h$š The quad video camera and Ethernet switch versions to the left illustrate our option panel system. In addition, the P1 and P2 connectors are available for custom I/O. Call Octagon today for help in configuring your next OEM system.

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but replaced 6U CompactPCI with many boards available from many vendors, the number of VITA 31 and VITA 41 products available is quite limited. This is largely due to the acceptance of CompactPCI in a wide variety of market segments beyond defense and aerospace, making it more viable and less risky for vendors to build PICMG 2.16 boards.

Future Considerations for the System Designer

surprising to see MicroTCA in heavy use within these programs (Figure 2). Other factors that have nothing to do with the standards will help to drive system designers to an appropriate architecture. For example, the existence of multicore processors and multiprocessor boards have increased processing power to a point where multiple systems can be combined into a single set of boards on a single backplane. On the other hand, the

ability to do more computation within a system requires that the system be architecturally designed in such a way that communication can keep up with the computation. Kontron America Poway, CA. (858) 677-0877. [].

The coming months should be very interesting for system designers, as more architecture options will be available, and the technical differences between the options will diminish. PICMG EXP.0, commonly referred to as CompactPCI Express, will likely grow and flourish. Standardized in 2005, EXP.0 provides greatly improved throughput via PCI Express connectivity on the backplane. While there currently are a few commercial offerings supporting the standard, more products will come to market to complete the EXP.0 ecosystem in the coming year. This makes it possible to build complete EXP.0 systems with bestin-class products throughout. VITA 46, also known as VPX, is still undergoing standardization, but products have been announced and designers can expect to see VITA 46-based solutions appearing in 2007. Interestingly, the VITA 46 standard no longer offers backward compatibility with VMEbus, and instead focuses on improved performance. In that sense, this is moving the VME-based VITA standards closer to the PCI-based PICMG standards, blurring the line between them. Unrelated to CompactPCI or VME, MicroTCA will expand its presence in small form-factor applications. Ratified in July 2006 as PICMG MTCA.0, MicroTCA offers extremely high communication bandwidth (up to 40 Gbits/s on the backplane) and high processing capacity (up to 12 blades running in parallel on a single backplane) in a 2U form-factor. It also supports up to seven nines (99.99999%) availability with such features as full redundancy, hot swap and IPMI support. Considering the communication-centric applications in today’s military programs, such as FCS and JTRS, it would not be January 2007


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TechnologyInContext CompactPCI Growth

CompactPCI – A Growing Alternative to COTS VMEbus Systems Systems based on CompactPCI are moving into application areas formerly dominated by VME. PICMG 2.16 systems in particular can take advantage of standard Ethernet and find applications in a “sweet spot” between VME and the newer ATCA. by R  eeves Mollman Performance Technologies


he PCI Industrial Computer Manufacturers Group (PICMG) introduced CompactPCI or PICMG 2.x in 1995. At the time, it represented a sea change for the embedded computing industry. The form-factor offered a valuable new choice to the industry, which had previously been dominated by the VME bus panies providing solutions now standard. CompactPCI quickly became ration into products, technologies and companies. Whetherwithin your goal the is to research the latest widely adopted, particularly ication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you telecommunications market. The technolce you require for whatever type of technology, anticipated es and products ogy you are searching for. and accommodated leading embedded computing technology innovations, including high-end processors, high-speed bus backplanes and state-ofthe-art power delivery and cooling. Recently, an increased number of COTS military and government applications have been migrating to CompactPCI 01 02 03 (cPCI) as a viable pin-and-socket followon to their existing VMEbus systems. The migration is being driven mainly by

End of Article

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January 2007 Get Connected with companies mentioned in this article.

PICMG 2.16 Chassis with I/O cluster processing and embedded Ethernet network.


performance, availability and the ease of implementing contemporary communications technologies. Some analysts have forecast that further penetration into applications including the defense and homeland security market will cause cPCI to experience further growth. Over the last 11 years, cPCI has undergone a continuing advance of “point specs,” which have incrementally improved the architecture, adding features such as hot-swap, redundancy, telephony bus and support for telephony mezzanine modules. Most dramatically, in 2001, PICMG 2.16 was developed to extend the life of existing cPCI systems by combining the inherent robustness and reliability of cPCI with packet-switched Ethernet fabrics. So popular was this new development, that within 18 months of its ratification, more than 40 companies were producing and shipping PICMG 2.16-compatible products. PICMG 2.16 eliminated bottlenecks in the traditional bus approach taken by VME and original cPCI technologies. Based on a network of independently switched nodes, it not only removed the limitations on the number of system elements, but also on the overall throughput capacity of the system. The PICMG 2.16 specification describes a redundant, switched 10/100/1000 Ethernet network within a cPCI chassis, providing IP connectivity using a “star” topography routed across the backplane for an aggregate bandwidth of up to 40 Gbits/s. This specification allowed for flexibility in selecting the connection speed and higher-level protocols based on specific application need. This frees equipment manufacturers to mix and match switches, single board computers, chassis and sub-components. The modular make-up of PICMG 2.16 system design simplifies deployment, increases serviceability and greatly improves reliability. In addition, having the switch in the chassis minimizes external wiring (Figure 1).

VME - Over the hill?

There is no denying that VME has an impressive lifespan. It has recently cel-

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Data received on cPCI communications server serial line and the appropriate radar protocol strips out the radar particulars and then retransmits the payload over Ethernet to a central server on the network for further processing and eventual display/monitoring on a radar operator’s console.

ebrated its 25th anniversary as an open system architecture, has continuously evolved its core technology and has introduced several advanced interconnect and fabric capabilities. According to some analysts, VME bus technologies still account for over 25 percent of all embedded market applications. However, with cPCI entering the market in the 1990s, and now the recent rise and growing acceptance of AdvancedTCA and MicroTCA in the telecom space, many are left wondering—has VME been taken as far as it can go through incremental improvement? Should it be phased out in favor of other form-factors that are designed from the beginning to accommodate the technology infrastructure as it exists today or is anticipated to require in the future? Will the components remain available over time? And will the ecosystem of suppliers continue to shrink? PICMG 2.16 is a mature, well-proven, deployed technology used in production today by hundreds of customers spanning many industries, from telecommunica-

tions to defense and homeland security. Experience has shown that the one thing embedded market customers look for is the size of the ecosystem. No one wants to use “standardized” products only to find that the “version” they want to use is not supported by many vendors. By far, the biggest advantage that PICMG 2.16 has going for it is that its vendor base is quite large, and that interoperability is a given, because there are really no choices to be made within 2.16. All other standards, including the newest from VITA and PICMG, have so many choices that it is extremely difficult for a customer to find more than a few vendors or products that are truly compatible. As this magazine’s editor recently mentioned, the networking industry is rife with examples of technologies that were designed for one purpose and wound up used and modified for other, equally lucrative applications far from the original intention. cPCI began with a telecom base both in central office and remote sites, but has January 2007


TechnologyInContext grown to encompass military, industrial, and other governmental applications. In particular, with the rise in military budgets since the early 2000s in both European nations and in the United States, cPCI has come to represent a major threat to established bus architectures including VME, especially within new military and defense projects looking to implement a more contemporary IP-based architecture. Governmental and industrial equipment integrators have the same fundamental needs as telecom equipment manufacturers and have been moving to cPCI systems for fixed applications including factories and remote sites, as well as for mobile communications needs including airborne, shipboard and military vehicles (Figure 2). In these scenarios, VMEbased systems struggle under the weight of throughput limitations due to their busbased approach. A number of new technical approaches have been tried in VME to staunch its loss of new design activity and market share, but as often happens, introducing new technologies like newer, highspeed interconnects for VME often leads to market fragmentation. Multiple choices have to be made between new quasi-proprietary buses and a number of networking topologies. In turn, such a plethora of choices leads to a confused vendor and customer base and limits the number of suppliers that an integrator can call on for solutions using the particular topology he or she has chosen. In contrast, systems based on Ethernet, Gigabit Ethernet and now 10 Gbit Ethernet (which is supported in 2.16 environments, but not in the backplane) have come to dominate cPCI, leading to a focused, mature ecosystem and broad choice of competitively priced vendors who offer an array of compatible blades. For example, there are now more than thirty suppliers of single board computers for the cPCI 2.16 market. Integrators are able to choose from a wide selection of competing boards that cover everything from low-cost Intel Pentium solutions to high-performance PowerPC and dual core x-86 solutions, along with a very impressive array of real-time and standard operating systems and applications for those blades. 20

January 2007

Intelligent Shelf-Manager

Figure 3

IPMI-based intelligent shelf manager overseeing all boards, power supplies and fans within a system.

Rugged Designs and Remote Management

It is easy to see why military and defense and homeland security are growing markets for cPCI as a migration path from existing VME COTS systems. Equipment vendors need to ship equipment that is tough and reliable and built to withstand extremes in temperature, shock and vibration. Due to its original market focus, just about all cPCI products are built to satisfy the rigorous requirements of the NEBs Level 3 telecom standards. This means that just about every board can, in fact, handle the Mil-Spec requirements dictated by government programs. Even if they don’t meet the requirements at the outset, most can be readily modified to do so. Conformally coated, ruggedized and conduction cooled, cPCI blades and systems have been deployed for everyday use worldwide by prime contactors and governmental users. Since they deal with a large number of remote locations, military and defense system managers must be able to remotely manage that equipment for software upgrades, alarm conditions and system con-

trol. Thanks to network-based blades and system management modules common in cPCI systems, they can easily do that. Network-based systems often use commercial packages based on Simple Network Management Protocol (SNMP), File Transfer Protocol (FTP) or its secure cousin SFTP, to remotely control and update individual system elements via an open or secure network. Similarly, the chassis itself can be completely controlled via an out-out-band connection to the PICMG 2.9 Intelligent Platform Management Interface (IPMI) controller or set of redundant controllers, which act as the single management entity responsible for overseeing all of the boards, power supplies and fans within a system. The IPMI system manager can automatically react to stimuli such as an over temperature condition, a board watchdog event or power supply failure, while at the same time sending an alarm to a central site. Many 2.16-based systems are specifically designed to shunt system workload to an alternative resource, either within that chassis or to a hot standby system (Figure 3).


Keeping up with the Joneses

Backwards compatibility is another major feature required by military system designers. The military has been using embedded systems for more than forty years. Unlike the PC market, where everything changes every nine months, maintaining and refreshing military systems, which are often based on custom designs with frozen technology, is a major challenge. The OS and drivers used by all boards in a bus-based system must be locked together, creating another impediment to keeping designs fresh and being able to integrate the latest technologies and techniques to adjust to user needs. Using 2.16 COTS systems changes that paradigm. A switched packet backplane approach grants a much finer granularity to system changes, since the now independent system nodes use the lingua franca of Ethernet to communicate at the network level, severing the master/slave co-dependency of bus-based systems. In this new scenario, the user simply changes one single board computer or communication node and puts in a higher performance unit to upgrade the whole system, greatly lessening the impact of obsolescence and upgrades. cPCI 2.16 represents the best, most balanced solution, because regardless of individual connection speeds, the fundamental technologies, topologies and protocols all work together. It is a standard that is evolving over time, but is inherently backward compatible. Elements of switched Ethernet backplane systems may all talk at different speeds, but all speak the same language. To some degree, PICMG 2.16 can attribute its success to its ability to leverage the ubiquity of Ethernet. Since the future of embedded application development is all about IP and to a large extent IP is so directly associated with transport over Ethernet—95 percent of the world’s data rides over Ethernet at one point or another—it only makes sense to build your infrastructure natively with Ethernet. Therefore, 2.16 has set the stage for this “revolution,” with other specifications including AdvancedTCA and MicroTCA following in its footsteps. Industry analysts support the idea that companies will still require cPCI even as

the new AdvancedTCA and MicroTCA for more and more applications that do specifications become more widely ac- not require the outright performance— cepted. For example, some analysts and associated price and footprint—of forecast that further penetration into ap- AdvancedTCA. plications including military and defense will cause the cPCI market to experience Performance Technologies strong growth over the coming years. Al- Rochester, NY. though VME still has its place in legacy (585) 256-0200. systems and AdvancedTCA solutions []. are an excellent choice for core telecom or other high-performance applications, growth RTI RTC in the 06 cPCI Ad 12/21/05 market will 10:57 continue AM Page 1

Count on Us For data-critical networked applications At the end of the day, mission success relies on the ability to respond to changes in an instant. Designers of missioncritical combat systems count on Real-Time Innovations (RTI) for fast and reliable standards-based software to communicate real-time data over a network. RTI’s NDDS middleware supports the DDS standard and is widely used in military and aerospace applications today.

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January 2007


TechnologyInContext CompactPCI Growth

CompactPCI / PICMG Standards on the Move: A Look at CPCI Express Several technological elements have emerged to provide a host of new options for system designers. 3U CompactPCI and CompactPCI Express are taking up strong new positions. by V  alerie Andrew ACT/Technico


n recent years, a flurry of activity has resulted in a multitude of new standards. Under the auspices of PICMG, new standards are being implemented that include AdvancedTCA and AMC, the newly approved MicroTCA, and CompactPCI Express (PICMG EXP.0) or CPCIe. In the VITA Standards Organization (VSO), we find an equally busy slate of emerging standards, under the names of Gigabit Ethernet on VME (VITA 31.1), VXS (VITA 41) and VPX (VITA 46). All of these standards share the same goal, panies providing solutions now albeit via different approaches: interoperration into products, technologies and companies. Whether your goal is to research the latest ability and backward compatibility. ication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you At the same time, processor technolce you require for whatever type of technology, hassearching progressed es and productsogy you are for. to offer greater options in density and granularity. Intel’s Core Figure 1 Example of a 3U CompactPCI PowerPC-based Single Board Computer micro architecture-based processors and from Interface Concept. Freescale’s high-performance / low-power PowerPC family of embedded processors (MPC744x) enable leaps in processing widely available on the Web. often coexist depending upon the user’s speeds at lower power usage (Figure 1). A third contributing technology trend application, either in the control plane, the FPGAs also are becoming more com- is high-speed serial packet-based archi- data plane or the backplane. monplace, to provide unique solutions at tectures, or fabrics. PCI Express is the de These highly scalable serial intersignificantly lower costs than proprietary facto fabric replacement for the traditional connects also help solve the speed bottleASICs, with IP cores becoming more PCI and PCI-X parallel buses. Other serial necks found in other traditional parallel fabrics making headway are Serial Rapi- buses such as CompactPCI (CPCI). PCI dIO, InfiniBand, Aurora and the ubiqui- Express is the next-generation fabric used Get Connected tous Gigabit Ethernet, closely followed by in consumer computers, which means it with companies mentioned in this article. 10 Gigabit Ethernet. These standards can will have wide acceptance as well as sup-

exploration er your goal eak directly l page, the resource. hnology, and products

End of Article


January 2007 Get Connected with companies mentioned in this article.


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port for key interfaces such as keyboard / mouse, video, audio, printers, etc. Another advantage of PCI Express is that it is largely transparent to application software, allowing for a much smoother migration from PCI-based systems. Where the above mentioned serial I/O technologies offer high-performance communication protocols, they are often overkill for onboard point-to-point communication. Here, lower latency protocols are more useful as they use less overhead than the more complex PCI Express. Both major FPGA vendors have introduced such protocols; both Xilinx’s Aurora Protocol and Altera’s SerialLite II offer low latency and low overhead protocols for offloading simpler, chip-to-chip communications. This is a topic that can be more adequately addressed in a separate dedicated article.

The Rise of 3U

The increase in performance along with reduction in density and power usage now make it more feasible to look at smaller form-factors for applications where processing capabilities previously could not be met in those small spaces. Historically, 3U VME was dominant in industrial control applications such as automotive assembly control equipment, food processing automation and inspection equipment. Since the I/O availability on 3U VME is limited, it did not lend itself well to increased functionality. This led in many applications to replacement by PCI-based solutions, either at the PLC level, custom board or PC-based system. 24

January 2007

The problem with PC-based solutions is that they are more dependent on the lifecycles of the consumer-oriented chip-level components, which can be as low as 18 to 24 months rather than the longer embedded lifecycle of a minimum of 5 years or more. This ends up contributing to a higher replacement and maintenance cost simply due to the unavailability of parts. Here is where the 3U form-factor is quickly re-emerging as a highly interesting alternative to previously used standard platforms, and even proprietary or PCIbased custom packages. The size lends itself nicely to several key applications such as industrial process automation, medical equipment, avionics, instrumentation, and other applications where there are space constraints on a design. Due to its expanded I/O capability, CPCIe in particular is ideal for any application where image capture and processing are necessary; this is a common requirement on the factory floor for example, where optical or physical inspection of goods are critical to the production line. Applications where Man-Machine Interface (MMI) is common, such as MRI and CT Scanning machines, will also benefit from CPCIe. Other advantages to the 3U CPCI form-factor are mechanical stability, facilitated by the robust highdensity pin and socket connector and well performing shock and vibration characteristics of the Eurocard design. This lends itself naturally to applications where harsher temperature and environmental conditions must be met, like unmanned aerial vehicles (UAVs).

A number of solutions have emerged on 3U CPCI that offer significant stability for applications requiring hardware that meets rugged environmental and mechanical requirements. Several processor boards now offer low power dissipation CPUs using either Freescale MPC7447/8 or Intel’s Core Duo or Core2Duo chips on either commercial grade, extended temperature or full rugged, conductioncooled platforms. Single Board Computers are available from companies such as ACT/Technico, Interface Concept, MEN Micro and others. In the realm of small, rugged system requirements, storage is also making progress. Until very recently, solid-state flash storage has been essentially too costly for use in embedded systems requiring any significant storage space. Rotating drives, however, have been a riskier investment for applications where environmental shock and vibration levels were high, although a few manufacturers make extended duty versions of 2.5” drives. Recent advances in flash technology and chip density however have helped change the situation, so that higher capacities are now feasible in smaller packages. A designer can now entertain adding a rugged storage solution as high as 32 Gbytes on a no-slot mezzanine added to a processor board. New products offer removable secure storage devices, such as the one shown in Figure 2, without compromising the rugged design of the system. Highly available Network Attached Storage (NAS) solutions are also now more achievable within an embedded system with the use of these new drives, or even traditional rotating drives in a removable package. Another interesting aspect of the new 3U CPCIe (CPCI Express, PICMG EXP.0) standard is the ability to customize a system, maintain backward compatibility with legacy CPCI, and still design a new standards-based solution that draws from a pool of suppliers. By keeping options open to multiple vendors, a system design can naturally migrate to or remain with a standards-based platform, becoming preferable to proprietary PC-based solutions, which often have a much shorter lifecycle and lower warranty/repair support than the industrial embedded platform solutions.


Figure 3

Detail example of a mixed CPCI and CPCIe backplane from Elma (standard CPCI slots on right).

Recent offerings show two different solutions for migration development from 3U CPCI to CompactPCI Express (CPCIe). In one case, a custom backplane provides four slots for legacy CPCI boards and four slots of CPCIe, with the bridge being implemented via a CPCIe side card mounted to the system processor. In a second example (Figure 3), the bridge is achieved via a rear bridge module that plugs into the CPCI and CPCIe system processor slots in the center of the backplane. While it requires the additional two-slot bridge module in the rear of the backplane, the system is not dependent on a specific processor board to perform the functions of the bridge, allowing the designer to select a processor from multiple vendors.

compatible Ethernet controller, a system can be monitored and managed through a remote console. Critical system problems such as a hard disk failure can be quickly diagnosed and managed, significantly reducing down times. New products using 3U CPCI and CPCIe have become available over the past year and more are to come in 2007, making it a viable option for current design upgrade considerations. Other standards based platforms such as MicroTCA and 3U VPX offer higher availability to

bandwidth and I/O performance increases as well; each, however, is filling a need within different applications due to the design and availability of products and niche requirements. CPCIe is a solid standard-based on a historically proven platform with long-term component lifecycle and maintenance support. ACT/Technico Ivyland, PA. (215) 956-1200. [].

Redefining Debug

System Management Revisited

Another growing trend in PICMGbased platforms is the increased need and use of system monitoring and management. Loosely introduced a few years ago under the CPCI standard in PICMG 2.9, the Intelligent Platform Management Interface (IPMI) was more deeply developed and then adopted in the PICMG 3.x standard, better known as AdvancedTCA, and more recently in MicroTCA. CPCIe lends itself well to these same platform management methods; this is of increased interest in industrial automation and process control as well as missioncritical or high-availability applications. The system management is performed by a controller card, connected through a system management bus on the backplane to the host processor. By adding an IPMIJanuary 2007


SolutionsEngineering High-Speed and Hybrid Backplanes

Trends in High-Speed Backplane Design As backplane designers begin eyeing speeds of 25 Gbits/s and higher, new architectures, board materials and silicon may be required, as well as the evolution of interconnect techniques and attachment methods.

by D  avid Helster Tyco Electronics


exploration er your goal eak directly al page, the resource. chnology, and products


ackplane design is typically driven more noteworthy trends deal with speed. by performance, cost and function- Backplane designers may consider changality influences. Often, the resulting ing the backplane’s architecture to obtain design calls for balancing one or more of higher speeds. Other factors include matethese drivers to meet overall objectives, rials and the future-proofing of backplane since one driver has some effect on the designs. Hybrid backplanes, regardless of others. Soon after a specific approach to backplane design is selected, designers must specify the requirements for components and other items, such as high-speed backplane interconnect (Figure 1). panies providing solutions now manufacturers typically do Connector ration into products, and final companies. Whether your goal is to research the latest not technologies wait for the interconnect requirelication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you ments before determining ice you require for whatever type of technology, how well a new will for. work with new backplane ies and productsconnector you are searching characteristics, such as speed, silicon and chassis. Instead, they collaborate with silicon developers and backplane designers and manufacturers, as well as electronic manufacturing service providers. This collaboration often runs in parallel to the development and selection of silicon, as well as other stages in the design process such as modeling. Of course, when it comes to highspeed backplane design, some of the

their definition, are also subject to these trends to a certain degree and are likely to influence future generations of backplanes. Regardless of the particular backplane design, it usually has some type of influence on the interconnect design.

End of Article Get Connected

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Figure 1

January 2007 Get Connected with companies mentioned in this article.

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Figure 2

Orthogonal architectures employ a midplane (center) connection between the front daughter card (left) and back daughter card (right).

Getting More Speed from Board to Board

By definition, high-speed backplanes fill the need for high-speed applications and their designers are under continuous pressure to increase speed. Not long ago, the benchmark for high-speed backplanes was 3 Gbits/s. Now, designers are implementing 6 and 12 Gbits/s and even looking toward 25 Gbits/s. The real question, however, deals with how the high-speed design will be facilitated. In connectors, it is difficult to identify one specific change that occurred to get backplanes up to 3 Gbits/s. At this speed, designers made changes on the backplane and used existing shielded connector technology. Many aspects of the backplane changed, but only in relatively small ways. The challenges in designing for high speed are how to effectively manage the combination of factors that make high speed work, as well as balancing all factors in the backplane design to get better performance while maintaining acceptable levels of cost and ease of manufacturing. Higher-density interconnect solutions, lower noise methodology and even smaller connector pinholes may all result in better performance. Additional considerations that figure into the speed and performance equation include silicon, signal distance, material types and board thickness. As speed and performance requirements increase, more design techniques are required to accommodate them. Silicon developments that incorporate sophisticated equalization techniques can overcome some of the hurdles to making 28

January 2007

systems function at higher speeds. If the silicon is advanced enough, it may allow lesser performance in other areas of the backplane, such as the board, connectors and other components. Using higher-performance silicon may not be the only action required. Designers may also need to consider counter-boring vias on the board, or sacrificing density to allow multiple channels in and out of the backplane. However, by investing in higher-performing silicon with sophisticated equalization, high-performance connectors or high-grade materials may not be needed on the PCB. Speed and density are interdependent and continue to be driven by throughput. So the need to get, for example, 100 Gbits/s from one board to another can be accomplished by running 10 lanes of 10 Gbits/s, 20 lanes of 5 Gbits/s or 40 lanes of 2.5 Gbits/s. Clearly, density and speed work together and can drive connector design. If more throughput is required, and there is enough space in the backplane, the highest speed connector may not be needed. In contrast, if space is limited more speed is required to get the same amount of data through less space, and a higherperforming connector is needed. This tendency influences backplane design lifecycles, because speed and density can only increase until no physical space remains to grow or expand the backplane. The development of modular connectors emerged as a secondary result of scaling density and speed on the backplane. Jumping from 3 Gbits/s to 6 Gbits/s involved mainly tweaking the backplane in various areas. The effort was somewhat similar to the activity needed to achieve 3 Gbits/s, but a little more extensive. However, real challenges arise all around the backplane when moving to 12 Gbits/s. Backplanes that take speeds to 12 Gbits/s also raise connector performance requirement issues. The main changes in connectors when moving from 3 Gbits/s to 6 Gbits/s required manipulating additional performance factors. These included less noise, better impedance control and better board attachment. But the shift to 12 Gbits/s requires designers to use additional techniques, such as changes in silicon, board materials, density and architecture. To

get to 25 Gbits/s and higher, refinements to current methods may be required, or it could be that entirely different methods and technology will be needed. Some even speculate that a complete overhaul in backplanes as we know them could occur. Although backplane designers have figured out 12 Gbits/s fairly well, requirements for 25 Gbits/s are purely hypothetical. First, new silicon is probably needed, since existing silicon is not expected to achieve this speed. This next-generation silicon could be developed so that it avoids the electrical issues encountered at 25 Gbits/s by building upon existing silicon’s sophisticated equalization techniques. Other questions, such as the nearterm profitability potential of such products, cloud the issue a bit. Speeds of 12 Gbits/s are probably fast enough to meet near-term market needs, but some in the industry see a need to develop faster backplanes with links of 25 Gbits/s up to 100 Gbits/s. While these links are largely I/O in nature and can be handled primarily by fiber, more throughput from the I/O will necessitate haste in developing backplanes of 25 Gbits/s and higher. The major question that remains for backplanes of the future is how designers will get from 12 Gbits/s to 25 Gbits/s and beyond that at the board-to-board backplane level. Designers will also be contemplating the move from 25 Gbits/s to 100 Gbits/s and its complexities.

Trends in High-Speed Backplane Architecture

Traditional high-speed backplane architectures work fairly well and allow acceptable performance at current speeds. But recent developments in how topologies are used and implemented are changing some conventional thought about connectivity. An emerging, although not new, method is orthogonal architectures. These are a variant of traditional switch configurations in which each fabric card has a star topology. It is accepted that having two stars on a backplane is a complicated issue, and moving to three stars complicates things even further. But with an orthogonal architecture, complex interconnectivity is simplified. Orthogonal applications twist backplanes,


Figure 3

Press fit connectors incorporate an “eye-of-theneedle” tail. Investigations are ongoing to determine whether surface-mount connectors are viable in backplane applications.

line cards and connectors, both literally and figuratively. An orthogonal, or crossconnect, architecture involves mating a front card vertically with a mid-plane interconnect that serves as a pass-through to another back card that is twisted 90° compared to traditional backplane/daughter card arrangements (Figure 2). In addition to simplifying the interconnect, orthogonal architectures also improve electrical performance. Since they do not have mid-plane traces, the result is less electrical loss. However, orthogonal architectures are not suited to all applications. Since they use a mid-plane arrangement, line cards must be accessible from the front and rear of the chassis, which is not possible in all cases. Where they can be used, orthogonal architectures offer reduced board thicknesses and layer counts. To accommodate them, connectors have changed to facilitate the 90° orientation on the mid-plane and line card. This is most notable on the mid-plane, since conventional backplanes do not have 90° connections. It should be pointed out that the thermal profile of an orthogonal mid-plane poses different challenges from that of a traditional backplane, since line cards are arranged horizontally and do not have the natural venting possessed by vertical line cards. The PCBs used in backplanes are evaluated regularly, particularly for cost and performance. The pursuit of higher speed and performance on the board re-

vealed the advantages of counter-bored vias, which have influenced connectors as this method of improving board performance gained acceptance. Designers have previously manipulated board materials to help optimize speed and performance, but board material selection is becoming a primary concern. Increasingly, high-speed backplane designers want to future-proof their systems so that more and more backplane designs can accommodate the higher speeds expected later in their design lives. To facilitate this, designers may use some components, such as connectors, capable of operating at higher speeds than those at which they are currently used. Designers should balance the need for futureproofing with the backplane’s expected lifespan. This is usually accomplished by using a connector with the highest speed capability on the backplane, then letting the mating line card interconnect evolve to the expected higher speeds. In this scenario, the backplane’s lifecycle is assumed to be longer than that of less costly, easierto-replace line cards. Other trends in backplane design have a lesser or indirect impact on interconnects, such as quad routing. Here, the columns of signals are spaced far enough apart so that two differential signal pairs can pass between them. For applications that can sacrifice density, this increases the amount of signal placed on a single layer, resulting in thinner boards, fewer layers and, consequently, lower cost. Alternatively, some designers may invest in better board materials in addition to quad routing, providing an even higherperforming line card or backplane. Additionally, with potentially thinner boards, shorter via stubs result and counter-boring may not be necessary. With shorter via stubs, signal performance is better, and if counter-boring is not required, manufacturing costs are reduced. In the end, higher-performing connectors are probably better suited for quad-routed applications and enhance overall backplane performance.

Connector Board Attachment Methods

to the backplane, and has allowed acceptable performance to date (Figure 3). Alternatives include surface-mount (SMT). Currently, the use of SMT connectors in backplanes is limited because of considerable manufacturing concerns, including co-planarity, inspection and repairability. However, some speculate that SMT connectors may offer a better board attachment method for backplanes because of possible improvements in electrical performance, such as reducing the size of, or altogether eliminating, board vias to the layers in some applications. The main part of the discussion regarding attachment methods involves the performance improvements that SMT might provide and whether a transition to SMT would allow enough improvements to counterbalance cost, manufacturing process changes and industry acceptance issues. Others caution that improvements will be marginal and further development is required, but with many seeking a way to get to 25 Gbits/s, SMT is not off the table. The gradual movement toward higher-speed backplanes results from many influences. While improvements in speed and performance are top priorities, some questions remain about how to get there. Certainly, connectors will play a role in many of the future needs of highspeed backplanes. A gradual evolution in connector performance and design is expected. The development of new silicon to power backplanes will undoubtedly drive much subsequent design activity. Further, with the new silicon, additional, more functional topologies may emerge that will help improve performance. Materials and other components will likely follow with innovations to accommodate the new performance requirements. After the first successful attempts to get to 25 or 100 Gbits/s, all participants will begin developing new tools to tweak and optimize each respective part of the backplane, and the cycle will continue. Tyco Electronics Harrisburg, PA. (717) 986-7777. [].

Another key issue is connector board attachment methods. Press-fit is the known, reliable method for attaching a connector January 2007


SolutionsEngineering High-Speed and Hybrid Backplanes

Designing High-Speed Backplanes with PCI Express High-speed backplane design is in the process of a major transition as older parallel bus structures give way to new serial buses with blazingly fast signaling speeds. The most significant of these is PCI Express.

by S  teve Cooper One Stop Systems


lready pervasive in desktop and laptop systems, PCI Express (PCIe) is now poised to move into traditional industrial bus boards. It is poised to replace legacy PCI as the bus structure of choice for nearly all applications, including those based on embedded or industrial form-factors. Already the bus’s electrical definition has been added to over 60 unique bus form-factors. But PCIe is a new kind of bus structure that is, in many ways, more complex than its predecessor. Implementation of PCIe backplane systems requires an extensive knowledge of this new structure, including its new architecture, high switching speeds and particular sensitivity to noise buildup throughout the system. To understand PCIe, it is best to start with an understanding of what a “lane” is. The lane is the basic building block of PCIe and is defined as two low-voltage differential pairs of signals that allow communication between two PCIe devices (Figure 1). Each differential pair is unidirectional, and the connection is entirely point-to-point. Additionally, the clock timing is embedded within each differential pair using a technique known as 8/10b encoding. 30

January 2007

Each lane is unidirectional, so bus interface components do not have to change direction; therefore, they are either always driving or always receiving. Since the bus is point-to-point, there is no need for arbitration, nor are there any stub traces to multiple drops to distort signal quality. There is no skew between the clock and the signals because the clock is embedded in the signal. Since the signaling is done through low-voltage differential pairs, the transition time is quick and any external noise will affect both wires. Consequently, that noise will not alter the difference between the two wires. All of these factors allow the data transfers across the PCIe bus to occur at substantially higher rates than they do across the legacy PCI bus. The signaling for PCIe occurs at a fixed clock rate of 2.5 GHz. This is ap-

Figure 1

A PCIe lane is defined as two pairs of traces, one transmitting data and the other receiving it.

Lane Width

Transfer Rate for Gen 1 Timing

Transfer Rate for Gen 2 Timing


500 MB/sec

1 GB/sec


2 GB/sec

4 GB/sec


4 GB/sec

8 GB/sec


8 GB/sec

16 GB/sec

Table 1

Performance of PCIe Links with Different Lane Widths

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Figure 2

CompactPCIe backplanes can include a mixture of CompactPCIe and legacy CompactPCI slots.

proximately 10 times faster than the fastest version of PCI. This clock rate is expected to double to 5 GHz in an update to PCIe known as Gen 2 timing. The specification for Gen 2 timing has already been approved and the first products utilizing Gen 2 timing are expected to appear later this year. In order to achieve even higher performance, PCIe defines connections with multiple lanes. For example, a x4 connection utilizes four complete lanes for the connection. The interface components at each end of the connection divide the transfer to go across the four pairs in parallel, and at the other end re-construct the data. The specification allows lane widths of x1, x2, x4, x8, x16 and x32, although in practice the x2 and x32 are rarely used. The high level of performance is the key feature of PCIe (Table 1).

Incorporating PCIe into Existing Form-Factors

Since most applications are well suited to their existing physical form-factors, the industry has taken the approach of simply replacing the PCI bus with PCIe while using as much of the existing formfactor definition as possible. The one area that requires change is the interface con-

Figure 3


nector that carries PCIe signals. Connectors used for legacy PCI are insufficient to carry these high-speed signals, particularly at Gen 2 clock rates. Therefore, for each bus structure, the legacy connectors used with PCI have been replaced with new high-speed connectors for PCIe. Two of the more popular embedded form-factors with PCIe versions are the PICMG 1.0 or passive backplane formfactor and the CompactPCI form-factor. The upgrade to PICMG 1.0 is called System Host Board Express (SHBe). This standard defines a special slot that contains the CPU electronics that are traditionally found on a motherboard in the form of an add-in board. Thus, systems can be constructed with a separate CPU board, a passive backplane and a number of I/O boards. This approach facilitates several applications where more or different types of slots than are found in a traditional PC are needed. System Host Board Express systems also tend to be more rugged and have much shorter mean-time-torepair characteristics than desktop PCs. The wide variety of unique SHBecompatible backplanes is key to this formfactor’s flexibility. These backplanes can include all PCIe slots. Alternatively, with the use of bridges they can include a mixture of PCIe and legacy PCI slots. The ability to utilize any SHBe CPU board in any backplane allows the construction of a nearly limitless number of unique system configurations. The upgrade to CompactPCI is called CompactPCIe. This upgrade replaces the connectors known as P1 and P2 with four new connectors that occupy the same “air space.” The new connectors provide the high-speed PCIe signals as well as improved power to each board. CompactPCIe is the preferred form-factor for rugged, fault-tolerant and/or multiprocessor

Examples of how to properly lay out traces to deal with trace length mismatch.

January 2007

systems, and is particularly popular in military, industrial control, communication and instrumentation applications. CompactPCIe has been adopted as the basis for the new version of the PXI instrumentation standard, called PXI Express. This standard allows CompactPCIe boards to be used with instrumentationspecific boards that have additional timing and trigger lines defined. CompactPCIe is a classic modular compute architecture that lets designers select CPU boards, I/O boards and backplanes independently and easily integrate them to solve unique application challenges. CompactPCIe backplanes can support up to 21 slots total, with any combination of CompactPCIe and legacy CompactPCI slots (Figure 2).

Backplane Design Parameters

Due to the high speed of PCIe signals, a number of new techniques are needed to ensure reliable data transfer. These techniques primarily focus on keeping the two traces involved in each differential pair “matched.” Ideally, the PCIe signals that propagate on the two traces constituting the differential pair should appear as the mirror reflection of each other: one positive and the other negative. As long as this matching continues, any external electrical noise will couple into each signal equally and will not affect the combined differential at the receiver. Unfortunately, there are physical challenges in backplane layout that cause this mirroring to break down. There are several guidelines for designers that can help reduce the negative impacts of these phenomena. Maintaining tight spacing between the two traces of a differential pair located physically close together is critical. Typically, traces should be 4 mils wide separated by 4 mils of spacing. In addition, trace lengths must also be matched: the two traces of a differential pair must be nearly identical in total length. Typically, this means that their lengths must be matched to within 3 mils of one another. Any length mismatch that occurs between the two traces should be corrected as close as possible to the point on the board where the mismatch occurs. Length mismatches usually occur due to turns (the outside trace has a longer path) or where traces pass through connectors (Figure 3).

SolutionsEngineering Minimizing stubs is another major strategy. Stub traces that branch off from either signal must be minimized or eliminated altogether. Stubs commonly occur where traces pass through vias or connectors. In connectors, a stub is created where the pin of the connector goes all the way through the board, whereas the trace routing the signal is connected at one of the layers. For vias, the stub problem can be corrected by reverse drilling the via; however, this technique is expensive and typically not required.

change over to the new bus structure, allowing designers the flexibility to mix and match modules to build new high-performance systems. The expertise and equipment needed to design these new systems is extensive and requires significant investment throughout the embedded computer community. The enormous marketplace for PCIe-compatible products has allowed oscilloscope manufacturers to automate the process of specification compliance validation. With the aid of these new product

validation tools, specification compliance and multi-vendor product interoperability will be enhanced. As designers gain experience with these new tools and techniques, PCIe technology promises to revolutionize system performance and facilitate a new generation of embedded systems with high feature content. One Stop Systems Escondido, CA. (760) 745-9883. [].

Design Validation Tools

The result of careful design is a high level of signal integrity at the receiver end of each differential pair. In order to assure multi-vendor product interoperability, the PCI SIG has developed extensive definitions and product validation methodologies for PCIe-compliant products. Makers of high-end oscilloscopes and other instruments have incorporated these parameters and methodologies into their products, making validation testing straightforward. For example, Tektronix’s high-end oscilloscope product line has a special PCIe compliance software program that presets the oscilloscope to the correct settings and automatically runs the PCIe compliance testing. This software then automatically generates a full compliance test report, including pass and fail indications for specific areas. The key parameters that require validation are the signal “eye” diagrams and jitter. The eye diagrams illustrate how cleanly the differential pair transitions from one state to another. The well-defined “keep-out” area—the diamond shape in the middle of the signals—gives these diagrams their distinctive look. High-end oscilloscopes test the signal transitions for millions of transfers and note any occurrence of a signal infringing on the keepout zone. PCI Express takes buses to a new level of performance by utilizing new techniques for transferring data. Over the next few years, this technology will move from the desktop into traditional embedded bus form-factors. These upgraded buses will look strikingly similar to their predecessors, but will be distinguished by their use of new types of connectors. Modular CPU boards, I/O boards and backplanes will all January 2007


IndustryInsight RFID Infrastructure

Supply Chain Management Challenges RFID Technology Although the challenges of implementing RFID tracking in supply-chain management are many, an infrastructure is gradually being put into place.

by Ann R. Thryft Senior Editor


adio frequency identification (RFID) is a major enabling technology of real-time location systems (RTLS) that provide location tracking of assets in real time, usually in a closed-loop network based on WiFi and/or other wireless network protocols. It has been used in automotive vehicle identification for over 15 years, but the focus of much effort today is on using RFID to track products for supply-chain management. Several barriers to full-scale, widespread deployment of RFID in the supply chain remain. These include the cost of RFID tags for the higher frequencies needed, lack of standardization of networks and tag data, moving tag data from the pallet level to the item level and integrating RFID networks into existing systems. However, major pilot programs have been conducted and some systems are now in place. For example, last year Toshiba began using ultrahigh frequency (UHF) Generation 2 RFID tags to track laptops at its plant in Regensburg, Germany. 34

January 2007

Figure 1

Software defined radio (SDR) promises to bring lower cost and greater flexibility to RFID readers. Texas Instruments’ Small Form-Factor SDR Development Platform is a hardware/software co-development environment that supplies the full signal chain for a multi-protocol SDR, including RF front-end module, A/D and D/A data conversion module and digital processing module.

“The infrastructure for RFID in supply-chain management using ultra-high frequency is slowly being built out based on the mandates of major retailers,” says Bruce Roesner, chief technology officer of RFID reader maker Sirit. “We’re going to get there, but it will take some time. As you move from high-frequency to ultra-high frequency applications, the level of complexity and difficulty rises steeply. There are far more tags being read in a given time unit and each tag has a lot more information on it, so system usage and complexity increase.” Infrastructure includes not just tags and readers, but also sensor networks, as well as

systems for data collection and analysis. Ultra-high frequency readers for the retail supply chain exist but in lower volumes, says Jeff Kohnle, director of asset tracking for Texas Instruments’ RFID business, which makes the passive devices used in RFID tags for global asset tracking and secure/contactless applications. “Supply chain RFID is happening now at the level of cases and pallets, but the goal is to get to the item itself, beginning at the factory in China where the iPod goes into a box.” Most current readers are proprietary designs that use both DSPs and ASICs. Very few semiconductor manufacturers are


producing ASICs for readers in UHF applications and those are being sold in low volumes, says Roesner. Today, an RFID reader for UHF systems consists of discretes and generalpurpose processors, according to Kevin Ashton, marketing vice president of RFID reader maker ThingMagic. As chips have gotten denser, more complex data can be placed on tags so many tags can be read at once and over the longer read ranges required in supply-chain applications. “Although ASICs are already used in older high-frequency systems, longer-range UHF systems are a much harder problem to solve with ASICs,” he says. “It’s going to take a few years before hardware is commercial. This year will see the first custom ICs for supply-chain management RFID readers, and a number of reader ASICs will be launched during the first half in low volumes.” A new approach to designing RFID readers is software defined radio (SDR). Many, including SDR-based RFID reader pioneer ThingMagic, say this architecture is necessary to achieve the cost and flexibility needs of deploying large-scale supply-chain management RFID. TI’s Small Form-Factor SDR Development Platform lets developers easily design waveforms as well as create and test single- or multi-protocol radios for RFID readers (Figure 1). Instead of a single fixed architecture, the platform separates out baseband, IF and RF as distinct modules, so developers can optimize for cost and power consumption by substituting their own or third-party modules. The ability to quickly and remotely upgrade SDR-based hardware is valuable in a large-scale environment and can make possible a much less expensive infrastructure. But to a large extent, the main challenges in supply-chain management RFID lie less in the hardware than in the complexity of installation and deployment. In addition, work is needed on application software to manage real-time messaging both within and between companies. “Most application software is not really designed to deal with highly automated, always-on data,” says Ashton. Middleware is also needed to integrate other existing wire-

less systems, and there are human interface issues, since RFID will bring computing to people that don’t normally use it. Standardization will be required for the large-scale deployments envisioned for UHF supply-chain RFID systems. But the RFID standards situation is very complex, in part because of the complexity of RFID itself, says Roesner. “There are a number of standards within a given frequency. Within each of those standards there are several different versions and a number of options for each version.” A move in that direction is the Generation 2 air interface standard for communication between RFID readers and tags, administered by EPCglobal, which will allow more information to be stored on each tag, provide greater security, and better address RFID environments that contain multiple sources of interference. Earlier this month, Odin Technologies, an RFID integration and software development company, released the first RFID EPC-compliant Generation 2 tag benchmark. The benchmark includes performance testing for distance, orientation sensitivity, material type, modulation depth and quality. Odin publishes the RFID Benchmark Series, the industry’s first and most referenced head-to-head performance analysis of leading RFID tags and readers. Odin Technologies Dulles, VA. (703) 968-0000. []. Sirit Toronto, Ontario, Canada. (416) 367-1897. []. Texas Instruments Radio Frequency Identification Systems Plano, TX. (800) 962-7343. []. ThingMagic Cambridge, MA. (866) 833-4069. [].

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January 2007


IndustryInsight RFID Infrastructure

RFID Tag Data Security Infrastructure Strengthens Pharmaceutical Supply Chain When combined with a secure tag and data infrastructure, RFID technology can assure both package authenticity and origin in high-value goods supply chains. by Joseph Pearson Texas Instruments Radio Frequency Identification Systems


exploration er your goal peak directly al page, the t resource. chnology, and products


aising confidence about the authen- ing both network-based and off-network ticity of its prescription drugs is the deployment options, a tag data security end goal for the pharmaceutical in- infrastructure (TDSI) offers a “common dustry, especially as the number of coun- ground” approach for all parties. terfeit, gray market and diverted products continues to climb. Radio frequency Deploying RFID at the Item identification (RFID) technology, when Level combined with a secure tag and data inOne of the primary reasons the pharfrastructure, can assure both package au- maceutical industry is exploring RFID thenticity and pedigree while creating new technology at the item level is because it revenue opportunities. In addition, while offers external validation of a product’s mpanies providing solutions now manufacturers, distributors and retailers authenticity and provenance. Determining oration into products, technologies and companies. Whether your goal is to research the latest continue expandtechnical collaborative RFID whether isorto put notyoupharmaceutical products lication Engineer, or jump to atocompany's page, the goal of Get Connected programs, and may agree on their in the supply chain are genuine, automativice you require pilot for whatever type of technology, ies and productsgoals, you arethey searching arefor. not all on the same page cally and without human intervention, is when it comes to deployment methods. simply not economical without RFID. For the pharmaceutical industry to RFID tags applied to products within create a secure supply chain using RFID a secure infrastructure raise the level of technology at the item level, a broader confidence that the product is genuine on and more flexible approach is needed, two fronts: by determining the authenticone that addresses all stakeholder re- ity of the packaging, and by providing quirements and provides a range of automated traceability, that is, creating implementation options. Designed to an itemized electronic pedigree or record expand and unify the industry’s informa- that shows an item has passed through aution technology ecosystem by incorporat- thorized entities (Figure 1). Although all stakeholders in the pharmaceutical supply chain appreciate the Get Connected with companies mentioned in this article. value of these RFID benefits for item-level tagging, there are three essential elements

End of Article


January 2007 Get Connected with companies mentioned in this article.

Figure 1

A pharmaceutical bottle is equipped with a Texas Instruments RFID tag consisting of a chip and antenna.

necessary to move the industry from selective pilot programs to full-scale deployment. These are participation by all segments, including manufacturers, distributors and retailers; the development of an item-level tagging specification; and an information technology infrastructure that employs both centralized and decentralized applications.

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dustry-driven standards for the Electronic Product Code (EPC) to support the use of RFID in today’s supply chain networks. The EPCglobal standards process provides a forum for both the pharmaceutical industry and the RFID technical community to share ideas and work together on a common course of action.

How the Tag Data Security Infrastructure Works Figure 2

High-value goods susceptible to counterfeiting are scanned with RFID readers.

What Is a Tag Data Security Infrastructure and Why Is it Needed?

The ability to have deployment “options” within a “standard” item-level tagging infrastructure is not an oxymoron. The TDSI is a set of rules, specifications and common protocols that allow itemlevel tags and readers to work within and across the industry’s information technology ecosystem. First, the TDSI always supports network-based applications. Second, it bridges the centralized/decentralized infrastructure divide that exists among pharmaceutical sectors by augmenting network-based applications with the capability of anytime, anywhere authentication and product information. The TDSI addresses the contentious points of whether or not to put product data, such as the National Drug Code (NDC), on the tag, as well as how to authenticate products, methods for ensuring consumer privacy and how to secure tagged products at the case, pallet and item level. An item-level tagging standard has yet to be defined. Therefore, the timing is right for RFID tag, reader and security technology providers to bring a fresh solution to the industry as it debates the specifications, rules and methods of supply chain collaboration in the standards development process that is ongoing within the EPCglobal standards organization. EPCglobal is leading the development of in-

An Electronic Product Code number (see sidebar) should be programmed onto the tag as the cornerstone for pharmaceutical product identification. The TDSI can be used to incorporate both network and off-network capabilities that support the available infrastructure in the pharmaceutical supply chain ecosystem. For example, to answer the question of where product data such as NDC should reside—on the tag or not—the TDSI can accommodate both scenarios by providing options as to how the EPC number contains product data: either encrypted on the tag or accessed through a network link. In the network scenario, a new version of an EPC numbering scheme is introduced that contains no product information in the data structure of the EPC. Here, the tag’s

product data is held in a central database where it is referenced by the EPC number as a unique pointer. By contrast, product information is not currently included on the tag because encryption is not addressed. So either pilot-stage closed loop networks are being used or, alternatively, off-network authentication of products is occurring but without including the product information. Without this product information, retailers cannot do automated inventory of their products once they put them on the shelves. The Serialized Global Trade Identification Number (SGTIN) is a method of identifying unique items at the unit or retail level, as well as at the case and carton levels. For an EPC numbering scheme using SGTIN with encryption, the tag’s product data is digitally scrambled or signed using private key and cryptographic software in an RFID reader, and can only be decrypted by a reader with the appropriate corresponding public key and software. The product information can then be made available for local applications, such as smart shelves. Because the EPC number maintains its uniqueness, it can still be used as a unique pointer for network applications.

EPC Gen 2 tag data structure with encryption Centralized Data Access Decentralized Data Access

Reader with Decryption Software

Figure 3


Header Data Fields

Manufacturer Identification

Product Class

Serial Number

EPC golbal Pharma Type 2 - item level Acme Pharma Inc. NDC: 0903-0303-30 E N C R Y PPolotium TC: 0903-030 ED Unique #


Centralized Data Access


In the EPC Generation 2 tag data structure with encryption, only the product class information portion of an EPC number is encrypted. This allows both standard readers with no decryption capability (right) and EPC-compliant readers with decryption software (left) to process tag EPC numbers to the EPCglobal Network. EPC-compliant readers also decrypt product data for local use. January 2007


IndustryInsight The currently used 96-bit EPC SGTIN numbering scheme has four basic data elements: a header, a manufacturer ID, product class information and a serial number. Using TDSI, only the product class information portion of an EPC number is encrypted. This allows standard readers that have no decryption capability to process tag EPC numbers to the EPCglobal Network for centralized data processing. EPC-compliant readers with decryption software are able to both decrypt product data for local use and forward the tag EPC number to the EPCglobal Network (Figure 3). Furthermore, EPC-compliant readers with decryption software can work with non-encrypted item-level tags and the EPCglobal Network.

Encrypting tag data requires special reader software and distribution of cryptographic keys. The TDSI should employ a single standardized cryptographic methodology for tags and readers and the cryptographic approach should provide both authentication and product encryption capability. As stated previously, a standardized cryptography method should be used as part of the TDSI for tag encryption and authentication. The IEEE has developed the IEEE Standard 1363a Elliptic Curve Cryptographic (ECC) algorithm as a new standard for public-key cryptography. The National Security Agency (NSA) has selected ECC as critical technology for protecting mission-critical national security information. The NSA has de-

The Electronic Product Code, the EPCglobal Network and Generation 2 The Electronic Product Code (EPC) is a method of product identification that uniquely identifies objects in the supply chain, such as items, cases, pallets or locations. It is built on a basic hierarchical structure that can be used in a variety of existing numbering systems, such as the EAN.UCC System Keys and Vehicle Identification Number. Like many other numbering schemes used in commerce, the EPC is divided into fields of numbers that identify the manufacturer and product type. In addition, it uses a serial number field to identify unique items. The EPC is the key to the information about the product it identifies that exists in the EPCglobal Network. An EPC number contains several components. These include a header, which identifies the length, type, structure, version and generation of EPC; a manager number, which identifies the company or company entity; the object class, similar to a stock-keeping unit, or SKU; and a serial number, the specific instance of the object class being tagged. In order to properly encode and decode information from different numbering systems into human-readable forms, additional fields may be used. The EPCglobal Network enables automatic, immediate identification and sharing of information on items in the supply chain. Version 1.0, released in September 2003, offers technical information on the number system, tag, readers and reference implementations on software components. (Source: Generation 2, or “Gen 2,” is the second-generation air interface standard for communication between an RFID reader and tag, administered by EPCglobal. Currently, ISO/IEC 15693 (high-frequency) and EPC Gen 2, Class 1 (ultra-high frequency) are the two internationally accepted air interface protocol standards being used by the pharmaceutical industry. In addition, a few proprietary protocols are being implemented in pilot programs. A single RFID air interface communication standard is necessary for industry-wide deployment. EPCglobal has active working groups to create item-level tagging (ILT) specifications with the air interface communication attributes necessary to meet performance requirements. It is anticipated that ILT specifications will be ratified by mid-2007, and that they will include faster data rates for reading and programming.


January 2007

fined two algorithm families for use in U.S. government communications: Suite A and Suite B. The Suite A family consists of secret algorithms. Suite B is a standardized set of algorithms designed to meet U.S. government requirements for sensitive but unclassified secret and top-secret levels of security. Included in Suite B are ECC for the public key and key agreement protocols, and the Advanced Encryption Standard (AES). ECC security has many benefits in RFID applications. It allows very fast signature creation ensuring no incremental delays in production line operation and a level of security equivalent to 1,024-bit RSA encryption, while using considerably less tag memory. The EPCglobal 96-bit product class information can be encrypted. Any standard reader can read the 96-bit number from an encrypted tag, and can forward it to the EPCglobal Network as a “pointer.” Finally, readers equipped with the verification key can both authenticate the tag and decrypt the product class portion of the EPC number off-network. One of the primary advantages of ECC RFID security for item-level tagging is that it employs conventional levels of IC processing capability used in supply chain RFID tags, thus achieving a higher level of security without increasing the chip’s complexity or cost. An item-level tag that incorporates ECC RFID security requires a 64-bit tag identifier (TID) and 352 bits of user memory, which includes the EPC number, digital signature and encrypted product information. It is expected that the new ILT air interface specification that will define how tags talk to readers will also incorporate faster data exchange rates, reducing the time it takes to read and write to a tag when employing ECC RFID.

Achieving the Tag Data Security Infrastructure

The TDSI is designed for flexible and secure ILT deployment throughout the supply chain that will support the major concerns of the various industry and government stakeholders. These include product authentication; electronic pedigree; product information; consumer privacy; case-, pallet- and


All Other Commodities

Wearing Apparel 15%


Pharmaceuticals 2%


3% Watches/Parts

3% 5%




9% Toys/Electronic Games 10% 9% 10%


Consumer Electronics Footwear

Figure 4

A tag data security infrastructure for item-level tagging is applicable to a range of high-value branded goods susceptible to counterfeiting, as shown by the categories of counterfeit products seized by the U.S. Customs and Border Control in 2005. (Source: U.S. Customs and Border Protection, L.A. Strategic Trade Center.)

item-level security; supply chain data exchange; and a standards-based, interoperable infrastructure. From a technical perspective, the various working groups currently in the process of defining the EPC ILT specification for high-frequency (HF) and ultra-high-frequency (UHF) RFID networks should consider adopting the IEEE Standard 1363a ECC algorithm. To make the hardware infrastructure available to the industry, reader manufacturers and other RFID solution providers should incorporate the IEEE 1363a ECC standard into their devices as part of their product offerings. EPCglobal has established a certification procedure to address both compliance and interoperability for UHF RFID systems, in parallel with the introduction of the Generation 2 air interface specification (see sidebar). In a similar manner, EPCglobal’s role in establishing an itemlevel specification should extend to the selection of a certifying authority for the public-key cryptographic infrastructure.

The role of that authority will be to issue certificates to authorized supply chain participants and manage the allocation of private and public keys. Although outside the scope of the TDSI, additional security measures can be considered in the ILT standard, such as password read/write and/or a kill command that would completely deactivate the tag. Prior to the availability of new products based on the ILT standard, pharmaceutical supply chain participants can conduct TDSI pilot programs using ISO/ IEC 15693 standard tags and readers because they have the required 64-bit TID user memory for deployment.

a sophisticated level of security in the supply chain while creating a more flexible approach and a range of options for implementation. Although the proposed infrastructure is being developed initially for the pharmaceutical industry, it is an approach for item-level tagging in a secure, yet open, supply chain that is applicable to a range of branded goods markets such as highvalue cosmetics, apparel, sports collectibles, antiques and art (Figure 4). Texas Instruments Radio Frequency Identification Systems Plano, TX. (800) 962-7343. [].

Tag Data Security for ILT of High-Value Branded Goods

A foundation for tag data security in an infrastructure for item-level tagging is possible that provides both networked and off-network capabilities to address the requirements of all pharmaceutical supply chain participants. It incorporates January 2007


IndustryInsight RFID Infrastructure

SDR-Based Readers Keep Pace With Changing RFID Technology As RFID in supply-chain management moves from pilot programs to actual deployment, readers must continue to accommodate new protocols and standards. Platforms based on softwaredefined radio are flexible enough to keep up with these changes. by Margaret Wasserman ThingMagic


he challenge of RFID readers no longer consists of merely reading tags. Instead, now that the technology has moved past the stage of pilot programs and is being deployed for supply-chain management, these readers are taking on new strategic importance. The scope has widened to include issues such as integration into the corporate network, manageability, scalability, security, low total cost of ownership and especially avoiding obsolescence. Adopters of radio frequency identification technology are continually challenged to accommodate new RFID tags, update their RFID systems with the latest technology and implement new protocols, including EPCglobal Generation 2, which allows more information to be stored on each tag, greater security, and better addresses noisy RFID environments with multiple interference sources (Figure 1). Since RFID readers do the bulk of the tag processing required, users are tasked with determining which readers will perform best through their ability to utilize new technologies, protocols and upgrades. Recognizing that the reader is key to ensuring that RFID systems remain current with fast-changing technology, ThingMagic engineers made a critical commitment when designing the Mercury reader system. They decided to design an advanced software defined radio (SDR)-based reader platform for fixed, embedded and mobile readers. The result is an intelligent, network-ready reader that reads any tag. 42

January 2007

Tag Reader Network Architecture


Location 1 UHF

Location 2


Tag Reader 2

HF Location N


Inventory Database Server

Tag Reader 1

Tag Reader N

TCP/IP Network

Other Enterprise Information System


EPC Tags

Figure 1

Objects with RFID tags attached move through multiple locations. Tags use high frequency (HF) or ultra-high frequency (UHF) radio signals to communicate with RFID tag readers, which extract tag data, filter out redundant reads and send data to the network.

Mercury RFID Reader Hardware System Architecture

Conventional RFID readers were unintelligent data radios, reading a single tag protocol in a single radio frequency and communicating with a PC via a serial interface. Today’s SDR-based RFID readers are agile, intelligent data readers, TCP/IP network nodes and data processors able to simultaneously read multiple tags while filtering out interference from other RFID readers and wireless devices. The Mercury platform hardware con-

sists of analog front-ends (AFEs), a DSP, a network processor, memory and communications ports (Figure 2). The AFEs are essentially stateless; their hardware is designed to be protocolneutral. They are, however, optimized by frequency band to meet the requirements of the radio regulations in the geographical region in which they operate, for example, FCC Part 15 regulations in the U.S. or ETSI EN302-208 regulations in Europe. They are connected via high-speed A/D and D/A converters to a real-time signal processing system that is currently based on a 600 MIPS


Figure 2 An SDR-based RFID reader, such as ThingMagic’s Mercury platform, consists of an RF analog front-end, a DSP, a network processor, memory and communications ports.

Texas Instruments DSP. This DSP uses ThingMagic’s proprietary, real-time, signal processing software engine to manage all aspects of transmission and reception. The AFEs are capable of fully general I/Q modulation and demodulation with bandwidths up to a Nyquist anti-aliasing filter limit of 5 MHz (double sideband), allowing up to 10 MHz of incoming signal spectrum to be simultaneously digitized and processed. Protocol-related software is loaded into the DSP, which then controls how the AFEs communicate with RFID tags. In turn, the DSP is controlled by a network processor, currently an Intel IXP42x running at 266 MHz. The Mercury4 was the first RFID reader to use an Intel processor, the result of close teamwork between Intel and ThingMagic. The main function of the IXP42x in this architecture is to initiate tag searches, load protocols and process the results. It also handles backend networking and high-level developer interfaces. The DSP in both the Mercury4 and the Mercury5 is a high-performance, lowpower Texas Instruments TMS320VC5502. It provides 600 MIPS of processing on parallel multiply-accumulate pipelines at a clock speed of 300 MHz. Using a high-performance DSP allows the reader to switch between protocols in real time and quickly separate signal from noise. The most common RFID tags have no battery and reflect power from the reader, resulting in weak and noisy responses that often require advanced signal processing to decode. Coupled with the protocol-neutral AFEs, the high-speed DSP ensures that the reader’s hardware can read any tag that falls within its frequency band and regulatory setup, up to

the limits of a tag subcarrier frequency of 5 MHz on either side of the transmitted carrier. This accommodates all Generation 2 waveforms. Tag reading and writing is purely a matter of software. Once ThingMagic’s engineers have developed the appropriate protocol software, the Mercury platform can read and write to any tags that fall within the frequency band and regulatory regime supported by the AFE. Currently, Mercury readers can read and write to all variants of EPC Class 1 Generation 2 tags as well as EPC Generation 1 Class 1, Generation 1 Class 0, Class 0+, ISO 180006b and -6c and UCODE 1.19. All Mercury readers have at least 64 Mbytes of DRAM and 16 Mbytes of flash memory so that third-party software and


middleware can operate on the reader. This allows data processing to occur at the point of data capture for truly real-time operation, with no extra hardware at the edge of the network. This memory can also be used to buffer tag data in case of network disruptions or power outages. A standard 10/100 BaseT Ethernet port is provided for connection to corporate networks. An RS-232 serial port is also available for user applications, including controlling an external device and debugging user code. Two general-purpose input and three general-purpose output ports (GPIOs) are accessible through the serial port. These GPIOs can be used to allow external events to trigger a response from the reader, allowing the reader to be customized for specific applications. GPIO signal levels are compatible with standard RS-232 signal levels.


Maxwell Q404

Shannon Q205

Tesla Q405

Linux1 Real-time OS for RFID Tags buffered on reader

User programs on reader OS extension by end user Linux developer APIs Multi-region support (NA/EU/JP) 2

Reader personalization Conveyor belt API

Win32 developer API

Linux 2




NTP TFTP telnet


Cisco Catalyst Compatible

Reads any tag

EPC0 EPC1 ISO 18000-6B UCODE 1.19

EPC0+ Matrics

EPCO+ Impinj

GEN2 5


Web interface support APIs and reference code Developer Kit

Firmware push via API Firmware pull via reader Config. pull via DHCP syslog


Automatic policybased firmware upgrades 6

1 Open-source, free, industrial strength, operating system

3 Multiple dock-door portal synchronization for maximal system performance

5 Certified by EPCGlobal for GEN2 performance

2 Software is identical across regions

4 Support for high-speed GPIOdriven conveyor-belt operations

6 Readers upgrade themselves when new firmware is available on the network

Figure 3

The MercuryOS, designed for an SDR-based RFID reader platform, includes a user-programmable network operating system based on Linux that enables high-performance threading, scheduling mechanisms, memory protection and networking, as well as a real-time SDR system. January 2007


IndustryInsight While conventional RFID readers were essentially data radios, the Mercury4 is a full-fledged network device that can support mission-critical operations. In addition to managing a dynamic population of tags, then routing data into networks, databases and business applications, these readers speak TCP/IP natively. They also fully support standard network technologies such as DHCP, User Datagram Protocol (UDP)/IP over Ethernet, 802.11x, HTTP, SNMP and remote upgrades. d1

Specify your I/O requirements.

can receive and transmit new forms of RFID communication protocols simply by running new software on existing hardware. An SDR-based RFID reader consists of an RF analog front-end that converts RF signals to and from the reader’s antennas into an analog baseband or intermediate frequency (IF) signal, as well as A/D converters and D/A converters that convert these signals to, and from, a digital representation that can be processed in software running on the reader’s DSP. SDR-based readers store all protocol information in software, and use protocolneutral hardware to generate and detect radio waves. Conventional readers create protocols by adding hardware, so that changing protocols requires physically swapping out components in every reader in the field. For example, in a distribution center with 100 doors and a reader at each door, that would require swapping out components in all 100 readers. Clearly, the use of an SDR architecture can save considerable time and money. There are other significant benefits of SDR-based readers. With the addition of standard networking capabilities, including remote management, large networks of deployed SDR-based RFID readers can be upgraded in a matter of minutes from a remote console in a customer’s network operations center, becoming instantly capable of reading new types of tags. An SDR architecture can also be used to implement non-RFID functions. In the EU, the radio can be used to detect RF interference from non-RFID sources, a distinctly non-RFID function. This feature is called Listen Before Talk (LBT) and is required for European deployments. When operating in LBT mode, a reader first listens and tries to detect any RF signals in its channel. If it does detect such signals, it waits and tries again. If no other signals are present, the reader begins interrogating tags.

Choose your operating system.

The MercuryOS



SDR-Based Reader Architecture

By using an SDR-based architecture, readers can continue to be updated without the risk of being rendered obsolete. New tag protocols and features can be easily incorporated to existing hardware with a firmware update. ThingMagic pioneered the use of SDR for RFID applications. An SDR uses software to modulate and demodulate RF signals. It performs the majority of signal processing in the digital domain, most commonly in a DSP. SDR-based RFID readers


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January 2007

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All Mercury readers run ThingMagic’s MercuryOS reader operating system. It defines the company’s implementation of SDR and enables the hardware to easily adapt to new and changing RFID tag communications standards (Figure 3). For example, MercuryOS 2.3 Tesla, released in late 2005, upgraded the large deployed base of ThingMagic’s RFID readers to use an important new RFID tag protocol, the Class 1 Genera-

IndustryInsight tion 2 standard created by RFID standards body EPCglobal. This upgrade was certified by EPCglobal as complying with all aspects of the Generation 2 protocol, including Dense Reader Mode, which helps many RFID readers interoperate in one location. Since Mercury readers are full-fledged network devices, they could easily be remotely updated with the Tesla upgrade. This is a key proof point for the benefits of SDR in RFID: all other non-SDR-based RFID readers had to either be replaced, or required the installation of new circuit boards, in order to work with the Generation 2 standard. The latest major upgrade to this software, MercuryOS 2.4 Yagi, is scheduled for release this month. It improves overall tag reading performance by up to 400% and enables the Mercury5 to read 180 unique RFID tags per second, far more than other RFID readers. The MercuryOS consists of two parts: a user-programmable network operating system based on Linux, and a real-time SDR system. The network OS uses a full Linux 2.4 kernel, the same one used on many PCs and servers, but compiled for a different processor. This OS enables high-performance threading, scheduling mechanisms, memory protection and networking. The company’s engineers also developed a Reader Query Language (RQL) server as a simple but general network protocol that allows the use of syntax similar to Structured Query Language (SQL) to perform tag operations. No client software is required other than a standard Telnet application. Additional RQL commands that are not included in SQL allow RQL to support time-based operations. The server also provides tag-specific data (id, protocol_id) as well as event metadata (antenna_id, read_count, frequency) and enables timesynchronized operations. Developers can also use APIs, giving them a powerful way to customize Mercury readers to suit their needs, by enabling access to higher-level functions beyond what is available via RQL. Developers can write customized APIs, as well as use APIs created by ThingMagic. With the release of MercuryOS 2.3 Tesla, the ability to use Windows-based APIs is included, offering the flexibility to program in either Linux or Windows environments. The onboard Web server supports typical Web server functionality, including CGI

scripting. It can be used to serve static content such as help pages, dynamic read-only content such as status pages, forms to update settings and client-side Java applets. The Web server can be used to upload firmware, configuration files and user programs, and to perform firmware updates. The radio features of the SDR are controlled by the Mercury OS server. Protocol modules are stored in flash memory, which can be expanded to include as many additional protocols as required over time. By using an innovative SDR-based design, networked RFID readers can be

quickly and remotely upgraded with a single keystroke. This replaces the laborious handling of every deployed reader. In environments with dozens, or even hundreds, of deployed RFID readers, the upgrade efficiency delivered through SDR-based design dramatically increases ROI and maintains a reasonable total cost of ownership. ThingMagic Cambridge, MA. (866) 833-4069. [].

Essential building blocks … Innovative solutions. From Digital Signal Processing, to I/O interfaces, to IP cores and Software tools … ... at BittWare you’ll find the essential building blocks you need for your signal processing applications. Whether your application needs to thrive under extreme conditions of the battlefield, meet the ever-changing requirements of the communications market, or process highly-precise medical imaging data, BittWare has the capabilities to meet your needs. Reliable cutting-edge products are backed by timely delivery, reduced cost, and a dedicated support team – enabling your innovative solutions.

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January 2007


Executive Interview

“Never underestimate the ability of good engineers to overcome problems.” RTC Interviews Jeffry Milrod, President and CEO, BittWare

RTC: By and large, the embedded comUntil one system architecture or spec puter business has been going gangemerges with the critical mass to attract busters over the past two or three years multiple vendors, healthy competition and exploration r your goal with compound growth in the commulongevity, why bet the farm on any of these eak directly nications, commercial, medical, secu“better mouse traps?” Of course, most page, the rity and industrial sectors growing at customers will continue to play with new resource. better than double-digit rates. Only systems concepts and technologies in their hnology, nd products certain areas of the military have seen R&D labs; but they will be, and should be, programs delayed and business flat if very tentative with respect to actually denot down. Here at RTC, we happen to veloping new systems and/or products. be bullish about the industry and beCountering this negative developlieve that the industry will continue to ment is the fact that “the show must go enjoy this kind of growth. Do you beon.” For many customers, this means conlieve the industry is going to keep going tinuing to buy and build the older VME, in solutions the right CompactPCI, or PCI based systems. This panies providing nowdirection? What market segments doandyou envision growing scenario should provide board vendors ation into products, technologies companies. Whether your goal isatto research the latest fastest rate? Why? with some cation Engineer,the or jump to a company's technical page, the goal of Get Connected is tosafe, put youdecent margin continuing ce you require for whatever type technology, we’ve also expeMilrod: At ofBittWare, business from established design-wins. es and productsrienced you are searching for. tremendous growth the last few Other customers, such as the Military and years. But unfortunately, I predict that the commercial communications, need to get overall rate of growth for the COTS board new technologies deployed whether or not market will slow considerably in 2007, the standards are safe. These early adoptand maybe even through 2008. ers might provide significant rewards to My belief is based on the turmoil in board vendors who have taken great risks the industry regarding next-gen systems and find themselves in the right place at standards. Without a clear successor to the right time with the right stuff, but the VME or CompactPCI, I think many COTS success may still be short-lived if a difcustomers have adopted a wait and see apferent standard emerges victorious in the proach—I know I would in their shoes. long run. Ultimately, either of these scenarios Get Connected means that we should see some really with companies mentioned in this article. serious catch-up growth once one or two

End of Article


January 2007 Get Connected with companies mentioned in this article.

standards cross the chasm, enabling customers to safely release their pent-up demand for next-gen systems. Until then, I think both vendors and customers will have to proceed cautiously. RTC: I noticed that your product listing includes AMC cards. Does BittWare see a current market in this area or do you believe that market is still out in the future? How far? Have you been seeing AMC applications outside of the communications sector? Where? Milrod: Well, I never said I was very good at taking my own advice! Seriously though, this is a great example of BittWare proceeding with caution—while still attempting to lead. Thanks to some large lead customers who really wanted our high-end signal processing solutions on AMC, we’ve been able to blaze new trails without taking undue financial risks. As a result, I think we’ve been able to have our cake and eat it too. Without compromising our core competencies, customers, or existing design-wins, we’ve still been able to invest in some new, high-risk technology, and have given ourselves a chance to be in the right place at the right time with the right stuff. As an AdvancedTCA module, AdvancedMC is not very compelling; but


as a new, independent form-factor for use in MicroTCA systems, I’m thrilled with this format and excited about its potential. I strongly believe that switched fabric-based, small form-factor boards are the future of the COTS board market, and right now AMC in MicroTCA is the only game in town. We’ve done well with this format, and are forecasting significant growth for 2007. While it’s true that the bulk of our current AMC customers are commercial communications, we are seeing a lot of interest from the military and industrial markets as well. With a well-established market in the behemoth commercial communications industry, the emergence of the MicroTCA, and the promise of at least a semi-rugged version, AMC has great promise. Clearly, this is the most significant new format in our industry since the introduction of PMC. By the second half of 2007, we’ll know whether or not the MicroTCA platform has really gained acceptance; if the ruggedization spec happens, then we’ll know for sure if it will take off or not.

other words: it might not be the best spec, but it’s the only one we’ve got! We’ve been shipping AMC products for over a year now, and our customers have successfully built and deployed systems. To me, that’s the definition of a good spec. Also, one of my “truisms” is that you should never underestimate the ability of good engineers to overcome problems. In the early days of VME and CompactPCI, there were legions of problems; even now there are still issues with those mature systems, but everyone knows how to work around them. When there is the possibility of compelling solutions, clever engineers can, and will, overcome a multitude of limitations, as they have with VME and CompactPCI. My feeling is that AMC has gained a fair bit of momentum, and a lot of clever engineers are starting to think AMC is looking pretty compelling. At BittWare, we’ve already overcome several limitations, and are working at overcoming others. Also, don’t forget that there will be additional spec tweaks, and the environmental extensions are coming soon.

RTC: Many have been critical of the AdvancedMC and MicroTCA specifications as being inadequate for any but the most benign communications applications. In addition, it has been criticized for other limitations such as the maximum number of layers, frailty of the connector and lack of power management. Do you believe such perceived limitations will limit the useful applications for the spec? Milrod: No spec is perfect, and no matter what trade-offs you make, there will be people who disagree. We have certainly had our share of problems with AMC. We’ve blown up boards due to connector malfunctions, had to scrap finished designs because we couldn’t build the PCBs thin enough, had to re-spin working boards to accommodate spec changes, and continue to have PCB yield issues because our complex boards require so many layers. There is no doubt that designing and building AMC boards is challenging, but it is a real spec that supports small format switched fabrics, and it really works. In

RTC: There seems to be a trend in the embedded computer industry to attempt to supply more and more complete systems to OEMs thus climbing up the food chain in hopes of increasing revenue with the additional parts of the systems supplied. Many companies have done this through acquisitions that allow the company to provide additional parts of systems. Do you believe the industry will continue to consolidate in this way? At what point do you think embedded computer suppliers will begin competing with their customers? Will a time ever come when there are only a small handful of system makers and the traditional merchant board market will go away? Milrod: I think the main reason that many COTS board vendors have had to climb up the food chain is because the fragmentation of specs has made it extremely difficult to integrate boards together into a system, and because no one spec fragment has broad enough vendor support. BittWare got into systems inte-


January 2007

gration to lower these barriers to entry for our customers. However, we’ve been careful to provide this value to our customers without competing with them. Typically, this means providing a system and framework upon which our customers can build their applications, while stopping short of developing the actual application itself. Another important point is that we try to never force the customer to do it our way or to limit them to using only our proprietary pieces. If they want our stuff, great, we’ve got a bunch of stuff; but if they want to put some of their own secret sauce in, or add some other third-party component to differentiate their system, that’s fine with us. Once a new standard develops critical mass with broad support and customers gain experience with it, the barriers to integration will recede. Then I think we’ll see this trend reverse, and board vendors will, by and large, return to selling boards. RTC: RoHS has been the bane of just about everyone in electronic manufacturing in recent months. And, it is expected to have wide-reaching impact in the embedded computer industry where there is not enough volume to drive semiconductor makers to update ICs to RoHS compliance. It’s possible that many ICs such as PCI chips may well quickly go end-of-life. Do you think this will happen and cause a major disruption in technologies such as CompactPCI? PMC? What work-arounds do you envision? Can programmable logic take up the slack? Will there be other advantages if that’s the case? Milrod: Honestly, I don’t know what’s going to happen. Our customers are not asking us to move to RoHS, in fact quite the opposite, but clearly the high-volume consumer products are quickly moving over. I’m not a semiconductor business analyst, but it surely seems like the business case for continuing to make older, non-RoHS parts might be hard to make; justifying the investment to move these older parts to RoHS is even harder. Hopefully, these older parts will still be prof-

7 ( !4 - ! + % 3 ! 0 2 / $ 5 # 4 % 8 4 ) . # 4 



















itable enough for them to keep making a few lots every once in a while. I can’t think of anything in the past to compare this to, so there’s just no way to tell how this will play out. The work-arounds that we’ve put in place are twofold. First, we now support mixed process assemblies so that we can use RoHS parts on a non-RoHS board if that’s the only way we can get a given part. Secondly, we are increasing inventories of at-risk parts, and monitoring their status very closely. For us, I don’t think the programmable logic option makes sense. Since these parts would not be pin-compatible, they would necessitate a PCB re-spin which, in addition to being costly, might introduce latent bugs that could bite our customers in the butt. If we ever need to obsolete a board that our customers still want, I think it would be better for everyone involved if we invested in helping them upgrade to newer products rather than keeping the older stuff alive. RTC: IBM’s announcement of the Cell processor was initially hailed as a breakthrough in processing power. However, few in the embedded computer community have taken advantage of it outside of Mercury Computers. Do you believe the Cell processor has potential in embedded-computer systems going forward? What about some of the other dual or multicore devices based on established instruction sets? Milrod: Apparently, the Cell is a pretty awesome processor, but all that processing doesn’t do anyone any good unless it’s useable. Right now, using this processor is very, very hard. My guess is that the total available market for the embedded space is less than one week’s worth of PlayStation 3 production, so IBM doesn’t have a lot of incentive to invest in developing general-purpose tools, training, or support. This puts a tremendous burden on an embedded board vendor and their customers. The vendor must either create very sophisticated tools, or basically program the processor for the customer, or the customer must climb a very steep learning curve—all options that seem untenable. 50

January 2007

Another major concern I have about this processor is the thermal problem. As I’ve said previously, I think the future lies in small formats with switched fabrics. It’s hard to see how a Cell processor could support that type of embedding. Not only are other multicore processors with established instruction sets easier to use, many of them are sensitive to the requirements of portable devices, such as laptops, so they often have lower power versions available. I think they are still hard to use in embedded applications, but the amount of existing code and expertise is compelling. If you’ll indulge a brief stroll down memory lane, this question reminds me of similar questions I was asked a decade ago about the new C80 chip from TI. Remember that one? Most people don’t. It too was a video-oriented, multicore processor that had tremendous processing power and was touted as a major breakthrough, but it was a little hot and difficult to program. TI invested heavily in marketing, tools and training, and several companies built boards based on it. Ultimately, people found the potential simply wasn’t worth the hassles, and its use in the embedded computer space died quickly. RTC: What is going on in DSP? Are a lot of high-end DSP applications migrating to more general-purpose processors such as the Pentium and Altivec? Both of these are beginning to include instructions for DSP operations. Do you envision traditional DSP circuits such as those from ADI and TI eventually migrating to general-purpose processors? Why, or why not? What is the role of FPGAs in DSP? They seem to be taking hold in numerous applications that have been the domain of traditional DSP chips. Where do you think FPGAs fit in the continuum from general-purpose processors to DSP-exclusive devices? Milrod: Wow, that’s quite a question! I’ll try to hit the highlights. First off, it’s important to note that the DSP market as a whole is huge and very diverse. Secondly, I think the use and role of DSPs in the embedded computer and COTS board markets is changing rapidly.

DSPs are used to solve a broad range of applications in our community, most of which are complex and involve multiple trade-offs for processing capability, power consumption, scalability, interprocessor communication, real-time issues such as low latencies and determinism, I/O, and of course ease-of-use and cost. I think it’s fair to say that no one DSP can adequately address all of these issues for all applications, and the semiconductor companies seem to have stopped trying. Historically, most COTS DSP boards have featured floating-point DSPs. These are generally faster and more capable than their fixed point counterparts, and are significantly easier to program as well. Unfortunately, they also cost as much as an order of magnitude more, so volume applications quickly move their solutions to fixed-point implementations. From the semiconductor manufacturer’s point of view, this has left a limited market for floating-point DSPs, mostly prototype, development and lunatic fringe applications—not a compelling business case. While there are plenty of compelling business cases for semiconductor vendors to invest in fixed point DSPs, the need to optimize them for power and cost tends to cause these DSPs to be narrowly targeted at specific applications, and not well suited to general-purpose, high-end COTS solutions. Despite this, we haven’t seen application migration to Pentium or Opteron. These processors provide plenty of raw number crunching power, but they just don’t have the processing agility or sustained real-time capabilities that DSPs provide. We have seen some applications migrate to the AltiVec floating-point accelerator in the past, but recently, however, we’ve seen some backward migration as the PowerPCs with AltiVec are getting hotter and hotter. Given the fundamentally different nature of the processing and I/O requirements, I don’t see how GPPs can ever replace or incorporate high-end DSPs. Enter the FPGA. With the addition of specialized DSP blocks, these devices can do some serious DSP. It’s not easy, but it’s possible. While floating-point and complex algorithms are still a challenge, they are quite good at the hard real-time


data movement, I/O and low-latency, deterministic number crunching problems, and they continue to improve at the power and cost issues. That being said, I don’t see FPGAs obviating the need for specialized DSP chips. I think that both of these approaches to high-end signal processing, that is FPGAs and DSPs, are more complementary than competitive, and that even GPPs can add value for certain applications. I now believe that intelligently combining these technologies is the optimal way to approach signal processing. Therefore, we’re investing a lot of time, money and energy creating hybrid signal processing architectures and boards that provide FPGAs in combination with DSPs and GPPs.

duce development time. Our ATLANTiS FPGA framework is being completely overhauled to take advantage of Altera’s SOPC Builder tools and IP cores, and we plan to significantly expand our own IP offerings and integrated FPGA solutions. Finally, you’ll see more ruggedized and application-targeted boards and systems from us. Our customers are pulling us hard into these arenas, and who are we to deny them?

Thanks for giving me the opportunity to share my thoughts in this great publication; it has really been an honor. BittWare Concord, NH. (603) 226-0404. [].

RTC: BittWare has been a leader in providing DSP technology on a variety of platforms with a variety of different processor approaches. What can our readers look forward to from BittWare in coming months? Milrod: We will continue to provide essential building blocks that enable our customers to create innovative signal processing systems. Based on what I’ve already said here, these will be primarily focused on switched fabrics, small formfactors and hybrid signal processing, along with the software and frameworks to make them more useable. I’m particularly excited about the integration of Altera Stratix II FPGAs on our latest VME/VXS, 3U cPCI and AMC offerings. This has allowed us to implement switched fabrics such as Serial RapidIO and PCI Express, in addition to leveraging these powerful FPGAs in our new hybrid signal processing architectures. We started out adding FPGAs to our DSP boards, and now it seems that we have moved toward FPGA boards that have DSPs on them. In fact, we will soon be releasing some FPGA-only boards. We are also already working with Altera on Stratix III designs. Recently, we announced our Trident real-time multiprocessing operating environment for the TigerSHARC DSP, and we hope to extend this to the FPGAs in order to create a hybrid operating environment that should greatly reJanuary 2007


Software&Development Tools Software for Multicore

Software for Multicore Processors Advances in processor technology in the areas of multicore security and virtualization allow new paradigms for embedded application design that allow developers to combine the best principles of multiprocessing, virtualization, real-time and hard partitioning. by Arun Subbarao LynuxWorks


f late, innovation in processor architecture has been focused on creating multicore processors. Multicore processors introer exploration duce two or more processing cores in a single chip, thereby ether your goal speak directly allowing operating systems and applications to avail themselves of ical page, the increased computing power. One of the significant advantages of ght resource. multicore processors is access to additional computing resources technology, es and products without any significant increase in size and weight. Previous generations of multiprocessing configurations involved two or more physical chips that required additional real estate on processor boards. The immediate benefits are obvious; applications that were designed around uniprocessor configurations can replace uniprocessor cores with dual or quad core processors. The computing power of these configurations increases dramatically with no appreciable change in their physical configuration. mpanies providing solutions now The software impact of multicore processors is fairly immeploration into products, technologies and companies. Whether your goal is to research the latest diate on operating system design. The OS has to adapt to support pplication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you symmetric ervice you require for whatevermultiprocessing type of technology, (SMP) or asymmetric multiprocessing (AMP), majorfor.approaches for support of multicore processors. anies and products you aretwo searching The operating system design has to adapt in the areas of scheduling, interrupt handling, synchronization and load balancing. Application programs can also be affected by multicore processors based on the ability of the OS to provide fine-grained control of process scheduling to applications. For example, an application can make a request to execute on a specific processor core only. However, the increase in compute power through multicore processors can be better harnessed through another recent trend in OS design, namely, virtualization.


End of Article

Virtualization in RTOS design

Virtualization is a technique used to create an execution enGet Connected vironmentwith forcompanies softwarementioned that is insimilar to the one it was originally this article. designed for, but on a different hardware or operating system. Virtualization can be achieved usually at two levels: operating system Get Connected with companies mentioned in this article.



January 2007

virtualization and hardware virtualization. Operating System virtualization is done using binary compatibility layers that run on heterogeneous operating system environments, while presenting an interface similar to the original OS environment. This is most often done to achieve migration and execution of applications across multiple heterogeneous operating system environments. For example, the ability to run Windows applications on Linux uses a virtualization technique that simulates the behavior of the Windows operating system on Linux. Hardware virtualization involves the emulation of the underlying hardware capabilities to allow operating systems themselves to run in a hardware environment different from their original environment. These software programs that emulate the underlying hardware capabilities are called virtual machines (VM) or virtual machine monitors (VMM). A VM abstracts the capabilities of hardware and makes it available in environments different from the original hardware. Some of the well-known virtual machines are VMware, which emulates a standard Intel x86 PC architecture on a Macintosh environment, and Java Virtual Machine (JVM), which emulates a specialized byte-code for a pseudo-processor. Hardware virtualization can also be extended to allow multiple heterogeneous operating systems to execute on a single physical machine. The ample computing resources of modern multicore processors make this extension possible. However, these multiple instances of heterogeneous operating systems need to execute in a resource-isolated environment, with no functional impact to other instances of operating systems. This is essential since they will be sharing computing resources.

Hardware Virtualization for an OS

Enabling multiple instances of heterogeneous operating systems on a single machine involves solving technical challenges in virtualization and resource isolation, while retaining complete binary compatibility and an acceptable level of performance. Virtualizing multiple instances of an operating system can be done using either full or partial virtualization. In either case, the virtual machine virtualizes the hardware to provide the illusion of real hardware

Software&DevelopmentTools for the operating systems executing on this virtual machine. However, both full and partial virtualizations have some key differences in their overall architecture, leading to a different set of trade-offs. Full virtualization of the underlying hardware requires virtualizing all the capabilities of the processor and board. This involves complex manipulations of memory management and privilege levels that are compute-intensive on commodity processors. This leads to performance overheads that are much higher than the non-virtualized versions of the OS. However, the biggest benefit of full virtualization is to allow operating systems to run unmodified, although at the cost of a significant performance overhead. In partial, or para-virtualization, the underlying hardware is not completely simulated in software. This architecture allows commodity operating systems to be easily virtualized on commodity processors, although the virtualized operating system requires code modifications to adhere to the partially virtualized architecture. However, the performance of partially virtualized architectures is much better than the fully virtualized machines, usually falling within a few percent of the non-virtualized versions. The other key requirement for running multiple operating systems in the context of a virtual machine is the ability to isolate the physical resources of a computer. This is achieved by time-space

partitioning, a concept used extensively in safety-critical and secure systems. In a time-space partitioned system, the virtual machine sub-divides two key computing resources: CPU time and physical memory. The physical memory is divided into unique, non-overlapping ranges, and assigned to individual heterogeneous virtualized operating systems. The time scheduler allocates periods of CPU time to each virtualized OS, which is usually fixed and cyclic. This gives the illusion of exclusive access to computing resources for the virtualized operating systems. The ability of the virtual machine to support time-space partitioning is a basic prerequisite for the execution of multiple virtualized operating systems on a single machine. Both full and partial virtualization support 100% binary compatibility with the stand-alone version of the operating system. They also retain the benefits of multiple address spaces within a single operating system instance. One significant difference between a stand-alone operating system and a virtualized version is that the virtualized OS runs in a less privileged mode (user mode). This is necessary since the virtual machine that provides the virtualized architecture is the sole entity that is running at the highest privileged level (supervisor mode). Figure 1 shows the generic architecture supporting multiple heterogeneous operating systems running on a virtual machine.

Partition 1

Partition 2

Partition 3

Multiple address spaces

Multiple address spaces

Multiple address spaces

Process A

Process 1 GUI

Process B

Process 2

Linux (MP aware)

RTOS (MP aware)

Windows (MP aware)

Separation Kernel (VMM)

Hardware (Multicore CPU) Figure 1


Virtualized OS architecture on a Multicore processor.

January 2007


100% binary compatible


100% binary compatible


100% binary compatible

User Mode Supervisor Mode

Software&DevelopmentTools One of the key benefits of creating a virtualized OS architecture is the addition of security capabilities into embedded design. The time-space partitioning capabilities provided in this architecture form a natural foundation for creating secure applications in embedded design. The MILS architecture based on time-space partitioning design is an approach that naturally evolves from the time-space partitioning paradigm.


The Multiple Independent Levels of Security/Safety (MILS) architecture adopts the best principles of security and safety-critical design to define a hard real-time, secure embedded OS that can be evaluated to the highest levels of security—Evaluation Assurance Layer (EAL) 7 and safety assurance (DO-178B)—while preserving the flexibility to support diverse security policies. The architecture identifies four key security policies: Information Flow, Data Isolation, Residual Information Protection and Damage Limitation. • Information Flow policy states that only authorized subjects can exchange information using pre-configured communication channels. • Data Isolation policy states that objects can be isolated into separate partitions, such that subjects can only gain access to objects they are authorized to access. • Residual Information Protection policy states that covert channels cannot exist through unintended transfer of residual state information. • Damage limitation policy states that fault isolation is present and faults in one partition do not propagate to other partitions

The MILS architecture uses a small partitioning kernel (RTOS) that runs in supervisor mode and provides brick-wall partitioning of memory, time and I/O resources. The partitioning kernel only provides the basic functionality needed to support the underlying hardware. Within each partition, the traditional OS functionality executes in user mode completely isolated from other partitions. The middleware and applications make up the rest of the components that may execute in a single partition. The MILS architecture is an example of component layering (kernel, middleware and application), and provides a platform for virtualization of commodity operating systems. This architecture provides flexible security capabilities and can be the basis of several secure embedded designs atop multicore processors.

Example Architecture

An example architecture that exemplifies the principles of virtualization, real-time and security on multicore processors is the LynxSecure architecture from LynuxWorks, Inc. Such an RTOS combines time-space partitioning and virtualization to allow multiple, heterogeneous operating systems to execute in a robust, highly secure environment on 64-bit, multicore processors. It allows safety-critical and secure operating systems to function alongside non-secure operating systems without compromising the entire system’s security, reliability and data integrity. This separation kernel is also a virtual machine monitor that will be submitted for certification to (a) Common Criteria EAL7 Security certification (Evaluated Assurance Level 7), which is a level of certification unattained by any known operating system to date; and (b) DO-178B Level A, the highest level of FAA certifiPartition 2

Partition 1

Partition 0 Posix App

Linux App

Win App




Open Standards API





Linux App GLIBC

Windows API

Partition N A P P


Open Standards API


Linux Virtual CSP/BS/Drivers


Windows Virtual CSP/BSP/Drivers


LynxOS-SE Virtual CSP/BS/Drivers

Security Monitor (EAL7) Open Standards API High Assurance Run-time (EAL 7)

User Mode Supervisor Mode

LynxSecure Separation Kernel (EAL7)

Hardware (64-bit, Multicore processor)

Figure 2

Example architecture on a Multicore processor.

January 2007


High-Performance 3U CompactPCI Intel® Pentium® M / Intel® Celeron® M Processor SBC with Dual GbE on PCI Express

ETXexpress Module with Intel® Pentium® M and Mobile Intel® 915GM Express Chipset As the first member of the ADLINK ETXexpress family, the ETXexpress-IA533 uses low power Intelfi Pentiumfi M processor 760 at 2.0GHz and the Mobile Intel fi 915GM Express Chipset. Both the processor and chipset are part of the embedded Intelfi Architecture that ensures a long production life for applications that need extended availability. The ETXexpress-IA533 supports dual channel DDR2 533MHz memory and comes with a single on-board Gigabit Ethernet port. In addition to the on-board integrated graphics, a Graphic PCI Express x16 slot is also available. The board connects up to four additional PCI Express x1 devices. The module has legacy support for 32-bit PCI and ISA through LPC.

The cPCI-3915 CPU board is a 3U 4HP or 8HP system slot single-board computer with up to 2.0GHz for the Intelfi Pentiumfi M CPU. This SBC is based on the Intelfi 915GM chipset with 400 or 533 MHz FSB. One SO-DIMM socket carries up to 1GB 400/533 MHz non-ECC DDR2 RAM. The cPCI-3915 offers two Gigabit Ethernet ports, two RS-232 ports, one IDE ATA 100/66/33 port, one CompactFlash socket, two SATA-150 interfaces, quad USB 2.0, and a VGA/DVI interface. The Ethernet ports support PXE remote boot. For more info, go to:

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For more info, go to:

Two AdvancedTCA Processor Blades with Dual Intelfi Xeon 800FSB

Full-size Intel® Pentium® 4 (LGA775) Processor SBC The new NuPRO-851DV has a high-computing capability. It supports an 800MHz FSB and Intelfi Pentiumfi 4 (LGA775) processor with Hyper-Threading technology. It has a large communication bandwidth with two PCI Express x1 Gigabit Ethernet ports. It supports Serial ATA for high-speed storage, USB 2.0 and other generic features including VGA, COM, keyboard, mouse and hardware monitoring. For more info, go to:

� PICMG 3.4 ATCA Advanced Switching Option3 � Quad ASI x4 Fabric Interface Channels up to 5-Slot Full-Mesh Configuration, 32Gbps � Dual Intelfi 64-bit LV-Xeon 2.8GHz, 1MB L2 Cache, Hyper-Threading Processors � Dual DDR2-400 REG/ECC Channels with 16GB max.

AdvancedTCA Base/Fabric Switch Blade with 10GbE Uplink Port � 24-Port 10/100/1000BASE-T Base Interface: 12 Node-Slot, 8 Egress, 2 ShMC Ports, 1 Inter-Switch and 1 Control Plane Port � 24-Port 1000BASE-BX Fabric Interface: 14 Node-Slot, PICMG 3.0 Option1 Ports, 2 Egress and 8 RTM Ports � Layer 2/3 Packet Switching and Routing � Vitessefi VSC7310 GbE Switch-on-a-chip 5U Five-Slot AdvancedTCA Rackmount System

A Compact Multi-Application Computer with New CPU Options, and the Latest Chipset The GEME-4000 offers multiple CPU choices and USB 2.0 connectors, LVDS support for display and DDR RAM in addition to the standard GEME features. The GEME-4000 comes with an Intelfi Ultra Low Voltage Celeronfi M 600MHz processor. They can be controlled from remote locations and run continuously in many critical applications such as machine tools and digital video capture. It also comes equipped with anti-vibration features. For more info, go to:

� 19" Rackmount, 15.3" Depth � Five-Slot Full Mesh Topology Fabric Interface � Five-Slot Standard Rear Transition Module � Dual Bussed IPMB

Call us toll-free at (866) 4-ADLINK or email

Software&DevelopmentTools cation for mission-critical avionics applications. It is designed to provide a virtualized hardware interface to allow multiple guest operating systems to run in a context of a single physical machine. To achieve this, the separation kernel creates a virtualization layer that maps physical system resources to each guest operating system, thereby virtualizing operating systems like Linux, Windows and LynxOS-SE to run within ultra-secure partitions. This virtualization technique provides superior performance for virtualized operating systems and their applications, while preserving 100% application binary compatibility with the non-virtualized instance. In addition, it guarantees resource availability, such as memory- and processor-execution resources, to each partition, so that no software can fully exhaust or consume the scheduled memory or time resources of other partitions. There is support for simultaneous use of system interfaces, including multiple instances of the same or different operating systems in different partitions. A fixed-cyclic ARINC653-based scheduler to ensure that all partitions are allocated adequate CPU time to prevent starvation for any partition, as well as a dynamic scheduling policy to allow maximum flexibility, are additional capabilities of this architecture. This example separation kernel provides the essential components for a complete implementation of a scalable, multithreaded and secure architecture through support for Symmetric multiprocessing (SMP) for optimal resource utilization and load balancing on multicore processors. It also provides additional high-end scalability and memory support through 64-bit execution mode and addressing capabilities. As the complexity of embedded applications continues to grow, the need for greater computing power continues to drive advances redrock_03.indd in processor architecture. The emergence of multicore processors marks a strategic inflection point in the embedded industry. The confluence of innovation in operating system design in the areas of virtualization, real-time and security on these newer processors is enabling new paradigms in embedded application design, the effects of which will propel further advances in application design in the embedded marketplace. The design of embedded applications is becoming a complex endeavor. The need for advanced operating systems and tools to enable application designers to take advantage of these hardware innovations has never been greater. The technology issues outlined in this article should help embedded designers make appropriate choices for their embedded software needs, as the embedded industry moves into the 21st century.

Mass Storage Modules for VMEbus and CompactPCI速

Ultra SCSI Flash Drive

Up to 128GB in VMEbus Form Factor -40C to +85C Operating See the full line of VMEbus single and multi-slot mass storage module products at

or call Toll-Free: 800-808-7837 Red Rock Technologies, Inc. 480-483-3777


10/13/06 3:28:23 PM

LynuxWorks, San Jose, CA. (408) 979-3900. [].

January 2007


Products&Technology High Channel Density, Compact Plug and Play Data Acquisition Solution

A fully integrated acoustic data acquisition/conversion system is available in a rackmount 1U form-factor. DaqNet from Radstone Embedded Computing is characterized by its high channel density analog (192 channels) and digital (240 channels) I/O. The compact size and competitive pricing of daqNet makes it appropriate for a broad range of sonar applications in surface ships and submarines, in vibration analysis and in test and measurement. An autonomous high-speed acoustic server designed for today’s network-centric environment, daqNet provides data connections and control capabilities via dual Gigabit Ethernet interfaces. The server is configurable via the redundant dual Gigabit Ethernet connections using the SNMP protocol. With its plug and play capabilities, daqNet can be connected to the network, configured with the sample application provided and the connection tested through hardware-implemented AD/DA test channels. DaqNet is customizable using any combination of up to four I/O modules—analog input, analog output or digital I/O: each digital I/O module provides several options for triggering control including the ability to precisely synchronize digital and analog outputs for use in sonar transmit systems. An unlimited number of daqNet servers and channels can be synchronized in real-time using Radstone Sensor Processing’s advanced time stamping technology. Each daqNet supports master/slave configuration for redundancy in the event of a failure.

Mid-Size AMC Card Enhances AdvancedTCA and MicroTCA systems

The reliability, flexibility and usability of ATCA, AdvancedMC and MicroTCA are key factors in their acceptance. The KosaiPM, a mid-size Advanced Mezzanine Card from Emerson Network Power, seeks to increase acceptance by adding reliability, high-performance control and packet processing capability to MicroTCA systems, AdvancedTCA blades, and custom carrier blades equipped with AdvancedMC sites. The KosaiPM is optimized for optical and wireless infrastructure systems, voice gateways and SS7/SIGTRAN signaling systems that require high-speed control, protocol and packet processing. The low-power, hot-swappable module features a Pentium M processor operating at speeds of up to 1.8 GHz, two Mbytes of Level 2 cache, up to two Gbytes of DDR SDRAM with ECC, a USB 2.0 interface, 1 Gbyte of flash memory, and a front panel RS-232 console interface. The KosaiPM’s AdvancedMC interface combines dual Gigabit Ethernet channels with a 1 x 8 or 2 x 4 PCI Express interface. The RoHScompliant KosaiPM is supported by Carrier Grade Linux software and an I2C-based Intelligent Platform Management Interface (IPMI). The mass storage support includes an onboard storage interface, which gives the KosaiPM access to Serial-ATA (SATA) hard drives residing on either the carrier card, in other AdvancedMC bays, or MicroTCA system. Emerson Network Power, Madison, WI. (608) 831-5500 [].

Radstone, Belerica, MA. (613) 749-924. [].

ARM EPIC SBC with Power Over Ethernet Plus Multiple Communication Interfaces

PCI Card Offers Easy-to-Use Motion Control

Intended for remote terminals, protocol conversion or data logging in power-shy environments, SBC4670 from Micro/sys matches the fast yet low-power PX270 ARM processor with an abundance of onboard communication formats: Power Over Ethernet; socket modem capable of GSM/ GPRS, CDMA, or Bluetooth; onboard GPS and/or CAN bus interface. Fitting on the 4.5” x 6.5” EPIC footprint, the board’s multimedia capabilities include support for an 800 x 600 color flat panel display, audio output and debounced keypad input. Control and monitoring applications are served by 8 channels of 14-bit A/D with simultaneous reads, 8 channels of 14-bit D/A and 24 channels of digital I/O. The SBC4670’s Intel PXA270 processor running at 520 MHz is based on the ARM5 core, which implements a super-pipelined RISC architecture and adds multiple integrated peripherals. The SBC4670 features five serial ports. The 10/100BASE-T Ethernet controller can include the option of Power Over Ethernet, which supplies the board with 15watts of power through the Ethernet connector. With 128MB of SDRAM, and a 64MB resident flash array, feature-rich operating systems are an ideal match. I/O expansion through the CompactFlash socket allows users to implement additional storage and I/O devices such as Wi-Fi cards. The SBC4670 has a 16-bit PC/104 bus interface, which allows access to numerous off-the-shelf boards. The basic SBC4670 starts at $595 in single quantity. An industrial temperature (-40° to +85°C) version is also available starting at $650.

A new PCI-based motion card for multi-axis, high-performance control is available in 1, 2, 3 and 4-axis versions. The Prodigy-PCI motion control card from Performance Motion Devices provides advanced motion control features including trajectory generation, servo loop closure, quadrature signal input, motor output signal generation, performance trace, on-the-fly changes, commutation, and much more. Motor type can be software-selected on a per-axis basis and includes DC brush, brushless DC, step and microstepping. The card communicates via a PCI bus, CANbus or serial port. The card features include S-curve, trapezoidal, velocity contouring, electronic gearing and user-generated profile modes. The card accepts input parameters such as position, velocity, acceleration and jerk from the host, and generates a corresponding trajectory. Instantaneous on-the-fly changes can be sent by the user, and external signal inputs can be used to program automatic profile changes. Prodigy-PCI provides servo loop rates of up to 50 μSec/Axis, 8 Mcount/sec quadrature encoder input rate, high-speed motion trace for servo tuning diagnostics (with 40 Kbytes onboard dual-port memory), and pulse and direction output of up to 5 Mpulses/sec. Additional features include limit switch input, high-speed position capture, dual loop encoder input, 6-step and sinusoidal commutation, PID filter with feedforward and dual biquad filters, incremental and parallel encoder input, eight general-purpose digital inputs and outputs, and eight 10-bit general-purpose analog inputs. Prodigy-PCI is available now. Pricing starts at $380 in OEM quantities.

Micro/sys, Montrose, Ca. (818) 244-4600 [].

Performance Motion Devices, Lincoln, MA. (781) 674-9860 [].


January 2007

Products Get Connected with companies and products featured in this section.

A Mix of Mid-Size AdvancedMC Modules

Four new AdvancedMC modules aimed at facilitating the security, processing, I/O and storage configurations of pre-integrated open modular equipment designed for a multitude of IMS, 3G wireless and wireline network applications have been introduced by Kontron. Two of the four new AdvancedMC units—the Kontron AM4330 IPSec module and the Kontron AM4301 Quad GbE module—are based on the new Mid-Size (4HP) form-factor, recently introduced by PICMG. The AM4330 AdvancedMC IPSec module is designed to dynamically handle both IPSec and SSL VPN processing applications deployed within mobile communications infrastructure systems. The AM4330 is designed with a Hifn HIPP-II 8155 IPSec encryption controller, which performs multi-protocol packet processing for security protocols such as IPSec (ESP and AH), SSL/TLS, L2TP and PPTP. The AM4520 SAS module offers up to 73 Gbyte storage capacity. Built in accordance to the AMC.0 and AMC.3 specifications, the Kontron AM4520 features a 10K rpm spindle and the industry’s highest reliability at 1.4M hours MTBF. Easily managed via IPMI v1.5, this hot-swappable field-replaceable unit also follows the same stringent carrier grade RASM feature set. The Kontron AM4002 processor module is equipped with the latest Pentium M available at 1.4 and 1.8 GHz with a high-performance Intel E7320 chip set. It supports up to 4 Gbytes of DDR-II memory (PC400) as well as AMC.1 (PCIe), AMC.2 (Gigabit Ethernet), AMC.3 (Serial ATA) and ComPort connections. Supporting the PICMG subspecifications AMC.1/.2/.3, the AM4002 ensures a comprehensive set of interconnecting capabilities to the Kontron AMC Carrier. A x4 PCI Express lane according to AMC.1 guarantees high throughput for I/Ointensive applications. The AM4301 Quad GbE module is designed for network applications that require multiple ports directly from an AdvancedTCA processor blade. Based on the Intel 82571EB Gigabit Controller, the AM4301 features 4 x 10Base-T/100Base-Tx/1000Base-T ports and supports PCIE x8, x4 and x1 links and remote management via IPMI v1.5, as a hotswappable, field-replaceable unit (FRU). Kontron America, Poway, CA. (858) 677-0877 [].

Lightpipes Come in Multiple Widths, Colors

A line of lightpipes is now available from Elma Electronic in a wide range of colors and widths. The LEDs transfer light to the front panel with a translucent, yet intense coloration of the lightpipe. The variable lightguides are available in either protruding styles or versions that are mounted flush with the front panel. The lightpipes are visible and can emit light even when embedded deep within a panel. They also have a chambered light coupling area, allowing other LEDs to emit light perpendicular to the circuit board. ESD resistance reaches 10 kV at a length of 4.5 mm and increases by approximately 1 kV per additional mm of length. Elma’s lightpipes come in 1-10 width options. Combinations of single, dual, vertical and horizontal configurations are available. Pricing is $0.20/ea. in production quantity volumes, depending on configuration. Elma Electronic, Fremont, CA. (510) 656-3400. [].

VXS-Enabled Intelligent I/O Carrier Supports 10 GbE Applications

An intelligent VXS (VITA-41) I/O controller with dual PMC/XMC sites is optimized for moving data, making it suited for performance Get Connected with companies and products featured in this embedded applications high data throughput is essential. The Phoenix M6000 from VMetro is targeted at applications including military and aerospace intelligence, surveillance and reconnaissance like ELINT, COMINT, SIGINT, SAR (radar), MTI and SDR, as well as numerous recording applications. With support for 133 MHz PCI-X and x8 PCI Express, the M6000 can move data at over 800 Mbytes/s from the PMC sites to memory, making it one of the highest performance I/O carrier boards on the market. XMC module support for the Phoenix M6000 already includes the VMetro SFM, a quad SerialFPDP XMC, and the AdvancedIO Systems V1020, a 10 Gigabit Ethernet (10GbE) XMC with intelligent protocol acceleration and an FPGA for realtime packet processing. AdvancedIO and VMetro worked together to integrate the V1020 onto the M6000 to enable 10 GbE in embedded applications in a simple and straightforward manner. The architecture of the Phoenix M6000 enables support for emerging 10 GbE applications at full speed, and having the V1020 integrated with the M6000 makes it easy for customers to incorporate the combined solution into their systems. Software support for the M6000 includes a VxWorks 6.2 BSP and a Linux 2.6 distribution. FPGA firmware development support for the Phoenix M6000 is provided by TransComm, VMetro’s FPGA communications toolbox aimed at real-time FPGA-centric data communications. VMetro, Houston, TX. (281) 584-0728. []

AMD Geode-Based SBC Is Fanless

A new low-power, fanless industrial SBC from Adlink Technology is based on the AMD Geode GX 533 processor. The NuPRO-796 half-size SBC boasts CPU power consumption of only 1.1W to deliver low power, low cost and high computing performance. The NuPRO-796 comes with the Geode CS5535 Companion Device chipset, 128 Mbytes of onboard DDR266 memory in a single SODIMM socket, one UltraATA 66 IDE connector and four SATA connectors with RAID support. Also included are an ACPI-compliant 10/100BASET LAN port, four USB 1.1 ports, integrated audio controllers with an AC’97 interface, two RS-232 COM ports with ESD protection and a watchdog timer. Onboard CompactFlash support is provided, along with an ATX power connector for backplane-less applications. Options include four SATA-150 channels. The board supports VGA/CRT monitors (1600x1200, 16 bpp @ 85 Hz or 1280x1024, 24 bpp @ 85 Hz), TFT LCDs (1280x1024, 24 bpp) and LVDS. The NuPRO-796 is compatible with Adlink’s compact, wallmount RK-604A chassis and the six-slot RK-606FC chassis. Pricing starts at $390. Volume discounts are available. Adlink Technology, Irvine, CA. (949) 727-2077. []. January 2007



A/D Recording System Speeds Data Acquisition

Commercial, aerospace, defense and intelligence industries all seek affordable, high-speed, continuous waveform recorders to create a realtime recording system from non-real-time components. A new series of waveform capture systems from Signatec transforms near-real-time PC environments into real-time data recording systems and can continuously record up to 700 Msamples/s direct to disk storage without any data loss. The DR-Series’ advanced recording features are built into the system to allow various segmented or pulse-based acquisitions, as well as channel interleaving to maximize the continuous 700 Mbytes/s of recording bandwidth. Options include a choice of 700 Mbyte/s, 350 Mbyte/s or 250 Mbyte/s configurations, up to eight channels, streaming the digitized data at up to 1 Gbyte/s to the company’s real-time parallel processing solutions and arbitrary waveform playback capabilities. For signal playback features, Signatec’s signal waveform generator component features can be added to deliver 16-bit, 1 GHz analog solutions. Eight-bit options have peak sample rates of 1 GHz per channel and 14-bit options can sample at up to 100 MHz per channel. Prices start at $20,000.

FC Interface Delivers 4 Gbit/s, ATCA AMC.1 Hot-Swap

Next-generation computer systems in telecom, military and enterprise computing applications need high levels of online maintainability. A new Fibre Channel interface from Critical I/O delivers 4 Gbit/s connectivity to ATCA systems and provides hot-swap capability via its compliance with the ATCA Advanced Mezzanine Card standard (AMC.1 with PCI Express host interface). The Model FCA2460 AMC Host Bus Adapter module has two independent 4 Gbit/s FC interfaces that, when combined, achieve sustained data rates of 1.5 Gbytes/s, 10 microsecond RDMA data transfers and up to 300,000 SCSI I/O operations per second. The AMC also provides a four-lane PCI Express host interface, full hotswap capabilities and extensive integrated hardware BIT. The Model FCA2460 is compatible with X86 and PowerPC ATCA processor blades and is software compatible with the company’s PMC and XMC Fibre Channel interfaces. It is supported by a full complement of library and drivers for VxWorks, Linux and Windows. Pricing is $1,995 in production quantities. Critical I/O, Irvine, CA. (949) 553-2200. [].

Signatec, Newport Beach, CA. (949) 729-1084. [].

Enhanced Platform for Software Defined Radio Server-Class Dual-Core Xeon 6U cPCI Blade Is Rugged, Manageable

The platform for Software Defined Radio (SDR) from Green Hills Software has been significantly enhanced through a broad range of technology integrations and partnerships, resulting in substantial new customer adoption, according to the company. The Green Hills Platform for SDR continues to deliver support for a broad range of SDR designs that require options for platform scalability, waveform development and debug, and integrated reference and deployment platforms. The Green Hills Platform for Software Defined Radio includes the Integrity royalty-free RTOS, certified by the IEEE to the latest POSIX 1003.1 standard; the new GHNet v2 dual-mode IPv4/ v6 networking stack; industry leading CORBA integrations; numerous SCA core frameworks; advanced waveform development tools; and a wide range of integrated reference platforms to help move from concept to deployment as fast as possible. The Green Hills SDR Platform has been enhanced to offer reference Platforms from Spectrum Signal Processing (complete JTRS radio platforms) and Lyrtech’s Small Form Factor SDR Development Platform for SCA and non-SCA radios. In addition, there is the SCA Technica High Assurance Wireless Computing System (HAWCS). SCA operating environment and development tools include the Communications Research Centre Canada (CRC) - SCARI Software Suite, development tools and OE, the Spectra Tools and OE from PrismTech, Zeligsoft’s waveform development tools and Objective Interface Systems’ ORBex-

The expansion of multiprocessing systems and Intel computing platforms to CompactPCI architectures is benefiting a new generation of embedded applications in which scalability, extensibility and reliability are as critical as performance, size, weight and power. One example of this trend is the 6U CompactPCI cPENTXM2 from Thales Computers, a rugged, server-class blade that uses the 1.67 GHz Dual-Core Xeon, Intel’s most advanced low-power IA-32 technology, combined with the Intel E7520 server class memory controller hub (MCH). The cPENTXM2 is completely scalable and boasts up to 4 Gbytes of DDR2-400 SDRAM with dual Gigabit Ethernet ports on the backplane. It is compliant with switched backplane recommendation PICMG 2.16/VITA31 and supports PICMG 2.9/VITA 38 standard intelligent platform management interface (IPMI). It provides two additional Gigabit Ethernet ports and two USB 2.0 ports on the front panel. A SATA port, two USB 2.0 ports and a PCI Express port are available on the back panel connector as PICMG 2.16 dual Gigabit Ethernet interfaces. The cPENTXM2 runs Red Hat Linux. It is available as a stand-alone board or pre-integrated into large systems with full data transport and management software based on standards such as MPI and HTTP. Pricing for the cPENTXM2 starts at $3,950.

press Real-Time CORBA, among others.

Thales Computers, Raleigh, NC. (919) 231-8000. [].

Green Hills Software, Santa Barbara, CA. (805) 965-6044. [].


January 2007

Acromag introduces affordable FPGA I/O. For ALL your projects.


s an engineer, your projects are unique, ever-changing, and budget-bound.That's why our new PMC modules give you an affordable solution to create custom I/O boards. But if you thought FPGA computing was only for top-end applications, think again. Our PMCs are ideal for protocol conversion, simulation, in-circuit testing, and much more. So why settle for generic I/O when you can design exactly what you need while staying in budget and reducing your time to market? • Virtex®-II FPGA with 500K, 2M or 3M system gates • 1Mb on-chip RAM, 9Mb on-board SRAM • Fast PCI with 32-bit, 66MHz dual DMA

Cost-effective custom I/O Choose from a variety of I/O configurations: • Digital I/O:TTL, RS422, or LVDS I/O • Analog I/O:four 20 or 65MHz A/D and two D/A Faster time to market Why waste precious time building a board from scratch? Our new FPGA modules let you process your I/O signals any way you want. Quickly. Flexibility to meet unexpected challenges Acromag FPGA I/O will help you bring your projects in on time and under budget. And with FPGAs, you'll be ready to adapt to all the inevitable changes. Thinking about FPGA I/O? Think flexible. Think affordable. Think Acromag.

Industry Pack FPGA I/O also available



Manufactured in Wixom, Michigan, USA



Call or visit our website today – for VME, CompactPCI, PCI, PMC, and Industry Pack solutions. 800-881-0268 or 248-624-1541



All trademarks are the property of their respective companies

• Quality and reliability by design • Long term supply •

PERFORMANCE IN THE EXTREME Intel® Pentium® M Processor embedded SBCs for demanding environments

-30°C Power On

MAT 1100 • • • • • • •

Intel® Pentium® M Processor 1.4, 1.8, 2.1G 5V only PICMG 1.0 -30°C option Ideal upgrade for Pentium® III and Pentium® 4 designs Far lower power than the Pentium® 4 Intel® Extreme 2 Graphics Optional High Performance Graphics using ATI 9000, dual screen, DVI/DFP, LVDS • 2 Serial, 4 USB, dual Gigabit Ethernet, Sound, CompactFlash

page 62

[ 62 ] versalogic G4F01554 12 to 36 watts -

for fanless sealed system design

MAT 1111 • Intel® Pentium® M Processor 1.4G (738), 1.8G or 2.1G • Intel® Celeron® M Processor 600Mhz • Low power 12 watts to 36 watts depending on CPU and loading • EBX size, Mini PCI, PC/104-Plus, CompactFlash • Heat spreader plate to support sealed system design • Fanless option • Extended temperature -30°C power on option • Intel® Extreme 2 Graphics, LVDS, CRT • High Performance Graphics using ATI, dual screen, DVI/DFP • Two independent video input channels; mux up to 4 inputs • 5V only

Two Philips 7130 for PAL/NTSC input For full specifications go to our website

Contact us Europe & rest of world: Microbus plc Tel: +44 (0) 1628 537333 Fax: +44 (0) 1628 537334 email:

USA & Canada: Microbus Inc Tel: +1 (800) 688-4405 or (281) 568-4744 Fax: +1 (281) 568-4604 email:

Designed and manufactured in the UK

<> Microbus Better by design

FPGA-Based DSP VME Engine Is ConductionCooled

Demanding signal processing applications require survivability in harsh environments throughout the full range of military application environments. To meet that need, Curtiss-Wright has introduced conduction-cooled rugged versions of its CHAMP FX DSP 6U VME64x and VITA-41 engines. The company has also qualified the high-performance IP blocks included in its CHAMPtools-FX Design Kit, including I/O logic blocks for SRAM and SDRAM memory controllers, the PCI interface and serial controllers, for use over the entire Level 200 (-40° to 85°C) temperature range. The CHAMP-FX is designed for DSP applications such as radar, sonar and signal intelligence. FPGA computing power is complemented with I/O speeds of more than 10 Gbytes/s implemented with high-speed differential serial RocketIO, XMC/ PMC sites and StarFabric interfaces. The FPGAs have more than 8 Gbytes/s of memory bandwidth from the board’s DDR SDRAM and fast DDR-2 SRAM. The conduction-cooled rugged versions meet Curtiss-Wright’s Level 100 (-40° to 71°C) and Level 200 ruggedization guidelines, which fully address use in high shock and vibration environments. These versions are constructed with a hybrid aluminum/copper frame that provides mechanical stiffening while conducting heat from the electronic components to the edge of the card, where it is transferred to the chassis. Prices start at $36,000. Volume discounts are available. Curtiss-Wright Controls Embedded Computing, Leesburg, VA. (703) 779-7800. [].

SOM ETX Module with AMD Geode LX800 Processor

A system-on-module based on the ETX form-factor (SOM-ETX) offers a very short time-to-market solution for OEM customers. The MB-07302 from WIN Enterprises consists of an AMD Geode LX800 processor and AMD Geode CS5536 companion chip in the ETX formfactor (95 mm x 144 mm). The module supports onboard one 200-pin DDR-based SO DIMM up to 1 Gbyte memory and incorporates a VGA controller, an EIDE controller supporting four USB 2.0 ports, two serial ports, one parallel port (SPP/ECP/EPP) shared with FDD and one PS2 keyboard/mouse interface. The product features a Realtek 8139CL+-based 10/100 Mbits/s Ethernet port, watchdog timer, an AC97 audio codec and support for CRT and 24-bit LVDS-based displays. The CM-6120 fully supports ISA interface and embedded features such as RS-232 console redirection for BIOS settings. AEWIN provides R&D support and product review for companies that are doing their own carrier board design, and offers full development and production services for those who wish to outsource their carrier boards. An evaluation base board companion product (IP-09026) enables fast product development. The SOM-ETX module attaches to a larger standardized carrier board. WIN Enterprises also announces the IP09026, a 5.25” disk-size ETX evaluation carrier board that accompanies the MB-07302 to enable rapid testing and prototyping. The single unit pricing is $269 for the MB-07302. Single unit pricing for the IP-09026 evaluation carrier board is $130 with quantity discounts available for both. WIN Enterprises, North Andover, MA. (978) 688-2000 [].

3U cPCI Express CPU Board Delivers HighSpeed I/O

Today’s powerful, resource-consuming applications such as robotics and military/avionics need the support of robust, high-speed interfaces between devices. A new 3U CompactPCI Express CPU board delivers this high-speed connectivity to I/O by installing in a cPCIe Type 1 system slot. The MAXExpress cPCI Express CPU board connects to a cPCIe backplane via four PCIe x1 lanes at 5 Gbits/s per lane. The MAXExpress cPCIe Pentium M CPU board features a 1.4 or 2 GHz Pentium M CPU, the Intel 915 chipset, a 2 Mbyte L2 cache and up to 2 Gbytes of soldered DRAM. Front-panel I/O includes a Gigabit Ethernet port, three USB 2.0 ports and a VGA port. A dual-slot option supports a second GbE port, three more USB ports, a PS2 keyboard/ mouse port and a COM port. Other options include installing a rear I/O module that provides a single rear access to all external cables, either a standard 1.8-in. parallel ATA hard drive or conventional CompactFlash and active or passive cooling. The MAXExpress cPCIe Pentium M CPU board supports Windows 2000 and XP, Linux, VxWorks and QNX. It is priced at $3,995 in OEM quantities.

SBC Features LGA775 Socket, 865GV Express Chipset

One Stop Systems, Escondido, CA. (760) 745-9883. [].

American Portwell Technologies, Fremont, CA. (510) 403-3399. [].

A new PICMG 1.0 SBC from American Portwell Technologies, the ROBO-8713BVG2, is based on the Intel Core 2 Duo processor, running at up to 1.066 GHz. It also supports Pentium D, Pentium 4, or Celeron D processors via an LGA775 socket equipped with dual-core, hyper-threading, EM64T, EIST, XD and VT technologies. The board includes the price-competitive Intel 865GV Express chipset and 2 Gbytes of DDR 400/333/266 SDRAM in dual, 184-pin DIMM sockets. I/O includes dual Gigabit Ethernet ports, dual SATA connectors, dual IDE channels, one FDD channel, eight USB 2.0 ports, dual serial ports, a parallel port, GPIO and watchdog timer. The VGA interface utilizes the Integrated Intel Extreme Graphics 2 graphics engine with Intel’s Dynamic Video Memory Technology 2.0, with shared system memory of up to 64 Mbytes. List price is $495.

January 2007



Serial Attached SCSI Explodes into the Embedded Arena Now that there are fully integrated SAS products in the marketplace and costs are decreasing, SAS is rapidly growing in the embedded marketplace. The time has come for the embedded market to fully embrace the serialization of storage interface technologies.


by Matthew Knowles, PhD,

tached SCSI (SAS) technology at the enterprise level and the recent availability of SAS at the mid and entry level is providing unprecedented performance and flexibility to infrastructure and storage solutions. As SAS is now ramping in the IT markets, the stability of the technology is maturing and the price point for SAS implementations is going down as it is driven by the large volume IT markets. mpanies providingIntel solutions andnow other member companies of the SCSI Trade Asploration into products, technologies companies. Whether goal is toblocks researchto theprovide latest sociation (STA)and now have the SASyour building all pplication Engineer, or jump to a company's technical page, the goal of Get Connected is to put you the of high-speed rvice you require for benefits whatever type of technology, serial communications to both IT and embedded markets. anies and products you are searching for. The speed and scalability of SAS brings realtime performance to large storage arrays or inter-box communications. This presents a new opportunity to enhance next-generation embedded system design with SAS technology to create scalable designs with improved performance and flexibility.

Why SAS?

Over the past 20 years, disk interface technology has followed two parallel paths in the IT desktop segment and the enterprise market segment. Personal computer desktops, commonly sold to consumers and businesses, have used parallel ATA (PATA) controllers and disk drives as the mass storage device of choice. The term PATA is inclusive of IDE and Ultra IDE, Get Connected which arewith also used tomentioned describe these controllers and disk drives. companies in this article. In the enterprise market, parallel SCSI has dominated for highperformance, high-reliability disk drives for everything from

End of Article

Get Connected with companies mentioned in this article.



January 2007

Parallel SCSI Bandwidth Evolution 350

Megabytes per second

er exploration Intel ther your goal speak directly cal page, the The need for reliable, scalable, high-performance digital ght resource. storage is rapidly expanding in both the worlds of IT computtechnology, ing and embedded systems. In IT, the availability of Serial Ats and products

300 250 200 150 100 50 0


Figure 1


Ultra SCSI

Ultra2 SCSI

Wide Ultra2

Ultra 160

Ultra 320

Parallel SCSI Bandwidth Evolution.

small servers to mainframes and storage arrays. As the needs for higher-performance I/O increased over the past 20 years, parallel SCSI has maintained and executed to an aggressive roadmap of increased throughput graphically shown in Figure 1. Parallel SCSI has evolved from a 5 Mbyte/s standard to 320 Mbytes/s with Ultra320 SCSI. In the desktop arena, PATA has maintained a similar roadmap of performance (topping out at 133 Mbytes/s) while maintaining cost structures for the consumer and business PC market. Although both technologies were successful for their respective market segments (PATA achieving 133 Mbytes/s and SCSI hitting 320 Mbytes/s), both reached fundamental technical and logistical challenges due to the parallel nature of the interfaces. Parallel communications require a large number of conductors (40/80-pin for PATA, 68-pin for SCSI), which makes for bulky cabling and increased signal cross-talk with increasing frequencies. Both have jumper/termination requirements and support a limited number of devices (2 for PATA and 15 for SCSI). Neither can support hot-swap of hard drives required for serviceability of storage designs.


Enter a World of Embedded Computing Solutions Attend open-door technical seminars and workshops especially designed for those developing computer systems and time-critical applications. Get ahead with sessions on Multi-Core, Embedded Linux, VME, PCI Express, ATCA, FPGA, Java, RTOS, SwitchFabric Interconnects, Windows, Wireless Connectivity, and much more.

Meet the Experts Exhibits arranged in a unique setting to talk face-to-face with technical experts. Table-top exhibits make it easy to compare technologies, ask probing questions and discover insights that will make a big difference in your embedded computing world. Join us for this complimentary event! Be sure to enter the drawing on-site for an iPod Video

Coming to Your Doorstep in ‘07... January




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Tier 1

Tier 2

Tier 3



SAS JBOD Internet or WAN NAS




Integrated SAS scales across DSS Tiered Storage Topology

Figure 2

Where SAS fits into DSS Tiered Storage Topology.

The introduction of serial communications to disk I/O has overcome many of the previous limitations of both PATA and parallel SCSI. The fundamental serial signaling topology allows for higher performance and higher scalability that can support up to 3 Gbits/s today and will scale to 6 Gbits/s in the second generation. Cabling is reduced to seven conductors per link. Hotswap device functionality is supported. Point-to-point communications increases the number of devices supported to thousands. The introduction of expanders (simple switching devices) facilitates the development of complex topologies with a reduced number of controller (initiator) points and/or more complex bridging/ switching devices. Embedded system designers have used mainstream compute technologies and standards from the desktop space to their best abilities to keep increasing performance and reducing costs. Historically, IT/compute standards migrate into the general embedded space after some â&#x20AC;&#x153;maturationâ&#x20AC;? of the technology by the mainstream IT market. The example of PC internal bus standards provides some useful perspective. The ISA (Industry Standard Architecture) bus gave PCs an increase in performance in the 1980s but was not fully adopted by the general embedded market until standards such as PC/104, a stackable I/O specification, allowed small form-factor embedded designs to take advantage of this 16-bit interface. Although PCI was initially proposed by Intel on PC platforms in the early 1990s and widely adopted by PCs with the introduction of Windows 95 in 1995, the general embedded market did not embrace this technology until both the technology was widely hardened in the consumer and IT space and until real embedded standard form factors and implementations were established, namely the evolution of PC/104 to PC/104-Plus. Continuing this analogy into the serialization of the bus design, PCI Express (the serial evolution of PCI and PCI-X) launched on server platforms in 2004 but has only recently seen success in high-end embedded applications where I/O bandwidth is required. In the storage world, SAS-enabled servers with ROMB (RAID On Motherboard) and RAID host bus adapters entered the server market in 2004. These solutions were comprised of a discrete SAS controller and an I/O Processor (IOP) running an embedded RAID software stack. Recently, Intel and others have 66

January 2007

developed new highly integrated SoCs (System on Chips) for both the server and the general embedded market, which integrate the SAS protocol controller with a high-performance I/O Processor. The Intel IOP34x Storage Processor family (IOP341, IOP342, IOP348 and IOC340) is one example that utilizes two new highperformance Intel XScale processing cores for SAS protocol capability and application computing. This milestone signifies the maturation of SAS technology and will enable more integrated, high-performance SAS designs to enter new markets. With the advent of SAS and IOPs with integrated SAS, there are new embedded storage solutions entering the market. Storage blades that require dense designs and low thermals are taking advantage of this technology. Modular storage subsystems are being integrated into small form-factor designs. By utilizing SAS, these new designs are flexibleâ&#x20AC;&#x201D;they can use both SAS and SATA devices depending on the price point and reliability requirements. They are scalable and serviceable with the use of expanders and the point-to-point architecture delivered with a serial topology. Each SAS device has its own unique ID set at the factory so identifying failed devices is much more straightforward. Embedded computing manufacturers can still take advantage of their significant investment in software for SCSI. Especially in higher-end embedded designs and communications systems where the SCSI protocol has seen most success, the basic command set of serial attached SCSI is still SCSI. Embedded systems using SAS technologies are also more future proof due to the solid roadmap for increased performance to 6 Gbits/s and beyond.

Tiered Storage in DSS

Local and global concerns about security combined with the availability of high-resolution digital imaging devices at lower costs (CMOS sensors etc.), are driving rapid demand for digital security surveillance (DSS) both in the public and private sectors. In larger installations, massive amounts of data need to be rapidly and reliably captured and stored for analysis. Depending on the type of data, the age of data and the context in which the data was collected, users of said data will have different priorities and accessibility requirements for the data. This line of thought applies not only to video security but also to other systems where massive amounts of data are generated and need to be analyzed. A few examples include industrial metrology, test and measurement and medical imaging. In order to optimize the valuable compute, network and storage resources needed to design and build such a system, a tiered-storage model is applied. Figure 2 shows a potential DSS implementation. Under Tier 1, multiple servers are shown with associated surveillance cameras attached. These are the capture servers that need fast data capture and storage running 24 hours a day, 7 days a week. This would be considered Tier 1 where highly available, highly-reliable storage is needed. SAS is most appropriate here. When SAS drives are tested and validated by manufacturers, MTBF (Mean Time Between Failure) is measured on a rigorous 24 x 7 duty cycle. SATA disk drives, on the other hand, are tested on a less aggressive duty cycle of 8 hours a day, 5 days a week. When optimizing the implementation design, although SAS drives are more costly, they are the appropriate choice for Tier 1 storage where only small amounts of data are being stored and rapidly analyzed.


If you have a thermal problem Figure 3

SAS JBOD Cabling, option 1.

Tier 2 of the design could be on the LAN, providing some intermediate level of storage capacity and performance. This area is a perfect fit for SAS due to the support for SATA as well. SAS provides a number of advantages that facilitate this flexibility. Connector/backplane compatibility and support for Serial Tunneling Protocol (STP) make designing a system for SAS and SATA drives cost-effective. After all this real-time data is collected and analyzed in Tier 1 and Tier 2, there could be a Tier 3 storage area either at a remote location through the Internet or within a WAN. At the far right of Figure 2, two distinct storage solutions are shown. At the top, a basic server is shown with a SAS JBOD (Just a Bunch Of Disks) connected via an external SAS link. Depending on the reliability requirements, either a JBOD or an RBOD (RAID Bunch of Disks) could be used. In the JBOD case there would be no local RAID striping of the disks, thus if one disk failed, the data would be lost. In the RBOD case, there would be an integrated IOP such as the Intel IOP348 I/O Processor with hardware-accelerated RAID5 and RAID6 providing data protection for one disk (RAID5) or two disk (RAID6) failures. At the bottom of Tier 3, two NAS (Networked Attached Storage) boxes are shown with SATA drives for the lowest cost-per-Gbyte hard disk storage solution. STA provides many useful materials for designing SAS systems and topologies. In Figures 3 and 4, two cabling examples are shown for SAS JBODs similar to that shown in Tier 3 of Figure 2. The cables and connectors are compact and support 4 links of SAS, or “x4,” providing 12 Gbit/s throughput to the JBOD. Another example of SAS technology entering the embedded marketplace is Digital Video Delivery/Distribution. This is especially attractive for SoC solutions that have integrated SAS in an I/O Processor. As the transportation industry searches for new revenue streams and new service differentiators, premium content delivery to individual passengers is growing in popularity. Airlines are leading the charge with many companies developing high-bandwidth, highly reliable, high-density embedded systems for local premium content distribution in commercial and private aircraft. Although a large standard server would meet the performance requirements for this application, the transportation requirements can restrict the use of complete server solutions. The requirements include small form-factor (low power, high density), reliability (RAID5/6) and serviceability (hot swap) at lower

We can create a solution! Radian understands thermal design - as well as how to optimize manufacturing processes for your particular thermal needs. Which means we can help you solve your thermal problems.

radian ISO 9001:2000 Certified

We have a range of products from mini Heatsinks to large CPU coolers, and if our standard parts don’t solve your needs our engineers will work with you to create a solution. In addition to providing tailored design assistance, Radian also offers complimentary thermal analysis and simulation services for your custom heatsink designs.

web: · tel: 001-408-988-6200 · fax: 001-408-988-0683 Radian Heatsinks is a division of Intricast Company Inc.

Figure 4

SAS JBOD Cabling, option 2 (Figures 3 and 4 courtesy of the SCSI Trade Association).

costs. Having the performance, scalability and reliability of SAS on such platforms in single-chip solutions is very attractive to this growing in-flight entertainment (IFE) market segment. Intel Santa Clara, CA. (408) 765-8080. [].

January 2007


one of the most rugged pieces of equipment in its class.

s o i s t h e ta n k .

Not all rugged boards are the same. Neither are the companies that make them. At CurtissWright, we’re fully focused on the unique and demanding requirements of the rugged defense and aerospace market. That’s why our design philosophy encompasses every critical area of rugged product design. Whether it’s unique thermal demands, extreme shock and vibration, or even the latest requirements for line-replaceable modules and two-level maintenance, our approach to ruggedization goes above and beyond.

w w w. c w c e m b e d d e d . c o m

The VPX6-185 single board computer is just one example in our broad range of ruggedized board-level and subsystems products. It’s VPX format is expressly designed to bring advanced serial fabric I/O performance to rugged defense and aerospace computing platforms.

r u g g e d i z at i o n . . .

with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.

Advertiser Index Get Connected with technology and companies providing solutions now Get Connected is a new resource for further exploration into products, technologies and companies. Whether your goal is to research the latest datasheet from a company, speak directly with an Application Engineer, or jump to a company's technical page, the goal of Get Connected is to put you in touch with the right resource. Whichever level of service you require for whatever type of technology, Get Connected will help you connect with the companies and products you are searching for.








Microbus, Inc........................................62.....................


Microsoft Windows

ADLINK Technology, Inc.........................56...............

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Advanet Technologies............................


Advantech Technologies, Inc..................


products featured in this section. Alphi Technology Corporation.................

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American Arium

Performance Technologies.....................27......................................


Phoenix International...............................4............................

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Get Connected with companies mentioned in this article.

a div. of Intricast Co., Inc.......................67.................

CompactPCI Showcase..........................10......................................................... Critical I/

Real-Time & Embedded Computing

Curtiss-Wright Controls Embedded Elma Bustronic Corp..............................33.................... Embedded Planet..................................44................ GE Fanuc Embedded Systems..................2............ General Micro Systems, Inc...................

Real-Time Innovations, Inc.....................21...................................... Red Rock Technologies, Inc...................57....................... Sensoray Thales Computers.................................11................ Tri-M Systems.......................................35.................................. VersaLogic Corporation..........................49..........................

Interactive Circuits and Systems/Radstone................................ 71................................ Kontron America....................................23..............................

White Electronic WinSystems..........................................37........................

Logic Supply,

Correction: In our November Editorial we inadvertently confused two VITA specification designations—VITA 56 and VITA 58. To set the record straight, VITA 56 is the small form factor being developed by VSO, apparently as a rugged alternative to the PICMG AMC specification. VITA 58 refers to line replaceable units (LRUs) or “cans” that contain boards and also offer cooling technology. RTC (Issn#1092-1524) magazine is published monthly at 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673. Periodical postage paid at San Clemente and at additional mailing offices. POSTMASTER: Send address changes to RTC, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.

January 2007


Publisher’s Letter 2007

The (Truly) Ubiquitous PC Heads Growth in EmbeddedComputer Market


ur research shows that the embedded computer industry has been growing at a staggering annual rate of better than 15%. Just a quick look around at everything from gas pumps to paving machines and from office copiers to X-ray machines (not to mention war machines), and it’s easy to see that pretty near everything is run by computers. In many cases some are in third, fourth, and even fifth generation. And, there’s strong evidence pointing to the fact that the personal computer (x86 architecture) in its many incarnations has largely taken over the embedded computer world. Many of the typical embedded computer form-factors such as cPCI, VME, ATCA and MicroTCA are experiencing far slower growth than that of PC-oriented hardware. These architectures are bumping along—some lucky to be flat, others up as much as 5%. And while much of this 15%+ growth has been through a variety of standard architectures from basic PC/104, PC/104+ and variants to more exotic form-factors such as CommExpress, a look at the revenue of these companies alone doesn’t explain all of the dramatic growth. Some PC/104 companies have been able to maintain something in the area of 12% growth and a few have closed in on the 15% mark, and still others are catapulting to rates approaching 20% and 25%. But the overall average is under 15% growth. What makes up the difference? It would appear that the lonely motherboard-based PC is taking up the slack. Once the bane of many industrial and commercial systems, the motherboard-based computer has come a long way. It wasn’t too long ago that PCs earned a bad name as low-cost motherboards usually imported and slapped together in a system that, perhaps more often than not, failed for one or more of a variety of reasons. But, PCs that were designed for intermittent operation in benign environments were often piled up together with limited air circulation in un-air-conditioned equipment closets and asked to perform 24/7. There was no notion, at the time, of a ruggedized PC. And, often the difference in price between rugged computers and motherboard-based PCs was so dramatic there was little option. Nightmare stories abound about the early days of PCs in industrial control and communications. Some took the form of humor, such as instead of having lamps to indicate which unit(s) failed, an operator simply had to look and see where the smoke was coming from. Other stories talked of costly molding machines and other in-


January 2007

dustrial equipment rendered useless because of computer failures. Those days are now behind us. PCs are finding themselves in a variety of places one might have found PDP-11s or VAX or SGI machines in years past. This was particularly apparent at the recent I/ITSEC (Interservice/Industrial Training, Simulation and Education Conference). This traditionally military-oriented conference focuses on a variety of simulation and training. However, over the past few years there seems to be a significant shift. First, there’s been a shift away from what was once the main military thrust of the show from aircraft cockpit, small arms and battle simulators to all variety of simulation for both military as well as both industrial and commercial applications. That’s not to say the former were not there, they were; but they are beginning to be upstaged by more commercial/industrial simulators. Everyone from engine repair and service technicians to heavy crane operators now learn their craft on elaborate simulators. Second, there’s been a shift as more and more PCs are replacing racks of minicomputers and other elaborate hardware. In some booths, purpose-built hardware still prevailed, but in an increasing number, PCs were apparent. In some cases they were specially packaged to withstand the rigors of the specific application, in others, several stand-alone PCs were sitting around the periphery of the simulator cabled together. And PCs seem to be up to the task of running advanced simulation. It’s come a long way from the early days of Microsoft’s Flight Simulator—or for that matter, the early Link trainer. Today’s PCs often have multiple multicore processors, elaborate graphics subsystems ultra-high-performance memory and more. And in some cases also feature custom packaging incorporating multiple fans—one for the processor chip, one for the graphics subsystem, one for the memory subsystem, one for the power supply and two to bring in and expel fresh air. Is the battle over for other architectures? Not by a long shot—expect to see big growth numbers for MicroTCA and others in the future—but in the meantime, PCs are here to stay and are expected to see continued growth in industrial and commercial applications.

Warren Andrews Associate Publisher

Images Courtesy of U.S. Army

More Features. More Rugged. More reasons to choose Radstone. The one and only ICS-8550. Designed for high-speed data acquisition applications such as Software Defined Radio, SIGINT, tactical communications and radar, the ICS-8550 XMC module – which is available for both benign and rugged environments – can simultaneously sample two RF/IF inputs at frequencies up to 210 MHz at a resolution of 12 bits. With the industry-leading Xilinx Virtex-4 FPGA at its heart to deliver unprecedented power and user programmability – and enabling IF/UHF signals to be processed directly on the board itself, freeing the host board for other tasks - the ICS-8550 is truly an ADC module that sets new standards. And with up to eight lanes of high-speed serial I/O, the ICS-8550 provides the throughput to match its performance and flexibility. Configure it with Radstone’s remarkable V4DSP FPGA/PowerPC processor, and the partnership is unbeatable.

Radstone. For when you need more.



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