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Tech Focus: OpenVPX SBC Roundup


The Journal of Military Electronics & Computing

HPEC Technologies Push Envelope of Compute Density

Programming Language Innovations Enable SafetyCritical Systems Integrated Systems Benefit from Formal Thermal Testing An RTC Group Publication

July 2014 Volume 16 Number 7

Rugged Boards & Solutions We know PCIe/104. And we do it best. At RTD, designing and manufacturing rugged, top-quality boards and system solutions is our passion. As a founder of the PC/104 Consortium back in 1992, we moved desktop computing to the embedded world. Over the years, we've provided the leadership and support that brought the latest signaling and I/O technologies to the PC/104 form factor. Most recently, we've championed the latest specifications based on stackable PCI Express: PCIe/104 and PCI/104-Express.

With our focused vision, we have developed an entire suite of compatible boards and systems that serve the defense, aerospace, maritime, ground, industrial and research arenas. But don't just think about boards and systems. Think solutions. That is what we provide: high-quality, cutting-edge, concept-to-deployment, rugged, embedded solutions. Whether you need a single board, a stack of modules, or a fully enclosed system, RTD has a solution for you. Keep in mind that as an RTD customer, you're not just

working with a selection of proven, quality electronics; you're benefitting from an entire team of dedicated engineers and manufacturing personnel driven by excellence and bolstered by a 28-year track record of success in the embedded industry. If you need proven COTS-Plus solutions, give us a call. Or leverage RTD's innovative product line to design your own embedded system that is reliable, flexible, expandable, and serviceable in the field for the long run. Contact us and let us show you what we do best.



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The Journal of Military Electronics & Computing


COTS (kots), n. 1. Commercial off-the-shelf. Terminology popularized in 1994 within U.S. DoD by SECDEF Wm. Perry’s “Perry Memo” that changed military industry purchasing and design guidelines, making Mil-Specs acceptable only by waiver. COTS is generally defined for technology, goods and services as: a) using commercial business practices and specifications, b) not developed under government funding, c) offered for sale to the general market, d) still must meet the program ORD. 2. Commercial business practices include the accepted practice of customer-paid minor modification to standard COTS products to meet the customer’s unique requirements. —Ant. When applied to the procurement of electronics for he U.S. Military, COTS is a procurement philosophy and does not imply commercial, office environment or any other durability grade. E.g., rad-hard components designed and offered for sale to the general market are COTS if they were developed by the company and not under government funding.

July2014 Volume 16 Number 7

FEATURED p.10 HPEC Solutions Strive for Data Center Computing Levels SPECIAL FEATURE HPEC System Strategies in Defense


10  HPEC Solutions Strive for Data Center Computing Levels

6 Editorial

18  Affordable and Approachable HPEC Technologies Meet New Defense Needs


The Inside Track


COTS Products


Marching to the Numbers

Open Season

Jeff Child, Editor-in-Chief Vincent Chuffart, Kontron

TECH RECON Safety-Critical and Mission-Critical Embedded Software 24  Parallel Programming Languages Enable Safer Systems S. Tucker Taft, AdaCore

SYSTEM DEVELOPMENT Pre-integrated Systems Tackle Technology Readiness 30 Filling the Need for Formal Methods in ATR Thermal Testing Part 1 Miguel de la Torre, CM Computer

TECHNOLOGY FOCUS OpenVPX SBCs 38 OpenVPX Secures Place alongside VME as a Staple in Military Systems Jeff Child, Editor-in-Chief


OpenVPX SBC Roundup

Digital subscriptions available:

Coming in August See Page 48 On The Cover: High Performance Embedded Computing (HPEC) continues to be a critical technology for a variety of shipboard systems. Shown here, the guided-missile cruiser USS Cape St. George (CG 71) operates in the Pacific during exercise Koa Kai 14-1. The exercise is designed to prepare independent deployers in multiple warfare areas and provide training in a multi-ship environment. (U.S. Navy photo by Mass Communication Specialist 1st Class David Kolmel)



The Journal of Military Electronics & Computing

Editorial EDITOR-IN-CHIEF Jeff Child, EXECUTIVE EDITOR Johnny Keggler,

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COTS Journal | July 2014

HOME OFFICE The RTC Group 905 Calle Amanecer, Suite 250 San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050 EDITORIAL OFFICE Jeff Child, Editor-in-Chief 20A Northwest Blvd., PMB#137, Nashua, NH 03063 Phone: (603) 429-8301 PUBLISHED BY THE RTC GROUP Copyright 2014, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.

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EDITORIAL Jeff Child, Editor-in-Chief

Open Season


he idea of open architecture and standards-based technology seems fundamental to our military embedded computing industry. So much so that it’s hard to imagine our industry without VME and OpenVPX, CompactPCI, COM Express, PC/104 and so on. But the reality is that the defense industry is still full of untapped territory when it comes to open systems. For every successful legacy system based on technology refreshed VME, there are others based on a proprietary system box that requires a single contractor for any upgrades or maintenance. It’s not that the idea is new. Paralleling the birth of the COTS movement, the open systems talk started as long ago as the DoD’s Open Systems Joint Task Force (OSJTF) as 1994. And there have been recent initiatives too, such as the 2010 and 2012 Better Buying Power Initiatives, and a 2013 Interim DoD Instruction 5000.02, “Operation of the Defense Acquisition System” that called for “applying open systems approaches in product designs where feasible and cost-effective.” And then there’s the more recent Open Systems Architecture Data Rights Team, co-chaired by the Office of the Under Secretary of Defense for Acquisition, Technology and Logistics and the Office of the Assistant Secretary of the Navy for Research, Development, Test and Evaluation. In this new era of highly scrutinized DoD budget spending, I believe the prime contractors that exhibit the most cost-efficiency will emerge as the leading force for the next generation of military platform design and acquistion. And I think a vital part of achieving that efficiency will require moving to a more comprehensive reliance on open architectures—and leveraging standards-based efforts across many similar platforms. For their part, each of the Service branches has had policies for incorporating open systems on their weapon acquisition programs. A recent GAO report reviewed some of the challenges that the DoD has had with open systems practices. The Navy has had the most success in institutionalizing open system acquisitions. Examples of success stories along those lines include three unmanned aircraft systems, the P-8 Poseidon maritime patrol aircraft, and the most recent effort to develop a replacement Presidential Helicopter. Meanwhile, the Air Force and the Army are beginning to embrace open systems acquisitions as well, albeit in a more ad hoc fashion, with some programs such as the Air Force’s KC-46 Tanker showing promise for future lifecycle cost savings, according to program officials.


COTS Journal | July 2014

According to the GAO report, the most difficult challenge is overcoming a general cultural preference within the Services for acquiring proprietary systems that puts lifecycle decisions in the hands of the contractors that developed and produced those systems. The contractor making those systems benefits from maintaining the status quo with respect to long-term weapon system sustainment. Although new open systems guidance, tools and training are being developed, the report says the DoD is not tracking the extent to which programs are implementing this approach, or if programs have the right amount of expertise to implement an open systems approach. A couple examples where using proprietary systems has caused problems are the B-2 bomber and the C-130 aircraft. The Air Force is spending over $2 billion to upgrade the B-2 bomber’s communications, networking and defensive management capabilities. Because the B-2 program’s prime contractor is the sole system integrator and possesses proprietary technical data and software, there’s no opportunity for competition to help drive down program costs. The Air Force planned to replace the aging avionics systems on the C-130 aircraft with open architecture avionics systems. But because of the various configurations, the upgrades required custom-built hardware, and less expensive COTS technology could not be used. As a result, the C-130 modernization cost estimates rose from $4 billion to over $6 billion. And the number of planes able to be modernized shrank from 519 to 221. For the fiscal 2015 budget, the Air Force is proposing a scaled-down cheaper upgrade effort. The GAO recommendations on this topic began with a report in July 2013, and were reviewed last month when documenting its “Review of Private Industry and DoD Open System Experiences” briefing to the House’s Committee on Armed Services. Some interesting recommendations were made. They recommended that the Air Force and Army implement their open systems policies, and that the DoD develop metrics to track open systems implementation. They also recommended that the Services report on these metrics, and that they assess and address any gaps in expertise. The time is ripe for this kind of thinking. With costs at the forefront of many military budget decisions, it’s open season for open systems practices. And our industry has the products and technologies that feed those needs.


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INSIDE TRACK Army, Lockheed Martin Complete Second Autonomous Convoy Demo The U.S. Army Tank Automotive Research, Development and Engineering Center (TARDEC) and Lockheed Martin successfully demonstrated additional capabilities of the Autonomous Mobility Appliqué System (AMAS) May 29th at the Department of Energy’s Savannah River Site in South Carolina by conducting a driverless line-haul convoy with seven military trucks at speeds up to 40 mph. The recent AMAS CAD II demonstration built upon the capabilities that were demonstrated at Ft. Hood, Texas in January 2014, where three unmanned military trucks negotiated oncoming traffic, followed rules of the road, recognized pedestrians and avoided various obstacles at speeds up to 25 mph in an urban environment (Figure 1) AMAS is a Joint Capability Technology Demonstrator, or JCTD; which means it’s a joint program between the U.S. Army and the U.S. Marine Corps. The AMAS common appliqué kit consists of the bi-wire active safety kit and the autonomy kit. It uses Global Positioning System (GPS), Light Detecting Radar (LIDAR) systems, Automotive Radio Detection and Ranging (RADAR) and commercially available automotive sensors in order to make the system affordable. The AMAS JCTD goal is to standardize these kits across both the Army and Marine Corps and give the warfighter the ability to transform ordinary vehicles into optionally manned vehicles.

Figure 1

Lockheed Martin Bethesda, MD (301) 897-6000

Air Force Taps IAI for Aircraft Damage Registration Tool Contract Intelligent Automation, Inc. (IAI) has been awarded a $4 million contract from the Air Force Research Laboratory, under the Critical R&D SBIR program, to develop an inlet and exhaust damage registration sensor for high-performance aircraft. The U.S. Air Force is interested in improving methods to quickly and effectively assess aircraft damage that occurs during routine training, combat and maintenance activities. Demanding operational tempos require near real-time assessment of aircraft operational status. Though partially automated health assessment systems have been integrated into daily maintenance routines, many FIND the products featured in this section and more at


COTS Journal | July 2014

Demo of the Autonomous Mobility Appliqué System (AMAS) consisted of a driverless line-haul convoy with seven military trucks at speeds up to 40 mph.

inspections are still conducted manually, including inspecting engine inlet and exhaust cavities. To address this critical need, in this effort IAI will develop AUTOSCAN, a simple, cost-effective automated inlet and exhaust coating damage registration system that electronically captures the defect/ damage characteristics, location and orientation relative to the aircraft coordinate system for transfer to existing aircraft maintenance health assessment systems. Intelligent Automation Rockville, MD (301) 294-5200

Northrop Grumman and Navy Team to Boost MQ-8B Fire Scout’s Visual Reach Northrop Grumman and the U.S. Navy demonstrated a new

multimode maritime surveillance radar on the MQ-8B Fire Scout unmanned helicopter that will drastically enhance long-range imaging and search capabilities for Navy commanders (Figure 2). Warfighters will now have the latest in radar technology to pair with their current electro-optical infrared payload. Integrating this new radar system will provide the MQ-8B Fire Scout with essential operational capabilities in all tactical environments and will improve how it addresses threats in real-world scenarios. This modernized radar complements Fire Scout’s other sensors and systems to provide the Navy with increased visibility far beyond the horizon, while collecting vital imaging for maritime operations. Northrop Grumman modified a Telephonics Corporation AN/ZPY-4 multi-mode maritime surveillance radar system used for manned

aircraft, so it could be used on the unmanned MQ-8B Fire Scout. Northrop Grumman Los Angeles, CA (310) 553-6262

Figure 2 A new multimode maritime surveillance radar on the MQ-8B Fire Scout unmanned helicopter will drastically enhance long-range imaging and search capabilities for Navy commanders.



Figure 3

Figure 4

New MH-60R Seahawk helicopters have a mix of sophisticated sensors allowing them to assume the U.S. Navy’s primary anti-submarine and antisurface warfare roles of today’s SH-60B and SH-60F aircraft.

The Iver3 Nano AUVs represent a new class of very small lightweight AUVs weighing less than 39 lbs with modern chirp-based sonar.

Cubic Awarded Contract to Support Navy Fielded Training Systems

Raytheon Selected to Demo Next Generation, Modular Radar System

Cubic Worldwide Technical Services (CWTS), a subsidiary of Cubic, was awarded a task order under the U.S. Navy’s Fielded Training Systems Support (FTSS) III Indefinite Delivery/Indefinite Quantity (IDIQ) contract. The five-year program is valued in excess of $65 million and provides operations and maintenance support of aviation training devices for the MH-60R, MH-60S and other aircraft (Figure 3). Operations and maintenance support will be provided at NAS North Island, CA; NAS Jacksonville and NS Mayport, FL; NS Norfolk and MCBF Quantico, VA.; and MCBH Kaneohe Bay, Hawaii. This task order also provides simulator and academic instruction for Navy helicopter pilots and aircrew at NAS North Island and MCAF Quantico.

Raytheon has been awarded a $6 million study and demonstration contract by the Office of Naval Research (ONR) to further develop an Enterprise Air Surveillance Radar (EASR). Raytheon’s EASR concept leverages proven Radar Modular Assembly (RMA) architecture matured on Air and Missile Defense Radar (AMDR). EASR’s flexible approach meets the performance needs of different candidate ship classes for ship self-defense, situational awareness, air traffic control and weather monitoring. The Radar Modular Assembly (RMA) affords EASR the scalability to be used on a variety of ship sizes across a diverse set of mission requirements ultimately offering reduced total ownership cost across all the EASR equipped platforms. The RMA has been designed and tested to prove that it operates successfully in the stressing EASR naval marine environments. Raytheon

Cubic Defense Systems San Diego, CA (858) 277-6780

is the largest producer of active phased arrays in the world and has a long and distinguished history of providing Naval radar systems. Raytheon Waltham, MA (781) 522-3000

U.S. Navy Purchases Four Iver3 AUVs and Modernizes Three Iver2 Systems OceanServer Technology announced that it has received orders for four new Iver3 AUVs across three different U.S. Navy contracts. The new vehicles will include two standard Iver3-580 units and two new Iver3-450 Nano AUVs. The Iver3 Nano AUVs represent a new class of very small lightweight AUVs weighing less than 39 lbs with modern chirp-based sonar (Figure 4). Two new Iver3-580 systems have already been delivered to the Navy EOD Group, and the other two will be delivered within the next few months to the Naval Oceanography Special Warfare Center (NOSWC).

OceanServer will also modernize three older Iver2 systems with higher resolution sonar and new DVL units that improve navigation and collect current profile data. The Iver platform has gained strong acceptance from Navy customers around the world for high-resolution imaging in littoral waters. OceanServer continues to lead the AUV industry in driving costs lower while offering world-class sonar solutions from five different recognized vendors. OceanServer Technology Fall River, MA (508) 678-0550

FIND the products featured in this section and more at

COTS Journal | July 2014


SPECIAL FEATURE HPEC System Strategies in Defense


COTS Journal | July 2014


HPEC Solutions Strive for Data Center Computing Levels While it’s hard to find any consistent definition of High Performance Embedded Computing (HPEC), the demand for high levels of serverclass compute muscle is growing for defense system designs. Jeff Child, Editor-in-Chief


here are few terms more hotly debated right now than High Performance Embedded Computing (HPEC). Definitions vary among technology vendors in our industry. At a broad level the basic idea is to leverage technologies like VPX and PCIe to provide massive processing power for compute-intensive systems. Such systems can meet immense throughput and processing requirements in space-constrained systems handling more than a teraflop of data. But the disagreement comes in about just what is truly HPEC. Systems with highly dense arrays of GPGPUs are one approach. Another is achieving a data-center level of computing with the use of server-class Xeon processors and all their support electronics. Then there’s the added twist of some sort of computing virtualization, allowing software programs to function on massively parallel multiprocessing systems as if they’re on a single processor. And still others would lump any boards or systems using the latest and greatest laptop processors under HPEC. Meanwhile, there’s overlap between military use of supercomputing-level High Performance Computing (HPC) and more rugged High Performance Embedded Computing (HPEC) systems that meet the cooling and size constraints particular to deployed military platforms. For the purposes of this article, we will concentrate on those HPEC approaches from companies who expressed a particular opinion on the topic to COTS Journal.

COTS Journal | July 2014




JSOW Scores Direct Hits in Back-to-Back Flight Tests Raytheon and the U.S. Navy recently showcased the operational capability of the Joint Standoff Weapon in challenging back-to-back flight tests. Launched from F/A-18F Super Hornets, at approximately 25,000 feet, two JSOW II C air-to-ground weapons flew preplanned routes before destroying simulated cave targets. JSOW C is designed to provide fleet forces with robust and flexible capability against high value land targets, at launch ranges up to 70 nautical miles.

Navy ISR Task Order Continues Aerosonde UAV Multi-Mission Role Textron Systems Unmanned Systems, a business of the Textron Systems segment of Textron, announced a task order under the U.S. Navy Intelligence, Surveillance and Reconnaissance (ISR) Services program. Award of this new task order is in addition to extension of existing task orders, bringing the total monthly mission hours provided under the contract to 4,500 across all international sites. Under the ISR Services IDIQ, Textron provides end-to-end, turnkey mission support with its Aerosonde Small Unmanned Aircraft System (SUAS).

Raytheon Conducts First Live Fire Test of Excalibur S In a company-funded R&D initiative, Raytheon last month announced that it had successfully fired the dual-mode GPSand laser-guided Excalibur S for the first time. Although the Excalibur S was initialized with a GPS target location, it scored a direct hit on a different, or offset, target after being terminally guided with a laser designator. The new variant incorporates a laser spot tracker (LST) into the combat-proven Excalibur Ib projectile, the world’s most precise GPS guided 155mm artillery projectile now in production.

Sagem Integrates Its Patroller UAV with New Imagery/Sensors Payload Sagem (Safran) recently tested and integrated successfully a new generation optronics multi-sensors suite on its Patroller endurance UAS. Tested in France between April and June 2014 during a campaign of 30 flights, this new optronics suite is based on a Euroflir 410 gyrostabilized turret. It is characterized by extended capabilities for long distance identification, day and night. Developed by Sagem, the Patroller is a 1-ton class tactical UAS.


COTS Journal | July 2014

Figure 1 The HDS6602 High Density Server is a 6U OpenVPX processing module with two 10-core Intel Xeon processors running at 1.9 GHz and supporting up to 128 Gbytes of memory.

Open Fabrics for HPEC One of the first emergences of HPEC in our industry was two years ago when Curtiss Wright announced a commercially available port of OFED (Open Fabrics Enterprise Distribution) for RapidIO. The stack included support for Remote Direct Memory Access (RDMA), and it allowed users to build high-performance, scalable HPEC systems using open software and Serial RIO. Since then Curtiss Wright has introduced numerous products in their HPEC family, and its fabric efforts evolved into the Fabric40 ecosystem. Fabric40 allows system integrators to build optimally configured HPEC systems using the latest high-speed fabrics. Fabric40 supports both Ethernet and InfiniBand protocols with data rates up to 40 Gbits/s to ensure processing nodes are not starved waiting for data. Ethernet is supported using industry standard 10G and 40G interconnects, and InfiniBand supports data rates of SDR (10G), DDR (20G) and both QDR and FDR-10 (40G). Fabric40 also includes middleware software enablement such as IPC and OFED/ MPI interfaces. The company’s latest HPEC product is its CHAMPFX4 module, a 6U FPGA engine featuring triple onboard Xilinx Virtex-7 devices in a single chassis slot, which is scheduled for full L0 production in Q2 2014. The board has been demoed moving more than 1 Terabit of data per second.

Server-Class Embedded Processing One definition of HPEC that’s prevalent is the idea that the computing must be a server-class solution. What’s meant by that is not just the processing, but also all the I/O and memory technology used in data-center type servers but designed into an embedded platform. An example of this server-class computing approach is Mercury’s Ensemble HDS6602 High Density Server (Figure 1). Powered by two 10-core Intel Xeon processors E5-2648L v2 (codenamed Ivy Bridge-EP) running at 1.9 GHz and supporting up to 128 Gbytes of memory, this 6U card is a standard, 1-inch pitch OpenVPX module. Native Intel Quick Path Interconnect (QPI) v1.1 inter-processor interconnects enable virtual cache coherent processor cores deliver-

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Figure 2 The Tarantula, a ruggedized, Xeonbased Secure Virtual Machine (SVM) server with six hardware-independent I/O modules, was reportedly chosen for the Army’s MRAP Night Vision program .

ing true deterministic processing. Onboard Gen 3 PCIe pipes feed the data plane with either 40 Gbit/s Ethernet (TCP/IP and Sockets) or DDR/QDR/FDR10 InfiniBand. QPI is one example of technology that’s available

in Xeon-based systems but not the more laptop-based processors like Core i7 processors. For its part, one of Mercury Systems most representative applications of the HPEC server technology is an airborne server application. Announced last fall, the system can process and exploit huge amounts of sensor data in real time, store it on board for retrieval and forensic analysis, and send imagery to ground stations or handheld devices. According to the company, this capability is achieved through the integration of Intel Xeon server-class processors, general purpose graphical processing units (GPGPUs) and ruggedized solid state disk storage arrays. The system was deployed effectively as a data center server in the sky onto airborne pods.

Keeping HPEC Cool One of the challenges in HPEC systems is that massive amounts of processing means a much trickier heat dissipation problem. Rather than tackle that them-

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More and more military applications want not just HPEC-level computing, but they also want it in ever small footprints. The demand is for creating several virtual systems in one box, in as small a rugged system as possible. Along just those lines, General Micro Systems (GMS) recently rolled out a conduction-cooled, fully ruggedized Secure Virtual Machine (SVM) server with six hardware-independent I/O modules. Designed to replace multiple workstations using virtual machine technology, Tarantula (SO302 4-in-1) incorporates an enterpriselevel Layer 2 or Layer 3 intelligent switch for high-speed connectivity. The box measures 11.75 x7.75 x4.5 inches, weighs 18 lbs and is powered at as low as 180W. Tarantula is well suited for applications requiring ultra-efficient information sharing between several computers serving varied purposes. Intel’s Xeon processor, the IvyBridge-EP, is the host CPU driver and features 10 physical cores each operating up to 2.4 GHz, with the ability to TurboBoost to 3.0 GHz. Support for hyperthreading expands its capability to 20 logical cores. Tarantula dynamically al-

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COTS Journal | July 2014

selves, military system developers can leverage complete box-level solutions that come with those problems already addressed. Introduced in March, an example along those lines is GE Intelligent Platforms’ CRS 48.5 High Performance Embedded Computing (HPEC) Rugged Subsystem. This system uses advanced VITA 48.5-compliant air-flow through-cooling to allow the integration of up to eight quad core Intel Core i7 processing nodes. The CRS 48.5 ATR subsystem features the GE DSP280 multiprocessor with two quad core Intel Core i7 processors. The DSP280 is capable of more than 260 gigaflops peak performance and delivers main memory bandwidth of up to 21 Gbytes/s per CPU node. The CRS 48.5 rugged subsystem takes advantage of the connectivity and performance of GE’s switch fabric module (SFM) family such as the GBX460 fully managed 10 Gigabit Ethernet data plane switch or the IBX400 InfiniBand SFM for increased data plane bandwidth with lower latency. Sensor data input is supported via up to four 10 Gigabit BASE-SR fiber channels via the external connectors.

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Figure 3 The 3U High-Density Compute Accelerator (CA16000) provides up to 73.3 Teraflops of computational power using NVIDIA Tesla K10 GPU accelerators.

locates these cores in real time as needed by each of up to six virtual machines and their individual application requirements. The host CPU supports one 4-lane PCIe XMC site, one 10 Gigabit Ethernet port, four USB 3.0 and two USB 2.0 ports with power, two serial ports with RS-232/422/485 buffers, full HD-Audio and eight general purpose I/O lines.


COTS Journal | July 2014

Tarantula’s intelligent Gigabit Ethernet switch functions are powered by a 416 MHz MIPS CPU (with 128 Mbytes of DRAM) that controls the (up to) 18 Gbit Ethernet ports, and a second 10 Gigabit Ethernet port, which comes with the option of copper or fiber. According to GMS, the Army selected Tarantula for the MRAP Night Vision program because the six virtual machines can control real-time video, defensive counter measures and other critical operations—all in one small chassis (Figure 2).

(RES-XR4-TRM) module is an out-of-band resource management system that also occupies one of four HD chassis slots. And the 2U RES-XR4-HD system chassis houses stand-alone, hot-pluggable processor, storage (HDS, HDFS and HDS8), high-speed switching and system management module options. The leading-edge components include Intel Xeon E5 2600 V2 Series processors and Supermicro motherboards; processor modules support up to three 56 Gbit/s InfiniBand (IB) or 40 Gbit Ethernet.

High-Density Computing

GPGPUs as Compute Elements for HPC

Computing-density is a definite theme in the HPEC technology trend. Themis Computer recently announced the addition of system management and networking modules for their Intel-based RES-XR4 highdensity (HD) server product line. The RESXR4-Switch module occupies one of four HD chassis slots with a 12-port, managed 56 Gbit/s InfiniBand VPI SDN/40GBe switch system that delivers up to 1.3 Terabits/s of non-blocking bandwidth and 200ns port-toport latency. The Themis Resource Manager

In our industry, there’s definitely some overlap between HPEC and the broader term High Performance Computing. A number of solutions are available under the HPC categories where the goal is more pure performance than ruggedness. Performance levels of these systems are in the Teraflop range and usually make use of GPGPU or FPGA technologies. Along such lines, One Stop Systems offers a PCIe Gen3 expansion appliance that supports up to 16 high-end accelerator boards from a single or multiple


servers. The 3U High-Density Compute Accelerator (CA16000) provides up to 73.3 Teraflops of computational power using NVIDIA Tesla K10 GPU accelerators (Figure 3). The CA16000 is a complete appliance, solving integration issues and making installation easy. The user simply connects the cable or cables to the host server(s) and has hundreds or thousands of additional compute cores readily available. Also achieving Teraflop levels of performance is BittWare’s TeraBox, an FPGA platform designed for network/packet processing and High Performance Computing (HPC) applications. Featuring up to sixteen of the largest Altera Stratix V Family FPGAs, the TeraBox offers 20 Teraflops of processing power, along with 6.5 Terabits/s of memory bandwidth and 1.28 Terabits/s of I/O—all in a turnkey rackmount solution. The system arrives tested and configured, and includes complete development software support with BittWare’s BittWorks II Toolkit, allowing users to immediately focus on developing their specific application. The TeraBox features up to eight BittWare full-size S5PE-DS PCIe boards based on the high-bandwidth, power-efficient Altera Stratix V FPGA. Each S5PE-DS PCIe board features two Altera Stratix V FPGAs for a system total of up to 15 million logic elements (952,000 per FPGA) and 62,000 18 x 18 variable precision multipliers (3,926 per FPGA). While the definition of HPEC can get a little fuzzy in this industry, it’s definitely feeding the military’s almost insatiable demand for dense computing solutions. This trend will only strengthen as military embedded system vendors leverage the latest and greatest processor and fabric technologies into packaged solutions for defense applications.

General Micro Systems Rancho Cucamonga, CA (909) 980-4863

One Stop Systems Escondido, CA (877) 438-2724

Mercury Systems Chelmsford, MA (978) 967-1401

Themis Computer Fremont, CA (510) 252-0870

BittWare Concord, NH (603) 226-0404 Curtiss-Wright Controls Defense Solutions Ashburn, VA (703) 779-7800 GE Intelligent Platforms Charlottesville, VA (800) 368-2738

COTS Journal | July 2014


SPECIAL FEATURE HPEC System Strategies in Defense

Affordable and Approachable HPEC Technologies Meet New Defense Needs High-performance embedded computing is a major requirement for the compute-heavy needs of many of today’s military systems. But the trick is to achieve an affordable solution that’s straightforward to implement. Vincent Chuffart, Military & Aerospace Product Manager, Kontron


hen most defense program contractors think of high-performance embedded computing (HPEC) systems, they envision huge behemoth solutions that can take on the most labor-intensive processing that would have taxed lesser computing technology only a few years ago. That perception is definitely accurate with HPEC systems continually advancing to allow command and control units to see or detect smaller objects in a bigger field. Today’s cameras have up to a massive 20K plus field of view with amazing resolution from pixel points that go on forever. That camera input requires HPEC systems to process huge amounts of data. And, the latest extremely sensitive sensor-based systems deliver capabilities that leapfrog previously developed technology.

Two Types of HPEC Needs Available computing architectures have enabled defense program developers to build a very broad spectrum of HPEC applications to match diverse requirements. When developers evaluate computing solutions, they typically have two different types of needs for HPEC. The first is compute-bound, which demands multiple processors to solve a problem, without the need for extensive bandwidth capabilities. The second type of HPEC system is I/O18

COTS Journal | July 2014

bound, where application data comes in and is split or shared between systems that do little work with the data but needs highbandwidth connectivity between processors and with the outside world. Supporting the high-end camera example previously mentioned is a separate I/O-bound application that would be used to push all this data down to a ground station. That requires enough bandwidth to enable the system to parse the data out for access by varying systems and personnel, enabling them to make intelligent decisions. There seems to be no end in sight for increasingly advanced defense capabilities that can be achieved from the processing of multisensor data. The prevailing development approach for HPEC is to look for specialized silicon primarily adopting FPGAs as the solution that will allow systems to react immediately to data and perform electronic warfare algorithms and co-processing functions. All that said, the latest with HPEC solutions is that they’ve been evolving quietly but steadily. They’ve progressed to where they can be implemented in much smaller standardsbased platforms—rather than in the perceived mega-computing solutions currently deployed. Many new HPEC system needs can actually be handled now with more mainstream IT technology packaged in a compact way in a 3U VPX-based system that balances I/O and

CPU power with high-speed I/O backplanes and multicore x86 processing architectures.

Why Mainstream IT Makes Sense Tackling many of the HPEC-type problems that used to require highly sophisticated architecture with mainstream IT solutions is really an advantage for defense contractors. They can save their most experienced engineering resources for complex, large-scale systems that still require that level of expertise. Instead of requiring a lot of specialty hardware, I/O and switch fabric to qualify as an HPEC system, developers now have access to proven technologies such as Intel multicore processors, PCIe and 10/40 Gbit Ethernet, which allows a complete HPEC compute engine to be built off of only standards-based components. For example, Intel architecture provides coprocessing capabilities with a GPU that enable designers to include specific-function FFTs for 3D radar applications. This eliminates extra design steps to offload certain functions from an all-standard architecture. Plus, there is widespread engineering familiarity with mainstream IT technologies such as x86 processors, TCP-IP and the PCIe interface. This means a broader knowledge base can implement HPEC systems from laptops to high-end servers or even a conductioncooled, ruggedized HPEC for a UAV or ground program. Developers can now tackle larger

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Figure 1 VXFabric provides the required software between the PCIe Gen 3 switch and the bottom of the standard TCP/IP stack to enable boards to run any existing TCP/IP-based application without having to be modified. HPEC requirements that used to require specific proprietary solutions with well-known architectures that are easier to program and deploy. Experienced embedded computing suppliers have application-ready, small COTS VPX-based 3U solutions readily available.

meet defense program metrics by delivering the ultra-fast speeds they need on the backplane in a much smaller footprint. It also helps that COTS suppliers have the experience to accommodate new proof-of-concept requirements.

Endless Performance Appetite

Affordable, Approachable Solutions

The task of meeting mounting data processing needs from defense OEMs that typically request “as much performance as you can give us” is now met with the realities of tightening budgets and the fact that new technology is not created or needed every year. Defense contractors remain competitive by developing new technology templates that can be used for multiple programs and are viable solutions for three to five years. Without huge budgets and unlimited user support, defense contractors are finding it more difficult to support specialized silicon, language and fabric solutions. In addition, technology advancements move too fast to re-imagine new architectures from scratch. This is where COTS-based computing suppliers come in to help. They have proven building blocks and system solutions with the algorithms required mapped onto the computing architecture. Fewer OEM specialists are needed when HPEC suppliers can

Mainstream HPEC building blocks naturally reduce costs and provide an approachable engineering solution due to their standards-based platform methodology. They are proven to support everything from Gbyte/s performance needed for current radar systems, to tens of Gbytes/s needed for camera interfaces, and also satisfy five plus teraflops of computing power required for 3D radar. Taking HPEC from the data center into the field are simplified standards-based multicore platforms that solve high connectivity and low latency interconnects requirements. This approach gives basic skill level engineers the ability to build effective systems using modular processor interconnect fabrics that implement the TCP/IP protocol over the PCI Express infrastructure. The result is a tenfold increase in I/O performance with no porting effort, well-suited for most HPEC-based applications. Figure 1 shows an example solution along those lines. Experienced suppliers


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that offer mainstream HPEC platforms are able to support customers by building the computing portion of the application or giving them the right tools that streamline the replacement of a significant size system now with a couple of 3U VPX boards housed in a rugged, small chassis. It also helps that COTS suppliers have the experience to accommodate new proofof-concept requirements. In any complex application that requires a lot of processing power and I/O, there is the need to do upfront evaluation and benchmarking to ensure the system will meet specifications—from input rates, processing rates to the output.

Tools to Get the Job Done HPEC isn’t just for what developers consider the most compute-intensive applications anymore—HPEC fits a wider spectrum of program needs. But experienced and novice developers, too, still need tools to streamline the design process. Understanding system health management status is more important than ever with continued technology advancements. A good example is the changing clock speed to match battery demand in x86 processor architectures. While varying clock speed is fine for individual PCs, it isn’t good for military embedded systems that depend upon mul-

tiple computers and boards where each board has a different clock cycle that can result in an unstable power system. Health management software tools that control speed and computing power in one place are the answer. Available today are 3U VPX box-level systems that integrate a computer management board (CMB) for extensive health status information at the board and sub-rack level. Information such as airflow temperature can be controlled for each slot, and payload boards can be held in standby mode to accommodate low-energy surveillance mode. Figure 2 shows an example of a computer management board (CMB) that does system health management. Another way these tools are valuable is to ensure more realistic lab testing that simulates the stresses and environmental conditions where a system will be deployed. Simplification is key in testing new ideas, so using mainstream TCP/IP makes it so much easier to go from the lab to deployment with the same technology. Waiting until the last stage of development and integration to find out that the algorithm doesn’t perform to mission standards is very unwelcome news. A tool such as this becomes invaluable in terms of designing for power management when one considers that a typical user’s guide for today’s chipset devotes 12 pages to defining power management guidelines.

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Ready Mainstream HPEC Solutions Approaching the problem of HPEC with complexity is no longer necessary. Current 3U VPX systems strike the right balance between CPU computing power and I/O bandwidth by leveraging high-speed switched PCIe and 10 Gbit Ethernet on the backplane. These VPX-based, multiprocessor and highly integrated HPEC systems meet defense program performance and bandwidth specifications, making it far less

attractive to use more proprietary architectures. Furthermore, these modular pre-integrated HPEC solutions ensure longevity and flexibility while also providing beneficial customization features, enabling system designers to meet specific requirements of multiple programs. The modular building block approach makes way for future system upgrades, eliminating the need for a complete system redesign.

Figure 3 StarVX is based on a 3U VPX platform architecture, and provides up to 6 Gbytes/s sustained bandwidth on the data plane through TCP/IP and 4 Gbytes/s on the PCIe backplane from a high-speed switch fabric, VXFabric.

The use of standard communication protocols such as TCP/IP or UDP/IP allows OEMs to protect their application software investments. Developers can design legacy software to operate in the current application, and if the requirements evolve or change, new software based on TCP/IP is ensured to be supported for years to come. This design approach enables OEMs to optimize the total cost of ownership (TCO) and have a direct migration path from their existing application to systems deployed in the future. Figure 3 shows an embedded HPEC solution using TCP/IP over PCI Express.

Untapped Potential There is certainly untapped potential for defense OEMs to implement mainstream HPEC platforms that have reached a milestone using VPX to satisfy size, weight and power (SWaP) demands while at the same time delivering the higher performance and bandwidth. Because major jumps in technology occur in cycles, incremental program improvements and not just the toughest computing problems, offer new revenue streams for HPEC. These upgrades or mid-range systems can benefit from smaller machines that can get the job done. Kontron Poway, CA (858) 677-0877


COTS Journal | July 2014

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TECH RECON Safety-Critical and Mission-Critical Embedded Software

Parallel Programming Languages Enable Safer Systems Languages that use garbage collection pose tricky issues for military system developers. Innovative new parallel programming techniques offer a safer solution. S. Tucker Taft, VP and Director of Language Research, AdaCore


t is hard to escape the fact that we have entered an era of parallel computing based on multicore chips, GPUs and/ or distributed clouds of processing elements. What this means is that every military embedded system developer will sooner or later have to learn how to create and maintain parallel programs if they want to keep their job. Unfortunately, it is hard enough to create safe, secure, correct sequential embedded system software, so what will it be like when we have to create and debug parallel programs on a daily basis? For military embedded system developers to survive this transition to becoming parallel programmers, we could use some help from the language design world. Luckily, the systems programming language design world, after a decade or more of a relatively sleepy phase, has suddenly woken up and started to crank out a growing number of programming languages that support safe, or at least safer, parallel programming suitable for embedded systems development.

Trouble with Garbage Collection One particular feature appearing in a growing number of sequential languages, garbage collection is being reconsidered in the context of supporting safe, high-performance parallel programming. Fully general, asynchronous garbage collection had become a 24

COTS Journal | July 2014

Figure 1 The Titan Supercomputer performs distributed computing with 18,688 “nodes� including multicore processors (16 cores each) with vector units and GPUs with 64 warps of 32 lanes.

nearly universal aspect of newer sequential programming languages, and even in the embedded world the use of so-called managed languages is growing. But as the challenges of high-performance parallel system development are faced, alternative approaches to storage management are being considered. What is it about the parallel programming environment that argues for new approaches to storage management? There are three fundamental challenges with the use

of a global garbage-collected heap in such an environment. First of all, if there are many parallel computations generating garbage within a single program, there typically need to be many parallel garbage collector threads to keep up with them. Running garbage collection concurrently with program execution is challenging to begin with, particularly for a system with real-time requirements. Having multiple garbage collectors running in parallel with each other and with the running program, can add significant complexity and synchronization overhead, thereby reducing the advantages of parallelism to a point where it might no longer produce any speedup. The second major challenge associated with the use of a global garbage-collected heap in a parallel environment is that it makes it harder to determine whether two objects might share some amount of underlying data, meaning that it is also harder to safely parallelize the processing of two such potentially overlapping data structures. Most parallel speedups are based on a divide-and-conquer approach, and if it is difficult to divide up a large problem into pieces that are guaranteed to be non-overlapping, then additional synchronization overhead is needed to avoid conflicting simultaneous access to the same data. The third significant challenge associated with a global garbage-collected heap in this new parallel world is that the powerful


capabilities associated with GPU and distributed computing (including Cloud computing) depend on making use of multiple processing elements with potentially little or no shared memory An example is the Titan Supercomputer at Oak Ridge National Lab (Figure 1). A programming approach that allocates objects in a global heap, while freely sharing pointers across program components, is not easily adapted to an environment where processing elements run in their own address space, and need data allocated in that space or passed to them across the network. Unrestricted pointer-based data structures are notoriously difficult to pass across a network, as a decision must be made for each pointer value how to represent it within a message, and how or whether to reconstruct it on the receiving end. The alternative of allocating data initially in different memory spaces is challenging, because it runs counter to the free sharing of pointers across components.

tomatic storage reclamation. However, this approach has a downside in parallel environments, because some sort of synchronization is required when updating reference counts to avoid race conditions. At the next level, systems programming languages have begun to associate storage ownership properties with pointers. Along one dimension, pointers can be strong or weak—strong pointers will keep an object

alive, while weak pointers will point to an object only as long as it remains live, and will be set to null if the pointed-to object is reclaimed. Along a different dimension, owning or unique pointers provide exclusive access to an object, where language rules prevent any other way of getting to the same object, while shared pointers provide multiple paths to access the same object. The Singularity OS from Microsoft Re-

Storage Management There are moves afoot to introduce alternatives to the global garbage-collected heap, particularly for systems programming languages, where predictable performance is critical. At the simplest level, storage allocators have been getting smarter about providing separate storage arenas for separate parallel threads. This can dramatically reduce synchronization overheads associated with storage allocation. However, this does little to address the other issues mentioned above, and even this simple approach may not reduce overheads as much as it might, because generally it is possible for a different thread to deallocate storage from the one that allocated it, which brings back the need for synchronization. An alternative approach for automatic storage reclamation has been to abandon asynchronous garbage collection in favor of automatic reference counting, because it provides pause-free execution with immediate reclamation of storage when an object becomes inaccessible, modulo the requirement to manually break cyclic dependencies. This approach has been embraced for use in the iOS mobile operating system, and is being considered for other systems programming languages that support au-




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COTS Journal | July 2014



Rust and Singularity O/S memory model Per-task heaps (gcol’ed) Managed pointers


Handoff Owning pointers

Global data-exchange heap (no gcol)

Figure 2 The Rust and Singularity OS languages use owning (tracked) pointers to ensure thread safety in a global exchange heap, while allowing shared (untracked) pointers only to objects within (garbage-collected) per-task heaps.

search used owning (tracked) pointers to ensure thread safety in a global exchange heap, while allowing shared (untracked) pointers only to objects within (garbagecollected) per-task heaps. A very similar approach has been adopted by the Rust language (Figure 2). The 2011 version of C++ provides unique_ptr, shared_ptr, and weak_ptr pointer types, corresponding to these distinctions. While pointer ownership approaches can make parallel programs safer, they don’t generally simplify the programmer’s job, as the programmer now has to decide between various different heaps and various different kinds of pointers. As an example, the Rust language has three different kinds of safe pointer types, plus a raw pointer type for unsafe programming. In some sense, we have exchanged one kind of “garbage” with another—the language now has significantly more “stuff ” for the programmer to worry about.

Virtuous Cycle of Simplification

Region-Based Storage Management in ParaSail Regions

Region Chunks

Object handles

If a language is born specifically to address the challenges of safe parallel and/or distributed programming, there is an option to address these storage management challenges by leaving out the parallelism-unfriendly features of languages born in the sequential era. An early language with this mission was the language Hermes (originally named Nil), with a strong focus on distributed programming. For more details on Hermes, see the Web-only sidebar “Simplifying Using Hermes.”

ParaSail Parallel Programming Language (no chunks)

Figure 3 Region-based automatic storage management in a language like ParaSail is appropriate for restricted-resource embedded system environments, where predictable, bounded, pause-free performance is critical.


COTS Journal | July 2014

ParaSail is a new parallel systems programming language that attempts to take the safety through simplicity approach to the next level. As with Hermes, ParaSail eliminates pointers and global variables. ParaSail also adopts the Hermes model of a hand-off semantics, but extends that even to calls within the same memory space, and with the important notion of a parameter mode, which allows both a read-only and read-write parameter hand-off. A read-only parameter hand-off prevents any further writing to the object by the sender/ caller, but allows parallel reading; a read-write parameter hand-off gives full exclusive control to the receiver/callee. These parameter modes (effectively capabilities for the object) apply

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to the object as a whole, not just to some toplevel layer of a pointer-based structure. The net effect is that safe shared read-only access, and exclusive read-write access, is built right into the parameter passing mode, eliminating race conditions “by construction,” and enabling the compiler to automatically parallelize all ParaSail expressions as it sees fit. For more details on the ParaSail programming language, see the Web-only sidebar “More Attributes of ParaSail” in the online version of this article. Because there are no global variables, all objects are associated with some logical stack frame or scope, and storage can be broken up into separate regions, one per scope, as in region-based storage management, eliminating the need for a single global heap and the associated synchronization bottleneck. The overall result is that region-based automatic storage management in a language like ParaSail is appropriate for restricted-resource embedded system environments, where predictable, bounded, pause-free performance is critical. Figure 3 shows a diagram of region-based storage management in ParaSail.

Cleaning out the Garage As programming languages evolve, it is almost inevitable that they grow more rather than less complex, and much like the typical garage, more and more “stuff ” accumulates that no longer serves the purpose of the current environment. But if we are going to expect all serious embedded system programmers to become authors of safe, secure, high-performance parallel programs, we need to examine all of the accumulated “stuff ” in our programming languages, and consider making a clean sweep. We should consider getting back to a nearly pristine state where we can start over and make certain that our languages have no features standing in the way of high-performance, resource-efficient parallel computing. A garbage-collected global heap is one common feature in sequential programming languages that is being reexamined in the context of the new highly parallel, distributed hardware environment that the embedded system programmers are now, or will soon be, facing. Furthermore, we

should reconsider our heavy reliance on pointer-based structures in embedded system programming. They should probably be swept out of the language “garage,” replacing them with higher-level pointer-free structuring mechanisms that support efficient divide-and-conquer parallelization and fast automatic storage reclamation. Finally, we should consider eliminating the whole pass-by-copy versus pass-by-reference distinction, and adopt a hand-off semantics for parameter passing that provides for safe, high-performance parallelism in both shared-memory and distributed-memory environments. AdaCore New York, NY (212) 620-7300

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COTS Journal | July 2014


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SYSTEM DEVELOPMENT Pre-integrated Systems Tackle Technology Readiness

Filling the Need for Formal Methods in ATR Thermal Testing Part 1 It’s no simple task to evaluate chassis heat dissipation and enclosed payload reliability in military systems. Establishing a universal criteria to obtain ATR benchmark thermal performance figures helps smooth the way. Miguel de la Torre, General Manager, CM Computer


specially with today’s electronics, ATR chassis payload cooling is an engineering challenge. The implementation of efficient heat dissipation techniques represents significant investment, engineering know-how and manufacturing cost for chassis suppliers. Chassis thermal dissipation figures are essential for making comparisons and establishing benchmark performance. Until now, no standard thermal testing procedures for COTS ATR chassis have been published in the market. Most manufacturers have been reluctant to provide comprehensive thermal performance data to facilitate clear product evaluation. With that in mind, discussed here is a set of standard procedures in order to classify and measure COTS military chassis thermal performance. Integrators and system developers can now access detailed enclosure thermal specifications to guarantee compliance with strict military system requirements.

ATR Thermal Testing Procedures Three thermal testing procedures, Linear Thermal Test (LT), Peak Thermal Test (PT) and Mixed Thermal Test (MT), are considered to be the most representative when examining an ATR chassis’ ability to dissipate heat (Figure 1). Temperature sen30

COTS Journal | July 2014

LT [4] [3] [2] [1]











T2 [3]











T1 T-room: 20ºC P-room:1atm

250W Total Payload Dissipation Example 5 Slot Chassis (5 x 50W Loads)










T2 T1

T-room: 20ºC P-room:1atm 250W Total Payload Dissipation Example 5 Slot Chassis (2 x 125W Loads)

T-room: 20ºC P-room:1atm 250W Total Payload Dissipation Example 5 Slot Chassis (1 x 125W + 4 x 31W Loads)

Figure 1 Shown here are example 250W - 5 Slot, Linear Thermal Test (LT), Peak Thermal Test (PT) and Mixed Thermal Test (MT) methods for different ATR chassis payload distribution.

sors should be installed on payload module card-rails as this is considered standard practice. Chassis thermal figures are obtained by powering on a thermally stable loaded chassis and plotting payload cardrail temperature rise over time. The Linear Thermal Test (LT) method divides the total system payload power by the number of chassis slots, loading each slot with conduction-cooled Eurocards of equal wattage. All chassis on the market can be easily tested under LT conditions

and fixed ambient temperature, allowing a standardized, straightforward comparison between chassis models. Chassis thermal performance figures (Temperature vs. Time) is averaged over the total number of slots, where chassis payload average temperature is LT-AV= (T1+T2+T3+...Tn)/n. ATR manufacturers are encouraged to publish Linear Test data for benchmark analysis and product evaluation. A Peak Thermal Test (PT) method is intended to evaluate chassis dissipation

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Surface Mount (and Plug-In) Models Figure 2 Shown here are examples of Linear, Peak and Mixed chassis thermal test figures obtained under different payload card-cage distributions. All tests are conducted with an equal Total Payload Power (TPP) of 250W.

performance against high power payloads concentrated within two slots (such as hot SBCs, DSP or FPGA boards). The total payload dissipation is shared between two conduction-cooled Eurocards that are positioned at opposing ends of the card-cage ( first and last slot). This is carried out in order to minimize heat concentration and thermal influence between payloads. Thermal figures are obtained from the average temperatures taken in both modules PTAV= (T1+T2)/2. The Mixed Thermal Test (MT) procedure simulates the most common ATR enclosure loading scenario. Total chassis payload dissipation is split between a single high power module inserted in slot 1 and an array of equal power payloads that fill the remaining slots. In deployed systems, the single “hot” module represents a SBC, DSP, or FPGA, etc., and the low power modules represent boards such as analog or discrete I/O modules, memory storage, etc. This test yields two payload temperature results, MT-T1 and the average MTAV=(T2+T3+T4+...Tn)/n-1 (Figure 2).

Eurocards tested in slots may either be passive (power resistors) or active (chips). Resistive rugged modules are desirable due to their high temperature tolerance above chassis PSU and backplane limits. All thermal procedures should be repeated for increasing payload wattages—100W, 250W, 400W and so on—until reaching internal temperature limits. Payload wattage testing will generate figures of payload Temperature versus Time, providing a thorough chassis thermal evaluation.

ATR Chassis Thermal Performance Linear Thermal Testing (LT) is the predominate method due to its simplicity and universal application. Therefore, ATR manufacturer thermal specifications should refer to LT data when supplying a product thermal performance coefficient. Rarely will manufacturers provide information regarding PT and MT data as they are primarily carried out for detailed chassis design evaluation and specific end system applications. Even when total payload power remains the same, each chassis thermal test

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COTS Journal | July 2014



chassis thermal self-dissipation performance: Chassis Payload Delta-T (ΔT) and Chassis Thermal Resistance (CTR). Chassis Payload Delta-T is the difference between payload card-rail temperature and external ambient reference temperature measured in a thermally stable operating chassis. Delta-T values are a function of chassis dissipation performance and Total Payload Power (TPP). In Figure 2, Peak Test ΔT is 43°C at 250 watts TPP, meaning two payloads of 125 watts each deliver an average payload card-rail temperature of 63°C at 20°C ambient. Therefore, ΔT-PT = 63°C - 20°C = 43°C. If Total Payload Power is increased, for example to 300 watts, then a new ΔT-PT of approximately 51.5°C is expected. Delta-T is a key figure of merit regarding enclosure dissipation capacity; low ΔT values are inherent in high-performance chassis. Chassis Payload Thermal Resistance (CPTR) indicates the rise in payload temperature per watt of payload power (°C/W). Given the selected test method (LT, PT, or MT), CPTR is obtained by dividing Delta-T and Total Payload Power (CPTR = ΔT/TPP). Chassis payload Peak Test thermal resistance is: 43°C/250W = 0.172°C/W (Figure 2).

Other Heat Dissipating Elements

Figure 3 Shown here are heat dissipation curves for increasing chassis electrical input power (Linear Test).

procedure, LT, PT, or MT, yields plots showing small temperature deviations as a consequence of different payload distributions in the card-cage. For simplicity, manufacturers should select 20°C at 1 atmosphere as the initial environmental chassis/payload reference conditions. This starting point facilitates laboratory testing and provides equally valid results as more complex scenarios that may require specialized equipment. A 60-minute test is sufficient to stabilize payload temperatures in most cases. During initial minutes of testing, payloads typically display a rapid increase in temperature; this is characterized by a sharp slope ramp rate (°C/min). As enclosure temperatures rise, heat transfer to ambient increases and payload temperature ramp rates stabi32

COTS Journal | July 2014

lize (Figure 2, Stage 2). Ramp rates are good indicators of thermal response time and measure the enclosure’s ability to respond to sudden changes in temperature (thermal shock). Short thermal response times are characteristic of Open Flowthrough ATRs, while slow response times are observed in Sealed systems. Several LT tests should be conducted with increasing payload or electrical input wattages in order to generate chassis selfdissipation thermal performance figures (Figure 3). Chassis are considered tooperate in “self-dissipation mode” when no external cooling mechanisms assist to improve their natural thermal performance—no attachment to cold base-plate, no external air forced through chassis frame, and so on. Two key parameters define COTS

Payload is not the only heat dissipating element within a chassis: PSU, filters, fans, TSU, backplane and other subsystems also generate a degree of heat that must be dissipated by the enclosure. System electrical power consumption (measured at ATR input voltage) is a good indicator of total system heat dissipation (Total Chassis Electrical Power (TCEP) is 28 VDC at 11.5 amps = 322 watts). The integral enclosure performance is characterized by the Chassis Global Thermal Resistance (CGTR) that indicates the rise in payload temperature per watt of system electrical power consumption. Given the selected test method (LT, PT, or MT), CGTR is obtained by dividing Delta-T and Total Chassis Electrical Power (CGTR = ΔT/TCEP). In Figure 2, CGTR Peak Test is: 43°C/322W = 0.133°C/W. For chassis designers, CGTR represents the “overall chassis thermal dissipation capacity” since this coefficient measures overall efficiency of the combined enclosure implemented

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Figure 4 This 7-slot 1” pitch VPX CM-ATR-135/HES COTS ATR supports sealed systems up to 450W (CGTR: 0.07°C/W).

cooling techniques (metalwork, heat exchangers, internal fans, exhaust fans, heat pipes, etc.). CGTR takes into account that chassis not only dissipate payload heat, but also dissipate the total amount of system generated heat. In practice, backplane, supervisory systems, auxiliary devices and so forth usually dissipate a relatively low amount of heat. Therefore, Chassis Payload Thermal Resistance (CPTR) and Chassis Global Thermal Resistance (CGTR) converge as PSU efficiency increases. Chassis thermal testing figures can be obtained by plotting payload temperatures against Total Chassis Electrical Power (TCEP). These “gross” figures (Figure 3) are of interest to chassis designers and manufacturers, being very similar to those “net” figures based on Total Payload Power (TPP). System Integrators are primarily concerned with net payload TPP figures. Figure 4 shows an example ATR product that supports sealed systems up to 450W.

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For more information: 34

COTS Journal | July 2014


Figure 5 Charted here is payload MTBF degradation vs. increasing system Total Payload Power (TPP).

Chassis Effects on Payload MTBF It is assumed that for every 10°C rise in electronic devices, MTBF is decreased approximately by half. As chassis payload temperatures increase while in operation, the specified payload MTBF at ambient temperature will be reduced by a factor proportional to ΔT. For military chassis products, it is interesting to determine how many watts of payload power will generate a ΔT increase of 10°C (50% MTBF reduction). This is referred to as “Chassis Half MTBF Power Factor” and can be determined from chassis thermal testing results, or obtained from Chassis Payload Thermal Resistance (CPTR). Chassis Half MTBF Power Factor (CHMPF) = 10°C / Chassis Payload Thermal Resistance (CPTR)). Calculated out CHMPF = 10°C / 0.172°C/W = 58 watts. This PT result indicates that the chassis payload MTBF will be reduced by half

for every 58 watts of payload increase. A classic question from system designers is: Knowing payload MTBF at reference temperature and total system payload power (TPP), what will be the payload’s approximate MTBF (in-service) inside this ATR chassis? The question can be answered using the Chassis Payload MTBF Degradation Coefficient (CPMDC) that calculates the payload’s in-service MTBF reduction factor as: CPMDC = (½) multiplied by (Total Payload Power / Half MTBF Power Factor). Once CPMDC is known, the approximate operating payload MTBF degradation can be determined by the expression: In Service Payload MTBF = Ambient Payload MTBF x CPMDC. System Integrators may be interested in specific chassis payload MTBF figures as shown in Figure 5 (CHMPF-PT = 58W), illustrating the Eurocard’s expected service life (with respect to COTS Journal | July 2014



ambient temperature) vs. increasing chassis payload power dissipation. Referring to the payload MTBF degradation examples, it’s clear that the chassis thermal performance has a dramatic influence on payload Mean Time Between Failures. This emphasizes that selecting military enclosures with increased performance is crucial for system reliability and success. Over-heated systems may operate for a period, but due to extraordinary MTBF reduction, they are expected to fail in the short term.

Payload MTBF Degradation Example A conduction-cooled Eurocard module is specified with MTBF 180,000 hours at 20°C GB (Ground Benign). The module is inserted in an ATR chassis with a Half MTBF Power Factor (CHMPF) of 58 watts. The system Total Payload Power (TPP) is 200 watts. If the system operates at 20°C ambient, the Eurocard’s in service MTBF can be determined by the Chassis Payload MTBF Degradation Coefficient (CPMDC):

Eurocard In Service MTBF = Eurocard Ambient MTBF x CPMDC = 180,000 x 0.0916 = 16,488 hours. Reliability provided by this chassis model may disappoint system integrators. The solution is to migrate the same payload into a higher performance chassis, e.g. with double CHMPF (116 watts), where payload in-service MTBF will become: Eurocard In Service MTBF = 54,486 hours. This higher performance ATR chassis yields far greater payload reliability. Next month this discussion of thermal test procedures is continued in Part 2 of this article. CM Computer Sevilla, Spain +34 95 425 31 16

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OpenVPX Secures Place alongside VME as a Staple in Military Systems OpenVPX has emerged as a natural fit for high-bandwidth, data-intensive military applications. A constantly growing ecosystem of vendors and product choices feeds this strong position VPX now claims. Jeff Child, Editor-in-Chief


hough sprung from the same source community as VME, the VPX standard (VITA 46), or OpenVPX, has come onto the scene with quite a different set of characteristics for system bandwidth and backward compatibility than its VME cousin. That said, VPX isn’t really positioned as a replacement for VME. Rather VPX is decidedly aimed more at high-bandwidth, data-intensive military applications. After years of growing pains, it’s clear now that VPX has won its way to a pretty clear acceptance in the military market. Like its VME predecessor, OpenVPX provides backward compatibility (to OpenVPX) that is so important in the military where program development cycles span many years. Just like with VME, a new VPX board with newer processor, memory and I/O components can easily be dropped into a slot that could be several years old. That means that as vendors continue to roll out new OpenVPX boards, the VPX technology will follow a similar parallel path of tech refresh cycles that VME has enjoyed for decades. VPX revenues were projected by industry analysts to match VME by 2012. This didn’t quite pan out, as the cuts and uncertainty on DoD program spending went on longer than expected. Market analysis from IHS Electronics & Media shows the crossover more likely to occur in 2016 or 2017. 38

COTS Journal | July 2014

Figure 1 Project Missouri demonstrations successfully implemented and tested two data links between an F-22 and the F-35 Cooperative Avionics Test Bed (CAT-B) (shown).

According to the report, the defense sector represents about 80 percent of the revenue for VME and VPX combined. This could be even higher for VPX exclusively, as the defense sector is the primary market for VPX technology. In contrast, just the opposite was the case in the early days of VMEbus: the focus was on industrial, and defense had no interest. The Product Roundup on the next several pages shows representative OpenVPX SBC products. VPX continues to gain design wins in many data-intensive applications where high throughput and high compute density (size) are critical factors. As an example,

recently Curtiss-Wright announced that its Defense Solutions division’s rugged OpenVPX processing and network switch modules contributed to the recent Project Missouri series of test flights at Nellis AFB, NV. These flights were performed by a Lockheed Martin-led industry team, with support from key government agencies, to successfully demonstrate how a true open systems architecture can enable improved interoperability between next generation and legacy fighter aircraft. The demonstration, which was based on the U.S. Air Force’s Open Mission Systems (OMS) standard, successfully implemented and tested two data links between an F-22 and the F-35 Cooperative Avionics Test Bed (CATB) (Figure 1). Technology used in the Project Missouri demonstration included the company’s off-the-shelf OpenVPX standard-based VPX6-187 Power Architecture SBC, VPX61957 Intel Core i7 SBC and VPX6-684 Gigabit Ethernet Switch/Router modules. The open systems architecture implementation on Project Missouri leveraged UCI-related software and development tools from the Air Force’s Common Mission Control Center effort.

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OpenVPX SBC Roundup

3U VPX Blade Marries Core i7 and 8 Gbytes of DRAM ADLINK Technology offers the VPX3000 Series rugged 3U VPX processor blade. The ADLINK VPX3000 Series features the 3rd generation Intel Core i7 processor with Mobile Intel QM77 Express Chipset. The VPX3000 Series provides up to 8 Gbytes of DDR3-1333/1600 dual channel ECC memory soldered on board, one PCI Express x8 XMC.3 site with VITA 46.9 rear I/O and onboard soldered 16 Gbyte SLC SATA solid state drive. The processor blade provides two Gen2 PCI Express x4 (or 1x PCIe x8) to P1 with DMA and NonTransparent Capability. Rear I/O via P1 and P2 includes 1000BASE-T, HD audio (line-in, line-out), 2x SATA 6 Gbits/s, 1x SATA 3 Gbits/s, USB 3.0, USB 2.0, GPIO, VGA, DVI, RS-232 and RS-422. The VPX3000 Series is rugged conduction-cooled with conformal coating and supports VITA 46, VPX REDI 48, OpenVPX VITA 65, as well as VITA 47-2005 environmental specifications. A VPX-R300 Rear Transition Module is available to access rear I/O signals from the VPX3000, and a TBP-VPX3000 Test Backplane supporting three payload slots is available for users to validate VPX3000 functionality. ADLINK Technology San Jose, CA (408) 360-0200

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COTS Journal | July 2014

3U VPX GPGPU Board Aims at C4ISR Aitech Defense Systems released a 3U VPX GPGPU that combines exceptional processing and high data throughput capabilities with a rugged design ideal for C4ISR and advanced sensor processing. Aitech’s new C530 carries the latest industry-standard MXM modules with the ability to easily upgrade to newer modules as they become available. The C530 GPGPU board is currently offered with one of two state-of-the-art MXM modules. The first option is an NVIDIA GeForce GTX 675MX at 600 MHz with 4 Gbytes of GDDR5 memory at 1800 MHz. The other is an AMD Radeon HD 7970M at 850 MHz with 2 Gbytes of GDDR5 memory at 1200 MHz. The multiple format video output channels included as standard on the new C530 enable the board to be used in a variety of rugged signal processing and high resolution graphics requirements. The C530 connects to any Intel-based VPX SBC via a high-speed PCIe Gen 2.0 link using up to 16 lanes over the VPX backplane. The new C530 GPGPU comes in commercial and rugged air-cooled as well as conduction-cooled configurations for severe and harsh environments per VITA 46. Conduction-cooled versions are compliant with VPX-REDI (VITA 48.2). Aitech Defense Systems Chatsworth, CA (888) 248-3248

3U OpenVPX Board Blends PCI Express, Gbit Ethernet and XMC The iVPX7225 from Artesyn Embedded Technologies is an 3U OpenVPX SBC based on the dual-core third generation Intel Core i7 2.5 GHz processor. The iVPX7225 is designed to operate in a wide range of OpenVPX enclosures, including the company’s VPX3000 system platform. Onboard memory includes up to 16 Gbyte DDR3L-1600 memory, embedded USB flash and 1 Mbyte nonvolatile Ferroelectric Random Access Memory (F-RAM). The card offers both PCI Express high-speed data plane fabric connectivity and Gigabit Ethernet control plane connectivity with data transfer rates up to 5 Gbits/s. Additional connectivity includes three USB 2.0 ports, two serial ports, three SATA ports, eight GPIO, DisplayPort, VGA and one XMC site for maximum flexibility. Available as a fully rugged single board computer for extreme environments with extended shock, vibration, temperatures and conduction- or air-cooling, it provides an exceptionally versatile platform for a wide range of High Performance Embedded Computing (HPEC) applications. The iVPX7225 software support includes UEFIcompliant BIOS with password protection and a wide range of operating systems including Wind River VxWorks 6.9 and Linux 3.x. Artesyn Embedded Technologies Tempe, AZ (888) 412-7832


6U OpenVPX Card Has Stratix V FPGAs and Anemone Coprocessors

6U VPX Board Sports 4th Generation Intel Core Processor

3U OpenVPX Module Provides 24-Core QorIQ T4240 CPU

BittWare offers a 6U VPX board powered by Altera’s 28nm Stratix V FPGAs. The S5-6U-VPX (S56X) is a rugged VITA 65 6U VPX card providing a configurable 48port multi-gigabit transceiver interface supporting a variety of protocols, including Serial RapidIO, PCI Express and 10GigE, and two VITA 57 FMC sites for enhancing the board’s I/O and processing capabilities. When combined with the optional BittWare Anemone floating point coprocessors, the board packs a powerful punch for those applications requiring flexible FPGA processing in a rugged form factor. By leveraging the Stratix V GS FPGA’s floating point DSP blocks, which deliver up to one TeraFLOP of computing performance, combined with the FPGA’s low-power, multi-gigabit transceivers and a high-density, high-performance architecture, BittWare’s S56X board delivers a rugged and completely flexible signal processing solution capable of driving innovative new capabilities in military applications. The board also sports an 800 MHz ARM Cortex-A8 control processor and two Anemone floating point coprocessors (optional). I/O includes 48 multi-gigabit transceivers along with GigE, SerDes, LVDS and RS-232 links. Up to 8 Gbytes of onboard DDR3 memory are also included.

Concurrent Technologies’ latest 6U VPX processor board is based on the 4th generation Intel Core processor family (previously codenamed “Haswell”). The VR E1x/msd is a 6U VPX board featuring either the quad-core Intel Core i7-4700EQ processor or the dual core Intel Core i5-4400E processor, together with the associated mobile Intel QM87 Express chipset. With up to 32 Gbytes of DRAM and a rich assortment of I/O interfaces, this board is an ideal processor board for 6U VPX solutions requiring the latest in processing performance. Additional features include 4 x SATA600 mass storage interfaces including an onboard SATA 600 HDD/SSD site, onboard CompactFlash site, serial, USB, GPIO and GPI interfaces, Gigabit Ethernet ports, graphics and stereo audio interfaces. The wide range of I/O interfaces can be further expanded by the addition of one or two XMC/PMC modules. The board supports a configurable control plane fabric interface (VITA 46.6) and a flexible PCI Express (PCIe) data plane fabric interface (VITA 46.4) supporting up to Gen 3 data rates and is compatible with several OpenVPX profiles.

A 3U OpenVPX single board computer in a compact, rugged form factor is targeted for extremely challenging applications that require very high performance, both in I/O and computation. The RIOV-2440 from Creative Electronic Systems features the Freescale QorIQ T Series T4240 communications processor, with 12 dualthreaded cores supporting 24 virtual cores. Processor I/O configuration options include the T4240 processor’s PCIe, SRIO, GbE, 10GbE and SATA II ports. It is compatible with most OpenVPX payload slot profiles. The RIOV-2440 provides easy access to the essential I/O on the front panel, as well as complete connectivity on the backplane. Various rear transition modules (RTMs) are available to access the wide range of I/O and debug signals. An Advanced Board Management Controller (aBMC) is implemented for VITA 46.11 support, configuration management, event logging and other supporting tasks. It is fully compatible with the CES Configuration, Load and Monitor (CLM) tool.

BittWare Concord, NH (603) 226-0404

Concurrent Technologies Woburn, MA (781) 933-5900

Creative Electronic Systems Geneva, Switzerland +41 (0)22 884 51 00

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COTS Journal | July 2014



6U OpenVPX Blade Boasts Dual Xeon Processor Sockets

VPX Single Board Computer Sports Low-Power ARM Processing

Xeon Quad-Core 6U VPX SBC Includes Ethernet Switch

The 3220Q from CSPI is a rugged, high-performance 6U OpenVPX Blade with a dual socket Intel Xeon processor and QuickPath Interconnect (QPI) to deliver superior performance-per-watt and low latency. Operating as a general purpose compute engine, it is one of the fundamental building blocks in the CSPI TeraXP family of Embedded Servers. The 3220Q supports Red Hat Enterprise MRG delivering real-time capabilities and highspeed messaging in a commercial off-theshelf (COTS) Linux-based operating system. Featuring an Open Software Stack (OpenMPI/OFED, AMQP) and a Converged Fabric (supporting FDR InfiniBand, 10/40GbE, Fibre Channel), the TeraXP Embedded Servers provide the scalable processing power and I/O bandwidth needed for embedded military computing applications such as radar, sonar, digital signal processing, command and control, and ISR. The board’s processor is a QuadCore 45nm Intel 2.13 GHz Xeon LC5528 interconnected via 4.8 GT/s QPI. Two Banks of DDR3-1066 ECC memory provide 8 Gbytes of memory per socket. Two independent 64 Mbit SPI flash memory devices are on board along with one USB 2.0 port and an Ethernet RJ45 jack.

Curtiss-Wright announced that its Defense Solutions division has introduced the first member of its new family of rugged ARM-based COTS processing modules. The VPX3-1701 is a 3U VPX SBC based on a CPU that features dual 1 GHz ARM processors. This cost-effective, low-power small form factor SBC is rated at less than 15W maximum power dissipation. The VPX3-1701 delivers the benefits of ARM technology to system designers today while providing a path to technology insertion with pin-compatible, higher-performance Curtiss-Wright ARM SBCs to follow. The VPX3-1701’s integral high-speed backplane and XMC connectivity enable multi-Gbyte/s data flows from board to board through the backplane interface and from the backplane to its onboard XMC site to support the acquisition, processing and distribution of sensor data for demanding C4ISR applications such as video, radar and sonar data processing. The new small form factor VPX3-1701 provides similar I/O interfaces and pincompatibility with Curtiss-Wright’s other popular 3U VPX SBCs, including the Power Architecture-based VPX3-131 and VPX3133 and the Intel-based VPX3-1257. The compact, lightweight VPX-1701 is ideal for technology refresh applications.

A rugged, high-performance 6U VPX (VITA 46) SBC features a quadcore Intel L5408 Xeon processor and integrated 10 Gigabit Ethernet switch to support full-mesh backplane data layer interconnectivity for up to eight SBCs integrated into a single chassis. Available in air-cooled or conduction-cooled formats, the CPU-111-10 from Dynatem conforms to the OpenVPX (VITA 65) payload module profile MOD6-PAY-4F2T- with four fat pipes (10 GBase-BX4) and two thin pipes (1000Base-T). The CPU-111-10 serves as a suitable open-architecture building block for next-generation command, control, communications, computers, intelligence, surveillance and reconnaissance (C4ISR) applications on board (un)manned air / ground vehicles and shipboard platforms. Standard onboard I/O resources include up to 8x 10 Gigabit Ethernet, 2x 1 Gigabit Ethernet, 4x SATA, 2x USB 2.0, 1x RS232/485 and 1x VGA video ports. Dual XMC / PMC expansion module sites enable additional I/O expansion, including 10G XAUI lanes from each XMC card to the 10G switched fabric. Offered in both convectioncooled and ruggedized conduction-cooled variants, the CPU-111-10 is designed for use with ANSI/VITA 46 1.0” pitch VPX form factor backplanes.

CSPI Billerica, MA (800) 325-3110

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COTS Journal | July 2014

Curtiss-Wright Controls Defense Solutions Ashburn, VA (703) 779-7800

Dynatem Mission Viejo, CA (800) 543-3830


3U OpenVPX REDI SBC Serves Up QorIQ T2080 Processor.

3U VPX SBC Features 4th Gen ‘Haswell’ Quad Core technology

Core i7 OpenVPX Board Features Rich Set of I/O

The XPedite5970 from Extreme Engineering Solutions is a 3U OpenVPX REDI single board computer based on the Freescale QorIQ T2080 processor. The XPedite5970 provides a rugged, featurerich processing solution that maximizes the performance-per-watt capabilities of a PowerPC-based processor module. The T2080 processor offers eight virtual ( four dual-threaded) e6500 cores, running at up to 1.8 GHz, and integrates a 128-bit AltiVec technology-based SIMD engine per core. The integrated AltiVec SIMD engines enable the XPedite5970 to support DSPlevel floating-point performance and an extensive inventory of software libraries. The XPedite5970 also supports up to 8 Gbytes of DDR3-1600 SDRAM and provides a plethora of I/O options to the backplane, including 10 Gbit Ethernet, Gen3 PCIe and Gen2 SRIO. The XPedite5970 provides superior growth and expansion capabilities by including an XMC or PMC site with full 10 mm I/O envelope support while maintaining a 0.8-inch VPX slot pitch, providing the system integrator with a wide variety of COTS options for additional I/O, storage, or processing while minimizing total system SWaP-C. Wind River VxWorks, Linux and Green Hills INTEGRITY Board Support Packages (BSPs) are available.

GE Intelligent Platforms has announced the SBC346 Rugged 3U VPX Single Board Computer. Based on 4th Generation Intel Core i7 (‘Haswell’) quad core technology, it offers significantly higher levels of performance than its predecessor while maintaining the same SWaP (size, weight and power) characteristics. The SBC346 offers a x16 PCI Express link (Gen3-capable) for maximum bandwidth to highperformance peripherals such as GPGPUs, or for multiple high-bandwidth links to multiple peripherals using a combination of x4 and x8 PCI Express ports. The SBC346 is also pin-compatible with the PCI Express and I/O configuration of earlier 3U VPX single board computers from GE, in line with the company’s commitment to maximizing the long-term value of customer investments, making it a straightforward, cost-effective upgrade/ technology insertion opportunity for programs needing increased processing power without impacting the SWaP envelope. Up to 16 Gbytes of memory is supported by the SBC346. I/O includes up to three Gigabit Ethernet ports; a VGA port; two SATA 6 Gbit/s ports; two COM ports; up to three USB 2.0 ports; audio (on some build variants) and up to eight GPIO pins.

The VPXCB1002 “Sparrow” is an Intel fourth-generation Core i7 OpenVPX SBC module from General Micro Systems (GMS). This ruggedized and conduction-cooled VPX module operates up to -40° to +85°C. Utilizing OpenVPX 3U specifications, the card is fully compliant to VITA 46/47/48. The Sparrow supports the latest Intel Core i7 processor with up to four physical CPU cores with Hyper-Threading for total of 8 logical cores, each operating at up to 2.4 GHz with the ability to TurboBoost up to 3.4 GHz. This is coupled with up to 32 Gbytes of RAM organized in two banks, supporting Error Correcting Code (ECC). The ECC RAM provides 2-bit error detection and 1-bit error correction, and supports up to 1600 Mega Transfers per Second (MTS) between CPU and memory. The I/O subsystem for the Sparrow is designed to support a wide array of standard and custom I/O functions. The VPXCB1002 standard configuration supports four independent Gigabit Ethernet channels with MAC/PHY/ Magnetics with TCP/IP Offloading Engine (TOE) to VPX-P1, two USB 3.0 and two USB 2.0 with power, up to two COM ports with Handshaking, one 6 Gbit/s eSATA port, two x1 lane PCI Express, four buffered digital I/O lines with interrupt capabilities, and three Display Port for video.

Extreme Engineering Solutions Middleton, WI (608) 833-1155

GE Intelligent Platforms Charlottesville, VA (800) 368-2738

General Micro Systems Rancho Cucamonga, CA (909) 980-4863

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COTS Journal | July 2014



3U OpenVPX Virtex-6 FPGA Board Features FMC Site

3U VPX Board Has Quad-Core Freescale QorIQ CPU

OpenVPX SBC Provides SMP Using Dual 10-Core Xeon Processors

A 3U OpenVPX front-end processing board boasts a flexible Virtex-6 FPGA and an FMC site (VITA 57.1). The IC-FEP-VPX3b from Interface Concept is suitable for applications such as radar, sonar, electronic warfare, imaging and communications. The FMC site, being VITA 57.1-compliant, interconnects ADC, DAC, general I/Os, video, Serial FPDP cards, or additional FPGA FMC modules. In terms of processing unit, the board, based on a Xilinx Virtex-6 FPGA, offers two banks of 40-bit 1.25 Gbyte DDR3 memory and a Spartan-6 control node. Complying with the VPX standard, the IC-FEP-VPX3b features four 4-lane fabric ports on the P1 and general-purpose I/Os (on P2). The board is available in standard, rugged and conduction-cooled grades and comes with the Xilinx ISE design tool. The IC-FEP-VPX3b is compliant with the several OpenVPX profiles (VITA 65). The company’s FPGA boards could be delivered with a firmware demonstrating all the capabilities and performance of the boards. The aim of these packages is to accelerate the design cycle and enable FPGA designers to spend less time developing the infrastructure and to focus on their valueadd design.

The Kontron 3U VPX processor board VX3240 features the new, power-optimized Freescale P2041 QorIQ quad-core processor. The headless VPX design has four 1.2 GHz Power Architecture e500mc cores. Its wide range of I/Os, including Gigabit Ethernet, GPIOs, USB, SATA and serial interfaces, simplifies integration in new, dataintensive, low-power system designs. The Kontron VX3240 is based on the 1.2 GHz quad-core Freescale QorIQ P2041 processor with up to 8 Gbyte soldered DDR-3 SDRAM. An optional XMC/PMC slot enables application-specific customization by adding specialized PCIe- or PCI-based expansion boards, saving a valuable system slot. Additional VPX boards can be connected over the backplane via four PCI Express lanes. For networking and peripherals there are two Gigabit Ethernet ports, two USB 2.0, two serial interfaces and six GPIOs. Storage media are connected via one SATA 2 port over the backplane. An onboard soldered SATA NAND-Flash up to 32 Gbyte is optionally available to host OS and application code for a rugged and space-saving system layout in missioncritical applications. The new Kontron VX3240 is available with standard aircooling or conduction-cooling operating at an extended temperature range of -40° to +85°C.

Mercury Systems offers the Ensemble HDS6602 High Density Server. According to the company, the board is the only embedded, dual Intel Xeon processor E52600 v2-based processing module able to deliver peak Symmetric Multi-Processing (SMP) performance of 608 Glops. Using Mellanox’s ConnectX-3 technology to exploit InfiniBand or Ethernet as a highperformance interconnect in OpenVPX, the HDS6602 is well suited to meet the processing demands of the most complex Radar and other massively intensive embedded processing applications. Powered by two 10-core Intel Xeon processors E5-2648L v2 running at 1.9 GHz and supporting up to 128 Gbytes of memory, this 6U addition to Mercury’s Ensemble series of sensor chain building blocks offers a lot of processing power into a standard, 1-inch pitch OpenVPX module. Onboard Gen 3 PCIe pipes feed the data plane with either 40 Gbit/s Ethernet (TCP/IP and Sockets) or DDR/QDR/ FDR10 InfiniBand (OpenMPI and OFED) via two Mellanox ConnectX-3 bridges. Air Flow-By technology more efficiently cools the HDS6602, enabling full-throttle processing. Air Flow-By delivers the most efficient cooling available while providing environmental isolation for the module from moisture, liquids and dust.

Kontron Poway, CA (858) 677-0877

Mercury Systems Chelmsford, MA (978) 967-1401

Interface Concept Briec de l’Odet, France +33 (0)2 98 57 30 30

FIND the products featured in this section and more at


COTS Journal | July 2014


FIND the products featured in this section and more at


Rugged System Blends Secure Virtual Machines, Ethernet Switching and RAID Storage General Micro Systems (GMS) has introduced the industry’s first conduction-cooled, fully ruggedized, Secure Virtual Machine (SVM) server with six hardware independent I/O modules. Designed to replace multiple workstations using virtual machine technology, Tarantula (SO302 4-in1) incorporates an enterprise-level Layer 2 or Layer 3 intelligent switch for high-speed connectivity. Tarantula is well suited for applications requiring ultra-efficient information sharing between several computers serving varied purposes. Intel’s Xeon processor, the Ivy-Bridge-EP, is the host CPU driver and features 10 physical cores each operating up to 2.4 GHz, with the ability to TurboBoost to 3.0 GHz. Support for hyperthreading expands its capability to 20 logical cores. Tarantula dynamically allocates these cores in real time as needed by each of up to six virtual machines and their individual application requirements. The host CPU supports one 4-lane PCIe XMC site, one 10 Gigabit Ethernet port, four USB 3.0 and two USB 2.0 ports with power, two serial ports with RS-232/422/485 buffers, full HD-Audio, and eight general purpose I/O lines. Tarantula’s intelligent Gigabit Ethernet switch functions are powered by a 416 MHz MIPS CPU (with 128 Mbytes of DRAM) that controls the (up to) 18 Gbit Ethernet ports and a second 10 Gigabit Ethernet port, which comes with the option of copper or fiber. The CPU is loaded with up to 128 Gbytes of RAM. In addition to many standard and unique host system I/O features like USB 3.0, serial ports and XMC site, Tarantula incorporates one storage RAID controller and one Auxiliary Power Unit (APU), each housed in a removable canister for quick replacement. The storage unit secures up to eight 2 Terabyte SATA SSD drives (16 Tbytes total) in one canister for easy removal and quick transfer of critical data. Tarantula is compliant to MIL-STD 810-G, MIL-STD 1275D, MIL-STD 461E, MIL-S 901D, DO-160D and IP66. It is available in quantity starting at $28,000. General Micro Systems, Rancho Cucamonga, CA. (909) 980-4863.

2U Rackmount Platform Serves up Haswell Core i7/i5/i3 Processor

2.5 GSPS D/A Converter Functionality Meets FMC Format

WIN Enterprises has announced the PL-10480, a 2U rackmounted platform designed for network service applications. PL-10480 supports the Intel 22nm Haswell Core i3/i5/i7 or E31200V3 processors and uses the Intel extended-life Embedded IA versions of these components to enable long OEM product life. The 2U platform supports four DIMM sockets with a maximum capacity of 32 Gbytes. Storage interfaces include one 2.5-inch SATA HDD and CompactFlash. The PL-10480 supports one PCIe x4 expansion slot and comes standard with 2 GbE LAN expandable to a maximum of 48 GbE Ethernet ports accessible from the front-panel. The front panel also features one USB 2.0 port, one RJ-45 console port and LED indicators that monitor power and storage device activities.

VadaTech offers a Digital-to-Analog Converter (DAC) in the FPGA Mezzanine Card (FMC) format. The high-speed DAC offers 14-bit at 2.5 Giga samples per second (GSPS). The FMC223 features a TRIG Out, CLK In and Analog Out, along with a Multi-IO LVDS connector and status LEDs on the front panel. The FMC conforms to the latest VITA 57 specifications. The mezzanine offers 8, 16, 32 or 72 QAM for amplitude modulation. An RF PLL (Phased Locked Loop) synthesizer provides enhanced linearity and band flatness performance. The company offers FMCs in three types: networking interface, A/D and D/A conversion, and RF modules. The company also provides the full Xilinx suite of FPGA carriers and several Altera-based designs.

WIN Enterprises, North Andover, MA. (978) 688-2000.

Vadatech, Henderson, NV. (702) 896-3337.

40G ATCA Product Family Boasts Futureproof Capabilities Asis has announced the availability of MaXum, its future-proof 40G product line. The MaXum product line was designed to support more than two blade generations through its unique expandability features. This 14-slot expandable chassis offers the ability to easily scale its cooling and electrical power capacity through the addition of removable fan and AC power trays. The chassis offer multiple interchangeable configurations for every need: A real-estate efficient 13U/14-slot with pull cooling of 350W per slot; an energy-efficient 14U/14-slot with pull cooling of 435W per slot; and a powerful 14U/14-slot with pressurized push pull cooling of 500W-600W per slot. The interchangeable AC/DC solution allows system vendors to ship both versions of the same product and even move a chassis from a DC environment to an AC environment without special integration. The product line also includes a mid-sized ATCA (6-slot) chassis with front-to-back airflow cooling of 400W blades. This new form factor opens new opportunities for system integrators to provide a more efficiently sized enclosure without being restricted by compatibility constraints. Another product is the Intera, a dedicated small-sized switch card slot that is located in the chassis itself, freeing up to two additional payload slots for significantly greater processing power. FIND the products featured in this section and more at


COTS Journal | July 2014

Asis, Pittsburgh PA. (412) 275-6700.


AFFORDABLE MISSION SUCCESS: MEETING THE CHALLENGE Oct. 6–8, 2014 Baltimore Convention Center The premier international conference and exposition for military communications, MILCOM 2014 showcases the technical innovations and creative talents of military, academic and industry leaders. Attendees will experience an in-depth technical program with industry exhibits, panel discussions and tutorials, which are eligible for continuing education units. Technical tracks and topics include: Cyber Security and Trusted Computing Waveforms and Signal Processing Networking: Architectures, Management, Protocols and Performance System Perspectives Selected Topics in Communications


ADVERTISERS INDEX GET CONNECTED WITH INTELLIGENT SYSTEMS SOURCE AND PURCHASABLE SOLUTIONS NOW Intelligent Systems Source is a new resource that gives you the power to compare, review and even purchase embedded computing products intelligently. To help you research SBCs, SOMs, COMs, Systems, or I/O boards, the Intelligent Systems Source website provides products, articles, and whitepapers from industry leading manufacturers---and it's even connected to the top 5 distributors. Go to Intelligent Systems Source now so you can start to locate, compare, and purchase the correct product for your needs.


Company Page# Website

Company Page# Website

Acromag..............................................22........................... Ballard Technology, Inc........................5........................ Calex Manufacturing Co., Inc. ............36................................. Creative Electronic Curtiss-Wright, Corp...........................45.................... Extreme Engineering GE Intelligent Harting................................................14...................... Innovative Intelligent Systems Source...................4... Interface LCR Embedded Systems, Inc...............28........ Mercury Systems, Inc. Milcom 2014.......................................47...............................

Mobile North Atlantic Industries.................. 19,21................................. One Stop Systems, Inc. .................... 37,49.............. Pelican Products, Inc..........................52............... Pentek, Phoenix International Systems, Inc. Pico Electronics, RTD Embedded Technologies, Inc. SIE Computing SynQor, Inc..........................................23............................... Tadiran Batteries................................13........................ TE Connectivity Ltd.............................29.............................................. TeleCommunication Systems, Trenton Systems, Inc. .........................33.................

COTS Journal (ISSN#1526-4653) is published monthly at 905 Calle Amanecer, Suite 250, San Clemente, CA 92673. Periodicals Class postage paid at San Clemente and additional mailing offices. POSTMASTER: Send address changes to COTS Journal, 905 Calle Amanecer, Ste. 250, San Clemente, CA 92673.

COMING NEXT MONTH Special Feature: Marrying Development Systems to Deployable Solutions

System Development: Space-Qualified Electronics and Subsystems

With budgets and schedules more compressed than ever, the pressure is on to move from development to deployment as smoothly as possible. An ability to do so can make or break the chances of a contract win—especially when complete working demos are often the requirement. Addressing this issue, a number of box-level system developers have crafted development systems designed specifically to be aligned with the all the same key aspects of the final deployed system. Articles in this section explore this trend and how it eases the path from development to system deployment.

With the Space Shuttle program no more and the commercial space industry taking the baton, the space electronics industry is in a period of transition. Feeding those systems, space-based semiconductors and board-level systems must be capable of withstanding everything from intense radiation due to highenergy atoms to bombardments from neutrons and other particles. Articles in this section explore the radiation concerns facing space designers, and update readers on radiation-hardened boards and subsystems as well as ASICs, FPGAs and power components designed for those applications.

Tech Recon: Rugged Laptops, Workstations and Tablets as Military User Interfaces

Tech Focus: COM and COM Express Boards

Today’s networked military has a multitude of platforms that require sophisticated graphical user interfaces. Often in the form of rugged laptops, workstations and display systems, and even rugged tablets, these interfaces are how the warfighter gets the complex situational awareness data—maps, video, images and text—it requires and how they interface directly to military weapons platforms on networks. This section explores the technology trends and capabilities of these mission-critical products. 48

COTS Journal | July May 2014 2014

The Computer-on-Module (COM) concept has found a solid and growing foothold in military embedded systems. COM Express adds high-speed fabric interconnects to the mix. COM boards provide a complete computing core that can be upgraded when needed, leaving the application-specific I/O on the baseboard. This Tech Focus section updates readers on these trends and provides a product album of representative COM and COM Express products.



XMC 10-Gigabit Ethernet Interface Modules

User-Configurable Kintex®-7 FPGA Modules

• XMC-6280 with quad SFP+ copper/fibre ports •X  MC-6260-CC with dual XAUI ports •P  CIe Gen 2 x8 high-speed serial interface •A  SIC provides full offload support for TCP, UDP, iSCSI, FCoE •T  raffic filtering and management

• Two versions: high-speed serial I/O and AXM I/O • Reconfigurable Xilinx© Kintex®-7 FPGA with 325k or 410k logic cells • Quad DDR3 SDRAM 128M x 64-bit • 32M x 16-bit parallel flash memory for MicroBlaze™ FPGA program code storage • 8-lane high-speed serial interface for PCIe Gen 2



Phone: (877) 295-7084 Fax: (248) 624-9234 Email: Web:

Phone: (877) 295-7084 Fax: (248) 624-9234 Email: Web:



XMC-SIO4BX Four Channel High Performance Serial I/O XMC Card • One Lane XMC Interface • Four Independent Multi-Protocol Serial Channels • Serial Mode Protocols include Asynchronous, Monosync, Bisync, SDLC, HDLC, Nine-Bit, and IEEE 802.3 • Synchronous Serial Data Rates up to 10Mbps • Asynchronous Serial Data Rates up to 1Mbps • Independent Transmit and Receive FIFOs for each channel - 32K byte each • Multiprotocol Transceivers support RS422 (V.11)/ RS485, RS423 (V.10), RS232 (V.28), V.35, and RS530

General Standards Corporation Phone: (256) 880-8787 Email: Web:

expansion enclosures

Choose from a variety of options: ExpressCard, PCIe, or Thunderbolt connectivity package

1, 2, 3, 5, or 8 slots

Full-length (13.25”), mid-length (9.5” ), or short card (7.5” )

Half-height or full-height cards

36W, 180W, 400W, 550W or 1100W power supply


Flexible and Versatile: Supports any combination of Flash drives, video, lm editing, GPU’s, and other PCIe I/O cards. The CUBE, The mCUBE, and The nanoCUBE are trademarks of One Stop Systems, Inc. and the logo are trademarks of One Stop Systems, Inc. Thunderbolt and the Thunderbolt logo are trademarks of the Intel Corporation in the U.S. and other countries.

COTS Journal | July 2014


COTS Journal’s

MARCHING TO THE NUMBERS 550 kilometers $9 MILLION Range up to which the JLENS radar can detect and target threat objects. The U.S. Army has placed blimp-borne radar in strategic readiness, and Raytheon has completed preparing JLENS radar for contingency deployment. Joint Land Attack Cruise Missile Defense Elevated Netted Sensor System, or JLENS, is a powerful airborne radar system that floats at altitudes as high as 10,000 feet, suspended from two 80-yard-long, helium-filled blimp-like aerostats that are tethered to ground stations via a rugged cable.

LESS THAN 2 METERS Area from target within which Raytheon’s Excalibur consistently strikes. In a company-funded R&D initiative, Raytheon successfully fired the dual-mode GPS- and laser-guided Excalibur S for the first time. Although the Excalibur S was initialized with a GPS target location, it scored a direct hit on a different, or offset, target after being terminally guided with a laser designator. The new variant incorporates a laser spot tracker (LST) into the combat-proven Excalibur Ib projectile, the world’s most precise GPS guided 155mm artillery projectile now in production.


Time since the launch of the first Milstar satellite in February 1994. There’s now a constellation of satellites made up of five Milstar and three Advanced Extremely High Frequency (AEHF) satellites, all communicating with each other via satellite-to-satellite crosslinks. Northrop Grumman announced that its protected communications payload for the U.S. Air Force’s third AEHF satellite has completed on orbit testing ahead of schedule without any discrepancies. 50

COTS Journal | July 2014

Size of most recent order Kopin has received for display modules in support of the U.S. Army’s Thermal Weapon Sight (TWS) program. The new order calls for the immediate delivery of Kopin’s VGA-resolution display modules, with continued production over the next nine months. The company’s overlay display systems for smart weapon sights can deliver brightness in excess of 5,000 ft-Lambert (or about 17,000 nits) for bright daytime use or very low brightness of 0.01 ft-Lambert for totally dark environments


Length of time BAE Systems has done concept development in support of its recent submission of its highly survivable low-risk solution for the U.S. Army’s Armored MultiPurpose Vehicle (AMPV) competition. The company’s offering addresses the critical need to replace the Vietnam-era M113. BAE Systems’ AMPV capitalizes on the proven Bradley and Paladin designs. The Army plans to award an initial contract for the 52-month engineering manufacturing and development phase in January 2015.

Module and System-Level Solutions from Intel® and Freescale™ Single Board Computers


4th Gen Intel® Core™ i7-based 3U VPX SBC with XMC/PMC


Freescale QorIQ T4240-based 6U VPX SBC with dual XMC/PMC

Secure Ethernet Switches and IP Routers


Secure Gigabit Ethernet router XMC utilizing Cisco™ IOS®


3U VPX 10 Gigabit Ethernet managed switch and router

High-Performance FPGA and I/O Modules


Xilinx Virtex-7 FPGA-based XMC with high-throughput DAC

High-Capacity Power Supplies


3U VPX 300W power supply with EMI filtering for MIL-STD-704 & 1275

Rugged, SWaP-Optimized, COTS-Based Systems


Sub-½ ATR, 6x 3U VPX slot system with removable SSDs


SFF 2x 3U VPX system with removable SSD and integrated power supply


SFF Intel® Core™ i7 or Freescale QorIQ-based system with XMC/PMC

Extreme Engineering Solutions 608.833.1155

Designed, manufactured, and supported in the USA


Use of the military image does not imply or constitute Department of Defense endorsement.




Custom cases created by Pelican-Hardigg Advanced Case Solutions™ (ACS) provide Mission Critical confidence using a four-stage process of analysis, design, testing and manufacturing. From technical prototypes to sensitive military electronics – ACS has the experience and resources to guarantee performance. When failure is not an option, an Authentic ACS solution is the answer.

Pelican Products, Inc. 23215 Early Avenue, Torrance, CA 90505

877.619.4637 (TOLL FREE) sTel 310.326.4700 sFax 310.326.3311 s

All trademarks are registered and/or unregistered trademarks of Pelican Products, Inc., its subsidiaries and/or affiliates.

COTS Journal  

July 2014

COTS Journal  

July 2014