Tech Focus: Test and
Instrumentation Boards Roundup
The Journal of Military Electronics & Computing
DoD UAV D E INTEGRAT ROADMAP WITH THIS ISSUE
PLUS: ATCA Sets Sights on Navy Modernization Needs
— Volume 13 Number 10 October 2011
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Training/Simulation Tech Steps Up to New Levels of Detail
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The Journal of Military Electronics & Computing
COTS (kots), n. 1. Commercial off-the-shelf. Terminology popularized in 1994 within U.S. DoD by SECDEF Wm. Perry’s “Perry Memo” that changed military industry purchasing and design guidelines, making Mil-Specs acceptable only by waiver. COTS is generally defined for technology, goods and services as: a) using commercial business practices and specifications, b) not developed under government funding, c) offered for sale to the general market, d) still must meet the program ORD. 2. Commercial business practices include the accepted practice of customerpaid minor modification to standard COTS products to meet the customer’s unique requirements. —Ant. When applied to the procurement of electronics for the U.S. Military, COTS is a procurement philosophy and does not imply commercial, office environment or any other durability grade. E.g., rad-hard components designed and offered for sale to the general market are COTS if they were developed by the company and not under government funding.
VME and VPX FPGA Processing Advances Target Radar and SIGINT Needs
CONTENTS October 2011
SPECIAL FEATURE FPGA Processing for Radar and SIGINT Systems
Departments 6 Publisher’s Notebook Change and How to Capitalize on It 8
The Inside Track
10 VME and VPX FPGA Processing Advances Target Radar and SIGINT Needs
16 FPGAs Pave New Processing Paths for VPX and VME Systems
Editorial Pondering the Steve Jobs Legacy
Rodger Hosking, Pentek
24 VPX Cabling Solutions from Prototyping to Deployment Justin Moll, Elma Bustronic, and Jason Lippincott, Maritec
30 Roadmap Approach Eases Technology Readiness Challenges Mike Macpherson, Curtiss-Wright Controls Embedded Computing
34 FPGAs Inject New Levels of Flexibility into Military SBCs
Coming in November See Page 80
Susan Wooley, Micro/sys
TECH RECON Technology Trends for Navy Modernization
44 Form, Fit and Function Make ATCA Right for Navy Modernization John Long, RadiSys
SYSTEM DEVELOPMENT Training and Simulation Technology
50 Training and Simulation Systems Advance to New Realism Levels Jeff Child
56 Virtual Simulation Enhances Military Maintenance Training Josie Sutcliffe, NGRAIN
TECHNOLOGY FOCUS Test and Instrumentation Boards
64 Test and Instrumentation Boards Offer Highly Integrated Solutions Jeff Child
Test and Instrumentation Boards Roundup Digital subscriptions available: cotsjournalonline.com
On The Cover: The E-2D Advanced version of the Hawkeye aircraft features an entirely new avionics suite, including the new APY-9 radar, radio suite, mission computer, integrated satellite communications capability, flight management system, improved engines, and an advanced “glass” cockpit. The APY-9 radar features an Active Electronically Scanned Array, which adds electronic scanning to the mechanical rotation of the radar in its radome. (Image courtesy of Northrop Grumman)
U.S. Postal Service Statement of Ownership, Management and Circulation Required by 39 USC 3685. 1) Title of Publication: COTS Journal. 2) Publication Number 1526-4653. 3) Filing Date 10/01/2011. 4) Frequency of issue is monthly. 5) Number of issues published annually: 12. 6) Annual subscription price: n/a. 7) Complete Mailing Address of Known Offices of Publication: The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County. 8) Complete Mailing Address of Headquarters of General Office of Publisher: The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, California. 9) Publisher: John Reardon, The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, CA 92673. Editor: Jeff Child, 20A Northwest Blvd., PMB#137, Nashua, NH 03063. Managing Editor: Sandra Sillion: The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County, CA 92673. 10) Owners: John Reardon, Zoltan Hunor. The RTC Group; 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Orange County. 11) Known Bondholders Holding 1 Percent or More of Total Amount of Bonds, Mortgages, or Other Securities: None. 12) Tax Status: The purpose, function, and nonprofit status of this organization and the exempt status for federal income tax purposes have not changed during the preceding 12 months. 13) Publication Title: COTS Journal. 14) Issue date for Circulation data: 9/1/2011. 15a) Extent and Nature of Circulation: average number of copies each issue during preceding 12 months (Net press run): 20,417. Number copies of single issue published nearest to filing date: (net press run) 20,001 15b) 1. Paid/requested outside-county mail subscriptions stated on form 3541. (Include advertiser¹s proof and exchange copies)/Average number copies each issue during preceding 12 months: 19,255; number copies of single issue published nearest to filing date: 19,292. b)2. Paid in-county subscriptions (include advertiser¹s proof and exchange copies)/average number copies each issue during preceding 12 months/number copies of single issue published nearest to filing date: n/a. b)3. Sales through dealers and carriers, street vendors, counter sales and other non-USPS paid distribution/average number copies each issue during preceding 12 months: n/a, number copies of single issue published nearest to filing date: n/a. b)4. Other classes mailed through the USPS/average number copies each issue during preceding 12 months: n/a, number copies of single issue published nearest to filing date: n/a. c) Total paid and/or requested circulation [sum of 15c. (1), (2), (3) average number copies each issue during preceding 12 months: 19,255 number copies of single issue published nearest to filing date: 19,292. d) Free distribution outside of the mail (carriers or other means)/ average number copies each issue during preceding 12 months: 1141; number copies of single issue published nearest to filing date: 674. e) Total free distribution (sum of 15d. and 15e.)/ average number copies each issue during preceding 12 months: 1141, number copies of single issue published nearest to filing date: 674. f) Total distribution (sum of 15 c and15e)/ average number copies each issue during preceding 12 months: 20,396 number copies of single issue published nearest to filing date: 19,966. g) Copies not distributed/ average number copies each issue during preceding 12 months: 21, number copies of single issue published nearest to filing date: 35. h) Total (sum of 15g and h)/ average number copies each issue during preceding 12 months: 20,417, number copies of single issue published nearest to filing date: 20,001. i) Percent paid and/or requested circulation (15c divided by 15g times 100)/ average number copies each issue during preceding 12 months: 94.4%, number copies of single issue published nearest to filing date: 96.6% 16. Publication of statement of ownership. Publication will be printed in October issue of this publication. 17) Signature and title of the editor, publisher, business manager or owner: Sandra Sillion (Managing Editor), Date: 10/01/2011. I certify that all information furnished on this form is true and complete. I understand that anyone who furnishes false or misleading information on this form or who omits material or information requested on the form may be subjected to criminal sanctions (including fines and imprisonment)and/or civil sanctions(including multiple damages and civil penalties). Sandra Sillion Managing Editor
[ 4 ] COTS Journal October 2011
The Journal of Military Electronics & Computing
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COTS Journal HOME OFFICE The RTC Group, 905 Calle Amanecer, Suite 250, San Clemente, CA 92673 Phone: (949) 226-2000 Fax: (949) 226-2050, www.rtcgroup.com Editorial office Jeff Child, Editor-in-Chief 20A Northwest Blvd., PMB#137, Nashua, NH 03063 Phone: (603) 429-8301 Fax: (603) 424-8122 Published by THE RTC GROUP Copyright 2011, The RTC Group. Printed in the United States. All rights reserved. All related graphics are trademarks of The RTC Group. All other brand and product names are the property of their holders.
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Notebook Change and How to Capitalize on It
’m trying to set the discussion stage for COTS Journal’s annual Analysts Breakfast at this November’s MILCOM 2011 in Baltimore, and keep it from focusing on the Mil budget. Over the last few months, finding people willing to talk about our market has been like pulling teeth. Basing a company’s direction on vague government concepts is difficult, so talking about market direction is all but impossible. Companies also can’t wait. They have to develop a plan and set tasks with the limited visibility available. However, the last thing companies want to do is talk to people like me and state that so far they haven’t figured it out—or something less intelligent like “none of this will affect us.” Eventually someone in government has to determine exactly what they want the military to be or look like for the next ten years. Until that happens we can be intelligent enough to formulate some basic concepts and then try to role-play our industry into those concepts. Let’s work with these three basics: First, there will be less money and how it’s spent will be closely monitored and controlled. Second, a greater use of commercially available technology and products is inevitable. And third, all products will be fielded much quicker than ever before. Each of these three basic premises has advantages and obstacles for our industry. Understandably, primes will want to keep as much business as possible in-house, focusing on where they have strengths, expertise and exclusivity. This opens opportunities for electronics suppliers to provide elements for deliverable systems to primes. They will then integrate these elements—subsystems, boards, modules and so on—with other subsystems for delivery of an entire system to the end user platform. With all that in mind, there are individual issues to determine: like the level of cooperation to invest to partner with primes and other subsystem providers, and deciding how many platforms warrant these types of efforts. Primes are making their own determination of how to best serve the military and their shareholders. Expect to see them have less interest in buying complete subsystems and instead return to buying boards or pre-integrated subsystems. There will also be a return to a demand for solutions that are not over qualified beyond the military’s immediate need—in other words, fewer unrequired bells and whistles included to serve potential future needs. Preintegrated systems will still see growth but the growth in their sophistication will be less not more. There will also be an urgency on the part of primes to get working demos put together as quickly as possible so they can show their customers—the military—a high Technology Readiness Level (TRL) solution. They’ll need the right mix of boards and pre-integration expertise to help them do that. [ 6 ] COTS Journal October 2011
The current and future sophistication and density of silicon has also complicated our industry’s decision making process. On one had there’s the ongoing problem that a majority of the silicon only has an 18-month life cycle. Meanwhile its complexity limits the differentiation that can be performed between module suppliers. Once you make the decision as to whether you use AMD, Intel, Freescale or another processor family, you need to determine how to position your product for market success. Do you just offer a basic product with broad market application potential—perhaps only having price and company reputation as differentiators? Or choose one of two other alternatives. One option is to design a series of products that support one or two exotic interfaces or controls. Another is to design one or two complex products with multiple exotic interfaces and controls. The limited options approach almost mandates designing a product for each potential quote. That’s good if you can do it quickly and you can afford the efforts. The multiple options strategy meanwhile increases a product’s potential application spectrum but elevates the cost of the product—even if the design philosophy allows for component depopulation. Many military deliverable program concepts will have to be smaller in scope and part of a “road map” rather than an “end all” concept that will work for decades. FCS has already experienced this fate. Will JTRS follow? JTRS resolves an absolutely essential need but has been in development for decades and is now just starting to get fielded. The question is how far will JTRS continue to be incorporated and for how long? Is it easier and cheaper to find a way to militarize and secure a smartphone and a tablet concept for the military? This only highlights the evolution of the COTS trend. Decades ago we saw COTS as a necessity to force the use of high-performance commercially available silicon. Today we need to elevate our thought process for COTS even higher to include concepts. Whether we’re willing to accept it or not, our industry uses the concepts developed for gaming in training, simulation, unmanned vehicles and dozens more military applications. All the concepts that are changing faster than we can incorporate them in our personal lives have to be considered for modification and use in the military. This means more opportunities for companies that know the military market and adapt technology. Pete Yeatman, Publisher COTS Journal
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A Sensor Interface and Processing Company
Inside Track Lockheed Martin/Kaman K-MAX Completes U.S. Navy Unmanned Cargo Assessment The Lockheed Martin-led unmanned K-MAX team successfully completed a five-day Quick Reaction Assessment (QRA) for the U.S. Navy’s Cargo Unmanned Aircraft Systems (UAS) program. The autonomous flying K-MAX is designed to resupply Marines on the battlefield and in remote locations. Through various scenarios during QRA, the unmanned K-MAX UAS reportedly performed extremely well, exceeding the cargo delivery objectives of the assessment. The U.S. Navy awarded Lockheed Martin a $45.8 million contract in December 2010 for unmanned K-MAX helicopters to perform in a U.S. Marine Corps evaluation of unmanned cargo resupply. The Navy intends to field a Cargo UAS this fall for a six-month deployment to augment Marine Corps ground and air logistics operations in Afghanistan. A formal report will be released by Commander Operational Test and Evaluation Force (COMOPTEVFOR) 30 days post completion of QRA. Results will be reviewed by Navy and Marine Corps leadership to determine the system’s suitability for deployment. Kaman designed the K-MAX platform, and Lockheed Martin has designed the helicopter’s mission management and control systems to provide the K-MAX with exceptional flight autonomy in remote environments and over long distances.
The autonomous flying K-MAX is designed to resupply Marines on the battlefield and in remote locations.
Lockheed Martin, Bethesda, MD. (301) 897-6000. [www.lockheedmartin.com].
Army Awards CHS-4 Contract to General Dynamics C4 Systems The Army Contracting Command Aberdeen Proving Ground (ACC-APG) has awarded the Common Hardware Systems-4 (CHS-4) contract, which will keep the Army in front of procurement requirements for essential hardware and information technology services of the future. The $3.7 billion, five-year indefinite delivery, indefinite quantity contract was awarded to General Dynamics C4 Systems (GDC4S). The contract is for procurement of tactical information technology hardware and services using two types of contracts, firm fixed price and cost plus fixed fee, for services on non-commercial items. The hardware will be procured in four different versions: version one non- ruggedized, version one [ 8 ] COTS Journal October 2011
plus some ruggedization, version two fully ruggedized and version three near military specifications ruggedized with a comprehensive five-year warranty program. The hardware items procured will include handheld devices, notebooks, servers, network devices, peripherals, cables, operational transit cases and other items. General Dynamics C4 Systems Scottsdale, AZ. (480) 441-3033. [www.gdc4s.com].
ASC Signal Tapped by L-3 to Support BAMS UAV Program ASC Signal has been awarded a $3.8 million sub-contract by L-3 Communications Systems-West to build a dual-band antenna system to support global data collection
and dissemination worldwide for the U.S. Navy MQ-4C Broad Area Maritime Surveillance Unmanned Aircraft System (BAMS UAS) program (Figure 2). The advanced antenna terminals will be designed to meet the stringent ARSTRAT (Army Forces Strategic Command) standards required to operate with the U.S. Department of Defense’s Wideband Global Satcom (WGS) constellation; a high-capacity satellite system deployed across the Pacific, Indian and Atlantic Ocean regions that supports BAMS and other military platforms. ASC Signal will provide L-3 Communications Systems-West with precision-tracking antenna systems that communicate with the WGS satellites in both the X- and Ka-band frequencies, enabling full operational capability by the BAMS UAS over large maritime distances for long periods of time. The antenna system, which employs ASC’s
Artist’s rendering of an MQ-4C Broad Area Maritime Surveillance UAV in flight above the clouds. advanced Sub-Reflector Tracking (SRT) to permit 6-axis tracking of satellites, is part of a contract Northrop Grumman awarded to L-3 Communications to develop the communications equipment required for the BAMS UAS program. ASC Signal Plano, TX. (214) 291-7654. [www.ascsignal.com].
Mercury Selected for AESA Radar Upgrade Program
U.S. Navy Chooses Intellicheck Mobilisa for Aegeus Buoy Program
Mercury Computer Systems has received a multi-year contract from a leading prime contractor to deliver extremely powerful signal processing modules that will be used to field-upgrade advanced active electronically scanned array (AESA) radar systems. These systems are used on board military aircraft (Figure 3) to broadcast strong radar signals while remaining undetected. The technology Mercury is providing for the AESA system includes signal processing modules that are fully software compatible, meaning that
Intellicheck Mobilisa announced that the U.S. Navy has renewed its contract for funding for the company’s wireless security “Aegeus” buoy program. The contract provides the company approximately $3 million over a 12- to 18-month period for the buoy system. With research and development funding for the program from the U.S. Navy since 2005, Intellicheck Mobilisa currently has seven buoys deployed in Puget Sound and one in the Potomac River. The buoy is a multipurpose system outfitted with environmental and security applications for our nation’s ports. It uses Intellicheck Mobilisa’s exclusive technology and serves as an antiterrorism asset for the Department of Homeland Security (DHS) through the detection of radiological dispersal devices (“dirty bombs”); a deployable asset for providing fleet support in ports; and an environmental asset through the testing for oil spills, pH, salinity levels and dissolved oxygen.
AESA radar systems are used on board military aircraft like the F/A-18F Super Hornet to broadcast strong radar signals while remaining undetected. upgrades can be made easily and quickly in the field. As Mercury continues to support legacy, deployed solutions with significant technology upgrades, it remains the only company to support this caliber of fully compatible, board-swap upgrades. U.S.based manufacturers of the AESA radars include Northrop Grumman and Raytheon. Mercury Computer Systems Chelmsford, MA. (866) 627-6951. [www.mc.com].
Intellicheck Mobilisa Port Townsend, WA. (360) 344-3233. [www.icmobil.com].
Curtiss Wright to Provide Systems for High Resolution Surveillance Radar Curtiss-Wright Controls announced that it has been awarded a contract by Advanced Radar Technologies (ART) to provide the radar receiver for the High Resolution Surveillance Radar program. The potential value of the contract is valued in excess of $1 million over the lifetime of the program. Production is expected to begin mid-
Event Calendar October 28
Real-Time & Embedded Computing Conference Toronto, ON, Canada www.rtecc.com November 7-10
The SCP-124 is based on the Freescale PowerPC 7447A and 7448 processors and runs at a clock speed of 1000/1200 MHz while executing an 2773 Dhrystone Millions of Instructions per Second. 2013. ART’s High Resolution Surveillance Radar is designed to address the large and ever growing asset protection market, including Civil and Homeland security and border protection. The system will provide early warning to any threats to government and historic landmark buildings. Curtiss-Wright’s radar receiver subsystem, which features a fully integrated packaged COTS chassis with the company’s small form factor, rugged 3U single board computers and mezzanine cards (SCP-124 (Figure 4), XF05D and ADC-MOD2),will perform the acquisition and processing of the radar signals. Curtiss-Wright’s Embedded Computing business is developing and manufacturing the radar receiver at its High Wycombe, UK facility. The products will be shipped to ART in Madrid, Spain.
MILCOM 2011 Baltimore, MD www.milcom.org November 17
MILESTONE, the Military Electronics Development Conference Los Angeles, CA www.milestone2011.com December 6
Real-Time & Embedded Computing Conference Albuquerque, NM www.rtecc.com December 8
Real-Time & Embedded Computing Conference Phoenix, AZ www.rtecc.com January 17
Real-Time & Embedded Computing Conference Santa Clara, CA www.rtecc.com
To list your event, email: firstname.lastname@example.org
Curtiss-Wright Controls Charlotte, NC. (704) 869-4600. [www.cwcontrols.com].
October 2011 COTS Journal [ 9 ]
FPGA Processing for Radar and SIGINT Systems
VME and VPX FPGA Processing Advances Target Radar and SIGINT Needs
[ 10 ] COTS Journal October 2011
A variety of VPX and VME solutions package FPGA processing and supporting technology into rugged products designed for radar, SIGINT and similar military applications. Jeff Child, Editor-in-Chief
o longer viewed as peripheral or coprocessing devices, faster FPGA-based DSP capabilities combined with an expanding array of IP cores and development tools for FPGAs are enabling new system architectures. No longer used merely as glue-logic, FPGAs are now complete systems on a chip. In fact, since many of them even have general-purpose CPU cores on them, the military is hungry to use FPGAs to fill processing roles. As the signal processing capabilities of FPGAs continue to climb, theyâ€™ve become key enablers for waveform-intensive applications like sonar, radar, SIGINT and SDR. Devices like the Xilinx Virtex-5 and -6 and the Altera Stratix IV and V are example FPGAs that have been redefined as complete processing engines in their own right. That means complete systems can now be integrated into one or more FPGAs. Using those FPGAs, board-level subsystems are able to quickly acquire and process massive amounts of data in real time. Board-level product developers are leveraging those FPGA advances to create powerful compute engines that perform signal processing computation on the FPGAs themselves. At the same time, FPGAs are enabling a new class of I/O board solution that let users customize their I/O as well as do I/O-specific processing functions.
The Flexibly of FPGAs System developers can now use FPGA chips and boards to build radar receiver systems with a higher instantaneous bandwidth thanks to the converters, and that can handle the corresponding increase in compute power required to process the received data streams. In contrast, the ASIC-based radar design approaches of the past could achieve the performance needed, but lacked the flexibility inherent in designs based on FPGA technology. An example program that relies heavily on FPGA processing is Northrop Grummanâ€™s Airborne Signals Intelligence Payload (ASIP) program. ASIP is a next-generation signals intelligence (SIGINT) sensor for the U.S. Air Force that delivers enhanced signals intelligence capabilities to the warfighter, detecting, identifying and locating October 2011 COTS Journal [ 11 ]
Maintenance technicians go over pre-flight inspections on their RQ-4 Global Hawk aircraft before a mission while deployed at an air base in Southwest Asia. radar, communication and other types of electronic signals. ASIP systems fly on Northrop Grumman’s RQ-4 Global Hawk (Figure 1) and Lockheed Martin’s U-2 reconnaissance aircraft. Over the last twelve months FPGA processing boards in the emerging OpenVPX architecture have represented the largest category of new FPGA solutions. In synch with that trend, Pentek offers a family of ruggedized boards for high-performance military and avionics applications utilizing the industry’s most advanced FPGA technology. Pentek’s 53xxx Cobalt board family incorporates Xilinx’s Virtex-6 FPGAs for onboard signal processing, delivering digital sampling rates to 1 GHz in a compact 3U VPX form factor. By combining processing, data conversion and preconfigured functions, the 53xxx family is suitable for such applications as UAV, CommINT (Communications Intelligence) transceivers, airborne communications recorders, airborne ra[ 12 ] COTS Journal October 2011
dar countermeasures, shipboard diversity transceivers and armored vehicle antiIED systems. All Cobalt VPX products are available with a choice of Xilinx Virtex-6 LXT or SXT FPGA devices to match the application. Other common features of Cobalt boards include PCI Express (Gen 2) interfaces up to 8 lanes wide, synchronous clocking locked to an external system reference, and an LVPECL synch bus for synchronizing multiple modules to increase channel count.
FPGA Processing Rides OpenVPX The latest version 6 of the Xilinx Virtex line is feeding the flame of FPGA processing demand. Riding that wave, Curtiss-Wright Controls Embedded Computing (CWCEC) offers the CHAMP-FX3, the first rugged, high-performance FPGA OpenVPX 6U VPX board that features dual Xilinx Virtex-6 FPGAs. Available in both conduction-cooled and air-cooled versions, the CHAMP-FX3 provides dense
FPGA resources combined with generalpurpose processing, I/O flexibility and support for multiprocessing applications. The CHAMP-FX3 combines the dense processing resources of two large Xilinx Virtex-6 FPGAs (SX475T or LX550T) with a powerful AltiVec-enabled dual-core Freescale Power Architecture MPC8640D processor on a rugged 6U OpenVPX-compatible (VITA 65) form factor module. The CHAMP-FX3 complements this processing capability with a rich assortment of rear-panel I/O and memories, including a Serial RapidIO (SRIO)-based switching fabric, 16 high-speed serial links per FPGA, and 20 pairs of LVDS links to the backplane that can be used to support high-speed parallel interfaces such as Camera Link.
FPGA Solution Targets IED Defeat Electronics to defeat IEDs are extremely important in today’s conflicts. IEDs represent the largest cause of ca-
sualties in current U.S. conflicts. GE Intelligent Platforms has announced the SPR870A (Figure 2) 3U VPX Wideband Digital Receiver/Exciter Module. It features Xilinx Virtex-6 FPGA technology to enable its deployment in wideband signal acquisition and conversion applications such as radar ECM (electronic counter measures), pulse intercept and analysis (ELINT) and RF (radio frequency) test applications. The type of highly demanding, sophisticated ECM applications for which the SPR870A is ideal include spoofing hostile radar—allowing the host to change its perceived characteristics, for example, to confuse enemy intelligence—or for jamming remote control IED (improvised explosive device) signals, enabling bombs to be defused more safely. Fully rugged and conduction-cooled, the SPR870A is capable of digitizing analog input signals from below 50 MHz to over 1.5 GHz, using a dual channel 10-bit ADC (analog to digital converter) and two 12-bit DACs (digital to analog converters), and (re) creating analog output waveforms over a similar frequency range. A newer entrant into the VPX realm, Acromag’s latest offering is the VPX-VLX series of 3U VPX FPGA boards that feature a configurable Xilinx Virtex-5 FPGA enhanced with multiple high-speed memory buffers and a high-throughput PCIe interface. Field I/O interfaces to the FPGA via the rear P2 connector and/or with optional front mez-
zanine plug-in I/O modules. Three models provide a choice of logic-optimized FPGAs to match the performance requirements. Cards can be ordered with a Xilinx VLX85T, VLX110T, or VLX155T FPGA featuring up to 155,000 logic cells and 128 DSP48E slices. Each model is available in a format designed for use in air-cooled or conduction-cooled systems suitable for -40° to 85°C operation. Xilinx-based FPGA processing isn’t the only game in town. The features and performance of Altera’s Stratix line of FPGAs have won it a solid following among military system developers. One example is BittWare’s S4-3U-VPX (S43X) is a commercial or rugged 3U VPX card based on the high-density, low-power Altera Stratix IV GX FPGA. The Stratix IV GX is designed specifically for serial I/O-based applications, creating a completely flexible, reconfigurable VPX board. BittWare’s ATLANTiS FrameWork and the FINe Host/ Control Bridge greatly simplify application development and integration of this powerful board. The board provides a configurable 25-port SerDes interface supporting a variety of protocols, including
Serial RapidIO, PCI Express and 10 GigE. The board also features 10/100/1000 Ethernet and up to 4 Gbytes of DDR3 SDRAM. Providing enhanced flexibility is the VITA 57-compliant FMC site, which supports 10 SerDes, 60 LVDS pairs and 6 clocks.
VME and VXS Retains Military Mindshare While OpenVPX has positioned itself well as the next generation military form factor for advanced computing, the reality is that the upgrades and tech insertions based on VME or VXS will dominate the activity in the next couple years—especially as defense budgets tighten. Board vendors continue to roll out new solutions marrying the latest FPGA technology to VME or VXS. Along those lines, Mercury Computer Systems’ two latest Echotek Series products both use three Xilinx Virtex-5 FPGA processors, two high-speed fiber transceivers, and two FPGA Mezzanine Card (FMC) sites for high-bandwidth I/O. As integrated
The SPR870A 3U VPX Wideband Digital Receiver/Exciter Module uses Xilinx Virtex-6 FPGA technology to enable tasks such as spoofing hostile radar or jamming remote control IED signals, enabling bombs to be defused more safely. October 2011 COTS Journal [ 13 ]
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VXS/VME is still going strong for upgrades and even new systems. The latest Echotek Series products both use three Xilinx Virtex-5 FPGA processors, two high-speed fiber transceivers, and two FPGA Mezzanine Card (FMC) sites for high-bandwidth I/O.
components, they extend the functional range of Mercury’s VXS and RACE++ Series systems with digitization and FPGA processing of sensor-based data streams. The Echotek Series DCM-V5-VXS digital receiver features the latest in A/D and D/A technology via converters mounted on the FMC sites, allowing for high-speed/high-resolution data conversion while still preserving the quality of the original signal. The module couples this data conversion capability with market-leading processing power delivered by a set of three Virtex-5 SX240T or LX330T FPGAs, which can be programmed by the end user for customer-specific application features. Moreover, these FPGA processors provide up to 3,156 DSP slices. Each Virtex-5 FPGA is accompanied by both DDR-II-SDRAM and QDR-II-SRAM chips and is connected by multiple highspeed data paths to the FMC sites, to the system backplane interface, and to two fiber transceivers. For today’s advanced FPGAs it’s not just about the on-chip signal processing. Getting data off and on the FPGAs is just as important. With all that in mind, TEK Microsystems offers a platform based on its next-generation QuiXilica-V6 architecture,
bringing Xilinx’s Virtex-6 FPGA technology to VME and VXS-based applications. The QuiXilica-V6 VME/VXS baseboard combines three Xilinx Virtex-6 FPGAs with two QuiXmodule sites, supporting the industry’s widest range of Analog-toDigital Converter (ADC) and Digital-toAnalog Converter (DAC) resolutions and bandwidths using a common hardware architecture. Like previous generations of QuiXilica products based on Virtex II Pro and Virtex 5 technology, the QuiXilica-V6 VME/VXS is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS-based systems in both laboratory and deployed / rugged applications. Acromag Wixom, MI. (248) 295-0310. [www.acromag.com]. BittWare Concord, NH. (603) 226-0404. [www.bittware.com]. Curtiss-Wright Controls Embedded Computing Ashland, VA. (703) 779-7800. [www.cwcembedded.com]. GE Intelligent Platforms Charlottesville, VA. (800) 368-2738. [www.ge-ip.com]. Mercury Computer Systems Chelmsford, MA. (978) 967-1401. [www.mc.com]. Pentek Upper Saddle River, NJ. (201) 818-5900. [www.pentek.com]. TEK Microsystems Chelmsford, MA. (978) 244-9200. [www.tekmicro.com].
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FPGA Processing for Radar and SIGINT Systems
FPGAs Pave New Processing Paths for VPX and VME Systems Military applications like radar and military communications have an almost endless appetite for complex signal processing. The latest generation of FPGA offerings married with VME and VPX is feeding those needs.
Rodger Hosking, Vice President Pentek
very new FPGA generation delivers more DSP horsepower, higher resource densities, more memory and faster interfaces. Because FPGAs are so well suited to embedded computing boards, these benefits translate directly into higher performance for VME and VPX software radio systems. Specifically, additional DSP48E1 engines, faster DDR3 SDRAM memory interfaces, higher-speed gigabit serial links for Aurora and PCIe, and improved look-up table architectures, all support faster benchmarks and system throughput for FFTs, pattern recognition, target identification and tracking, decoding and decryption, signal analysis and classification, and low-latency countermeasure processing tasks. The latest board level products for real-time embedded systems have directly benefitted from these new features through new system architectures and interconnection strategies. FPGA resources in the latest Xilinx Series-7 family target various aspects of compute-intensive signal processing for VPX and VME radar and communications applications.
New FPGA Generation Xilinx’s newest generation of FPGAs [ 16 ] COTS Journal October 2011
is the Series 7, based upon low-power 28nm process technology to implement DSP resources of up to 6.7 TMACs, I/O transfer rates of 3.1 Terabits/s, and over 2 million logic cells. Series 7 is split into three families, each addressing different performance/price market spaces: Artix-7, Kintex-7 and Virtex-7. With a two-fold increase in performance and resources over the previous Virtex-6 devices, the Virtex-7 family targets the highest performance applications often required by Mil/Aero embedded systems. The 28nm Series 7 process technology, coupled with some clever power management techniques, results in a 50 percent reduction in power for a given function. Figure 1 compares the maximum FPGA resources and relative power dissipation levels between the Virtex-6 and Virtex-7 devices. To better address signal processing tasks, the maximum number of DSP blocks has increased by a factor of 2.5. Military embedded systems benefit significantly from this combination of lower power and higher performance for each of the key resources, by opening up new product markets and extending the capabilities of existing applications.
Gigabit Serial Links Traditional parallel buses like VME have become serious bottlenecks because
of higher speed peripherals and processors and high-density packaging. Just as desktop PCs have migrated away from PCI and PCI-X toward PCIe (PCI Express), new embedded system architectures like VPX abandon parallel backplane buses in favor of switched serial fabrics and gigabit serial links. The two main advantages are higher speed interconnects and multiple simultaneous paths between software radio system boards and components. More than any other device, FPGAs are the enabling technology for the migration from VME to VPX. Protocol engines for specific standards can be configured using FPGA logic for different protocols as required. They correctly process protocol-specific packets, header information, control functions, error detection and correction and payload data format. The strategy makes FPGA-based modules truly “fabric agnostic” and allows one hardware design to be deployed in several different fabric environments. This flexibility in using one hardware product to cover several different protocols in VPX systems encourages board vendors to develop FPGA-based products for the general market. It also affords system integrators the luxury of not having to commit to any particular standard when selecting boards for their systems.
6.4 GB/ sec
75% 70% 4.0 GB/ sec
Maximum DSP48E1 Blocks
Maximum Gigabit Serial Rate
Maximum Logic Cells
Maximum Block RAM
Maximum PCIe Data Rate
Maximum Configurable Logic Blocks
Relative I/O Power
Relative Dynamic Power
Relative Maximum Static Power
Compared here are the key resources and power consumption of the Virtex-6 and Virtex-7 devices.
By using JTRS handheld radios, soldiers can make use of wideband waveforms to move voice information further and more efficiently than legacy waveforms across the battlefield through ad-hoc mobile networking. In their latest Virtex-7 devices, Xilinx offers gigabit serial transceivers with four different bit rates: 6.6 GHz (GTP), 12.5 GHz (GTH), 13.1 GHz (GTX) and 28 GHz (GTZ). Xilinx FPGAs advance gigabit serial technology even further by includ[ 18 ] COTS Journal October 2011
ing integrated PCI interface blocks for PCI Express that incorporate key layers of the PCI Express protocol stack. This saves FPGA resources for other tasks and offers a standardized solution for sending and receiving data using one of the most popular system protocols. Some Virtex-7 devices now support the PCI Express Base Specification 3.0 with capabilities for both endpoint and root port. Since each generation also accommodates lower generation devices, the Gen3 interface, which operates at 8 Gbits/s, is backward compatible with Gen1 at 2.5 Gbits/s and Gen2 at 5 Gbits/s. The integrated PCIe interface blocks can be configured for 1, 2, 4 or 8 lanes and advanced buffering schemes raise the size to 1024 bytes for maximum sustained throughput rates.
Radar and Wideband Military Comms Advanced radar systems and new wideband military communications standards like SRW require channel
bandwidths of 20 MHz and beyond (Figure 2). To handle these new signals, embedded software radio systems seek to digitize and process signals as close to the antenna as possible. Because these wideband signals implement complex modulation schemes, the parallel processing horsepower of FPGAs is well matched to real-time tasks like encryption and decryption, beamforming and decoding. However, these higher signal bandwidths require faster data converters. Monolithic A/D converters suitable for embedded systems have steadily boosted maximum sampling rates. As an example, the National Semiconductor ADC12D1800 3.6 GHz 12-bit A/D converter can now digitize signal bandwidths of 1500 MHz. The digital interface splits the data path into four 12-bit demultiplexed outputs, each operating at 900 MHz. Of course, the problem now becomes how to connect these devices to the necessary signal processing elements. At these high rates, interconnecting traces require controlled impedances, matched
3U OpenVPX SOFTWARE RADIO MODULE
Virtex-7 FPGA 12-bit LVDS 900 MHz DDR
3.6 GHz 12-bit A/D Converter
National Semiconductor ADC12D1800
12-bit LVDS 900 MHz DDR 12-bit LVDS 900 MHz DDR
DDR3 Controller DDR3 Controller DDR3 Controller DDR3 Controller
32 bits 800 MHz 32 bits 800 MHz 32 bits 800 MHz 32 bits 800 MHz
DDR3 SDRAM 1 GB DDR3 SDRAM 1 GB DDR3 SDRAM 1 GB DDR3 SDRAM 1 GB
12-bit LVDS 900 MHz DDR x8 PCIe Gen 3.0 Interface
x8 PCIe Gen 3.0 6.4 Gbytes/s
V P X
Virtex-7 provides direct interfacing to a 3.6 GHz 12-bit A/D converter through four demultiplexed DDR ports operating at 900 MHz each. Four Gbytes of DDR3 SDRAM can capture, buffer and delay A/D data at the full sample rate. The x8 PCIe Gen 3.0 system interface delivers data at 6.4 Gbytes/s.
10/6/11 9:46:16 AM ] October 2011 COTS Journal [ 19
lengths and proper termination. The latest Virtex-7 FPGAs provide a direct connection to these types of highspeed peripheral devices with I/O transfer rates reaching 1866 MHz. They include per-bit skew adjustments to help align bits in a data word, easing the onerous printed circuit board layout constraints of trace length matching. Digitally controlled termination networks eliminate the need for external discrete resistors and aid in tuning the links for optimum performance. Figure 3 shows a 3U OpenVPX Virtex-7 software radio module using the 3.6 GHz A/D converter and taking full advantage of the high-speed I/O capabilities of the FPGA.
Memory Interfaces for VME, VPX Virtually all VME and VPX embedded systems require deep and fast memory for storage, processing and buffering data. The densest and most economical solution for large memory arrays is the SDRAM. In addition, DDR3 SDRAMs transfer data at both edges of the clock to deliver extremely fast read/write writes. At these speeds, interface timing for each memory must be carefully tuned for reliable operation. For this reason, DDR3 memory controllers must include highresolution programmable delay elements and training algorithms, so that optimum timing parameters can be calibrated each time the system is powered up.
The latest Virtex-7 devices can support DDR3 devices running bit transfer rates up to 1.866 Gbits/s. Special FPGA I/O pins allow a direct, glueless connection to these memories. To support these extreme speeds, Xilinx developed the Phasor clock generator in the Virtex-7, which allows a 1:4 ratio between the logic fabric clock and the memory clock, doubling the 1:2 ratio for the Virtex-6. Figure 3 shows direct connections from the FPGA to four 1 Gbyte banks of DDR3 SDRAM capable of capturing, buffering and delaying data samples from the 3.6 GHz A/D in real time with no data loss.
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[ 20cots1110_scv2.indd ] COTS Journal 1 October 2011
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Data Buffering Once high-speed peripherals have been successfully interfaced to the FPGA, the designer must now deal with managing the staggering flow of data to and from other system resources. While A/D and D/A converters operate at a constant clock rate, networks and VPX system buses transfer data in packets or blocks. Block RAM resources of FPGAs can be used as FIFOs to provide an elastic data buffer for some applications. In other cases, a swinging buffer memory is more appropriate, especially for blockoriented bus interfaces. A swinging buffer, also built from FPGA internal block RAM, allows one memory bank to be filled from one resource (like an A/D converter) while another bank is being emptied by another resource (like the PCIe interface). These schemes are extremely effective when the average data rate of peripheral is less than the average rate of the system interface. The largest Virtex-7 devices now offer more than 10 Mbytes of internal block RAM,
more than twice as much as the previous generation. However, transient capture applications like radar require a large amount of data to be captured at a very high rate in real time during a range gate, even though the duty cycle of the gate is relatively low. In this case, because FPGA block RAM is too small, external memory must be used, and the specialized SDRAM interfaces discussed above come into play. In these applications, duty cycle averaging allows the system interface to operate at a much lower speed with no data loss.
Riding the FPGA Wave For example, in a radar system, a 3.6 GHz A/D converter VPX module as shown in Figure 3 generates sample data at 4.8 Gbytes/s (assuming 1.5 bytes per sample). For a range gate of 100 msec duration, the capture buffer size must be 480 Mbytes, fitting nicely within any of the four 1 Gbyte SDRAMs. If the duty cycle is 20%, data in the buffer must be delivered to the system interface at an average rate
of only 960 Mbytes/s, a reasonable rate for most VPX backplane interconnects. Virtually every aspect of a VME or VPX module can benefit from this new FPGA technology. Faster gigabit serial links with internal PCIe engines, faster memory controllers, higher-speed peripheral and sensor interfaces, plus greatly enhanced DSP capabilities offer a tremendous performance boost to embedded system applications. This is especially critical for unmanned vehicles, where size, weight and power dominate as key factors. As FPGA vendors continue to compete for design wins by offering new features, better performance, higher density and lower power, VME and VPX designers must constantly track the industry to take best advantage of these powerful components.
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FPGA Processing for Radar and SIGINT Systems
VPX Cabling Solutions from Prototyping to Deployment The wealth of I/O options in VPX provides powerful flexibility but daunting complexity. By optimizing the cabling scheme, military systems can get the most of out of the architecture. Justin Moll, Director of Marketing, Elma Bustronic Jason Lippincott, Marketing Manager, Meritec
ith the design flexibility of VPX, there are many configurations available for all types of applications. For certain I/O requirements, achieving the intended design goals could be challenging. Using custom designed Rear Transition Modules (RTMs) for VPX is one solution. But for development and deployed systems, an RTM solution is not practical. It would be ideal to be able to directly connect one VPX slot to another and pull out I/O signals to connectors such as RJ45, 38999 circular connectors, SMA contacts and more. When the VPX VITA 46 specification was being drafted, the developers were looking for an architecture that provided a high-bandwidth solution in 3U and 6U height and offered plenty of I/O options. So, the specification was designed for a high degree of I/O flexibility. As VPX has morphed into the OpenVPX VITA 65 specification (largely due to too much flexibility in VITA 46), bringing out the I/O signals is as important as ever. Custom RTMs are always a possibility. Plus, there are “universal RTMs” in the market for VPX that have many of the common connector interfaces (Figure 1). A typical configuration has connectors installed to bring out J0, J2, J3 and J4 signals. [ 24 ] COTS Journal October 2011
This Universal VPX RTM Breakout Board can allow a test engineer to access I/O signals on custom built VPX boards.
Prototyping/Testing The board would not be intended for high-speed signals but would typically be used to bring out single-ended TTL signals that might be part of a customer’s custom I/O board. Boards like the universal RTM can be helpful tools in VPX design. However, it would be ideal to also directly connect slots via cabling. Plus, RTM solutions are not always practical for all applications, so alternatives would be useful. Responding to market demand, a VPX cabling system was created to give engineers more options in design solu-
tions and prototyping/testing. This system was designed and based on input and suggestions from several engineers in the embedded industry from different fields. The goal was to gather the input from the industry and provide a durable, flexible, cost-effective cabling solution. The direct cabling solution enables the testing of VPX systems. There are test backplanes that have signals routed from the P1 section of the backplane to SMA and SATA connectors (Figure 2). With direct VPX cabling, engineers can now directly plug into the backplane, for example, with a SMA connector off the
cables into a TDR or other test device. This makes for a simpler and more efficient test setup. Using VPX cabling, the engineer can use a wide range of terminations. All of the termination options have the ability to transform into single, double, triple, or quad stacked assemblies, while supporting multiple protocols, such as InfiniBand, Serial Rapid I/O, Ethernet and PCIe.
For Todayâ€™s Applications
The test backplane (a) has SMA and SATA connectors for connecting to external test devices. Using VPX cables, the simpler test backplane (b) could be created.
This close-up of VPX wafers shows they can start and end with either an odd row or even row signal.
[ 26 ] COTS Journal October 2011
VPX has been ideal for the Mil/Aero market with its high-performance, 3U and 6U size options, I/O flexibility, expanding ecosystem, rugged design and more. Using VPX cabling systems would benefit many of the Mil/Aero applications. This includes ATR applications bringing certain I/O signals to the front of the enclosure. Rather than customizing an I/O module, the cables can handle the routing simply and securely. This could be true in any UAV, cargo or fighter aircraft, as well as in sea and land-based applications. There may also be a need to connect signals across the backplane from one slot to another. Ground-based communications systems for signal relays and processing are also using VPX. These are often in a rackmount application, where cabling could be used to bring out I/O signals or could connect multiple chassis in the rack. Despite the application, the cabling systems will be very helpful in prototyping/testing the systems. This will allow the designer to experiment with different configuration options during prototyping. The cables can also help the engineer do various tests for a working prototype while waiting for some pluggable modules to be available. In VPX systems, there are various types of signal clusters, such as ultra thin pipes (one link: 1 Tx pair + 1 Rx pair), thin pipes (2 links), and fat pipes (4 links). VPX cabling wafers can be snapped together to create the signal channel that is required (Figure 3). One VPX wafer comprises of 4 coax wire lines, so both differential pairs are terminated. Each wafer therefore consists of an ultra thin pipe. To create a thin pipe, the engineer can simply snap together two wafers. For
a fat pipe, snap together four wafers. The wafer modules plug directly into backplane slots and can be securely latched with optional locking bars. For rugged deployed applications, ensuring that the cabling solution can withstand shock and vibration is critical. Therefore, locking bars are supported in a metal shell, which outlines the Multi-gig connector. The shell is mounted down with screws using the same type of implementation that has been used in other Mil/Aero designs for decades. Figure 4
Rear Cabling Options The cabling system can be used on the front or rear of the backplane. However, supporting the weight of the cables from the rear RTM connectors can be challenging. But, it is possible to use the larger diameter holes from the front guide pins. This would allow large enough screws to support the weight. Locking rails can be attached at the four mounting points on each shroud to secure the cable assemblies and provide a smooth surface with
This figure shows multiple connector options/types with wafers plugged into the backplane. slots for tie-wraps. The tie-wraps also provide strain relief. VPX cabling can also be used to make connections to a SerDes Test Device easy. The device is a simple “health monitor” allowing fast and efficient BER testing for VPX backplanes, boards, or the full interconnect path. The wait queues for a full
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room of test equipment (let alone a specialized SI engineer) can be staggering. With a simple-to-use device, BER testing and pattern generation can be done with a laptop, downloadable software, and a small space for the SerDes Test Unit and hardware. With a wafer-to-SMA cable connection, the testing of a VPX back-
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8/29/11 1:20:31 PM ] October 2011 COTS Journal [ 27
plane or board is quick and direct, without the use of probes.
VPX Cabling in Test Applications Open VPX backplane requirements are laid out in the VITA 46 and VITA 65 standard. With the accelerated design to market cycles always challenging deadlines, efficiency in testing of the product is crucial. With the versatility of a cabling solution, it allows the engineers to emulate
the system without the time and expense of a large PCB solution. Typical applications are to test cross talk between rows, measure signal integrity from slot to slot, and allow easy access to check skew and Tx quality. Some examples of second end terminations that have been instrumental in testing applications include SMA, CX4, DVI, ESATA, USB and VGA connectors along with a variety of other options. Figure 4 shows multiple connector options/
types with wafers plugged into the backplane. With the point to point architecture flexibility that VPX cabling allows, the possibilities for moving single or multiple signals has opened up many benefits for the designers. With the need for rapid development it is not always possible to finalize the required selection until further information is known. VPX cabling provides the ability to utilize cabling solutions and to keep the costs low in terms of time and custom board designs. Engineers can use the cabling to adapt a standard backplane for rapid deployment, also providing the option of transmitting I/O through external connectors.
A Variety of Options Using several available cable wire types, engineers have the option of taking double-ended wafer assemblies, cutting to length and terminating to a large variety of off-the-shelf connectors. There is also a variety of existing configurations with popular connectors terminated to the second end available. This provides a quick and flexible method of meeting their specific requirements for their application. This is a cost-effective and time saving alternative to re-spinning the backplane. VPX cabling enables system designers to disregard the normal developmental time frames and use a highly flexible option in prototyping and deployment. They also make reliable testing of VPX systems simpler with a direct plugging mechanism from SerDes test devices, TDRs, oscilloscopes and other test equipment. Elma Electronic Systems Fremont, CA. (510) 656-3400. [www.elma.com]. Meritec Painesville, OH. (440) 354-3148. [www.meritec.com].
[ 28Untitled-4 ] COTS1Journal October 2011
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FPGA Processing for Radar and SIGINT Systems
Roadmap Approach Eases Technology Readiness Challenges Technology readiness has moved up into very high levels of priority for todayâ€™s military. By using off-the-shelf technology, system developers can manage technology and obsolescence risks.
Mike Macpherson, Director, Business Development Curtiss-Wright Controls Embedded Computing
Technology Readiness Assessment (TRA) is a systematic, metrics-based process that assesses the maturity of, and the risk associated with, critical technologies to be used in U.S. Department of Defense funded Major Defense Acquisition Programs. The Assessment results in a Technical Readiness Level (TRL), with TRL 1 being the least mature, and TRL 9 designating the most mature. The success of an acquisition program depends on its ability to balance the right amount of technical maturity with the minimum threat of product obsolescence. The use of immature technology adds technical risk to a program that can significantly raise its development time and cost. On the other hand, incorporation of overly mature technology will add obsolescence risk to the program, potentially increasing the programâ€™s life cycle costs. Traditionally, vendors focused on delivering the latest and greatest technology as quickly as possible to military programs. With shifting missions and budget re-organization, the DoD is now more attracted to demonstrable mature technology solutions, and less interested in pushing the leading edge (Figure 1). There is less money available
[ 30 ] COTS Journal October 2011
With shifting missions and budget re-organization, the DoD is more interested in demonstrable mature technology solutions and less keen on pushing the leading edge.
Vehicle Electronic Module Roadmap Example 2008
Processor Module 2.26 GHz Core2 Duo, 45nm SP9300 / GS45 Chipset 4GB DDR3 RAM, 4GB Flash VPX Form Factor
1.5 GHz Core2 Duo, 65nm L7400 / E7520 Chipset 1GB DDR2 RAM, 1GB Flash cPCI Form Factor TRL Status
TRL > 8
Intel. SandyBridge CPU Quad Core, 32nm 8/16GB DDR3 RAM, 16/32GB Flash VPX Form Factor
TRL > 6
TRL < 6
Next Intel Processor & Chipset Quad Core, 22nm 8/16GB DDR3 RAM, 16/32GB Flash VPX Form Factor
Technology Readiness Levels are shown across a roadmap of COTS products using the example of Curtiss-Wright’s vehicle processor family of boards. Transitioning Between Technology Readiness Levels TRL 6
• A product is TRL 6 when publically announced as available to customers. However, it could go higher if a pre-release module is delivered and tested by the customer in a test bed. Then it would get a TRL 7.
• A product is rated as TRL 7 when the first item is installed and tested on a customer’s system and/or test bed in the intended operational environment.
• A product is TRL 8 when the system is qualified for use on the military platform (Development Test of the Platform)
Described here are TRL levels of COTS products from announcement to deployment.
for ground-up R&D projects. Today, the challenge for system integrators and vendors is to deliver a proven technology. The good news is that COTS vendors have a unique advantage that directly addresses these evolving requirements. COTS vendors can provide a product roadmap that offers the mature solution today with a path to the next-generation technology when it becomes the next mature technology.
Determining TRL Levels During the TRA process it’s typical for vendors to state the TRL level of the technology that they propose for use in a system. For open standard, off-the-shelf COTS modules this can be a difficult thing to determine. Measuring TRL in a classic TRA scenario involves assessing technology that has been purpose-built for [ 32 ] COTS Journal October 2011
that particular application. This unique technology will have progressed from the conceptual stage, driven by a specific requirement, after which the technology was matured through a development cycle to meet that specific requirement. It’s a completely different scenario when COTS technology is being used. COTS technology is typically driven by a market need rather than a specific program or application need. What’s more, the resulting technology is usually designed to address the complete spectrum of potential uses for that technology. For a vendor such as CurtissWright, the spectrum of potential uses targeted for a new COTS product such as a new single board computer, rugged switch or graphics card would include aerospace, ground systems, and rugged naval systems, all of which might be ad-
dressed by the same product. Mapping COTS products to the proper TRL level for TRA purposes results in the intersection of classic technology readiness assessment and the realities of COTS product development. Once deployed, the COTS product earns a fairly high TRL since that particular technology has been demonstrated in the same or a similar operational environment to the new application for which it is being considered.
Roadmap Approach To make the process of mapping COTS technologies to TRL levels as accurate and useful as possible, CurtissWright has developed a new model, based on COTS product roadmaps, that is called the Technology Readiness Roadmap (TRR). This new approach solves the problem of defining the TRL for a COTS technology that was not developed specifically for a particular application, but for the market in general. Figure 1 shows an example roadmap showing Curtiss-Wright’s vehicle processor family of boards. Another advantage of the TRR is that it helps the system integrator select the proper COTS technology to optimize the balance between technology readiness and obsolescence mitigation. Although the TRL approach encourages system designers to prefer high TRL products, the highest rated TRL product is not always the best choice. That’s because the higher the TRL level the older and closer to obsolescence the underlying components will be, adding to the obsolescence risk. The good news is that a COTS TRR can help system designers mitigate the risk of obsolescence while delivering a high TRL solution. A key benefit of roadmap-based COTS technology is that it transitions with each advance in a key component’s evolution and adopts the next generation of that technology. That transition path is reflected in a vendor’s product roadmaps. Each time an improved version of a key component is released, such as a new Intel CPU chip, an embedded military customer is likely to see that new technology on a next-generation
COTS module within 3 to 6 months of it becoming available.
Field Proven Solutions Older technology, rated from TRL 7 to TRL 9, can be attractive because it’s been proven in the field. The downside is that this very mature technology is older and getting closer to its end-of-life in an obsolescence sense. In contrast, newer technology, for example TRL 6, uses the newer generation of components but hasn’t been in the field very long, resulting in its lower TRL rating. Future generations of technology will always be in development, and so will rate an even lower TRL. It’s helpful to treat COTS product families TRL levels as maturing through a continuum. Predecessor products, with a higher TRL level, are based on older technology; current generation products with a medium TRL level feature current technology; and lastly, successor products under development have a low TRL because they are next-generation technology.
through their development programs, a particular product’s TRL will increase accordingly. Typically, COTS programs mature from Product Release (TRL 6) to Qualified System (TRL 8) within 2-4 years. Once an individual item makes it through this cycle for any program, we can claim the TRL level for the product in general.
A C R O M A G
Curtiss-Wright Controls Embedded Computing Ashburn, VA. (613) 254-5112. [www.cwembedded.com].
E M B E D D E D
I / O
S O L U T I O N S
FPGAs Your Way.
Mitigating Risks COTS modules and systems are better able to balance and properly mitigate technology risk and obsolescence risk by providing the latest technology with proven COTS standard modules, based on industry standards and an open system architecture. Unlike custom technologies, COTS products are designed to a technology roadmap that tracks the technology improvements of processors and components, while maintaining a consistent form factor, software and pin outs (when possible). Upgraded modules from the same product roadmap can be easily installed in the systems without demanding major changes for system integrators. Furthermore, Lifecycle Services provide further protection against the cost of obsolescence through obsolescence management programs that can guarantee product availability needed to support Department of Defense lifecycle requirements. Table 1 lists the TRL levels for COTS modules: COTS products mature as they are designed into multiple programs. As those programs evolve
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FPGA Processing for Radar and SIGINT Systems
FPGAs Inject New Levels of Flexibility into Military SBCs With the ability to embed virtually any type of computing functionality, FPGAs are changing the scope of what a military SBC can do.
Susan Wooley, President Micro/sys
mplementing FPGAs on embeddable SBCs provides military OEM system integrators a completely new set of tools for customizing their embedded applications into small, harsh, rugged environments. As CPU designs and FPGA technology have evolved, it has become increasingly more appropriate to combine these two technologies onto an SBC. The combination of these technologies enables SBC vendors to provide the military with infinitely more flexible SBCs capable of adaptation to a broad range of unique circumstances, environments, custom protocols and security requirements. Single chip solutions such as the Intel Atom with an Altera FPGA as well as more flexible dual chip integrations such as a Xilinx FPGA with a Freescale ARM processor are dramatically changing the way embedded system designers implement COTS applications in the future. Figure 1 shows an example of an SBC sporting a Xilinx Spartan 6 FPGA.
Limitless Possibilities In the 1990s the military implemented policies mandating the use of COTS technology whenever possible. For years this often required multiple daugh[ 34 ] COTS Journal October 2011
Single board solution featuring Xilinx Spartan 6 FPGA and Freescale Semiconductorâ€™s ARM Cortex-A8 processor. ter cards or companion I/O boards. By implementing FPGAs on SBCs though, the military is able to implement the right mix of I/O and protocols for their target application eliminating additional hardware. The user is empowered to re-define
the SBC to meet their needs. The power and flexibility of an onboard FPGA lies in the fact that it can be defined and then re-defined to meet the changing needs of the system or user. The days of being short a memory socket or
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64 TTL bi-directional signals
Registers UART Core
Spartan 6 Support FPGA
Addition of UART IP Core via FPGA firmware. Header
64 TTL bi-directional signals
MicroBlaze Processor iMX515
WEIM bus (IRQ Driven)
Spartan 6 Support FPGA Application
Xilinx Video IP Core
Addition of video processing via FPGA firmware. COM port in the final release are gone. Figure 2 shows a block diagram of a UART addition using an FPGA. Such flexibility is accomplished by programming into the FPGA off-the shelf IP cores or by writing [ 36 ] COTS Journal October 2011 Untitled-4 1
10/7/11 5:12:57 PM
custom FPGA firmware for the application. In addition, this re-programmability enables military applications to adjust to satisfy the evolving standardization requirements the DoD authorizes.
Ethernet 1 PHY (LAN8710)
Ethernet 2 MAC/PHY (LAN9221)
25 MHz Clock
FPGA SPI NOR FLASH (AT45DB321D)
U LT R A
RS232/485 Transceiver 0
50 MHz Clock
50 MHz Oscillator
RS232/485 Transceiver 1
25 MHz Clock
SATA Controller (GL830)
RS232/485 Transceiver 2
24 MHz Clock
Audio Codec (SGTL5000)
RS232/485 Transceiver 3
16 MHz Clock
USB Host 2 Transceiver (USB3315)
USB Host 1 Transceiver (USB3315)
Surface Mount Audio Transformers
CAN Controller (MCP2515)
Low Profile from
24 MHz Clock
24 MHz Clock
24 MHz Clock
iately immed c o m g lo a t Ca ics. See fulli c o e l e c t r o n p . w ww
USB Host 3 Transceiver (USB3315)
Transceiver mapping to the Xilinx Spartan 6 on the Micro/sys SBC1651.
IP Cores are purchased similar to software and configured by the user for installation into the FPGA. Off-the-shelf IP cores or “stacks” are available from a wide variety of sources: the FPGA manufacturers themselves or third-party vendors who have deep specialized know-how, often in narrow, niche technical fields. Some IP Cores are even available from technical communities such as ProfiNet and ModBus. Meanwhile there are “free” or almost free open source downloadable cores online. Problem is those may cost more in manpower than is saved by not buying a validated IP Core which often comes with technical support. For OEMs wanting to write a custom IP core for their own dedicated interfaces, proprietary algorithms or special-
M I N I AT U R E
ized processing, there is a large base of easy-to-use FPGA tools available. Typically designers implementing custom IP cores will write their firmware in Verilog or VHDL and using the tools provided by the FPGA manufacturer for their specific FPGA. However, a user may choose to use a third-party development tool chain that generates HDL code for a wide selection of FPGAs. The functionality that can be incorporated into an FPGA is limitless. Users needing to have onboard DSP or to add a video controller for dual video displays can do so. Complex signal processing, motion control and machine vision can also be implemented, all using the same off-the-shelf SBC. For example, Figure 3 illustrates how the Micro/sys solution
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October 2011 COTS Journal [ 37 ] Untitled-9 1
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integrates Xilinx’s Spartan 6 FPGA with Freescale Semiconductor’s i.MX515 ARM Cortex A8 processor to create a high-performance video processing application. The intelligent integration of the Xilinx FPGA and Freescale ARM processor enables users to design innovative embedded systems while significantly reducing time-to-market and R&D all while leveraging existing IP cores to accomplish their unique, complex tasks.
Ultimate Security In military applications, security is critical. As counterfeiting and IP theft is on the rise, concerns over what means are available to provide security for the IP inside FPGAs is also on the rise. The reprogrammable architecture of FPGAs acts as an inherent barrier to a straightforward tampering attempt to reverse engineer designs. There are, however, other means to violate the security of FPGAs, which
involve cloning the bitstream during configuration and/or JTAG and SEUs (single event upsets) manipulation. FPGA manufacturers, aware of these highly sophisticated technical vulnerabilities, provide additional security measures for users who are sensitive to threats at this level. Encrypted solutions can protect the “know-how” inside the FPGA, adding a higher level of safety than the off-the-shelf software security application program might. This reduces the likelihood IP can be examined, explored and adopted illegally by others. Some FPGAs can even be programmed to erase upon any detection of tampering to ensure that the enemy is unable to reverse engineer or extract any confidential IP.
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[ 38Untitled-4 ] COTS1Journal October 2011
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10/13/11 11:42:54 AM
Due to the low-volume nature of the defense market, cost savings are often harder to realize, but by utilizing FPGA technology on a COTS single board computer, the military is able to capitalize on several new significant bottom-line efficiencies. Whether it is components on a circuit board or daughter boards in a system, using an FPGA enables users to add functionality while reducing the BOM count and lower the manufacturing costs in terms of complexity as well as BOM costs. System I/O such as serial interfaces, Ethernet controllers, userdefined I/O, legacy protocols, or feature enhancements through the use of selected IP cores from third-party vendors can enhance or extend the life of an embedded system while reducing component count on BOMs. The possibilities are endless for reducing hardware revisions, daughter cards and “stuffing options” on the SMT line. By including provisions for these versions of an OEM system in the FPGA, build time options are simplified and costs are reduced.
Easing the Impact of Obsolescence Whether military or commercial, end-of-life concerns are present from day one. For users who have experienced the pain of a panic need to redesign a system because a video controller has gone obsolete or a required protocol is no longer
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supported by silicon, using SBCs with onboard FPGAs is a means to extend and stretch system lifetimes. The FPGA eases end-of-life issues in two ways. First, FPGAs reduce the number of times an “at risk” function needs to be implemented with a low-volume, high-risk chip. For example, a specialized SATA controller or DSP chip can be alternatively implemented with an IP core in a generic, high volume FPGA that is standard to many applications. Most FPGAs roadmaps extend further than specialized I/O chips, which face obsolescence faster due to manufacturing costs or technological advances. Secondly, an FPGA can offer a failsafe for unexpected end-of-life bumps. A FPGA can act as a very effective and efficient “Band-Aid” for a chip that is somewhat generic but has gone obsolete suddenly while remaining critical to a system’s performance. For example, if for software reasons or other system constraints, a product needs to maintain Ethernet performance at 10 Mbyte/s rather than 100
Mbytes/s, an IP core can be an excellent solution, but only if an FPGA is on board to act as a life saver. FPGAs can act as a tool into the future as well as into the past for easing the on-going issue of end-oflife challenges in the electronic industry.
Challenges amidst Rewards FPGAs are an ideal technology to be matched with SBCs that will lead to highly innovative applications. And while the opportunities are exciting, it must be tempered with a respect for the challenges that still exist. First, today’s FPGAs are not a solution for systems requiring analog hardware functions. Also, implementations to expand communication devices require the SBC vendor to plan ahead for the users and provide access to transceivers as illustrated in Figure 4, indicating the peripheral interconnects to the Xilinx Spartan 6 FPGA on the Micro/ sys SBC1651. Absent this, users will be responsible for adaptor boards or “garbage boards” to implement the transceivers, negating the advantages of reducing
BOM count and manufacturing complexity. SBC users need to be savvy when selecting an SBC vendor to determine if there is a “system” mentality to their approach in implementing FPGAs on SBCs. This includes inquiring as to what types of off-board signals are supplied and what interfaces are required to complete the transaction. Additionally, spending some time with your SBC vendor to learn what platforms they provide for developing FPGA code is important. This research and system planning should include discovering how and under what circumstances you will write or configure your IP core, how you will download it, and what interfaces are given access to by the SBC vendor. You will need to know about the interface between the FPGA and CPU to validate if your application will have the speed and signal strength necessary to service your IP core or application. Paying attention to the details at the system level will pay off as you begin to address implementation questions. There are great rewards for the military in the emergence of off-the-shelf single board computers with onboard FPGAs. There are potential OEM systems cost savings because of reduced BOM count and simplified production control issues. FPGAs make adhering to military protocols and standards easier to manage by enabling system upgrades over a long product life cycle without the need for a complete redesign. FPGAs can be implemented in ways to maximize the protection of your IP by embedding it in the FPGA code as well as providing potential options in case there are EOL issues in the future. These FPGA rewards will make the savvy system designer a hero over the lifetime of his product’s system. Micro/sys Montrose, CA. (818) 244-4600. [www.embeddedsys.com].
[ 40Untitled-5 ] COTS1Journal October 2011
9/7/11 8:22:13 AM
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