Accessed by Yancoal Australia Ltd on 21 Jul 2016 (Document currency not guaranteed when printed)
HB 301—2001
© Standards Australia
Design phase (refer to Section 1 for process) B rief
Fault-loop impedance schedule P la n ni n g
R e v i e w t h e p l a nn i ng
The values recorded in this schedule are necessary for the testing and verification phase
YE S
Has the plann in g chan ged?
NO
D e si g n
R e de s i g n
Is th e in s tallation th e s ame as the des ign ?
NO
YE S
Ins t a l l a t i o n
T e st i n g & V er i f i c a t i o n
For example Device designation
Device impedance limit
Cable impedance
Ω
Ω
&0
Cable impedance
Cable impedance
60 WR 03 60 WR '% Ω
Ω
Cable impedance
)6& Ω
Cable impedance
Total impedance
Result obtained in test
Ω
Ω
Ω
176
Cable designation/ Fault loop Section
8QLW $ &% W\SH & '% WR $ &%
8QLW $ &% W\SH & '% WR $ &%
Legend: CM = Consumers mains, SM ‘n’ = Submains ‘Section n’, FSC = Final subcircuit, MP = Metering point, DB = Distribution board.
2.4: Retail development
www.standards.com.au
60 WR '% 8QLW +: 60 WR '% 8QLW +: